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google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_blink/main.vhd | 1 | 5,682 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity blink_10m04 is
Port (
c1_1 : inout std_logic;
c1_2 : inout std_logic;
c1_3 : inout std_logic;
c1_5 : inout std_logic;
c1_6 : inout std_logic;
c1_7 : inout std_logic;
c1_9 : inout std_logic;
c1_10 : inout std_logic;
c1_11 : inout std_logic;
c1_12 : inout std_logic;
c1_13 : inout std_logic;
c1_14 : inout std_logic;
c1_16 : inout std_logic;
c1_17 : inout std_logic;
c1_18 : inout std_logic;
c1_19 : inout std_logic;
c1_20 : inout std_logic;
c1_22 : inout std_logic;
c1_23 : inout std_logic;
c1_24 : inout std_logic;
c1_25 : inout std_logic;
c1_26 : inout std_logic;
c1_27 : inout std_logic;
c1_28 : inout std_logic;
c1_29 : inout std_logic;
c1_30 : inout std_logic;
c1_31 : inout std_logic;
c1_33 : inout std_logic;
c1_34 : inout std_logic;
c1_36 : inout std_logic;
c1_37 : inout std_logic;
c1_38 : inout std_logic;
c2_1 : inout std_logic;
c2_3 : inout std_logic;
c2_4 : inout std_logic;
c2_5 : inout std_logic;
c2_8 : inout std_logic;
c2_12 : inout std_logic;
c3_1 : inout std_logic;
c3_2_CLK3n : inout std_logic;
c3_3 : inout std_logic;
c3_4 : inout std_logic;
c3_5_CLK3p : inout std_logic;
c3_6 : inout std_logic;
c3_7 : inout std_logic;
c3_8 : inout std_logic;
c3_9 : inout std_logic;
c3_10 : inout std_logic;
c3_11 : inout std_logic;
c3_12 : inout std_logic;
c4_3_VREFB2N0 : inout std_logic;
c4_4 : inout std_logic;
c4_6 : inout std_logic;
c4_7 : inout std_logic;
c4_8 : inout std_logic;
c4_10 : inout std_logic;
c4_11 : inout std_logic;
c4_12 : inout std_logic;
c4_13 : inout std_logic;
c4_14 : inout std_logic;
c4_15_DPCLK1 : inout std_logic;
c4_16_DPCLK0 : inout std_logic;
c4_17 : inout std_logic;
c4_18 : inout std_logic;
c4_19 : inout std_logic;
c4_20 : inout std_logic;
c4_21 : inout std_logic;
c4_22 : inout std_logic;
c4_23 : inout std_logic;
c4_24 : inout std_logic;
c4_25 : inout std_logic;
c4_26 : inout std_logic;
c4_27 : inout std_logic;
c4_28 : inout std_logic;
c4_30 : inout std_logic;
c4_31 : inout std_logic;
c4_32 : inout std_logic;
c4_33 : inout std_logic;
c4_34 : inout std_logic;
c4_35 : inout std_logic;
c4_36 : inout std_logic;
c4_37 : inout std_logic;
c4_38 : inout std_logic;
c4_39 : inout std_logic;
c4_40 : inout std_logic
);
end blink_10m04;
architecture rtl of blink_10m04 is
component internal_osc is
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component internal_osc;
signal clk : std_logic; -- 55-115MHz clock from internal oscillator
signal clk_div_count : std_logic_vector(26 downto 0) := (others => '0');
signal slow_clk : std_logic; -- clk/(128*1024*1024), 0.4-0.85 Hz
begin
osc0 : component internal_osc
port map (
oscena => '1',
clkout => clk
);
process (clk)
begin
if rising_edge(clk) then
clk_div_count <= std_logic_vector(unsigned(clk_div_count) + 1);
if unsigned(clk_div_count) = 0 then
slow_clk <= not slow_clk;
end if;
end if;
end process;
c1_1 <= slow_clk;
c1_2 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_3 <= slow_clk;
c1_5 <= slow_clk;
c1_6 <= slow_clk;
c1_7 <= slow_clk;
c1_9 <= slow_clk;
c1_10 <= slow_clk;
c1_11 <= slow_clk;
c1_12 <= slow_clk;
c1_13 <= slow_clk;
c1_14 <= slow_clk;
c1_16 <= slow_clk;
c1_17 <= slow_clk;
c1_18 <= slow_clk;
c1_19 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_20 <= slow_clk;
c1_22 <= slow_clk;
c1_23 <= slow_clk;
c1_24 <= slow_clk;
c1_25 <= slow_clk;
c1_26 <= slow_clk;
c1_27 <= slow_clk;
c1_28 <= slow_clk;
c1_29 <= slow_clk;
c1_30 <= slow_clk;
c1_31 <= slow_clk;
c1_33 <= slow_clk;
c1_34 <= slow_clk;
c1_36 <= slow_clk;
c1_37 <= slow_clk;
c1_38 <= slow_clk;
c2_1 <= slow_clk;
c2_3 <= slow_clk;
c2_4 <= slow_clk;
c2_5 <= slow_clk;
c2_8 <= slow_clk;
c2_12 <= slow_clk;
c3_1 <= slow_clk;
c3_2_CLK3n <= slow_clk;
c3_3 <= slow_clk;
c3_4 <= slow_clk;
c3_5_CLK3p <= slow_clk;
c3_6 <= slow_clk;
c3_7 <= slow_clk;
c3_8 <= slow_clk;
c3_9 <= slow_clk;
c3_10 <= slow_clk;
c3_11 <= slow_clk;
c3_12 <= slow_clk;
c4_3_VREFB2N0 <= slow_clk;
c4_4 <= slow_clk;
c4_6 <= slow_clk;
c4_7 <= slow_clk;
c4_8 <= slow_clk;
c4_10 <= slow_clk;
c4_11 <= slow_clk;
c4_12 <= slow_clk;
c4_13 <= slow_clk;
c4_14 <= slow_clk;
c4_15_DPCLK1 <= slow_clk;
c4_16_DPCLK0 <= slow_clk;
c4_17 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_18 <= slow_clk;
c4_19 <= slow_clk;
c4_20 <= slow_clk;
c4_21 <= slow_clk;
c4_22 <= slow_clk;
c4_23 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_24 <= slow_clk;
c4_25 <= slow_clk;
c4_26 <= slow_clk;
c4_27 <= slow_clk;
c4_28 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_30 <= slow_clk;
c4_31 <= slow_clk;
c4_32 <= slow_clk;
c4_33 <= slow_clk;
c4_34 <= slow_clk;
c4_35 <= slow_clk;
c4_36 <= slow_clk;
c4_37 <= slow_clk;
c4_38 <= slow_clk;
c4_39 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_40 <= slow_clk;
end rtl;
| apache-2.0 | 7d77856d961037dd101a861e15bb735a | 0.552974 | 2.593336 | false | false | false | false |
google/myelin-acorn-electron-hardware | expansion_minispartan_breakout/fpga-basic/minispartan_expansion.vhd | 1 | 7,962 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity minispartan_expansion is
Port (
-- miniSpartan LEDs
MS_LEDS : out std_logic_vector(7 downto 0);
-- miniSpartan serial port
MS_SERIAL_TX : out std_logic := '1';
MS_SERIAL_RTS : out std_logic := '1';
MS_SERIAL_RX : in std_logic;
MS_SERIAL_CTS : in std_logic;
-- miniSpartan SD card
MS_SD_MOSI : out std_logic := '1';
MS_SD_MISO : in std_logic;
MS_SD_SCK : out std_logic := '1';
MS_SD_SS : out std_logic := '0';
-- clock inputs from ULA
elk_16MHZ : in std_logic; -- buffered 16MHZ from ULA
elk_16MHZ_DIV13 : in std_logic; -- buffered 1.23 MHz from ULA
elk_PHI0 : in std_logic; -- buffered PHI0 from ULA
-- reset line from ULA
elk_nRST : in std_logic; -- buffered nRST from ULA
-- RDY: pulled up in the ULA
elk_RDY : in std_logic; -- buffered RDY from elk
nDEASSERT_RDY : out std_logic := '1'; -- drives RDY=0 if '0'
-- nNMI: pulled up on the Elk motherboard
elk_nNMI : in std_logic; -- buffered nNMI from elk
nASSERT_nNMI : out std_logic := '1'; -- drives nNMI=0 if '0'
-- nIRQ: pulled up on the Elk motherboard
elk_nIRQ : in std_logic; -- buffered nIRQ from elk
nASSERT_nIRQ : out std_logic := '1'; -- drives nIRQ=0 if '0'
-- RnW: driven by the 6502
elk_RnW : in std_logic; -- buffered RnW from elk
RnW_out : out std_logic := '1'; -- RnW that we can drive
RnW_nOE : out std_logic := '1'; -- fpga drives RnW if '0', high-Z if '1'
-- bidirectional data bus
elk_D : inout std_logic_vector(7 downto 0) := (others => 'Z');
DATA_nOE : out std_logic := '1'; -- '0' to enable data buffer
DATA_READ : out std_logic := '1'; -- elk->fpga if '1', fpga->elk if '0'
-- address bus: driven by the 6502
elk_A : in std_logic_vector(15 downto 0);
A_DIR : out std_logic := '1' -- elk->fpga if '1', fpga->elk if '0'
);
end minispartan_expansion;
architecture Behavioural of minispartan_expansion is
-- '1' when elk_A is in sideways space
signal SIDEWAYS : std_logic;
-- '1' when elk_A = FCFx
signal DEBUG : std_logic;
signal debug_reg : std_logic_vector(7 downto 0);
-- '1' when elk_A = FCB1 (Elk User Port for UPURS)
signal EUP_SERIAL : std_logic;
-- '1' when elk_A = FC71 (parallel port data reg)
signal EPP_DATA : std_logic;
-- '1' when elk_A = FC72 (parallel port status reg)
signal EPP_STATUS : std_logic;
-- currently selected memory bank, defaults to BASIC
signal bank : std_logic_vector(3 downto 0) := x"A";
-- '1' when we're selected
signal driving_bus : std_logic;
-- '1' when reading from the embedded ROM
signal reading_rom_zero : std_logic;
-- internal wiring for embedded ROM
signal rom_zero_D : std_logic_vector(7 downto 0);
-- '1' when reading from the embedded ROM
signal reading_rom_upurs : std_logic;
-- internal wiring for embedded ROM
signal rom_upurs_D : std_logic_vector(7 downto 0);
-- '1' when reading from the embedded ROM
signal reading_rom_mmfs : std_logic;
-- internal wiring for embedded ROM
signal rom_mmfs_D : std_logic_vector(7 downto 0);
begin
-- sideways address space
SIDEWAYS <= '1' when elk_A(15 downto 14) = "10" else '0';
-- debug register
DEBUG <= '1' when elk_A(15 downto 4) = x"FCF" else '0';
-- EUP serial and MMFS parallel
EUP_SERIAL <= '1' when elk_A = x"FCB1" else '0';
EPP_DATA <= '1' when elk_A = x"FC71" else '0';
EPP_STATUS <= '1' when elk_A = x"FC72" else '0';
-- '1' when reading from the embedded ROM
reading_rom_zero <= '1' when SIDEWAYS = '1' and bank = x"0" else '0';
reading_rom_upurs <= '1' when SIDEWAYS = '1' and bank = x"6" else '0';
reading_rom_mmfs <= '1' when SIDEWAYS = '1' and bank = x"7" else '0';
-- the actual embedded rom
rom_zero : entity work.RomZero
port map (
CLK => elk_PHI0,
A => elk_A(13 downto 0),
D => rom_zero_D,
CS => reading_rom_zero
);
rom_upurs : entity work.RomUPURS
port map (
CLK => elk_PHI0,
A => elk_A(13 downto 0),
D => rom_upurs_D,
CS => reading_rom_upurs
);
rom_mmfs : entity work.RomMMFS
port map (
CLK => elk_PHI0,
A => elk_A(13 downto 0),
D => rom_mmfs_D,
CS => reading_rom_mmfs
);
-- data bus access
driving_bus <=
-- never when cpu is writing
'0' when elk_RnW = '0' else
-- drive when reading embedded rom
'1' when reading_rom_zero = '1' or reading_rom_upurs = '1' or reading_rom_mmfs = '1' else
-- drive when reading registers
'1' when DEBUG = '1' or EUP_SERIAL = '1' or EPP_STATUS = '1' else
-- we're not selected
'0';
-- only drive buffers during high clock period and
-- either the cpu is writing, or we're selected and
-- the cpu is reading
DATA_nOE <= '0' when (
elk_PHI0 = '1' and (elk_RnW = '0' or driving_bus = '1')
) else '1';
-- data direction matches elk_RnW
DATA_READ <= '0' when elk_RnW = '1' else '1';
-- data bus
elk_D <=
-- failsafe: tristate when the buffers are pointing elk->fpga
"ZZZZZZZZ" when (elk_PHI0 = '0' or elk_RnW = '0' or driving_bus = '0') else
-- reading data from the embedded ROM
rom_zero_D when reading_rom_zero = '1' else
rom_upurs_D when reading_rom_upurs = '1' else
rom_mmfs_D when reading_rom_mmfs = '1' else
-- reading debug register
debug_reg when elk_A = x"FCF0" else
elk_A(3 downto 0) & elk_A(3 downto 0) when DEBUG = '1' else
-- reading SPI status
MS_SD_MISO & "0000000" when EPP_STATUS = '1' else
-- reading serial RX
MS_SERIAL_RX & "11111" & MS_SERIAL_CTS & "1" when EUP_SERIAL = '1' else
-- default: this should never happen
"10101010";
process (--elk_nRST,
elk_PHI0)
begin
-- TODO figure out why nRST is going low.
-- multimeter shows it at ~2.3V; is it shorted to PHI0? PORTA5
--if elk_nRST = '0' then
-- -- default to BASIC ROM
-- bank <= x"A";
-- MS_LEDS <= x"55";
--els
if falling_edge(elk_PHI0) then
-- set sideways bank
if (
elk_RnW = '0' and
elk_A(15 downto 8) & elk_A(3 downto 0) = x"FE5" and
elk_D(7 downto 4) = x"0"
) then
bank <= elk_D(3 downto 0);
end if;
-- set serial output
if elk_RnW = '0' and EUP_SERIAL = '1' then
MS_SERIAL_RTS <= elk_D(6);
MS_SERIAL_TX <= elk_D(0);
end if;
-- set SPI output
if elk_RnW = '0' and EPP_DATA = '1' then
MS_SD_MOSI <= elk_D(0);
MS_SD_SCK <= elk_D(1);
end if;
-- set leds on minispartan board by writing to FCFx
if elk_RnW = '0' and DEBUG = '1' then
MS_LEDS <= elk_D;
debug_reg <= elk_D;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 8f2eb117e4bf3404b2e6f7da002395d8 | 0.563175 | 3.320267 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_blk_mem_gen_0_0/sim/base_zynq_design_blk_mem_gen_0_0.vhd | 1 | 12,111 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY base_zynq_design_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END base_zynq_design_blk_mem_gen_0_0;
ARCHITECTURE base_zynq_design_blk_mem_gen_0_0_arch OF base_zynq_design_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.3746 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END base_zynq_design_blk_mem_gen_0_0_arch;
| gpl-3.0 | 42d8dc0be900e4c67b3fbffabc7af95f | 0.613409 | 3.205664 | false | false | false | false |
alvieboy/xtc-base | alu_b.vhd | 1 | 2,507 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity alu_B is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
op: in alu2_op_type;
co: out std_logic;
zero: out std_logic;
bo: out std_logic;
sign: out std_logic
);
end entity;
architecture behave of alu_B is
component shifter is
port (
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end component shifter;
signal r: unsigned(32 downto 0);
signal shift_a: unsigned(31 downto 0);
signal shift_b: unsigned(4 downto 0);
signal shift_o: unsigned(31 downto 0);
signal shift_left: std_logic;
signal shift_arith: std_logic;
signal ar: unsigned(32 downto 0);
begin
o<=r(31 downto 0);
shift_a <= a;
shift_b <= b(4 downto 0);
shft: shifter
port map (
a => shift_a,
b => shift_b,
o => shift_o,
left => shift_left,
arith => shift_arith
);
process(a, b, op, shift_o)
variable delta: unsigned(31 downto 0);
begin
shift_left <= 'X';
shift_arith <= 'X';
ar <= (others => 'X');
r <= (others =>'X');
case op is
when ALU2_ADD =>
r <= (a(31)&a) + (b(31)&b);
when ALU2_CMPI =>
ar <= (a(31)&a) - (b(31)&b);
r <= (others => 'X');
when ALU2_SRA =>
if ENABLE_SHIFTER then
r(31 downto 0) <= shift_o;
r(32) <= '0';
shift_left<='0';
shift_arith<='1';
end if;
when ALU2_SRL =>
if ENABLE_SHIFTER then
r(31 downto 0) <= shift_o;
r(32) <= '0';
shift_left<='0';
shift_arith<='0';
end if;
when ALU2_SHL =>
if ENABLE_SHIFTER then
r(31 downto 0) <= shift_o;
r(32) <= '0';
shift_left<='1';
end if;
when ALU2_SEXTB =>
r(7 downto 0) <= a(7 downto 0);
r(32 downto 8) <= (others => a(7));
when ALU2_SEXTS =>
r(15 downto 0) <= a(15 downto 0);
r(32 downto 16) <= (others => a(15));
when ALU2_NOT =>
r(31 downto 0) <= not a;
r(32) <= '0';
when others => null;
end case;
end process;
co <= ar(32);
sign <= ar(31);
bo <= ar(32);
zero <= '1' when ar(31 downto 0)=x"00000000" else '0';
end behave;
| bsd-3-clause | 34bfb964ed2a70b517d07ef429b9e192 | 0.516554 | 3.114286 | false | false | false | false |
EPiCS/reconos | pcores/reconos_v3_01_a/hdl/vhdl/reconos_pkg.vhd | 2 | 54,669 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: VHDL Package - ReconOS
--
-- project: ReconOS
-- author: Enno Lübbers, University of Paderborn
-- Andreas Agne, University of Paderborn
-- Christoph Rüthing, University of Paderborn
-- description: The entire ReconOS package with type definitions and
-- hardware OS services in VHDL
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
package reconos_pkg is
constant C_FIFO_WIDTH : integer := 32;
constant C_OSIF_WIDTH : integer := C_FIFO_WIDTH;
constant C_MEMIF_WIDTH : integer := C_FIFO_WIDTH;
-- any request will be split up in multiple requests of size C_CHUNK_SIZE (in words)
constant C_CHUNK_SIZE : integer := 64;
constant C_CHUNK_SIZE_BYTES : integer := C_CHUNK_SIZE * 4;
constant C_MEMIF_LENGTH_WIDTH : integer := 24;
constant C_MEMIF_CMD_WIDTH : integer := C_MEMIF_WIDTH - C_MEMIF_LENGTH_WIDTH;
-- common constants
constant C_RECONOS_FAILURE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000000";
constant C_RECONOS_SUCCESS : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000001";
-- commands
constant OSIF_CMD_THREAD_GET_INIT_DATA : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A0";
constant OSIF_CMD_THREAD_DELAY : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A1"; -- ToDo
constant OSIF_CMD_THREAD_EXIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A2";
constant OSIF_CMD_THREAD_YIELD : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A3"; -- ToDo
constant OSIF_CMD_THREAD_RESUME : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A4"; -- ToDo
constant OSIF_CMD_THREAD_LOAD_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A5"; -- ToDo
constant OSIF_CMD_THREAD_STORE_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A6"; -- ToDo
constant OSIF_CMD_SEM_POST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B0";
constant OSIF_CMD_SEM_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B1";
constant OSIF_CMD_MUTEX_LOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C0";
constant OSIF_CMD_MUTEX_UNLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C1";
constant OSIF_CMD_MUTEX_TRYLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C2"; -- Not tested, yet
constant OSIF_CMD_COND_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D0"; -- Not tested, yet
constant OSIF_CMD_COND_SIGNAL : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D1"; -- Not tested, yet
constant OSIF_CMD_COND_BROADCAST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D2"; -- Not tested, yet
constant OSIF_CMD_RQ_RECEIVE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E0"; -- ToDo
constant OSIF_CMD_RQ_SEND : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E1"; -- ToDo
constant OSIF_CMD_MBOX_GET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F0";
constant OSIF_CMD_MBOX_PUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F1";
constant OSIF_CMD_MBOX_TRYGET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F2"; -- ToDo
constant OSIF_CMD_MBOX_TRYPUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F3"; -- ToDo
constant OSIF_CMD_YIELD_MASK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"80000000";
constant MEMIF_CMD_READ : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"00";
constant MEMIF_CMD_WRITE : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"F0";
-- type definitions for easier handling of signals
type i_fifo_t is record
s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
s_fill : std_logic_vector(15 downto 0);
s_empty : std_logic;
m_rem : std_logic_vector(15 downto 0);
m_full : std_logic;
s_re : std_logic;
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
type o_fifo_t is record
s_re : std_logic;
m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
alias i_osif_t is i_fifo_t;
alias o_osif_t is o_fifo_t;
alias i_memif_t is i_fifo_t;
alias o_memif_t is o_fifo_t;
type i_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
type o_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
we : std_logic;
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
-- setup functions
-- ONLY FOR INTERNAL USE
-- Assigns signals to the FIFO record. This function must be called
-- asynchronously in the main entity including the OS-FSM.
--
-- i_fifo - i_fifo_t record
-- o_fifo - o_fifo_t record
-- s_data - data signal of slave FIFO
-- s_fill - fill signal of slave FIFO
-- s_empty - empty signal of slave FIFO
-- m_rem - remaining signal of master FIFO
-- m_full - full signal of master FIFO
-- s_re - read signal of slave FIFO
-- m_data - data signal of master FIFO
-- m_we - write signal of master FIFO
--
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
);
-- ONLY FOR INTERNAL USE
-- Resets the FIFO signals to a default state.
--
-- o_fifo - o_fifo_t
--
procedure fifo_reset (
signal o_fifo : out o_fifo_t
);
-- Assigns signals to the OSIF record. This function must be called
-- asynchronously in the main entity including the OS-FSM.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t_record
-- sw2hw_data - data signal of OSIF - OSIF_FIFO_Sw2Hw_Data
-- sw2hw_fill - fill signal of OSIF - OSIF_FIFO_Sw2Hw_Fill
-- sw2hw_empty - empty signal of OSIF - OSIF_FIFO_Sw2Hw_Empty
-- hw2sw_rem - remaining signal of OSIF - OSIF_FIFO_Hw2Sw_Rem
-- hw2sw_full - full signal of OSIF - OSIF_FIFO_Hw2Sw_Full
-- sw2hw_re - read signal of OSIF - OSIF_FIFO_Sw2Hw_RE
-- hw2sw_data - data signal of OSIF - OSIF_FIFO_Hw2Sw_Data
-- hw2sw_we - write signal of OSIF - OSIF_FIFO_Hw2Sw_WE
--
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
);
-- Resets the OSIF signals to a default state. This function should be called
-- on reset of the OS-FSM.
--
-- o_osif - o_osif_t record
--
procedure osif_reset (
signal o_osif : out o_osif_t
);
-- Assigns signals to the MEMIF record. This function must be called
-- asynchronously in the main entity including the OS-FSM.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- mem2hwt_data - data signal of MEMIF - MEMIF_FIFO_Mem2Hwt_Data
-- mem2hwt_fill - fill signal of MEMIF - MEMIF_FIFO_Mem2Hwt_Fill
-- mem2hwt_empty - empty signal of MEMIF - MEMIF_FIFO_Mem2Hwt_Empty
-- hwt2mem_rem - remaining signal of MEMIF - MEMIF_FIFO_Hwt2Mem_Rem
-- hwt2mem_full - full signal of MEMIF - MEMIF_FIFO_Hwt2Mem_Full
-- mem2hwt_re - read signal of MEMIF - MEMIF_FIFO_Mem2Hwt_RE
-- hwt2mem_data - data signal of MEMIF - MEMIF_FIFO_Hwt2Mem_Data
-- hwt2mem_we - write signal of MEMIF - MEMIF_FIFO_Hwt2Mem_WE
--
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
);
-- Resets the MEMIF signals to a default state. This function should be called
-- on reset of the OS-FSM.
--
-- o_memif - o_memif_t record
--
procedure memif_reset (
signal o_memif : out o_memif_t
);
-- Assigns signals to the MEMIF record. This function must be called
-- asynchronously in the main entity including the OS-FSM.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- addr - address signal of the local ram
-- we - write enable signal of the local ram
-- o_data - output data signal of the local ram
-- i_data - input data signal of the local ram
--
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
);
-- Resets the RAM signals to a default state. This function should be called
-- on reset of the OS-FSM.
--
-- o_ram - o_ram_t record
--
procedure ram_reset (
signal o_ram : out o_ram_t
);
-- fifo access functions
-- ONLY FOR INTERNAL USE
--
-- Resets FIFO signals to a default state (sets read and write flag to '0')
--
-- o_fifo - o_fifo_t record
--
procedure fifo_default (
signal o_fifo : out o_fifo_t
);
-- ONLY FOR INTERNAL USE
--
-- Reads a single word out of the FIFO and sets o_fifo.step to next_step.
-- Be aware, that you must set continue if you want to read multiple words
-- after another.
--
-- i_fifo - i_fifo_t record
-- o_fifo - o_fifo_t record
-- result - the word read from the FIFO
-- next_step - the new value of o_fifo.step after the word was read
-- continue - boolean value, indicating if the next clock cycle another
-- read will be performed
--
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
);
-- ONLY FOR INTERNAL USE
--
-- Writes a single word into the FIFO and sets o_fifo.step to next_step.
--
-- i_fifo - i_fifo_t record
-- o_fifo - o_fifo_t record
-- data - the word that should be written into the FIFO
-- next_step - the new value of o_fifo.step after the word was written
--
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
);
-- ONLY FOR INTERNAL USE
--
-- Reads multiple words from the FIFO into a local ram and sets o_fifo.step to
-- next_step. This function reads from i_ram.addr and increases this address
-- appropriately.
--
-- i_fifo - i_fifo_t record
-- o_fifo - o_fifo_t record
-- i_ram - i_ram record
-- o_ram - o_ram record
-- count - number of words to read
-- next_step - the new value of o_fifo.step after the word was written
--
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
-- ONLY FOR INTERNAL USE
--
-- Writes multiple words from a local ram into the FIFO and sets o_fifo.step to
-- next_step. This function reads from i_ram.addr and increases this address
-- appropriately.
--
-- i_fifo - i_fifo_t record
-- o_fifo - o_fifo_t record
-- i_ram - i_ram record
-- o_ram - o_ram record
-- count - number of words to read
-- next_step - the new value of o_fifo.step after the word was written
--
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
-- functions to access osif directly
-- Reads a single word from the OSIF.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- result - word read from the OSIF
-- done - indicates when read finished
--
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Writes a single word into the OSIF
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- data - word to write int the OSIF
-- done - indicates when write finished
--
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- generic osif functions
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with no arguments and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- result - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with one argument and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - argument of the system call
-- result - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with one arguments and to results.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - argument of the system call
-- result1 - first result of the system call
-- result2 - second result of the system call
-- done - indicates when system call finished
--
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- ONLY FOR INTERNAL USE
--
-- Issues a system call with two arguments and a single result.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- call_id - id of the system call
-- arg0 - first argument of the system call
-- arg1 - second argument of the system call
-- result - result of the system call
-- done - indicates when system call finished
--
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- osif functions
-- Yields the hardware thread slots. This causes the scheduler to be called
-- and might result in an preemtion of the hardware thread. This method alone
-- does not issue any call but only sets the yield bit for a regular system call.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
--
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
-- Posts the semaphore specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Waits for the semaphore specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Locks the mutex specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Unlocks the mutex specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Tries to lock the mutex specified by handle and returns if successful or not.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Waits for the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Signals a single thread waiting on the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Signals all threads waiting on the condition variable specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Puts a single word into the mbox specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word to write into the mbox
-- result - result of the osif call
-- done - indicates when call finished
--
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Reads a single word from the mbox specified by handle.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result - word read from the mbox
-- done - indicates when call finished
--
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Tries to put a single word into the mbox specified by handle but does not
-- blocks until the mbox gets populated.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- word - word to write into the mbox
-- result - indicates if word was written into the mbox
-- done - indicates when call finished
--
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Tries to read a single word from the mbox specified by handle but does not
-- blocks until the mbox gets free.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- handle - index representing the resource in the resource array
-- result1 - word read from the mbox
-- result2 - indicates if a word was read from the mbox
-- done - indicates when call finished
--
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- NOT IMPLEMENTED YET
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- NOT IMPLEMENTED YET
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Gets the pointer to the initialization data of the hardware thread
-- specified by reconos_hwt_setinitdata.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
-- result - the pointer to the initialization data
-- done - indicated when call finished
--
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Terminates the current hardware thread and the delegate in software.
--
-- i_osif - i_osif_t record
-- o_osif - o_osif_t record
--
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
-- memif functions
-- Flushes the MEMIF-FIFOs to guarantee that no more words are
-- waiting to be written into the memory. Be aware, that this function only
-- checks the words in the MEMIF-FIFOs but does not guarantee that even the last
-- word was written into the memory.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- done - indicates that the call finished
--
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
);
-- Writes a single word into the main memory.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- addr - address of the main memory to write
-- data - word to write into the main memory
-- done - indicates that the call finished
--
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
);
-- Reads a single word from the main memory.
--
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- addr - address of the main memory to read from
-- data - word read from the main memory
-- done - indicates that the call finished
--
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
);
-- Writes several words from the local ram into the main memory.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- src_addr - start address to read from the local ram
-- dst_addr - start address to write into the main memory
-- len - number of writes to transmit
-- done - indicates that the call finished
--
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
-- Writes several words from the local ram into the main memory.
--
-- i_ram - i_ram_t record
-- o_ram - o_ram_t record
-- i_memif - i_memif_t record
-- o_memif - o_memif_t record
-- src_addr - start address to read from the main memory
-- dst_addr - start address to write into the local ram
-- len - number of writes to transmit
-- done - indicates that the call finished
--
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
end package reconos_pkg;
package body reconos_pkg is
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
) is begin
i_fifo.step <= o_fifo.step;
i_fifo.s_data <= s_data;
i_fifo.s_fill <= s_fill;
i_fifo.s_empty <= s_empty;
i_fifo.m_rem <= m_rem;
i_fifo.m_full <= m_full;
s_re <= o_fifo.s_re;
m_data <= o_fifo.m_data;
m_we <= o_fifo.m_we;
i_fifo.s_re <= o_fifo.s_re;
i_fifo.m_we <= o_fifo.m_we;
i_fifo.void <= o_fifo.void;
end procedure fifo_setup;
procedure fifo_reset (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.step <= 0;
o_fifo.m_we <= '0';
o_fifo.s_re <= '0';
o_fifo.m_data <= (others => '0');
o_fifo.void <= '0';
end procedure fifo_reset;
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
) is begin
fifo_setup(i_osif, o_osif, sw2hw_data, sw2hw_fill, sw2hw_empty,
hw2sw_rem, hw2sw_full, sw2hw_re, hw2sw_data, hw2sw_we);
end procedure osif_setup;
procedure osif_reset (
signal o_osif : out o_osif_t
) is begin
fifo_reset(o_osif);
end procedure osif_reset;
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
) is begin
fifo_setup(i_memif, o_memif, mem2hwt_data, mem2hwt_fill, mem2hwt_empty,
hwt2mem_rem, hwt2mem_full, mem2hwt_re, hwt2mem_data, hwt2mem_we);
end procedure memif_setup;
procedure memif_reset (
signal o_memif : out o_memif_t
) is begin
fifo_reset(o_memif);
end procedure memif_reset;
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
) is begin
i_ram.data <= i_data;
addr <= o_ram.addr;
we <= o_ram.we;
o_data <= o_ram.data;
i_ram.addr <= o_ram.addr;
i_ram.count <= o_ram.count;
i_ram.step <= o_ram.step;
i_ram.remote_addr <= o_ram.remote_addr;
i_ram.remainder <= o_ram.remainder;
end procedure ram_setup;
procedure ram_reset (
signal o_ram : out o_ram_t
) is begin
o_ram.we <= '0';
o_ram.addr <= (others => '0');
o_ram.data <= (others => '0');
o_ram.count <= (others => '0');
o_ram.step <= 0;
o_ram.remote_addr <= (others => '0');
o_ram.remainder <= (others => '0');
end procedure ram_reset;
-- fifo access functions
procedure fifo_default (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.s_re <= '0';
o_fifo.m_we <= '0';
end procedure fifo_default;
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
) is begin
-- set re, if FIFO is empty this is no problem
--if i_fifo.s_empty = '0' then
o_fifo.s_re <= '1';
--end if;
-- read data one clock cycle after setting the re
-- and only if FIFO not empty
if i_fifo.s_empty = '0' and i_fifo.s_re = '1' then
result <= i_fifo.s_data;
o_fifo.step <= next_step;
-- stop reading if continue is false (last read)
if not continue then
o_fifo.s_re <= '0';
end if;
end if;
end procedure fifo_pull_word;
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
) is begin
o_fifo.m_data <= data;
if i_fifo.m_full = '0'
and (i_fifo.m_we = '0' or or_reduce(i_fifo.m_rem) = '1') then
-- write data into FIFO if
-- FIFO is not full
-- and no previous write or more than one word free
o_fifo.m_we <= '1';
o_fifo.step <= next_step;
end if;
end procedure fifo_push_word;
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- because of the FIFO implementation used
-- we can keep the RE high and check the empty flag
o_fifo.s_re <= '1';
-- set address one word before actual address
--o_ram.addr <= i_ram.addr - 1;
o_ram.step <= 1;
o_ram.count <= (others => '0');
when 1 =>
o_fifo.s_re <= '1';
if i_fifo.s_empty = '0' then
o_ram.we <= '1';
o_ram.data <= i_fifo.s_data;
if or_reduce(i_ram.count) = '0' then
o_ram.addr <= i_ram.addr;
else
o_ram.addr <= i_ram.addr + 1;
end if;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
end if;
when others =>
o_ram.we <= '0';
o_ram.step <= 0;
o_fifo.s_re <= '0';
o_fifo.step <= next_step;
end case;
end procedure fifo_pull;
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- waiting for FIFO to become empty enough
-- this is not so nice, but should be now major drawback
-- since the FIFOs are empty most of the time
if i_fifo.m_full = '0' and i_fifo.m_rem >= count - 1 then
o_ram.count <= (others => '0');
o_ram.addr <= i_ram.addr + 1;
o_ram.step <= 1;
end if;
when 1 =>
o_fifo.m_we <= '1';
o_fifo.m_data <= i_ram.data;
o_ram.addr <= i_ram.addr + 1;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
when others =>
o_ram.addr <= i_ram.addr - 2;
o_ram.step <= 0;
o_fifo.m_we <= '0';
o_fifo.step <= next_step;
end case;
end procedure fifo_push;
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_pull_word(i_osif, o_osif, result, 1, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_read;
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_push_word(i_osif, o_osif, data, 1);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_write;
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
fifo_pull_word(i_osif, o_osif, result, 3, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_0;
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result, 4, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1;
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result1, 4, True);
when 4 =>
fifo_pull_word(i_osif, o_osif, result2, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1_2;
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
-- push arg1 into FIFO
fifo_push_word(i_osif, o_osif, arg1, 4);
when 4 =>
fifo_pull_word(i_osif, o_osif, result, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_2;
-- osif functions
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
o_osif.void <= '1';
end procedure osif_set_yield;
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_POST, handle, result, done);
end procedure osif_sem_post;
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_WAIT, handle, result, done);
end procedure osif_sem_wait;
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_LOCK, handle, result, done);
end procedure osif_mutex_lock;
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_UNLOCK, handle, result, done);
end procedure osif_mutex_unlock;
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_TRYLOCK, handle, result, done);
end procedure osif_mutex_trylock;
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_COND_WAIT, cond_handle, mutex_handle, result, done);
end procedure osif_cond_wait;
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_SIGNAL, handle, result, done);
end procedure osif_cond_signal;
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_BROADCAST, handle, result, done);
end procedure osif_cond_broadcast;
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_PUT, handle, word, result, done);
end procedure osif_mbox_put;
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MBOX_GET, handle, result, done);
end procedure osif_mbox_get;
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYPUT, handle, word, result, done);
end procedure osif_mbox_tryput;
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYGET, handle, result1, result2, done);
end procedure osif_mbox_tryget;
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_receive;
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_send;
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_0(i_osif, o_osif, OSIF_CMD_THREAD_GET_INIT_DATA, result, done);
end procedure osif_get_init_data;
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- push THREAD_EXIT
fifo_push_word(i_osif, o_osif, OSIF_CMD_THREAD_EXIT, 1);
when others =>
-- never return from this loop
o_osif.step <= 2;
end case;
end procedure osif_thread_exit;
--memif functions
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
) is begin
done := False;
if i_memif.m_rem = X"007F" and i_memif.m_full = '0' then
done := True;
end if;
end procedure memif_flush;
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr(31 downto 2) & "00", 2);
when 2 =>
fifo_push_word(i_memif, o_memif, data, 3);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write_word;
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr(31 downto 2) & "00", 2);
when 2 =>
fifo_pull_word(i_memif, o_memif, data, 3, False);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read_word;
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= src_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= dst_addr(31 downto 2) & "00";
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_push(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write;
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= dst_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= src_addr(31 downto 2) & "00";
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_pull(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_pull(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read;
end package body reconos_pkg;
| gpl-2.0 | ab39519f272e05abf2ba500602ec6d54 | 0.61946 | 2.822251 | false | false | false | false |
EPiCS/reconos | pcores/reconos_osif_intc_v1_00_a/hdl/vhdl/reconos_osif_intc.vhd | 2 | 9,187 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library reconos_osif_intc_v1_00_a;
use reconos_osif_intc_v1_00_a.user_logic;
entity reconos_osif_intc is
generic (
-- INTC paramters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
OSIF_INTC_Rst : in std_logic;
-- INTC ports
-- BEGIN GENERATE LOOP
OSIF_INTC_In_#i# : in std_logic;
-- END GENERATE LOOP
OSIF_INTC_Out : out std_logic;
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
-- BEGIN GENERATE LOOP
attribute SIGIS of OSIF_INTC_In_#i# : signal is "Intr_Level_High";
-- END GENERATE LOOP
attribute SIGIS of OSIF_INTC_Out : signal is "Intr_Level_High";
end entity reconos_osif_intc;
architecture implementation of reconos_osif_intc is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := C_NUM_INTERRUPTS / C_SLV_DWIDTH + 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal intc_in : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity reconos_osif_intc_v1_00_a.user_logic
generic map (
-- INTC ports
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- only one global reset
OSIF_INTC_Rst => OSIF_INTC_Rst,
-- INTC ports
OSIF_INTC_In => intc_in,
OSIF_INTC_Out => OSIF_INTC_Out,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
-- BEGIN GENERATE LOOP
intc_in(#i#) <= OSIF_INTC_In_#i#;
-- END GENERATE LOOP
end implementation;
| gpl-2.0 | ded79bf95e1cdfde3cf46edc8a778f67 | 0.586871 | 2.820387 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/pciwbsequ.vhd | 1 | 15,855 | --+-------------------------------------------------------------------------------------------------+
--| |
--| Fileo: pciwbsequ.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: FSM controling pci to whisbone transactions. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pciwbsequ is
generic (
BARS : string := "1BARMEM";
WBSIZE : integer := 16;
WBENDIAN : string := "BIG"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- pci
cmd_i : in std_logic_vector(3 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
frame_i : in std_logic;
irdy_i : in std_logic;
devsel_o : out std_logic;
trdy_o : out std_logic;
stop_o : out std_logic;
targ_oe : out std_logic;
-- control
adrcfg_i : in std_logic;
adrmem_i : in std_logic;
pciadrLD_o : out std_logic;
pcidOE_o : out std_logic;
parOE_o : out std_logic;
wbdatLD_o : out std_logic;
wrcfg_o : out std_logic;
rdcfg_o : out std_logic;
-- whisbone
wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_rty_i : in std_logic;
wb_err_i : in std_logic
);
end pciwbsequ;
architecture rtl of pciwbsequ is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, BACKOFF, TURN_ARL, TURN_ARE );
signal pst_pci : PciFSM;
signal nxt_pci : PciFSM;
signal bbusy : std_logic;
signal idle : std_logic;
signal sdata1 : std_logic;
signal sdata2 : std_logic;
signal sdata1NX : std_logic;
signal sdata2NX : std_logic;
signal turnarlNX : std_logic;
signal turnarl : std_logic;
signal devselNX_n : std_logic;
signal trdyNX_n : std_logic;
signal stopNx_n : std_logic;
signal devsel : std_logic;
signal trdy : std_logic;
signal stop : std_logic;
signal adrpci : std_logic;
signal acking : std_logic;
signal retrying : std_logic;
signal rdcfg : std_logic;
signal targOE : std_logic;
signal pcidOE : std_logic;
signal pcidOE_s : std_logic;
begin
--+-------------------------------------------------------------------------+
--| PCI-Whisbone Sequencer |
--+-------------------------------------------------------------------------+
--+-------------------------------------------------------------+
--| FSM PCI-Whisbone |
--+-------------------------------------------------------------+
PCIFSM_CLOCKED: process( rst_i, clk_i, nxt_pci )
begin
if( rst_i = '1' ) then
pst_pci <= PCIIDLE;
elsif( rising_edge(clk_i) ) then
pst_pci <= nxt_pci;
end if;
end process PCIFSM_CLOCKED;
PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking, retrying )
begin
devselNX_n <= '1';
trdyNX_n <= '1';
stopNX_n <= '1';
case pst_pci is
when PCIIDLE =>
if ( frame_i = '0' ) then
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end if;
when B_BUSY =>
if ( adrpci = '0' ) then
nxt_pci <= TURN_ARE;
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA1 =>
if (acking = '1') then
if (frame_i = '0') then
stopNX_n <= '0';
end if;
nxt_pci <= S_DATA2;
devselNX_n <= '0';
trdyNX_n <= '0';
elsif (retrying = '1') then
nxt_pci <= BACKOFF;
devselNX_n <= '0';
stopNX_n <= '0';
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA2 =>
nxt_pci <= TURN_ARL;
when BACKOFF =>
if ( frame_i = '1' and irdy_i = '0' ) then
nxt_pci <= TURN_ARL;
else
nxt_pci <= BACKOFF;
devselNX_n <= '0';
stopNX_n <= '0';
end if;
when TURN_ARL =>
if (frame_i = '0') then
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end if;
when TURN_ARE =>
if (frame_i = '0') then
nxt_pci <= TURN_ARE;
else
nxt_pci <= PCIIDLE;
end if;
end case;
end process PCIFSM_COMB;
--+-------------------------------------------------------------+
--| FSM control signals |
--+-------------------------------------------------------------+
adrpci <= adrmem_i or adrcfg_i;
acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0')
else '0';
retrying <= '1' when ( wb_rty_i = '1' ) else '0';
--+-------------------------------------------------------------+
--| FSM derived Control signals |
--+-------------------------------------------------------------+
idle <= '1' when ( pst_pci = PCIIDLE ) else '0';
bbusy <= '1' when ( pst_pci = B_BUSY ) else '0';
sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0';
sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0';
--turnar <= '1' when ( pst_pci = TURN_AR ) else '0';
turnarl <= '1' when ( pst_pci = TURN_ARL ) else '0';
sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0';
sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0';
--turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0';
turnarlNX <= '1' when ( nxt_pci = TURN_ARL ) else '0';
--+-------------------------------------------------------------+
--| PCI Data Output Enable |
--+-------------------------------------------------------------+
PCIDOE_P: process( rst_i, clk_i, cmd_i(0), sdata1NX, turnarlNX )
begin
if ( rst_i = '1' ) then
pcidOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' and cmd_i(0) = '0' ) then
pcidOE <= '1';
elsif ( turnarlNX = '1' ) then
pcidOE <= '0';
end if;
end if;
end process PCIDOE_P;
pcidOE_o <= pcidOE;
--+-------------------------------------------------------------+
--| PAR Output Enable |
--| PCI Read data phase |
--| PAR is valid 1 cicle after data is valid |
--+-------------------------------------------------------------+
uu1: entity work.syncl port map ( clk => clk_i, rst => rst_i, d => pcidOE, q => pcidOE_s );
parOE_o <= pcidOE_s;
--+-------------------------------------------------------------+
--| Target s/t/s signals OE control |
--+-------------------------------------------------------------+
TARGOE_P: process( rst_i, clk_i, sdata1NX, turnarl )
begin
if ( rst_i = '1' ) then
targOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' ) then
targOE <= '1';
elsif ( turnarl = '1' ) then
targOE <= '0';
end if;
end if;
end process TARGOE_P;
--+-------------------------------------------------------------------------+
--| WHISBONE outs |
--+-------------------------------------------------------------------------+
cyc_p: process(rst_i, clk_i, adrmem_i, bbusy, acking, retrying, frame_i)
begin
if ( rst_i = '1' ) then
wb_cyc_o <= '0';
elsif ( rising_edge(clk_i) ) then
if (adrmem_i = '1' and bbusy = '1' ) then
wb_cyc_o <= '1';
elsif ((acking = '1' or retrying = '1') and frame_i = '1') then
wb_cyc_o <= '0';
end if;
end if;
end process cyc_p;
wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';
wb_we_o <= cmd_i(0);
--+-----------------------------------------+
--| wb_sel_o generation depending on WBSIZE |
--| and WBENDIAN "generics" configuration |
--+-----------------------------------------+
sel32: if (WBSIZE = 32) generate
wb_sel_o(3) <= not cbe_i(3);
wb_sel_o(2) <= not cbe_i(2);
wb_sel_o(1) <= not cbe_i(1);
wb_sel_o(0) <= not cbe_i(0);
end generate;
sel16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));
wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));
end generate;
sel16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
wb_sel_o(1) <= (not cbe_i(1)) or (not cbe_i(3));
wb_sel_o(0) <= (not cbe_i(0)) or (not cbe_i(2));
end generate;
sel8: if (WBSIZE = 8) generate
wb_sel_o(0) <= not (cbe_i(0) and cbe_i(1) and cbe_i(2) and cbe_i(3));
end generate;
--+-------------------------------------------------------------------------+
--| Syncronized PCI outs |
--+-------------------------------------------------------------------------+
PCISIG: process( rst_i, clk_i, devselNX_n, trdyNX_n, stopNX_n)
begin
if( rst_i = '1' ) then
devsel <= '1';
trdy <= '1';
stop <= '1';
elsif( rising_edge(clk_i) ) then
devsel <= devselNX_n;
trdy <= trdyNX_n;
stop <= stopNX_n;
end if;
end process PCISIG;
targ_oe <= targOE;
devsel_o <= devsel;
trdy_o <= trdy;
stop_o <= stop;
--+-------------------------------------------------------------------------+
--| Other outs |
--+-------------------------------------------------------------------------+
-- rd/wr Configuration Space Registers
wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';
rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';
rdcfg_o <= rdcfg;
-- LoaD enable signals
--pciadrLD_o <= '1' when(frame_i = '0' and idle = '1') else '0';
-- added turnarl to support Fast Back to Back
pciadrLD_o <= '1' when(frame_i = '0' and (idle = '1' or turnarl = '1')) else '0';
wbdatLD_o <= wb_ack_i;
end rtl;
| gpl-3.0 | c8991301e837c8bbee1fbcc09a2ed8a1 | 0.315547 | 4.626495 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_atoms.vhd | 1 | 351,195 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixv_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixv_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixv_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixv_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixv_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixv_pllpack;
package body stratixv_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixv_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
entity stratixv_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixv_dffe : entity is TRUE;
end stratixv_dffe;
-- architecture body --
architecture behave of stratixv_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixv_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixv_atom_pack.all;
entity stratixv_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixv_mux21 : entity is TRUE;
end stratixv_mux21;
architecture AltVITAL of stratixv_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixv_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixv_atom_pack.all;
entity stratixv_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixv_mux41 : entity is TRUE;
end stratixv_mux41;
architecture AltVITAL of stratixv_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixv_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixv_atom_pack.all;
-- entity declaration --
entity stratixv_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixv_and1 : entity is TRUE;
end stratixv_and1;
-- architecture body --
architecture AltVITAL of stratixv_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_ff
--
-- Description : STRATIXV FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
use work.stratixv_and1;
entity stratixv_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixv_ff : entity is TRUE;
end stratixv_ff;
architecture vital_lcell_ff of stratixv_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixv_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixv_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixv_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixv_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------------
--Module Name: stratixv_pseudo_diff_out --
--Description: Simulation model for Stratix V Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tipd_oein : VitalDelayType01 := DefPropDelay01;
tpd_oein_oeout : VitalDelayType01 := DefPropDelay01;
tpd_oein_oebout : VitalDelayType01 := DefPropDelay01;
tipd_dtcin : VitalDelayType01 := DefPropDelay01;
tpd_dtcin_dtc : VitalDelayType01 := DefPropDelay01;
tpd_dtcin_dtcbar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratuxv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic;
dtcin : in std_logic := '0';
oein : in std_logic := '0';
dtc : OUT std_logic;
dtcbar : OUT std_logic;
oeout : OUT std_logic;
oebout : OUT std_logic
);
END stratixv_pseudo_diff_out;
ARCHITECTURE arch OF stratixv_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
SIGNAL dtcin_ipd : std_logic ;
SIGNAL dtc_tmp : std_logic ;
SIGNAL dtcbar_tmp : std_logic;
SIGNAL oein_ipd : std_logic ;
SIGNAL oeout_tmp : std_logic ;
SIGNAL oebout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
-- oe
WireDelay_OE : block
begin
VitalWireDelay (oein_ipd, oein, tipd_oein);
end block;
PROCESS( oein_ipd)
BEGIN
IF (oein_ipd = '0') THEN
oeout_tmp <= '0';
oebout_tmp <= '0';
ELSE
IF (oein_ipd = '1') THEN
oeout_tmp <= '1';
oebout_tmp <= '1';
ELSE
oeout_tmp <= oein_ipd;
oebout_tmp <= oein_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( oeout_tmp,oebout_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => oeout,
OutSignalName => "oeout",
OutTemp => oeout_tmp,
Paths => (0 => (oein_ipd'last_event, tpd_oein_oeout, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => oebout,
OutSignalName => "oebout",
OutTemp => oebout_tmp,
Paths => (0 => (oein_ipd'last_event, tpd_oein_oebout, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
-- dtc
WireDelay_DTC : block
begin
VitalWireDelay (dtcin_ipd, dtcin, tipd_dtcin);
end block;
PROCESS( dtcin_ipd)
BEGIN
IF (dtcin_ipd = '0') THEN
dtc_tmp <= '0';
dtcbar_tmp <= '0';
ELSE
IF (dtcin_ipd = '1') THEN
dtc_tmp <= '1';
dtcbar_tmp <= '1';
ELSE
dtc_tmp <= dtcin_ipd;
dtcbar_tmp <= dtcin_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( dtc_tmp,dtcbar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable dtcbar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dtc,
OutSignalName => "dtc",
OutTemp => dtc_tmp,
Paths => (0 => (dtcin_ipd'last_event, tpd_dtcin_dtc, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => dtcbar,
OutSignalName => "dtcbar",
OutTemp => dtcbar_tmp,
Paths => (0 => (dtcin_ipd'last_event, tpd_dtcin_dtcbar, TRUE)),
GlitchData => dtcbar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_lcell_comb
--
-- Description : STRATIXV LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
entity stratixv_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixv_lcell_comb : entity is TRUE;
end stratixv_lcell_comb;
architecture vital_lcell_comb of stratixv_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_routing_wire
--
-- Description : STRATIXV Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixv_routing_wire : entity is TRUE;
end stratixv_routing_wire;
ARCHITECTURE behave of stratixv_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY stratixv_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
ecc_pipeline_stage_enabled : STRING := "false";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 2;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
bist_ena : STRING := "false";
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : STRING := "";
mem_init1 : STRING := "";
mem_init2 : STRING := "";
mem_init3 : STRING := "";
mem_init4 : STRING := "";
mem_init5 : STRING := "";
mem_init6 : STRING := "";
mem_init7 : STRING := "";
mem_init8 : STRING := "";
mem_init9 : STRING := "";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
nerror : IN STD_LOGIC := '1';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixv_ram_block;
ARCHITECTURE block_arch OF stratixv_ram_block IS
COMPONENT generic_m20k
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
ecc_pipeline_stage_enabled : STRING := "false";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 2;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
bist_ena : STRING := "false";
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock : STRING := "clock1";
port_b_read_enable_clock : STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : STRING := "";
mem_init1 : STRING := "";
mem_init2 : STRING := "";
mem_init3 : STRING := "";
mem_init4 : STRING := "";
mem_init5 : STRING := "";
mem_init6 : STRING := "";
mem_init7 : STRING := "";
mem_init8 : STRING := "";
mem_init9 : STRING := "";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
nerror : IN STD_LOGIC := '1';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
BEGIN
inst : generic_m20k
generic map (
operation_mode => operation_mode,
mixed_port_feed_through_mode => mixed_port_feed_through_mode,
ram_block_type => ram_block_type,
logical_ram_name => logical_ram_name,
init_file => init_file,
init_file_layout => init_file_layout,
ecc_pipeline_stage_enabled => ecc_pipeline_stage_enabled,
enable_ecc => enable_ecc,
width_eccstatus => width_eccstatus,
data_interleave_width_in_bits => data_interleave_width_in_bits,
data_interleave_offset_in_bits => data_interleave_offset_in_bits,
port_a_logical_ram_depth => port_a_logical_ram_depth,
port_a_logical_ram_width => port_a_logical_ram_width,
port_a_first_address => port_a_first_address,
port_a_last_address => port_a_last_address,
port_a_first_bit_number => port_a_first_bit_number,
port_a_data_out_clear => port_a_data_out_clear,
port_a_data_out_clock => port_a_data_out_clock,
port_a_data_width => port_a_data_width,
port_a_address_width => port_a_address_width,
port_a_byte_enable_mask_width => port_a_byte_enable_mask_width,
port_b_logical_ram_depth => port_b_logical_ram_depth,
port_b_logical_ram_width => port_b_logical_ram_width,
port_b_first_address => port_b_first_address,
port_b_last_address => port_b_last_address,
port_b_first_bit_number => port_b_first_bit_number,
port_b_address_clear => port_b_address_clear,
port_b_data_out_clear => port_b_data_out_clear,
port_b_data_in_clock => port_b_data_in_clock,
port_b_address_clock => port_b_address_clock,
port_b_write_enable_clock => port_b_write_enable_clock,
port_b_read_enable_clock => port_b_read_enable_clock,
port_b_byte_enable_clock => port_b_byte_enable_clock,
port_b_data_out_clock => port_b_data_out_clock,
port_b_data_width => port_b_data_width,
port_b_address_width => port_b_address_width,
port_b_byte_enable_mask_width => port_b_byte_enable_mask_width,
port_a_read_during_write_mode => port_a_read_during_write_mode,
port_b_read_during_write_mode => port_b_read_during_write_mode,
power_up_uninitialized => power_up_uninitialized,
lpm_type => lpm_type,
lpm_hint => lpm_hint,
connectivity_checking => connectivity_checking,
mem_init0 => mem_init0,
mem_init1 => mem_init1,
mem_init2 => mem_init2,
mem_init3 => mem_init3,
mem_init4 => mem_init4,
mem_init5 => mem_init5,
mem_init6 => mem_init6,
mem_init7 => mem_init7,
mem_init8 => mem_init8,
mem_init9 => mem_init9,
port_a_byte_size => port_a_byte_size,
port_b_byte_size => port_b_byte_size,
clk0_input_clock_enable => clk0_input_clock_enable,
clk0_core_clock_enable => clk0_core_clock_enable,
clk0_output_clock_enable => clk0_output_clock_enable,
clk1_input_clock_enable => clk1_input_clock_enable,
clk1_core_clock_enable => clk1_core_clock_enable,
clk1_output_clock_enable => clk1_output_clock_enable,
bist_ena => bist_ena,
port_a_address_clear => port_a_address_clear,
port_a_data_in_clock => port_a_data_in_clock,
port_a_address_clock => port_a_address_clock,
port_a_write_enable_clock => port_a_write_enable_clock,
port_a_byte_enable_clock => port_a_byte_enable_clock,
port_a_read_enable_clock => port_a_read_enable_clock
)
port map (
portadatain => portadatain ,
portaaddr => portaaddr ,
portawe => portawe ,
portare => portare ,
portbdatain => portbdatain ,
portbaddr => portbaddr ,
portbwe => portbwe ,
portbre => portbre ,
clk0 => clk0 ,
clk1 => clk1 ,
ena0 => ena0 ,
ena1 => ena1 ,
ena2 => ena2 ,
ena3 => ena3 ,
clr0 => clr0 ,
clr1 => clr1 ,
nerror => nerror ,
portabyteenamasks => portabyteenamasks,
portbbyteenamasks => portbbyteenamasks,
portaaddrstall => portaaddrstall ,
portbaddrstall => portbaddrstall ,
devclrn => devclrn ,
devpor => devpor ,
eccstatus => eccstatus ,
portadataout => portadataout ,
portbdataout => portbdataout ,
dftout => dftout
);
END block_arch;
----------------------------------------------------------------------------
-- Entity Name : stratixv_mlab_cell
-- Description : LUTRAM VHDL Simulation Model
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixv_atom_pack.all;
ENTITY stratixv_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "stratixv_mlab_cell";
lpm_hint : STRING := "true";
mem_init0 : STRING := "";
mixed_port_feed_through_mode : STRING := "new"
);
PORT (
-- -------- PORT DECLARATIONS ---------
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
clr : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixv_mlab_cell;
ARCHITECTURE trans OF stratixv_mlab_cell IS
COMPONENT generic_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "stratixv_mlab_cell";
lpm_hint : STRING := "true";
mem_init0 : STRING := "";
mixed_port_feed_through_mode : STRING := "new"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
clr : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
BEGIN
inst : generic_mlab_cell
generic map (
logical_ram_name => logical_ram_name ,
logical_ram_depth => logical_ram_depth ,
logical_ram_width => logical_ram_width ,
first_address => first_address ,
last_address => last_address ,
first_bit_number => first_bit_number ,
init_file => init_file ,
data_width => data_width ,
address_width => address_width ,
byte_enable_mask_width => byte_enable_mask_width ,
byte_size => byte_size ,
port_b_data_out_clock => port_b_data_out_clock ,
port_b_data_out_clear => port_b_data_out_clear ,
lpm_type => lpm_type ,
lpm_hint => lpm_hint ,
mem_init0 => mem_init0 ,
mixed_port_feed_through_mode => mixed_port_feed_through_mode
)
port map (
portadatain => portadatain ,
portaaddr => portaaddr ,
portabyteenamasks => portabyteenamasks ,
portbaddr => portbaddr ,
clk0 => clk0 ,
clk1 => clk1 ,
ena0 => ena0 ,
ena1 => ena1 ,
ena2 => ena2 ,
clr => clr ,
devclrn => devclrn ,
devpor => devpor ,
portbdataout => portbdataout
);
END trans;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_io_ibuf
--
-- Description : STRATIXV IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixv_io_ibuf;
ARCHITECTURE arch OF stratixv_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_io_obuf
--
-- Description : STRATIXV IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tipd_parallelterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixv_io_obuf;
ARCHITECTURE arch OF stratixv_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixv_ddio_in
--
-- Description : STRATIXV DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixv_ddio_in;
ARCHITECTURE arch OF stratixv_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_ddio_oe
--
-- Description : STRATIXV DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixv_ddio_oe;
ARCHITECTURE arch OF stratixv_ddio_oe IS
component stratixv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixv_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixv_ddio_out
--
-- Description : STRATIXV DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixv_ddio_out;
ARCHITECTURE arch OF stratixv_ddio_out IS
component stratixv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp;
sel_mux : stratixv_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixv_io_pad
-- Description : Simulation model for stratixv IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixv_io_pad IS
GENERIC (
lpm_type : string := "stratixv_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixv_io_pad;
ARCHITECTURE arch OF stratixv_io_pad IS
BEGIN
padout <= padin;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixv_bias_logic
--
-- Description : STRATIXV Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixv_bias_logic : ENTITY IS TRUE;
end stratixv_bias_logic;
ARCHITECTURE vital_bias_logic of stratixv_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixv_bias_generator
--
-- Description : STRATIXV Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixv_bias_generator : ENTITY IS TRUE;
end stratixv_bias_generator;
ARCHITECTURE vital_bias_generator of stratixv_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 202;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixv_bias_block
--
-- Description : STRATIXV Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixv_atom_pack.all;
ENTITY stratixv_bias_block IS
GENERIC (
lpm_type : string := "stratixv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixv_bias_block : ENTITY IS TRUE;
end stratixv_bias_block;
ARCHITECTURE vital_bias_block of stratixv_bias_block IS
COMPONENT stratixv_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixv_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixv_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixv_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_mac is
generic (
lpm_type : string := "stratixv_mac";
ax_width : integer := 16;
ay_scan_in_width : integer := 16;
az_width : integer := 1;
bx_width : integer := 16;
by_width : integer := 16;
scan_out_width : integer := 1;
result_a_width : integer := 33;
result_b_width : integer := 1;
operation_mode : string := "m18x18_sumof2";
mode_sub_location : integer := 0;
operand_source_max : string := "input";
operand_source_may : string := "input";
operand_source_mbx : string := "input";
operand_source_mby : string := "input";
preadder_subtract_a : string := "false";
preadder_subtract_b : string := "false";
signed_max : string := "false";
signed_may : string := "false";
signed_mbx : string := "false";
signed_mby : string := "false";
ay_use_scan_in : string := "false";
by_use_scan_in : string := "false";
delay_scan_out_ay : string := "false";
delay_scan_out_by : string := "false";
use_chainadder : string := "false";
load_const_value : integer := 0;
coef_a_0 : integer := 0;
coef_a_1 : integer := 0;
coef_a_2 : integer := 0;
coef_a_3 : integer := 0;
coef_a_4 : integer := 0;
coef_a_5 : integer := 0;
coef_a_6 : integer := 0;
coef_a_7 : integer := 0;
coef_b_0 : integer := 0;
coef_b_1 : integer := 0;
coef_b_2 : integer := 0;
coef_b_3 : integer := 0;
coef_b_4 : integer := 0;
coef_b_5 : integer := 0;
coef_b_6 : integer := 0;
coef_b_7 : integer := 0;
ax_clock : string := "none";
ay_scan_in_clock : string := "none";
az_clock : string := "none";
bx_clock : string := "none";
by_clock : string := "none";
coef_sel_a_clock : string := "none";
coef_sel_b_clock : string := "none";
sub_clock : string := "none";
negate_clock : string := "none";
accumulate_clock : string := "none";
load_const_clock : string := "none";
complex_clock : string := "none";
output_clock : string := "none"
);
port (
sub : in std_logic := '0';
negate : in std_logic := '0';
accumulate : in std_logic := '0';
loadconst : in std_logic := '0';
complex : in std_logic := '0';
cin : in std_logic := '0';
ax : in std_logic_vector(ax_width-1 downto 0) := (others => '0');
ay : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0');
scanin : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0');
az : in std_logic_vector(az_width-1 downto 0) := (others => '0');
bx : in std_logic_vector(bx_width-1 downto 0) := (others => '0');
by : in std_logic_vector(by_width-1 downto 0) := (others => '0');
coefsela : in std_logic_vector(2 downto 0) := (others => '0');
coefselb : in std_logic_vector(2 downto 0) := (others => '0');
clk : in std_logic_vector(2 downto 0) := (others => '0');
aclr : in std_logic_vector(1 downto 0) := (others => '0');
ena : in std_logic_vector(2 downto 0) := (others => '1');
chainin : in std_logic_vector(63 downto 0) := (others => '0');
cout : out std_logic;
dftout : out std_logic;
resulta : out std_logic_vector(result_a_width-1 downto 0);
resultb : out std_logic_vector(result_b_width-1 downto 0);
scanout : out std_logic_vector(scan_out_width-1 downto 0);
chainout : out std_logic_vector(63 downto 0)
);
end stratixv_mac;
architecture behavior of stratixv_mac is
component stratixv_mac_encrypted
generic (
lpm_type : string := "stratixv_mac";
ax_width : integer := 16;
ay_scan_in_width : integer := 16;
az_width : integer := 1;
bx_width : integer := 16;
by_width : integer := 16;
scan_out_width : integer := 1;
result_a_width : integer := 33;
result_b_width : integer := 1;
operation_mode : string := "m18x18_sumof2";
mode_sub_location : integer := 0;
operand_source_max : string := "input";
operand_source_may : string := "input";
operand_source_mbx : string := "input";
operand_source_mby : string := "input";
preadder_subtract_a : string := "false";
preadder_subtract_b : string := "false";
signed_max : string := "false";
signed_may : string := "false";
signed_mbx : string := "false";
signed_mby : string := "false";
ay_use_scan_in : string := "false";
by_use_scan_in : string := "false";
delay_scan_out_ay : string := "false";
delay_scan_out_by : string := "false";
use_chainadder : string := "false";
load_const_value : integer := 0;
coef_a_0 : integer := 0;
coef_a_1 : integer := 0;
coef_a_2 : integer := 0;
coef_a_3 : integer := 0;
coef_a_4 : integer := 0;
coef_a_5 : integer := 0;
coef_a_6 : integer := 0;
coef_a_7 : integer := 0;
coef_b_0 : integer := 0;
coef_b_1 : integer := 0;
coef_b_2 : integer := 0;
coef_b_3 : integer := 0;
coef_b_4 : integer := 0;
coef_b_5 : integer := 0;
coef_b_6 : integer := 0;
coef_b_7 : integer := 0;
ax_clock : string := "none";
ay_scan_in_clock : string := "none";
az_clock : string := "none";
bx_clock : string := "none";
by_clock : string := "none";
coef_sel_a_clock : string := "none";
coef_sel_b_clock : string := "none";
sub_clock : string := "none";
negate_clock : string := "none";
accumulate_clock : string := "none";
load_const_clock : string := "none";
complex_clock : string := "none";
output_clock : string := "none"
);
port (
sub : in std_logic;
negate : in std_logic;
accumulate : in std_logic;
loadconst : in std_logic;
complex : in std_logic;
cin : in std_logic;
ax : in std_logic_vector(ax_width-1 downto 0);
ay : in std_logic_vector(ay_scan_in_width-1 downto 0);
scanin : in std_logic_vector(ay_scan_in_width-1 downto 0);
az : in std_logic_vector(az_width-1 downto 0);
bx : in std_logic_vector(bx_width-1 downto 0);
by : in std_logic_vector(by_width-1 downto 0);
coefsela : in std_logic_vector(2 downto 0);
coefselb : in std_logic_vector(2 downto 0);
clk : in std_logic_vector(2 downto 0);
aclr : in std_logic_vector(1 downto 0);
ena : in std_logic_vector(2 downto 0);
chainin : in std_logic_vector(63 downto 0);
cout : out std_logic;
dftout : out std_logic;
resulta : out std_logic_vector(result_a_width-1 downto 0);
resultb : out std_logic_vector(result_b_width-1 downto 0);
scanout : out std_logic_vector(scan_out_width-1 downto 0);
chainout : out std_logic_vector(63 downto 0)
);
end component;
begin
inst : stratixv_mac_encrypted
generic map (
lpm_type => lpm_type,
ax_width => ax_width,
ay_scan_in_width => ay_scan_in_width,
az_width => az_width,
bx_width => bx_width,
by_width => by_width,
scan_out_width => scan_out_width,
result_a_width => result_a_width,
result_b_width => result_b_width,
operation_mode => operation_mode,
mode_sub_location => mode_sub_location,
operand_source_max => operand_source_max,
operand_source_may => operand_source_may,
operand_source_mbx => operand_source_mbx,
operand_source_mby => operand_source_mby,
preadder_subtract_a => preadder_subtract_a,
preadder_subtract_b => preadder_subtract_b,
signed_max => signed_max,
signed_may => signed_may,
signed_mbx => signed_mbx,
signed_mby => signed_mby,
ay_use_scan_in => ay_use_scan_in,
by_use_scan_in => by_use_scan_in,
delay_scan_out_ay => delay_scan_out_ay,
delay_scan_out_by => delay_scan_out_by,
use_chainadder => use_chainadder,
load_const_value => load_const_value,
coef_a_0 => coef_a_0,
coef_a_1 => coef_a_1,
coef_a_2 => coef_a_2,
coef_a_3 => coef_a_3,
coef_a_4 => coef_a_4,
coef_a_5 => coef_a_5,
coef_a_6 => coef_a_6,
coef_a_7 => coef_a_7,
coef_b_0 => coef_b_0,
coef_b_1 => coef_b_1,
coef_b_2 => coef_b_2,
coef_b_3 => coef_b_3,
coef_b_4 => coef_b_4,
coef_b_5 => coef_b_5,
coef_b_6 => coef_b_6,
coef_b_7 => coef_b_7,
ax_clock => ax_clock,
ay_scan_in_clock => ay_scan_in_clock,
az_clock => az_clock,
bx_clock => bx_clock,
by_clock => by_clock,
coef_sel_a_clock => coef_sel_a_clock,
coef_sel_b_clock => coef_sel_b_clock,
sub_clock => sub_clock,
negate_clock => negate_clock,
accumulate_clock => accumulate_clock,
load_const_clock => load_const_clock,
complex_clock => complex_clock,
output_clock => output_clock
)
port map (
sub => sub,
negate => negate,
accumulate => accumulate,
loadconst => loadconst,
complex => complex,
cin => cin,
ax => ax,
ay => ay,
scanin => scanin,
az => az,
bx => bx,
by => by,
coefsela => coefsela,
coefselb => coefselb,
clk => clk,
aclr => aclr,
ena => ena,
chainin => chainin,
cout => cout,
dftout => dftout,
resulta => resulta,
resultb => resultb,
scanout => scanout,
chainout => chainout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_clk_phase_select is
generic (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
invert_phase : string := "false";
physical_clock_source : string := "auto"
);
port (
clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
phaseinvertctrl : in std_logic := '0';
powerdown : in std_logic := '0';
clkout : out std_logic
);
end stratixv_clk_phase_select;
architecture behavior of stratixv_clk_phase_select is
component stratixv_clk_phase_select_encrypted
generic (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
invert_phase : string := "false";
physical_clock_source : string := "auto"
);
port (
clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
phaseinvertctrl : in std_logic := '0';
powerdown : in std_logic := '0';
clkout : out std_logic
);
end component;
begin
inst : stratixv_clk_phase_select_encrypted
generic map (
use_phasectrlin => use_phasectrlin,
phase_setting => phase_setting,
invert_phase => invert_phase,
physical_clock_source => physical_clock_source
)
port map (
clkin => clkin,
phasectrlin => phasectrlin,
phaseinvertctrl => phaseinvertctrl,
powerdown => powerdown,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_clkena is
generic (
clock_type : string := "auto";
ena_register_mode : string := "always enabled";
lpm_type : string := "stratixv_clkena";
ena_register_power_up : string := "high";
disable_mode : string := "low";
test_syn : string := "high"
);
port (
inclk : in std_logic := '1';
ena : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
end stratixv_clkena;
architecture behavior of stratixv_clkena is
component stratixv_clkena_encrypted
generic (
clock_type : string := "auto";
ena_register_mode : string := "always enabled";
lpm_type : string := "stratixv_clkena";
ena_register_power_up : string := "high";
disable_mode : string := "low";
test_syn : string := "high"
);
port (
inclk : in std_logic;
ena : in std_logic;
enaout : out std_logic;
outclk : out std_logic
);
end component;
begin
inst : stratixv_clkena_encrypted
generic map (
clock_type => clock_type,
ena_register_mode => ena_register_mode,
lpm_type => lpm_type,
ena_register_power_up => ena_register_power_up,
disable_mode => disable_mode,
test_syn => test_syn
)
port map (
inclk => inclk,
ena => ena,
enaout => enaout,
outclk => outclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_clkselect is
generic (
lpm_type : string := "stratixv_clkselect";
test_cff : string := "low"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
end stratixv_clkselect;
architecture behavior of stratixv_clkselect is
component stratixv_clkselect_encrypted
generic (
lpm_type : string := "stratixv_clkselect";
test_cff : string := "low"
);
port (
inclk : in std_logic_vector(3 downto 0);
clkselect : in std_logic_vector(1 downto 0);
outclk : out std_logic
);
end component;
begin
inst : stratixv_clkselect_encrypted
generic map (
lpm_type => lpm_type,
test_cff => test_cff
)
port map (
inclk => inclk,
clkselect => clkselect,
outclk => outclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_delay_chain is
generic (
sim_intrinsic_rising_delay : integer := 200;
sim_intrinsic_falling_delay : integer := 200;
sim_rising_delay_increment : integer := 10;
sim_falling_delay_increment : integer := 10;
lpm_type : string := "stratixv_delay_chain"
);
port (
datain : in std_logic := '0';
delayctrlin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic
);
end stratixv_delay_chain;
architecture behavior of stratixv_delay_chain is
component stratixv_delay_chain_encrypted
generic (
sim_intrinsic_rising_delay : integer := 200;
sim_intrinsic_falling_delay : integer := 200;
sim_rising_delay_increment : integer := 10;
sim_falling_delay_increment : integer := 10;
lpm_type : string := "stratixv_delay_chain"
);
port (
datain : in std_logic := '0';
delayctrlin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic
);
end component;
begin
inst : stratixv_delay_chain_encrypted
generic map (
sim_intrinsic_rising_delay => sim_intrinsic_rising_delay,
sim_intrinsic_falling_delay => sim_intrinsic_falling_delay,
sim_rising_delay_increment => sim_rising_delay_increment,
sim_falling_delay_increment => sim_falling_delay_increment,
lpm_type => lpm_type
)
port map (
datain => datain,
delayctrlin => delayctrlin,
dataout => dataout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_dll_offset_ctrl is
generic (
use_offset : string := "false";
static_offset : integer := 0;
use_pvt_compensation : string := "false"
);
port (
clk : in std_logic := '0';
offsetdelayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offset : in std_logic_vector(6 downto 0) := (OTHERS => '0');
addnsub : in std_logic := '0';
aload : in std_logic := '0';
offsetctrlout : out std_logic_vector(6 downto 0);
offsettestout : out std_logic_vector(6 downto 0)
);
end stratixv_dll_offset_ctrl;
architecture behavior of stratixv_dll_offset_ctrl is
component stratixv_dll_offset_ctrl_encrypted
generic (
use_offset : string := "false";
static_offset : integer := 0;
use_pvt_compensation : string := "false"
);
port (
clk : in std_logic := '0';
offsetdelayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offset : in std_logic_vector(6 downto 0) := (OTHERS => '0');
addnsub : in std_logic := '0';
aload : in std_logic := '0';
offsetctrlout : out std_logic_vector(6 downto 0);
offsettestout : out std_logic_vector(6 downto 0)
);
end component;
begin
inst : stratixv_dll_offset_ctrl_encrypted
generic map (
use_offset => use_offset,
static_offset => static_offset,
use_pvt_compensation => use_pvt_compensation
)
port map (
clk => clk,
offsetdelayctrlin => offsetdelayctrlin,
offset => offset,
addnsub => addnsub,
aload => aload,
offsetctrlout => offsetctrlout,
offsettestout => offsettestout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_dll is
generic (
input_frequency : string := "0 MHz";
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0;
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixv_dll";
delay_chain_length : integer := 8
);
port (
aload : in std_logic := '0';
clk : in std_logic := '0';
upndnin : in std_logic := '0';
upndninclkena : in std_logic := '0';
delayctrlout : out std_logic_vector(6 downto 0);
dqsupdate : out std_logic;
offsetdelayctrlout : out std_logic_vector(6 downto 0);
offsetdelayctrlclkout : out std_logic;
upndnout : out std_logic;
dffin : out std_logic;
locked : out std_logic
);
end stratixv_dll;
architecture behavior of stratixv_dll is
component stratixv_dll_encrypted
generic (
input_frequency : string := "0 MHz";
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0;
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixv_dll";
delay_chain_length : integer := 8
);
port (
aload : in std_logic := '0';
clk : in std_logic := '0';
upndnin : in std_logic := '0';
upndninclkena : in std_logic := '0';
delayctrlout : out std_logic_vector(6 downto 0);
dqsupdate : out std_logic;
offsetdelayctrlout : out std_logic_vector(6 downto 0);
offsetdelayctrlclkout : out std_logic;
upndnout : out std_logic;
dffin : out std_logic;
locked : out std_logic
);
end component;
begin
inst : stratixv_dll_encrypted
generic map (
input_frequency => input_frequency,
delayctrlout_mode => delayctrlout_mode,
jitter_reduction => jitter_reduction,
use_upndnin => use_upndnin,
use_upndninclkena => use_upndninclkena,
dual_phase_comparators => dual_phase_comparators,
sim_valid_lock => sim_valid_lock,
sim_valid_lockcount => sim_valid_lockcount,
sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment,
static_delay_ctrl => static_delay_ctrl,
lpm_type => lpm_type,
delay_chain_length => delay_chain_length
)
port map (
aload => aload,
clk => clk,
upndnin => upndnin,
upndninclkena => upndninclkena,
delayctrlout => delayctrlout,
dqsupdate => dqsupdate,
offsetdelayctrlout => offsetdelayctrlout,
offsetdelayctrlclkout => offsetdelayctrlclkout,
upndnout => upndnout,
dffin => dffin,
locked => locked
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_dqs_config is
generic (
lpm_type : string := "stratixv_dqs_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '0';
update : in std_logic := '0';
dqsbusoutdelaysetting : out std_logic_vector(5 downto 0);
dqsbusoutdelaysetting2 : out std_logic_vector(5 downto 0);
dqsinputphasesetting : out std_logic_vector(1 downto 0);
dqsoutputphasesetting : out std_logic_vector(1 downto 0);
dqoutputphasesetting : out std_logic_vector(1 downto 0);
resyncinputphasesetting : out std_logic_vector(1 downto 0);
enaoctcycledelaysetting : out std_logic_vector(2 downto 0);
enainputcycledelaysetting : out std_logic;
enaoutputcycledelaysetting : out std_logic_vector(2 downto 0);
dqsenabledelaysetting : out std_logic_vector(7 downto 0);
octdelaysetting1 : out std_logic_vector(4 downto 0);
octdelaysetting2 : out std_logic_vector(4 downto 0);
enadqsenablephasetransferreg : out std_logic;
enaoctphasetransferreg : out std_logic;
enaoutputphasetransferreg : out std_logic;
enainputphasetransferreg : out std_logic;
resyncinputphaseinvert : out std_logic;
dqoutputphaseinvert : out std_logic;
dqsoutputphaseinvert : out std_logic;
dataout : out std_logic;
resyncinputzerophaseinvert : out std_logic;
dqs2xoutputphasesetting : out std_logic_vector(1 downto 0);
dqs2xoutputphaseinvert : out std_logic;
ck2xoutputphasesetting : out std_logic_vector(1 downto 0);
ck2xoutputphaseinvert : out std_logic;
dq2xoutputphasesetting : out std_logic_vector(1 downto 0);
dq2xoutputphaseinvert : out std_logic;
postamblephasesetting : out std_logic_vector(1 downto 0);
postamblephaseinvert : out std_logic;
dividerphaseinvert : out std_logic;
addrphasesetting : out std_logic_vector(1 downto 0);
addrphaseinvert : out std_logic;
enadqscycledelaysetting : out std_logic_vector(2 downto 0);
enadqsphasetransferreg : out std_logic;
dqoutputzerophasesetting : out std_logic_vector(1 downto 0);
postamblezerophasesetting : out std_logic_vector(2 downto 0);
dividerioehratephaseinvert : out std_logic;
dqsdisablendelaysetting : out std_logic_vector(7 downto 0);
addrpowerdown : out std_logic;
dqsoutputpowerdown : out std_logic;
dqoutputpowerdown : out std_logic;
resyncinputpowerdown : out std_logic;
dqs2xoutputpowerdown : out std_logic;
ck2xoutputpowerdown : out std_logic;
dq2xoutputpowerdown : out std_logic;
postamblepowerdown : out std_logic
);
end stratixv_dqs_config;
architecture behavior of stratixv_dqs_config is
component stratixv_dqs_config_encrypted
generic (
lpm_type : string := "stratixv_dqs_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '0';
update : in std_logic := '0';
dqsbusoutdelaysetting : out std_logic_vector(5 downto 0);
dqsbusoutdelaysetting2 : out std_logic_vector(5 downto 0);
dqsinputphasesetting : out std_logic_vector(1 downto 0);
dqsoutputphasesetting : out std_logic_vector(1 downto 0);
dqoutputphasesetting : out std_logic_vector(1 downto 0);
resyncinputphasesetting : out std_logic_vector(1 downto 0);
enaoctcycledelaysetting : out std_logic_vector(2 downto 0);
enainputcycledelaysetting : out std_logic;
enaoutputcycledelaysetting : out std_logic_vector(2 downto 0);
dqsenabledelaysetting : out std_logic_vector(7 downto 0);
octdelaysetting1 : out std_logic_vector(4 downto 0);
octdelaysetting2 : out std_logic_vector(4 downto 0);
enadqsenablephasetransferreg : out std_logic;
enaoctphasetransferreg : out std_logic;
enaoutputphasetransferreg : out std_logic;
enainputphasetransferreg : out std_logic;
resyncinputphaseinvert : out std_logic;
dqoutputphaseinvert : out std_logic;
dqsoutputphaseinvert : out std_logic;
dataout : out std_logic;
resyncinputzerophaseinvert : out std_logic;
dqs2xoutputphasesetting : out std_logic_vector(1 downto 0);
dqs2xoutputphaseinvert : out std_logic;
ck2xoutputphasesetting : out std_logic_vector(1 downto 0);
ck2xoutputphaseinvert : out std_logic;
dq2xoutputphasesetting : out std_logic_vector(1 downto 0);
dq2xoutputphaseinvert : out std_logic;
postamblephasesetting : out std_logic_vector(1 downto 0);
postamblephaseinvert : out std_logic;
dividerphaseinvert : out std_logic;
addrphasesetting : out std_logic_vector(1 downto 0);
addrphaseinvert : out std_logic;
enadqscycledelaysetting : out std_logic_vector(2 downto 0);
enadqsphasetransferreg : out std_logic;
dqoutputzerophasesetting : out std_logic_vector(1 downto 0);
postamblezerophasesetting : out std_logic_vector(2 downto 0);
dividerioehratephaseinvert : out std_logic;
dqsdisablendelaysetting : out std_logic_vector(7 downto 0);
addrpowerdown : out std_logic;
dqsoutputpowerdown : out std_logic;
dqoutputpowerdown : out std_logic;
resyncinputpowerdown : out std_logic;
dqs2xoutputpowerdown : out std_logic;
ck2xoutputpowerdown : out std_logic;
dq2xoutputpowerdown : out std_logic;
postamblepowerdown : out std_logic
);
end component;
begin
inst : stratixv_dqs_config_encrypted
generic map (
lpm_type => lpm_type
)
port map (
datain => datain,
clk => clk,
ena => ena,
update => update,
dqsbusoutdelaysetting => dqsbusoutdelaysetting,
dqsbusoutdelaysetting2 => dqsbusoutdelaysetting2,
dqsinputphasesetting => dqsinputphasesetting,
dqsoutputphasesetting => dqsoutputphasesetting,
dqoutputphasesetting => dqoutputphasesetting,
resyncinputphasesetting => resyncinputphasesetting,
enaoctcycledelaysetting => enaoctcycledelaysetting,
enainputcycledelaysetting => enainputcycledelaysetting,
enaoutputcycledelaysetting => enaoutputcycledelaysetting,
dqsenabledelaysetting => dqsenabledelaysetting,
octdelaysetting1 => octdelaysetting1,
octdelaysetting2 => octdelaysetting2,
enadqsenablephasetransferreg => enadqsenablephasetransferreg,
enaoctphasetransferreg => enaoctphasetransferreg,
enaoutputphasetransferreg => enaoutputphasetransferreg,
enainputphasetransferreg => enainputphasetransferreg,
resyncinputphaseinvert => resyncinputphaseinvert,
dqoutputphaseinvert => dqoutputphaseinvert,
dqsoutputphaseinvert => dqsoutputphaseinvert,
dataout => dataout,
resyncinputzerophaseinvert => resyncinputzerophaseinvert,
dqs2xoutputphasesetting => dqs2xoutputphasesetting,
dqs2xoutputphaseinvert => dqs2xoutputphaseinvert,
ck2xoutputphasesetting => ck2xoutputphasesetting,
ck2xoutputphaseinvert => ck2xoutputphaseinvert,
dq2xoutputphasesetting => dq2xoutputphasesetting,
dq2xoutputphaseinvert => dq2xoutputphaseinvert,
postamblephasesetting => postamblephasesetting,
postamblephaseinvert => postamblephaseinvert,
dividerphaseinvert => dividerphaseinvert,
addrphasesetting => addrphasesetting,
addrphaseinvert => addrphaseinvert,
enadqscycledelaysetting => enadqscycledelaysetting,
enadqsphasetransferreg => enadqsphasetransferreg,
dqoutputzerophasesetting => dqoutputzerophasesetting,
postamblezerophasesetting => postamblezerophasesetting,
dividerioehratephaseinvert => dividerioehratephaseinvert,
dqsdisablendelaysetting => dqsdisablendelaysetting,
addrpowerdown => addrpowerdown,
dqsoutputpowerdown => dqsoutputpowerdown,
dqoutputpowerdown => dqoutputpowerdown,
resyncinputpowerdown => resyncinputpowerdown,
dqs2xoutputpowerdown => dqs2xoutputpowerdown,
ck2xoutputpowerdown => ck2xoutputpowerdown,
dq2xoutputpowerdown => dq2xoutputpowerdown,
postamblepowerdown => postamblepowerdown
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_dqs_delay_chain is
generic (
dqs_input_frequency : string := "unused";
dqs_phase_shift : integer := 0;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
use_alternate_input_for_first_stage_delayctrl : string := "false";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
test_enable : string := "false"
);
port (
dqsin : in std_logic := '0';
dqsenable : in std_logic := '1';
dqsdisablen : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
dqsupdateen : in std_logic := '1';
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
testin : in std_logic := '0';
dffin : out std_logic;
dqsbusout : out std_logic
);
end stratixv_dqs_delay_chain;
architecture behavior of stratixv_dqs_delay_chain is
component stratixv_dqs_delay_chain_encrypted
generic (
dqs_input_frequency : string := "unused";
dqs_phase_shift : integer := 0;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
use_alternate_input_for_first_stage_delayctrl : string := "false";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
test_enable : string := "false"
);
port (
dqsin : in std_logic := '0';
dqsenable : in std_logic := '1';
dqsdisablen : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
dqsupdateen : in std_logic := '1';
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
testin : in std_logic := '0';
dffin : out std_logic;
dqsbusout : out std_logic
);
end component;
begin
inst : stratixv_dqs_delay_chain_encrypted
generic map (
dqs_input_frequency => dqs_input_frequency,
dqs_phase_shift => dqs_phase_shift,
use_phasectrlin => use_phasectrlin,
phase_setting => phase_setting,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
use_alternate_input_for_first_stage_delayctrl => use_alternate_input_for_first_stage_delayctrl,
sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment,
test_enable => test_enable
)
port map (
dqsin => dqsin,
dqsenable => dqsenable,
dqsdisablen => dqsdisablen,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
phasectrlin => phasectrlin,
testin => testin,
dffin => dffin,
dqsbusout => dqsbusout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_dqs_enable_ctrl is
generic (
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
sim_dqsenablein_pre_delay : integer := 0;
bypass_output_register : string := "false";
ext_delay_chain_setting : integer := 0;
int_delay_chain_setting : integer := 0;
use_enable_tracking : string := "false";
use_on_die_variation_tracking : string := "false";
use_pvt_compensation : string := "false"
);
port (
dqsenablein : in std_logic := '1';
zerophaseclk : in std_logic := '1';
enaphasetransferreg : in std_logic := '0';
levelingclk : in std_logic := '1';
dffin : out std_logic;
dffphasetransfer : out std_logic;
dffextenddqsenable : out std_logic;
dqsenableout : out std_logic;
prevphasevalid : out std_logic;
enatrackingreset : in std_logic := '0';
enatrackingevent : out std_logic;
enatrackingupdwn : out std_logic;
nextphasealign : out std_logic;
prevphasealign : out std_logic;
prevphasedelaysetting : out std_logic_vector(5 downto 0)
);
end stratixv_dqs_enable_ctrl;
architecture behavior of stratixv_dqs_enable_ctrl is
component stratixv_dqs_enable_ctrl_encrypted
generic (
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
sim_dqsenablein_pre_delay : integer := 0;
bypass_output_register : string := "false";
ext_delay_chain_setting : integer := 0;
int_delay_chain_setting : integer := 0;
use_enable_tracking : string := "false";
use_on_die_variation_tracking : string := "false";
use_pvt_compensation : string := "false"
);
port (
dqsenablein : in std_logic := '1';
zerophaseclk : in std_logic := '1';
enaphasetransferreg : in std_logic := '0';
levelingclk : in std_logic := '1';
dffin : out std_logic;
dffphasetransfer : out std_logic;
dffextenddqsenable : out std_logic;
dqsenableout : out std_logic;
prevphasevalid : out std_logic;
enatrackingreset : in std_logic := '0';
enatrackingevent : out std_logic;
enatrackingupdwn : out std_logic;
nextphasealign : out std_logic;
prevphasealign : out std_logic;
prevphasedelaysetting : out std_logic_vector(5 downto 0)
);
end component;
begin
inst : stratixv_dqs_enable_ctrl_encrypted
generic map (
delay_dqs_enable_by_half_cycle => delay_dqs_enable_by_half_cycle,
add_phase_transfer_reg => add_phase_transfer_reg,
sim_dqsenablein_pre_delay => sim_dqsenablein_pre_delay,
bypass_output_register => bypass_output_register,
ext_delay_chain_setting => ext_delay_chain_setting,
int_delay_chain_setting => int_delay_chain_setting,
use_enable_tracking => use_enable_tracking,
use_on_die_variation_tracking => use_on_die_variation_tracking,
use_pvt_compensation => use_pvt_compensation
)
port map (
dqsenablein => dqsenablein,
zerophaseclk => zerophaseclk,
enaphasetransferreg => enaphasetransferreg,
levelingclk => levelingclk,
dffin => dffin,
dffphasetransfer => dffphasetransfer,
dffextenddqsenable => dffextenddqsenable,
dqsenableout => dqsenableout,
prevphasevalid => prevphasevalid,
enatrackingreset => enatrackingreset,
enatrackingevent => enatrackingevent,
enatrackingupdwn => enatrackingupdwn,
nextphasealign => nextphasealign,
prevphasealign => prevphasealign,
prevphasedelaysetting => prevphasedelaysetting
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_duty_cycle_adjustment is
generic (
duty_cycle_delay_mode : string := "none";
lpm_type : string := "stratixv_duty_cycle_adjustment"
);
port (
clkin : in std_logic := '0';
delaymode : in std_logic := '0';
delayctrlin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
clkout : out std_logic
);
end stratixv_duty_cycle_adjustment;
architecture behavior of stratixv_duty_cycle_adjustment is
component stratixv_duty_cycle_adjustment_encrypted
generic (
duty_cycle_delay_mode : string := "none";
lpm_type : string := "stratixv_duty_cycle_adjustment"
);
port (
clkin : in std_logic := '0';
delaymode : in std_logic := '0';
delayctrlin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
clkout : out std_logic
);
end component;
begin
inst : stratixv_duty_cycle_adjustment_encrypted
generic map (
duty_cycle_delay_mode => duty_cycle_delay_mode,
lpm_type => lpm_type
)
port map (
clkin => clkin,
delaymode => delaymode,
delayctrlin => delayctrlin,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_fractional_pll is
generic (
lpm_type : string := "stratixv_fractional_pll";
output_clock_frequency : string := "0 ps";
pll_chg_pump_crnt : integer := 10;
pll_clkin_cmp_path : string := "nrm";
pll_cmp_buf_dly : string := "0 ps";
pll_dnm_phsf_cnt_sel : string := "all_c";
pll_dsm_k : integer := 1;
pll_dsm_out_sel : string := "cram";
pll_enable : string := "true";
pll_fbclk_cmp_path : string := "nrm";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_lock_fltr_cfg : integer := 0;
pll_lock_fltr_test : string := "false";
pll_lock_win : string := "nrm";
pll_lp_fltr_cs : integer := 0;
pll_lp_fltr_rp : integer := 20;
pll_m_cnt_bypass_en : string := "false";
pll_m_cnt_coarse_dly : string := "0 ps";
pll_m_cnt_fine_dly : string := "0 ps";
pll_m_cnt_hi_div : integer := 0;
pll_m_cnt_in_src : string := "ph_mux_clk";
pll_m_cnt_lo_div : integer := 0;
pll_m_cnt_odd_div_duty_en : string := "false";
pll_m_cnt_ph_mux_prst : integer := 0;
pll_m_cnt_prst : integer := 0;
pll_mmd_div_sel : integer := 2;
pll_n_cnt_bypass_en : string := "false";
pll_n_cnt_coarse_dly : string := "0 ps";
pll_n_cnt_fine_dly : string := "0 ps";
pll_n_cnt_hi_div : integer := 1;
pll_n_cnt_lo_div : integer := 1;
pll_n_cnt_odd_div_duty_en : string := "false";
pll_p_cnt_set : integer := 1;
pll_pfd_pulse_width_min : string := "0 ps";
pll_ref_vco_over : integer := 1300;
pll_ref_vco_under : integer := 500;
pll_s_cnt_set : integer := 1;
pll_slf_rst : string := "true";
pll_tclk_mux_en : string := "false";
pll_unlock_fltr_cfg : integer := 0;
pll_vco_div : integer := 600;
pll_vco_ph0_en : string := "false";
pll_vco_ph1_en : string := "false";
pll_vco_ph2_en : string := "false";
pll_vco_ph3_en : string := "false";
pll_vco_ph4_en : string := "false";
pll_vco_ph5_en : string := "false";
pll_vco_ph6_en : string := "false";
pll_vco_ph7_en : string := "false";
pll_vco_rng_dt : string := "dis_en";
pll_vt_bp_reg_div : integer := 1700;
pll_vt_out : integer := 1650;
pll_vt_rg_mode : string := "nrm_mode";
pll_vt_test : string := "false";
reference_clock_frequency : string := "0 ps"
);
port (
analogtest : in std_logic;
cntnen : in std_logic;
coreclkfb : in std_logic;
crcm : in std_logic_vector(1 downto 0);
crcp : in std_logic_vector(2 downto 0);
crdltasgma : in std_logic_vector(23 downto 0);
crdsmen : in std_logic;
crfbclkdly : in std_logic_vector(2 downto 0);
crfbclksel : in std_logic_vector(1 downto 0);
crlckf : in std_logic_vector(11 downto 0);
crlcktest : in std_logic;
crlfc : in std_logic_vector(1 downto 0);
crlfr : in std_logic_vector(4 downto 0);
crlfrd : in std_logic_vector(5 downto 0);
crlock : in std_logic_vector(3 downto 0);
crmdirectfb : in std_logic;
crmhi : in std_logic_vector(8 downto 0);
crmlo : in std_logic_vector(8 downto 0);
crmmddiv : in std_logic_vector(1 downto 0);
crmprst : in std_logic_vector(10 downto 0);
crmrdly : in std_logic_vector(4 downto 0);
crmsel : in std_logic_vector(1 downto 0);
crnhi : in std_logic_vector(8 downto 0);
crnlckf : in std_logic_vector(2 downto 0);
crnlo : in std_logic_vector(8 downto 0);
crnrdly : in std_logic_vector(4 downto 0);
crpcnt : in std_logic_vector(3 downto 0);
crpfdpulsewidth : in std_logic;
crrefclkdly : in std_logic_vector(2 downto 0);
crrefclksel : in std_logic_vector(1 downto 0);
crscnt : in std_logic_vector(3 downto 0);
crselfrst : in std_logic_vector(1 downto 0);
crtclk : in std_logic_vector(1 downto 0);
crtest : in std_logic_vector(1 downto 0);
crvcop : in std_logic_vector(7 downto 0);
crvcophbyps : in std_logic;
crvr : in std_logic_vector(6 downto 0);
enpfd : in std_logic;
lfreset : in std_logic;
lvdsfbin : in std_logic;
niotricntr : in std_logic;
pdbvr : in std_logic;
pfden : in std_logic;
pllpd : in std_logic;
refclkin : in std_logic;
reset0 : in std_logic;
roc : in std_logic;
shift : in std_logic;
shiftdonein : in std_logic;
shiften : in std_logic;
up : in std_logic;
vcopen : in std_logic;
zdbinput : in std_logic;
fbclk : out std_logic;
fblvdsout : out std_logic;
lock : out std_logic;
mcntout : out std_logic;
selfrst : out std_logic;
shiftdoneout : out std_logic;
tclk : out std_logic;
vcoover : out std_logic;
vcoph : out std_logic_vector(7 downto 0);
vcounder : out std_logic
);
end stratixv_fractional_pll;
architecture behavior of stratixv_fractional_pll is
component stratixv_fractional_pll_encrypted
generic (
lpm_type : string := "stratixv_fractional_pll";
output_clock_frequency : string := "0 ps";
pll_chg_pump_crnt : integer := 10;
pll_clkin_cmp_path : string := "nrm";
pll_cmp_buf_dly : string := "0 ps";
pll_dnm_phsf_cnt_sel : string := "all_c";
pll_dsm_k : integer := 1;
pll_dsm_out_sel : string := "cram";
pll_enable : string := "true";
pll_fbclk_cmp_path : string := "nrm";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_lock_fltr_cfg : integer := 0;
pll_lock_fltr_test : string := "false";
pll_lock_win : string := "nrm";
pll_lp_fltr_cs : integer := 0;
pll_lp_fltr_rp : integer := 20;
pll_m_cnt_bypass_en : string := "false";
pll_m_cnt_coarse_dly : string := "0 ps";
pll_m_cnt_fine_dly : string := "0 ps";
pll_m_cnt_hi_div : integer := 0;
pll_m_cnt_in_src : string := "ph_mux_clk";
pll_m_cnt_lo_div : integer := 0;
pll_m_cnt_odd_div_duty_en : string := "false";
pll_m_cnt_ph_mux_prst : integer := 0;
pll_m_cnt_prst : integer := 0;
pll_mmd_div_sel : integer := 2;
pll_n_cnt_bypass_en : string := "false";
pll_n_cnt_coarse_dly : string := "0 ps";
pll_n_cnt_fine_dly : string := "0 ps";
pll_n_cnt_hi_div : integer := 1;
pll_n_cnt_lo_div : integer := 1;
pll_n_cnt_odd_div_duty_en : string := "false";
pll_p_cnt_set : integer := 1;
pll_pfd_pulse_width_min : string := "0 ps";
pll_ref_vco_over : integer := 1300;
pll_ref_vco_under : integer := 500;
pll_s_cnt_set : integer := 1;
pll_slf_rst : string := "true";
pll_tclk_mux_en : string := "false";
pll_unlock_fltr_cfg : integer := 0;
pll_vco_div : integer := 600;
pll_vco_ph0_en : string := "false";
pll_vco_ph1_en : string := "false";
pll_vco_ph2_en : string := "false";
pll_vco_ph3_en : string := "false";
pll_vco_ph4_en : string := "false";
pll_vco_ph5_en : string := "false";
pll_vco_ph6_en : string := "false";
pll_vco_ph7_en : string := "false";
pll_vco_rng_dt : string := "dis_en";
pll_vt_bp_reg_div : integer := 1700;
pll_vt_out : integer := 1650;
pll_vt_rg_mode : string := "nrm_mode";
pll_vt_test : string := "false";
reference_clock_frequency : string := "0 ps"
);
port (
analogtest : in std_logic;
cntnen : in std_logic;
coreclkfb : in std_logic;
crcm : in std_logic_vector(1 downto 0);
crcp : in std_logic_vector(2 downto 0);
crdltasgma : in std_logic_vector(23 downto 0);
crdsmen : in std_logic;
crfbclkdly : in std_logic_vector(2 downto 0);
crfbclksel : in std_logic_vector(1 downto 0);
crlckf : in std_logic_vector(11 downto 0);
crlcktest : in std_logic;
crlfc : in std_logic_vector(1 downto 0);
crlfr : in std_logic_vector(4 downto 0);
crlfrd : in std_logic_vector(5 downto 0);
crlock : in std_logic_vector(3 downto 0);
crmdirectfb : in std_logic;
crmhi : in std_logic_vector(8 downto 0);
crmlo : in std_logic_vector(8 downto 0);
crmmddiv : in std_logic_vector(1 downto 0);
crmprst : in std_logic_vector(10 downto 0);
crmrdly : in std_logic_vector(4 downto 0);
crmsel : in std_logic_vector(1 downto 0);
crnhi : in std_logic_vector(8 downto 0);
crnlckf : in std_logic_vector(2 downto 0);
crnlo : in std_logic_vector(8 downto 0);
crnrdly : in std_logic_vector(4 downto 0);
crpcnt : in std_logic_vector(3 downto 0);
crpfdpulsewidth : in std_logic;
crrefclkdly : in std_logic_vector(2 downto 0);
crrefclksel : in std_logic_vector(1 downto 0);
crscnt : in std_logic_vector(3 downto 0);
crselfrst : in std_logic_vector(1 downto 0);
crtclk : in std_logic_vector(1 downto 0);
crtest : in std_logic_vector(1 downto 0);
crvcop : in std_logic_vector(7 downto 0);
crvcophbyps : in std_logic;
crvr : in std_logic_vector(6 downto 0);
enpfd : in std_logic;
lfreset : in std_logic;
lvdsfbin : in std_logic;
niotricntr : in std_logic;
pdbvr : in std_logic;
pfden : in std_logic;
pllpd : in std_logic;
refclkin : in std_logic;
reset0 : in std_logic;
roc : in std_logic;
shift : in std_logic;
shiftdonein : in std_logic;
shiften : in std_logic;
up : in std_logic;
vcopen : in std_logic;
zdbinput : in std_logic;
fbclk : out std_logic;
fblvdsout : out std_logic;
lock : out std_logic;
mcntout : out std_logic;
selfrst : out std_logic;
shiftdoneout : out std_logic;
tclk : out std_logic;
vcoover : out std_logic;
vcoph : out std_logic_vector(7 downto 0);
vcounder : out std_logic
);
end component;
begin
inst : stratixv_fractional_pll_encrypted
generic map (
lpm_type => lpm_type,
output_clock_frequency => output_clock_frequency,
pll_chg_pump_crnt => pll_chg_pump_crnt,
pll_clkin_cmp_path => pll_clkin_cmp_path,
pll_cmp_buf_dly => pll_cmp_buf_dly,
pll_dnm_phsf_cnt_sel => pll_dnm_phsf_cnt_sel,
pll_dsm_k => pll_dsm_k,
pll_dsm_out_sel => pll_dsm_out_sel,
pll_enable => pll_enable,
pll_fbclk_cmp_path => pll_fbclk_cmp_path,
pll_fbclk_mux_1 => pll_fbclk_mux_1,
pll_fbclk_mux_2 => pll_fbclk_mux_2,
pll_lock_fltr_cfg => pll_lock_fltr_cfg,
pll_lock_fltr_test => pll_lock_fltr_test,
pll_lock_win => pll_lock_win,
pll_lp_fltr_cs => pll_lp_fltr_cs,
pll_lp_fltr_rp => pll_lp_fltr_rp,
pll_m_cnt_bypass_en => pll_m_cnt_bypass_en,
pll_m_cnt_coarse_dly => pll_m_cnt_coarse_dly,
pll_m_cnt_fine_dly => pll_m_cnt_fine_dly,
pll_m_cnt_hi_div => pll_m_cnt_hi_div,
pll_m_cnt_in_src => pll_m_cnt_in_src,
pll_m_cnt_lo_div => pll_m_cnt_lo_div,
pll_m_cnt_odd_div_duty_en => pll_m_cnt_odd_div_duty_en,
pll_m_cnt_ph_mux_prst => pll_m_cnt_ph_mux_prst,
pll_m_cnt_prst => pll_m_cnt_prst,
pll_mmd_div_sel => pll_mmd_div_sel,
pll_n_cnt_bypass_en => pll_n_cnt_bypass_en,
pll_n_cnt_coarse_dly => pll_n_cnt_coarse_dly,
pll_n_cnt_fine_dly => pll_n_cnt_fine_dly,
pll_n_cnt_hi_div => pll_n_cnt_hi_div,
pll_n_cnt_lo_div => pll_n_cnt_lo_div,
pll_n_cnt_odd_div_duty_en => pll_n_cnt_odd_div_duty_en,
pll_p_cnt_set => pll_p_cnt_set,
pll_pfd_pulse_width_min => pll_pfd_pulse_width_min,
pll_ref_vco_over => pll_ref_vco_over,
pll_ref_vco_under => pll_ref_vco_under,
pll_s_cnt_set => pll_s_cnt_set,
pll_slf_rst => pll_slf_rst,
pll_tclk_mux_en => pll_tclk_mux_en,
pll_unlock_fltr_cfg => pll_unlock_fltr_cfg,
pll_vco_div => pll_vco_div,
pll_vco_ph0_en => pll_vco_ph0_en,
pll_vco_ph1_en => pll_vco_ph1_en,
pll_vco_ph2_en => pll_vco_ph2_en,
pll_vco_ph3_en => pll_vco_ph3_en,
pll_vco_ph4_en => pll_vco_ph4_en,
pll_vco_ph5_en => pll_vco_ph5_en,
pll_vco_ph6_en => pll_vco_ph6_en,
pll_vco_ph7_en => pll_vco_ph7_en,
pll_vco_rng_dt => pll_vco_rng_dt,
pll_vt_bp_reg_div => pll_vt_bp_reg_div,
pll_vt_out => pll_vt_out,
pll_vt_rg_mode => pll_vt_rg_mode,
pll_vt_test => pll_vt_test,
reference_clock_frequency => reference_clock_frequency
)
port map (
analogtest => analogtest,
cntnen => cntnen,
coreclkfb => coreclkfb,
crcm => crcm,
crcp => crcp,
crdltasgma => crdltasgma,
crdsmen => crdsmen,
crfbclkdly => crfbclkdly,
crfbclksel => crfbclksel,
crlckf => crlckf,
crlcktest => crlcktest,
crlfc => crlfc,
crlfr => crlfr,
crlfrd => crlfrd,
crlock => crlock,
crmdirectfb => crmdirectfb,
crmhi => crmhi,
crmlo => crmlo,
crmmddiv => crmmddiv,
crmprst => crmprst,
crmrdly => crmrdly,
crmsel => crmsel,
crnhi => crnhi,
crnlckf => crnlckf,
crnlo => crnlo,
crnrdly => crnrdly,
crpcnt => crpcnt,
crpfdpulsewidth => crpfdpulsewidth,
crrefclkdly => crrefclkdly,
crrefclksel => crrefclksel,
crscnt => crscnt,
crselfrst => crselfrst,
crtclk => crtclk,
crtest => crtest,
crvcop => crvcop,
crvcophbyps => crvcophbyps,
crvr => crvr,
enpfd => enpfd,
lfreset => lfreset,
lvdsfbin => lvdsfbin,
niotricntr => niotricntr,
pdbvr => pdbvr,
pfden => pfden,
pllpd => pllpd,
refclkin => refclkin,
reset0 => reset0,
roc => roc,
shift => shift,
shiftdonein => shiftdonein,
shiften => shiften,
up => up,
vcopen => vcopen,
zdbinput => zdbinput,
fbclk => fbclk,
fblvdsout => fblvdsout,
lock => lock,
mcntout => mcntout,
selfrst => selfrst,
shiftdoneout => shiftdoneout,
tclk => tclk,
vcoover => vcoover,
vcoph => vcoph,
vcounder => vcounder
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_half_rate_input is
generic (
power_up : string := "low";
async_mode : string := "no_reset";
use_dataoutbypass : string := "false"
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '1');
directin : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
dataoutbypass : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0);
dffin : out std_logic_vector(1 downto 0)
);
end stratixv_half_rate_input;
architecture behavior of stratixv_half_rate_input is
component stratixv_half_rate_input_encrypted
generic (
power_up : string := "low";
async_mode : string := "no_reset";
use_dataoutbypass : string := "false"
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '1');
directin : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
dataoutbypass : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0);
dffin : out std_logic_vector(1 downto 0)
);
end component;
begin
inst : stratixv_half_rate_input_encrypted
generic map (
power_up => power_up,
async_mode => async_mode,
use_dataoutbypass => use_dataoutbypass
)
port map (
datain => datain,
directin => directin,
clk => clk,
areset => areset,
dataoutbypass => dataoutbypass,
dataout => dataout,
dffin => dffin
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_input_phase_alignment is
generic (
power_up : string := "low";
async_mode : string := "no_reset";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
lpm_type : string := "stratixv_input_phase_alignment"
);
port (
datain : in std_logic := '1';
levelingclk : in std_logic := '0';
zerophaseclk : in std_logic := '0';
areset : in std_logic := '0';
enainputcycledelay : in std_logic := '0';
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dffphasetransfer : out std_logic
);
end stratixv_input_phase_alignment;
architecture behavior of stratixv_input_phase_alignment is
component stratixv_input_phase_alignment_encrypted
generic (
power_up : string := "low";
async_mode : string := "no_reset";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
lpm_type : string := "stratixv_input_phase_alignment"
);
port (
datain : in std_logic := '1';
levelingclk : in std_logic := '0';
zerophaseclk : in std_logic := '0';
areset : in std_logic := '0';
enainputcycledelay : in std_logic := '0';
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dffphasetransfer : out std_logic
);
end component;
begin
inst : stratixv_input_phase_alignment_encrypted
generic map (
power_up => power_up,
async_mode => async_mode,
add_input_cycle_delay => add_input_cycle_delay,
bypass_output_register => bypass_output_register,
add_phase_transfer_reg => add_phase_transfer_reg,
lpm_type => lpm_type
)
port map (
datain => datain,
levelingclk => levelingclk,
zerophaseclk => zerophaseclk,
areset => areset,
enainputcycledelay => enainputcycledelay,
enaphasetransferreg => enaphasetransferreg,
dataout => dataout,
dffin => dffin,
dff1t => dff1t,
dffphasetransfer => dffphasetransfer
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_io_clock_divider is
generic (
power_up : string := "low";
invert_phase : string := "false";
use_masterin : string := "false";
lpm_type : string := "stratixv_io_clock_divider"
);
port (
clk : in std_logic := '0';
phaseinvertctrl : in std_logic := '0';
masterin : in std_logic := '0';
clkout : out std_logic;
slaveout : out std_logic
);
end stratixv_io_clock_divider;
architecture behavior of stratixv_io_clock_divider is
component stratixv_io_clock_divider_encrypted
generic (
power_up : string := "low";
invert_phase : string := "false";
use_masterin : string := "false";
lpm_type : string := "stratixv_io_clock_divider"
);
port (
clk : in std_logic := '0';
phaseinvertctrl : in std_logic := '0';
masterin : in std_logic := '0';
clkout : out std_logic;
slaveout : out std_logic
);
end component;
begin
inst : stratixv_io_clock_divider_encrypted
generic map (
power_up => power_up,
invert_phase => invert_phase,
use_masterin => use_masterin,
lpm_type => lpm_type
)
port map (
clk => clk,
phaseinvertctrl => phaseinvertctrl,
masterin => masterin,
clkout => clkout,
slaveout => slaveout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_io_config is
generic (
lpm_type : string := "stratixv_io_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
update : in std_logic := '0';
outputdelaysetting1 : out std_logic_vector(5 downto 0);
outputdelaysetting2 : out std_logic_vector(5 downto 0);
padtoinputregisterdelaysetting : out std_logic_vector(5 downto 0);
padtoinputregisterrisefalldelaysetting : out std_logic_vector(5 downto 0);
inputclkdelaysetting : out std_logic_vector(1 downto 0);
inputclkndelaysetting : out std_logic_vector(1 downto 0);
dutycycledelaymode : out std_logic;
dutycycledelaysetting : out std_logic_vector(3 downto 0);
dataout : out std_logic
);
end stratixv_io_config;
architecture behavior of stratixv_io_config is
component stratixv_io_config_encrypted
generic (
lpm_type : string := "stratixv_io_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
update : in std_logic := '0';
outputdelaysetting1 : out std_logic_vector(5 downto 0);
outputdelaysetting2 : out std_logic_vector(5 downto 0);
padtoinputregisterdelaysetting : out std_logic_vector(5 downto 0);
padtoinputregisterrisefalldelaysetting : out std_logic_vector(5 downto 0);
inputclkdelaysetting : out std_logic_vector(1 downto 0);
inputclkndelaysetting : out std_logic_vector(1 downto 0);
dutycycledelaymode : out std_logic;
dutycycledelaysetting : out std_logic_vector(3 downto 0);
dataout : out std_logic
);
end component;
begin
inst : stratixv_io_config_encrypted
generic map (
lpm_type => lpm_type
)
port map (
datain => datain,
clk => clk,
ena => ena,
update => update,
outputdelaysetting1 => outputdelaysetting1,
outputdelaysetting2 => outputdelaysetting2,
padtoinputregisterdelaysetting => padtoinputregisterdelaysetting,
padtoinputregisterrisefalldelaysetting => padtoinputregisterrisefalldelaysetting,
inputclkdelaysetting => inputclkdelaysetting,
inputclkndelaysetting => inputclkndelaysetting,
dutycycledelaymode => dutycycledelaymode,
dutycycledelaysetting => dutycycledelaysetting,
dataout => dataout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_leveling_delay_chain is
generic (
physical_clock_source : string := "dqs";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10
);
port (
clkin : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
clkout : out std_logic_vector(3 downto 0)
);
end stratixv_leveling_delay_chain;
architecture behavior of stratixv_leveling_delay_chain is
component stratixv_leveling_delay_chain_encrypted
generic (
physical_clock_source : string := "dqs";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10
);
port (
clkin : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
clkout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_leveling_delay_chain_encrypted
generic map (
physical_clock_source => physical_clock_source,
sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
port map (
clkin => clkin,
delayctrlin => delayctrlin,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_lvds_rx is
generic (
data_align_rollover : integer := 2;
enable_dpa : string := "false";
lose_lock_on_one_change : string := "false";
reset_fifo_at_first_lock : string := "true";
align_to_rising_edge_only : string := "true";
use_serial_feedback_input : string := "off";
dpa_debug : string := "false";
x_on_bitslip : string := "true";
enable_soft_cdr : string := "false";
dpa_clock_output_phase_shift : integer := 0;
enable_dpa_initial_phase_selection : string := "false";
dpa_initial_phase_value : integer := 0;
enable_dpa_align_to_rising_edge_only : string := "false";
net_ppm_variation : integer := 0;
is_negative_ppm_drift : string := "false";
rx_input_path_delay_engineering_bits : integer := 2;
lpm_type : string := "stratixv_lvds_rx";
data_width : integer := 10
);
port (
clock0 : in std_logic := '0';
datain : in std_logic := '0';
enable0 : in std_logic := '0';
dpareset : in std_logic := '0';
dpahold : in std_logic := '0';
dpaswitch : in std_logic := '0';
fiforeset : in std_logic := '0';
bitslip : in std_logic := '0';
bitslipreset : in std_logic := '0';
serialfbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic_vector(data_width-1 downto 0);
dpalock : out std_logic;
bitslipmax : out std_logic;
serialdataout : out std_logic;
postdpaserialdataout : out std_logic;
divfwdclk : out std_logic;
dpaclkout : out std_logic;
observableout : out std_logic_vector(3 downto 0)
);
end stratixv_lvds_rx;
architecture behavior of stratixv_lvds_rx is
component stratixv_lvds_rx_encrypted
generic (
data_align_rollover : integer := 2;
enable_dpa : string := "false";
lose_lock_on_one_change : string := "false";
reset_fifo_at_first_lock : string := "true";
align_to_rising_edge_only : string := "true";
use_serial_feedback_input : string := "off";
dpa_debug : string := "false";
x_on_bitslip : string := "true";
enable_soft_cdr : string := "false";
dpa_clock_output_phase_shift : integer := 0;
enable_dpa_initial_phase_selection : string := "false";
dpa_initial_phase_value : integer := 0;
enable_dpa_align_to_rising_edge_only : string := "false";
net_ppm_variation : integer := 0;
is_negative_ppm_drift : string := "false";
rx_input_path_delay_engineering_bits : integer := 2;
lpm_type : string := "stratixv_lvds_rx";
data_width : integer := 10
);
port (
clock0 : in std_logic := '0';
datain : in std_logic := '0';
enable0 : in std_logic := '0';
dpareset : in std_logic := '0';
dpahold : in std_logic := '0';
dpaswitch : in std_logic := '0';
fiforeset : in std_logic := '0';
bitslip : in std_logic := '0';
bitslipreset : in std_logic := '0';
serialfbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic_vector(data_width-1 downto 0);
dpalock : out std_logic;
bitslipmax : out std_logic;
serialdataout : out std_logic;
postdpaserialdataout : out std_logic;
divfwdclk : out std_logic;
dpaclkout : out std_logic;
observableout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_lvds_rx_encrypted
generic map (
data_align_rollover => data_align_rollover,
enable_dpa => enable_dpa,
lose_lock_on_one_change => lose_lock_on_one_change,
reset_fifo_at_first_lock => reset_fifo_at_first_lock,
align_to_rising_edge_only => align_to_rising_edge_only,
use_serial_feedback_input => use_serial_feedback_input,
dpa_debug => dpa_debug,
x_on_bitslip => x_on_bitslip,
enable_soft_cdr => enable_soft_cdr,
dpa_clock_output_phase_shift => dpa_clock_output_phase_shift,
enable_dpa_initial_phase_selection => enable_dpa_initial_phase_selection,
dpa_initial_phase_value => dpa_initial_phase_value,
enable_dpa_align_to_rising_edge_only => enable_dpa_align_to_rising_edge_only,
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
rx_input_path_delay_engineering_bits => rx_input_path_delay_engineering_bits,
lpm_type => lpm_type,
data_width => data_width
)
port map (
clock0 => clock0,
datain => datain,
enable0 => enable0,
dpareset => dpareset,
dpahold => dpahold,
dpaswitch => dpaswitch,
fiforeset => fiforeset,
bitslip => bitslip,
bitslipreset => bitslipreset,
serialfbk => serialfbk,
devclrn => devclrn,
devpor => devpor,
dpaclkin => dpaclkin,
dataout => dataout,
dpalock => dpalock,
bitslipmax => bitslipmax,
serialdataout => serialdataout,
postdpaserialdataout => postdpaserialdataout,
divfwdclk => divfwdclk,
dpaclkout => dpaclkout,
observableout => observableout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_lvds_tx is
generic (
bypass_serializer : string := "false";
invert_clock : string := "false";
use_falling_clock_edge : string := "false";
use_serial_data_input : string := "false";
use_post_dpa_serial_data_input : string := "false";
is_used_as_outclk : string := "false";
tx_output_path_delay_engineering_bits : integer := -1;
enable_dpaclk_to_lvdsout : string := "false";
lpm_type : string := "stratixv_lvds_tx";
data_width : integer := 10
);
port (
datain : in std_logic_vector(data_width-1 downto 0) := (OTHERS => '0');
clock0 : in std_logic := '0';
enable0 : in std_logic := '0';
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic := '0';
dataout : out std_logic;
serialfdbkout : out std_logic;
observableout : out std_logic_vector(2 downto 0)
);
end stratixv_lvds_tx;
architecture behavior of stratixv_lvds_tx is
component stratixv_lvds_tx_encrypted
generic (
bypass_serializer : string := "false";
invert_clock : string := "false";
use_falling_clock_edge : string := "false";
use_serial_data_input : string := "false";
use_post_dpa_serial_data_input : string := "false";
is_used_as_outclk : string := "false";
tx_output_path_delay_engineering_bits : integer := -1;
enable_dpaclk_to_lvdsout : string := "false";
lpm_type : string := "stratixv_lvds_tx";
data_width : integer := 10
);
port (
datain : in std_logic_vector(data_width-1 downto 0) := (OTHERS => '0');
clock0 : in std_logic := '0';
enable0 : in std_logic := '0';
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic := '0';
dataout : out std_logic;
serialfdbkout : out std_logic;
observableout : out std_logic_vector(2 downto 0)
);
end component;
begin
inst : stratixv_lvds_tx_encrypted
generic map (
bypass_serializer => bypass_serializer,
invert_clock => invert_clock,
use_falling_clock_edge => use_falling_clock_edge,
use_serial_data_input => use_serial_data_input,
use_post_dpa_serial_data_input => use_post_dpa_serial_data_input,
is_used_as_outclk => is_used_as_outclk,
tx_output_path_delay_engineering_bits => tx_output_path_delay_engineering_bits,
enable_dpaclk_to_lvdsout => enable_dpaclk_to_lvdsout,
lpm_type => lpm_type,
data_width => data_width
)
port map (
datain => datain,
clock0 => clock0,
enable0 => enable0,
serialdatain => serialdatain,
postdpaserialdatain => postdpaserialdatain,
devclrn => devclrn,
devpor => devpor,
dpaclkin => dpaclkin,
dataout => dataout,
serialfdbkout => serialfdbkout,
observableout => observableout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_output_alignment is
generic (
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
add_phase_transfer_reg : string := "false"
);
port (
datain : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
sreset : in std_logic := '0';
enaoutputcycledelay : in std_logic_vector(2 downto 0) := (OTHERS => '0');
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dff2t : out std_logic;
dffphasetransfer : out std_logic
);
end stratixv_output_alignment;
architecture behavior of stratixv_output_alignment is
component stratixv_output_alignment_encrypted
generic (
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
add_phase_transfer_reg : string := "false"
);
port (
datain : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
sreset : in std_logic := '0';
enaoutputcycledelay : in std_logic_vector(2 downto 0) := (OTHERS => '0');
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dff2t : out std_logic;
dffphasetransfer : out std_logic
);
end component;
begin
inst : stratixv_output_alignment_encrypted
generic map (
power_up => power_up,
async_mode => async_mode,
sync_mode => sync_mode,
add_output_cycle_delay => add_output_cycle_delay,
add_phase_transfer_reg => add_phase_transfer_reg
)
port map (
datain => datain,
clk => clk,
areset => areset,
sreset => sreset,
enaoutputcycledelay => enaoutputcycledelay,
enaphasetransferreg => enaphasetransferreg,
dataout => dataout,
dffin => dffin,
dff1t => dff1t,
dff2t => dff2t,
dffphasetransfer => dffphasetransfer
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_dll_output is
generic (
lpm_type : string := "stratixv_pll_dll_output";
pll_dll_src : string := "c_0_cnt"
);
port (
cclk : in std_logic_vector(17 downto 0);
clkin : in std_logic_vector(3 downto 0);
crsel : in std_logic_vector(4 downto 0);
mout : in std_logic;
clkout : out std_logic
);
end stratixv_pll_dll_output;
architecture behavior of stratixv_pll_dll_output is
component stratixv_pll_dll_output_encrypted
generic (
lpm_type : string := "stratixv_pll_dll_output";
pll_dll_src : string := "c_0_cnt"
);
port (
cclk : in std_logic_vector(17 downto 0);
clkin : in std_logic_vector(3 downto 0);
crsel : in std_logic_vector(4 downto 0);
mout : in std_logic;
clkout : out std_logic
);
end component;
begin
inst : stratixv_pll_dll_output_encrypted
generic map (
lpm_type => lpm_type,
pll_dll_src => pll_dll_src
)
port map (
cclk => cclk,
clkin => clkin,
crsel => crsel,
mout => mout,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_dpa_output is
generic (
lpm_type : string := "stratixv_pll_dpa_output";
pll_vcoph_div_en : integer := 1
);
port (
crdpaen : in std_logic_vector(1 downto 0);
pd : in std_logic;
phin : in std_logic_vector(7 downto 0);
phout : out std_logic_vector(7 downto 0)
);
end stratixv_pll_dpa_output;
architecture behavior of stratixv_pll_dpa_output is
component stratixv_pll_dpa_output_encrypted
generic (
lpm_type : string := "stratixv_pll_dpa_output";
pll_vcoph_div_en : integer := 1
);
port (
crdpaen : in std_logic_vector(1 downto 0);
pd : in std_logic;
phin : in std_logic_vector(7 downto 0);
phout : out std_logic_vector(7 downto 0)
);
end component;
begin
inst : stratixv_pll_dpa_output_encrypted
generic map (
lpm_type => lpm_type,
pll_vcoph_div_en => pll_vcoph_div_en
)
port map (
crdpaen => crdpaen,
pd => pd,
phin => phin,
phout => phout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_extclk_output is
generic (
lpm_type : string := "stratixv_pll_extclk_output";
pll_extclk_cnt_src : string := "m0_cnt";
pll_extclk_enable : string := "true";
pll_extclk_invert : string := "false";
pll_extclken_invert : string := "false"
);
port (
cclk : in std_logic_vector(17 downto 0);
clken : in std_logic;
crenable : in std_logic;
crextclkeninv : in std_logic;
crinv : in std_logic;
crsel : in std_logic_vector(4 downto 0);
mcnt : in std_logic;
niotri : in std_logic;
extclk : out std_logic
);
end stratixv_pll_extclk_output;
architecture behavior of stratixv_pll_extclk_output is
component stratixv_pll_extclk_output_encrypted
generic (
lpm_type : string := "stratixv_pll_extclk_output";
pll_extclk_cnt_src : string := "m0_cnt";
pll_extclk_enable : string := "true";
pll_extclk_invert : string := "false";
pll_extclken_invert : string := "false"
);
port (
cclk : in std_logic_vector(17 downto 0);
clken : in std_logic;
crenable : in std_logic;
crextclkeninv : in std_logic;
crinv : in std_logic;
crsel : in std_logic_vector(4 downto 0);
mcnt : in std_logic;
niotri : in std_logic;
extclk : out std_logic
);
end component;
begin
inst : stratixv_pll_extclk_output_encrypted
generic map (
lpm_type => lpm_type,
pll_extclk_cnt_src => pll_extclk_cnt_src,
pll_extclk_enable => pll_extclk_enable,
pll_extclk_invert => pll_extclk_invert,
pll_extclken_invert => pll_extclken_invert
)
port map (
cclk => cclk,
clken => clken,
crenable => crenable,
crextclkeninv => crextclkeninv,
crinv => crinv,
crsel => crsel,
mcnt => mcnt,
niotri => niotri,
extclk => extclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_lvds_output is
generic (
lpm_type : string := "stratixv_pll_lvds_output";
pll_loaden_coarse_dly : string := "0 ps";
pll_loaden_fine_dly : string := "0 ps";
pll_lvdsclk_coarse_dly : string := "0 ps";
pll_lvdsclk_fine_dly : string := "0 ps"
);
port (
ccout : in std_logic_vector(1 downto 0);
crdly : in std_logic_vector(9 downto 0);
loaden : out std_logic;
lvdsclk : out std_logic
);
end stratixv_pll_lvds_output;
architecture behavior of stratixv_pll_lvds_output is
component stratixv_pll_lvds_output_encrypted
generic (
lpm_type : string := "stratixv_pll_lvds_output";
pll_loaden_coarse_dly : string := "0 ps";
pll_loaden_fine_dly : string := "0 ps";
pll_lvdsclk_coarse_dly : string := "0 ps";
pll_lvdsclk_fine_dly : string := "0 ps"
);
port (
ccout : in std_logic_vector(1 downto 0);
crdly : in std_logic_vector(9 downto 0);
loaden : out std_logic;
lvdsclk : out std_logic
);
end component;
begin
inst : stratixv_pll_lvds_output_encrypted
generic map (
lpm_type => lpm_type,
pll_loaden_coarse_dly => pll_loaden_coarse_dly,
pll_loaden_fine_dly => pll_loaden_fine_dly,
pll_lvdsclk_coarse_dly => pll_lvdsclk_coarse_dly,
pll_lvdsclk_fine_dly => pll_lvdsclk_fine_dly
)
port map (
ccout => ccout,
crdly => crdly,
loaden => loaden,
lvdsclk => lvdsclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_output_counter is
generic (
lpm_type : string := "stratixv_pll_output_counter";
duty_cycle : integer := 50;
output_clock_frequency : string := "0 ps";
phase_shift : string := "0 ps";
pll_c_cnt_bypass_en : string := "false";
pll_c_cnt_coarse_dly : string := "0 ps";
pll_c_cnt_fine_dly : string := "0 ps";
pll_c_cnt_hi_div : integer := 3;
pll_c_cnt_in_src : string := "ph_mux_clk";
pll_c_cnt_lo_div : integer := 3;
pll_c_cnt_odd_div_even_duty_en : string := "false";
pll_c_cnt_ph_mux_prst : integer := 0;
pll_c_cnt_prst : integer := 1
);
port (
cascadein : in std_logic;
crhi : in std_logic_vector(8 downto 0);
crlo : in std_logic_vector(8 downto 0);
nen : in std_logic;
shift : in std_logic;
shiftdonei : in std_logic;
shiften : in std_logic;
tclk : in std_logic;
up : in std_logic;
vcoph : in std_logic_vector(7 downto 0);
divclk : out std_logic;
shiftdoneo : out std_logic
);
end stratixv_pll_output_counter;
architecture behavior of stratixv_pll_output_counter is
component stratixv_pll_output_counter_encrypted
generic (
lpm_type : string := "stratixv_pll_output_counter";
duty_cycle : integer := 50;
output_clock_frequency : string := "0 ps";
phase_shift : string := "0 ps";
pll_c_cnt_bypass_en : string := "false";
pll_c_cnt_coarse_dly : string := "0 ps";
pll_c_cnt_fine_dly : string := "0 ps";
pll_c_cnt_hi_div : integer := 3;
pll_c_cnt_in_src : string := "ph_mux_clk";
pll_c_cnt_lo_div : integer := 3;
pll_c_cnt_odd_div_even_duty_en : string := "false";
pll_c_cnt_ph_mux_prst : integer := 0;
pll_c_cnt_prst : integer := 1
);
port (
cascadein : in std_logic;
crhi : in std_logic_vector(8 downto 0);
crlo : in std_logic_vector(8 downto 0);
nen : in std_logic;
shift : in std_logic;
shiftdonei : in std_logic;
shiften : in std_logic;
tclk : in std_logic;
up : in std_logic;
vcoph : in std_logic_vector(7 downto 0);
divclk : out std_logic;
shiftdoneo : out std_logic
);
end component;
begin
inst : stratixv_pll_output_counter_encrypted
generic map (
lpm_type => lpm_type,
duty_cycle => duty_cycle,
output_clock_frequency => output_clock_frequency,
phase_shift => phase_shift,
pll_c_cnt_bypass_en => pll_c_cnt_bypass_en,
pll_c_cnt_coarse_dly => pll_c_cnt_coarse_dly,
pll_c_cnt_fine_dly => pll_c_cnt_fine_dly,
pll_c_cnt_hi_div => pll_c_cnt_hi_div,
pll_c_cnt_in_src => pll_c_cnt_in_src,
pll_c_cnt_lo_div => pll_c_cnt_lo_div,
pll_c_cnt_odd_div_even_duty_en => pll_c_cnt_odd_div_even_duty_en,
pll_c_cnt_ph_mux_prst => pll_c_cnt_ph_mux_prst,
pll_c_cnt_prst => pll_c_cnt_prst
)
port map (
cascadein => cascadein,
crhi => crhi,
crlo => crlo,
nen => nen,
shift => shift,
shiftdonei => shiftdonei,
shiften => shiften,
tclk => tclk,
up => up,
vcoph => vcoph,
divclk => divclk,
shiftdoneo => shiftdoneo
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_reconfig is
generic (
lpm_type : string := "stratixv_pll_reconfig"
);
port (
cntsel0 : in std_logic_vector(4 downto 0);
cr3lo : out std_logic_vector(10 downto 0);
cr3prst : out std_logic_vector(10 downto 0);
cr3sel : out std_logic_vector(1 downto 0);
cr4dly : out std_logic_vector(10 downto 0);
cr4hi : out std_logic_vector(10 downto 0);
cr4lo : out std_logic_vector(10 downto 0);
cr4prst : out std_logic_vector(10 downto 0);
cr4sel : out std_logic_vector(1 downto 0);
cr5dly : out std_logic_vector(10 downto 0);
cr5hi : out std_logic_vector(10 downto 0);
cntsel1 : in std_logic_vector(4 downto 0);
cr5lo : out std_logic_vector(10 downto 0);
cr5prst : out std_logic_vector(10 downto 0);
cr5sel : out std_logic_vector(1 downto 0);
cr6dly : out std_logic_vector(10 downto 0);
cr6hi : out std_logic_vector(10 downto 0);
cr6lo : out std_logic_vector(10 downto 0);
cr6prst : out std_logic_vector(10 downto 0);
cr6sel : out std_logic_vector(1 downto 0);
cr7dly : out std_logic_vector(10 downto 0);
cr7hi : out std_logic_vector(10 downto 0);
dprio0addr : in std_logic_vector(6 downto 0);
cr7lo : out std_logic_vector(10 downto 0);
cr7prst : out std_logic_vector(10 downto 0);
cr7sel : out std_logic_vector(1 downto 0);
cr8dly : out std_logic_vector(10 downto 0);
cr8hi : out std_logic_vector(10 downto 0);
cr8lo : out std_logic_vector(10 downto 0);
cr8prst : out std_logic_vector(10 downto 0);
cr8sel : out std_logic_vector(1 downto 0);
cr9dly : out std_logic_vector(10 downto 0);
cr9hi : out std_logic_vector(10 downto 0);
dprio0byteen : in std_logic_vector(1 downto 0);
cr9lo : out std_logic_vector(10 downto 0);
cr9prst : out std_logic_vector(10 downto 0);
cr9sel : out std_logic_vector(1 downto 0);
crclkenen : out std_logic_vector(3 downto 0);
crdll : out std_logic_vector(9 downto 0);
crext : out std_logic_vector(19 downto 0);
crextclkeninv : out std_logic_vector(3 downto 0);
crextclkinv : out std_logic_vector(10 downto 0);
crfpll0cp : out std_logic_vector(2 downto 0);
crfpll0dpadiv : out std_logic_vector(1 downto 0);
dprio0clk : in std_logic;
crfpll0lckbypass : out std_logic;
crfpll0lfc : out std_logic_vector(1 downto 0);
crfpll0lfr : out std_logic_vector(4 downto 0);
crfpll0lfrd : out std_logic_vector(5 downto 0);
crfpll0lockc : out std_logic_vector(3 downto 0);
crfpll0lockf : out std_logic_vector(11 downto 0);
crfpll0mdirectfb : out std_logic;
crfpll0mdly : out std_logic_vector(4 downto 0);
crfpll0mhi : out std_logic_vector(8 downto 0);
crfpll0mlo : out std_logic_vector(8 downto 0);
dprio0din : in std_logic_vector(15 downto 0);
crfpll0mprst : out std_logic_vector(10 downto 0);
crfpll0msel : out std_logic_vector(1 downto 0);
crfpll0ndly : out std_logic_vector(4 downto 0);
crfpll0nhi : out std_logic_vector(8 downto 0);
crfpll0nlo : out std_logic_vector(8 downto 0);
crfpll0pfdpulsewidth : out std_logic;
crfpll0selfrst : out std_logic_vector(1 downto 0);
crfpll0tclk : out std_logic_vector(1 downto 0);
crfpll0test : out std_logic_vector(1 downto 0);
crfpll0unlockf : out std_logic_vector(2 downto 0);
dprio0mdiodis : in std_logic;
crfpll0vcop : out std_logic_vector(7 downto 0);
crfpll0vcophbyps : out std_logic;
crfpll0vcorangeen : out std_logic;
crfpll0vr : out std_logic_vector(6 downto 0);
crfpll1cp : out std_logic_vector(2 downto 0);
crfpll1dpadiv : out std_logic_vector(1 downto 0);
crfpll1lckbypass : out std_logic;
crfpll1lfc : out std_logic_vector(1 downto 0);
crfpll1lfr : out std_logic_vector(4 downto 0);
crfpll1lfrd : out std_logic_vector(5 downto 0);
dprio0read : in std_logic;
crfpll1lockc : out std_logic_vector(3 downto 0);
crfpll1lockf : out std_logic_vector(11 downto 0);
crfpll1mdirectfb : out std_logic;
crfpll1mdly : out std_logic_vector(4 downto 0);
crfpll1mhi : out std_logic_vector(8 downto 0);
crfpll1mlo : out std_logic_vector(8 downto 0);
crfpll1mprst : out std_logic_vector(10 downto 0);
crfpll1msel : out std_logic_vector(1 downto 0);
crfpll1ndly : out std_logic_vector(4 downto 0);
crfpll1nhi : out std_logic_vector(8 downto 0);
dprio0rstn : in std_logic;
crfpll1nlo : out std_logic_vector(8 downto 0);
crfpll1pfdpulsewidth : out std_logic;
crfpll1selfrst : out std_logic_vector(1 downto 0);
crfpll1tclk : out std_logic_vector(1 downto 0);
crfpll1test : out std_logic_vector(1 downto 0);
crfpll1unlockf : out std_logic_vector(2 downto 0);
crfpll1vcop : out std_logic_vector(7 downto 0);
crfpll1vcophbyps : out std_logic;
crfpll1vcorangeen : out std_logic;
crfpll1vr : out std_logic_vector(6 downto 0);
dprio0sershiftload : in std_logic;
crinv : out std_logic_vector(85 downto 0);
crlvds : out std_logic_vector(39 downto 0);
crphaseshiftsel : out std_logic_vector(17 downto 0);
crvcosel : out std_logic_vector(17 downto 0);
crwrapback : out std_logic;
crwrapbackmux : out std_logic;
dprio0blockselect : out std_logic;
dprio0dout : out std_logic_vector(15 downto 0);
dprio1blockselect : out std_logic;
dprio1dout : out std_logic_vector(15 downto 0);
dprio0write : in std_logic;
fpll0cntnen : out std_logic;
fpll0enpfd : out std_logic;
fpll0lfreset : out std_logic;
fpll0niotricntr : out std_logic;
fpll0pdbvr : out std_logic;
fpll0pllpd : out std_logic;
fpll0reset0 : out std_logic;
fpll0vcopen : out std_logic;
fpll1cntnen : out std_logic;
fpll1enpfd : out std_logic;
dprio1addr : in std_logic_vector(6 downto 0);
fpll1lfreset : out std_logic;
fpll1niotricntr : out std_logic;
fpll1pdbvr : out std_logic;
fpll1pllpd : out std_logic;
fpll1reset0 : out std_logic;
fpll1vcopen : out std_logic;
iocsrdataout : out std_logic;
phasedone : out std_logic_vector(1 downto 0);
shift0 : out std_logic;
shift1 : out std_logic;
dprio1byteen : in std_logic_vector(1 downto 0);
shiftdone0o : out std_logic;
shiftdone1o : out std_logic;
shiften : out std_logic_vector(17 downto 0);
up0 : out std_logic;
up1 : out std_logic;
dprio1clk : in std_logic;
dprio1din : in std_logic_vector(15 downto 0);
dprio1mdiodis : in std_logic;
dprio1read : in std_logic;
dprio1rstn : in std_logic;
dprio1sershiftload : in std_logic;
dprio1write : in std_logic;
fpll0selfrst : in std_logic;
fpll1selfrst : in std_logic;
iocsrclkin : in std_logic;
iocsrdatain : in std_logic;
ioplniotri : in std_logic;
nfrzdrv : in std_logic;
nreset : in std_logic_vector(1 downto 0);
pfden : in std_logic;
phaseen0 : in std_logic;
phaseen1 : in std_logic;
pllbias : in std_logic;
updn0 : in std_logic;
updn1 : in std_logic;
cr0dly : out std_logic_vector(10 downto 0);
cr0hi : out std_logic_vector(10 downto 0);
cr0lo : out std_logic_vector(10 downto 0);
cr0prst : out std_logic_vector(10 downto 0);
cr0sel : out std_logic_vector(1 downto 0);
cr10dly : out std_logic_vector(10 downto 0);
cr10hi : out std_logic_vector(10 downto 0);
cr10lo : out std_logic_vector(10 downto 0);
cr10prst : out std_logic_vector(10 downto 0);
cr10sel : out std_logic_vector(1 downto 0);
cr11dly : out std_logic_vector(10 downto 0);
cr11hi : out std_logic_vector(10 downto 0);
cr11lo : out std_logic_vector(10 downto 0);
cr11prst : out std_logic_vector(10 downto 0);
cr11sel : out std_logic_vector(1 downto 0);
cr12dly : out std_logic_vector(10 downto 0);
cr12hi : out std_logic_vector(10 downto 0);
cr12lo : out std_logic_vector(10 downto 0);
cr12prst : out std_logic_vector(10 downto 0);
cr12sel : out std_logic_vector(1 downto 0);
cr13dly : out std_logic_vector(10 downto 0);
cr13hi : out std_logic_vector(10 downto 0);
cr13lo : out std_logic_vector(10 downto 0);
cr13prst : out std_logic_vector(10 downto 0);
cr13sel : out std_logic_vector(1 downto 0);
cr14dly : out std_logic_vector(10 downto 0);
cr14hi : out std_logic_vector(10 downto 0);
cr14lo : out std_logic_vector(10 downto 0);
cr14prst : out std_logic_vector(10 downto 0);
cr14sel : out std_logic_vector(1 downto 0);
cr15dly : out std_logic_vector(10 downto 0);
cr15hi : out std_logic_vector(10 downto 0);
cr15lo : out std_logic_vector(10 downto 0);
cr15prst : out std_logic_vector(10 downto 0);
cr15sel : out std_logic_vector(1 downto 0);
cr16dly : out std_logic_vector(10 downto 0);
cr16hi : out std_logic_vector(10 downto 0);
cr16lo : out std_logic_vector(10 downto 0);
cr16prst : out std_logic_vector(10 downto 0);
cr16sel : out std_logic_vector(1 downto 0);
cr17dly : out std_logic_vector(10 downto 0);
cr17hi : out std_logic_vector(10 downto 0);
cr17lo : out std_logic_vector(10 downto 0);
cr17prst : out std_logic_vector(10 downto 0);
cr17sel : out std_logic_vector(1 downto 0);
cr1dly : out std_logic_vector(10 downto 0);
cr1hi : out std_logic_vector(10 downto 0);
cr1lo : out std_logic_vector(10 downto 0);
cr1prst : out std_logic_vector(10 downto 0);
cr1sel : out std_logic_vector(1 downto 0);
cr2dly : out std_logic_vector(10 downto 0);
cr2hi : out std_logic_vector(10 downto 0);
cr2lo : out std_logic_vector(10 downto 0);
cr2prst : out std_logic_vector(10 downto 0);
cr2sel : out std_logic_vector(1 downto 0);
cr3dly : out std_logic_vector(10 downto 0);
cr3hi : out std_logic_vector(10 downto 0)
);
end stratixv_pll_reconfig;
architecture behavior of stratixv_pll_reconfig is
component stratixv_pll_reconfig_encrypted
generic (
lpm_type : string := "stratixv_pll_reconfig"
);
port (
cntsel0 : in std_logic_vector(4 downto 0);
cr3lo : out std_logic_vector(10 downto 0);
cr3prst : out std_logic_vector(10 downto 0);
cr3sel : out std_logic_vector(1 downto 0);
cr4dly : out std_logic_vector(10 downto 0);
cr4hi : out std_logic_vector(10 downto 0);
cr4lo : out std_logic_vector(10 downto 0);
cr4prst : out std_logic_vector(10 downto 0);
cr4sel : out std_logic_vector(1 downto 0);
cr5dly : out std_logic_vector(10 downto 0);
cr5hi : out std_logic_vector(10 downto 0);
cntsel1 : in std_logic_vector(4 downto 0);
cr5lo : out std_logic_vector(10 downto 0);
cr5prst : out std_logic_vector(10 downto 0);
cr5sel : out std_logic_vector(1 downto 0);
cr6dly : out std_logic_vector(10 downto 0);
cr6hi : out std_logic_vector(10 downto 0);
cr6lo : out std_logic_vector(10 downto 0);
cr6prst : out std_logic_vector(10 downto 0);
cr6sel : out std_logic_vector(1 downto 0);
cr7dly : out std_logic_vector(10 downto 0);
cr7hi : out std_logic_vector(10 downto 0);
dprio0addr : in std_logic_vector(6 downto 0);
cr7lo : out std_logic_vector(10 downto 0);
cr7prst : out std_logic_vector(10 downto 0);
cr7sel : out std_logic_vector(1 downto 0);
cr8dly : out std_logic_vector(10 downto 0);
cr8hi : out std_logic_vector(10 downto 0);
cr8lo : out std_logic_vector(10 downto 0);
cr8prst : out std_logic_vector(10 downto 0);
cr8sel : out std_logic_vector(1 downto 0);
cr9dly : out std_logic_vector(10 downto 0);
cr9hi : out std_logic_vector(10 downto 0);
dprio0byteen : in std_logic_vector(1 downto 0);
cr9lo : out std_logic_vector(10 downto 0);
cr9prst : out std_logic_vector(10 downto 0);
cr9sel : out std_logic_vector(1 downto 0);
crclkenen : out std_logic_vector(3 downto 0);
crdll : out std_logic_vector(9 downto 0);
crext : out std_logic_vector(19 downto 0);
crextclkeninv : out std_logic_vector(3 downto 0);
crextclkinv : out std_logic_vector(10 downto 0);
crfpll0cp : out std_logic_vector(2 downto 0);
crfpll0dpadiv : out std_logic_vector(1 downto 0);
dprio0clk : in std_logic;
crfpll0lckbypass : out std_logic;
crfpll0lfc : out std_logic_vector(1 downto 0);
crfpll0lfr : out std_logic_vector(4 downto 0);
crfpll0lfrd : out std_logic_vector(5 downto 0);
crfpll0lockc : out std_logic_vector(3 downto 0);
crfpll0lockf : out std_logic_vector(11 downto 0);
crfpll0mdirectfb : out std_logic;
crfpll0mdly : out std_logic_vector(4 downto 0);
crfpll0mhi : out std_logic_vector(8 downto 0);
crfpll0mlo : out std_logic_vector(8 downto 0);
dprio0din : in std_logic_vector(15 downto 0);
crfpll0mprst : out std_logic_vector(10 downto 0);
crfpll0msel : out std_logic_vector(1 downto 0);
crfpll0ndly : out std_logic_vector(4 downto 0);
crfpll0nhi : out std_logic_vector(8 downto 0);
crfpll0nlo : out std_logic_vector(8 downto 0);
crfpll0pfdpulsewidth : out std_logic;
crfpll0selfrst : out std_logic_vector(1 downto 0);
crfpll0tclk : out std_logic_vector(1 downto 0);
crfpll0test : out std_logic_vector(1 downto 0);
crfpll0unlockf : out std_logic_vector(2 downto 0);
dprio0mdiodis : in std_logic;
crfpll0vcop : out std_logic_vector(7 downto 0);
crfpll0vcophbyps : out std_logic;
crfpll0vcorangeen : out std_logic;
crfpll0vr : out std_logic_vector(6 downto 0);
crfpll1cp : out std_logic_vector(2 downto 0);
crfpll1dpadiv : out std_logic_vector(1 downto 0);
crfpll1lckbypass : out std_logic;
crfpll1lfc : out std_logic_vector(1 downto 0);
crfpll1lfr : out std_logic_vector(4 downto 0);
crfpll1lfrd : out std_logic_vector(5 downto 0);
dprio0read : in std_logic;
crfpll1lockc : out std_logic_vector(3 downto 0);
crfpll1lockf : out std_logic_vector(11 downto 0);
crfpll1mdirectfb : out std_logic;
crfpll1mdly : out std_logic_vector(4 downto 0);
crfpll1mhi : out std_logic_vector(8 downto 0);
crfpll1mlo : out std_logic_vector(8 downto 0);
crfpll1mprst : out std_logic_vector(10 downto 0);
crfpll1msel : out std_logic_vector(1 downto 0);
crfpll1ndly : out std_logic_vector(4 downto 0);
crfpll1nhi : out std_logic_vector(8 downto 0);
dprio0rstn : in std_logic;
crfpll1nlo : out std_logic_vector(8 downto 0);
crfpll1pfdpulsewidth : out std_logic;
crfpll1selfrst : out std_logic_vector(1 downto 0);
crfpll1tclk : out std_logic_vector(1 downto 0);
crfpll1test : out std_logic_vector(1 downto 0);
crfpll1unlockf : out std_logic_vector(2 downto 0);
crfpll1vcop : out std_logic_vector(7 downto 0);
crfpll1vcophbyps : out std_logic;
crfpll1vcorangeen : out std_logic;
crfpll1vr : out std_logic_vector(6 downto 0);
dprio0sershiftload : in std_logic;
crinv : out std_logic_vector(85 downto 0);
crlvds : out std_logic_vector(39 downto 0);
crphaseshiftsel : out std_logic_vector(17 downto 0);
crvcosel : out std_logic_vector(17 downto 0);
crwrapback : out std_logic;
crwrapbackmux : out std_logic;
dprio0blockselect : out std_logic;
dprio0dout : out std_logic_vector(15 downto 0);
dprio1blockselect : out std_logic;
dprio1dout : out std_logic_vector(15 downto 0);
dprio0write : in std_logic;
fpll0cntnen : out std_logic;
fpll0enpfd : out std_logic;
fpll0lfreset : out std_logic;
fpll0niotricntr : out std_logic;
fpll0pdbvr : out std_logic;
fpll0pllpd : out std_logic;
fpll0reset0 : out std_logic;
fpll0vcopen : out std_logic;
fpll1cntnen : out std_logic;
fpll1enpfd : out std_logic;
dprio1addr : in std_logic_vector(6 downto 0);
fpll1lfreset : out std_logic;
fpll1niotricntr : out std_logic;
fpll1pdbvr : out std_logic;
fpll1pllpd : out std_logic;
fpll1reset0 : out std_logic;
fpll1vcopen : out std_logic;
iocsrdataout : out std_logic;
phasedone : out std_logic_vector(1 downto 0);
shift0 : out std_logic;
shift1 : out std_logic;
dprio1byteen : in std_logic_vector(1 downto 0);
shiftdone0o : out std_logic;
shiftdone1o : out std_logic;
shiften : out std_logic_vector(17 downto 0);
up0 : out std_logic;
up1 : out std_logic;
dprio1clk : in std_logic;
dprio1din : in std_logic_vector(15 downto 0);
dprio1mdiodis : in std_logic;
dprio1read : in std_logic;
dprio1rstn : in std_logic;
dprio1sershiftload : in std_logic;
dprio1write : in std_logic;
fpll0selfrst : in std_logic;
fpll1selfrst : in std_logic;
iocsrclkin : in std_logic;
iocsrdatain : in std_logic;
ioplniotri : in std_logic;
nfrzdrv : in std_logic;
nreset : in std_logic_vector(1 downto 0);
pfden : in std_logic;
phaseen0 : in std_logic;
phaseen1 : in std_logic;
pllbias : in std_logic;
updn0 : in std_logic;
updn1 : in std_logic;
cr0dly : out std_logic_vector(10 downto 0);
cr0hi : out std_logic_vector(10 downto 0);
cr0lo : out std_logic_vector(10 downto 0);
cr0prst : out std_logic_vector(10 downto 0);
cr0sel : out std_logic_vector(1 downto 0);
cr10dly : out std_logic_vector(10 downto 0);
cr10hi : out std_logic_vector(10 downto 0);
cr10lo : out std_logic_vector(10 downto 0);
cr10prst : out std_logic_vector(10 downto 0);
cr10sel : out std_logic_vector(1 downto 0);
cr11dly : out std_logic_vector(10 downto 0);
cr11hi : out std_logic_vector(10 downto 0);
cr11lo : out std_logic_vector(10 downto 0);
cr11prst : out std_logic_vector(10 downto 0);
cr11sel : out std_logic_vector(1 downto 0);
cr12dly : out std_logic_vector(10 downto 0);
cr12hi : out std_logic_vector(10 downto 0);
cr12lo : out std_logic_vector(10 downto 0);
cr12prst : out std_logic_vector(10 downto 0);
cr12sel : out std_logic_vector(1 downto 0);
cr13dly : out std_logic_vector(10 downto 0);
cr13hi : out std_logic_vector(10 downto 0);
cr13lo : out std_logic_vector(10 downto 0);
cr13prst : out std_logic_vector(10 downto 0);
cr13sel : out std_logic_vector(1 downto 0);
cr14dly : out std_logic_vector(10 downto 0);
cr14hi : out std_logic_vector(10 downto 0);
cr14lo : out std_logic_vector(10 downto 0);
cr14prst : out std_logic_vector(10 downto 0);
cr14sel : out std_logic_vector(1 downto 0);
cr15dly : out std_logic_vector(10 downto 0);
cr15hi : out std_logic_vector(10 downto 0);
cr15lo : out std_logic_vector(10 downto 0);
cr15prst : out std_logic_vector(10 downto 0);
cr15sel : out std_logic_vector(1 downto 0);
cr16dly : out std_logic_vector(10 downto 0);
cr16hi : out std_logic_vector(10 downto 0);
cr16lo : out std_logic_vector(10 downto 0);
cr16prst : out std_logic_vector(10 downto 0);
cr16sel : out std_logic_vector(1 downto 0);
cr17dly : out std_logic_vector(10 downto 0);
cr17hi : out std_logic_vector(10 downto 0);
cr17lo : out std_logic_vector(10 downto 0);
cr17prst : out std_logic_vector(10 downto 0);
cr17sel : out std_logic_vector(1 downto 0);
cr1dly : out std_logic_vector(10 downto 0);
cr1hi : out std_logic_vector(10 downto 0);
cr1lo : out std_logic_vector(10 downto 0);
cr1prst : out std_logic_vector(10 downto 0);
cr1sel : out std_logic_vector(1 downto 0);
cr2dly : out std_logic_vector(10 downto 0);
cr2hi : out std_logic_vector(10 downto 0);
cr2lo : out std_logic_vector(10 downto 0);
cr2prst : out std_logic_vector(10 downto 0);
cr2sel : out std_logic_vector(1 downto 0);
cr3dly : out std_logic_vector(10 downto 0);
cr3hi : out std_logic_vector(10 downto 0)
);
end component;
begin
inst : stratixv_pll_reconfig_encrypted
generic map (
lpm_type => lpm_type
)
port map (
cntsel0 => cntsel0,
cr3lo => cr3lo,
cr3prst => cr3prst,
cr3sel => cr3sel,
cr4dly => cr4dly,
cr4hi => cr4hi,
cr4lo => cr4lo,
cr4prst => cr4prst,
cr4sel => cr4sel,
cr5dly => cr5dly,
cr5hi => cr5hi,
cntsel1 => cntsel1,
cr5lo => cr5lo,
cr5prst => cr5prst,
cr5sel => cr5sel,
cr6dly => cr6dly,
cr6hi => cr6hi,
cr6lo => cr6lo,
cr6prst => cr6prst,
cr6sel => cr6sel,
cr7dly => cr7dly,
cr7hi => cr7hi,
dprio0addr => dprio0addr,
cr7lo => cr7lo,
cr7prst => cr7prst,
cr7sel => cr7sel,
cr8dly => cr8dly,
cr8hi => cr8hi,
cr8lo => cr8lo,
cr8prst => cr8prst,
cr8sel => cr8sel,
cr9dly => cr9dly,
cr9hi => cr9hi,
dprio0byteen => dprio0byteen,
cr9lo => cr9lo,
cr9prst => cr9prst,
cr9sel => cr9sel,
crclkenen => crclkenen,
crdll => crdll,
crext => crext,
crextclkeninv => crextclkeninv,
crextclkinv => crextclkinv,
crfpll0cp => crfpll0cp,
crfpll0dpadiv => crfpll0dpadiv,
dprio0clk => dprio0clk,
crfpll0lckbypass => crfpll0lckbypass,
crfpll0lfc => crfpll0lfc,
crfpll0lfr => crfpll0lfr,
crfpll0lfrd => crfpll0lfrd,
crfpll0lockc => crfpll0lockc,
crfpll0lockf => crfpll0lockf,
crfpll0mdirectfb => crfpll0mdirectfb,
crfpll0mdly => crfpll0mdly,
crfpll0mhi => crfpll0mhi,
crfpll0mlo => crfpll0mlo,
dprio0din => dprio0din,
crfpll0mprst => crfpll0mprst,
crfpll0msel => crfpll0msel,
crfpll0ndly => crfpll0ndly,
crfpll0nhi => crfpll0nhi,
crfpll0nlo => crfpll0nlo,
crfpll0pfdpulsewidth => crfpll0pfdpulsewidth,
crfpll0selfrst => crfpll0selfrst,
crfpll0tclk => crfpll0tclk,
crfpll0test => crfpll0test,
crfpll0unlockf => crfpll0unlockf,
dprio0mdiodis => dprio0mdiodis,
crfpll0vcop => crfpll0vcop,
crfpll0vcophbyps => crfpll0vcophbyps,
crfpll0vcorangeen => crfpll0vcorangeen,
crfpll0vr => crfpll0vr,
crfpll1cp => crfpll1cp,
crfpll1dpadiv => crfpll1dpadiv,
crfpll1lckbypass => crfpll1lckbypass,
crfpll1lfc => crfpll1lfc,
crfpll1lfr => crfpll1lfr,
crfpll1lfrd => crfpll1lfrd,
dprio0read => dprio0read,
crfpll1lockc => crfpll1lockc,
crfpll1lockf => crfpll1lockf,
crfpll1mdirectfb => crfpll1mdirectfb,
crfpll1mdly => crfpll1mdly,
crfpll1mhi => crfpll1mhi,
crfpll1mlo => crfpll1mlo,
crfpll1mprst => crfpll1mprst,
crfpll1msel => crfpll1msel,
crfpll1ndly => crfpll1ndly,
crfpll1nhi => crfpll1nhi,
dprio0rstn => dprio0rstn,
crfpll1nlo => crfpll1nlo,
crfpll1pfdpulsewidth => crfpll1pfdpulsewidth,
crfpll1selfrst => crfpll1selfrst,
crfpll1tclk => crfpll1tclk,
crfpll1test => crfpll1test,
crfpll1unlockf => crfpll1unlockf,
crfpll1vcop => crfpll1vcop,
crfpll1vcophbyps => crfpll1vcophbyps,
crfpll1vcorangeen => crfpll1vcorangeen,
crfpll1vr => crfpll1vr,
dprio0sershiftload => dprio0sershiftload,
crinv => crinv,
crlvds => crlvds,
crphaseshiftsel => crphaseshiftsel,
crvcosel => crvcosel,
crwrapback => crwrapback,
crwrapbackmux => crwrapbackmux,
dprio0blockselect => dprio0blockselect,
dprio0dout => dprio0dout,
dprio1blockselect => dprio1blockselect,
dprio1dout => dprio1dout,
dprio0write => dprio0write,
fpll0cntnen => fpll0cntnen,
fpll0enpfd => fpll0enpfd,
fpll0lfreset => fpll0lfreset,
fpll0niotricntr => fpll0niotricntr,
fpll0pdbvr => fpll0pdbvr,
fpll0pllpd => fpll0pllpd,
fpll0reset0 => fpll0reset0,
fpll0vcopen => fpll0vcopen,
fpll1cntnen => fpll1cntnen,
fpll1enpfd => fpll1enpfd,
dprio1addr => dprio1addr,
fpll1lfreset => fpll1lfreset,
fpll1niotricntr => fpll1niotricntr,
fpll1pdbvr => fpll1pdbvr,
fpll1pllpd => fpll1pllpd,
fpll1reset0 => fpll1reset0,
fpll1vcopen => fpll1vcopen,
iocsrdataout => iocsrdataout,
phasedone => phasedone,
shift0 => shift0,
shift1 => shift1,
dprio1byteen => dprio1byteen,
shiftdone0o => shiftdone0o,
shiftdone1o => shiftdone1o,
shiften => shiften,
up0 => up0,
up1 => up1,
dprio1clk => dprio1clk,
dprio1din => dprio1din,
dprio1mdiodis => dprio1mdiodis,
dprio1read => dprio1read,
dprio1rstn => dprio1rstn,
dprio1sershiftload => dprio1sershiftload,
dprio1write => dprio1write,
fpll0selfrst => fpll0selfrst,
fpll1selfrst => fpll1selfrst,
iocsrclkin => iocsrclkin,
iocsrdatain => iocsrdatain,
ioplniotri => ioplniotri,
nfrzdrv => nfrzdrv,
nreset => nreset,
pfden => pfden,
phaseen0 => phaseen0,
phaseen1 => phaseen1,
pllbias => pllbias,
updn0 => updn0,
updn1 => updn1,
cr0dly => cr0dly,
cr0hi => cr0hi,
cr0lo => cr0lo,
cr0prst => cr0prst,
cr0sel => cr0sel,
cr10dly => cr10dly,
cr10hi => cr10hi,
cr10lo => cr10lo,
cr10prst => cr10prst,
cr10sel => cr10sel,
cr11dly => cr11dly,
cr11hi => cr11hi,
cr11lo => cr11lo,
cr11prst => cr11prst,
cr11sel => cr11sel,
cr12dly => cr12dly,
cr12hi => cr12hi,
cr12lo => cr12lo,
cr12prst => cr12prst,
cr12sel => cr12sel,
cr13dly => cr13dly,
cr13hi => cr13hi,
cr13lo => cr13lo,
cr13prst => cr13prst,
cr13sel => cr13sel,
cr14dly => cr14dly,
cr14hi => cr14hi,
cr14lo => cr14lo,
cr14prst => cr14prst,
cr14sel => cr14sel,
cr15dly => cr15dly,
cr15hi => cr15hi,
cr15lo => cr15lo,
cr15prst => cr15prst,
cr15sel => cr15sel,
cr16dly => cr16dly,
cr16hi => cr16hi,
cr16lo => cr16lo,
cr16prst => cr16prst,
cr16sel => cr16sel,
cr17dly => cr17dly,
cr17hi => cr17hi,
cr17lo => cr17lo,
cr17prst => cr17prst,
cr17sel => cr17sel,
cr1dly => cr1dly,
cr1hi => cr1hi,
cr1lo => cr1lo,
cr1prst => cr1prst,
cr1sel => cr1sel,
cr2dly => cr2dly,
cr2hi => cr2hi,
cr2lo => cr2lo,
cr2prst => cr2prst,
cr2sel => cr2sel,
cr3dly => cr3dly,
cr3hi => cr3hi
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_pll_refclk_select is
generic (
lpm_type : string := "stratixv_pll_refclk_select";
pll_auto_clk_sw_en : string := "false";
pll_clk_loss_edge : string := "pll_clk_loss_both_edges";
pll_clk_loss_sw_en : string := "false";
pll_clk_sw_dly : string := "0 ps";
pll_manu_clk_sw_en : string := "false";
pll_sw_refclk_src : string := "clk_0";
reference_clock_frequency_0 : string := "0 ps";
reference_clock_frequency_1 : string := "0 ps"
);
port (
extswitch : in std_logic;
pllen : in std_logic;
refclk : in std_logic_vector(1 downto 0);
clk0bad : out std_logic;
clk1bad : out std_logic;
clkout : out std_logic;
pllclksel : out std_logic
);
end stratixv_pll_refclk_select;
architecture behavior of stratixv_pll_refclk_select is
component stratixv_pll_refclk_select_encrypted
generic (
lpm_type : string := "stratixv_pll_refclk_select";
pll_auto_clk_sw_en : string := "false";
pll_clk_loss_edge : string := "pll_clk_loss_both_edges";
pll_clk_loss_sw_en : string := "false";
pll_clk_sw_dly : string := "0 ps";
pll_manu_clk_sw_en : string := "false";
pll_sw_refclk_src : string := "clk_0";
reference_clock_frequency_0 : string := "0 ps";
reference_clock_frequency_1 : string := "0 ps"
);
port (
extswitch : in std_logic;
pllen : in std_logic;
refclk : in std_logic_vector(1 downto 0);
clk0bad : out std_logic;
clk1bad : out std_logic;
clkout : out std_logic;
pllclksel : out std_logic
);
end component;
begin
inst : stratixv_pll_refclk_select_encrypted
generic map (
lpm_type => lpm_type,
pll_auto_clk_sw_en => pll_auto_clk_sw_en,
pll_clk_loss_edge => pll_clk_loss_edge,
pll_clk_loss_sw_en => pll_clk_loss_sw_en,
pll_clk_sw_dly => pll_clk_sw_dly,
pll_manu_clk_sw_en => pll_manu_clk_sw_en,
pll_sw_refclk_src => pll_sw_refclk_src,
reference_clock_frequency_0 => reference_clock_frequency_0,
reference_clock_frequency_1 => reference_clock_frequency_1
)
port map (
extswitch => extswitch,
pllen => pllen,
refclk => refclk,
clk0bad => clk0bad,
clk1bad => clk1bad,
clkout => clkout,
pllclksel => pllclksel
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_termination_logic is
generic (
lpm_type : string := "stratixv_termination_logic";
a_iob_oct_test : string := "a_iob_oct_test_off"
);
port (
s2pload : in std_logic := '0';
serdata : in std_logic := '0';
scanenable : in std_logic := '0';
scanclk : in std_logic := '0';
enser : in std_logic := '0';
seriesterminationcontrol : out std_logic_vector(15 downto 0);
parallelterminationcontrol : out std_logic_vector(15 downto 0)
);
end stratixv_termination_logic;
architecture behavior of stratixv_termination_logic is
component stratixv_termination_logic_encrypted
generic (
lpm_type : string := "stratixv_termination_logic";
a_iob_oct_test : string := "a_iob_oct_test_off"
);
port (
s2pload : in std_logic;
serdata : in std_logic;
scanenable : in std_logic;
scanclk : in std_logic;
enser : in std_logic;
seriesterminationcontrol : out std_logic_vector(15 downto 0);
parallelterminationcontrol : out std_logic_vector(15 downto 0)
);
end component;
begin
inst : stratixv_termination_logic_encrypted
generic map (
lpm_type => lpm_type,
a_iob_oct_test => a_iob_oct_test
)
port map (
s2pload => s2pload,
serdata => serdata,
scanenable => scanenable,
scanclk => scanclk,
enser => enser,
seriesterminationcontrol => seriesterminationcontrol,
parallelterminationcontrol => parallelterminationcontrol
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_termination is
generic (
lpm_type : string := "stratixv_termination";
a_oct_cal_mode : string := "a_oct_cal_mode_none";
a_oct_user_oct : string := "a_oct_user_oct_off";
a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off";
a_oct_pwrdn : string := "a_oct_pwrdn_on";
a_oct_intosc : string := "a_oct_intosc_none";
a_oct_test_0 : string := "a_oct_test_0_off";
a_oct_test_1 : string := "a_oct_test_1_off";
a_oct_test_4 : string := "a_oct_test_4_off";
a_oct_test_5 : string := "a_oct_test_5_off";
a_oct_pllbiasen : string := "a_oct_pllbiasen_dis";
a_oct_clkenusr_inv : string := "a_oct_clkenusr_inv_off";
a_oct_enserusr_inv : string := "a_oct_enserusr_inv_off";
a_oct_scanen_inv : string := "a_oct_scanen_inv_off";
a_oct_vrefl : string := "a_oct_vrefl_m";
a_oct_vrefh : string := "a_oct_vrefh_m";
a_oct_rsmult : string := "a_oct_rsmult_1";
a_oct_rsadjust : string := "a_oct_rsadjust_none";
a_oct_calclr : string := "a_oct_calclr_off";
a_oct_rshft_rup : string := "a_oct_rshft_rup_enable";
a_oct_rshft_rdn : string := "a_oct_rshft_rdn_enable";
a_oct_usermode : string := "false"
);
port (
rzqin : in std_logic := '0';
enserusr : in std_logic := '0';
nclrusr : in std_logic := '0';
clkenusr : in std_logic := '0';
clkusr : in std_logic := '0';
scanen : in std_logic := '0';
serdatafromcore : in std_logic := '0';
scanclk : in std_logic := '0';
otherenser : in std_logic_vector(9 downto 0) := (OTHERS => '0');
serdatain : in std_logic := '0';
serdataout : out std_logic;
enserout : out std_logic;
compoutrup : out std_logic;
compoutrdn : out std_logic;
serdatatocore : out std_logic;
scanin : in std_logic := '0';
scanout : out std_logic;
clkusrdftout : out std_logic
);
end stratixv_termination;
architecture behavior of stratixv_termination is
component stratixv_termination_encrypted
generic (
lpm_type : string := "stratixv_termination";
a_oct_cal_mode : string := "a_oct_cal_mode_none";
a_oct_user_oct : string := "a_oct_user_oct_off";
a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off";
a_oct_pwrdn : string := "a_oct_pwrdn_on";
a_oct_intosc : string := "a_oct_intosc_none";
a_oct_test_0 : string := "a_oct_test_0_off";
a_oct_test_1 : string := "a_oct_test_1_off";
a_oct_test_4 : string := "a_oct_test_4_off";
a_oct_test_5 : string := "a_oct_test_5_off";
a_oct_pllbiasen : string := "a_oct_pllbiasen_dis";
a_oct_clkenusr_inv : string := "a_oct_clkenusr_inv_off";
a_oct_enserusr_inv : string := "a_oct_enserusr_inv_off";
a_oct_scanen_inv : string := "a_oct_scanen_inv_off";
a_oct_vrefl : string := "a_oct_vrefl_m";
a_oct_vrefh : string := "a_oct_vrefh_m";
a_oct_rsmult : string := "a_oct_rsmult_1";
a_oct_rsadjust : string := "a_oct_rsadjust_none";
a_oct_calclr : string := "a_oct_calclr_off";
a_oct_rshft_rup : string := "a_oct_rshft_rup_enable";
a_oct_rshft_rdn : string := "a_oct_rshft_rdn_enable";
a_oct_usermode : string := "false"
);
port (
rzqin : in std_logic;
enserusr : in std_logic;
nclrusr : in std_logic;
clkenusr : in std_logic;
clkusr : in std_logic;
scanen : in std_logic;
serdatain : in std_logic;
serdatafromcore : in std_logic;
scanclk : in std_logic;
otherenser : in std_logic_vector(9 downto 0);
serdataout : out std_logic;
enserout : out std_logic;
compoutrup : out std_logic;
compoutrdn : out std_logic;
serdatatocore : out std_logic;
scanin : in std_logic := '0';
scanout : out std_logic;
clkusrdftout : out std_logic
);
end component;
begin
inst : stratixv_termination_encrypted
generic map (
lpm_type => lpm_type,
a_oct_cal_mode => a_oct_cal_mode,
a_oct_user_oct => a_oct_user_oct,
a_oct_nclrusr_inv => a_oct_nclrusr_inv,
a_oct_pwrdn => a_oct_pwrdn,
a_oct_intosc => a_oct_intosc,
a_oct_test_0 => a_oct_test_0,
a_oct_test_1 => a_oct_test_1,
a_oct_test_4 => a_oct_test_4,
a_oct_test_5 => a_oct_test_5,
a_oct_pllbiasen => a_oct_pllbiasen,
a_oct_clkenusr_inv => a_oct_clkenusr_inv,
a_oct_enserusr_inv => a_oct_enserusr_inv,
a_oct_scanen_inv => a_oct_scanen_inv,
a_oct_vrefl => a_oct_vrefl,
a_oct_vrefh => a_oct_vrefh,
a_oct_rsmult => a_oct_rsmult,
a_oct_rsadjust => a_oct_rsadjust,
a_oct_calclr => a_oct_calclr,
a_oct_rshft_rup => a_oct_rshft_rup,
a_oct_rshft_rdn => a_oct_rshft_rdn,
a_oct_usermode => a_oct_usermode
)
port map (
rzqin => rzqin,
enserusr => enserusr,
nclrusr => nclrusr,
clkenusr => clkenusr,
clkusr => clkusr,
scanen => scanen,
serdatain => serdatain,
serdatafromcore => serdatafromcore,
scanclk => scanclk,
otherenser => otherenser,
serdataout => serdataout,
enserout => enserout,
compoutrup => compoutrup,
compoutrdn => compoutrdn,
serdatatocore => serdatatocore,
scanin => scanin,
scanout => scanout,
clkusrdftout => clkusrdftout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_asmiblock is
generic (
lpm_type : string := "stratixv_asmiblock"
);
port (
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic
);
end stratixv_asmiblock;
architecture behavior of stratixv_asmiblock is
component stratixv_asmiblock_encrypted
generic (
lpm_type : string := "stratixv_asmiblock"
);
port (
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic
);
end component;
begin
inst : stratixv_asmiblock_encrypted
generic map (
lpm_type => lpm_type
)
port map (
dclk => dclk,
sce => sce,
oe => oe,
data0out => data0out,
data1out => data1out,
data2out => data2out,
data3out => data3out,
data0oe => data0oe,
data1oe => data1oe,
data2oe => data2oe,
data3oe => data3oe,
data0in => data0in,
data1in => data1in,
data2in => data2in,
data3in => data3in
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_chipidblock is
generic (
lpm_type : string := "stratixv_chipidblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
regout : out std_logic
);
end stratixv_chipidblock;
architecture behavior of stratixv_chipidblock is
component stratixv_chipidblock_encrypted
generic (
lpm_type : string := "stratixv_chipidblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
regout : out std_logic
);
end component;
begin
inst : stratixv_chipidblock_encrypted
generic map (
lpm_type => lpm_type
)
port map (
clk => clk,
shiftnld => shiftnld,
regout => regout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_controller is
generic (
lpm_type : string := "stratixv_controller"
);
port (
nceout : out std_logic
);
end stratixv_controller;
architecture behavior of stratixv_controller is
component stratixv_controller_encrypted
generic (
lpm_type : string := "stratixv_controller"
);
port (
nceout : out std_logic
);
end component;
begin
inst : stratixv_controller_encrypted
generic map (
lpm_type => lpm_type
)
port map (
nceout => nceout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_crcblock is
generic (
oscillator_divider : integer := 256;
lpm_type : string := "stratixv_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end stratixv_crcblock;
architecture behavior of stratixv_crcblock is
component stratixv_crcblock_encrypted
generic (
oscillator_divider : integer := 256;
lpm_type : string := "stratixv_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end component;
begin
inst : stratixv_crcblock_encrypted
generic map (
oscillator_divider => oscillator_divider,
lpm_type => lpm_type
)
port map (
clk => clk,
shiftnld => shiftnld,
crcerror => crcerror,
regout => regout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_jtag is
generic (
lpm_type : string := "stratixv_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo : out std_logic;
tmsutap : out std_logic;
tckutap : out std_logic;
tdiutap : out std_logic;
shiftuser : out std_logic;
clkdruser : out std_logic;
updateuser : out std_logic;
runidleuser : out std_logic;
usr1user : out std_logic
);
end stratixv_jtag;
architecture behavior of stratixv_jtag is
component stratixv_jtag_encrypted
generic (
lpm_type : string := "stratixv_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo : out std_logic;
tmsutap : out std_logic;
tckutap : out std_logic;
tdiutap : out std_logic;
shiftuser : out std_logic;
clkdruser : out std_logic;
updateuser : out std_logic;
runidleuser : out std_logic;
usr1user : out std_logic
);
end component;
begin
inst : stratixv_jtag_encrypted
generic map (
lpm_type => lpm_type
)
port map (
tms => tms,
tck => tck,
tdi => tdi,
ntrst => ntrst,
tdoutap => tdoutap,
tdouser => tdouser,
tdo => tdo,
tmsutap => tmsutap,
tckutap => tckutap,
tdiutap => tdiutap,
shiftuser => shiftuser,
clkdruser => clkdruser,
updateuser => updateuser,
runidleuser => runidleuser,
usr1user => usr1user
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_prblock is
generic (
lpm_type : string := "stratixv_prblock"
);
port (
clk : in std_logic;
corectl : in std_logic;
prrequest : in std_logic;
data : in std_logic_vector(15 downto 0);
externalrequest : out std_logic;
error : out std_logic;
ready : out std_logic;
done : out std_logic
);
end stratixv_prblock;
architecture behavior of stratixv_prblock is
component stratixv_prblock_encrypted
generic (
lpm_type : string := "stratixv_prblock"
);
port (
clk : in std_logic;
corectl : in std_logic;
prrequest : in std_logic;
data : in std_logic_vector(15 downto 0);
externalrequest : out std_logic;
error : out std_logic;
ready : out std_logic;
done : out std_logic
);
end component;
begin
inst : stratixv_prblock_encrypted
generic map (
lpm_type => lpm_type
)
port map (
clk => clk,
corectl => corectl,
prrequest => prrequest,
data => data,
externalrequest => externalrequest,
error => error,
ready => ready,
done => done
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_rublock is
generic (
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
lpm_type : string := "stratixv_rublock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixv_rublock;
architecture behavior of stratixv_rublock is
component stratixv_rublock_encrypted
generic (
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
lpm_type : string := "stratixv_rublock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
begin
inst : stratixv_rublock_encrypted
generic map (
sim_init_watchdog_value => sim_init_watchdog_value,
sim_init_status => sim_init_status,
sim_init_config_is_application => sim_init_config_is_application,
sim_init_watchdog_enabled => sim_init_watchdog_enabled,
lpm_type => lpm_type
)
port map (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
regin => regin,
rsttimer => rsttimer,
rconfig => rconfig,
regout => regout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_tsdblock is
generic (
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
lpm_type : string := "stratixv_tsdblock"
);
port (
clk : in std_logic;
ce : in std_logic;
clr : in std_logic;
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic
);
end stratixv_tsdblock;
architecture behavior of stratixv_tsdblock is
component stratixv_tsdblock_encrypted
generic (
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
lpm_type : string := "stratixv_tsdblock"
);
port (
clk : in std_logic;
ce : in std_logic;
clr : in std_logic;
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic
);
end component;
begin
inst : stratixv_tsdblock_encrypted
generic map (
clock_divider_enable => clock_divider_enable,
clock_divider_value => clock_divider_value,
sim_tsdcalo => sim_tsdcalo,
lpm_type => lpm_type
)
port map (
clk => clk,
ce => ce,
clr => clr,
tsdcalo => tsdcalo,
tsdcaldone => tsdcaldone
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_read_fifo is
generic (
use_half_rate_read : string := "false";
sim_wclk_pre_delay : integer := 0
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '0');
wclk : in std_logic := '0';
we : in std_logic := '0';
rclk : in std_logic := '0';
re : in std_logic := '0';
areset : in std_logic := '0';
plus2 : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0)
);
end stratixv_read_fifo;
architecture behavior of stratixv_read_fifo is
component stratixv_read_fifo_encrypted
generic (
use_half_rate_read : string := "false";
sim_wclk_pre_delay : integer := 0
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '0');
wclk : in std_logic := '0';
we : in std_logic := '0';
rclk : in std_logic := '0';
re : in std_logic := '0';
areset : in std_logic := '0';
plus2 : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_read_fifo_encrypted
generic map (
use_half_rate_read => use_half_rate_read,
sim_wclk_pre_delay => sim_wclk_pre_delay
)
port map (
datain => datain,
wclk => wclk,
we => we,
rclk => rclk,
re => re,
areset => areset,
plus2 => plus2,
dataout => dataout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_read_fifo_read_enable is
generic (
use_stalled_read_enable : string := "false"
);
port (
re : in std_logic := '1';
rclk : in std_logic := '0';
plus2 : in std_logic := '0';
areset : in std_logic := '0';
reout : out std_logic;
plus2out : out std_logic
);
end stratixv_read_fifo_read_enable;
architecture behavior of stratixv_read_fifo_read_enable is
component stratixv_read_fifo_read_enable_encrypted
generic (
use_stalled_read_enable : string := "false"
);
port (
re : in std_logic := '1';
rclk : in std_logic := '0';
plus2 : in std_logic := '0';
areset : in std_logic := '0';
reout : out std_logic;
plus2out : out std_logic
);
end component;
begin
inst : stratixv_read_fifo_read_enable_encrypted
generic map (
use_stalled_read_enable => use_stalled_read_enable
)
port map (
re => re,
rclk => rclk,
plus2 => plus2,
areset => areset,
reout => reout,
plus2out => plus2out
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_phy_clkbuf is
generic (
level1_mux : string := "VALUE_FAST";
level2_mux : string := "VALUE_FAST"
);
port (
inclk : in std_logic_vector(3 downto 0) := (OTHERS => '1');
outclk : out std_logic_vector(3 downto 0)
);
end stratixv_phy_clkbuf;
architecture behavior of stratixv_phy_clkbuf is
component stratixv_phy_clkbuf_encrypted
generic (
level1_mux : string := "VALUE_FAST";
level2_mux : string := "VALUE_FAST"
);
port (
inclk : in std_logic_vector(3 downto 0) := (OTHERS => '1');
outclk : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_phy_clkbuf_encrypted
generic map (
level1_mux => level1_mux,
level2_mux => level2_mux
)
port map (
inclk => inclk,
outclk => outclk
);
end behavior;
| gpl-3.0 | c636f09853a2dc780d23c30b57ceea8c | 0.451817 | 3.990399 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_mmu_microblaze_v1_00_a/hdl/vhdl/reconos_memif_mmu_microblaze.vhd | 2 | 11,503 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_memif_mmu_microblaze_v1_00_a;
use reconos_memif_mmu_microblaze_v1_00_a.tlb;
entity reconos_memif_mmu_microblaze is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of MMU_Clk : signal is "Clk";
attribute SIGIS of MMU_Rst : signal is "Rst";
end entity reconos_memif_mmu_microblaze;
architecture implementation of reconos_memif_mmu_microblaze is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= "00" & l1_table_addr(29 downto 12) & ctrl_addr(31 downto 22) & "00";
l2_descriptor_addr <= "00" & l2_table_addr(29 downto 12) & ctrl_addr(21 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if or_reduce(MEMIF_FIFO_Mmu_Data) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity reconos_memif_mmu_microblaze_v1_00_a.tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
| gpl-2.0 | 8e953495dad7f13eb2deccf09238a798 | 0.572248 | 2.900883 | false | false | false | false |
alvieboy/xtc-base | cop_mmu.vhd | 1 | 7,517 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity cop_mmu is
port (
clk: in std_logic;
rst: in std_logic;
tlbw: out std_logic;
tlba: out std_logic_vector(2 downto 0);
tlbv: out tlb_entry_type;
mmuen: out std_logic;
dbgi: in execute_debug_type;
mdbgi: in memory_debug_type;
proten: out std_logic;
protw: out std_logic_vector(31 downto 0);
fflags: in std_logic_vector(31 downto 0);
ci: in copi;
co: out copo
);
end entity cop_mmu;
architecture behave of cop_mmu is
signal addr_q: unsigned(2 downto 0);
signal req: std_logic;
signal wrq: std_logic_vector(31 downto 0);
signal ack: std_logic;
-- TODO: move this to other place
--type logtype is record
-- pc: word_type;
-- lhs: word_type;
-- rhs: word_type;
-- opc: word_type;
--end record;
subtype logtype is std_logic_vector(127 downto 0);
constant LOGSIZE: integer := 16;
type logbuffertype is array (0 to LOGSIZE-1) of logtype;
shared variable logbuffer: logbuffertype;
signal loghigh,logread: integer range 0 to LOGSIZE-1;
signal logenabled: std_logic;
signal rlog: logtype;
-- memory debugging.
subtype mlogtype is std_logic_vector(95 downto 0);
constant MLOGSIZE: integer := 32;
type mlogbuffertype is array (0 to MLOGSIZE-1) of mlogtype;
shared variable mlogbuffer: mlogbuffertype;
signal mloghigh,mlogread: integer range 0 to MLOGSIZE-1;
signal mlogenabled: std_logic;
signal mrlog: mlogtype;
signal mmatch: word_type;
signal mmatchen: std_logic;
signal msetup: boolean;
signal enablelog: std_logic;
begin
tlba<=std_logic_vector(addr_q);
req<='1' when ci.en='1' else '0';
tlbv.pagesize <= wrq(31 downto 30);
tlbv.ctx <= wrq(24 downto 24);
tlbv.flags <= wrq(23 downto 20);
tlbv.paddr <= wrq(19 downto 0);
tlbv.vaddr <= ci.data(19 downto 0);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
mmuen<='0';
tlbw<='0';
ack<='0';
mmatchen<='1';
mmatch<=x"001640E4";
msetup<=false;
enablelog<='0';
proten<='0';
addr_q <= (others => 'X');
wrq <= (others => 'X');
protw <= (others => 'X');
co.data<= (others => 'X');
else
tlbw<='0';
ack<='0';
msetup<=false;
if req='1' and ack='0' then
co.data<=(others => '0');
case ci.reg is
when "0000" =>
if ci.wr='1' then
addr_q <= unsigned(ci.data(2 downto 0));
end if;
when "0001" =>
if ci.wr='1' then
wrq <= ci.data;
end if;
when "0010" =>
if ci.wr='1' then
tlbw<='1';
end if;
when "0011" =>
if ci.wr='1' and MMU_ENABLED then
mmuen<=ci.data(0);
end if;
when "0100" =>
when "0110" =>
if ci.wr='1' then
if TRACER_ENABLED then
enablelog<= ci.data(0);
end if;
proten<=ci.data(1);
end if;
co.data <= std_logic_vector(fflags);
when "0111" =>
if ci.wr='1' then
protw<=ci.data;
end if;
co.data <= std_logic_vector(mdbgi.faddr);
-- TODO: move this to another COP
when "1000" =>
if TRACER_ENABLED then
if ci.wr='1' then
logread<=to_integer(unsigned(ci.data));
end if;
co.data(15 downto 0) <= std_logic_vector(to_unsigned(loghigh,16));
co.data(31 downto 16) <= std_logic_vector(to_unsigned(LOGSIZE,16));
end if;
when "1001" =>
if TRACER_ENABLED then
co.data <= rlog(127 downto 96);
end if;
when "1010" =>
if TRACER_ENABLED then
co.data <= rlog(95 downto 64);
end if;
when "1011" =>
if TRACER_ENABLED then
co.data <= rlog(63 downto 32);
end if;
when "1100" =>
if TRACER_ENABLED then
co.data <= rlog(31 downto 0);
end if;
when "0101" =>
if TRACER_ENABLED then
if ci.wr='1' then
mlogread<=to_integer(unsigned(ci.data));
end if;
co.data(15 downto 0) <= std_logic_vector(to_unsigned(mloghigh,16));
co.data(31 downto 16) <= std_logic_vector(to_unsigned(MLOGSIZE,16));
end if;
when "1101" =>
if TRACER_ENABLED then
co.data <= mrlog(95 downto 64);
end if;
when "1110" =>
if TRACER_ENABLED then
if ci.wr='1' then
msetup<=true;
mmatch<=unsigned(ci.data);
if (ci.data/=x"FFFFFFFF") then
mmatchen<='1';
else
mmatchen<='0';
end if;
end if;
co.data <= mrlog(63 downto 32);
end if;
when "1111" =>
if TRACER_ENABLED then
co.data <= mrlog(31 downto 0);
end if;
when others =>
end case;
ack<='1';
else
end if;
end if;
end if;
end process;
co.valid<=ack;
tracer: if TRACER_ENABLED generate
-- TODO: trace
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
logenabled<='0';
--loghigh<=0;
else
if dbgi.trap='1' then
logenabled<='0';
end if;
if logenabled='1' then
if dbgi.valid and dbgi.executed then
if loghigh=LOGSIZE-1 then
loghigh<=0;
else
loghigh<=loghigh+1;
end if;
logbuffer(loghigh) := std_logic_vector(dbgi.pc) &
std_logic_vector(dbgi.lhs) &
std_logic_vector(dbgi.rhs) &
std_logic_vector(dbgi.opcode1) &
std_logic_vector(dbgi.opcode2);
end if;
end if;
if enablelog='1' then
logenabled<='1';
end if;
rlog <= logbuffer(logread);
end if;
end if;
end process;
-- TODO: trace
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
mlogenabled<='1';
mloghigh<=0;
else
if msetup then
mlogenabled<='1';
end if;
if dbgi.trap='1' then
mlogenabled<='0';
end if;
if mlogenabled='1' then
if mdbgi.strobe='1' and (mmatchen='0' or mdbgi.address=mmatch) and mdbgi.write='1' then
if mloghigh=MLOGSIZE-1 then
mloghigh<=0;
else
mloghigh<=mloghigh+1;
end if;
-- synthesis translate_on
mlogbuffer(mloghigh) :=
std_logic_vector(mdbgi.pc(31 downto 1)) &
mdbgi.write &
std_logic_vector(mdbgi.address) &
std_logic_vector(mdbgi.data);
end if;
end if;
mrlog <= mlogbuffer(mlogread);
end if;
end if;
end process;
end generate;
end behave;
| bsd-3-clause | 891c53fac49792c61ea5d1d50729125a | 0.489823 | 3.684804 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/altera_mf_components.vhd | 1 | 99,850 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
----------------------------------------------------------------------------
-- ALtera Megafunction Component Declaration File
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package altera_mf_components is
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component altclklock
generic (
inclock_period : natural := 10000; -- units in ps
inclock_settings : string := "UNUSED";
valid_lock_cycles : natural := 5;
invalid_lock_cycles : natural := 5;
valid_lock_multiplier : natural := 5;
invalid_lock_multiplier : natural := 5;
operation_mode : string := "NORMAL";
clock0_boost : natural := 1;
clock0_divide : natural := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay : string := "0";
clock1_boost : natural := 1;
clock1_divide : natural := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay : string := "0";
clock2_boost : natural := 1;
clock2_divide : natural := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay : string := "0";
clock_ext_boost : natural := 1;
clock_ext_divide : natural := 1;
clock_ext_settings : string := "UNUSED";
clock_ext_time_delay : string := "0";
outclock_phase_shift : natural := 0; -- units in ps
intended_device_family : string := "Stratix" ;
lpm_hint : string := "UNUSED";
lpm_type : string := "altclklock" );
port(
inclock : in std_logic; -- required port, input reference clock
inclocken : in std_logic := '1'; -- PLL enable signal
fbin : in std_logic := '1'; -- feedback input for the PLL
clock0 : out std_logic; -- clock0 output
clock1 : out std_logic; -- clock1 output
clock2 : out std_logic; -- clock2 output
clock_ext : out std_logic; -- external clock output
locked : out std_logic ); -- PLL lock signal
end component;
component altlvds_rx
generic (
number_of_channels : natural;
deserialization_factor : natural;
inclock_boost : natural:= 0;
registered_output : string := "ON";
inclock_period : natural;
cds_mode : string := "UNUSED";
intended_device_family : string := "Stratix";
input_data_rate : natural:= 0;
inclock_data_alignment : string := "UNUSED";
registered_data_align_input : string :="ON";
common_rx_tx_pll : string :="ON";
enable_dpa_mode : string := "OFF";
enable_dpa_pll_calibration : string := "OFF";
enable_dpa_calibration : string := "ON";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror : string := "OFF";
use_coreclock_input : string := "OFF";
dpll_lock_count : natural:= 0;
dpll_lock_window : natural:= 0;
outclock_resource : string := "AUTO";
data_align_rollover : natural := 10;
lose_lock_on_one_change : string := "OFF";
reset_fifo_at_first_lock : string := "ON";
use_external_pll : string := "OFF";
implement_in_les : string := "OFF";
buffer_implementation : string := "RAM";
port_rx_data_align : string := "PORT_CONNECTIVITY";
port_rx_channel_data_align : string := "PORT_CONNECTIVITY";
pll_operation_mode : string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift : string := "ON";
rx_align_data_reg : string := "RISING_EDGE";
inclock_phase_shift : integer := 0;
enable_soft_cdr_mode : string := "OFF";
sim_dpa_output_clock_phase_shift : integer := 0;
sim_dpa_is_negative_ppm_drift : string := "OFF";
sim_dpa_net_ppm_variation : natural := 0;
enable_dpa_align_to_rising_edge_only : string := "OFF";
enable_dpa_initial_phase_selection : string := "OFF";
dpa_initial_phase_value :natural := 0;
pll_self_reset_on_loss_lock : string := "OFF";
refclk_frequency : string := "UNUSED";
data_rate : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
clk_src_is_pll : string := "off" );
port (
rx_in : in std_logic_vector(number_of_channels-1 downto 0);
rx_inclock : in std_logic := '0';
rx_syncclock : in std_logic := '0';
rx_dpaclock : in std_logic_vector(0 downto 0) := (others => '0');
rx_readclock : in std_logic := '0';
rx_enable : in std_logic := '1';
rx_deskew : in std_logic := '0';
rx_pll_enable : in std_logic := '1';
rx_data_align : in std_logic := '0';
rx_data_align_reset : in std_logic := '0';
rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
pll_areset : in std_logic := '0';
rx_data_reset : in std_logic := '0';
dpa_pll_recal : in std_logic := '0';
pll_phasedone : in std_logic := '1';
rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
rx_outclock : out std_logic;
rx_locked : out std_logic;
rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0);
dpa_pll_cal_busy : out std_logic;
pll_phasestep : out std_logic;
pll_phaseupdown : out std_logic;
pll_phasecounterselect: out std_logic_Vector(3 downto 0);
pll_scanclk : out std_logic);
end component;
component altlvds_tx
generic (
number_of_channels : natural;
deserialization_factor : natural:= 4;
inclock_boost : natural := 0;
outclock_divide_by : positive:= 1;
registered_input : string := "ON";
multi_clock : string := "OFF";
inclock_period : natural;
center_align_msb : string := "UNUSED";
intended_device_family : string := "Stratix";
output_data_rate : natural:= 0;
outclock_resource : string := "AUTO";
common_rx_tx_pll : string := "ON";
inclock_data_alignment : string := "EDGE_ALIGNED";
outclock_alignment : string := "EDGE_ALIGNED";
use_external_pll : string := "OFF";
implement_in_les : STRING := "OFF";
preemphasis_setting : natural := 0;
vod_setting : natural := 0;
differential_drive : natural := 0;
outclock_multiply_by : natural := 1;
coreclock_divide_by : natural := 2;
outclock_duty_cycle : natural := 50;
inclock_phase_shift : integer := 0;
outclock_phase_shift : integer := 0;
use_no_phase_shift : string := "ON";
pll_self_reset_on_loss_lock : string := "OFF";
refclk_frequency : string := "UNUSED";
data_rate : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_tx";
clk_src_is_pll : string := "off" );
port (
tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
tx_inclock : in std_logic := '0';
tx_syncclock : in std_logic := '0';
tx_enable : in std_logic := '1';
sync_inclock : in std_logic := '0';
tx_pll_enable : in std_logic := '1';
pll_areset : in std_logic := '0';
tx_data_reset : in std_logic := '0';
tx_out : out std_logic_vector(number_of_channels-1 downto 0);
tx_outclock : out std_logic;
tx_coreclock : out std_logic;
tx_locked : out std_logic );
end component;
component altdpram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
ram_block_type : string := "AUTO";
width_byteena : natural := 1;
byte_size : natural := 5;
read_during_write_mode_mixed_ports : string := "DONT_CARE";
intended_device_family : string := "Stratix";
lpm_type : string := "altdpram" );
port(
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
inclock : in std_logic := '1';
inclocken : in std_logic := '1';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
outclock : in std_logic := '1';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0) );
end component;
component alt3pram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "OFF";
write_reg : string := "UNREGISTERED";
write_aclr : string := "OFF";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a : string := "OFF";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b : string := "OFF";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a : string := "OFF";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b : string := "OFF";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OFF";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OFF";
intended_device_family : string := "Stratix";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram" );
port (
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad-1 downto 0);
rdaddress_b : in std_logic_vector(widthad-1 downto 0);
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
qa : out std_logic_vector(width-1 downto 0);
qb : out std_logic_vector(width-1 downto 0) );
end component;
component scfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
intended_device_family : string := "NON_STRATIX";
almost_full_value : natural := 0;
almost_empty_value : natural := 0;
overflow_checking : string := "ON";
underflow_checking : string := "ON";
allow_rwcycle_when_full : string := "OFF";
add_ram_output_register : string := "OFF";
use_eab : string := "ON";
lpm_type : string := "scfifo";
maximum_depth : natural := 0 );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo_mixed_widths
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_width_r : natural := 0;
lpm_widthu_r : natural := 0;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo_mixed_widths";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width_r-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 0;
wrsync_delaypipe : natural := 0;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component altddio_in
generic (
width : positive; -- required parameter
invert_input_clocks : string := "OFF";
intended_device_family : string := "Stratix";
power_up_high : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_in" );
port (
datain : in std_logic_vector(width-1 downto 0);
inclock : in std_logic;
inclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
hrbypass : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
combout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0);
dqsundelayedout : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altshift_taps
generic (
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altshift_taps";
intended_device_family : string := "Stratix" );
port (
shiftin : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
clken : in std_logic := '1';
aclr : in std_logic := '0';
shiftout : out std_logic_vector (width-1 downto 0);
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
end component;
component altmult_add
generic (
WIDTH_A : integer := 1;
WIDTH_B : integer := 1;
WIDTH_RESULT : integer := 1;
NUMBER_OF_MULTIPLIERS : integer := 1;
-- A inputs
INPUT_REGISTER_A0 : string := "CLOCK0";
INPUT_ACLR_A0 : string := "ACLR3";
INPUT_SOURCE_A0 : string := "DATAA";
INPUT_REGISTER_A1 : string := "CLOCK0";
INPUT_ACLR_A1 : string := "ACLR3";
INPUT_SOURCE_A1 : string := "DATAA";
INPUT_REGISTER_A2 : string := "CLOCK0";
INPUT_ACLR_A2 : string := "ACLR3";
INPUT_SOURCE_A2 : string := "DATAA";
INPUT_REGISTER_A3 : string := "CLOCK0";
INPUT_ACLR_A3 : string := "ACLR3";
INPUT_SOURCE_A3 : string := "DATAA";
PORT_SIGNA : string := "PORT_CONNECTIVITY";
REPRESENTATION_A : string := "UNSIGNED";
SIGNED_REGISTER_A : string := "CLOCK0";
SIGNED_ACLR_A : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
-- B inputs
INPUT_REGISTER_B0 : string := "CLOCK0";
INPUT_ACLR_B0 : string := "ACLR3";
INPUT_SOURCE_B0 : string := "DATAB";
INPUT_REGISTER_B1 : string := "CLOCK0";
INPUT_ACLR_B1 : string := "ACLR3";
INPUT_SOURCE_B1 : string := "DATAB";
INPUT_REGISTER_B2 : string := "CLOCK0";
INPUT_ACLR_B2 : string := "ACLR3";
INPUT_SOURCE_B2 : string := "DATAB";
INPUT_REGISTER_B3 : string := "CLOCK0";
INPUT_ACLR_B3 : string := "ACLR3";
INPUT_SOURCE_B3 : string := "DATAB";
PORT_SIGNB : string := "PORT_CONNECTIVITY";
REPRESENTATION_B : string := "UNSIGNED";
SIGNED_REGISTER_B : string := "CLOCK0";
SIGNED_ACLR_B : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
MULTIPLIER_REGISTER0 : string := "CLOCK0";
MULTIPLIER_ACLR0 : string := "ACLR3";
MULTIPLIER_REGISTER1 : string := "CLOCK0";
MULTIPLIER_ACLR1 : string := "ACLR3";
MULTIPLIER_REGISTER2 : string := "CLOCK0";
MULTIPLIER_ACLR2 : string := "ACLR3";
MULTIPLIER_REGISTER3 : string := "CLOCK0";
MULTIPLIER_ACLR3 : string := "ACLR3";
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
MULT01_ROUND_ACLR : string := "ACLR3";
MULT01_ROUND_REGISTER : string := "CLOCK0";
MULT01_SATURATION_REGISTER : string := "CLOCK0";
MULT01_SATURATION_ACLR : string := "ACLR3";
MULT23_ROUND_REGISTER : string := "CLOCK0";
MULT23_ROUND_ACLR : string := "ACLR3";
MULT23_SATURATION_REGISTER : string := "CLOCK0";
MULT23_SATURATION_ACLR : string := "ACLR3";
multiplier1_direction : string := "ADD";
multiplier3_direction : string := "ADD";
OUTPUT_REGISTER : string := "CLOCK0";
OUTPUT_ACLR : string := "ACLR0";
-- StratixII parameters
multiplier01_rounding : string := "NO";
multiplier01_saturation : string := "NO";
multiplier23_rounding : string := "NO";
multiplier23_saturation : string := "NO";
adder1_rounding : string := "NO";
adder3_rounding : string := "NO";
port_mult0_is_saturated : string := "UNUSED";
port_mult1_is_saturated : string := "UNUSED";
port_mult2_is_saturated : string := "UNUSED";
port_mult3_is_saturated : string := "UNUSED";
-- Stratix III parameters
scanouta_register : string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
-- Rounding parameters
output_rounding : string := "NO";
output_round_type : string := "NEAREST_INTEGER";
width_msb : integer := 17;
output_round_register : string := "UNREGISTERED";
output_round_aclr : string := "NONE";
output_round_pipeline_register : string := "UNREGISTERED";
output_round_pipeline_aclr : string := "NONE";
chainout_rounding : string := "NO";
chainout_round_register : string := "UNREGISTERED";
chainout_round_aclr : string := "NONE";
chainout_round_pipeline_register : string := "UNREGISTERED";
chainout_round_pipeline_aclr : string := "NONE";
chainout_round_output_register : string := "UNREGISTERED";
chainout_round_output_aclr : string := "NONE";
-- saturation parameters
port_output_is_overflow : string := "PORT_UNUSED";
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
output_saturation : string := "NO";
output_saturate_type : string := "ASYMMETRIC";
width_saturate_sign : integer := 1;
output_saturate_register : string := "UNREGISTERED";
output_saturate_aclr : string := "NONE";
output_saturate_pipeline_register : string := "UNREGISTERED";
output_saturate_pipeline_aclr : string := "NONE";
chainout_saturation : string := "NO";
chainout_saturate_register : string := "UNREGISTERED";
chainout_saturate_aclr : string := "NONE";
chainout_saturate_pipeline_register : string := "UNREGISTERED";
chainout_saturate_pipeline_aclr : string := "NONE";
chainout_saturate_output_register : string := "UNREGISTERED";
chainout_saturate_output_aclr : string := "NONE";
-- chainout parameters
chainout_adder : string := "NO";
chainout_register : string := "UNREGISTERED";
chainout_aclr : string := "NONE";
width_chainin : integer := 1;
zero_chainout_output_register : string := "UNREGISTERED";
zero_chainout_output_aclr : string := "NONE";
-- rotate & shift parameters
shift_mode : string := "NO";
rotate_aclr : string := "NONE";
rotate_register : string := "UNREGISTERED";
rotate_pipeline_register : string := "UNREGISTERED";
rotate_pipeline_aclr : string := "NONE";
rotate_output_register : string := "UNREGISTERED";
rotate_output_aclr : string := "NONE";
shift_right_register : string := "UNREGISTERED";
shift_right_aclr : string := "NONE";
shift_right_pipeline_register : string := "UNREGISTERED";
shift_right_pipeline_aclr : string := "NONE";
shift_right_output_register : string := "UNREGISTERED";
shift_right_output_aclr : string := "NONE";
-- loopback parameters
zero_loopback_register : string := "UNREGISTERED";
zero_loopback_aclr : string := "NONE";
zero_loopback_pipeline_register : string := "UNREGISTERED";
zero_loopback_pipeline_aclr : string := "NONE";
zero_loopback_output_register : string := "UNREGISTERED";
zero_loopback_output_aclr : string := "NONE";
-- accumulator parameters
accum_sload_register : string := "UNREGISTERED";
accum_sload_aclr : string := "NONE";
accum_sload_pipeline_register : string := "UNREGISTERED";
accum_sload_pipeline_aclr : string := "NONE";
accum_direction : string := "ADD";
accumulator : string := "NO";
-- Stratix V parameters
width_c : integer := 22;
loadconst_value : integer := 64;
preadder_mode : string := "SIMPLE";
preadder_direction_0 : string := "ADD";
preadder_direction_1 : string := "ADD";
preadder_direction_2 : string := "ADD";
preadder_direction_3 : string := "ADD";
input_register_c0 : string := "CLOCK0";
input_aclr_c0 : string := "ACLR0";
coefsel0_register : string := "CLOCK0";
coefsel1_register : string := "CLOCK0";
coefsel2_register : string := "CLOCK0";
coefsel3_register : string := "CLOCK0";
coefsel0_aclr : string := "ACLR0";
coefsel1_aclr : string := "ACLR0";
coefsel2_aclr : string := "ACLR0";
coefsel3_aclr : string := "ACLR0";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0;
width_coef : integer := 18;
EXTRA_LATENCY : integer :=0;
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
DSP_BLOCK_BALANCING : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_add";
intended_device_family : string := "Stratix" );
port (
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
-- clock ports
clock3 : in std_logic := '1';
clock2 : in std_logic := '1';
clock1 : in std_logic := '1';
clock0 : in std_logic := '1';
aclr3 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr0 : in std_logic := '0';
ena3 : in std_logic := '1';
ena2 : in std_logic := '1';
ena1 : in std_logic := '1';
ena0 : in std_logic := '1';
-- control signals
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
addnsub1 : in std_logic := 'Z';
addnsub3 : in std_logic := 'Z';
-- StratixII only input ports
mult01_round : in std_logic := '0';
mult23_round : in std_logic := '0';
mult01_saturation : in std_logic := '0';
mult23_saturation : in std_logic := '0';
addnsub1_round : in std_logic := '0';
addnsub3_round : in std_logic := '0';
-- Stratix III only input ports
output_round : in std_logic := '0';
chainout_round : in std_logic := '0';
output_saturate : in std_logic := '0';
chainout_saturate : in std_logic := '0';
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
zero_chainout : in std_logic := '0';
rotate : in std_logic := '0';
shift_right : in std_logic := '0';
zero_loopback : in std_logic := '0';
accum_sload : in std_logic := '0';
-- Stratix V only input ports
coefsel0 : in std_logic_vector (2 downto 0) := (others => '0');
coefsel1 : in std_logic_vector (2 downto 0) := (others => '0');
coefsel2 : in std_logic_vector (2 downto 0) := (others => '0');
coefsel3 : in std_logic_vector (2 downto 0) := (others => '0');
datac : in std_logic_vector (width_c -1 downto 0) := (others => '0');
-- output ports
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
-- StratixII only output ports
mult0_is_saturated : out std_logic := '0';
mult1_is_saturated : out std_logic := '0';
mult2_is_saturated : out std_logic := '0';
mult3_is_saturated : out std_logic := '0';
-- Stratix III only output ports
overflow : out std_logic := '0';
chainout_sat_overflow : out std_logic := '0');
end component;
component altmult_accum
generic (
width_a : integer := 1;
width_b : integer := 1;
width_c : natural := 1;
width_result : integer := 2;
width_upper_data : integer := 1;
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg : string := "CLOCK0";
addnsub_pipeline_aclr : string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr : string := "ACLR3";
accum_sload_pipeline_reg : string := "CLOCK0";
accum_sload_pipeline_aclr : string := "ACLR3";
representation_a : string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a : string := "CLOCK0";
sign_pipeline_aclr_a : string := "ACLR3";
representation_b : string := "UNSIGNED";
port_signb : string := "PORT_CONNECTIVITY";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b : string := "CLOCK0";
sign_pipeline_aclr_b : string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR0";
extra_multiplier_latency : integer := 0;
extra_accumulator_latency : integer := 0;
dedicated_multiplier_circuitry : string := "AUTO";
dsp_block_balancing : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_accum";
intended_device_family : string := "Stratix";
multiplier_rounding : string := "NO";
multiplier_saturation : string := "NO";
accumulator_rounding : string := "NO";
accumulator_saturation : string := "NO";
port_mult_is_saturated : string := "UNUSED";
port_accum_is_saturated : string := "UNUSED";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr : string := "ACLR3";
mult_saturation_reg : string := "CLOCK0";
accum_round_aclr : string := "ACLR3";
accum_round_reg : string := "CLOCK3";
accum_round_pipeline_aclr : string := "ACLR3";
accum_round_pipeline_reg : string := "CLOCK0";
accum_saturation_aclr : string := "ACLR3";
accum_saturation_reg : string := "CLOCK0";
accum_saturation_pipeline_aclr : string := "ACLR3";
accum_saturation_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_reg : string := "CLOCK0";
-- StratixV parameters
preadder_mode : string := "SIMPLE";
loadconst_value : integer := 0;
width_coef : integer := 0;
loadconst_control_register : string := "CLOCK0";
loadconst_control_aclr : string := "ACLR0";
coefsel0_register : string := "CLOCK0";
coefsel1_register : string := "CLOCK0";
coefsel2_register : string := "CLOCK0";
coefsel3_register : string := "CLOCK0";
coefsel0_aclr : string := "ACLR0";
coefsel1_aclr : string := "ACLR0";
coefsel2_aclr : string := "ACLR0";
coefsel3_aclr : string := "ACLR0";
preadder_direction_0 : string := "ADD";
preadder_direction_1 : string := "ADD";
preadder_direction_2 : string := "ADD";
preadder_direction_3 : string := "ADD";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
-- coefficient storage
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0 );
port (
dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0');
datab : in std_logic_vector(width_b -1 downto 0) := (others => '0');
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
sourcea : in std_logic := '1';
sourceb : in std_logic := '1';
-- control signals
addnsub : in std_logic := 'Z';
accum_sload : in std_logic := '0';
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
-- clock ports
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clock2 : in std_logic := '1';
clock3 : in std_logic := '1';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr3 : in std_logic := '0';
-- round and saturation ports
mult_round : in std_logic := '0';
mult_saturation : in std_logic := '0';
accum_round : in std_logic := '0';
accum_saturation : in std_logic := '0';
-- StratixV only input ports
coefsel0 : in std_logic_vector(2 downto 0) := (others => '0');
coefsel1 : in std_logic_vector(2 downto 0) := (others => '0');
coefsel2 : in std_logic_vector(2 downto 0) := (others => '0');
coefsel3 : in std_logic_vector(2 downto 0) := (others => '0');
-- output ports
result : out std_logic_vector(width_result -1 downto 0);
overflow : out std_logic;
scanouta : out std_logic_vector (width_a -1 downto 0);
scanoutb : out std_logic_vector (width_b -1 downto 0);
mult_is_saturated : out std_logic := '0';
accum_is_saturated : out std_logic := '0' );
end component;
component altaccumulate
generic (
width_in : integer:= 4;
width_out : integer:= 8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:= 0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate" );
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0' );
end component;
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
width_eccstatus : integer := 3;
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
sim_show_memory_data_in_port_b_layout : string := "OFF";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := 'Z';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') );
end component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : natural; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 0;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_type : string := "AUTO";
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
self_reset_on_gated_loss_lock : string := "OFF";
self_reset_on_loss_lock : string := "OFF";
lock_window_ui : string := "0.05";
width_clock : natural := 6;
width_phasecounterselect : natural := 4;
charge_pump_current_bits : natural := 9999;
loop_filter_c_bits : natural := 9999;
loop_filter_r_bits : natural := 9999;
scan_chain_mif_file : string := "UNUSED";
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk9_multiply_by : natural := 1;
clk8_multiply_by : natural := 1;
clk7_multiply_by : natural := 1;
clk6_multiply_by : natural := 1;
clk5_multiply_by : natural := 1;
clk4_multiply_by : natural := 1;
clk3_multiply_by : natural := 1;
clk2_multiply_by : natural := 1;
clk1_multiply_by : natural := 1;
clk0_multiply_by : natural := 1;
clk9_divide_by : natural := 1;
clk8_divide_by : natural := 1;
clk7_divide_by : natural := 1;
clk6_divide_by : natural := 1;
clk5_divide_by : natural := 1;
clk4_divide_by : natural := 1;
clk3_divide_by : natural := 1;
clk2_divide_by : natural := 1;
clk1_divide_by : natural := 1;
clk0_divide_by : natural := 1;
clk9_phase_shift : string := "0";
clk8_phase_shift : string := "0";
clk7_phase_shift : string := "0";
clk6_phase_shift : string := "0";
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk9_duty_cycle : natural := 50;
clk8_duty_cycle : natural := 50;
clk7_duty_cycle : natural := 50;
clk6_duty_cycle : natural := 50;
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
clk2_output_frequency : natural := 0;
clk1_output_frequency : natural := 0;
clk0_output_frequency : natural := 0;
clk9_use_even_counter_mode : string := "OFF";
clk8_use_even_counter_mode : string := "OFF";
clk7_use_even_counter_mode : string := "OFF";
clk6_use_even_counter_mode : string := "OFF";
clk5_use_even_counter_mode : string := "OFF";
clk4_use_even_counter_mode : string := "OFF";
clk3_use_even_counter_mode : string := "OFF";
clk2_use_even_counter_mode : string := "OFF";
clk1_use_even_counter_mode : string := "OFF";
clk0_use_even_counter_mode : string := "OFF";
clk9_use_even_counter_value : string := "OFF";
clk8_use_even_counter_value : string := "OFF";
clk7_use_even_counter_value : string := "OFF";
clk6_use_even_counter_value : string := "OFF";
clk5_use_even_counter_value : string := "OFF";
clk4_use_even_counter_value : string := "OFF";
clk3_use_even_counter_value : string := "OFF";
clk2_use_even_counter_value : string := "OFF";
clk1_use_even_counter_value : string := "OFF";
clk0_use_even_counter_value : string := "OFF";
-- external clock specifications
extclk3_multiply_by : natural := 1;
extclk2_multiply_by : natural := 1;
extclk1_multiply_by : natural := 1;
extclk0_multiply_by : natural := 1;
extclk3_divide_by : natural := 1;
extclk2_divide_by : natural := 1;
extclk1_divide_by : natural := 1;
extclk0_divide_by : natural := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 0;
c0_high : natural := 1;
c1_high : natural := 1;
c2_high : natural := 1;
c3_high : natural := 1;
c4_high : natural := 1;
c5_high : natural := 1;
c6_high : natural := 1;
c7_high : natural := 1;
c8_high : natural := 1;
c9_high : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
c0_low : natural := 1;
c1_low : natural := 1;
c2_low : natural := 1;
c3_low : natural := 1;
c4_low : natural := 1;
c5_low : natural := 1;
c6_low : natural := 1;
c7_low : natural := 1;
c8_low : natural := 1;
c9_low : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
c0_initial : natural := 1;
c1_initial : natural := 1;
c2_initial : natural := 1;
c3_initial : natural := 1;
c4_initial : natural := 1;
c5_initial : natural := 1;
c6_initial : natural := 1;
c7_initial : natural := 1;
c8_initial : natural := 1;
c9_initial : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
c0_mode : string := "bypass" ;
c1_mode : string := "bypass" ;
c2_mode : string := "bypass" ;
c3_mode : string := "bypass" ;
c4_mode : string := "bypass" ;
c5_mode : string := "bypass" ;
c6_mode : string := "bypass" ;
c7_mode : string := "bypass" ;
c8_mode : string := "bypass" ;
c9_mode : string := "bypass" ;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
c0_ph : natural := 0;
c1_ph : natural := 0;
c2_ph : natural := 0;
c3_ph : natural := 0;
c4_ph : natural := 0;
c5_ph : natural := 0;
c6_ph : natural := 0;
c7_ph : natural := 0;
c8_ph : natural := 0;
c9_ph : natural := 0;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natural := 0;
g1_time_delay : natural := 0;
g2_time_delay : natural := 0;
g3_time_delay : natural := 0;
e0_time_delay : natural := 0;
e1_time_delay : natural := 0;
e2_time_delay : natural := 0;
e3_time_delay : natural := 0;
m_time_delay : natural := 0;
n_time_delay : natural := 0;
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
c6_test_source : integer := 5;
c7_test_source : integer := 5;
c8_test_source : integer := 5;
c9_test_source : integer := 5;
extclk3_counter : string := "e3" ;
extclk2_counter : string := "e2" ;
extclk1_counter : string := "e1" ;
extclk0_counter : string := "e0" ;
clk9_counter : string := "c9" ;
clk8_counter : string := "c8" ;
clk7_counter : string := "c7" ;
clk6_counter : string := "c6" ;
clk5_counter : string := "l1" ;
clk4_counter : string := "l0" ;
clk3_counter : string := "g3" ;
clk2_counter : string := "g2" ;
clk1_counter : string := "g1" ;
clk0_counter : string := "g0" ;
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : natural := 2;
loop_filter_r : string := " 1.000000";
loop_filter_c : natural := 5;
vco_post_scale : natural := 0;
vco_frequency_control : string := "AUTO";
vco_phase_shift_step : natural := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpll";
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY";
port_extclkena0 : string := "PORT_CONNECTIVITY";
port_extclkena1 : string := "PORT_CONNECTIVITY";
port_extclkena2 : string := "PORT_CONNECTIVITY";
port_extclkena3 : string := "PORT_CONNECTIVITY";
port_extclk0 : string := "PORT_CONNECTIVITY";
port_extclk1 : string := "PORT_CONNECTIVITY";
port_extclk2 : string := "PORT_CONNECTIVITY";
port_extclk3 : string := "PORT_CONNECTIVITY";
port_clkbad0 : string := "PORT_CONNECTIVITY";
port_clkbad1 : string := "PORT_CONNECTIVITY";
port_clk0 : string := "PORT_CONNECTIVITY";
port_clk1 : string := "PORT_CONNECTIVITY";
port_clk2 : string := "PORT_CONNECTIVITY";
port_clk3 : string := "PORT_CONNECTIVITY";
port_clk4 : string := "PORT_CONNECTIVITY";
port_clk5 : string := "PORT_CONNECTIVITY";
port_clk6 : string := "PORT_CONNECTIVITY";
port_clk7 : string := "PORT_CONNECTIVITY";
port_clk8 : string := "PORT_CONNECTIVITY";
port_clk9 : string := "PORT_CONNECTIVITY";
port_scandata : string := "PORT_CONNECTIVITY";
port_scandataout : string := "PORT_CONNECTIVITY";
port_scandone : string := "PORT_CONNECTIVITY";
port_sclkout1 : string := "PORT_CONNECTIVITY";
port_sclkout0 : string := "PORT_CONNECTIVITY";
port_activeclock : string := "PORT_CONNECTIVITY";
port_clkloss : string := "PORT_CONNECTIVITY";
port_inclk1 : string := "PORT_CONNECTIVITY";
port_inclk0 : string := "PORT_CONNECTIVITY";
port_fbin : string := "PORT_CONNECTIVITY";
port_fbout : string := "PORT_CONNECTIVITY";
port_pllena : string := "PORT_CONNECTIVITY";
port_clkswitch : string := "PORT_CONNECTIVITY";
port_areset : string := "PORT_CONNECTIVITY";
port_pfdena : string := "PORT_CONNECTIVITY";
port_scanclk : string := "PORT_CONNECTIVITY";
port_scanaclr : string := "PORT_CONNECTIVITY";
port_scanread : string := "PORT_CONNECTIVITY";
port_scanwrite : string := "PORT_CONNECTIVITY";
port_enable0 : string := "PORT_CONNECTIVITY";
port_enable1 : string := "PORT_CONNECTIVITY";
port_locked : string := "PORT_CONNECTIVITY";
port_configupdate : string := "PORT_CONNECTIVITY";
port_phasecounterselect : string := "PORT_CONNECTIVITY";
port_phasedone : string := "PORT_CONNECTIVITY";
port_phasestep : string := "PORT_CONNECTIVITY";
port_phaseupdown : string := "PORT_CONNECTIVITY";
port_vcooverrange : string := "PORT_CONNECTIVITY";
port_vcounderrange : string := "PORT_CONNECTIVITY";
port_scanclkena : string := "PORT_CONNECTIVITY";
using_fbmimicbidir_port : string := "ON";
sim_gate_lock_device_behavior : string := "OFF" );
port (
inclk : in std_logic_vector(1 downto 0) := (others => '0');
fbin : in std_logic := '0';
pllena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := (others => '1');
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
scanaclr : in std_logic := '0';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0');
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
configupdate : in std_logic := '0';
fbmimicbidir : inout std_logic := '1';
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
enable0 : out std_logic;
enable1 : out std_logic;
activeclock : out std_logic;
clkloss : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
sclkout0 : out std_logic;
sclkout1 : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fbout : out std_logic;
fref : out std_logic;
icdrclk : out std_logic );
end component;
component altfp_mult
generic (
width_exp : integer := 11;
width_man : integer := 31;
dedicated_multiplier_circuitry : string := "AUTO";
reduced_functionality : string := "NO";
pipeline : natural := 5;
denormal_support : string := "YES";
exception_handling : string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
aclr : in std_logic := '0';
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
overflow : out std_logic ;
underflow : out std_logic ;
zero : out std_logic ;
denormal : out std_logic ;
indefinite : out std_logic ;
nan : out std_logic );
end component;
component altsqrt
generic (
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt" );
port (
radical : in std_logic_vector(width - 1 downto 0) ;
clk : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector( q_port_width - 1 downto 0) ;
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
end component;
component parallel_add
generic (
width : natural := 4;
size : natural := 2;
widthr : natural := 4;
shift : natural := 0;
msw_subtract : string := "NO";
representation : string := "UNSIGNED";
pipeline : natural := 0;
result_alignment : string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "parallel_add" );
port (
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0) );
end component;
component a_graycounter
generic (
width : natural;
pvalue : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "a_graycounter" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
qbin : out std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0) );
end component;
component altsquare
generic (
data_width : natural;
pipeline : natural;
representation : string := "UNSIGNED";
result_alignment : string := "LSB";
result_width : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
aclr : in std_logic := '0';
clock : in std_logic := '1';
data : in std_logic_vector(data_width-1 downto 0);
ena : in std_logic := '1';
result : out std_logic_vector(result_width-1 downto 0)
);
end component;
component sld_virtual_jtag
generic (
lpm_type : string;
lpm_hint : string;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component altera_std_synchronizer
generic
(
depth : integer := 3
);
port
(
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component;
component altera_std_synchronizer_bundle
generic
(
depth : integer := 3;
width : integer := 1
);
port
(
clk : in std_logic;
reset_n : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0)
);
end component;
component alt_cal
generic (
number_of_channels : integer := 1;
channel_address_width : integer := 1;
sim_model_mode : string := "TRUE";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_cal"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
);
end component;
component alt_cal_c3gxb
generic (
number_of_channels : integer := 1;
channel_address_width : integer := 1;
sim_model_mode : string := "TRUE";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_cal_c3gxb"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
);
end component;
component alt_cal_mm
generic (
number_of_channels : integer := 1;
channel_address_width : integer := 1;
sim_model_mode : string := "TRUE";
CAL_PD_WR : string := "00101";
CAL_RX_RD : string := "00110";
CAL_RX_WR : string := "00111";
CH_ADV : string := "01100";
CH_WAIT : string := "00001";
DPRIO_READ : string := "01110";
DPRIO_WAIT : string := "01000";
DPRIO_WRITE : string := "01111";
IDLE : string := "00000";
KICK_DELAY_OC : integer := 10010;
KICK_PAUSE : integer := 10001;
KICK_START_RD : string := "01101";
KICK_START_WR : integer := 10000;
OFFSETS_PDEN_RD : string := "00011";
OFFSETS_PDEN_WR : string := "00100";
sample_length : string := "01100100";
SAMPLE_TB : string := "01001";
TEST_INPUT : string := "01010";
TESTBUS_SET : string := "00010";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_cal_mm"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC;
start : IN STD_LOGIC := '0';
transceiver_init : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
);
END component;
constant ELA_STATUS_BITS : natural := 4;
constant N_ELA_INSTRS : natural := 8;
constant SLD_IR_BITS : natural := N_ELA_INSTRS;
component sld_signaltap
generic (
SLD_CURRENT_RESOURCE_WIDTH : natural := 0;
SLD_INVERSION_MASK : std_logic_vector := "0";
SLD_POWER_UP_TRIGGER : natural := 0;
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic";
SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0;
SLD_INCREMENTAL_ROUTING : natural := 0;
SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0;
SLD_TRIGGER_IN_ENABLED : natural := 0;
SLD_STATE_BITS : natural := 11;
SLD_STATE_FLOW_USE_GENERATED : natural := 0;
SLD_INVERSION_MASK_LENGTH : integer := 1;
SLD_DATA_BITS : natural := 1;
SLD_BUFFER_FULL_STOP : natural := 1;
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0;
SLD_ATTRIBUTE_MEM_MODE : string := "OFF";
SLD_STORAGE_QUALIFIER_MODE : string := "OFF";
SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd";
SLD_NODE_CRC_LOWORD : natural := 50132;
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
SLD_TRIGGER_BITS : natural := 1;
SLD_STORAGE_QUALIFIER_BITS : natural := 1;
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
SLD_MEM_ADDRESS_BITS : natural := 7;
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
SLD_TRIGGER_LEVEL : natural := 10;
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
SLD_RAM_BLOCK_TYPE : string := "AUTO";
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
SLD_DATA_BIT_CNTR_BITS : natural := 4;
lpm_type : string := "sld_signaltap";
SLD_NODE_CRC_BITS : natural := 32;
SLD_SAMPLE_DEPTH : natural := 16;
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
SLD_SEGMENT_SIZE : natural := 0;
SLD_NODE_INFO : natural := 0;
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0;
SLD_NODE_CRC_HIWORD : natural := 41394;
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
SLD_ADVANCED_TRIGGER_3 : string := "NONE"
);
port (
jtag_state_sdr : in std_logic := '0';
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
jtag_state_cdr : in std_logic := '0';
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
tdi : in std_logic := '0';
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
jtag_state_uir : in std_logic := '0';
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
trigger_out : out std_logic;
storage_enable : in std_logic := '0';
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0');
jtag_state_udr : in std_logic := '0';
tdo : out std_logic;
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
jtag_state_e1dr : in std_logic := '0';
raw_tck : in std_logic := '0';
usr1 : in std_logic := '0';
acq_clk : in std_logic;
shift : in std_logic := '0';
ena : in std_logic := '0';
clr : in std_logic := '0';
trigger_in : in std_logic := '0';
update : in std_logic := '0';
rti : in std_logic := '0'
);
end component; --sld_signaltap
component altstratixii_oct
generic (
lpm_type : string := "altstratixii_oct"
);
port (
terminationenable : in std_logic;
terminationclock : in std_logic;
rdn : in std_logic;
rup : in std_logic
);
end component; --altstratixii_oct
constant PFL_QUAD_IO_FLASH_IR_BITS : NATURAL := 8;
constant PFL_CFI_FLASH_IR_BITS : NATURAL := 5;
constant PFL_NAND_FLASH_IR_BITS : NATURAL := 4;
constant N_FLASH_BITS : NATURAL := 4;
component altparallel_flash_loader
generic (
EXTRA_ADDR_BYTE : NATURAL := 0;
FEATURES_CFG : NATURAL := 1;
PAGE_CLK_DIVISOR : NATURAL := 1;
BURST_MODE_SPANSION : NATURAL := 0;
ENHANCED_FLASH_PROGRAMMING : NATURAL := 0;
FLASH_ECC_CHECKBOX : NATURAL := 0;
FLASH_NRESET_COUNTER : NATURAL := 1;
PAGE_MODE : NATURAL := 0;
NRB_ADDR : NATURAL := 65667072;
BURST_MODE : NATURAL := 0;
SAFE_MODE_REVERT_ADDR : NATURAL := 0;
US_UNIT_COUNTER : NATURAL := 1;
FIFO_SIZE : NATURAL := 16;
CONF_DATA_WIDTH : NATURAL := 1;
CONF_WAIT_TIMER_WIDTH : NATURAL := 14;
NFLASH_MFC : STRING := "NUMONYX";
OPTION_BITS_START_ADDRESS : NATURAL := 0;
SAFE_MODE_RETRY : NATURAL := 1;
DCLK_DIVISOR : NATURAL := 1;
FLASH_TYPE : STRING := "CFI_FLASH";
N_FLASH : NATURAL := 1;
TRISTATE_CHECKBOX : NATURAL := 0;
QFLASH_MFC : STRING := "ALTERA";
FEATURES_PGM : NATURAL := 1;
DISABLE_CRC_CHECKBOX : NATURAL := 0;
FLASH_DATA_WIDTH : NATURAL := 16;
RSU_WATCHDOG_COUNTER : NATURAL := 100000000;
PFL_RSU_WATCHDOG_ENABLED : NATURAL := 0;
SAFE_MODE_HALT : NATURAL := 0;
ADDR_WIDTH : NATURAL := 20;
NAND_SIZE : NATURAL := 67108864;
NORMAL_MODE : NATURAL := 1;
FLASH_NRESET_CHECKBOX : NATURAL := 0;
SAFE_MODE_REVERT : NATURAL := 0;
LPM_TYPE : STRING := "ALTPARALLEL_FLASH_LOADER";
AUTO_RESTART : STRING := "OFF";
CLK_DIVISOR : NATURAL := 1;
BURST_MODE_INTEL : NATURAL := 0;
BURST_MODE_NUMONYX : NATURAL := 0;
DECOMPRESSOR_MODE : STRING := "NONE"
);
port (
flash_nce : out std_logic_vector(N_FLASH-1 downto 0);
fpga_data : out std_logic_vector(CONF_DATA_WIDTH-1 downto 0);
fpga_dclk : out std_logic;
fpga_nstatus : in std_logic := '0';
flash_ale : out std_logic;
pfl_clk : in std_logic := '0';
fpga_nconfig : out std_logic;
flash_io2 : inout std_logic_vector(N_FLASH-1 downto 0);
flash_sck : out std_logic_vector(N_FLASH-1 downto 0);
flash_noe : out std_logic;
flash_nwe : out std_logic;
pfl_watchdog_error : out std_logic;
pfl_reset_watchdog : in std_logic := '0';
fpga_conf_done : in std_logic := '0';
flash_rdy : in std_logic := '1';
pfl_flash_access_granted : in std_logic := '0';
pfl_nreconfigure : in std_logic := '1';
flash_cle : out std_logic;
flash_nreset : out std_logic;
flash_io0 : inout std_logic_vector(N_FLASH-1 downto 0);
pfl_nreset : in std_logic := '0';
flash_data : inout std_logic_vector(FLASH_DATA_WIDTH-1 downto 0);
flash_io1 : inout std_logic_vector(N_FLASH-1 downto 0);
flash_nadv : out std_logic;
flash_clk : out std_logic;
flash_io3 : inout std_logic_vector(N_FLASH-1 downto 0);
flash_io : inout std_logic_vector(7 downto 0);
flash_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
pfl_flash_access_request : out std_logic;
flash_ncs : out std_logic_vector(N_FLASH-1 downto 0);
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
);
end component; --altparallel_flash_loader
component altserial_flash_loader
generic (
enhanced_mode : natural := 0;
intended_device_family : STRING := "Cyclone";
enable_shared_access : STRING := "OFF";
enable_quad_spi_support : natural := 0;
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
);
port (
data_in : in std_logic_vector(3 downto 0) := (others => '0');
noe : in std_logic := '0';
asmi_access_granted : in std_logic := '1';
data_out : out std_logic_vector(3 downto 0);
data_oe : in std_logic_vector(3 downto 0) := (others => '0');
sdoin : in std_logic := '0';
asmi_access_request : out std_logic;
data0out : out std_logic;
scein : in std_logic := '0';
dclkin : in std_logic := '0'
);
end component; --altserial_flash_loader
component sld_virtual_jtag_basic
generic (
lpm_hint : string := "UNUSED";
sld_sim_action : string := "UNUSED";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_n_scan : natural := 0;
sld_mfg_id : natural := 0;
sld_version : natural := 0;
sld_type_id : natural := 0;
lpm_type : string := "sld_virtual_jtag_basic";
sld_auto_instance_index : string := "NO";
sld_sim_total_length : natural := 0
);
port (
jtag_state_sdr : out std_logic;
jtag_state_sirs : out std_logic;
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_sir : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_e2dr : out std_logic;
tms : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_tlr : out std_logic;
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
virtual_state_sdr : out std_logic;
tdi : out std_logic;
jtag_state_uir : out std_logic;
jtag_state_cir : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_uir : out std_logic;
virtual_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
virtual_state_cir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_udr : out std_logic;
virtual_state_udr : out std_logic;
tdo : in std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_rti : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pdr : out std_logic;
tck : out std_logic
);
end component; --sld_virtual_jtag_basic
component altsource_probe
generic (
lpm_hint : string := "UNUSED";
sld_instance_index : natural := 0;
source_initial_value : string := "0";
sld_ir_width : natural := 4;
probe_width : natural := 1;
source_width : natural := 1;
instance_id : string := "UNUSED";
lpm_type : string := "altsource_probe";
sld_auto_instance_index : string := "YES";
SLD_NODE_INFO : natural := 4746752;
enable_metastability : string := "NO"
);
port (
source_clk : in std_logic;
probe : in std_logic_vector(probe_width-1 downto 0);
source : out std_logic_vector(source_width-1 downto 0);
source_ena : in std_logic
);
end component; --altsource_probe
end altera_mf_components;
| gpl-3.0 | 2856d9461c0d5c7a15429032b03ba516 | 0.469935 | 3.859981 | false | false | false | false |
thoralt/KCVGA | FPGA/ColorGenerator.vhd | 1 | 2,392 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ColorGenerator IS PORT
(
SIGNAL pixel : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL r, g, b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ColorGenerator;
ARCHITECTURE Behavioral OF ColorGenerator IS
TYPE RGB_type IS RECORD R, G, B : STD_LOGIC_VECTOR(3 DOWNTO 0);
END RECORD;
TYPE COLORS_type IS ARRAY (0 TO 31) OF RGB_type;
CONSTANT COLORS : COLORS_type := (
-- "00xxx" => background, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0111"), -- 1 blau
("0111", "0000", "0000"), -- 2 rot
("0111", "0000", "0111"), -- 3 purpur
("0000", "0111", "0000"), -- 4 grün
("0000", "0111", "0111"), -- 5 türkis
("0111", "0111", "0000"), -- 6 gelb
("0111", "0111", "0111"), -- 7 weiß
-- "01xxx" => undefined
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "0000"), -- 0 schwarz
-- "10xxx" => foreground, highlight
("0000", "0000", "0000"), -- 8 schwarz #000000
("0110", "0000", "1111"), -- 9 violett #5901FF
("1111", "0110", "0000"), -- A orange #FF5901
("1111", "0000", "1011"), -- B purpurrot #FF01B3
("0000", "1111", "0110"), -- C grünblau #01FF5A
("0000", "1000", "1111"), -- D blaugrün #0186FF
("1000", "1111", "0000"), -- E gelbgrün #86FF01
("1111", "1111", "1111"), -- F weiß #FFFFFF
-- "11xxx" => foreground, no highlight
("0000", "0000", "0000"), -- 0 schwarz
("0000", "0000", "1111"), -- 1 blau
("1111", "0000", "0000"), -- 2 rot
("1111", "0000", "1111"), -- 3 purpur
("0000", "1111", "0000"), -- 4 grün
("0000", "1111", "1111"), -- 5 türkis
("1111", "1111", "0000"), -- 6 gelb
("1111", "1111", "1111") -- 7 weiß
);
BEGIN
R <= COLORS(to_integer(unsigned(PIXEL))).R;
G <= COLORS(to_integer(unsigned(PIXEL))).G;
B <= COLORS(to_integer(unsigned(PIXEL))).B;
END Behavioral;
| mit | 8f5ed92d79040d7094f9de43bae33b91 | 0.490344 | 3.065637 | false | false | false | false |
google/myelin-acorn-electron-hardware | cpu_socket_minispartan_daughterboard/fpga-without-cpu/minispartan_expansion.vhd | 1 | 8,949 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity minispartan_expansion is
Port (
-- miniSpartan LEDs
MS_LEDS : out std_logic_vector(7 downto 0);
-- miniSpartan serial port
MS_SERIAL_TX : out std_logic := '1';
MS_SERIAL_RTS : out std_logic := '1';
MS_SERIAL_RX : in std_logic;
MS_SERIAL_CTS : in std_logic;
-- miniSpartan SD card
MS_SD_MOSI : out std_logic := '1';
MS_SD_MISO : in std_logic;
MS_SD_SCK : out std_logic := '1';
MS_SD_SS : out std_logic := '0';
-- connections to the cpu_socket_expansion board
ext_A : in std_logic_vector(15 downto 0);
ext_D : inout std_logic_vector(7 downto 0);
ext_GP0 : in std_logic; -- PHI2
ext_GP1 : out std_logic := '1'; -- n_global_enable
ext_GP2 : in std_logic; -- 16MHz
ext_GP3 : out std_logic := '1'; -- dbuf_nOE
ext_GP4 : out std_logic := '1'; -- n_accessing_shadow_ram
ext_GP5 : in std_logic := '1'; -- n_cpu_is_external
ext_GP6 : in std_logic; -- RnW
ext_GP7 : in std_logic; -- nRESET
ext_GP8 : in std_logic; -- READY
ext_GP9 : in std_logic; -- /NMI
ext_GP10 : in std_logic; -- /IRQ
ext_GP11 : out std_logic := '1'; -- dbuf_driven_by_cpu
ext_GP12 : in std_logic;
-- connections to the Raspberry Pi
tube_PHI0 : out std_logic := '1';
tube_D : inout std_logic_vector(7 downto 0);
tube_A : out std_logic_vector(2 downto 0);
tube_RnW : out std_logic := '1';
tube_nTUBE : out std_logic := '1';
tube_nRST : out std_logic := '1'
--TODO figure out directions here
--pi_serial_RX : in std_logic;
--pi_serial_TX : in std_logic;
);
end minispartan_expansion;
architecture Behavioural of minispartan_expansion is
-- '1' when ext_A is in sideways space
signal SIDEWAYS : std_logic;
-- '1' when ext_A = FCFx
signal DEBUG : std_logic;
signal debug_reg : std_logic_vector(7 downto 0);
-- '1' when ext_A = FCB1 (Elk User Port for UPURS)
signal EUP_SERIAL : std_logic;
-- '1' when ext_A = FC71 (parallel port data reg)
signal EPP_DATA : std_logic;
-- '1' when ext_A = FC72 (parallel port status reg)
signal EPP_STATUS : std_logic;
-- '1' when tube addresses are being accessed
signal tube_access : std_logic;
-- currently selected memory bank, defaults to BASIC
signal bank : std_logic_vector(3 downto 0) := x"A";
-- '1' when we're selected
signal driving_bus : std_logic;
-- '1' when reading from the embedded ROM
signal reading_rom_zero : std_logic;
-- internal wiring for embedded ROM
signal rom_zero_D : std_logic_vector(7 downto 0);
-- '1' when reading from the embedded ROM
signal reading_rom_upurs : std_logic;
-- internal wiring for embedded ROM
signal rom_upurs_D : std_logic_vector(7 downto 0);
-- '1' when reading from the embedded ROM
signal reading_rom_mmfs : std_logic;
-- internal wiring for embedded ROM
signal rom_mmfs_D : std_logic_vector(7 downto 0);
signal elk_PHI0 : std_logic;
signal n_global_enable : std_logic := '1';
signal DATA_nOE : std_logic := '1';
signal n_accessing_shadow_ram : std_logic := '1';
signal n_cpu_is_external : std_logic := '1';
signal elk_RnW : std_logic;
signal elk_nRST : std_logic;
begin
-- global settings
n_global_enable <= '0';
n_accessing_shadow_ram <= '1';
n_cpu_is_external <= '1';
-- translate ext_GP* to convenience names
elk_PHI0 <= ext_GP0;
ext_GP1 <= n_global_enable;
--clk_16MHz <= ext_GP2;
ext_GP3 <= DATA_nOE;
ext_GP4 <= n_accessing_shadow_ram;
ext_GP4 <= n_cpu_is_external;
elk_RnW <= ext_GP6;
elk_nRST <= ext_GP7;
--elk_READY <= ext_GP8;
--elk_nNMI <= ext_GP9;
--elk_nIRQ <= ext_GP10;
ext_GP11 <= not driving_bus; -- '0' to buffer from us to CPU
-- sideways address space
SIDEWAYS <= '1' when ext_A(15 downto 14) = "10" else '0';
-- debug register
DEBUG <= '1' when ext_A(15 downto 4) = x"FCF" else '0';
-- EUP serial and MMFS parallel
EUP_SERIAL <= '1' when ext_A = x"FCB1" else '0';
EPP_DATA <= '1' when ext_A = x"FC71" else '0';
EPP_STATUS <= '1' when ext_A = x"FC72" else '0';
-- Tube (&FCEx)
tube_access <= '1' when ext_A(15 downto 4) = x"FCE" else '0';
tube_D <= ext_D when elk_RnW = '0' else "ZZZZZZZZ";
tube_A <= ext_A(2 downto 0);
tube_PHI0 <= elk_PHI0;
tube_RnW <= elk_RnW;
tube_nTUBE <= not tube_access;
tube_nRST <= elk_nRST;
-- '1' when reading from the embedded ROM
reading_rom_zero <= '0'; --'1' when SIDEWAYS = '1' and bank = x"0" else '0';
reading_rom_upurs <= '1' when SIDEWAYS = '1' and bank = x"6" else '0';
reading_rom_mmfs <= '1' when SIDEWAYS = '1' and bank = x"7" else '0';
-- the actual embedded rom
rom_zero : entity work.RomZero
port map (
CLK => elk_PHI0,
A => ext_A(13 downto 0),
D => rom_zero_D,
CS => reading_rom_zero
);
rom_upurs : entity work.RomUPURS
port map (
CLK => elk_PHI0,
A => ext_A(13 downto 0),
D => rom_upurs_D,
CS => reading_rom_upurs
);
rom_mmfs : entity work.RomMMFS
port map (
CLK => elk_PHI0,
A => ext_A(13 downto 0),
D => rom_mmfs_D,
CS => reading_rom_mmfs
);
-- data bus access
driving_bus <=
-- never when cpu is writing
'0' when elk_RnW = '0' else
-- drive when reading embedded rom
'1' when reading_rom_zero = '1' or reading_rom_upurs = '1' or reading_rom_mmfs = '1' else
-- drive when reading registers
'1' when DEBUG = '1' or EUP_SERIAL = '1' or EPP_STATUS = '1' or tube_access = '1' else
-- we're not selected
'0';
-- only drive buffers during high clock period and
-- either the cpu is writing, or we're selected and
-- the cpu is reading
DATA_nOE <= '0' when (
elk_PHI0 = '1' and (elk_RnW = '0' or driving_bus = '1')
) else '1';
-- data bus
ext_D <=
-- failsafe: tristate when the buffers are pointing elk->fpga
"ZZZZZZZZ" when (elk_PHI0 = '0' or elk_RnW = '0' or driving_bus = '0') else
-- reading from tube
tube_D when tube_access = '1' else
-- reading data from the embedded ROM
rom_zero_D when reading_rom_zero = '1' else
rom_upurs_D when reading_rom_upurs = '1' else
rom_mmfs_D when reading_rom_mmfs = '1' else
-- reading debug register
debug_reg when ext_A = x"FCF0" else
ext_A(3 downto 0) & ext_A(3 downto 0) when DEBUG = '1' else
-- reading SPI status
MS_SD_MISO & "0000000" when EPP_STATUS = '1' else
-- reading serial RX
MS_SERIAL_RX & "11111" & MS_SERIAL_CTS & "1" when EUP_SERIAL = '1' else
-- default: this should never happen
"10101010";
-- Micro SD port debugging
MS_LEDS(2) <= MS_SD_MISO;
process (elk_nRST, elk_PHI0)
begin
if elk_nRST = '0' then
-- default to BASIC ROM
bank <= x"A";
MS_LEDS(7 downto 3) <= "10101";
MS_LEDS(1 downto 0) <= "00";
elsif falling_edge(elk_PHI0) then
-- set sideways bank
if (
elk_RnW = '0' and
ext_A(15 downto 8) & ext_A(3 downto 0) = x"FE5" and
ext_D(7 downto 4) = x"0"
) then
bank <= ext_D(3 downto 0);
end if;
-- set serial output
if elk_RnW = '0' and EUP_SERIAL = '1' then
MS_SERIAL_RTS <= ext_D(6);
MS_SERIAL_TX <= ext_D(0);
end if;
-- set SPI output
if elk_RnW = '0' and EPP_DATA = '1' then
MS_SD_MOSI <= ext_D(0);
MS_SD_SCK <= ext_D(1);
MS_LEDS(1 downto 0) <= ext_D(1 downto 0);
end if;
-- set leds on minispartan board by writing to FCFx
if elk_RnW = '0' and DEBUG = '1' then
MS_LEDS(7 downto 3) <= ext_D(7 downto 3);
debug_reg <= ext_D;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 1241487f384feff0a195819fb1df9b08 | 0.56118 | 3.230686 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_axi_bram_ctrl_0_0/sim/base_zynq_design_axi_bram_ctrl_0_0.vhd | 1 | 15,066 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY base_zynq_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END base_zynq_design_axi_bram_ctrl_0_0;
ARCHITECTURE base_zynq_design_axi_bram_ctrl_0_0_arch OF base_zynq_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END base_zynq_design_axi_bram_ctrl_0_0_arch;
| gpl-3.0 | 470458d0c2699245f43c96ea2cbc7c4e | 0.670649 | 3.113453 | false | false | false | false |
freecores/t400 | rtl/tech/generic/generic_ram.vhd | 1 | 3,081 | -------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM.
--
-- $Id: generic_ram.vhd,v 1.3 2008-04-27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity generic_ram is
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end generic_ram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of generic_ram is
type mem_t is array (natural range 0 to 2**addr_width_g-1) of
std_logic_vector(d_i'range);
signal mem_q : mem_t
-- pragma translate_off
:= (others => (others => '0'))
-- pragma translate_on
;
begin
mem: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if we_i = '1' then
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;
d_o <= mem_q(to_integer(unsigned(a_i)));
end if;
end process mem;
end rtl;
| gpl-2.0 | c0cbed5b93d6ae8bf80d2c58ae2ad5ee | 0.666991 | 3.89507 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_xlconcat_0_0/synth/base_zynq_design_xlconcat_0_0.vhd | 1 | 8,927 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY base_zynq_design_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_xlconcat_0_0;
ARCHITECTURE base_zynq_design_xlconcat_0_0_arch OF base_zynq_design_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_xlconcat_0_0_arch : ARCHITECTURE IS "base_zynq_design_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "base_zynq_design_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=1,NUM_PORTS=1}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 1,
NUM_PORTS => 1
)
PORT MAP (
In0 => In0,
In1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END base_zynq_design_xlconcat_0_0_arch;
| gpl-3.0 | 69e42d91269b54762f971af65a3d321c | 0.649602 | 3.23442 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_pcie_hip_components.vhd | 1 | 83,258 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
package STRATIXV_PCIE_HIP_COMPONENTS is
component stratixv_hssi_gen3_pcie_hip
generic (
func_mode : string := "disable";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count" ;
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "ch0_sel";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_gen3_pcie_hip
end STRATIXV_PCIE_HIP_COMPONENTS;
| gpl-3.0 | 911bf1bd396edfaaf50480a3995dc05d | 0.525139 | 3.276971 | false | false | false | false |
keith-epidev/md2x | build/code/debounce.vhd | 1 | 1,584 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:29:35 08/22/2012
-- Design Name:
-- Module Name: debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debounce is
generic(
delay:integer := 5000000
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal timer: std_logic_vector(19 downto 0);
signal state: std_logic;
begin
debounce_signal:process(clk)
begin
if(clk'event and clk = '1')then
if(input = state) then
if(timer < delay)then
timer <= timer + 1;
else
output <= state;
timer <= (others=>'0');
end if;
else
state <= input;
timer <= (others=>'0');
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | d34cbbe7b78ae6d37f03319488b76766 | 0.406566 | 4.728358 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_mmu_zynq_v1_00_a/hdl/vhdl/tlb.vhd | 4 | 2,967 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU - TLB
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The TLB (translation lookaside buffer) caches the last
-- address translations for faster access.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity tlb is
generic (
C_TLB_SIZE : integer := 128;
C_TAG_SIZE : integer := 20;
C_DATA_SIZE : integer := 32
);
port (
-- TLB ports
TLB_Tag : in std_logic_vector(C_TAG_SIZE - 1 downto 0);
TLB_DI : in std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_DO : out std_logic_vector(C_DATA_SIZE - 1 downto 0);
TLB_WE : in std_logic;
TLB_Hit : out std_logic;
TLB_Clk : in std_logic;
TLB_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TLB_Clk : signal is "Clk";
attribute SIGIS of TLB_Rst : signal is "Rst";
end entity tlb;
architecture implementation of tlb is
signal clk : std_logic;
signal rst : std_logic;
signal do : std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal hit : std_logic;
type TAG_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_TAG_SIZE - 1 downto 0);
type DATA_MEM_T is array (0 to C_TLB_SIZE - 1) of std_logic_vector(C_DATA_SIZE - 1 downto 0);
signal valid : std_logic_vector(0 to C_TLB_SIZE - 1);
signal tag_mem : TAG_MEM_T;
signal data_mem : DATA_MEM_T;
signal wrptr : std_logic_vector(clog2(C_TLB_SIZE) - 1 downto 0);
begin
clk <= TLB_Clk;
rst <= TLB_Rst;
TLB_DO <= do;
TLB_Hit <= hit;
write_proc : process(clk,rst) is
begin
if rst = '1' then
wrptr <= (others => '0');
valid <= (others => '0');
elsif rising_edge(clk) then
if TLB_WE = '1' then
tag_mem(CONV_INTEGER(wrptr)) <= TLB_Tag;
data_mem(CONV_INTEGER(wrptr)) <= TLB_DI;
valid(CONV_INTEGER(wrptr)) <= '1';
wrptr <= wrptr + 1;
end if;
end if;
end process write_proc;
read_proc : process(TLB_Tag,data_mem,valid,tag_mem) is
begin
hit <= '0';
do <= (others => '0');
-- loop over all tlb entries and take the first hit
for i in 0 to C_TLB_SIZE - 1 loop
if valid(i) = '1' and tag_mem(i) = TLB_Tag then
hit <= '1';
do <= data_mem(i);
exit;
end if;
end loop;
end process read_proc;
end architecture implementation;
| gpl-2.0 | 04aff6d77760a10c2c0b3bdc31cbab9d | 0.519555 | 3.05144 | false | false | false | false |
alvieboy/xtc-base | shift.vhd | 1 | 1,384 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity shifter is
port (
--clk: in std_logic;
--rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end entity shifter;
architecture behave of shifter is
signal ina: unsigned(31 downto 0);
begin
ina <= a;
process(ina,b,left,arith)
variable i: unsigned(63 downto 0);
variable cnt: unsigned(4 downto 0);
begin
i := x"00000000" & ina;
cnt := b;
if left='1' then
i(31 downto 0) := (others => '0');
i(63 downto 31) := '0' & ina;
cnt := not cnt;
elsif arith='1' then
if ina(31) = '1' then
i(63 downto 32) := (others => '1');
else
i(63 downto 32) := (others => '0');
end if;
end if;
-- Shift according to each bit.
if cnt(4)='1' then
i(47 downto 0) := i(63 downto 16);
end if;
if cnt(3)='1' then
i(39 downto 0) := i(47 downto 8);
end if;
if cnt(2) = '1' then
i(35 downto 0) := i(39 downto 4);
end if;
if cnt(1) = '1' then
i(33 downto 0) := i(35 downto 2);
end if;
if cnt(0) = '1' then
i(31 downto 0) := i(32 downto 1);
end if;
o <= i(31 downto 0);
end process;
end behave;
| bsd-3-clause | 7f3036db678a0e9e0e294397c915e45e | 0.543353 | 2.989201 | false | false | false | false |
alvieboy/xtc-base | generic_dp_ram_r.vhd | 1 | 3,606 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity generic_dp_ram_r is
generic (
address_bits: integer := 8;
srval_1: std_logic_vector(32-1 downto 0);
srval_2: std_logic_vector(32-1 downto 0)
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
ssra: in std_logic;
dia: in std_logic_vector(32-1 downto 0);
doa: out std_logic_vector(32-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
ssrb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(32-1 downto 0);
dob: out std_logic_vector(32-1 downto 0);
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end entity generic_dp_ram_r;
architecture behave of generic_dp_ram_r is
subtype RAM_WORD is STD_LOGIC_VECTOR (32-1 downto 0);
type RAM_TABLE is array (0 to (2**address_bits) - 1) of RAM_WORD;
shared variable RAM: RAM_TABLE := (others => (others => '0'));
begin
-- synthesis translate_off
dbg_do <= RAM(conv_integer(dbg_addr));
-- synthesis translate_on
process (clka)
begin
if rising_edge(clka) then
if ena='1' then
if wea='1' then
RAM( conv_integer(addra) ) := dia;
end if;
if ssra='1' then
doa <= srval_1;
else
doa <= RAM(conv_integer(addra)) ;
end if;
end if;
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if enb='1' then
if web='1' then
RAM( conv_integer(addrb) ) := dib;
end if;
if ssrb='1' then
dob <= srval_2;
else
dob <= RAM(conv_integer(addrb)) ;
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 0882a371c761333b5da4ca2b9e6fe572 | 0.617027 | 3.668362 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/220model.vhd | 1 | 375,551 | ---------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--------------------------------------------------------------------------
--
-- Quartus II 11.0 Build 157 04/27/2011
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
-- These models are based on LPM version 220 (EIA-IS103 October 1998).
--------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
-------------------------------------------------------------------------------
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_COMMON_CONVERSION
--
-- Description : Common conversion functions
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
-- PACKAGE DECLARATION
package LPM_COMMON_CONVERSION is
-- FUNCTION DECLARATION
function STR_TO_INT (str : string) return integer;
function INT_TO_STR (value : in integer) return string;
function HEX_STR_TO_INT (str : in string) return integer;
function BIN_STR_TO_INT (str : in string) return integer;
function OCT_STR_TO_INT (str : in string) return integer;
function INT_STR_TO_INT (str : in string) return integer;
function ALPHA_TOLOWER (given_string : in string) return string;
procedure SHRINK_LINE (str_line : inout line; pos : in integer);
end LPM_COMMON_CONVERSION;
package body LPM_COMMON_CONVERSION is
function STR_TO_INT ( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 10 + digit;
end loop;
return ivalue;
end STR_TO_INT;
-- This function converts an integer to a string
function INT_TO_STR (value : in integer) return string is
variable ivalue : integer := 0;
variable index : integer := 0;
variable digit : integer := 0;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end INT_TO_STR;
-- This function converts a hexadecimal number to an integer
function HEX_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal hex character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end HEX_STR_TO_INT;
-- This function converts a binary number to an integer
function BIN_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when others =>
ASSERT FALSE
REPORT "Illegal bin character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 2 + digit;
end loop;
return ivalue;
end BIN_STR_TO_INT;
-- This function converts a octadecimal number to an integer
function OCT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when others =>
ASSERT FALSE
REPORT "Illegal octadecimal character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 8 + digit;
end loop;
return ivalue;
end OCT_STR_TO_INT;
-- This function converts a integer string to an integer
function INT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto")
function ALPHA_TOLOWER (given_string : in string) return string is
-- VARIABLE DECLARATION
variable result_string : string(given_string'low to given_string'high);
begin
for i in given_string'low to given_string'high loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(given_string'low to given_string'high));
end;
-- This procedure "cuts" the str_line into desired length
procedure SHRINK_LINE (str_line : inout line; pos : in integer) is
subtype nstring is string(1 to pos);
variable str : nstring;
begin
if (pos >= 1) then
read(str_line, str);
end if;
end;
end LPM_COMMON_CONVERSION;
-- END OF PACKAGE
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_HINT_EVALUATION
--
-- Description : Common function to grep the value of altera specific parameters
-- within the lpm_hint parameter.
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_HINT_EVALUATION is
-- FUNCTION DECLARATION
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string;
end LPM_HINT_EVALUATION;
package body LPM_HINT_EVALUATION is
-- This function will search through the string (given string) to look for a match for the
-- a given parameter(compare_param_name). It will return the value for the given parameter.
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string is
variable param_name_left_index : integer := given_string'length;
variable param_name_right_index : integer := given_string'length;
variable param_value_left_index : integer := given_string'length;
variable param_value_right_index : integer := given_string'length;
variable set_right_index : boolean := true;
variable extract_param_value : boolean := true;
variable extract_param_name : boolean := false;
variable param_found : boolean := false;
variable given_string_tmp : string(1 to given_string'length) := given_string;
begin
-- checking every character of the given_string from right to left.
for i in given_string'length downto 1 loop
if (given_string(i) /= ' ') then
if (given_string(i) = '=') then
extract_param_value := false;
extract_param_name := true;
set_right_index := true;
elsif (given_string(i) = ',') then
extract_param_value := true;
extract_param_name := false;
set_right_index := true;
if (compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true; -- the compare_param_name have been found in the given_string
exit;
end if;
else
if (extract_param_value = true) then
if (set_right_index = true) then
param_value_right_index := i;
set_right_index := false;
end if;
param_value_left_index := i;
elsif (extract_param_name = true) then
if (set_right_index = true) then
param_name_right_index := i;
set_right_index := false;
end if;
param_name_left_index := i;
end if;
end if;
end if;
end loop;
-- for the case whether parameter's name is the left most part of the given_string
if (extract_param_name = true) then
if(compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true;
end if;
end if;
if(param_found = true) then
return given_string_tmp(param_value_left_index to param_value_right_index);
else
return ""; -- return empty string if parameter not found
end if;
end get_parameter_value;
end LPM_HINT_EVALUATION;
-- END OF PACKAGE
-- BEGINING OF PACKAGES
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_DEVICE_FAMILIES is
-- FUNCTION DECLARATION
function IS_FAMILY_MAX7000B (device : in string) return boolean;
function IS_FAMILY_MAX7000AE (device : in string) return boolean;
function IS_FAMILY_MAX3000A (device : in string) return boolean;
function IS_FAMILY_MAX7000S (device : in string) return boolean;
function IS_FAMILY_STRATIX (device : in string) return boolean;
function IS_FAMILY_STRATIXGX (device : in string) return boolean;
function IS_FAMILY_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_MAX (device : in string) return boolean;
function IS_VALID_FAMILY (device: in string) return boolean;
end LPM_DEVICE_FAMILIES;
package body LPM_DEVICE_FAMILIES is
function IS_FAMILY_MAX7000B (device : in string) return boolean is
variable is_max7000b : boolean := false;
begin
if ((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
then
is_max7000b := true;
end if;
return is_max7000b;
end IS_FAMILY_MAX7000B;
function IS_FAMILY_MAX7000AE (device : in string) return boolean is
variable is_max7000ae : boolean := false;
begin
if ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
then
is_max7000ae := true;
end if;
return is_max7000ae;
end IS_FAMILY_MAX7000AE;
function IS_FAMILY_MAX3000A (device : in string) return boolean is
variable is_max3000a : boolean := false;
begin
if ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
then
is_max3000a := true;
end if;
return is_max3000a;
end IS_FAMILY_MAX3000A;
function IS_FAMILY_MAX7000S (device : in string) return boolean is
variable is_max7000s : boolean := false;
begin
if ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
then
is_max7000s := true;
end if;
return is_max7000s;
end IS_FAMILY_MAX7000S;
function IS_FAMILY_STRATIX (device : in string) return boolean is
variable is_stratix : boolean := false;
begin
if ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
then
is_stratix := true;
end if;
return is_stratix;
end IS_FAMILY_STRATIX;
function IS_FAMILY_STRATIXGX (device : in string) return boolean is
variable is_stratixgx : boolean := false;
begin
if ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
then
is_stratixgx := true;
end if;
return is_stratixgx;
end IS_FAMILY_STRATIXGX;
function IS_FAMILY_CYCLONE (device : in string) return boolean is
variable is_cyclone : boolean := false;
begin
if ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
then
is_cyclone := true;
end if;
return is_cyclone;
end IS_FAMILY_CYCLONE;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean is
variable var_family_base_stratix : boolean := false;
begin
if (IS_FAMILY_STRATIX(device) or IS_FAMILY_STRATIXGX(device) )
then
var_family_base_stratix := true;
end if;
return var_family_base_stratix;
end FEATURE_FAMILY_BASE_STRATIX;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean is
variable var_family_base_cyclone : boolean := false;
begin
if (IS_FAMILY_CYCLONE(device) )
then
var_family_base_cyclone := true;
end if;
return var_family_base_cyclone;
end FEATURE_FAMILY_BASE_CYCLONE;
function FEATURE_FAMILY_MAX (device : in string) return boolean is
variable var_family_max : boolean := false;
begin
if ((device = "MAX5000") or IS_FAMILY_MAX3000A(device) or (device = "MAX7000") or (device = "MAX7000A") or IS_FAMILY_MAX7000AE(device) or (device = "MAX7000E") or IS_FAMILY_MAX7000S(device) or IS_FAMILY_MAX7000B(device) or (device = "MAX9000") )
then
var_family_max := true;
end if;
return var_family_max;
end FEATURE_FAMILY_MAX;
function IS_VALID_FAMILY (device : in string) return boolean is
variable is_valid : boolean := false;
begin
if (((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
or ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
or ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
or ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
or ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
or ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
or ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
or ((device = "MAX II") or (device = "max ii") or (device = "MAXII") or (device = "maxii") or (device = "Tsunami") or (device = "TSUNAMI") or (device = "tsunami"))
or ((device = "Stratix II") or (device = "STRATIX II") or (device = "stratix ii") or (device = "StratixII") or (device = "STRATIXII") or (device = "stratixii") or (device = "Armstrong") or (device = "ARMSTRONG") or (device = "armstrong"))
or ((device = "Stratix II GX") or (device = "STRATIX II GX") or (device = "stratix ii gx") or (device = "StratixIIGX") or (device = "STRATIXIIGX") or (device = "stratixiigx"))
or ((device = "Arria GX") or (device = "ARRIA GX") or (device = "arria gx") or (device = "ArriaGX") or (device = "ARRIAGX") or (device = "arriagx") or (device = "Stratix II GX Lite") or (device = "STRATIX II GX LITE") or (device = "stratix ii gx lite") or (device = "StratixIIGXLite") or (device = "STRATIXIIGXLITE") or (device = "stratixiigxlite"))
or ((device = "Cyclone II") or (device = "CYCLONE II") or (device = "cyclone ii") or (device = "Cycloneii") or (device = "CYCLONEII") or (device = "cycloneii") or (device = "Magellan") or (device = "MAGELLAN") or (device = "magellan"))
or ((device = "HardCopy II") or (device = "HARDCOPY II") or (device = "hardcopy ii") or (device = "HardCopyII") or (device = "HARDCOPYII") or (device = "hardcopyii") or (device = "Fusion") or (device = "FUSION") or (device = "fusion"))
or ((device = "Stratix III") or (device = "STRATIX III") or (device = "stratix iii") or (device = "StratixIII") or (device = "STRATIXIII") or (device = "stratixiii") or (device = "Titan") or (device = "TITAN") or (device = "titan") or (device = "SIII") or (device = "siii"))
or ((device = "Cyclone III") or (device = "CYCLONE III") or (device = "cyclone iii") or (device = "CycloneIII") or (device = "CYCLONEIII") or (device = "cycloneiii") or (device = "Barracuda") or (device = "BARRACUDA") or (device = "barracuda") or (device = "Cuda") or (device = "CUDA") or (device = "cuda") or (device = "CIII") or (device = "ciii"))
or ((device = "BS") or (device = "bs"))
or ((device = "Stratix IV") or (device = "STRATIX IV") or (device = "stratix iv") or (device = "TGX") or (device = "tgx") or (device = "StratixIV") or (device = "STRATIXIV") or (device = "stratixiv") or (device = "Stratix IV (GT)") or (device = "STRATIX IV (GT)") or (device = "stratix iv (gt)") or (device = "Stratix IV (GX)") or (device = "STRATIX IV (GX)") or (device = "stratix iv (gx)") or (device = "Stratix IV (E)") or (device = "STRATIX IV (E)") or (device = "stratix iv (e)") or (device = "StratixIV(GT)") or (device = "STRATIXIV(GT)") or (device = "stratixiv(gt)") or (device = "StratixIV(GX)") or (device = "STRATIXIV(GX)") or (device = "stratixiv(gx)") or (device = "StratixIV(E)") or (device = "STRATIXIV(E)") or (device = "stratixiv(e)") or (device = "StratixIIIGX") or (device = "STRATIXIIIGX") or (device = "stratixiiigx") or (device = "Stratix IV (GT/GX/E)") or (device = "STRATIX IV (GT/GX/E)") or (device = "stratix iv (gt/gx/e)") or (device = "Stratix IV (GT/E/GX)") or (device = "STRATIX IV (GT/E/GX)") or (device = "stratix iv (gt/e/gx)") or (device = "Stratix IV (E/GT/GX)") or (device = "STRATIX IV (E/GT/GX)") or (device = "stratix iv (e/gt/gx)") or (device = "Stratix IV (E/GX/GT)") or (device = "STRATIX IV (E/GX/GT)") or (device = "stratix iv (e/gx/gt)") or (device = "StratixIV(GT/GX/E)") or (device = "STRATIXIV(GT/GX/E)") or (device = "stratixiv(gt/gx/e)") or (device = "StratixIV(GT/E/GX)") or (device = "STRATIXIV(GT/E/GX)") or (device = "stratixiv(gt/e/gx)") or (device = "StratixIV(E/GX/GT)") or (device = "STRATIXIV(E/GX/GT)") or (device = "stratixiv(e/gx/gt)") or (device = "StratixIV(E/GT/GX)") or (device = "STRATIXIV(E/GT/GX)") or (device = "stratixiv(e/gt/gx)") or (device = "Stratix IV (GX/E)") or (device = "STRATIX IV (GX/E)") or (device = "stratix iv (gx/e)") or (device = "StratixIV(GX/E)") or (device = "STRATIXIV(GX/E)") or (device = "stratixiv(gx/e)"))
or ((device = "tgx_commercial_v1_1") or (device = "TGX_COMMERCIAL_V1_1"))
or ((device = "Arria II GX") or (device = "ARRIA II GX") or (device = "arria ii gx") or (device = "ArriaIIGX") or (device = "ARRIAIIGX") or (device = "arriaiigx") or (device = "Arria IIGX") or (device = "ARRIA IIGX") or (device = "arria iigx") or (device = "ArriaII GX") or (device = "ARRIAII GX") or (device = "arriaii gx") or (device = "Arria II") or (device = "ARRIA II") or (device = "arria ii") or (device = "ArriaII") or (device = "ARRIAII") or (device = "arriaii") or (device = "Arria II (GX/E)") or (device = "ARRIA II (GX/E)") or (device = "arria ii (gx/e)") or (device = "ArriaII(GX/E)") or (device = "ARRIAII(GX/E)") or (device = "arriaii(gx/e)") or (device = "PIRANHA") or (device = "piranha"))
or ((device = "HardCopy III") or (device = "HARDCOPY III") or (device = "hardcopy iii") or (device = "HardCopyIII") or (device = "HARDCOPYIII") or (device = "hardcopyiii") or (device = "HCX") or (device = "hcx"))
or ((device = "HardCopy IV") or (device = "HARDCOPY IV") or (device = "hardcopy iv") or (device = "HardCopyIV") or (device = "HARDCOPYIV") or (device = "hardcopyiv") or (device = "HardCopy IV (GX)") or (device = "HARDCOPY IV (GX)") or (device = "hardcopy iv (gx)") or (device = "HardCopy IV (E)") or (device = "HARDCOPY IV (E)") or (device = "hardcopy iv (e)") or (device = "HardCopyIV(GX)") or (device = "HARDCOPYIV(GX)") or (device = "hardcopyiv(gx)") or (device = "HardCopyIV(E)") or (device = "HARDCOPYIV(E)") or (device = "hardcopyiv(e)") or (device = "HCXIV") or (device = "hcxiv") or (device = "HardCopy IV (GX/E)") or (device = "HARDCOPY IV (GX/E)") or (device = "hardcopy iv (gx/e)") or (device = "HardCopy IV (E/GX)") or (device = "HARDCOPY IV (E/GX)") or (device = "hardcopy iv (e/gx)") or (device = "HardCopyIV(GX/E)") or (device = "HARDCOPYIV(GX/E)") or (device = "hardcopyiv(gx/e)") or (device = "HardCopyIV(E/GX)") or (device = "HARDCOPYIV(E/GX)") or (device = "hardcopyiv(e/gx)"))
or ((device = "Cyclone III LS") or (device = "CYCLONE III LS") or (device = "cyclone iii ls") or (device = "CycloneIIILS") or (device = "CYCLONEIIILS") or (device = "cycloneiiils") or (device = "Cyclone III LPS") or (device = "CYCLONE III LPS") or (device = "cyclone iii lps") or (device = "Cyclone LPS") or (device = "CYCLONE LPS") or (device = "cyclone lps") or (device = "CycloneLPS") or (device = "CYCLONELPS") or (device = "cyclonelps") or (device = "Tarpon") or (device = "TARPON") or (device = "tarpon") or (device = "Cyclone IIIE") or (device = "CYCLONE IIIE") or (device = "cyclone iiie"))
or ((device = "Cyclone IV GX") or (device = "CYCLONE IV GX") or (device = "cyclone iv gx") or (device = "Cyclone IVGX") or (device = "CYCLONE IVGX") or (device = "cyclone ivgx") or (device = "CycloneIV GX") or (device = "CYCLONEIV GX") or (device = "cycloneiv gx") or (device = "CycloneIVGX") or (device = "CYCLONEIVGX") or (device = "cycloneivgx") or (device = "Cyclone IV") or (device = "CYCLONE IV") or (device = "cyclone iv") or (device = "CycloneIV") or (device = "CYCLONEIV") or (device = "cycloneiv") or (device = "Cyclone IV (GX)") or (device = "CYCLONE IV (GX)") or (device = "cyclone iv (gx)") or (device = "CycloneIV(GX)") or (device = "CYCLONEIV(GX)") or (device = "cycloneiv(gx)") or (device = "Cyclone III GX") or (device = "CYCLONE III GX") or (device = "cyclone iii gx") or (device = "CycloneIII GX") or (device = "CYCLONEIII GX") or (device = "cycloneiii gx") or (device = "Cyclone IIIGX") or (device = "CYCLONE IIIGX") or (device = "cyclone iiigx") or (device = "CycloneIIIGX") or (device = "CYCLONEIIIGX") or (device = "cycloneiiigx") or (device = "Cyclone III GL") or (device = "CYCLONE III GL") or (device = "cyclone iii gl") or (device = "CycloneIII GL") or (device = "CYCLONEIII GL") or (device = "cycloneiii gl") or (device = "Cyclone IIIGL") or (device = "CYCLONE IIIGL") or (device = "cyclone iiigl") or (device = "CycloneIIIGL") or (device = "CYCLONEIIIGL") or (device = "cycloneiiigl") or (device = "Stingray") or (device = "STINGRAY") or (device = "stingray"))
or ((device = "Cyclone IV E") or (device = "CYCLONE IV E") or (device = "cyclone iv e") or (device = "CycloneIV E") or (device = "CYCLONEIV E") or (device = "cycloneiv e") or (device = "Cyclone IVE") or (device = "CYCLONE IVE") or (device = "cyclone ive") or (device = "CycloneIVE") or (device = "CYCLONEIVE") or (device = "cycloneive"))
or ((device = "Stratix V") or (device = "STRATIX V") or (device = "stratix v") or (device = "StratixV") or (device = "STRATIXV") or (device = "stratixv") or (device = "Stratix V (GS)") or (device = "STRATIX V (GS)") or (device = "stratix v (gs)") or (device = "StratixV(GS)") or (device = "STRATIXV(GS)") or (device = "stratixv(gs)") or (device = "Stratix V (GT)") or (device = "STRATIX V (GT)") or (device = "stratix v (gt)") or (device = "StratixV(GT)") or (device = "STRATIXV(GT)") or (device = "stratixv(gt)") or (device = "Stratix V (GX)") or (device = "STRATIX V (GX)") or (device = "stratix v (gx)") or (device = "StratixV(GX)") or (device = "STRATIXV(GX)") or (device = "stratixv(gx)") or (device = "Stratix V (GS/GX)") or (device = "STRATIX V (GS/GX)") or (device = "stratix v (gs/gx)") or (device = "StratixV(GS/GX)") or (device = "STRATIXV(GS/GX)") or (device = "stratixv(gs/gx)") or (device = "Stratix V (GS/GT)") or (device = "STRATIX V (GS/GT)") or (device = "stratix v (gs/gt)") or (device = "StratixV(GS/GT)") or (device = "STRATIXV(GS/GT)") or (device = "stratixv(gs/gt)") or (device = "Stratix V (GT/GX)") or (device = "STRATIX V (GT/GX)") or (device = "stratix v (gt/gx)") or (device = "StratixV(GT/GX)") or (device = "STRATIXV(GT/GX)") or (device = "stratixv(gt/gx)") or (device = "Stratix V (GX/GS)") or (device = "STRATIX V (GX/GS)") or (device = "stratix v (gx/gs)") or (device = "StratixV(GX/GS)") or (device = "STRATIXV(GX/GS)") or (device = "stratixv(gx/gs)") or (device = "Stratix V (GT/GS)") or (device = "STRATIX V (GT/GS)") or (device = "stratix v (gt/gs)") or (device = "StratixV(GT/GS)") or (device = "STRATIXV(GT/GS)") or (device = "stratixv(gt/gs)") or (device = "Stratix V (GX/GT)") or (device = "STRATIX V (GX/GT)") or (device = "stratix v (gx/gt)") or (device = "StratixV(GX/GT)") or (device = "STRATIXV(GX/GT)") or (device = "stratixv(gx/gt)") or (device = "Stratix V (GS/GT/GX)") or (device = "STRATIX V (GS/GT/GX)") or (device = "stratix v (gs/gt/gx)") or (device = "Stratix V (GS/GX/GT)") or (device = "STRATIX V (GS/GX/GT)") or (device = "stratix v (gs/gx/gt)") or (device = "Stratix V (GT/GS/GX)") or (device = "STRATIX V (GT/GS/GX)") or (device = "stratix v (gt/gs/gx)") or (device = "Stratix V (GT/GX/GS)") or (device = "STRATIX V (GT/GX/GS)") or (device = "stratix v (gt/gx/gs)") or (device = "Stratix V (GX/GS/GT)") or (device = "STRATIX V (GX/GS/GT)") or (device = "stratix v (gx/gs/gt)") or (device = "Stratix V (GX/GT/GS)") or (device = "STRATIX V (GX/GT/GS)") or (device = "stratix v (gx/gt/gs)") or (device = "StratixV(GS/GT/GX)") or (device = "STRATIXV(GS/GT/GX)") or (device = "stratixv(gs/gt/gx)") or (device = "StratixV(GS/GX/GT)") or (device = "STRATIXV(GS/GX/GT)") or (device = "stratixv(gs/gx/gt)") or (device = "StratixV(GT/GS/GX)") or (device = "STRATIXV(GT/GS/GX)") or (device = "stratixv(gt/gs/gx)") or (device = "StratixV(GT/GX/GS)") or (device = "STRATIXV(GT/GX/GS)") or (device = "stratixv(gt/gx/gs)") or (device = "StratixV(GX/GS/GT)") or (device = "STRATIXV(GX/GS/GT)") or (device = "stratixv(gx/gs/gt)") or (device = "StratixV(GX/GT/GS)") or (device = "STRATIXV(GX/GT/GS)") or (device = "stratixv(gx/gt/gs)"))
or ((device = "Arria II GZ") or (device = "ARRIA II GZ") or (device = "arria ii gz") or (device = "ArriaII GZ") or (device = "ARRIAII GZ") or (device = "arriaii gz") or (device = "Arria IIGZ") or (device = "ARRIA IIGZ") or (device = "arria iigz") or (device = "ArriaIIGZ") or (device = "ARRIAIIGZ") or (device = "arriaiigz"))
or ((device = "arriaiigz_commercial_v1_1") or (device = "ARRIAIIGZ_COMMERCIAL_V1_1"))
or ((device = "MAX V") or (device = "max v") or (device = "MAXV") or (device = "maxv") or (device = "Jade") or (device = "JADE") or (device = "jade"))
or ((device = "Arria V") or (device = "ARRIA V") or (device = "arria v") or (device = "ArriaV") or (device = "ARRIAV") or (device = "arriav")))
then
is_valid := true;
end if;
return is_valid;
end IS_VALID_FAMILY;
end LPM_DEVICE_FAMILIES;
-- END OF PACKAGE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_constant
--
-- Description : Parameterized constant generator megafunction. lpm_constant
-- may be useful for convert a parameter into a constant.
--
-- Limitation : n/a
--
-- results Expected: Value specified by the argument to lpm_cvalue.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CONSTANT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the result[] port. (Required)
lpm_cvalue : natural; -- Constant value to be driven out on the
-- result[] port. (Required)
lpm_strength : string := "UNUSED";
lpm_type : string := "LPM_CONSTANT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- // Value specified by the argument to lpm_cvalue. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_CONSTANT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CONSTANT is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= conv_std_logic_vector(lpm_cvalue, lpm_width);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inv
--
-- Description : Parameterized inverter megafunction.
--
-- Limitation : n/a
--
-- results Expected: Inverted value of input data.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_INV is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INV";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INV;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INV is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= not data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_and
--
-- Description : Parameterized AND gate. This megafunction takes in data inputs
-- for a number of AND gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each AND gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_and is
generic (
-- Width of the data[][] and result[] ports. Number of AND gates. (Required)
lpm_width : natural;
-- Number of inputs to each AND gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_AND";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the AND gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of the AND operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end lpm_and;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_and is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process; -- MSG process
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) and data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_or
--
-- Description : Parameterized OR gate megafunction. This megafunction takes in
-- data inputs for a number of OR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each OR gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_OR is
generic (
-- Width of the data[] and result[] ports. Number of OR gates. (Required)
lpm_width : natural;
-- Number of inputs to each OR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_OR";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the OR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of OR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0));
end LPM_OR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) or data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_xor
--
-- Description : Parameterized XOR gate megafunction. This megafunction takes in
-- data inputs for a number of XOR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each XOR gates.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_XOR is
generic (
-- Width of the data[] and result[] ports. Number of XOR gates. (Required)
lpm_width : natural;
-- Number of inputs to each XOR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_XOR";
lpm_hint : string := "UNUSED");
port (
-- data input to the XOR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- result of XOR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_XOR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_XOR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) xor data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bustri
--
-- Description : Parameterized tri-state buffer. lpm_bustri is useful for
-- controlling both unidirectional and bidirectional I/O bus
-- controllers.
--
-- Limitation : n/a
--
-- results Expected: Belows are the three configurations which are valid:
--
-- 1) Only the input ports data[lpm_width-1..0] and enabledt are
-- present, and only the output ports tridata[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabledt | tridata[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | data[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 2) Only the input ports tridata[lpm_width-1..0] and enabletr
-- are present, and only the output ports result[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabletr | result[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | tridata[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 3) All ports are present: input ports data[lpm_width-1..0],
-- enabledt, and enabletr; output ports result[lpm_width-1..0];
-- and bidirectional ports tridata[lpm_width-1..0].
--
-- ----------------------------------------------------------------------------
-- | Input | Bidirectional | Output |
-- |----------------------------------------------------------------------------|
-- | enabledt | enabletr | tridata[lpm_width-1..0] | result[lpm_width-1..0] |
-- |============================================================================|
-- | 0 | 0 | Z (input) | Z |
-- |----------------------------------------------------------------------------|
-- | 0 | 1 | Z (input) | tridata[lpm_width-1..0] |
-- |----------------------------------------------------------------------------|
-- | 1 | 0 | data[lpm_width-1..0] | Z |
-- |----------------------------------------------------------------------------|
-- | 1 | 1 | data[lpm_width-1..0] | data[lpm_width-1..0] |
-- ----------------------------------------------------------------------------
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_BUSTRI is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0 (Required)
lpm_type : string := "LPM_BUSTRI";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Bidirectional bus signal. (Required)
tridata : inout std_logic_vector(lpm_width-1 downto 0);
-- Data input to the tridata[] bus. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- If high, enables tridata[] onto the result bus.
enabletr : in std_logic := '1';
-- If high, enables data onto the tridata[] bus.
enabledt : in std_logic := '1';
-- Output from the tridata[] bus.
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BUSTRI;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BUSTRI is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- get the tri-state buffer output
BUSTRI: process(data, tridata, enabletr, enabledt)
begin
if enabledt = '0' and enabletr = '1' then
result <= tridata;
elsif enabledt = '1' and enabletr = '0' then
result <= (OTHERS => 'Z');
elsif enabledt = '1' and enabletr = '1' then
result <= data;
else
result <= (OTHERS => 'Z');
end if;
end process BUSTRI;
-- SIGNAL ASSIGNMENT
tridata <= data when (enabledt = '1')
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mux
--
-- Description : Parameterized multiplexer megafunctions.
--
-- Limitation : n/a
--
-- results Expected: Selected input port.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_MUX is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[][] and result[] ports. (Required)
lpm_size : natural; -- Number of input buses to the multiplexer. (Required)
lpm_widths : natural; -- Width of the sel[] input port. (Required)
lpm_pipeline : natural := 0;-- Specifies the number of Clock cycles of latency
-- associated with the result[] output.
lpm_type : string := "LPM_MUX";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Data input. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Selects one of the input buses. (Required)
sel : in std_logic_vector(lpm_widths-1 downto 0);
-- Clock for pipelined usage
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Selected input port. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_MUX;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MUX is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 1) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 1!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (aclr, clock, sel, data, clken)
variable resulttmp : t_resulttmp;
variable sel_int : integer;
begin
if (lpm_pipeline >= 0) then
sel_int := conv_integer(sel);
for i in 0 to lpm_width-1 loop
if (sel_int < lpm_size) then
resulttmp(lpm_pipeline)(i) := data(sel_int,i);
else
resulttmp(lpm_pipeline)(i) := 'X';
end if;
end loop;
if (lpm_pipeline > 0) then
if (aclr = '1') then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif (rising_edge(clock) and clken = '1') then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_decode
--
-- Description : Parameterized decoder megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Decoded output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_DECODE is
generic (
-- Width of the data[] port, or the input value to be decoded. (Required)
lpm_width : natural;
-- Number of explicit decoder outputs. (Required)
lpm_decodes : natural;
-- Number of Clock cycles of latency
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_DECODE";
lpm_hint : string := "UNUSED"
);
port (
-- Data input. Treated as an unsigned binary encoded number. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Enable. All outputs low when not active.
enable : in std_logic := '1';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Decoded output. (Required)
eq : out std_logic_vector(lpm_decodes-1 downto 0)
);
end LPM_DECODE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_DECODE is
-- TYPE DECLARATION
type t_eqtmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_decodes-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes <= 0) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes > (2**lpm_width)) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be less or equal to 2^lpm_width!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, data, enable)
variable eqtmp : t_eqtmp;
begin
for i in 0 to lpm_decodes-1 loop
if (conv_integer(data) = i) then
if (enable = '1') then
eqtmp(lpm_pipeline)(i) := '1';
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
end loop;
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
eqtmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
eqtmp(0 to lpm_pipeline - 1) := eqtmp(1 to lpm_pipeline);
end if;
end if;
eq <= eqtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_clshift
--
-- Description : Parameterized combinatorial logic shifter or barrel shifter
-- megafunction.
--
-- Limitation : n/a
--
-- results Expected: Return the shifted data and underflow/overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CLSHIFT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_widthdist : natural; -- Width of the distance[] input port.
-- MUST be greater than 0 (Required)
lpm_shifttype : string := "LOGICAL"; -- Type of shifting operation to be performed.
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency.
lpm_type : string := "LPM_CLSHIFT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- data to be shifted. (Required)
data : in STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Number of positions to shift data[] in the direction specified by the
-- direction port. (Required)
distance : in STD_LOGIC_VECTOR(lpm_widthdist-1 downto 0);
-- direction of shift. Low = left (toward the MSB), high = right (toward the LSB).
direction : in STD_LOGIC := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Shifted data. (Required)
result : out STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Logical or arithmetic underflow.
underflow : out STD_LOGIC;
-- Logical or arithmetic overflow.
overflow : out STD_LOGIC
);
end LPM_CLSHIFT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CLSHIFT is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal i_result : std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthdist <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthdist parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- Get the shifted data
process(data, distance, direction)
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
begin
if ((lpm_shifttype = "ARITHMETIC") or (lpm_shifttype = "LOGICAL")) then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance));
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= '0';
end if;
elsif (direction = '1') then
if ((i+tmpdist) < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
elsif (lpm_shifttype = "ARITHMETIC") then
i_result(i) <= data(lpm_width-1);
else
i_result(i) <= '0';
end if;
end if;
end loop;
elsif (lpm_shifttype = "ROTATE") then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance)) mod lpm_width;
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= tmpdata(i+lpm_width-tmpdist);
end if;
elsif (direction = '1') then
if (i+tmpdist < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
else
i_result(i) <= tmpdata(i-lpm_width+tmpdist);
end if;
end if;
end loop;
else
ASSERT FALSE
REPORT "Illegal lpm_shifttype property value for LPM_CLSHIFT!"
SEVERITY ERROR;
end if;
end process;
-- Get the overflow/underflow status bit.
process(aclr, clock, data, distance, direction, i_result)
variable neg_one : signed(lpm_width-1 downto 0) := (OTHERS => '1');
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
variable msb_cnt : integer := 0;
variable lsb_cnt : integer := 0;
variable sgn_bit : std_logic;
variable result_pipe : t_resulttmp := (OTHERS => (OTHERS => '0'));
variable overflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable underflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
begin
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(distance);
result_pipe(lpm_pipeline) := i_result;
overflow_pipe(lpm_pipeline) := '0';
underflow_pipe(lpm_pipeline) := '0';
if ((tmpdist /= 0) and (tmpdata /= 0)) then
if (lpm_shifttype = "ROTATE") then
overflow_pipe(lpm_pipeline) := 'U';
underflow_pipe(lpm_pipeline) := 'U';
else
if (tmpdist < lpm_width) then
if (lpm_shifttype = "LOGICAL") then
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = '0')) loop
msb_cnt := msb_cnt + 1;
end loop;
if ((tmpdist > msb_cnt) and (direction = '0')) then
overflow_pipe(lpm_pipeline) := '1';
elsif ((tmpdist + msb_cnt >= lpm_width) and (direction = '1')) then
underflow_pipe(lpm_pipeline) := '1';
end if;
elsif (lpm_shifttype = "ARITHMETIC") then
sgn_bit := '0';
if (tmpdata(lpm_width-1) = '1') then
sgn_bit := '1';
end if;
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = sgn_bit)) loop
msb_cnt := msb_cnt + 1;
end loop;
lsb_cnt := 0;
while ((lsb_cnt < lpm_width) and (tmpdata(lsb_cnt) = '0')) loop
lsb_cnt := lsb_cnt + 1;
end loop;
if (direction = '1') then -- shift right
if (tmpdata(lpm_width-1) = '1') then -- negative
if ((msb_cnt + tmpdist >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((msb_cnt + tmpdist) >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if;
elsif (direction = '0') then -- shift left
if (tmpdata(lpm_width-1) = '1') then -- negative
if (((signed(tmpdata) /= neg_one) and
(tmpdist >= lpm_width)) or (tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((tmpdata /= 0) and (tmpdist >= lpm_width-1)) or
(tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
end if;
end if;
end if;
else
if (direction = '0') then
overflow_pipe(lpm_pipeline) := '1';
elsif (direction = '1') then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if; -- tmpdist < lpm_width
end if; -- lpm_shifttype = "ROTATE"
end if; -- tmpdist /= 0 and tmpdata /= 0
if (aclr = '1') then
if (lpm_pipeline > 0) then
result_pipe := (OTHERS => (OTHERS => '0'));
overflow_pipe := (OTHERS => '0');
underflow_pipe := (OTHERS => '0');
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
result_pipe(0 to lpm_pipeline - 1) := result_pipe(1 to lpm_pipeline);
overflow_pipe(0 to lpm_pipeline - 1) := overflow_pipe(1 to lpm_pipeline);
underflow_pipe(0 to lpm_pipeline - 1) := underflow_pipe(1 to lpm_pipeline);
end if;
end if;
result <= result_pipe(0);
overflow <= overflow_pipe(0);
underflow <= underflow_pipe(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_signed
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for signed number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_SIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_SIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= (dataa(lpm_width) & dataa);
i_datab <= (datab(lpm_width) & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT"))and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtrator
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := (not resulttmp(lpm_pipeline)(lpm_width)) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- send the pipeline result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_unsigned
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for unsigned number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_UNSIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= ('0' & dataa);
i_datab <= ('0' & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtractor
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := not resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
overflowtmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1') ) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- Send the pipelined result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub
--
-- Description : Parameterized adder/subtractor megafunction.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_ADD_SUB_SIGNED;
use work.LPM_ADD_SUB_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_ADD_SUB is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_representation : string := "SIGNED";
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB is
-- COMPONENT DECLARATION
component LPM_ADD_SUB_SIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
component LPM_ADD_SUB_UNSIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "SIGNED") and
(lpm_representation /= "UNSIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: if (lpm_representation = "UNSIGNED") generate
U: LPM_ADD_SUB_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
L2: if (lpm_representation = "SIGNED") generate
V: LPM_ADD_SUB_SIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_signed
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "SIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_SIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_SIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (signed(dataa) > signed(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (signed(dataa) = signed(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_unsigned
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "UNSIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_UNSIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_UNSIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (unsigned(dataa) > unsigned(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (unsigned(dataa) = unsigned(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare
--
-- Description : Parameterized comparator megafunction. The comparator will
-- compare between data[] and datab[] and return the status of
-- comparation for the following operation.
-- 1) dataa[] < datab[].
-- 2) dataa[] == datab[].
-- 3) dataa[] > datab[].
-- 4) dataa[] >= datab[].
-- 5) dataa[] != datab[].
-- 6) dataa[] <= datab[].
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMPARE_SIGNED;
use work.LPM_COMPARE_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_COMPARE is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Type of comparison performed: "SIGNED", "UNSIGNED"
lpm_representation : string := "UNSIGNED";
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type: string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE is
-- COMPONENT DECLARATION
component LPM_COMPARE_SIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
component LPM_COMPARE_UNSIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "UNSIGNED") and (lpm_representation /= "SIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- instantiate LPM_COMPARE_UNSIGNED to perform "UNSIGNED" data comparison
L1: if lpm_representation = "UNSIGNED" generate
U1: LPM_COMPARE_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
-- instantiate LPM_COMPARE_SIGNED to perform "SIGNED" data comparison
L2: if lpm_representation = "SIGNED" generate
U2: LPM_COMPARE_SIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mult
--
-- Description : Parameterized multiplier megafunction.
--
-- Limitation : n/a
--
-- results Expected: dataa[] * datab[] + sum[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_MULT is
-- GENERIC DECLARATION
generic (
lpm_widtha : natural; -- Width of the dataa[] port. (Required)
lpm_widthb : natural; -- Width of the datab[] port. (Required)
lpm_widthp : natural; -- Width of the result[] port. (Required)
lpm_widths : natural := 1; -- Width of the sum[] port. (Required)
lpm_representation : string := "UNSIGNED"; -- Type of multiplication performed
lpm_pipeline : natural := 0; -- Number of clock cycles of latency
lpm_type : string := "LPM_MULT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Multiplicand. (Required)
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
-- Multiplier. (Required)
datab : in std_logic_vector(lpm_widthb-1 downto 0);
-- Partial sum.
sum : in std_logic_vector(lpm_widths-1 downto 0) := (OTHERS => '0');
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
result : out std_logic_vector(lpm_widthp-1 downto 0)
);
end LPM_MULT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MULT is
-- FUNCTION DECLARATION
function str2bin (constant i_str : in string;
constant i_width_str : in natural) return std_logic_vector is
variable binary_bits : std_logic_vector (255 downto 0) := (others => '0');
begin
if(i_str'length > 0) then
for i in 0 to (i_str'right - i_str'left) loop
if (i_str'left >= i) then
case i_str(i_str'right - i) is
when '0' => binary_bits(i) := '0';
when '1' => binary_bits(i) := '1';
when others => binary_bits(i) := 'X';
end case;
end if;
end loop;
end if;
return binary_bits(i_width_str -1 downto 0);
end str2bin;
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_widthp-1 downto 0);
-- CONSTANT DECLARATION
constant INPUT_A_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT");
constant INPUT_B_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT");
constant INPUT_A_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE");
constant INPUT_B_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE");
constant DATAA_FIXED : std_logic_vector(lpm_widtha-1 downto 0) := str2bin(INPUT_A_FIXED_VALUE, lpm_widtha);
constant DATAB_FIXED : std_logic_vector(lpm_widthb-1 downto 0) := str2bin(INPUT_B_FIXED_VALUE, lpm_widthb);
-- SIGNAL DECLARATION
signal i_dataa : std_logic_vector(lpm_widtha-1 downto 0);
signal i_datab : std_logic_vector(lpm_widthb-1 downto 0);
begin
i_dataa <= dataa when (INPUT_A_IS_CONSTANT /= "FIXED")
else DATAA_FIXED;
i_datab <= datab when (INPUT_B_IS_CONSTANT /= "FIXED")
else DATAB_FIXED;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widtha <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widtha parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthb <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthb parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthp <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthp parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (clock, aclr, i_dataa, i_datab, sum)
variable resulttmp : T_RESULTTMP;
variable tmp_prod_ab : std_logic_vector(lpm_widtha+lpm_widthb downto 0);
variable tmp_prod_s : std_logic_vector(lpm_widths downto 0);
variable tmp_prod_p : std_logic_vector(lpm_widthp-1 downto 0);
variable tmp_use : integer;
begin
if (lpm_representation = "SIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := signed(i_dataa) * signed(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := tmp_prod_ab(lpm_widtha+lpm_widthb-1);
elsif (lpm_representation = "UNSIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := unsigned(i_dataa) * unsigned(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := '0';
else
ASSERT FALSE
REPORT "Illegal lpm_representation property value for LPM_MULT!"
SEVERITY ERROR;
end if;
tmp_use := 1; --AB
if (lpm_widths > (lpm_widtha+lpm_widthb)) then
if (lpm_representation = "SIGNED") then
tmp_prod_s := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := signed(tmp_prod_s) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_s(lpm_widths));
else
tmp_prod_s := (OTHERS => '0');
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := unsigned(tmp_prod_s) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
tmp_use := 2; --S
elsif (lpm_widths > 0) then
if (lpm_representation = "SIGNED") then
tmp_prod_ab := signed(tmp_prod_ab) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
else
tmp_prod_ab := unsigned(tmp_prod_ab) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
end if;
if (tmp_use = 2) then --S
if (lpm_widthp > lpm_widths) then
tmp_prod_p(lpm_widths downto 0) := tmp_prod_s;
elsif (lpm_widthp = lpm_widths) then
tmp_prod_p := tmp_prod_s(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_s(lpm_widths-1 downto lpm_widths-lpm_widthp);
end if;
else --AB
if (lpm_widthp > (lpm_widtha+lpm_widthb)) then
tmp_prod_p(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab(lpm_widtha+lpm_widthb downto 0);
elsif (lpm_widthp = lpm_widtha+lpm_widthb) then
tmp_prod_p := tmp_prod_ab(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto lpm_widtha+lpm_widthb-lpm_widthp);
end if;
end if;
resulttmp(lpm_pipeline) := tmp_prod_p;
-- Pipelining the result of multiplication
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if((clken = '1') and (lpm_pipeline > 0) and (now > 0 ns)) then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_divide
--
-- Description : Parameterized divider megafunction. This function performs a
-- divide operation such that denom * quotient + remain = numer
-- The function allows for all combinations of signed(two's
-- complement) and unsigned inputs. If any of the inputs is
-- signed, the output is signed. Otherwise the output is unsigned.
-- The function also allows the remainder to be specified as
-- always positive (in which case remain >= 0); otherwise remain
-- is zero or the same sign as the numerator
-- (this parameter is ignored in the case of purely unsigned
-- division). Finally the function is also pipelinable.
--
-- Limitation : n/a
--
-- Results Expected: Return quotient and remainder.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_DIVIDE is
generic (
lpm_widthn : natural; -- Width of the numer[] and quotient[] port. (Required)
lpm_widthd : natural; -- Width of the denom[] and remain[] port. (Required)
lpm_nrepresentation : string := "UNSIGNED"; -- The representation of numer
lpm_drepresentation : string := "UNSIGNED"; -- The representation of denom
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency
lpm_type : string := "LPM_DIVIDE";
lpm_hint : string := "LPM_REMAINDERPOSITIVE=TRUE"
);
port (
numer : in std_logic_vector(lpm_widthn-1 downto 0); -- The numerator (Required)
denom : in std_logic_vector(lpm_widthd-1 downto 0); -- The denominator (Required)
clock : in std_logic := '0'; -- Clock input for pipelined usage
aclr : in std_logic := '0'; -- Asynchronous clear signal
clken : in std_logic := '1'; -- Clock enable for pipelined usage
quotient : out std_logic_vector(lpm_widthn-1 downto 0); -- Quotient (Required)
remain : out std_logic_vector(lpm_widthd-1 downto 0) -- Remainder (Required)
);
end LPM_DIVIDE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture behave of lpm_divide is
-- CONSTANT DECLARATION
constant MAX_WIDTH : integer := 256;
constant LPM_REMAINDERPOSITIVE : string := GET_PARAMETER_VALUE(LPM_HINT, "LPM_REMAINDERPOSITIVE");
-- TYPE DECLARATION
type QPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthn-1 downto 0);
type RPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthd-1 downto 0);
-- SIGNAL DECLARATION
signal quotient_pipe : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal quotient_value : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal remainder_pipe : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
signal remainder_value : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
-- FUNCTION DECLARATION
-- Bitwise left shift
procedure shift_left ( val : inout std_logic_vector; num : in integer) is
variable temp : std_logic_vector((val'length - 1) downto 0);
begin
if num /= 0 then
temp := val;
if (val'length > 1) then
for i in temp'high downto num loop
temp(i) := temp(i- num);
end loop;
for i in num-1 downto 0 loop
temp(i) := '0';
end loop;
end if;
temp(0) :='0';
val := temp;
end if;
end shift_left;
-- Bitwise right shift
procedure shift_right ( val : inout std_logic_vector ) is
variable temp : std_logic_vector(val'length-1 downto 0);
begin
temp := val;
if (val'length > 1) then
for i in 0 to temp'high - 1 loop
temp(i) := temp(i+1);
end loop;
end if;
temp(temp'high) := '0';
val := temp;
end shift_right;
begin
-- SIGNAL ASSIGNMENTS
quotient <= quotient_pipe when (lpm_pipeline > 0) else quotient_value;
remain <= remainder_pipe when (lpm_pipeline > 0) else remainder_value;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widthn <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthn parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthd <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthd parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((LPM_REMAINDERPOSITIVE /= "TRUE") and
(LPM_REMAINDERPOSITIVE /= "FALSE")) then
ASSERT FALSE
REPORT " LPM_REMAINDERPOSITIVE value must be TRUE or FALSE!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (numer, denom)
variable i_denom : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable i_quotient : std_logic_vector(lpm_widthn-1 downto 0) := (OTHERS => '0');
variable i_remain : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable sign_numer : std_logic;
variable sign_denom : std_logic;
variable trailing_zero_count : integer;
variable int_numer, int_denom, int_quotient, int_remain : integer := 0;
variable signed_quotient : signed(lpm_widthn-1 downto 0);
variable unsigned_quotient : unsigned(lpm_widthn-1 downto 0);
begin
if ((lpm_widthn < 32) and (lpm_widthd < 32)) then
-- perform division using integer division.
if (lpm_nrepresentation = "UNSIGNED") then
int_numer := conv_integer(unsigned(numer));
elsif (lpm_nrepresentation = "SIGNED") then
int_numer := conv_integer(signed(numer));
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
int_denom := conv_integer(unsigned(denom));
elsif (lpm_drepresentation = "SIGNED") then
int_denom := conv_integer(signed(denom));
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (int_denom = 0) then
remainder_value <= (OTHERS => 'X');
quotient_value <= (OTHERS => 'X');
else
int_quotient := int_numer / int_denom;
int_remain := int_numer rem int_denom;
-- LPM 220 standard
if ((LPM_REMAINDERPOSITIVE="TRUE") and (int_remain < 0)) then
if (int_denom < 0) then
int_quotient := int_quotient + 1;
else
int_quotient := int_quotient - 1;
end if;
int_remain := int_numer - (int_quotient*int_denom);
end if;
signed_quotient := conv_signed(int_quotient, lpm_widthn);
unsigned_quotient := conv_unsigned(int_quotient, lpm_widthn);
remainder_value <= conv_std_logic_vector(int_remain, lpm_widthd);
if ((lpm_nrepresentation = "UNSIGNED") and (lpm_drepresentation = "UNSIGNED")) then
quotient_value <= conv_std_logic_vector(unsigned_quotient, lpm_widthn);
else
quotient_value <= conv_std_logic_vector(signed_quotient, lpm_widthn);
end if;
end if;
else
-- perform division using long division algorithm
sign_numer := '0';
sign_denom := '0';
trailing_zero_count := 0;
i_quotient := (OTHERS => '0');
i_denom := (OTHERS => '0');
i_remain := (OTHERS => '0');
if (lpm_nrepresentation = "UNSIGNED") then
i_remain(lpm_widthn -1 downto 0) := numer;
elsif (lpm_nrepresentation = "SIGNED") then
if (numer(lpm_widthn-1) = '1') then
i_remain(lpm_widthn -1 downto 0) := not numer + 1;
sign_numer := '1';
else
i_remain(lpm_widthn -1 downto 0) := numer;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
elsif (lpm_drepresentation = "SIGNED") then
if (denom(lpm_widthd-1) = '1') then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := not denom + 1;
sign_denom := '1';
else
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
-- if divide with zero, set quotient to all 'X'
if (i_denom = 0) then
i_quotient := (OTHERS => 'X');
i_remain := (OTHERS => 'X');
elsif (numer = 0) then
i_quotient := (OTHERS => '0');
else
-- get number of zero bits in the denom
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-lpm_widthd + i) /= '0') then
trailing_zero_count := i;
exit;
end if;
end loop;
-- shift the i_denom until the first non-zero bit become leftmost bit.
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-1-i) /= '0') then
shift_left(i_denom, i);
exit;
end if;
end loop;
-- perform division
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
while (i_denom(trailing_zero_count) = '0') loop
shift_right(i_denom);
shift_left(i_quotient, 1);
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
end loop;
-- quotient is negative number if either numer or denom (but not both)
-- is negative number
if ((sign_numer xor sign_denom) = '1') then
i_quotient := not i_quotient + 1;
end if;
-- LPM 220 standard
if ((sign_numer = '1') and (i_remain /= 0)) then
if (LPM_REMAINDERPOSITIVE = "TRUE") then
if (sign_denom = '1') then
i_quotient := i_quotient + 1;
else
i_quotient := i_quotient - 1;
end if;
i_remain := i_denom - i_remain;
else
i_remain := not i_remain + 1;
end if;
end if;
end if;
remainder_value <= i_remain(lpm_widthd -1 downto 0);
quotient_value <= i_quotient;
end if;
end process;
process (aclr, clock)
variable tmp_quotient : QPIPELINE := (OTHERS => (OTHERS => '0'));
variable tmp_remain : RPIPELINE := (OTHERS => (OTHERS => '0'));
begin
if (aclr = '1') then
if (lpm_pipeline > 0) then
-- clear the pipeline
for i in 0 to lpm_pipeline loop
tmp_quotient(i) := (OTHERS => '0');
tmp_remain(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if (lpm_pipeline > 0) then
if (clken = '1') then
-- pipeline the result
tmp_remain(lpm_pipeline) := remainder_value;
tmp_quotient(lpm_pipeline) := quotient_value;
tmp_quotient(0 to lpm_pipeline-1) := tmp_quotient(1 to lpm_pipeline);
tmp_remain(0 to lpm_pipeline-1) := tmp_remain(1 to lpm_pipeline);
end if;
end if;
end if;
quotient_pipe <= tmp_quotient(0);
remainder_pipe <= tmp_remain(0);
end process;
end behave;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_abs
--
-- Description : Parameterized absolute value megafunction. This megafunction
-- requires the input data to be signed number.
--
-- Limitation :
--
-- results Expected: Return absolute value of data and the overflow status
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_abs is
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_type : string := "LPM_ABS";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0); -- (Required)
result : out std_logic_vector(lpm_width-1 downto 0); -- (Required)
overflow : out std_logic
);
end LPM_ABS;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ABS is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
GENERATE_ABS : process(data)
begin
if (data(lpm_width-1) = '1') then
if (lpm_width = 1) then
overflow <= '1';
result <= data;
elsif ((lpm_width > 1) and (data(lpm_width -2 downto 0) = 0)) then
overflow <= '1';
result <= data;
else
result <= 0 - data;
overflow <= '0';
end if;
else
result <= data;
overflow <= '0';
end if;
end process GENERATE_ABS;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_counter
--
-- Description : Parameterized counter megafunction. The lpm_counter
-- megafunction is a binary counter that features an up,
-- down, or up/down counter with optional synchronous or
-- asynchronous clear, set, and load ports.
--
-- Limitation : n/a
--
-- Results Expected: data output from the counter and carry-out of the MSB.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_COUNTER is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_modulus : natural := 0;
lpm_avalue : string := "UNUSED";
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_port_updown : string := "PORT_CONNECTIVITY";
lpm_type : string := "LPM_COUNTER";
lpm_hint : string := "UNUSED"
);
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
data : in std_logic_vector(lpm_width-1 downto 0):= (OTHERS => '0');
cin : in std_logic := '1';
q : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic := '0';
eq : out std_logic_vector(15 downto 0) := (OTHERS => '0')
);
end LPM_COUNTER;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COUNTER is
-- CONSTANT DECLARATION
constant ONES : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+5 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+4 downto 0) := unsigned(ivalue(lpm_width downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal count : std_logic_vector(lpm_width downto 0);
signal dir : std_logic_vector(1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_modulus < 0) then
ASSERT FALSE
REPORT "Value of lpm_modulus parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
if(lpm_width < 31) then
if (lpm_modulus > 2**lpm_width) then
ASSERT FALSE
REPORT "LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input."
SEVERITY WARNING;
end if;
end if;
wait;
end process MSG;
DIRECTION: process (updown)
begin
if (lpm_port_updown = "PORT_USED") then
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
dir(1) <= '1'; -- unknown
end if;
elsif (lpm_port_updown = "PORT_UNUSED") then
if (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir <= "01"; -- increment
end if;
else
if (lpm_direction = "UP") then
dir <= "01"; -- increment
elsif (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
if ((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) then
dir <= "01"; -- default to increment
else
dir(1) <= '1'; -- unknown
end if;
end if;
end if;
end if;
end process DIRECTION;
COUNTER: process (clock, aclr, aset, aload, data)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
variable avalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = false) then
-- Initialize to pvalue and setup variables
if (lpm_pvalue /= "UNUSED") then
count <= pvalue;
else
count <= (OTHERS => '0');
end if;
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
-- Check parameters validity
if ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT") and
(lpm_direction /= "UP") and (lpm_direction /= "DOWN")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for lpm_counter!"
SEVERITY ERROR;
end if;
init := true;
end if;
if (aclr = '1') then
count <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= avalue;
end if;
elsif (aload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (clock'event and (clock = '1')) then
if (clk_en = '1') then
if (sclr = '1') then
count <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= svalue;
end if;
elsif (sload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (cnt_en = '1') then
if (imodulus = 1) then
count <= (OTHERS => '0');
elsif (cin = '1') then
if ((dir(0) = '1') and (dir(1) = '0')) then
-- Increase the count
if (((lpm_modulus = 0) and (unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES))) or
((lpm_modulus /= 0) and ((count + 1) = imodulus))) then
count <= conv_std_logic_vector(0, lpm_width+1);
else
count <= count + 1;
end if;
elsif ((dir(0) = '0') and (dir(1) = '0')) then
-- Decrease the count
if (count = 0) then
if (lpm_modulus /= 0) then
count <= conv_std_logic_vector(imodulus-1, lpm_width+1);
else
count <= (OTHERS => '1');
end if;
else
count <= count - 1;
end if;
end if;
end if;
end if;
end if;
end if;
count(lpm_width) <= '0';
end process COUNTER;
CARRYOUT: process (count, cin, dir)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
begin
if (init = false) then
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
init := true;
end if;
if (dir(1) = '0') then
cout <= '0';
if (imodulus = 1) then
cout <= '1';
elsif (cin = '1') then
if (((dir(0) = '0') and (count = 0)) or
((dir(0) = '1') and (((count = imodulus - 1) and (lpm_modulus /= 0)) or
((lpm_modulus = 0) and
(unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES)))) )) then
cout <= '1';
end if;
end if;
end if;
end process CARRYOUT;
q <= count(lpm_width-1 downto 0);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_latch
--
-- Description : Parameterized latch megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the latch.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_LATCH is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and q[] ports. (Required)
lpm_avalue : string := "UNUSED"; -- Constant value that is loaded when aset is high.
lpm_pvalue : string := "UNUSED";
lpm_type : string := "LPM_LATCH";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
gate : in std_logic;
aclr : in std_logic := '0';
aset : in std_logic := '0';
aconst : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_LATCH;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_LATCH is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal init : std_logic := '0';
signal tmp_init: std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (data, gate, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
-- initialize to pvalue
q <= pvalue;
end if;
tmp_init <= '1';
else
if (aclr = '1') then
q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
q <= (OTHERS => '1');
else
q <= avalue;
end if;
elsif (gate = '1') then
q <= data;
end if;
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ff
--
-- Description : Parameterized flipflop megafunction. The lpm_ff function
-- contains features that are not available in the DFF, DFFE,
-- DFFEA, TFF, and TFFE primitives, such as synchronous or
-- asynchronous set, clear, and load inputs.
--
-- Limitation : n/a
--
-- Results Expected: Data output from D or T flipflops.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_FF is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
-- Type of flipflop.
lpm_fftype : string := "DFF";
lpm_type : string := "LPM_FF";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
clock : in std_logic;
enable : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_FF;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_FF is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal iq : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (data, clock, aclr, aset, aload)
variable init : std_logic := '0';
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- INITIALIZE TO PVALUE --
if (init = '0') then
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of LPM_WIDTH parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_fftype /= "DFF") and (lpm_fftype /= "TFF")) then
ASSERT FALSE
REPORT "Illegal LPM_FFTYPE property value for LPM_FF!"
SEVERITY ERROR;
end if;
if (lpm_pvalue /= "UNUSED") then
iq <= pvalue;
end if;
init := '1';
end if;
if (aclr = '1') then
iq <= (OTHERS => '0');
elsif (aclr = 'X') then
iq <= (OTHERS => 'X');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= avalue;
end if;
elsif (aload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
elsif ((aclr = '0') and (now = 0 ps)) then
if (lpm_pvalue = "UNUSED") then
iq <= (OTHERS => '0');
else
iq <= pvalue;
end if;
elsif (clock'event and (clock = '1') and (NOW > 0 ns)) then
if (enable = '1') then
if (sclr = '1') then
iq <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= svalue;
end if;
elsif (sload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
else
if (lpm_fftype = "TFF") then
for i in 0 to lpm_width-1 loop
if (data(i) = '1') then
iq(i) <= not iq(i);
end if;
end loop;
else
iq <= data;
end if;
end if;
end if;
end if;
end process;
q <= iq;
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_shiftreg
--
-- Description : Parameterized shift register megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the shift register and the Serial shift data output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_SHIFTREG is
generic (
-- Width of the data[] and q ports. (Required)
lpm_width : natural;
lpm_direction : string := "LEFT";
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_type : string := "L_SHIFTREG";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the shift register.
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- Positive-edge-triggered clock. (Required)
clock : in std_logic;
-- Clock enable input
enable : in std_logic := '1';
-- Serial shift data input.
shiftin : in std_logic := '1';
-- Synchronous parallel load. High (1): load operation; low (0): shift operation.
load : in std_logic := '0';
-- Asynchronous clear input.
aclr : in std_logic := '0';
-- Asynchronous set input.
aset : in std_logic := '0';
-- Synchronous clear input.
sclr : in std_logic := '0';
-- Synchronous set input.
sset : in std_logic := '0';
-- Data output from the shift register.
q : out std_logic_vector(lpm_width-1 downto 0);
-- Serial shift data output.
shiftout : out std_logic
);
end LPM_SHIFTREG;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_SHIFTREG is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal i_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal init : std_logic := '0';
signal tmp_init : std_logic := '0';
signal i_shiftout_pos : natural := lpm_width-1;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (clock, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- initIALIZE TO PVALUE --
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
i_q <= pvalue;
end if;
if ((lpm_direction = "LEFT") or (lpm_direction = "UNUSED")) then
i_shiftout_pos <= lpm_width-1;
elsif (lpm_direction = "RIGHT") then
i_shiftout_pos <= 0;
else
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_SHIFTREG!"
SEVERITY ERROR;
end if;
tmp_init <= '1';
elsif (aclr = '1') then
i_q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= avalue;
end if;
elsif (rising_edge(clock)) then
if (enable = '1') then
if (sclr = '1') then
i_q <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= svalue;
end if;
elsif (load = '1') then
i_q <= data;
else
if (lpm_width < 2) then
i_q(0) <= shiftin;
elsif (lpm_direction = "LEFT") then
i_q <= (i_q(lpm_width-2 downto 0) & shiftin);
else
i_q <= (shiftin & i_q(lpm_width-1 downto 1));
end if;
end if;
end if;
end if;
end process;
q <= i_q;
shiftout <= i_q(i_shiftout_pos);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dq
--
-- Description : Parameterized RAM with separate input and output ports megafunction.
-- lpm_ram_dp implement asynchronous memory or memory with synchronous
-- inputs and/or outputs.
--
-- Limitation : n/a
--
-- Results Expected: data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DQ is
generic (
-- Width of data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the address port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Controls whether the data port is registered.
lpm_indata : string := "REGISTERED";
-- Controls whether the address and we ports are registered.
lpm_address_control: string := "REGISTERED";
-- Controls whether the q ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
intended_device_family : string := "UNUSED";
lpm_type : string := L_RAM_DQ;
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Address input to the memory. (Required)
address : in std_logic_vector(lpm_widthad-1 downto 0);
-- Synchronizes memory loading.
inclock : in std_logic := '0';
-- Synchronizes q outputs from memory.
outclock : in std_logic := '0';
-- Write enable input. Enables write operations to the memory when high. (Required)
we : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DQ;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_ram_dq is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown intended_device_family " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
SYNC: process( data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= data;
else
ASSERT FALSE
REPORT "Illegal lpm_indata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, we_tmp, address_tmp, inclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if not (mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (lpm_file /= "UNUSED") then
FILE_OPEN(mem_data_file, lpm_file, READ_MODE);
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'low) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
FILE_CLOSE(mem_data_file);
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (we_tmp = '1') then
if (((use_eab = "ON") or
(lpm_hint = "use_eab=ON")) and (lpm_address_control = "REGISTERED")) then
if (inclock = '0') then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp;
end if;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dp
--
-- Description : Parameterized dual-port RAM megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DP is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the rdaddress[] and wraddress[] ports. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Determines the clock used by the data port.
lpm_indata : string := "REGISTERED";
-- Determines the clock used by the rdaddress and rden ports.
lpm_rdaddress_control : string := "REGISTERED";
-- Determines the clock used by the wraddress and wren ports.
lpm_wraddress_control : string := "REGISTERED";
-- Determines the clock used by the q[] port.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
-- Specified whether to use the rden port or not.
rden_used : string := "TRUE";
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_RAM_DP";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Read address input to the memory. (Required)
rdaddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Write address input to the memory. (Required)
wraddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Positive-edge-triggered clock for read operation.
rdclock : in std_logic := '0';
-- Clock enable for rdclock.
rdclken : in std_logic := '1';
-- Positive-edge-triggered clock for write operation.
wrclock : in std_logic := '0';
-- Clock enable for wrclock.
wrclken : in std_logic := '1';
-- Read enable input. Disables reading when low (0).
rden : in std_logic := '1';
-- Write enable input. (Required)
wren : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DP;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_RAM_DP is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal rdaddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal rdaddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wraddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal wraddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wren_tmp : std_logic;
signal wren_reg : std_logic := '0';
signal rden_tmp : std_logic;
signal rden_reg : std_logic := '0';
begin
-- SIGNAL ASSIGNMENTS
rden_tmp <= '1' when (rden_used = "FALSE")
else rden when (lpm_rdaddress_control = "UNREGISTERED")
else rden_reg;
rdaddress_tmp <= rdaddress when (lpm_rdaddress_control = "UNREGISTERED")
else rdaddress_reg;
wren_tmp <= wren when (lpm_wraddress_control = "UNREGISTERED")
else wren_reg;
wraddress_tmp <= wraddress when (lpm_wraddress_control = "UNREGISTERED")
else wraddress_reg;
data_tmp <= data when (lpm_indata = "UNREGISTERED")
else data_reg;
q <= q_tmp when (lpm_outdata = "UNREGISTERED")
else q_reg;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_indata /= "REGISTERED") and (lpm_indata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value lpm_indata must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_outdata /= "REGISTERED") and (lpm_outdata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_outdata parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_wraddress_control /= "REGISTERED") and
(lpm_wraddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_wraddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_rdaddress_control /= "REGISTERED") and
(lpm_rdaddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_rdaddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
INPUT_REG: process (wrclock)
begin
if (wrclock'event and (wrclock = '1')) then
if (wrclken = '1') then
data_reg <= data;
wraddress_reg <= wraddress;
wren_reg <= wren;
end if;
end if;
end process INPUT_REG;
OUTPUT_REG: process (rdclock)
begin
if (rdclock'event and (rdclock = '1')) then
if (rdclken = '1') then
rdaddress_reg <= rdaddress;
rden_reg <= rden;
q_reg <= q_tmp;
end if;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, wren_tmp, rdaddress_tmp, wraddress_tmp, rden_tmp, wrclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum : string(2 downto 1) := " ";
variable startadd : string(4 downto 1) := " ";
variable ibase : integer := 0;
variable ibyte : integer := 0;
variable istartadd : integer := 0;
variable check_sum_vec, check_sum_vec_tmp : std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((use_eab = "ON") or (lpm_hint = "use_eab=ON")) then
q_tmp <= (others => '1');
end if;
if (lpm_file /= "UNUSED") then
FILE_OPEN(mem_data_file, lpm_file, READ_MODE);
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00" => -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
FILE_CLOSE(mem_data_file);
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (wren_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "use_eab=ON")) and
(lpm_wraddress_control = "REGISTERED")) then
if (wrclock = '0') then
mem_data (conv_integer(wraddress_tmp)) := data_tmp;
end if;
else
mem_data (conv_integer(wraddress_tmp)) := data_tmp ;
end if;
end if;
if ((rden_tmp = '1') or (rden_used = "FALSE")) then
q_tmp <= mem_data(conv_integer(rdaddress_tmp));
end if;
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_io
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
entity LPM_RAM_IO is
generic ( LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_IO";
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port ( ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
OUTENAB : in STD_LOGIC := 'Z';
WE : in STD_LOGIC := 'Z';
DIO : inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end LPM_RAM_IO;
architecture LPM_SYN of lpm_ram_io is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, di, do : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp, q : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
signal memenab_tmp : std_logic;
signal memenab_reg : std_logic := '0';
signal outenab_used : std_logic;
-- provided for MP2 compliance
signal we_used : std_logic;
begin
sync: process( di, data_reg, address, address_reg, memenab, memenab_reg,
we,we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
memenab_tmp <= memenab_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
memenab_tmp <= memenab;
else
ASSERT FALSE
REPORT "Illegal LPM_ADDRESS_CONTROL property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= di;
else
ASSERT FALSE
REPORT "Illegal LPM_INDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal LPM_OUTDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= di;
address_reg <= address;
we_reg <= we;
memenab_reg <= memenab;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
INITIALIZE : process(we, outenab)
variable init : boolean := FALSE;
begin
if NOT (init) then
if (outenab = 'Z' and we = 'Z') then
ASSERT FALSE
REPORT "One of OutEnab or WE must be used!"
SEVERITY ERROR;
end if;
-- In reality, both are needed in current TDF implementation
if (outenab /= 'Z' and we /= 'Z') then
ASSERT FALSE
REPORT "Only one of OutEnab or WE should be used!"
-- Change severity to ERROR for full LPM 220 compliance
SEVERITY WARNING;
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
ASSERT FALSE
REPORT "WE is required!"
SEVERITY WARNING;
end if;
if (outenab = 'Z') then
outenab_used <= '0';
we_used <= '1';
else
outenab_used <= '1';
we_used <= '0';
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
we_used <= '0';
else
we_used <= '1';
end if;
init := TRUE;
end if;
end process;
memory: process(data_tmp, we_tmp, memenab_tmp, outenab, address_tmp, inclock, we_used, outenab_used)
variable mem_data : lpm_memory;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i,j,k,n,m,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE /= "UNUSED") then
FILE_OPEN(mem_data_file, LPM_FILE, READ_MODE);
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
FILE_CLOSE(mem_data_file);
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (((we_used = '1' and we_tmp = '1')
or (outenab_used = '1' and we_used = '0' and outenab = '0'))
and memenab_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "USE_EAB=ON")) and (lpm_address_control = "REGISTERED")) then
if inclock = '0' then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
q_tmp <= data_tmp ;
else
q_tmp <= mem_data(conv_integer(address_tmp)) ;
end if;
end process;
di <= dio when ((outenab_used = '0' and we = '1')
or (outenab_used = '1' and outenab = '0'))
else (OTHERS => 'Z');
do <= q when memenab_tmp = '1' else (OTHERS => 'Z') ;
dio <= do when ((outenab_used = '0' and we = '0')
or (outenab_used = '1' and outenab = '1'))
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_rom
--
-- Description : Parameterized ROM megafunction. This megafunction is provided
-- only for backward compatibility in Cyclone, Stratix, and
-- Stratix GX designs; instead, Altera recommends using the
-- altsyncram megafunction.
--
-- Limitation : This option is available for all Altera devices supported by
-- the Quartus II software except MAX 3000 and MAX 7000 devices.
--
-- Results Expected: Output of memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_ROM is
generic (
-- Width of the q[] port. (Required)
lpm_width : natural;
-- Width of the address[] port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Indicates whether the address port is registered.
lpm_address_control : string := "REGISTERED";
-- Indicates whether the q and eq ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the memory file containing ROM initialization data
lpm_file : string;
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_ROM";
lpm_hint : string := "UNUSED"
);
port (
-- Address input to the memory. (Required)
address : in STD_LOGIC_VECTOR(lpm_widthad-1 downto 0);
-- Clock for input registers.
inclock : in STD_LOGIC := '0';
-- Clock for output registers.
outclock : in STD_LOGIC := '0';
-- Memory enable input.
memenab : in STD_LOGIC := '1';
-- Output of memory. (Required)
q : out STD_LOGIC_VECTOR(lpm_width-1 downto 0)
);
end LPM_ROM;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_rom is
-- FUNCTION DECLARATION
--- Get the number of word stored in memory ---
function get_num_words (constant i_lpm_numwords,
i_lpm_widthad : in natural) return natural is
variable i_num_words : natural;
begin
if (i_lpm_numwords = 0) then
i_num_words := (2**lpm_widthad);
elsif (i_lpm_numwords > 0) then
i_num_words := i_lpm_numwords;
else
ASSERT FALSE
REPORT "Value of lpm_numwords parameter must be greater than 0!"
SEVERITY ERROR;
end if;
return i_num_words;
end get_num_words;
-- CONSTANT DECLARATION
constant NUM_WORDS : natural := get_num_words(lpm_numwords, lpm_widthad);
-- TYPE DECLARATION
type LPM_MEMORY is array(NUM_WORDS-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
if (FEATURE_FAMILY_MAX(intended_device_family) = true) then
ASSERT FALSE
REPORT "LPM_ROM megafunction does not support " & intended_device_family & " devices"
SEVERITY ERROR;
end if;
wait;
end process MSG;
ENABLE_MEM: process(memenab, q2)
begin
if (memenab = '1') then
q <= q2;
else
q <= (OTHERS => 'Z');
end if;
end process ENABLE_MEM;
SYNC: process(address, address_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q2 <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q2 <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
address_reg <= address;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(memenab, address_tmp)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- check for number of words out of bound
if ((NUM_WORDS > (2**lpm_widthad)) or
(NUM_WORDS <= (2**(lpm_widthad-1)))) then
ASSERT FALSE
REPORT "The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD!"
SEVERITY ERROR;
end if;
-- Initialize to zero
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((lpm_file = "UNUSED") or (lpm_file = "")) then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY ERROR;
else
FILE_OPEN(mem_data_file, lpm_file, READ_MODE);
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
FILE_CLOSE(mem_data_file);
end if;
mem_init := TRUE;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_FIFO is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_type : string := "LPM_FIFO";
lpm_hint : string := "");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0);
full : out std_logic;
empty : out std_logic);
end LPM_FIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO is
-- TYPE DECLARATION
type lpm_memory is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_overflow_checking;
function get_allow_rwcycle_when_full return string is
constant param_value : string := get_parameter_value(LPM_HINT, "ALLOW_RWCYCLE_WHEN_FULL");
begin
if ( param_value /= "") then
return param_value;
else
return "OFF";
end if;
end get_allow_rwcycle_when_full;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant UNKNOWNS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X');
constant underflow_checking : string := get_underflow_checking;
constant overflow_checking : string := get_overflow_checking;
constant allow_rwcycle_when_full : string := get_allow_rwcycle_when_full;
constant intended_device_family : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_count_id : integer := 0;
signal i_read_id : integer := 0;
signal i_write_id : integer := 0;
signal i_full_flag : std_logic := '0';
signal i_empty_flag : std_logic := '1';
signal i_tmp_q : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
begin
-- PROCESS DECLARATION
process (clock, aclr)
-- VARIABLE DECLARATION
variable mem_data : lpm_memory := (OTHERS => ZEROS);
variable tmp_data : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
variable write_id : integer := 0;
variable write_flag : boolean := false;
variable full_flag : boolean := false;
variable valid_rreq : boolean := false;
variable valid_wreq : boolean := false;
variable max_widthu : integer := 0;
variable numwords_minus_one : integer := 0;
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) then
ASSERT FALSE
REPORT "Illegal LPM_SHOWAHEAD property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal UNDERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal OVERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((allow_rwcycle_when_full /= "ON") and (allow_rwcycle_when_full /= "OFF")) then
ASSERT FALSE
REPORT "Illegal ALLOW_RWCYCLE_WHEN_FULL property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Illegal INTENDED_DEVICE_FAMILY for LPM_FIFO!"
SEVERITY ERROR;
end if;
for i in 0 to (lpm_widthu - 1) loop
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
mem_data(i) := UNKNOWNS;
else
mem_data(i) := ZEROS;
end if;
end loop;
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
i_tmp_q <= UNKNOWNS;
else
i_tmp_q <= ZEROS;
end if;
max_widthu := (2 ** lpm_widthu) - 1;
numwords_minus_one := lpm_numwords - 1;
need_init := false;
end if; -- need_init
if (aclr = '1') then
full_flag := false;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) then
i_tmp_q <= ZEROS;
end if;
write_id := 0;
if (lpm_showahead = "ON") then
i_tmp_q <= mem_data(0);
end if;
end if; -- aclr event
if (clock'event and (clock = '1') and
((aclr = '0') or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))))
then
valid_rreq := rdreq = '1' and ((i_empty_flag = '0') or
(underflow_checking = "OFF"));
valid_wreq := wrreq = '1' and ((i_full_flag = '0') or
(overflow_checking = "OFF") or ((rdreq = '1') and
(allow_rwcycle_when_full = "ON")));
if (sclr = '1')
then
i_tmp_q <= mem_data(i_read_id);
i_read_id <= 0;
i_count_id <= 0;
i_write_id <= 0;
i_full_flag <= '0';
i_empty_flag <= '1';
write_id := 0;
full_flag := false;
if (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
end if;
if ((lpm_showahead = "ON") or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
then
i_tmp_q <= mem_data(0);
end if;
else
-- Both WRITE and READ operations
if (valid_wreq and valid_rreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
i_empty_flag <= '0';
if (allow_rwcycle_when_full = "OFF")
then
i_full_flag <= '0';
full_flag := false;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
i_tmp_q <= mem_data(i_read_id);
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
-- WRITE operation only
elsif (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
i_count_id <= i_count_id + 1;
i_empty_flag <= '0';
if (i_count_id >= max_widthu)
then
i_count_id <= 0;
end if;
if ((i_count_id = numwords_minus_one) and (i_empty_flag = '0'))
then
i_full_flag <= '1';
full_flag := true;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
-- READ operation only
elsif (valid_rreq)
then
i_tmp_q <= mem_data(i_read_id);
i_count_id <= i_count_id - 1;
i_full_flag <= '0';
full_flag := false;
if (i_count_id <= 0)
then
i_count_id <= max_widthu;
end if;
if (i_count_id = 1 and i_full_flag = '0')
then
i_empty_flag <= '1';
end if;
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
end if; -- if Both WRITE and READ operations
end if; -- if sclr = '1'
elsif (clock'event and (clock = '0'))
then
if (write_flag)
then
write_flag := false;
mem_data(write_id) := tmp_data;
end if;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
end if; -- clock event
if (aclr = '1')
then
i_full_flag <= '0';
i_empty_flag <= '1';
i_read_id <= 0;
i_write_id <= 0;
i_count_id <= 0;
write_id := 0;
end if;
end process; -- clock, aclr events
q <= i_tmp_q;
full <= i_full_flag;
empty <= i_empty_flag;
usedw <= conv_std_logic_vector(i_count_id, lpm_widthu);
end behavior; -- LPM_FIFO
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_dffpipe
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_DFFPIPE is
-- GENERIC DECLARATION
generic (
lpm_delay : natural;
lpm_width : natural
);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
d : in std_logic_vector (lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector (lpm_width-1 downto 0)
);
end LPM_FIFO_DC_DFFPIPE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_DFFPIPE is
-- TYPE DECLARATION
type DELAYPIPE is array (lpm_delay downto 0) of std_logic_vector (lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (clock, aclr, d)
------ VARIABLE DECLARATION
variable intpipe : DELAYPIPE := (OTHERS => ZEROS);
variable delay : integer := lpm_delay - 1;
variable need_init : boolean := true;
begin
if (lpm_delay = 0)
then
if ((aclr = '1') or need_init)
then
q <= ZEROS;
need_init := false;
else
q <= d;
end if;
else
if ((aclr = '1') or need_init)
then
for i in lpm_delay downto 0 loop
intpipe(i) := ZEROS;
end loop;
need_init := false;
q <= ZEROS;
end if;
if (rising_edge(clock) and (NOW > 0 ns))
then
if (delay > 0) then
for i in delay downto 1 loop
intpipe(i) := intpipe(i-1);
end loop;
end if;
intpipe(0) := d;
q <= intpipe(delay);
end if;
end if; -- (lpm_delay = 0)
end process; -- clock, aclr, d events
end behavior; -- lpm_fifo_dc_dffpipe
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_fefifo
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_FEFIFO is
-- GENERIC DECLARATION
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
empty : out std_logic;
full : out std_logic);
end LPM_FIFO_DC_FEFIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_FEFIFO is
-- SIGNAL DECLARATION
signal i_empty : std_logic := '1';
signal i_full : std_logic := '0';
begin
-- PROCESS DECLARATION
process (clock, aclr)
------ VARIABLE DECLARATION
variable sm_empty : std_logic_vector(1 downto 0) := "00";
variable lrreq : std_logic := '0';
variable almost_full : integer := 0;
variable usedw_is_1 : boolean := false;
variable need_init : boolean := true;
begin
if (need_init)
then
if ((lpm_mode /= "READ") and (lpm_mode /= "WRITE"))
then
ASSERT FALSE
REPORT "Error! LPM_MODE must be READ or WRITE."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if (lpm_numwords >= 3)
then
almost_full := lpm_numwords - 3;
else
almost_full := 0;
end if;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
sm_empty := "00";
lrreq := '0';
i_empty <= '1';
i_full <= '0';
end if; -- aclr event
if (rising_edge(clock) and (aclr = '0') and (NOW > 0 ns))
then
if (lpm_mode = "READ")
then
case sm_empty is
-- state_empty
when "00" =>
if (usedw_in /= 0)
then
sm_empty := "01";
end if;
-- state_non_empty
when "01" =>
if (lpm_widthad > 1)
then
usedw_is_1 := ((usedw_in = 1) and (lrreq = '0')) or ((usedw_in = 2) and (lrreq = '1'));
else
usedw_is_1 := (usedw_in = 1) and (lrreq = '0');
end if;
if ((rreq = '1') and usedw_is_1)
then
sm_empty := "10";
end if;
-- state_emptywait
when "10" =>
if (usedw_in > 1)
then
sm_empty := "01";
else
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in read mode."
SEVERITY ERROR;
end case;
elsif (lpm_mode = "WRITE")
then
case sm_empty is
-- state_empty
when "00" =>
if (wreq = '1')
then
sm_empty := "01";
end if;
-- state_one
when "01" =>
if (wreq = '0')
then
sm_empty := "11";
end if;
-- state_non_empty
when "11" =>
if (wreq = '1')
then
sm_empty := "01";
elsif (usedw_in = 0)
then
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in write mode."
SEVERITY ERROR;
end case;
end if;
i_empty <= not sm_empty(0);
if ((aclr = '0') and (usedw_in >= almost_full) and (NOW > 0 ns))
then
i_full <= '1';
else
i_full <= '0';
end if;
if (underflow_checking = "OFF")
then
lrreq := rreq;
else
lrreq := rreq and not i_empty;
end if;
end if; -- clock event
end process; -- clock, aclr events
empty <= i_empty;
full <= i_full;
end behavior; -- lpm_fifo_dc_fefifo
-- END OF ARCHITECTURE
--
-- Entity Name : lpm_fifo_dc_async
--
-- Description : Asynchoronous Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_FIFO_DC_FEFIFO;
use work.LPM_FIFO_DC_DFFPIPE;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_ASYNC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
rdreq : in std_logic;
wrreq : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
rdempty : out std_logic;
wrempty : out std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC_ASYNC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_ASYNC is
-- TYPE DECLARATION
type LPM_MEMORY is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant ZEROU : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
constant GRAY_DELAYPIPE : integer := 1;
constant WRUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
constant RDUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
-- SIGNAL DECLARATION
signal i_data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal i_rdptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr_tmp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdptrrg : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrdelaycycle : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rden : std_logic := '0';
signal i_wren : std_logic := '0';
signal i_rdenclock : std_logic := '0';
signal i_wren_tmp : std_logic := '0';
signal i_rdempty : std_logic := '1';
signal i_wrempty : std_logic := '1';
signal i_rdfull : std_logic := '0';
signal i_wrfull : std_logic := '0';
signal i_rdusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_nbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_nbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_dbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_dbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_tmp : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_zero : std_logic := '0';
-- COMPONENT DECLARATION
component LPM_FIFO_DC_FEFIFO
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
port (
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
empty : out std_logic;
full : out std_logic);
end component;
component LPM_FIFO_DC_DFFPIPE
generic (
lpm_delay : natural;
lpm_width : natural);
port (
d : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
-- Delays & DFF Pipes
DP_RDPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 0,
lpm_width => lpm_widthu)
port map (
d => i_rdptr,
clock => i_rdenclock,
aclr => aclr,
q => i_rdptrrg);
DP_WRPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 1,
lpm_width => lpm_widthu)
port map (
d => i_wrptr,
clock => wrclk,
aclr => aclr,
q => i_wrdelaycycle);
DP_WS_NBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rdptrrg,
clock => wrclk,
aclr => aclr,
q => i_ws_nbrp);
DP_RS_NBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wrdelaycycle,
clock => rdclk,
aclr => aclr,
q => i_rs_nbwp);
DP_WS_DBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_ws_nbrp,
clock => wrclk,
aclr => aclr,
q => i_ws_dbrp);
DP_RS_DBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rs_nbwp,
clock => rdclk,
aclr => aclr,
q => i_rs_dbwp);
DP_WR_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_WRUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wrusedw);
DP_RD_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_RDUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rdusedw);
DP_WR_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wr_dbuw);
DP_RD_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rd_dbuw);
-- Empty/Full
WR_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "WRITE")
port map (
usedw_in => i_wr_dbuw,
wreq => wrreq,
rreq => i_zero,
clock => wrclk,
aclr => aclr,
empty => i_wrempty,
full => i_wrfull);
RD_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "READ")
port map (
usedw_in => i_rd_dbuw,
wreq => i_zero,
rreq => rdreq,
clock => rdclk,
aclr => aclr,
empty => i_rdempty,
full => i_rdfull);
-- PROCESS DECLARATION
-- FIFOram
process (wrclk, rdclk, aclr)
------ VARIABLE DECLARATION
variable max_widthu : integer := 0;
variable max_widthu_minus_one : integer := 0;
variable mem_data : LPM_MEMORY := (OTHERS => ZEROS);
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF"))
then
ASSERT FALSE
REPORT "Error! LPM_SHOWAHEAD must be ON or OFF."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((use_eab /= "ON") and (use_eab /= "OFF"))
then
ASSERT FALSE
REPORT "Error! USE_EAB must be ON or OFF."
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Error! Illegal INTENDED_DEVICE_FAMILY."
SEVERITY ERROR;
end if;
max_widthu := 2 ** lpm_widthu;
max_widthu_minus_one := (2 ** lpm_widthu) - 1;
for i in lpm_numwords - 1 downto 0 loop
mem_data(i) := ZEROS;
end loop;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
i_rdptr <= ZEROU;
i_wrptr <= ZEROU;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF"))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
end if;
end if; -- aclr event
if (rising_edge(wrclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
i_data_tmp <= ZEROS;
i_wrptr_tmp <= ZEROU;
i_wren_tmp <= '0';
elsif (NOW > 0 ns)
then
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= i_wren;
if (i_wren = '1')
then
if ((aclr = '0') and (i_wrptr < max_widthu_minus_one))
then
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= ZEROU;
end if;
if (use_eab = "OFF")
then
mem_data(CONV_INTEGER(i_wrptr) mod max_widthu) := data;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if;
end if;
end if; -- wrclk = '1' and wrclk'event
if ((falling_edge(wrclk) and (use_eab = "ON")) and (NOW > 0 ns))
then
if (i_wren_tmp = '1')
then
mem_data(CONV_INTEGER(i_wrptr_tmp) mod max_widthu) := i_data_tmp;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if; -- wrclk = '0' and wrclk event and (use_eab = "ON")) and (NOW > 0 ns)
if (rising_edge(rdclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
elsif ((i_rden = '1') and (NOW > 0 ns))
then
if ((aclr = '0') and (i_rdptr < max_widthu_minus_one))
then
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= ZEROU;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr + 1) mod max_widthu);
else
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if; -- rdclk = '1' and rdclk event
end process; -- aclr, wrclk, rdclk events
i_rden <= rdreq when underflow_checking = "OFF" else
rdreq and not i_rdempty;
i_wren <= wrreq when overflow_checking = "OFF" else
wrreq and not i_wrfull;
-- Delays & DFF Pipes
process (rdclk)
begin
if (falling_edge(rdclk))
then
i_rdenclock <= '0';
elsif (rising_edge(rdclk))
then
if (i_rden = '1')
then
i_rdenclock <= '1';
end if;
end if;
end process; -- rdclk event
process (i_wrptr, i_ws_dbrp)
begin
if (NOW > 0 ns)
then
i_wr_udwn <= i_wrptr - i_ws_dbrp;
end if;
end process; -- i_wrptr, i_ws_dbrp events
process (i_rdptr, i_rs_dbwp)
begin
if (NOW > 0 ns)
then
i_rd_udwn <= i_rs_dbwp - i_rdptr;
end if;
end process; -- i_rdptr, i_rs_dbwp events
-- Outputs
rdempty <= i_rdempty;
rdfull <= i_rdfull;
wrempty <= i_wrempty;
wrfull <= i_wrfull;
rdusedw <= i_rdusedw;
wrusedw <= i_wrusedw;
q <= i_q_tmp;
end behavior; -- lpm_fifo_dc_async
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc
--
-- Description : Dual clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
use work.LPM_FIFO_DC_ASYNC;
-- ENTITY DECLARATION
entity LPM_FIFO_DC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_hint : string := "";
lpm_type : string := "LPM_FIFO_DC");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclock : in std_logic;
wrclock : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
-- OUTPUT PORT DECLARATION
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC is
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return underflow_checking;
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return overflow_checking;
end if;
end get_overflow_checking;
function get_use_eab return string is
constant param_value : string := get_parameter_value(LPM_HINT, "USE_EAB");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_use_eab;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant C_UNDERFLOW_CHECKING : string := get_underflow_checking;
constant C_OVERFLOW_CHECKING : string := get_overflow_checking;
constant C_USE_EAB : string := get_use_eab;
constant C_INTENDED_DEVICE_FAMILY : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_rdfull_a : std_logic := '0';
signal i_wrfull_a : std_logic := '0';
signal i_rdempty_a : std_logic := '1';
signal i_wrempty_a : std_logic := '1';
signal i_rdfull_s : std_logic := '0';
signal i_wrfull_s : std_logic := '0';
signal i_rdempty_s : std_logic := '1';
signal i_wrempty_s : std_logic := '1';
signal i_rdusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_a : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_q_s : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- COMPONENT DECLARATION
component LPM_FIFO_DC_ASYNC
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
ASYNC: LPM_FIFO_DC_ASYNC
generic map (
lpm_width => lpm_width,
lpm_widthu => lpm_widthu,
lpm_numwords => lpm_numwords,
lpm_showahead => lpm_showahead,
underflow_checking => C_UNDERFLOW_CHECKING,
overflow_checking => C_OVERFLOW_CHECKING,
use_eab => C_USE_EAB,
intended_device_family => C_INTENDED_DEVICE_FAMILY)
port map (
data => data,
rdclk => rdclock,
wrclk => wrclock,
aclr => aclr,
rdreq => rdreq,
wrreq => wrreq,
rdfull => i_rdfull_a,
wrfull => i_wrfull_a,
rdempty => i_rdempty_a,
wrempty => i_wrempty_a,
rdusedw => i_rdusedw_a,
wrusedw => i_wrusedw_a,
q => i_q_a);
rdfull <= i_rdfull_a;
wrfull <= i_wrfull_a;
rdempty <= i_rdempty_a;
wrempty <= i_wrempty_a;
rdusedw <= i_rdusedw_a;
wrusedw <= i_wrusedw_a;
q <= i_q_a;
end behavior; -- lpm_fifo_dc
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_INpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INpad";
lpm_hint : string := "UNUSED"
);
port (
pad : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= pad;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_outpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_OUTpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "L_OUTpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
pad : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_OUTpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OUTpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
pad <= data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bipad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_BIpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_BIpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
enable : in std_logic;
result : out std_logic_vector(lpm_width-1 downto 0);
pad : inout std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BIpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BIpad is
signal tmp_pad : std_logic_vector(lpm_width-1 downto 0);
begin
tmp_pad <= pad;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(data, tmp_pad, enable)
begin
if enable = '1' then
pad <= data;
result <= (OTHERS => 'Z');
else
result <= tmp_pad;
pad <= (OTHERS => 'Z');
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
| gpl-3.0 | 50864430e092f7ce79a7b9ec86258d26 | 0.415121 | 4.5539 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/dac_mod.vhd | 1 | 6,734 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DAC_MOD is
generic (
-- IO-REQ: 3 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000011";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
SCLK_EDGE: in std_logic;
SCLK_STATE: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of DAC_MOD is
constant CMD_WriteA: std_logic_vector(7 downto 0) := "00000000";
constant CMD_WriteB_LoadAB: std_logic_vector(7 downto 0) := "00110100";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal shift_cnt: std_logic_vector(4 downto 0);
signal bitcnt_sync: std_logic;
signal bitcnt_top: std_logic;
signal dac1_data: std_logic_vector(15 downto 0);
signal dac2_data: std_logic_vector(15 downto 0);
signal dac2_reg: std_logic_vector(15 downto 0);
signal dac3_data: std_logic_vector(15 downto 0);
signal dac4_data: std_logic_vector(15 downto 0);
signal dac4_reg: std_logic_vector(15 downto 0);
signal dac5_data: std_logic_vector(15 downto 0);
signal dac6_data: std_logic_vector(15 downto 0);
signal dac6_reg: std_logic_vector(15 downto 0);
signal ssync: std_logic;
signal sclk: std_logic;
signal select_ab: std_logic;
signal dac12_shift: std_logic_vector(23 downto 0);
signal dac34_shift: std_logic_vector(23 downto 0);
signal dac56_shift: std_logic_vector(23 downto 0);
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux(15 downto 0) <= dac1_data;
wb_data_mux(31 downto 16) <= dac2_data;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux(15 downto 0) <= dac3_data;
wb_data_mux(31 downto 16) <= dac4_data;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux(15 downto 0) <= dac5_data;
wb_data_mux(31 downto 16) <= dac6_data;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
dac1_data <= (others => '0');
dac2_data <= (others => '0');
dac3_data <= (others => '0');
dac4_data <= (others => '0');
dac5_data <= (others => '0');
dac6_data <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
dac1_data <= WB_DATA_IN(15 downto 0);
dac2_data <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 1 =>
dac3_data <= WB_DATA_IN(15 downto 0);
dac4_data <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 2 =>
dac5_data <= WB_DATA_IN(15 downto 0);
dac6_data <= WB_DATA_IN(31 downto 16);
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- serial clock
----------------------------------------------------------
p_sclk: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
ssync <= '0';
sclk <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' then
ssync <= '0';
sclk <= '0';
if SCLK_STATE = '0' then
if bitcnt_sync = '1' then
ssync <= '1';
else
sclk <= '1';
end if;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- shift counter
----------------------------------------------------------
p_bitcnt_cnt: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
shift_cnt <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '1' then
if bitcnt_top = '1' then
shift_cnt <= (others => '0');
else
shift_cnt <= shift_cnt + 1;
end if;
end if;
end if;
end process;
bitcnt_sync <= '1' when shift_cnt = 23 else '0';
bitcnt_top <= '1' when shift_cnt = 24 else '0';
----------------------------------------------------------
--- output shift
----------------------------------------------------------
p_so_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
dac12_shift <= (others => '0');
dac34_shift <= (others => '0');
dac56_shift <= (others => '0');
dac2_reg <= (others => '0');
dac4_reg <= (others => '0');
dac6_reg <= (others => '0');
select_ab <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
if select_ab = '0' then
dac12_shift <= CMD_WriteA & dac1_data;
dac34_shift <= CMD_WriteA & dac3_data;
dac56_shift <= CMD_WriteA & dac5_data;
dac2_reg <= dac2_data;
dac4_reg <= dac4_data;
dac6_reg <= dac6_data;
else
dac12_shift <= CMD_WriteB_LoadAB & dac2_reg;
dac34_shift <= CMD_WriteB_LoadAB & dac4_reg;
dac56_shift <= CMD_WriteB_LoadAB & dac6_reg;
end if;
select_ab <= not select_ab;
else
dac12_shift <= dac12_shift(22 downto 0) & "1";
dac34_shift <= dac34_shift(22 downto 0) & "1";
dac56_shift <= dac56_shift(22 downto 0) & "1";
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
SV(3) <= '0';
SV(4) <= '0';
SV(5) <= not ssync;
SV(6) <= not sclk;
SV(7) <= not dac56_shift(23);
SV(8) <= not dac34_shift(23);
SV(9) <= not dac12_shift(23);
SV(10) <= OUT_EN;
end;
| gpl-3.0 | d46344e011ce73a53665688a1d9ceb36 | 0.504455 | 3.302599 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaii_components.vhd | 1 | 78,191 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
package arriaii_components is
--
-- arriaii_lcell_comb
--
COMPONENT arriaii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriaii_routing_wire
--
COMPONENT arriaii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_transmitter
--
COMPONENT arriaii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriaii_rublock
--
COMPONENT arriaii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriaii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_oscillator
--
COMPONENT arriaii_oscillator
generic
(
lpm_type: string := "arriaii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- arriaii_ram_block
--
COMPONENT arriaii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_ff
--
COMPONENT arriaii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- arriaii_clkselect
--
COMPONENT arriaii_clkselect
generic (
lpm_type : STRING := "arriaii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_clkena
--
COMPONENT arriaii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_mlab_cell
--
COMPONENT arriaii_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_io_ibuf
--
COMPONENT arriaii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- arriaii_io_obuf
--
COMPONENT arriaii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_ddio_in
--
COMPONENT arriaii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_oe
--
COMPONENT arriaii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_out
--
COMPONENT arriaii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_dll
--
COMPONENT arriaii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dll_offset_ctrl
--
COMPONENT arriaii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_dqs_enable
--
COMPONENT arriaii_dqs_enable
GENERIC (
lpm_type : string := "arriaii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_mac_mult
--
COMPONENT arriaii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_mac_out
--
COMPONENT arriaii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_io_pad
--
COMPONENT arriaii_io_pad
GENERIC (
lpm_type : string := "arriaii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- arriaii_pll
--
COMPONENT arriaii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "PiranhaIII";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- arriaii_asmiblock
--
COMPONENT arriaii_asmiblock
generic (
lpm_type : string := "arriaii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_receiver
--
COMPONENT arriaii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_pseudo_diff_out
--
COMPONENT arriaii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dqs_delay_chain
--
COMPONENT arriaii_dqs_delay_chain
GENERIC (
lpm_type : STRING := "arriaii_dqs_delay_chain";
delay_buffer_mode : STRING := "low";
dqs_ctrl_latches_enable : STRING := "false";
dqs_input_frequency : string := "unused" ;
dqs_offsetctrl_enable : STRING := "false";
dqs_phase_shift : INTEGER := 0;
phase_setting : INTEGER := 0;
sim_buffer_delay_increment : INTEGER := 10;
sim_high_buffer_intrinsic_delay : INTEGER := 175;
sim_low_buffer_intrinsic_delay : INTEGER := 350;
test_enable : STRING := "false";
test_select : INTEGER := 0 ;
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
dqsin : IN STD_LOGIC := '0';
dqsupdateen : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_dqs_enable_ctrl
--
COMPONENT arriaii_dqs_enable_ctrl
GENERIC (
lpm_type : STRING := "arriaii_dqs_enable_ctrl";
delay_dqs_enable_by_half_cycle : STRING := "false" ;
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN STD_LOGIC := '0';
dqsenablein : IN STD_LOGIC := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_jtag
--
COMPONENT arriaii_jtag
generic (
lpm_type : string := "arriaii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriaii_crcblock
--
COMPONENT arriaii_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_controller
--
COMPONENT arriaii_controller
generic (
lpm_type : string := "arriaii_controller"
);
port (
nceout : out std_logic
);
END COMPONENT;
--
-- arriaii_termination_logic
--
COMPONENT arriaii_termination_logic
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationselect : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination_logic"
);
PORT (
terminationclock : IN STD_LOGIC := '0';
terminationdata : IN STD_LOGIC := '0';
terminationselect : IN STD_LOGIC := '0';
terminationcontrol : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_termination
--
COMPONENT arriaii_termination
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_scanshiftmux : VitalDelayType01 := DefpropDelay01;
tipd_scaninmux : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclock : VitalDelayType01 := DefpropDelay01;
tipd_scanclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclear : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_rup : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination";
runtime_control : STRING := "false"
);
PORT (
rdn : IN STD_LOGIC := '0';
rup : IN STD_LOGIC := '0';
scanclock : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC := '0';
scaninmux : IN STD_LOGIC := '0';
scanshiftmux : IN STD_LOGIC := '0';
terminationuserclear : IN STD_LOGIC := '0';
terminationuserclock : IN STD_LOGIC := '0';
comparatorprobe : OUT STD_LOGIC;
scanout : OUT STD_LOGIC;
terminationclockout : OUT STD_LOGIC;
terminationcontrolprobe : OUT STD_LOGIC;
terminationdataout : OUT STD_LOGIC;
terminationdone : OUT STD_LOGIC;
terminationselectout : OUT STD_LOGIC
);
END COMPONENT;
end arriaii_components;
| gpl-3.0 | 62279ae7ffc29651de9f3d125243b401 | 0.460168 | 4.35653 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyiii_atoms.vhd | 1 | 953,345 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package hardcopyiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE hardcopyiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end hardcopyiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hardcopyiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end hardcopyiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package hardcopyiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end hardcopyiii_pllpack;
package body hardcopyiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end hardcopyiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiii_dffe : entity is TRUE;
end hardcopyiii_dffe;
-- architecture body --
architecture behave of hardcopyiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- hardcopyiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of hardcopyiii_mux21 : entity is TRUE;
end hardcopyiii_mux21;
architecture AltVITAL of hardcopyiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_mux41 : entity is TRUE;
end hardcopyiii_mux41;
architecture AltVITAL of hardcopyiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiii_atom_pack.all;
-- entity declaration --
entity hardcopyiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiii_and1 : entity is TRUE;
end hardcopyiii_and1;
-- architecture body --
architecture AltVITAL of hardcopyiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_lcell_comb
--
-- Description : HARDCOPYIII LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "hardcopyiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_lcell_comb : entity is TRUE;
end hardcopyiii_lcell_comb;
architecture vital_lcell_comb of hardcopyiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_routing_wire
--
-- Description : HARDCOPYIII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_routing_wire : entity is TRUE;
end hardcopyiii_routing_wire;
ARCHITECTURE behave of hardcopyiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_lvds_tx_reg : ENTITY is TRUE;
END hardcopyiii_lvds_tx_reg;
ARCHITECTURE vital_hardcopyiii_lvds_tx_reg of hardcopyiii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_hardcopyiii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the HARDCOPYIII
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyiii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END hardcopyiii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of hardcopyiii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyiii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END hardcopyiii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of hardcopyiii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiii_lvds_transmitter
--
-- Description : Timing simulation model for the HARDCOPYIII LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) HARDCOPYIII_lvds_tx_parallel_register and
-- 3) HARDCOPYIII_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE std.textio.all;
USE work.hardcopyiii_lvds_tx_parallel_register;
USE work.hardcopyiii_lvds_tx_out_block;
USE work.hardcopyiii_lvds_tx_reg;
ENTITY hardcopyiii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- HARDCOPYIII
tx_output_path_delay_engineering_bits : Integer := -1; -- HARDCOPYIII
enable_dpaclk_to_lvdsout : string := "off"; -- HARDCOPYIII
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- HARDCOPYIII
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- HARDCOPYIII
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- HARDCOPYIII
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end hardcopyiii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of hardcopyiii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;-- HARDCOPYIII
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT hardcopyiii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);-- HARDCOPYIII
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: hardcopyiii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: hardcopyiii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: hardcopyiii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd, -- HARDCOPYIII
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then-- HARDCOPYIII
dataout_tmp := dpaclkin_ipd;-- HARDCOPYIII
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then -- HARDCOPYIII
VitalPathDelay01 ( -- HARDCOPYIII
OutSignal => dataout, -- HARDCOPYIII
OutSignalName => "DATAOUT", -- HARDCOPYIII
OutTemp => dataout_tmp, -- HARDCOPYIII
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)), -- HARDCOPYIII
GlitchData => dataout_VitalGlitchData, -- HARDCOPYIII
Mode => DefGlitchMode, -- HARDCOPYIII
XOn => XOn, -- HARDCOPYIII
MsgOn => MsgOn ); -- HARDCOPYIII
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
----------------------------------------------------------------------------
-- Module Name : hardcopyiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END hardcopyiii_ram_register;
ARCHITECTURE reg_arch OF hardcopyiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : hardcopyiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF hardcopyiii_ram_pulse_generator:ENTITY IS TRUE;
END hardcopyiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF hardcopyiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_ram_register;
USE work.hardcopyiii_ram_pulse_generator;
ENTITY hardcopyiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END hardcopyiii_ram_block;
ARCHITECTURE block_arch OF hardcopyiii_ram_block IS
COMPONENT hardcopyiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : hardcopyiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : hardcopyiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : hardcopyiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : hardcopyiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : hardcopyiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : hardcopyiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : hardcopyiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_ff
--
-- Description : HARDCOPYIII FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_and1;
entity hardcopyiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "hardcopyiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_ff : entity is TRUE;
end hardcopyiii_ff;
architecture vital_lcell_ff of hardcopyiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component hardcopyiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: hardcopyiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: hardcopyiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: hardcopyiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for HARDCOPYIII CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- HARDCOPYIII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_clkselect is
generic (
lpm_type : STRING := "hardcopyiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_clkselect : entity is TRUE;
end hardcopyiii_clkselect;
architecture vital_clkselect of hardcopyiii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- hardcopyiii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiii_atom_pack.all;
-- entity declaration --
entity hardcopyiii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiii_and2 : entity is TRUE;
end hardcopyiii_and2;
-- architecture body --
architecture AltVITAL of hardcopyiii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_ena_reg : entity is TRUE;
end hardcopyiii_ena_reg;
ARCHITECTURE behave of hardcopyiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for HARDCOPYIII CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- HARDCOPYIII_CLKENA Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ena_reg;
use work.hardcopyiii_and2;
entity hardcopyiii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_clkena : entity is TRUE;
end hardcopyiii_clkena;
architecture vital_clkena of hardcopyiii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component hardcopyiii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component hardcopyiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : hardcopyiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : hardcopyiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : hardcopyiii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : hardcopyiii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Entity Name : hardcopyiii_hram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiii_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_hram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF hardcopyiii_hram_pulse_generator:ENTITY IS TRUE;
END hardcopyiii_hram_pulse_generator;
ARCHITECTURE pgen_arch OF hardcopyiii_hram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
----------------------------------------------------------------------------
-- Entity Name : hardcopyiii_hram
-- Description : HRAM VHDL Simulation Model
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_hram_pulse_generator;
USE work.hardcopyiii_ram_register;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_hram IS
GENERIC (
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tipd_ena0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_devclrn : VitalDelayType01 := DefpropDelay01;
tipd_clr0 : VitalDelayType01 := DefpropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_portabyteenamasks :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portadatain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clr1 : VitalDelayType01 := DefpropDelay01;
tipd_devpor : VitalDelayType01 := DefpropDelay01;
tipd_ena1 : VitalDelayType01 := DefpropDelay01;
tipd_ena2 : VitalDelayType01 := DefpropDelay01;
tipd_portaaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_ena3 : VitalDelayType01 := DefpropDelay01;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01;
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "hram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_address_clock : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "hardcopyiii_hram";
lpm_hint : STRING := "true";
mem_init0 : BIT_VECTOR := X"0";
mixed_port_feed_through_mode : STRING := "dont_care"
);
PORT (
-- -------- PORT DECLARATIONS ---------
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END hardcopyiii_hram;
ARCHITECTURE trans OF hardcopyiii_hram IS
CONSTANT port_byte_size : INTEGER := (data_width / byte_enable_mask_width) + (data_width rem byte_enable_mask_width);
CONSTANT num_rows : INTEGER := 2**address_width;
CONSTANT num_cols : INTEGER := 1;
signal ena0_ipd :STD_LOGIC;
signal clk1_ipd :STD_LOGIC;
signal devclrn_ipd :STD_LOGIC;
signal clr0_ipd :STD_LOGIC;
signal clk0_ipd :STD_LOGIC;
signal portabyteenamasks_ipd :STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
signal portadatain_ipd :STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
signal clr1_ipd :STD_LOGIC;
signal devpor_ipd :STD_LOGIC;
signal ena1_ipd :STD_LOGIC;
signal ena2_ipd :STD_LOGIC;
signal portaaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
signal portbaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
signal ena3_ipd :STD_LOGIC;
COMPONENT hardcopyiii_hram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
TYPE type_xhdl0 IS ARRAY (num_rows - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0' ;
SIGNAL ena1_reg : STD_LOGIC := '0' ;
SIGNAL ena2_reg : STD_LOGIC := '0' ;
SIGNAL ena3_reg : STD_LOGIC := '0' ;
SIGNAL viol_notifier : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
-- -------- INTERNAL signals ---------
-- clock / clock enable
SIGNAL clk_a_in : STD_LOGIC;
SIGNAL clk_b_in : STD_LOGIC;
SIGNAL clk_b_out : STD_LOGIC;
-- asynch clear
SIGNAL addr_b_clr_in : STD_LOGIC;
SIGNAL dataout_b_clr_in : STD_LOGIC;
SIGNAL dataout_b_clr : STD_LOGIC;
SIGNAL addr_b_clr : STD_LOGIC;
SIGNAL addr_a_clr : STD_LOGIC;
SIGNAL datain_a_clr : STD_LOGIC;
SIGNAL byteena_a_clr : STD_LOGIC;
-- port A registers
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
-- port B registers
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL portbdataout_tmp : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- placeholders for read/written data
SIGNAL read_data_latch : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL mem_data : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- pulses for A/B ports (no read pulse)
SIGNAL write_pulse : STD_LOGIC;
SIGNAL write_cycle : STD_LOGIC;
-- memory core
SIGNAL mem : type_xhdl0;
-- byte enable
SIGNAL mask_vector : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL mask_vector_int : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- memory initialization
SIGNAL init_mem : BOOLEAN := FALSE;
-- port active for read/write
SIGNAL active_a : STD_LOGIC;
SIGNAL active_a_in : STD_LOGIC;
SIGNAL active_write_a : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl1 : STD_LOGIC;
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk1_ipd,clk1, tipd_clk1);
VitalWireDelay (ena0_ipd,ena0, tipd_ena0);
bits_portadatain : FOR i in portadatain'RANGE GENERATE
VitalWireDelay (portadatain_ipd(i),portadatain(i), tipd_portadatain(i));
END GENERATE;
bits_portabyteenamasks : FOR i in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(i),portabyteenamasks(i), tipd_portabyteenamasks(i));
END GENERATE;
VitalWireDelay (clk0_ipd,clk0, tipd_clk0);
VitalWireDelay (clr0_ipd,clr0, tipd_clr0);
VitalWireDelay (devclrn_ipd,devclrn, tipd_devclrn);
VitalWireDelay (clr1_ipd,clr1, tipd_clr1);
VitalWireDelay (ena1_ipd,ena1, tipd_ena1);
VitalWireDelay (devpor_ipd,devpor, tipd_devpor);
bits_portaaddr : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i),portaaddr(i), tipd_portaaddr(i));
END GENERATE;
VitalWireDelay (ena2_ipd,ena2, tipd_ena2);
bits_portbaddr : FOR i in portbaddr'RANGE GENERATE
VitalWireDelay (portbaddr_ipd(i),portbaddr(i), tipd_portbaddr(i));
END GENERATE;
VitalWireDelay (ena3_ipd,ena3, tipd_ena3);
END BLOCK;
------------------------
-- Functionality Section --
------------------------
reset <= ena0_reg;
init_mem <= TRUE;
clk_a_in <= clk0_ipd;
clk_b_in <= clk0_ipd WHEN (port_b_address_clock = ("clock0")) ELSE
clk1_ipd WHEN (port_b_address_clock = ("clock1")) ELSE
'0';
clk_b_out <= clk1_ipd WHEN (port_b_data_out_clock = ("clock1")) ELSE
'0';
PROCESS (clk_a_in)
BEGIN
IF (clk_a_in'EVENT AND clk_a_in = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
PROCESS (clk_b_out)
BEGIN
IF (clk_b_out'EVENT AND clk_b_out = '1') THEN
ena1_reg <= ena1_ipd;
END IF;
END PROCESS;
PROCESS (clk_a_in)
BEGIN
IF (clk_a_in'EVENT AND clk_a_in = '1') THEN
ena2_reg <= ena2_ipd;
END IF;
END PROCESS;
PROCESS (clk_b_in)
BEGIN
IF (clk_b_in'EVENT AND clk_b_in = '1') THEN
ena3_reg <= ena3_ipd;
END IF;
END PROCESS;
addr_b_clr_in <= clr0_ipd WHEN (port_b_address_clear = ("clear0")) ELSE
'0';
dataout_b_clr_in <= clr1_ipd WHEN (port_b_data_out_clear = ("clear1")) ELSE
'0';
-- Port A registers
-- address register
addr_a_register : hardcopyiii_ram_register
GENERIC MAP (
width => address_width
)
PORT MAP (
d => portaaddr_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data register
datain_a_register : hardcopyiii_ram_register
GENERIC MAP (
width => data_width
)
PORT MAP (
d => portadatain_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable register
byteena_a_register : hardcopyiii_ram_register
GENERIC MAP (
width => byte_enable_mask_width
)
PORT MAP (
d => portabyteenamasks_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- Port B registers
-- address register
addr_b_register : hardcopyiii_ram_register
GENERIC MAP (
width => address_width
)
PORT MAP (
d => portbaddr_ipd,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena3,
stall => '0',
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data register
data_b_register : hardcopyiii_ram_register
GENERIC MAP (
width => data_width
)
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_in,
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena1,
stall => '0',
q => dataout_b_reg,
aclrout => dataout_b_clr
);
-- Write pulse generation
xhdl1 <= NOT(clk_a_in);
wpgen_a : hardcopyiii_hram_pulse_generator
PORT MAP (
clk => xhdl1,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Read pulse generation
-- -- none --
-- Create internal masks for byte enable processing
PROCESS (byteena_a_reg)
BEGIN
FOR i IN 0 TO data_width-1 LOOP
IF (byteena_a_reg(i / port_byte_size) = '1') THEN
mask_vector(i) <= '0';
ELSE
mask_vector(i) <= 'X';
END IF;
IF (byteena_a_reg(i / port_byte_size) = '0') THEN
mask_vector_int(i) <= '0';
ELSE
mask_vector_int(i) <= 'X';
END IF;
END LOOP;
END PROCESS;
PROCESS (init_mem, write_pulse)
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : type_xhdl0;
VARIABLE mem_data_p : STD_LOGIC_VECTOR(data_width-1 downto 0);
BEGIN
-- powerup output to 0
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "NONE" AND init_file /= "none") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(bin2int(addr_a_reg));
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector_int(i);
END LOOP;
mem(bin2int(addr_a_reg)) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(bin2int(addr_a_reg));
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(i) = '0') THEN
mem(bin2int(addr_a_reg))(i) <= datain_a_reg(i);
mem_data_p(i) := datain_a_reg(i);
ELSIF (mask_vector_int(i) = 'X') THEN
mem(bin2int(addr_a_reg))(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS;
-- Read stage : asynchronous continuous read
dataout_b <= mem(bin2int(portbaddr_ipd)) WHEN (port_b_address_clock = ("none")) ELSE
mem(bin2int(addr_b_reg));
portbdataout_tmp <= dataout_b_reg WHEN (port_b_data_out_clock = ("clock1")) ELSE
dataout_b;
--portbdataout <= portbdataout_tmp;
------------------------
-- Path Delay Section --
------------------------
PathDelay_portbdataout : BLOCK
BEGIN
portbdataout_GEN : FOR i IN portbdataout'RANGE GENERATE
PROCESS(portbdataout_tmp)
variable portbdataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => portbdataout(i),
OutSignalName => "portbdataout",
OutTemp => portbdataout_tmp(i),
Paths => (
0 => (portbaddr_ipd'last_event, tpd_portbaddr_portbdataout, TRUE)),
GlitchData => portbdataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS;
END GENERATE;
END BLOCK;
END trans;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_io_ibuf
--
-- Description : HARDCOPYIII IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "hardcopyiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END hardcopyiii_io_ibuf;
ARCHITECTURE arch OF hardcopyiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_io_obuf
--
-- Description : HARDCOPYIII IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "hardcopyiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END hardcopyiii_io_obuf;
ARCHITECTURE arch OF hardcopyiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_ddio_in
--
-- Description : HARDCOPYIII DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "hardcopyiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_ddio_in;
ARCHITECTURE arch OF hardcopyiii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_ddio_oe
--
-- Description : HARDCOPYIII DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "hardcopyiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_ddio_oe;
ARCHITECTURE arch OF hardcopyiii_ddio_oe IS
component hardcopyiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : hardcopyiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_ddio_out
--
-- Description : HARDCOPYIII DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "hardcopyiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_ddio_out;
ARCHITECTURE arch OF hardcopyiii_ddio_out IS
component hardcopyiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : hardcopyiii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: hardcopyiii_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY hardcopyiii_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END hardcopyiii_rt_sm;
ARCHITECTURE hardcopyiii_rt_sm_rtl OF hardcopyiii_rt_sm IS
CONSTANT HARDCOPYIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT HARDCOPYIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT HARDCOPYIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT HARDCOPYIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT HARDCOPYIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT HARDCOPYIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT HARDCOPYIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT HARDCOPYIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT HARDCOPYIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= HARDCOPYIII_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN HARDCOPYIII_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= HARDCOPYIII_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= HARDCOPYIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= HARDCOPYIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= HARDCOPYIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN HARDCOPYIII_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN HARDCOPYIII_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN HARDCOPYIII_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIII_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIII_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIII_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN HARDCOPYIII_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN HARDCOPYIII_RTOCT_DONE =>
next_state <= HARDCOPYIII_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= HARDCOPYIII_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END hardcopyiii_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiii_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY hardcopyiii_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END hardcopyiii_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF hardcopyiii_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_termination
--
-- Description : HARDCOPYIII Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.hardcopyiii_atom_pack.all;
USE WORK.hardcopyiii_termination_aux_clock_div;
USE WORK.hardcopyiii_rt_sm;
ENTITY hardcopyiii_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "hardcopyiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END hardcopyiii_termination;
ARCHITECTURE hardcopyiii_oct_arch OF hardcopyiii_termination IS
COMPONENT hardcopyiii_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiii_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : hardcopyiii_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : hardcopyiii_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END hardcopyiii_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_termination_logic
--
-- Description : HARDCOPYIII Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "hardcopyiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END hardcopyiii_termination_logic;
ARCHITECTURE hardcopyiii_oct_logic_arch OF hardcopyiii_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END hardcopyiii_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package hardcopyiii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end hardcopyiii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hardcopyiii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end hardcopyiii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY hardcopyiii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END hardcopyiii_dll_gray_encoder;
ARCHITECTURE hardcopyiii_dll_gray_encoder_arch OF hardcopyiii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END hardcopyiii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY hardcopyiii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END hardcopyiii_dll_gray_decoder;
ARCHITECTURE hardcopyiii_dll_gray_decoder_arch OF hardcopyiii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END hardcopyiii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_dll_gray_decoder;
ENTITY hardcopyiii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END hardcopyiii_ddr_delay_chain_s;
ARCHITECTURE hardcopyiii_ddr_delay_chain_s_arch OF hardcopyiii_ddr_delay_chain_s IS
COMPONENT hardcopyiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END hardcopyiii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiii_ddr_io_reg : entity is TRUE;
end hardcopyiii_ddr_io_reg;
architecture vital_hardcopyiii_ddr_io_reg of hardcopyiii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_hardcopyiii_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiii_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : HARDCOPYIII_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_pllpack.all;
use work.hardcopyiii_atom_ddr_pack.all;
use work.hardcopyiii_dll_gray_encoder;
ENTITY hardcopyiii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "hardcopyiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END hardcopyiii_dll;
ARCHITECTURE vital_hcxdll of hardcopyiii_dll is
COMPONENT hardcopyiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in hardcopyiii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in hardcopyiii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in hardcopyiii
signal pc_comp_range : integer := 0; -- new in hardcopyiii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : hardcopyiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in hardcopyiii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_hcxdll;
-------------------------------------------------------------------------------
--
-- Entity Name : HARDCOPYIII_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_pllpack.all;
use work.hardcopyiii_atom_ddr_pack.all;
use work.hardcopyiii_dll_gray_encoder;
use work.hardcopyiii_dll_gray_decoder;
ENTITY hardcopyiii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "hardcopyiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END hardcopyiii_dll_offset_ctrl;
ARCHITECTURE vital_hcxoffset of hardcopyiii_dll_offset_ctrl is
COMPONENT hardcopyiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : hardcopyiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_hcxoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_dll_gray_decoder;
ENTITY hardcopyiii_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_dqs_delay_chain_arch OF hardcopyiii_dqs_delay_chain IS
-- component section
COMPONENT hardcopyiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : hardcopyiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_dqs_enable IS
GENERIC (
lpm_type : string := "hardcopyiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_dqs_enable_arch OF hardcopyiii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiii_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ddr_io_reg;
use work.hardcopyiii_ddr_delay_chain_s;
ENTITY hardcopyiii_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_dqs_enable_ctrl_arch OF hardcopyiii_dqs_enable_ctrl IS
-- component section
COMPONENT hardcopyiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : hardcopyiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : hardcopyiii_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : hardcopyiii_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : hardcopyiii_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : hardcopyiii_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiii_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "hardcopyiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_delay_chain_arch OF hardcopyiii_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END hardcopyiii_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ddr_delay_chain_s;
ENTITY hardcopyiii_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_io_clock_divider_arch OF hardcopyiii_io_clock_divider IS
-- component section
COMPONENT hardcopyiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : hardcopyiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END hardcopyiii_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ddr_io_reg;
use work.hardcopyiii_ddr_delay_chain_s;
ENTITY hardcopyiii_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "hardcopyiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_output_phase_alignment_arch OF hardcopyiii_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT hardcopyiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : hardcopyiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : hardcopyiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiii_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ddr_io_reg;
use work.hardcopyiii_ddr_delay_chain_s;
ENTITY hardcopyiii_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_input_phase_alignment_arch OF hardcopyiii_input_phase_alignment IS
-- component section
COMPONENT hardcopyiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : hardcopyiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiii_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
use work.hardcopyiii_ddr_io_reg;
ENTITY hardcopyiii_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "hardcopyiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_half_rate_input_arch OF hardcopyiii_half_rate_input IS
-- component section
component hardcopyiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : hardcopyiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END hardcopyiii_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_io_config_arch OF hardcopyiii_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiii_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiii_dqs_config_arch OF hardcopyiii_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiii_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiii_mac_bit_register --
-- Description: HARDCOPYIII MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiii_mac_bit_register;
ARCHITECTURE arch OF hardcopyiii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiii_mac_register --
-- Description: HARDCOPYIII MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END hardcopyiii_mac_register;
ARCHITECTURE arch OF hardcopyiii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiii_mac_multiplier --
-- Description: HARDCOPYIII MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END hardcopyiii_mac_multiplier;
ARCHITECTURE arch OF hardcopyiii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: hardcopyiii_mac_mult_atom --
-- Description: Simulation model for hardcopyiii mac mult atom. --
-- This model instantiates the following components. --
-- 1.hardcopyiii_mac_bit_register. --
-- 2.hardcopyiii_mac_register. --
-- 3.hardcopyiii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_mac_mult;
ARCHITECTURE arch OF hardcopyiii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT hardcopyiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : hardcopyiii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_fsa_isse --
-- Description: HARDCOPYIII first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END hardcopyiii_fsa_isse;
ARCHITECTURE arch OF hardcopyiii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_first_stage_add_sub --
-- Description: HARDCOPYIII First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiii_first_stage_add_sub;
ARCHITECTURE arch OF hardcopyiii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_second_stage_add_accum --
-- Description: HARDCOPYIII Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END hardcopyiii_second_stage_add_accum;
ARCHITECTURE arch OF hardcopyiii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_round_block --
-- Description: HARDCOPYIII round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiii_round_block;
ARCHITECTURE arch OF hardcopyiii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_saturate_block --
-- Description: HARDCOPYIII saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END hardcopyiii_saturate_block;
ARCHITECTURE arch OF hardcopyiii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_round_saturate_block --
-- Description: HARDCOPYIII round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.hardcopyiii_round_block. --
-- 2.hardcopyiii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END hardcopyiii_round_saturate_block;
ARCHITECTURE arch OF hardcopyiii_round_saturate_block IS
COMPONENT hardcopyiii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : hardcopyiii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : hardcopyiii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_rotate_shift_block --
-- Description: HARDCOPYIII roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiii_rotate_shift_block;
ARCHITECTURE arch OF hardcopyiii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiii_carry_chain_adder --
-- Description: HARDCOPYIII carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END hardcopyiii_carry_chain_adder;
ARCHITECTURE arch OF hardcopyiii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: hardcopyiii_mac_out_atom --
-- Description: Simulation model for hardcopyiii mac out atom --
-- This model instantiates the following components --
-- 1.hardcopyiii_mac_bit_register --
-- 2.hardcopyiii_mac_register --
-- 3.hardcopyiii_fsa_isse --
-- 4.hardcopyiii_first_stage_add_sub --
-- 5.hardcopyiii_second_stage_add_accum --
-- 6.hardcopyiii_round_saturate_block --
-- 7.hardcopyiii_rotate_shift_block --
-- 8.hardcopyiii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END hardcopyiii_mac_out;
ARCHITECTURE arch OF hardcopyiii_mac_out IS
COMPONENT hardcopyiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : hardcopyiii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : hardcopyiii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : hardcopyiii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : hardcopyiii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : hardcopyiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : hardcopyiii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : hardcopyiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : hardcopyiii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : hardcopyiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : hardcopyiii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : hardcopyiii_io_pad
-- Description : Simulation model for hardcopyiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_io_pad IS
GENERIC (
lpm_type : string := "hardcopyiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END hardcopyiii_io_pad;
ARCHITECTURE arch OF hardcopyiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the HARDCOPYIII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END hardcopyiii_mn_cntr;
ARCHITECTURE behave of hardcopyiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the HARDCOPYIII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END hardcopyiii_scale_cntr;
ARCHITECTURE behave of hardcopyiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY hardcopyiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end hardcopyiii_pll_reg;
ARCHITECTURE behave of hardcopyiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiii_pll
--
-- Description : Timing simulation model for the HARDCOPYIII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_pllpack.all;
USE work.hardcopyiii_mn_cntr;
USE work.hardcopyiii_scale_cntr;
USE work.hardcopyiii_dffe;
USE work.hardcopyiii_pll_reg;
-- New Features : The list below outlines key new features in HARDCOPYIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY hardcopyiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "HARDCOPYIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END hardcopyiii_pll;
ARCHITECTURE vital_pll of hardcopyiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT hardcopyiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT hardcopyiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : hardcopyiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : hardcopyiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : hardcopyiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : hardcopyiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : hardcopyiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : hardcopyiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : hardcopyiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : hardcopyiii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : hardcopyiii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : hardcopyiii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : hardcopyiii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : hardcopyiii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/hardcopyiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/hardcopyiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_asmiblock
--
-- Description : HARDCOPYIII ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_asmiblock is
generic (
lpm_type : string := "hardcopyiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end hardcopyiii_asmiblock;
architecture architecture_asmiblock of hardcopyiii_asmiblock is
begin
end architecture_asmiblock; -- end of hardcopyiii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END hardcopyiii_lvds_reg;
ARCHITECTURE vital_hardcopyiii_lvds_reg of hardcopyiii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF hardcopyiii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_lvds_rx_fifo_sync_ram;
ENTITY hardcopyiii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of hardcopyiii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT hardcopyiii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : hardcopyiii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_lvds_reg;
ENTITY hardcopyiii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END hardcopyiii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF hardcopyiii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT hardcopyiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : hardcopyiii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : hardcopyiii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_rx_deser
--
-- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF hardcopyiii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF hardcopyiii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hardcopyiii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END hardcopyiii_pclk_divider;
ARCHITECTURE arch OF hardcopyiii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY hardcopyiii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END hardcopyiii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF hardcopyiii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY hardcopyiii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END hardcopyiii_dpa_retime_block;
ARCHITECTURE trans OF hardcopyiii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiii_dpa_retime_block;
ENTITY hardcopyiii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END hardcopyiii_dpa_block;
ARCHITECTURE trans OF hardcopyiii_dpa_block IS
COMPONENT hardcopyiii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : hardcopyiii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the hardcopyiii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) hardcopyiii_lvds_rx_fifo
-- 2) hardcopyiii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) hardcopyiii_lvds_rx_parallel_reg
-- 5) hardcopyiii_pclk_divider
-- 6) hardcopyiii_select_ini_phase_dpaclk
-- 7) hardcopyiii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiii_atom_pack.all;
USE work.hardcopyiii_lvds_rx_bitslip;
USE work.hardcopyiii_lvds_rx_fifo;
USE work.hardcopyiii_lvds_rx_deser;
USE work.hardcopyiii_lvds_rx_parallel_reg;
USE work.hardcopyiii_lvds_reg;
USE work.hardcopyiii_pclk_divider;
USE work.hardcopyiii_select_ini_phase_dpaclk;
USE work.hardcopyiii_dpa_block;
ENTITY hardcopyiii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF hardcopyiii_lvds_receiver IS
COMPONENT hardcopyiii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT hardcopyiii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
xhdl_12 <= devclrn OR devpor;
-- input register in non-DPA mode for sampling incoming data
in_reg : hardcopyiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : hardcopyiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: hardcopyiii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : hardcopyiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : hardcopyiii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: hardcopyiii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: hardcopyiii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : hardcopyiii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : hardcopyiii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : hardcopyiii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : hardcopyiii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : hardcopyiii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: hardcopyiii_pseudo_diff_out --
--Description: Simulation model for HARDCOPYIII Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "hardcopyiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END hardcopyiii_pseudo_diff_out;
ARCHITECTURE arch OF hardcopyiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiii_bias_logic
--
-- Description : HARDCOPYIII Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiii_bias_logic : ENTITY IS TRUE;
end hardcopyiii_bias_logic;
ARCHITECTURE vital_bias_logic of hardcopyiii_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiii_bias_generator
--
-- Description : HARDCOPYIII Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiii_bias_generator : ENTITY IS TRUE;
end hardcopyiii_bias_generator;
ARCHITECTURE vital_bias_generator of hardcopyiii_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 100;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiii_bias_block
--
-- Description : HARDCOPYIII Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
ENTITY hardcopyiii_bias_block IS
GENERIC (
lpm_type : string := "hardcopyiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiii_bias_block : ENTITY IS TRUE;
end hardcopyiii_bias_block;
ARCHITECTURE vital_bias_block of hardcopyiii_bias_block IS
COMPONENT hardcopyiii_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT hardcopyiii_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : hardcopyiii_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : hardcopyiii_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_tsdblock
--
-- Description : HARDCOPYIII TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "hardcopyiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end hardcopyiii_tsdblock;
architecture architecture_tsdblock of hardcopyiii_tsdblock is
begin
end architecture_tsdblock; -- end of hardcopyiii_tsdblock
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_jtag
--
-- Description : Hcx JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_jtag is
generic (
lpm_type : string := "hardcopyiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end hardcopyiii_jtag;
architecture architecture_jtag of hardcopyiii_jtag is
begin
end architecture_jtag;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiii_lcell_hsadder
--
-- Description : HARDCOPYIII LCELL_HSADDER VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiii_atom_pack.all;
entity hardcopyiii_lcell_hsadder is
generic (
dataa_width : integer := 2;
datab_width : integer := 2;
cin_inverted : string := "off";
lpm_type : string := "hardcopyiii_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_datab_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_cin_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic_vector(dataa_width - 1 downto 0) := (OTHERS => '0');
datab : in std_logic_vector(datab_width - 1 downto 0) := (OTHERS => '0');
cin : in std_logic := '0';
sumout: out std_logic_vector((calc_sum_len(dataa_width, datab_width)) - 2 downto 0);
cout : out std_logic
);
--attribute VITAL_LEVEL0 of hardcopyiii_lcell_hsadder : entity is TRUE;
end hardcopyiii_lcell_hsadder;
architecture vital_lcell_hsadder of hardcopyiii_lcell_hsadder is
-- attribute VITAL_LEVEL0 of vital_lcell_hsadder : architecture is TRUE;
constant sumout_width : integer := calc_sum_len(dataa_width, datab_width);
signal dataa_ipd : std_logic_vector(dataa_width - 1 downto 0);
signal datab_ipd : std_logic_vector(datab_width - 1 downto 0);
signal cin_ipd : std_logic := '0';
signal idataa_ipd : std_logic_vector(sumout_width - 1 downto 0);
signal idatab_ipd : std_logic_vector(sumout_width - 1 downto 0);
-- internal signal
signal cin_sel : std_logic;
-- output signal
signal sumout_tmp : std_logic_vector(sumout_width - 1 DOWNTO 0) := (OTHERS => '0');
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
loopa : FOR i in dataa'RANGE GENERATE
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
END GENERATE;
loopb : FOR i in datab'RANGE GENERATE
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
END GENERATE;
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
idataa_ipd <= ('0' & dataa_ipd);
idatab_ipd <= ('0' & datab_ipd);
cin_sel <= (NOT cin_ipd) WHEN cin_inverted = "on" ELSE cin_ipd;
sumout_tmp <= (idataa_ipd + idatab_ipd + 1) WHEN cin_sel = '1' ELSE
(idataa_ipd + idatab_ipd);
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
do1 : for i in sumout'RANGE generate
process(sumout_tmp(i))
VARIABLE sumout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => sumout(i),
OutSignalName => "sumout",
OutTemp => sumout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout(i),
TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout(i),
TRUE),
2 => (cin_ipd'last_event, tpd_cin_sumout(i), TRUE))
,
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(sumout_tmp(sumout_width - 1))
VARIABLE cout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "cout",
OutTemp => sumout_tmp(sumout_width - 1),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout,TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout,TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout,TRUE))
,
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end block;
end vital_lcell_hsadder;
---------------------------------------------------------------------------------------
--
-- Entity Name: hardcopyiii_otp
--
-- Description: VHDL Simulation model for HARDCOPYIII OTP (One Time Programmable)
--
---------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY STD;
USE STD.textio.ALL;
USE work.hardcopyiii_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiii_otp IS
GENERIC
(
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
TimingChecksOn : Boolean := True;
tipd_otpclken : VitalDelayType01 := DefpropDelay01;
tipd_otpclk : VitalDelayType01 := DefpropDelay01;
tipd_otpshiftnld : VitalDelayType01 := DefpropDelay01;
tpd_otpshiftnld_otpdout : VitalDelayType01 := DefpropDelay01;
tsetup_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
data_width : INTEGER := 128;
init_data : STD_LOGIC_VECTOR(127 DOWNTO 0) := (OTHERS => '0');
init_file : STRING := "init_file.hex";
lpm_type : STRING := "hardcopyiii_otp";
lpm_hint : STRING := "true"
);
---------- PORT DECLARATIONS ---------
PORT
(
otpclken : IN STD_LOGIC := '1';
otpclk : IN STD_LOGIC := '0';
otpshiftnld : IN STD_LOGIC := '0';
otpdout : OUT STD_LOGIC
);
END hardcopyiii_otp;
ARCHITECTURE arch OF hardcopyiii_otp IS
SIGNAL otpclken_ipd : STD_LOGIC := '1';
SIGNAL otpclk_ipd : STD_LOGIC := '0';
SIGNAL otpshiftnld_ipd : STD_LOGIC := '0';
SIGNAL otpdout_tmp : STD_LOGIC := '0';
SIGNAL viol_notifier : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL prev_loc : INTEGER := -1;
SIGNAL current_loc : INTEGER := 0;
SIGNAL first_use : STD_LOGIC := '1';
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (otpclken_ipd, otpclken, tipd_otpclken);
VitalWireDelay (otpclk_ipd, otpclk, tipd_otpclk);
VitalWireDelay (otpshiftnld_ipd, otpshiftnld, tipd_otpshiftnld);
END BLOCK;
---------------------------
-- Timing check section --
---------------------------
TimingChecks: PROCESS(otpclk_ipd, otpshiftnld_ipd)
VARIABLE Tviol_otpshiftnld_otpclk : STD_ULOGIC := '0';
VARIABLE TimingData_otpshiftnld_otpclk : VitalTimingDataType:= VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck
(
TestSignal => otpshiftnld_ipd,
TestSignalName => "otpshiftnld",
RefSignal => otpclk_ipd,
RefSignalName => "otpclk",
SetupHigh => tsetup_otpshiftnld_otpclk_noedge_posedge,
SetupLow => tsetup_otpshiftnld_otpclk_noedge_posedge,
HoldHigh => thold_otpshiftnld_otpclk_noedge_posedge,
HoldLow => thold_otpshiftnld_otpclk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => "/hardcopyiii_otp",
TimingData => TimingData_otpshiftnld_otpclk,
Violation => Tviol_otpshiftnld_otpclk
);
END IF;
END PROCESS TimingChecks;
----------------------------
-- Functionality Section --
----------------------------
PROCESS(prev_loc)
BEGIN
current_loc <= prev_loc + 1;
END PROCESS;
PROCESS(otpclk_ipd)
BEGIN
IF (otpclk_ipd'EVENT and otpclk_ipd = '1') THEN
-- operation only if clock enable is high
IF (otpclken_ipd = '1') THEN
-- shift data
IF (otpshiftnld_ipd = '1' AND first_use = '0') THEN
-- shifting out '0' if otpclken and otpshiftnld is high beyond 128 clock cycles
IF (prev_loc = 127) THEN
otpdout_tmp <= '0';
-- shifting the data bit by bit
ELSE
otpdout_tmp <= init_data(current_loc);
prev_loc <= current_loc;
END IF;
-- load data
ELSIF (otpshiftnld_ipd = '0') THEN
otpdout_tmp <= init_data(0);
first_use <= '0';
prev_loc <= 0;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------
-- Path Delay Section --
-------------------------
PathDelay : BLOCK
BEGIN
PROCESS(otpdout_tmp)
VARIABLE otpdout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01
(
OutSignal => otpdout,
OutSignalName => "otpdout",
OutTemp => otpdout_tmp,
Paths => ( 0 => (otpshiftnld_ipd'last_event, tpd_otpshiftnld_otpdout, TRUE)),
GlitchData => otpdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END BLOCK;
END arch;
| gpl-3.0 | bcdb98b768371f09b6050e3ce64672b7 | 0.469491 | 4.167155 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiii_atoms.vhd | 1 | 361,479 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cycloneiii_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiii_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cycloneiii_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiii_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cycloneiii_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiii_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cycloneiii_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiii_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
| gpl-3.0 | 018b36cbca6e5c71838d08cbcbd89b89 | 0.464553 | 4.172292 | false | false | false | false |
shvorin/pcie-emu | hdllib/common/vdata.vhd | 1 | 2,184 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
use work.util.all;
package vdata is
---------------------------------------------------------------------------
-- vdata: a flit with 'data valid' bit
---------------------------------------------------------------------------
type vdata_t is record
data : qword;
dv : boolean;
end record;
type vdata256_t is record
data : std_logic_vector(255 downto 0);
dv : boolean;
end record;
function nothing return vdata_t;
function nothing return vdata256_t;
type vdata_array is array (integer range <>) of vdata_t;
type vdata256_array is array (integer range <>) of vdata256_t;
-- binary (i.e. via std_logic_vector) representation of vdata256_t
subtype vdata256_binary is std_logic_vector(256 + 1 - 1 downto 0);
function compose(arg : vdata256_t) return vdata256_binary;
function decompose(arg : vdata256_binary) return vdata256_t;
type vdata256_binary_array is array (integer range <>) of vdata256_binary;
component vdata256_bypass
port (
vdata_i : in vdata256_t;
ready_i : out boolean;
--
vdata_o : out vdata256_t;
ready_o : in boolean;
--
clk : in std_logic;
reset : in std_logic);
end component;
end vdata;
package body vdata is
function nothing return vdata_t is
begin
return (dv => false, data => (others => 'X'));
end;
function nothing return vdata256_t is
begin
return (dv => false, data => (others => 'X'));
end;
function compose(arg : vdata256_t) return vdata256_binary is
begin
return to_stdl(arg.dv) & arg.data;
end;
function decompose(arg : vdata256_binary) return vdata256_t is
begin
return (dv => arg(arg'high) = '1',
data => arg(data256_t'range));
end;
end vdata;
| bsd-3-clause | 0dd42e4e898796d9decfcbba445aa82f | 0.565476 | 3.928058 | false | false | false | false |
alvieboy/xtc-base | regbank_3p.vhd | 1 | 2,281 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity regbank_3p is
generic (
ADDRESS_BITS: integer := 4;
ZEROSIZE: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_wr: in std_logic_vector(31 downto 0);
rb3_we: in std_logic;
rb3_en: in std_logic
-- RTL Debug access
-- dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
-- dbg_do: out std_logic_vector(32-1 downto 0)
);
end entity regbank_3p;
architecture behave of regbank_3p is
component regbank_2p is
generic (
ADDRESS_BITS: integer := 4;
ZEROSIZE: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic
);
end component;
signal dbg_addr: std_logic_vector(address_bits-1 downto 0) := (others => '0');
signal dbg_do: std_logic_vector(32-1 downto 0);
begin
-- Register bank, three port
rba: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS,
ZEROSIZE => ZEROSIZE
)
port map (
clk => clk,
rb1_addr => rb1_addr,
rb1_en => rb1_en,
rb1_rd => rb1_rd,
rb2_addr => rb3_addr,
rb2_wr => rb3_wr,
rb2_we => rb3_we,
rb2_en => rb3_en--,
--dbg_addr => dbg_addr,
-- dbg_do => dbg_do
);
rbb: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS,
ZEROSIZE => ZEROSIZE
)
port map (
clk => clk,
rb1_addr => rb2_addr,
rb1_en => rb2_en,
rb1_rd => rb2_rd,
rb2_addr => rb3_addr,
rb2_wr => rb3_wr,
rb2_we => rb3_we,
rb2_en => rb3_en
);
end behave;
| bsd-3-clause | ce50163c4b85c0aac5c1024214ad5371 | 0.573433 | 2.802211 | false | false | false | false |
alvieboy/xtc-base | xtc_wbmux2.vhd | 1 | 4,741 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity xtc_wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end entity xtc_wbmux2;
architecture behave of xtc_wbmux2 is
component reqcnt is
port (
clk: in std_logic;
rst: in std_logic;
stb: in std_logic;
cyc: in std_logic;
stall:in std_logic;
ack: in std_logic;
req: out std_logic
);
end component;
signal select_zero: std_logic;
--signal trcnt0, trcnt1: unsigned(3 downto 0);
signal t0,t1: std_logic;
signal qdat,qtag: std_logic_vector(31 downto 0);
signal queue, queued, qerr: std_logic;
signal internal_stall:std_logic;
signal req0,req1: std_logic;
signal endt0,endt1: std_logic;
begin
select_zero<='1' when m_wbi.adr(select_line)='0' else '0';
req0<=(select_zero and m_wbi.stb) and not internal_stall;
req1<=((not select_zero) and m_wbi.stb) and not internal_stall;
s0_wbo.dat <= m_wbi.dat;
s0_wbo.adr <= m_wbi.adr;
s0_wbo.stb <= req0;--m_wbi.stb and not internal_stall;
s0_wbo.we <= m_wbi.we;
s0_wbo.sel <= m_wbi.sel;
s0_wbo.tag <= m_wbi.tag;
s0_wbo.cti <= m_wbi.cti;
s0_wbo.bte <= m_wbi.bte;
s1_wbo.dat <= m_wbi.dat;
s1_wbo.adr <= m_wbi.adr;
s1_wbo.stb <= req1;--m_wbi.stb and not internal_stall;
s1_wbo.we <= m_wbi.we;
s1_wbo.sel <= m_wbi.sel;
s1_wbo.tag <= m_wbi.tag;
s1_wbo.cti <= m_wbi.cti;
s1_wbo.bte <= m_wbi.bte;
cnt0: reqcnt port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
stb => req0,
cyc => m_wbi.cyc,
stall => s0_wbi.stall,
ack => endt0,
req => t0
);
endt0<=s0_wbi.ack or s0_wbi.err;
cnt1: reqcnt port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
stb => req1,
cyc => m_wbi.cyc,
stall => s1_wbi.stall,
ack => endt1,
req => t1
);
endt1 <= s1_wbi.ack or s1_wbi.err;
process(m_wbi.cyc,select_zero,m_wbi.stb,t0,t1)
begin
if m_wbi.cyc='0' then
s0_wbo.cyc<='0';
s1_wbo.cyc<='0';
else
s0_wbo.cyc<=(select_zero and m_wbi.cyc) or t0;
s1_wbo.cyc<=(( not select_zero ) and m_wbi.cyc) or t1;
end if;
end process;
process(t0,t1,m_wbi.stb,m_wbi.cyc,select_zero)
begin
internal_stall<='0';
if m_wbi.stb='1' and m_wbi.cyc='1' then
-- Check if same request
if select_zero='1' and t1='1' then
internal_stall<='1';
elsif select_zero='0' and t0='1' then
internal_stall<='1';
end if;
end if;
end process;
process(select_zero,s1_wbi.stall,s0_wbi.stall,internal_stall)
begin
if select_zero='0' then
m_wbo.stall<=s1_wbi.stall or internal_stall;
else
m_wbo.stall<=s0_wbi.stall or internal_stall;
end if;
end process;
-- synthesis translate_off
process (wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if is_x(s0_wbi.err) then
--report "Slave0 'err' is X" severity failure;
end if;
if is_x(s1_wbi.err) then
--report "Slave1 'err' is X" severity failure;
end if;
end if;
end process;
-- synthesis translate_on
-- Process responses from both slaves.
-- USE ONLY IN SIMULATION FOR NOW!!!!!
process(s0_wbi,s1_wbi,queued,qdat,qtag)
variable sel: std_logic_vector(1 downto 0);
begin
sel(0) := s0_wbi.ack or s0_wbi.err;
sel(1) := s1_wbi.ack or s1_wbi.err;
queue <= '0';
case sel is
when "00" =>
if queued='0' then
m_wbo.ack<='0';
m_wbo.err<='0';
m_wbo.dat<=(others => 'X');
m_wbo.tag<=(others => 'X');
else
m_wbo.ack<='1';
m_wbo.dat<=qdat;
m_wbo.err<=qerr;
m_wbo.tag<=qtag;
end if;
when "01" =>
m_wbo.ack<='1';
m_wbo.dat<=s0_wbi.dat;
m_wbo.err<=s0_wbi.err;
m_wbo.tag<=s0_wbi.tag;
when "10" =>
m_wbo.ack<='1';
m_wbo.dat<=s1_wbi.dat;
m_wbo.err<=s1_wbi.err;
m_wbo.tag<=s1_wbi.tag;
when "11" =>
queue <= '1'; -- Queue S1 request.
m_wbo.ack<='1';
m_wbo.dat<=s0_wbi.dat;
m_wbo.err<=s0_wbi.err;
m_wbo.tag<=s0_wbi.tag;
when others => null;
end case;
end process;
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
queued<='0';
else
queued<='0';
if queue='1' and queued='0' then
queued<='1';
qdat <= s1_wbi.dat;
qtag <= s1_wbi.tag;
qerr <= s1_wbi.err;
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | f41337431826be03da3c1328e841e808 | 0.591436 | 2.569648 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiv_hssi_components.vhd | 1 | 127,621 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package STRATIXIV_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function stratixiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function stratixiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function stratixiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- stratixiv_hssi_clock_divider
--
COMPONENT stratixiv_hssi_clock_divider
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_refclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchdonein :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_clk0in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_vcobypassin : VitalDelayType01 := DefpropDelay01;
tipd_clk1in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchbaseclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdig : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(100 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "stratixiv_hssi_clock_divider";
channel_num : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
data_rate : INTEGER := 0;
divide_by : INTEGER := 4;
divider_type : STRING := "CHANNEL_REGULAR";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
enable_refclk_out : STRING := "false";
inclk_select : INTEGER := 0;
logical_channel_address : INTEGER := 0;
pre_divide_by : INTEGER := 1;
rate_switch_base_clk_in_select : INTEGER := 0;
rate_switch_done_in_select : INTEGER := 0;
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
refclkin_select : INTEGER := 0;
select_local_rate_switch_base_clock : STRING := "false";
select_local_rate_switch_done : STRING := "true"; -- shawn
select_local_refclk : STRING := "false";
select_refclk_dig : STRING := "false";
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0;
sim_refclkout_phase_shift : INTEGER := 0;
use_coreclk_out_post_divider : STRING := "false";
use_refclk_post_divider : STRING := "false";
use_vco_bypass : STRING := "false"
);
PORT (
clk0in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
clk1in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(100 - 1 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchbaseclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rateswitchdonein : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclkdig : IN STD_LOGIC := '0';
refclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
vcobypassin : IN STD_LOGIC := '0';
analogfastrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogfastrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkpulse : OUT STD_LOGIC;
analogrefclkpulseshifted : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(100 - 1 DOWNTO 0);
rateswitchbaseclock : OUT STD_LOGIC;
rateswitchdone : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_pll
--
COMPONENT stratixiv_hssi_pll
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_earlyeios : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_pfdfbclk : VitalDelayType01 := DefpropDelay01;
tipd_powerdown : VitalDelayType01 := DefpropDelay01;
tipd_inclk :VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tpd_inclk_clk : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_pll";
auto_settings : STRING := "true";
bandwidth_type : STRING := "Auto";
base_data_rate : STRING := "unused";
channel_num : INTEGER := 0;
charge_pump_current_bits : INTEGER := 0;
charge_pump_mode_bits : INTEGER := 0;
charge_pump_test_enable : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
fast_lock_control : STRING := "false";
inclk0_input_period : INTEGER := 0;
inclk1_input_period : INTEGER := 0;
inclk2_input_period : INTEGER := 0;
inclk3_input_period : INTEGER := 0;
inclk4_input_period : INTEGER := 0;
inclk5_input_period : INTEGER := 0;
inclk6_input_period : INTEGER := 0;
inclk7_input_period : INTEGER := 0;
inclk8_input_period : INTEGER := 0;
inclk9_input_period : INTEGER := 0;
input_clock_frequency : STRING := "unused";
logical_channel_address : INTEGER := 0;
logical_tx_pll_number : INTEGER := 0;
loop_filter_c_bits : INTEGER := 0;
loop_filter_r_bits : INTEGER := 0;
m : INTEGER := 0;
n : INTEGER := 0;
pd_charge_pump_current_bits : INTEGER := 0;
pd_loop_filter_r_bits : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
pfd_fb_select : STRING := "internal";
pll_type : STRING := "Auto";
protocol_hint : STRING := "basic";
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
sim_is_negative_ppm_drift : STRING := "false";
sim_net_ppm_variation : INTEGER := 0;
test_charge_pump_current_down : STRING := "false";
test_charge_pump_current_up : STRING := "false";
use_refclk_pin : STRING := "false";
vco_data_rate : INTEGER := 0;
vco_divide_by : INTEGER := 0;
vco_range : STRING := "low";
vco_multiply_by : INTEGER := 0;
vco_post_scale : INTEGER := 0;
vco_tuning_bits : INTEGER := 0;
volt_reg_control_bits : INTEGER := 0;
volt_reg_output_bits : INTEGER := 0;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0;
PARAM_DELAY : INTEGER := 0
);
PORT (
areset : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
earlyeios : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 - 1 DOWNTO 0) := (others => '0');
inclk : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
locktorefclk : IN STD_LOGIC := '1';
pfdfbclk : IN STD_LOGIC := '0';
powerdown : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locked : OUT STD_LOGIC;
pfdfbclkout : OUT STD_LOGIC;
pfdrefclkout : OUT STD_LOGIC;
vcobypassout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_tx_pma
--
COMPONENT stratixiv_hssi_tx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_datain :VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(20 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0inpulse : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_pclk : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_fastrefclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_refclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk4inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_rxdetecten : VitalDelayType01 := DefpropDelay01;
tipd_refclk1inpulse : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpmareset : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revserialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_refclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxpowerdown : VitalDelayType01 := DefpropDelay01;
tipd_refclk3inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdetectclk : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiv_hssi_tx_pma";
analog_power : STRING := "1.5V";
channel_number : INTEGER := 9999;
channel_type : STRING := "auto";
clkin_select : INTEGER := 0; -- 9999; out of bound in loading
clkmux_delay : STRING := "false";
common_mode : STRING := "0.6V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_reverse_serial_loopback : STRING := "false";
logical_channel_address : INTEGER := 0;
logical_protocol_hint_0 : STRING := "basic";
logical_protocol_hint_1 : STRING := "basic";
logical_protocol_hint_2 : STRING := "basic";
logical_protocol_hint_3 : STRING := "basic";
low_speed_test_select : INTEGER := 9999;
physical_clkin0_mapping : STRING := "x1";
physical_clkin1_mapping : STRING := "x4";
physical_clkin2_mapping : STRING := "xn_top";
physical_clkin3_mapping : STRING := "xn_bottom";
physical_clkin4_mapping : STRING := "hypertransport";
preemp_pretap : INTEGER := 0;
preemp_pretap_inv : STRING := "false";
preemp_tap_1 : INTEGER := 0;
preemp_tap_1_a : INTEGER := 0;
preemp_tap_1_b : INTEGER := 0;
preemp_tap_1_c : INTEGER := 0;
preemp_tap_2 : INTEGER := 0;
preemp_tap_2_inv : STRING := "false";
protocol_hint : STRING := "basic";
rx_detect : INTEGER := 9999;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_pclk : STRING := "false";
use_pma_direct : STRING := "false";
use_rx_detect : STRING := "false";
use_ser_double_data_mode : STRING := "false";
vod_selection : INTEGER := 0;
vod_selection_a : INTEGER := 0;
vod_selection_b : INTEGER := 0;
vod_selection_c : INTEGER := 0;
vod_selection_d : INTEGER := 0
);
PORT (
datain : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(20 - 1 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(11 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
pclk : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk0inpulse : IN STD_LOGIC := '0';
refclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk1inpulse : IN STD_LOGIC := '0';
refclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk2inpulse : IN STD_LOGIC := '0';
refclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk3inpulse : IN STD_LOGIC := '0';
refclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
refclk4inpulse : IN STD_LOGIC := '0';
revserialfdbk : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dftout : OUT STD_LOGIC_VECTOR(6 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_rx_pma
--
COMPONENT stratixiv_hssi_rx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_rxpmareset : VitalDelayType01 := DefpropDelay01;
tipd_plllocked : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_ignorephslck : VitalDelayType01 := DefpropDelay01;
tipd_locktoref : VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_adcestandby : VitalDelayType01 := DefpropDelay01;
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken : VitalDelayType01 := DefpropDelay01;
tipd_adcereset : VitalDelayType01 := DefpropDelay01;
tipd_deserclock :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_freqlock : VitalDelayType01 := DefpropDelay01;
tipd_offsetcancellationen : VitalDelayType01 := DefpropDelay01;
tipd_testbussel :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoverdatain :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_seriallpbkin : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_adaptcapture : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "stratixiv_hssi_rx_pma";
adaptive_equalization_mode : STRING := "none";
allow_serial_loopback : STRING := "false";
allow_vco_bypass : INTEGER := 0;
analog_power : STRING := "1.4V";
channel_number : INTEGER := 0;
channel_type : STRING := "auto";
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dfe_piclk_bandwidth : INTEGER := 0;
dfe_piclk_phase : INTEGER := 0;
dfe_piclk_sel : INTEGER := 0;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_adapt_seq_control : INTEGER := 0;
eq_dc_gain : INTEGER := 0;
eq_max_gradient_control : INTEGER := 0;
eqa_ctrl : INTEGER := 0;
eqb_ctrl : INTEGER := 0;
eqc_ctrl : INTEGER := 0;
eqd_ctrl : INTEGER := 0;
eqv_ctrl : INTEGER := 0;
eyemon_bandwidth : INTEGER := 0;
force_signal_detect : STRING := "true";
ignore_lock_detect : STRING := "false";
logical_channel_address : INTEGER := 0;
low_speed_test_select : INTEGER := 0;
offset_cancellation : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
send_direct_reverse_serial_loopback : STRING := "None";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 2;
signal_detect_loss_threshold : INTEGER := 3;
termination : STRING := "OCT 100 Ohms";
use_deser_double_data_width : STRING := "false";
use_external_termination : STRING := "false";
use_pma_direct : STRING := "false";
PARAM_DELAY : INTEGER := 0
);
PORT (
adaptcapture : IN STD_LOGIC := '0';
adcepowerdn : IN STD_LOGIC := '0';
adcereset : IN STD_LOGIC := '0';
adcestandby : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(38 - 1 DOWNTO 0) := (others => '0');
freqlock : IN STD_LOGIC := '0';
ignorephslck : IN STD_LOGIC := '0';
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
offsetcancellationen : IN STD_LOGIC := '0';
plllocked : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdatain : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rxpmareset : IN STD_LOGIC := '0';
seriallpbken : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
adaptdone : OUT STD_LOGIC;
analogtestbus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dataoutfull : OUT STD_LOGIC_VECTOR(20 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
locktorefout : OUT STD_LOGIC;
ppmdetectclkrel : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
revserialfdbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_tx_pcs
--
COMPONENT stratixiv_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
auto_spd_self_switch_enable : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_symbol_swap : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none";
ph_fifo_xn_mapping1 : STRING := "none";
ph_fifo_xn_mapping2 : STRING := "none";
ph_fifo_xn_select : INTEGER := 9999;
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
use_serializer_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk"; -- INT_CLK // int_clk
use_top_quad_as_mater : STRING := "true"; -- NEW_PARAM todo: select top/bottom to provide phfifo pointers
dprio_width : INTEGER := 150
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(39 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(43 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); --fix_width
forcedispcompliance : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
freezptr : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
hiptxdeemph : IN STD_LOGIC := '0';
hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
localrefclk : IN STD_LOGIC := '0';
phfifobyteserdisable : IN STD_LOGIC := '0';
phfifoptrsreset : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifoxnbottombytesel : IN STD_LOGIC := '0';
phfifoxnbottomrdclk : IN STD_LOGIC := '0';
phfifoxnbottomrdenable : IN STD_LOGIC := '0';
phfifoxnbottomwrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxntopbytesel : IN STD_LOGIC := '0';
phfifoxntoprdclk : IN STD_LOGIC := '0';
phfifoxntoprdenable : IN STD_LOGIC := '0';
phfifoxntopwrenable : IN STD_LOGIC := '0';
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
pipestatetransdone : IN STD_LOGIC := '0';
pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph;
pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0]
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
iqpphfifobyteselout : OUT STD_LOGIC;
iqpphfifordclkout : OUT STD_LOGIC;
iqpphfifordenableout : OUT STD_LOGIC;
iqpphfifowrenableout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifooverflow : OUT STD_LOGIC;
phfifordclkout : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rateswitchout : OUT STD_LOGIC;
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_rx_pcs
--
COMPONENT stratixiv_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_phfifox8bytesel : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidlerateswitch : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerstate :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnptrsreset :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_autospdxnconfigsel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_hiprateswitch : VitalDelayType01 := DefpropDelay01;
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_elecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_iqpautospdxnspgchg :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_rxfound :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_autospdxnspdchg :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_rx_pcs";
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
auto_spd_self_switch_enable : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_double_data_mode_mask_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
dec_8b_10b_polarity_inv_enable : STRING := "false";
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_k_detect : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_deep_align : STRING := "false";
enable_deep_align_byte_swap : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_true_complement_match_in_word_align : STRING := "true";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false"; -- b165
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_disable : STRING := "false";
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_select : INTEGER := 9999;
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove
pma_done_count : INTEGER := 53392; --ww47_cram_p1
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_almost_empty_threshold : INTEGER := 11; -- <integer 0-15>;
rate_match_almost_full_threshold : INTEGER := 13; -- <integer 0-15>;
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int_clk"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deserializer_double_data_mode : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
use_rising_edge_triggered_pattern_align : STRING := "false"; -- <true/false>; //83 para: new=23 rem=40
enable_phfifo_bypass : STRING := "false"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
autospdxnconfigsel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down
autospdxnspdchg : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down)
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
disablefifordin : IN STD_LOGIC := '0';
disablefifowrin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
hiprateswitch : IN STD_LOGIC := '0'; -- hip_rate
invpol : IN STD_LOGIC := '0';
iqpautospdxnspgchg : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnptrsreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnwrclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifox8bytesel : IN STD_LOGIC := '0';
phfifox8rdenable : IN STD_LOGIC := '0';
phfifox8wrclk : IN STD_LOGIC := '0';
phfifox8wrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX.
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down
phfifoxnwrclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX.
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxelecidlerateswitch : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
wareset : IN STD_LOGIC := '0'; -- new in 9.1
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
a1a2sizeout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
autospdrateswitchout : OUT STD_LOGIC;
autospdspdchgout : OUT STD_LOGIC; --ww47_out speed_chang_out_pipe
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- new in 6.1
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
disablefifordout : OUT STD_LOGIC;
disablefifowrout : OUT STD_LOGIC;
disperr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
iqpphfifobyteselout : OUT STD_LOGIC; --ww47_out rx_we_out_pipe
iqpphfifoptrsresetout : OUT STD_LOGIC; --ww47_out reset_pc_pters_out_pipe
iqpphfifordenableout : OUT STD_LOGIC; --ww47_out rd_enable_pipe_out
iqpphfifowrclkout : OUT STD_LOGIC; --ww47_out rx_div2_sync_out_pipe
iqpphfifowrenableout : OUT STD_LOGIC; --ww47_out wr_enable_out_pipe
k1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
k2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
patterndetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifobyteserdisableout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifooverflow : OUT STD_LOGIC;
phfifoptrsresetout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrclkout : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifowrenableout : OUT STD_LOGIC;
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifoalmostempty : OUT STD_LOGIC;
rmfifoalmostfull : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_cmu
--
COMPONENT stratixiv_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_cmu";
analog_test_bus_enable : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
bonded_quad_mode : STRING := "none";
bypass_bandgap : STRING := "false";
central_test_bus_select : INTEGER := 0;
cmu_type : STRING := "regular";
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
migrated_from_prev_family : STRING := "false";
num_con_align_chars_for_align : INTEGER := 4;
num_con_errors_for_align_loss : INTEGER := 2;
num_con_good_data_for_align_approach : INTEGER := 3;
offset_all_errors_align : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pma_done_count : INTEGER := 0;
portaddr : INTEGER := 1;
rx0_auto_spd_self_switch_enable : STRING := "false";
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_phfifo_wait_cnt : INTEGER := 0;
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_master_direction : STRING := "none";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
test_mode : STRING := "false";
tx0_auto_spd_self_switch_enable : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reg_mode : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_master_direction : STRING := "none";
tx_pll0_used_as_rx_cdr : STRING := "false";
tx_pll1_used_as_rx_cdr : STRING := "false";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_deskew_fifo : STRING := "false";
vcceh_voltage : STRING := "3.0V";
vcceh_voltage_user_specified_auto : STRING := "true";
protocol_hint : STRING := "basic";
clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1";
cmu_divider0_inclk0_physical_mapping : STRING := "pll0";
cmu_divider0_inclk1_physical_mapping : STRING := "pll1";
cmu_divider0_inclk2_physical_mapping : STRING := "x4";
cmu_divider0_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider0_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider1_inclk0_physical_mapping : STRING := "pll0";
cmu_divider1_inclk1_physical_mapping : STRING := "pll1";
cmu_divider1_inclk2_physical_mapping : STRING := "x4";
cmu_divider1_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider1_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider2_inclk0_physical_mapping : STRING := "pll0";
cmu_divider2_inclk1_physical_mapping : STRING := "pll1";
cmu_divider2_inclk2_physical_mapping : STRING := "x4";
cmu_divider2_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider2_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider3_inclk0_physical_mapping : STRING := "pll0";
cmu_divider3_inclk1_physical_mapping : STRING := "pll1";
cmu_divider3_inclk2_physical_mapping : STRING := "x4";
cmu_divider3_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider3_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider4_inclk0_physical_mapping : STRING := "pll0";
cmu_divider4_inclk1_physical_mapping : STRING := "pll1";
cmu_divider4_inclk2_physical_mapping : STRING := "x4";
cmu_divider4_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider4_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider5_inclk0_physical_mapping : STRING := "pll0";
cmu_divider5_inclk1_physical_mapping : STRING := "pll1";
cmu_divider5_inclk2_physical_mapping : STRING := "x4";
cmu_divider5_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider5_inclk4_physical_mapping : STRING := "xn_b";
pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll0_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll0_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll0_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll0_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll0_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll0_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll1_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll1_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll1_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll1_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll1_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll1_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll2_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll2_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll2_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll2_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll2_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll2_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll3_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll3_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll3_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll3_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll3_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll3_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll4_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll4_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll4_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll4_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll4_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll4_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll5_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll5_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll5_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll5_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll5_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll5_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll0_logical_to_physical_mapping : INTEGER := 0;
pll1_logical_to_physical_mapping : INTEGER := 1;
pll2_logical_to_physical_mapping : INTEGER := 2;
pll3_logical_to_physical_mapping : INTEGER := 3;
pll4_logical_to_physical_mapping : INTEGER := 4;
pll5_logical_to_physical_mapping : INTEGER := 5;
refclk_divider0_logical_to_physical_mapping : INTEGER := 0;
refclk_divider1_logical_to_physical_mapping : INTEGER := 1;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
rx4_logical_to_physical_mapping : INTEGER := 4;
rx5_logical_to_physical_mapping : INTEGER := 5;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
tx4_logical_to_physical_mapping : INTEGER := 4;
tx5_logical_to_physical_mapping : INTEGER := 5;
tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0');
fixedclk : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchdonein : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
rxanalogreset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxclk : IN STD_LOGIC := '0';
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0');
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(9999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
txpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
autospdx4configsel : OUT STD_LOGIC;
autospdx4rateswitchout : OUT STD_LOGIC;
autospdx4spdchg : OUT STD_LOGIC;
clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
extra10gout : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
phfifiox4ptrsreset : OUT STD_LOGIC;
pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
quadresetout : OUT STD_LOGIC;
refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(6999 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_calibration_block
--
COMPONENT stratixiv_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "stratixiv_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic);
END COMPONENT;
--
-- stratixiv_hssi_refclk_divider
--
COMPONENT stratixiv_hssi_refclk_divider
GENERIC (
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
enable_divider : STRING := "false";
lpm_type : STRING := "stratixiv_hssi_refclk_divider";
refclk_coupling_termination : STRING := "dc_coupling_external_termination";
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
inclk : IN STD_LOGIC:= '0';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
end stratixiv_hssi_components;
package body STRATIXIV_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function stratixiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end stratixiv_tx_pcs_mph_fifo_xn_mapping;
function stratixiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end stratixiv_tx_pcs_mphfifo_index;
function stratixiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end stratixiv_tx_pcs_miqp_phfifo_index;
end STRATIXIV_HSSI_COMPONENTS;
| gpl-3.0 | 0b0d3fc4938111811e5dc5a228842996 | 0.499879 | 4.282009 | false | false | false | false |
thoralt/KCVGA | FPGA/PIC32_INTERFACE.vhd | 1 | 7,642 | --
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED."+";
USE IEEE.STD_LOGIC_UNSIGNED."-";
USE IEEE.STD_LOGIC_UNSIGNED."=";
ENTITY PIC32_INTERFACE IS
PORT
(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- SRAM : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- OUT_FIFO_WR : OUT STD_LOGIC;
-- OUT_FIFO_FULL : IN STD_LOGIC;
nWR : IN STD_LOGIC;
nRD : IN STD_LOGIC;
-- FLAGS : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- DEBUG : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
SRAM_A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output
SRAM_D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output
SRAM_nOE : OUT STD_LOGIC; -- SRAM output enable
SRAM_nWE : OUT STD_LOGIC; -- SRAM write enable
SRAM_nCE : OUT STD_LOGIC; --
SRAM_nBLE : OUT STD_LOGIC; --
SRAM_nBHE : OUT STD_LOGIC --
-- suppress_no_load_pins_warning : IN STD_LOGIC
);
END PIC32_INTERFACE;
ARCHITECTURE Behavioral OF PIC32_INTERFACE IS
-- command constants
CONSTANT cmd_write_address : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT cmd_write_data : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
CONSTANT cmd_read_data : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000010";
CONSTANT cmd_bank_0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000011";
CONSTANT cmd_bank_1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000100";
CONSTANT cmd_read_debug0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000000";
CONSTANT cmd_read_debug1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000001";
CONSTANT cmd_read_debug2 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000010";
CONSTANT cmd_read_debug3 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000011";
SIGNAL A_sync : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL D_sync : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL D_buf, D_buf_next : STD_LOGIC_VECTOR(7 DOWNTO 0); -- internal value for D
SIGNAL cmd, cmd_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL data, data_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL data_s2f : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL addr, addr_next : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL nRD_sync, nWR_sync : STD_LOGIC;
SIGNAL mem, mem_next, rw, rw_next : STD_LOGIC;
BEGIN
-- only drive data output when PIC32 is trying to read
D <= D_buf WHEN nRD_sync = '0' AND nWR_sync = '1' ELSE
(OTHERS => 'Z');
-- set all registers and I/O synchronously
PROCESS (RESET, CLK)
BEGIN
IF RESET = '1' THEN
nRD_sync <= '0';
nWR_sync <= '0';
addr(16) <= '0';
ELSIF rising_edge(CLK) THEN
-- sync all inputs from PIC32 on rising edge of CLK
nRD_sync <= nRD;
nWR_sync <= nWR;
A_sync <= A;
D_sync <= D;
-- update all registers and I/O with their next values
D_buf <= D_buf_next;
data <= data_next;
addr <= addr_next;
cmd <= cmd_next;
mem <= mem_next;
rw <= rw_next;
END IF;
END PROCESS;
-- next state logic: PIC32 read
PROCESS (nRD_sync, A_sync, cmd, addr, data_s2f, D_buf)
BEGIN
-- default value for next state: keep previous value
D_buf_next <= D_buf;
IF nRD_sync = '0' THEN
CASE A_sync IS
WHEN "00" => -- read register 0: flags
D_buf_next <= addr(16) & "0000000";
WHEN "01" => -- read register 1: debug register
CASE cmd IS
WHEN cmd_read_debug3 =>
D_buf_next <= "11011110"; -- DE
WHEN cmd_read_debug2 =>
D_buf_next <= "10101101"; -- AD
WHEN cmd_read_debug1 =>
D_buf_next <= "10111110"; -- BE
WHEN cmd_read_debug0 =>
D_buf_next <= "11101111"; -- EF
WHEN OTHERS =>
D_buf_next <= D_buf; -- no change
END CASE;
WHEN "10" => -- read register 2: L byte of SRAM data
D_buf_next <= data_s2f(7 DOWNTO 0);
WHEN "11" => -- read register 3: H byte of SRAM data
D_buf_next <= data_s2f(15 DOWNTO 8);
WHEN OTHERS =>
D_buf_next <= D_buf; -- no change
END CASE;
END IF;
END PROCESS;
-- next state logic: PIC32 write
PROCESS (nWR_sync, A_sync, D_sync, data, rw, mem, addr, cmd)
BEGIN
-- default values for next state: keep previous values
rw_next <= rw;
addr_next <= addr;
data_next <= data;
cmd_next <= cmd;
-- always reset mem signal to SRAM_Controller
mem_next <= '0';
IF nWR_sync = '0' THEN
CASE A_sync IS
WHEN "00" => -- write register 0: currently unused
-- do nothing
WHEN "01" => -- write register 1: command register
CASE D_sync IS
WHEN cmd_write_address =>
-- save value last written to data into address
addr_next(15 DOWNTO 0) <= data;
WHEN cmd_write_data =>
-- address has been latched into addr previously
rw_next <= '0'; -- rw = 0: write
mem_next <= '1'; -- start SRAM controller cycle
WHEN cmd_read_data =>
-- read address has been latched into addr previously
rw_next <= '1'; -- rw = 1: read
mem_next <= '1'; -- start SRAM controller cycle
WHEN cmd_bank_0 =>
-- select memory bank 0
addr_next(16) <= '0';
WHEN cmd_bank_1 =>
-- select memory bank 1
addr_next(16) <= '1';
WHEN OTHERS =>
-- every other command gets stored in cmd
cmd_next <= D_sync;
END CASE;
WHEN "10" => -- write register 2: L byte of data register
data_next(7 DOWNTO 0) <= D_sync;
WHEN "11" => -- write register 3: H byte of data register
data_next(15 DOWNTO 8) <= D_sync;
WHEN OTHERS =>
-- do nothing
END CASE;
END IF;
END PROCESS;
i_SRAM_Controller : ENTITY work.SRAM_Controller PORT MAP
(
clk => clk,
reset => RESET,
mem => mem,
rw => rw,
addr => addr,
data_f2s => data,
--ready => ready,
data_s2f_r => data_s2f,
ad => SRAM_A,
we_n => SRAM_nWE,
oe_n => SRAM_nOE,
ce_n => SRAM_nCE,
ub_n => SRAM_nBHE,
lb_n => SRAM_nBLE,
dio => SRAM_D);
END Behavioral;
| mit | ffd667867cbf3257ff4ed079cca9c478 | 0.465062 | 4.11524 | false | false | false | false |
alvieboy/xtc-base | sdram_hamster.vhd | 1 | 30,001 | ------------------------------------------------------
-- FSM for a SDRAM controller
--
-- Version 0.1 - Ready to simulate
--
-- Authors: Mike Field ([email protected])
-- Alvaro Lopes ([email protected])
--
-- Feel free to use it however you would like, but
-- just drop us an email to say thanks.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_controller is
generic (
HIGH_BIT: integer := 22;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 12
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : IN STD_LOGIC_VECTOR (3 downto 0);
tag_in : in std_logic_vector(31 downto 0);
tag_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of sdram_controller is
type reg is record
address : std_logic_vector(11 downto 0);
bank : std_logic_vector( 1 downto 0);
init_counter : std_logic_vector(14 downto 0);
rf_counter : integer;
rf_pending : std_logic;
rd_pending : std_logic;
wr_pending : std_logic;
act_row : std_logic_vector(11 downto 0);
data_out_low : std_logic_vector(15 downto 0);
req_addr_q : std_logic_vector(22 downto 2);
req_data_write: std_logic_vector(31 downto 0);
req_mask : std_logic_vector(3 downto 0);
data_out_valid: std_logic;
dq_masks : std_logic_vector(1 downto 0);
tristate : std_logic;
tag_in : std_logic_vector(31 downto 0);
tag_out : std_logic_vector(31 downto 0);
tagq : std_logic_vector(31 downto 0);
tagqq : std_logic_vector(31 downto 0);
data_write : std_logic_vector(15 downto 0);
end record;
signal r : reg;
signal n : reg;
signal rstate : std_logic_vector(8 downto 0);
signal nstate : std_logic_vector(8 downto 0);
--signal data_write : std_logic_vector(15 downto 0);
--signal ndata_write : std_logic_vector(15 downto 0);
-- Vectors for each SDRAM 'command'
--- CS_N, RAS_N, CAS_N, WE_N
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
-- State assignments
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
constant CL: integer range 2 to 3 := 2;
-- DEBUG only
type statetype is (IDLE,RF0,RF1,RF2,RF3,RF4,RF5,
RA0,RA1,RA2,DR0,DR1,WR0,WR1,WR2,WR3,
RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,DRDR0,DRDR1,DRDR2);
signal dbgstate: statetype;
-- END DEBUG only
signal addr_row : std_logic_vector(11 downto 0); -- 12
signal addr_bank: std_logic_vector(1 downto 0); -- 2
signal addr_col : std_logic_vector(7 downto 0); -- 8 = 22 bits.
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
signal captured : std_logic_vector(15 downto 0);
constant tOPD: time := 2.1 ns;
constant tHZ: time := 8 ns;
signal dram_dq_dly : std_logic_vector(15 downto 0);
-- Debug only
signal debug_cmd: std_logic_vector(3 downto 0);
signal not_clock_100_delayed_3ns: std_logic;
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
attribute IOB: string;
signal i_DRAM_CS_N: std_logic;
attribute IOB of i_DRAM_CS_N: signal is "true";
signal i_DRAM_RAS_N: std_logic;
attribute IOB of i_DRAM_RAS_N: signal is "true";
signal i_DRAM_CAS_N: std_logic;
attribute IOB of i_DRAM_CAS_N: signal is "true";
signal i_DRAM_WE_N: std_logic;
attribute IOB of i_DRAM_WE_N: signal is "true";
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
attribute IOB of i_DRAM_ADDR: signal is "true";
signal i_DRAM_BA: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_BA: signal is "true";
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_DQM: signal is "true";
--attribute IOB of r.data_write: signal is "true";
attribute IOB of captured: signal is "true";
signal i_DRAM_CLK: std_logic;
attribute fsm_encoding: string;
attribute fsm_encoding of nstate: signal is "user";
attribute fsm_encoding of rstate: signal is "user";
begin
-- Each of the x16s 16,777,216-bit banks is organized as
-- 4,096 rows by 256 columns by 16 bits.
-- 12 bits rows, 8 bit columns, 2 bit banks, two words. 22 bits + 1
--
-- 22211111111110000000000
-- 21098765432109876543210
-- -----------------------
-- rrrrrrrrrrrrbbcccccccix
--
debug_cmd <= rstate(3 downto 0);
-- Addressing is in 32 bit words - twice that of the DRAM width,
-- so each burst of four access two system words.
--addr_row <= address(23 downto 11);
--addr_bank <= address(10 downto 9);
process(r.req_addr_q)
begin
addr_bank <= --r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
-- (24-2) downto (24-2 - 2 - 13 - 1)
-- 22 downto 6
r.req_addr_q(10 downto 9);
addr_row <= ----r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
--r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
r.req_addr_q(22 downto 11);
--addr_col <= (others => '0');
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
r.req_addr_q(8 downto 2) & "0";
end process;
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
clock: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "ASYNC")
port map (
D0 => '1',
D1 => '0',
Q => i_DRAM_CLK,
C0 => clock_100_delayed_3ns,
C1 => not_clock_100_delayed_3ns,
CE => '1',
R => '0',
S => '0'
);
DRAM_CKE <= '1';
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
i_DRAM_CS_N <= transport rstate(3) after tOPD;
DRAM_CS_N <= i_DRAM_CS_N;
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
DRAM_RAS_N <= i_DRAM_RAS_N;
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
DRAM_CAS_N <= i_DRAM_CAS_N;
i_DRAM_WE_N <= transport rstate(0) after tOPD;
DRAM_WE_N <= i_DRAM_WE_N;
i_DRAM_ADDR <= transport r.address after tOPD;
DRAM_ADDR <= i_DRAM_ADDR;
i_DRAM_BA <= transport r.bank after tOPD;
DRAM_BA <= i_DRAM_BA;
i_DRAM_DQM <= transport r.dq_masks after tOPD;
DRAM_DQM <= i_DRAM_DQM;
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
data_out_valid <= r.data_out_valid;
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else r.data_write;
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
tag_out <= r.tag_out;
process (r, rstate, address, req_read, req_write,
addr_row, addr_bank, addr_col, data_in, captured, tag_in, data_mask)
procedure shifttags is
begin
-- Shift tags.
n.tagq <= r.tag_in;
n.tagqq <=r.tagq;
if CL=2 then
n.tag_out <= r.tagq;
else
n.tag_out <= r.tagqq;
end if;
end procedure;
begin
-- copy the existing values
n <= r;
nstate <= rstate;
if req_read = '1' then
if r.rd_pending='0' and r.wr_pending='0' then
n.rd_pending <= '1';
n.req_addr_q <= address(22 downto 2);
n.req_data_write <= (others => 'X');
n.req_mask <= (others => 'X');
n.tag_in <= tag_in;
end if;
end if;
if req_write = '1' then
if r.wr_pending='0' and r.rd_pending='0' then
n.wr_pending <= '1';
n.req_addr_q <= address(22 downto 2);
n.req_data_write <= data_in;
n.req_mask <= data_mask;
n.tag_in <= tag_in;
end if;
end if;
n.dq_masks <= "11";
-- first off, do we need to perform a refresh cycle ASAP?
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
n.rf_counter <= 0;
n.rf_pending <= '1';
else
-- only start looking for refreshes outside of the initialisation state.
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
n.rf_counter <= r.rf_counter + 1;
end if;
end if;
-- Set the data bus into HIZ, high and low bytes masked
--DRAM_DQ <= (others => 'Z');
n.tristate <= '0';
n.init_counter <= r.init_counter-1;
--ndata_write <= (others => DontCareValue);
n.data_out_valid <= '0'; -- alvie- here, no ?
-- Process the FSM
case rstate(8 downto 4) is
when s_init_nop_id => --s_init_nop(8 downto 4) =>
nstate <= s_init_nop;
dbgstate<= IDLE;
n.address <= (others => 'X');
n.bank <= (others => '0');
--n.act_ba <= (others => '0');
n.rf_counter <= 0;
-- n.data_out_valid <= '1'; -- alvie- not here
-- T-130, precharge all banks.
if r.init_counter = "000000010000010" then
nstate <= s_init_pre;
n.address(10) <= '1';
end if;
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
nstate <= s_init_ref;
end if;
-- T-3, the load mode register
if r.init_counter = 3 then
nstate <= s_init_mrs;
-- Mode register is as follows:
-- resvd wr_b OpMd CAS=2 Seq bust=1
n.address <= "00" & "0" & "00" & "010" & "0" & "000";
-- resvd
n.bank <= "00";
end if;
-- T-1 The switch to the FSM (first command will be a NOP
if r.init_counter = 1 then
nstate <= s_idle;
end if;
------------------------------
-- The Idle section
------------------------------
when s_idle_id =>
nstate <= s_idle;
dbgstate<= IDLE;
-- do we have to activate a row?
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
end if;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
-- refreshes take priority over everything
if r.rf_pending = '1' then
nstate <= s_rf0;
end if;
n.rf_pending <= '0';
------------------------------
-- Row activation
-- s_ra2 is also the "idle with active row" state and provides
-- a resting point between operations on the same row
------------------------------
when s_ra0_id =>
nstate <= s_ra1;
dbgstate<= RA0;
when s_ra1_id =>
dbgstate<= RA1;
nstate <= s_ra2;
when s_ra2_id=>
dbgstate<= RA2;
-- we can stay in this state until we have something to do
nstate <= s_ra2;
n.tristate<='0';
n.address <= (others => 'X');
if r.rf_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
else
-- If there is a read pending, deactivate the row
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
end if;
-- unless we have a read to perform on the same row? do that instead
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_rd0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
--n.act_ba <= addr_bank;
n.dq_masks <= "00";
n.rd_pending <= '0';
n.data_write <= (others => 'X');
-- Shift tags.
shifttags;
end if;
-- unless we have a write on the same row? writes take priroty over reads
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_wr0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.data_write <= r.req_data_write(31 downto 16);
n.bank <= addr_bank;
--n.act_ba <= addr_bank;
n.dq_masks<= not r.req_mask(3 downto 2);
n.wr_pending <= '0';
-- Shift tags.
shifttags;
end if;
end if;
-- nstate <= s_dr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending;
-- n.wr_pending <= r.wr_pending;
--n.tristate <= '0';
--end if;
------------------------------------------------------
-- Deactivate the current row and return to idle state
------------------------------------------------------
when s_dr0_id =>
dbgstate<= DR0;
n.address <= (others => 'X');
nstate <= s_dr1;
when s_dr1_id =>
dbgstate<= DR1;
n.address <= (others => 'X');
nstate <= s_idle;
------------------------------
-- The Refresh section
------------------------------
when s_rf0_id =>
dbgstate<= RF0;
n.address <= (others => 'X');
nstate <= s_rf1;
when s_rf1_id =>
dbgstate<= RF1;
n.address <= (others => 'X');
nstate <= s_rf2;
when s_rf2_id =>
dbgstate<= RF2;
n.address <= (others => 'X');
nstate <= s_rf3;
when s_rf3_id =>
nstate <= s_rf4;
n.address <= (others => 'X');
dbgstate<= RF3;
when s_rf4_id =>
nstate <= s_rf5;
n.address <= (others => 'X');
dbgstate<= RF4;
when s_rf5_id =>
nstate <= s_idle;
dbgstate<= RF5;
n.address <= (others => 'X');
------------------------------
-- The Write section
------------------------------
when s_wr0_id =>
nstate <= s_wr3;
n.bank <= addr_bank;
n.address(0) <= '1';
n.data_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
--DRAM_DQ <= rdata_write;
n.dq_masks <= not r.req_mask(1 downto 0);
n.tristate <= '0';
shifttags;
dbgstate<= WR0;
when s_wr1_id => null;
dbgstate<= WR1;
when s_wr2_id =>
dbgstate<= WR2;
nstate <= s_dr0;
n.address(10) <= '1';
when s_wr3_id =>
dbgstate<= WR3;
-- Default to the idle+row active state
nstate <= s_ra2;
--DRAM_DQ <= rdata_write;
n.data_out_valid<='1'; -- alvie- ack write
shifttags;
--n.tag_out <= r.tagq;
n.tristate <= '0';
n.dq_masks<= "11";
-- If there is a read or write then deactivate the row
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_wr2;
--n.address(10) <= '1';
end if;
n.address <= (others => 'X');
-- But if there is a read pending in the same row, do that
if r.rd_pending = '1' and r.act_row = addr_row and r.bank = addr_bank then
nstate <= s_rd0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.dq_masks <= "00";
n.rd_pending <= '0';
end if;
-- unless there is a write pending in the same row, do that
if r.wr_pending = '1' and r.act_row = addr_row and r.bank = addr_bank then
nstate <= s_wr0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.data_write <= r.req_data_write(31 downto 16);
n.dq_masks<= not r.req_mask(3 downto 2);
n.wr_pending <= '0';
end if;
shifttags;
-- But always try and refresh if one is pending!
if r.rf_pending = '1' then
nstate <= s_wr2; --dr0;
n.wr_pending <= r.wr_pending;
n.rd_pending <= r.rd_pending;
--n.address(10) <= '1';
end if;
------------------------------
-- The Read section
------------------------------
when s_rd0_id => -- 10001
dbgstate<= RD0;
nstate <= s_rd1;
n.tristate<='1';
n.dq_masks <= "00";
n.address(0)<='1';
when s_rd1_id => -- 10010
dbgstate<= RD1;
if CL=3 then
nstate <= s_rd2;
else
nstate <= s_rd6;
end if;
n.dq_masks <= "00";
n.tristate<='1';
n.address <= (others => 'X');
if r.rd_pending = '1' and r.act_row = addr_row and r.bank=addr_bank then
nstate <= s_rd3; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
n.data_write <= (others => 'X');
--n.tagq <= r.tag_in;
--n.tagqq<=r.tagq;
--n.tag_out <= r.tag_in;
end if;
-- Shift tags.
shifttags;
-- Update output tag immediatly
--n.tag_out <= r.tagq;
when s_rd2_id => -- 10011
dbgstate<= RD2;
nstate <= s_rd7;
n.dq_masks <= "00";
n.tristate<='1';
when s_rd3_id => -- 10100
dbgstate<= RD3;
nstate <= s_rd4;
n.dq_masks <= "00";
n.address(0) <= '1';
n.tristate<='1';
if CL=2 then
n.data_out_low <= captured;
n.data_out_valid <= '1';
end if;
-- Data is still not ready...
when s_rd4_id => -- 10101
dbgstate<= RD4;
nstate <= s_rd5;
n.dq_masks <= "00";
n.tristate<='1';
n.address <= (others => 'X');
if r.rd_pending = '1' and r.act_row = addr_row and r.bank=addr_bank then
nstate <= s_rd5; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
n.data_write <= (others => 'X');
--n.tagq <= r.tag_in;
--n.tagqq<=r.tagq;
--n.tag_out <= r.tag_in;
else
if CL=3 then
nstate <= s_rd6; -- NOTE: not correct
else
nstate <= s_rd6;
end if;
end if;
-- Shift tags.
shifttags;
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending; -- Keep request
--end if;
if CL=3 then
n.data_out_low <= captured;
n.data_out_valid <= '1';
end if;
--n.tag_out <= r.tagqq;
when s_rd5_id =>
dbgstate<=RD5;
-- If a refresh is pending then always deactivate the row
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
--end if;
n.address(0) <= '1';
nstate <= s_rd4; -- Another request came, and we can pipeline -
n.dq_masks <= "00";
n.tristate<='1';
if CL=2 then
n.data_out_low <= captured;
n.data_out_valid <= '1';
end if;
when s_rd6_id =>
dbgstate<= RD6;
nstate <= s_rd7;
n.dq_masks<= "00";
n.tristate<='1';
n.address <= (others => 'X');
if CL=2 then
n.data_out_low <= captured;
n.data_out_valid <= '1';
nstate <= s_ra2;
--shifttags;
end if;
when s_rd7_id =>
dbgstate<= RD7;
nstate <= s_ra2;
if CL=3 then
n.data_out_low <= captured;
n.data_out_valid <= '1';
end if;
n.address <= (others => 'X');
shifttags;
--n.tag_out <= r.tagq;
--n.tag_out <= r.tag_in;
n.tristate<='1';
when s_rd8_id => dbgstate<=RD8;
when s_rd9_id => dbgstate<= RD9;
-- The Deactivate row during read section
------------------------------
when s_drdr0_id =>
dbgstate<= DRDR0;
n.address <= (others => 'X');
nstate <= s_drdr1;
when s_drdr1_id =>
dbgstate<= DRDR1;
n.address <= (others => 'X');
nstate <= s_drdr2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
shifttags;
--n.tag_out <= r.tag_in;
when s_drdr2_id =>
dbgstate<= DRDR2;
nstate <= s_idle;
if r.rf_pending = '1' then
nstate <= s_rf0;
end if;
n.address <= (others => 'X');
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
when others =>
nstate <= s_init_nop;
end case;
end process;
--- The clock driven logic
process (clock_100, n)
begin
if clock_100'event and clock_100 = '1' then
if rst='1' then
rstate <= (others => '0');
r.address <= (others => '0');
r.bank <= (others => '0');
r.init_counter <= "100000000000000";
-- synopsys translate_off
r.init_counter <= "000000100000000";
-- synopsys translate_on
r.rf_counter <= 0;
r.rf_pending <= '0';
r.rd_pending <= '0';
r.wr_pending <= '0';
r.act_row <= (others => '0');
r.data_out_low <= (others => '0');
r.data_out_valid <= '0';
r.dq_masks <= "11";
r.tristate<='1';
r.tag_in <= (others =>'0');
r.tag_out <= (others =>'0');
else
r <= n;
rstate <= nstate;
--rdata_write <= ndata_write;
end if;
end if;
end process;
dram_dq_dly <= transport dram_dq after 1.9 ns;
-- process (clock_100_delayed_3ns, dram_dq_dly)
-- begin
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
-- captured <= dram_dq_dly;
-- end if;
-- end process;
process (clock_100)
begin
if falling_edge(clock_100) then
captured <= dram_dq_dly;
end if;
end process;
end rtl;
| bsd-3-clause | b3813468fbab0d0441423ca3a156ed04 | 0.484984 | 3.387647 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/MicrocodeProcessor.vhd | 1 | 10,620 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 21:58:16 09/22/2011
-- Design Name:
-- Module Name: MicrocodeProcessor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MicrocodeProcessor is
Port (
CLK: in STD_LOGIC;
EN: in STD_LOGIC;
microcode: out std_logic_vector(3 downto 0);
DataBus : inout STD_LOGIC_VECTOR (11 downto 0);
AddrBus : out STD_LOGIC_VECTOR (11 downto 0);
Control : out STD_LOGIC_VECTOR (11 downto 0)
);
end MicrocodeProcessor;
architecture Behavioral of MicrocodeProcessor is
signal ProgramCounter: std_logic_vector(11 downto 0);
signal Instruction: std_logic_vector(11 downto 0);
signal Flags: std_logic_vector(11 downto 0);
signal microcodePC: std_logic_vector(3 downto 0) := "1111";
signal pOut: std_logic_vector(3 downto 0) := "0000";
signal output: std_logic_vector(6 downto 0);
-- alias AAA is Instruction(5 downto 3);
-- alias BBB is Instruction(2 downto 0);
-- alias PPP is Instruction(8 downto 6);
-- alias PPPP is Instruction(9 downto 6);
-- alias RR is Instruction(9 downto 8);
-- alias QQ is Instruction(7 downto 6);
-- alias KKKK is Instruction(6 downto 3);
-- alias MajOp is Instruction(11 downto 10);
-- alias LoadType is Instruction(9 downto 8);
-- alias SubOp is Instruction(9 downto 7);
-- alias MathCmp is Instruction(9);
-- alias iMathCmp is Instruction(6);
alias AAA is Instruction(8 downto 7);
alias BBB is Instruction(11 downto 9);
alias PPP is Instruction(6 downto 4);
alias PPPP is Instruction(6 downto 3);
alias RR is Instruction(4 downto 3);
alias QQ is Instruction(6 downto 5);
alias KKKK is Instruction(8 downto 5);
alias MajOp is Instruction(1 downto 0);
-- alias LoadType is Instruction(9 downto 8);
alias SubOp is Instruction(4 downto 2);
alias MathCmp is Instruction(2);
alias iMathCmp is Instruction(6);
constant WriteAtoR: std_logic_vector(6 downto 0):= "0100001";
constant WriteBtoR: std_logic_vector(6 downto 0):= "0101000";
constant WriteRtoA: std_logic_vector(6 downto 0):= "0010010";
constant WriteRtoB: std_logic_vector(6 downto 0):= "0011000";
constant WriteR: std_logic_vector(6 downto 0):= "0100000";
constant ReadR: std_logic_vector(6 downto 0):= "0010000";
constant ExeIntoR: std_logic_vector(6 downto 0):= "1100000";
--Microcode structure:
--6. Execute
--5. Write to RAM
--4. Enable RAM
--3. Write to Register B
--2. Enable Register B
--1. Write to Register A
--0. Enable Register A
begin
Control(0) <= output(4);
Control(1) <= output(5);
Control(2) <= output(1);
Control(3) <= output(3);
Control(5) <= output(6);
Control(11 downto 8) <= pOut;
process (CLK,EN, microcodePC, output, Instruction, Flags, ProgramCounter, DataBus, pOut)
begin
if(EN = '1') then
if(CLK = '1') then
microcode <= microcodePC;
microcodePC <= microcodePC + "0001";
if(microcodePC = "0000") then --Load RAM Program Counter
AddrBus <= "000000000000";
output <= ReadR;
ProgramCounter <= DataBus;
elsif(microcodePC = "0001") then --Load Flags
AddrBus <= "000000000001";
output <= ReadR;
Flags <= DataBus;
elsif(microcodePC = "0010") then --Load Assembly Instruction
AddrBus <= ProgramCounter;
output <= ReadR;
Instruction <= DataBus;
elsif(microcodePC = "0111") then --Inc PC
AddrBus <= "000000000000";
DataBus <= ProgramCounter + 1;
output <= "0100000";
else
--Math Opcode-------------------------------------------------------------------------------------------------------
if(MajOp = "00") then
if(microcodePC = "0011") then --Load MA->A
if(MathCmp = '0') then --Check If Execute on Compare
pOut(2 downto 0) <= PPP;
AddrBus(2 downto 0) <= AAA;
output <= WriteRtoA;
else --Check Compare Flag
if (Flags(0) = '1') then --Compare bit set
pOut(2 downto 0) <= PPP;
AddrBus(2 downto 0) <= AAA;
output <= WriteRtoA;
else
microcode <= "0111";
end if;
end if;
elsif(microcodePC = "0100") then --Load MB->B
AddrBus(2 downto 0) <= BBB;
output <= WriteRtoB;
elsif(microcodePC = "0101") then
pOut(2 downto 0) <= PPP;
AddrBus(2 downto 0) <= BBB;
output <= ExeIntoR; --Execute into MB
end if;
--Logic Opcode------------------------------------------------------------------------------------------------------
elsif (MajOp = "10") then --Logic Opcode
if(microcodePC = "0011") then --Load MA->A
AddrBus(2 downto 0) <= AAA;
output <= WriteRtoA;
elsif(microcodePC = "0100") then --Load MB->B
pOut(2 downto 0) <= PPP;
AddrBus(2 downto 0) <= BBB;
output <= WriteRtoB;
elsif(microcodePC = "0101") then --Execute into R
pOut(3 downto 0) <= PPPP;
AddrBus(2 downto 0) <= BBB;
output <= ExeIntoR;
end if;
--Load Opcode-------------------------------------------------------------------------------------------------------
elsif (MajOp = "01") then --Load Opcode
if(microcodePC = "0011") then --Load MA->A
if(RR = "00") then --Direct Access
AddrBus(2 downto 0) <= AAA;
output <= WriteRtoA;
-- microcodePC <= "0100"; --Jump past Indirect access microcode
elsif(RR = "01") then --Indirect access
AddrBus(2 downto 0) <= AAA;
output <= ReadR;
Flags <= DataBus; -- Dont need flags for this option
elsif(RR = "10") then
AddrBus(2 downto 0) <= AAA;
output <= ReadR;
Flags <= DataBus; -- Dont need flags for this option
elsif(RR = "11") then
AddrBus(2 downto 0) <= AAA;
output <= ReadR;
Flags <= DataBus - 1; -- Dont need flags for this option
end if;
elsif(microcodePC = "0100") then --Restore inc/dec pointer
AddrBus(2 downto 0) <= AAA;
if(RR = "10") then
output <=WriteR;
DataBus <= Flags + 1;
elsif(RR = "11") then
output <=WriteR;
DataBus <= Flags + 1;
end if;
elsif(microcodePC = "0101") then --Indirect access A
if(RR /= "00") then --Indirect access
AddrBus <= Flags;
output <= WriteRtoA; --Fetch Memory into A
end if;
elsif(microcodePC = "0110") then --Load MB->B
if(QQ = "00") then --Direct Access B
AddrBus(2 downto 0) <= BBB;
output <= WriteRtoB;
--microcodePC <= "0110"; --Jump past indirect
elsif(QQ = "01") then --Indirect access
AddrBus(2 downto 0) <= BBB;
output <= ReadR;
Flags <= DataBus; -- Dont need flags for this option
elsif(QQ = "10") then --Indirect access
AddrBus(2 downto 0) <= BBB;
output <= ReadR;
Flags <= DataBus; -- Dont need flags for this option
elsif(QQ = "11") then --Indirect access
AddrBus(2 downto 0) <= BBB;
output <= ReadR;
Flags <= DataBus -1; -- Dont need flags for this option
end if;
elsif(microcodePC = "0111") then --Restore inc/dec pointer
AddrBus(2 downto 0) <= BBB;
if(RR = "10") then
output <=WriteR;
DataBus <= Flags + 1;
elsif(RR = "11") then
output <=WriteR;
DataBus <= Flags + 1;
end if;
elsif(microcodePC = "1000") then --Indirect write into B
if(QQ /= "00") then --Indirect access
AddrBus <= Flags;
output <= WriteAtoR;
end if;
end if;
--Set/Right/Immediate Math Opcode----------------------------------------------------------------------------------
elsif (MajOp = "11") then --Set/Right/Immediate Math
if(SubOp = "100") then --Set subopcode
if(microcodePC = "0011") then --Load MA->A
AddrBus(2 downto 0) <= AAA;
output <= ReadR;
Flags <= DataBus; --Not needed yet
elsif(microcodePC = "0100") then
AddrBus(2 downto 0) <= BBB;
output <= ReadR;
if(Flags = DataBus) then
AddrBus(3 downto 0) <= "0001";
output <= WriteR;
DataBus <= "000000000001";
else
AddrBus(3 downto 0) <= "0001";
output <= WriteR;
DataBus <= "000000000000";
end if;
end if;
elsif(SubOp = "010") then --Rotate Right subopcode
if(microcodePC = "0011") then --Load *B->f
AddrBus(2 downto 0) <= BBB;
output <= ReadR;
Flags <= DataBus;
elsif(microcodePC = "0100") then
AddrBus(2 downto 0) <= BBB;
output <= WriteR;
--DataBus <= Flags ror 6;--(conv_integer(KKKK));
end if;
elsif(SubOp = "110") then --Immediate math
if(microcodePC = "0011") then --Load MA->A
if(iMathCmp = '0') then --Check If Execute on Compare
pOut(2 downto 0) <= AAA;
AddrBus(2 downto 0) <= BBB;
output <= WriteRtoB;
else --Check Compare Flag
if (Flags(0) = '1') then --Compare bit set
pOut(2 downto 0) <= AAA;
AddrBus(2 downto 0) <= BBB;
output <= WriteRtoB;
else
microcode <= "0111";
end if;
end if;
elsif(microcodePC = "0100") then --Execute into MB
pOut(2 downto 0) <= AAA;
AddrBus(2 downto 0) <= BBB;
output <= ExeIntoR;
end if;
end if;
end if;
end if;
elsif(CLK='0') then
end if;
else
output <= "ZZZZZZZ";
AddrBus <= "ZZZZZZZZZZZZ";
DataBus <= "ZZZZZZZZZZZZ";
pOut <= "ZZZZ";
Control <= "ZZZZZZZZZZZZ";
microcodePC <= "0000";
end if;
end process;
end Behavioral;
| bsd-3-clause | a5189be2ea0e605d30c63ca81e205e9f | 0.538136 | 3.59878 | false | false | false | false |
keith-epidev/md2x | build/code/seven_segment.vhdl | 1 | 1,891 | library ieee;
use ieee.std_logic_1164.all;
entity seven_segment is
port (
clk : in std_logic;
val : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
mode: in std_logic
);
end seven_segment;
architecture arch of seven_segment is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
signal spinner : std_logic_vector(5 downto 0) := "111110";
signal spin_spinner: std_logic;
begin
p1: pulser generic map(delay=>5000000) port map(clk,'1',spin_spinner);
spinner_pro: process(spin_spinner)
begin
if(spin_spinner'event and spin_spinner = '1')then
if(spinner = "011111")then
spinner <= "111110";
else
spinner <= spinner(4 downto 0) & '1';
end if;
end if;
end process spinner_pro;
disp_pro: process(clk,val,mode)
begin
if(mode = '0') then
case val is
when "0001" => led <= "1111001";
when "0010" => led <= "0100100";
when "0011" => led <= "0110000";
when "0100" => led <= "0011001";
when "0101" => led <= "0010010";
when "0110" => led <= "0000010";
when "0111" => led <= "1111000";
when "1000" => led <= "0000000";
when "1001" => led <= "0010000";
when "1010" => led <= "0001000";
when "1011" => led <= "0000011";
when "1100" => led <= "1000110";
when "1101" => led <= "0100001";
when "1110" => led <= "0000110";
when "1111" => led <= "0001110";
when others => led <= "1000000";
end case;
else
if( val = "0001") then
led <= "1000111";
else if ( val = "0010") then
led <= "0010010";
else if ( val = "0011") then
led <= '1'&spinner;
else
led <= "1111111";
end if;
end if;
end if;
end if;
end process disp_pro;
end arch;
| gpl-2.0 | 43a7fa3fba0fdcc234fa372bb0e49d3d | 0.559492 | 2.97327 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_stack.vhd | 1 | 4,724 | -------------------------------------------------------------------------------
--
-- The stack unit.
--
-- $Id: t400_stack.vhd,v 1.3 2006-06-11 02:12:11 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_stack is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Stack Control Interface ------------------------------------------------
op_i : in stack_op_t;
-- Program Counter Interface ----------------------------------------------
pc_i : in pc_t;
pc_o : out pc_t
);
end t400_stack;
-- pragma translate_off
use work.tb_pack.tb_sa_s;
-- pragma translate_on
architecture rtl of t400_stack is
signal sa_q,
sb_q,
sc_q : pc_t;
begin
-----------------------------------------------------------------------------
-- Process stack
--
-- Purpose:
-- Implements the stack consisting of SA, SB, SC.
-- SC is skipped when it's a 41xL.
--
stack: process (ck_i, por_i)
variable t41x_type_v : boolean;
begin
if por_i then
sa_q <= (others => '0');
sb_q <= (others => '0');
sc_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
if ck_en_i then
case op_i is
when STACK_PUSH =>
sa_q <= pc_i;
sb_q <= sa_q;
if not t41x_type_v then
sc_q <= sb_q;
else
sc_q <= (others => '0');
end if;
when STACK_POP =>
sa_q <= sb_q;
if not t41x_type_v then
sb_q <= sc_q;
end if;
when others =>
null;
end case;
end if;
end if;
end process stack;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- instrument interrupt testbench
tb_sa_s <= sa_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pc_o <= sa_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/27 19:15:59 arniml
-- instrument testbench
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 64e0a0ca42a8533d79cad5bba5f81c9d | 0.531329 | 4.236771 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyii_atoms.vhd | 1 | 674,573 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package hardcopyii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE hardcopyii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end hardcopyii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hardcopyii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end hardcopyii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package hardcopyii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end hardcopyii_pllpack;
package body hardcopyii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end hardcopyii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyii_dffe : entity is TRUE;
end hardcopyii_dffe;
-- architecture body --
architecture behave of hardcopyii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- hardcopyii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of hardcopyii_mux21 : entity is TRUE;
end hardcopyii_mux21;
architecture AltVITAL of hardcopyii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_mux41 : entity is TRUE;
end hardcopyii_mux41;
architecture AltVITAL of hardcopyii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyii_atom_pack.all;
-- entity declaration --
entity hardcopyii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyii_and1 : entity is TRUE;
end hardcopyii_and1;
-- architecture body --
architecture AltVITAL of hardcopyii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : hardcopyii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END hardcopyii_ram_register;
ARCHITECTURE reg_arch OF hardcopyii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : hardcopyii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF hardcopyii_ram_pulse_generator:ENTITY IS TRUE;
END hardcopyii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF hardcopyii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE work.hardcopyii_ram_register;
USE work.hardcopyii_ram_pulse_generator;
ENTITY hardcopyii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END hardcopyii_ram_block;
ARCHITECTURE block_arch OF hardcopyii_ram_block IS
COMPONENT hardcopyii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
SIGNAL m4k_write_error_port_a : STD_LOGIC := '0';
SIGNAL m4k_write_error_port_b : STD_LOGIC := '0';
SIGNAL m4k_write_a_not_ok : BOOLEAN := TRUE;
SIGNAL m4k_write_b_not_ok : BOOLEAN := TRUE;
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : hardcopyii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : hardcopyii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
m4k_write_error_port_a <= '1' WHEN ((port_b_read_enable_write_enable_clock = "clock1") AND (ram_type = FALSE) AND m4k_write_a_not_ok) ELSE '0';
m4k_write_error_port_b <= '1' WHEN ((port_b_read_enable_write_enable_clock = "clock1") AND (ram_type = FALSE) AND m4k_write_b_not_ok) ELSE '0';
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : hardcopyii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : hardcopyii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : hardcopyii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : hardcopyii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : hardcopyii_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : hardcopyii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : hardcopyii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : hardcopyii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1') AND (m4k_write_error_port_b = '0')) ELSE '0';
wpgen_a : hardcopyii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1') AND (m4k_write_error_port_a = '0')) ELSE '0';
wpgen_b : hardcopyii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : hardcopyii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : hardcopyii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : hardcopyii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : hardcopyii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
m4k_write_a : PROCESS(clk_a_in)
BEGIN
IF (clk_a_in'EVENT AND clk_a_in = '0') THEN
m4k_write_a_not_ok <= FALSE;
END IF;
END PROCESS m4k_write_a;
m4k_write_b : PROCESS(clk_b_in)
BEGIN
IF (clk_b_in'EVENT AND clk_b_in = '0') THEN
m4k_write_b_not_ok <= FALSE;
END IF;
END PROCESS m4k_write_b;
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : hardcopyii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : hardcopyii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyii_routing_wire
--
-- Description : FusionII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_routing_wire : entity is TRUE;
end hardcopyii_routing_wire;
ARCHITECTURE behave of hardcopyii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
-------------------------------------------------------------------
--
-- Entity Name : hardcopyii_jtag
--
-- Description : HardCopy II JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_jtag is
generic (
lpm_type : string := "hardcopyii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end hardcopyii_jtag;
architecture architecture_jtag of hardcopyii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : hardcopyii_crcblock
--
-- Description : HardCopy II CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "hardcopyii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end hardcopyii_crcblock;
architecture architecture_crcblock of hardcopyii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyii_lcell_ff
--
-- Description : HardCopy II LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_and1;
entity hardcopyii_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "hardcopyii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_lcell_ff : entity is TRUE;
end hardcopyii_lcell_ff;
architecture vital_lcell_ff of hardcopyii_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal adatasdata_ipd : std_logic;
signal adatasdata_dly : std_logic;
signal adatasdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component hardcopyii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: hardcopyii_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
adatasdatadelaybuffer: hardcopyii_and1
port map(IN1 => adatasdata_ipd,
Y => adatasdata_dly);
adatasdatadelaybuffer1: hardcopyii_and1
port map(IN1 => adatasdata_dly,
Y => adatasdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (adatasdata_ipd, adatasdata, tipd_adatasdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, adatasdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_adatasdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_adatasdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(aload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_adatasdata_clk,
TimingData => TimingData_adatasdata_clk,
TestSignal => adatasdata_ipd,
TestSignalName => "ADATASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_adatasdata_clk_noedge_posedge,
SetupLow => tsetup_adatasdata_clk_noedge_posedge,
HoldHigh => thold_adatasdata_clk_noedge_posedge,
HoldLow => thold_adatasdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_adatasdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (aload_ipd = '1') then
iregout := adatasdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := adatasdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (adatasdata_ipd'last_event, tpd_adatasdata_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyii_lcell_comb
--
-- Description : HardCopy II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "hardcopyii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_lcell_comb : entity is TRUE;
end hardcopyii_lcell_comb;
architecture vital_lcell_comb of hardcopyii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_ena_reg : entity is TRUE;
end hardcopyii_ena_reg;
ARCHITECTURE behave of hardcopyii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/ENA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for HardCopy II CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- HARDCOPYII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_ena_reg;
entity hardcopyii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_clkctrl : entity is TRUE;
end hardcopyii_clkctrl;
architecture vital_clkctrl of hardcopyii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component hardcopyii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : hardcopyii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
outclk <= cereg_out AND clkmux_out;
end vital_clkctrl;
--
--
-- HARDCOPYII_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
dqs_input_frequency : STRING := "10000 ps";
dqs_out_mode : STRING := "none";
dqs_delay_buffer_mode : STRING := "low";
dqs_phase_shift : INTEGER := 0;
dqs_offsetctrl_enable : STRING := "false";
dqs_ctrl_latches_enable : STRING := "false";
dqs_edge_detect_enable : STRING := "false";
gated_dqs : STRING := "false";
sim_dqs_intrinsic_delay : INTEGER := 0;
sim_dqs_delay_increment : INTEGER := 0;
sim_dqs_offset_increment : INTEGER := 0;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_regin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_dqsupdateen : VitalDelayType01 := DefPropDelay01;
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01));
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of hardcopyii_asynch_io : entity is TRUE;
end hardcopyii_asynch_io;
architecture behave of hardcopyii_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_in : std_logic_vector(5 downto 0);
signal offsetctrlin_in : std_logic_vector(5 downto 0);
signal dqsupdateen_in : std_logic;
signal dqs_delay_int : integer := 0;
signal tmp_dqsbusout : std_logic;
signal dqs_ctrl_latches_ena : std_logic := '1';
signal combout_tmp_sig : std_logic := '0';
signal dqsbusout_tmp_sig : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_in(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (delayctrlin_in(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_in(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_in(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_in(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_in(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
VitalWireDelay (offsetctrlin_in(5), offsetctrlin(5), tipd_offsetctrlin(5));
VitalWireDelay (offsetctrlin_in(4), offsetctrlin(4), tipd_offsetctrlin(4));
VitalWireDelay (offsetctrlin_in(3), offsetctrlin(3), tipd_offsetctrlin(3));
VitalWireDelay (offsetctrlin_in(2), offsetctrlin(2), tipd_offsetctrlin(2));
VitalWireDelay (offsetctrlin_in(1), offsetctrlin(1), tipd_offsetctrlin(1));
VitalWireDelay (offsetctrlin_in(0), offsetctrlin(0), tipd_offsetctrlin(0));
end block;
dqs_ctrl_latches_ena <= '1' when dqs_ctrl_latches_enable = "false" ELSE
dqsupdateen_in when dqs_edge_detect_enable = "false" ELSE
(not (combout_tmp_sig xor tmp_dqsbusout) and dqsupdateen_in);
process(delayctrlin_in, offsetctrlin_in, dqs_ctrl_latches_ena)
variable tmp_delayctrl : integer := 0;
variable tmp_offsetctrl : integer := 0;
begin
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
tmp_delayctrl := 31;
else
tmp_delayctrl := alt_conv_integer(delayctrlin_in);
end if;
if (dqs_offsetctrl_enable = "true") then
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
tmp_offsetctrl := 31;
else
tmp_offsetctrl := alt_conv_integer(offsetctrlin_in);
end if;
else
tmp_offsetctrl := 0;
end if;
if (dqs_ctrl_latches_ena = '1') THEN
dqs_delay_int <= sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
end if;
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
assert false report "OFFSETCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
end process;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, tmp_dqsbusout)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable dqsbusout_tmp : std_logic;
variable combout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
tmp_dqsbusout <= transport tmp_combout after (dqs_delay_int * 1 ps);
if (gated_dqs = "true") then
dqsbusout_tmp := tmp_dqsbusout AND regin;
else
dqsbusout_tmp := tmp_dqsbusout;
end if;
-- for dqs delay ctrl latches enable
dqsbusout_tmp_sig <= dqsbusout_tmp;
combout_tmp_sig <= tmp_combout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => dqsbusout_tmp,
Paths => (1 => (tmp_dqsbusout'last_event, tpd_padio_dqsbusout, TRUE),
2 => (regin'last_event, tpd_regin_dqsbusout, gated_dqs = "true")),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- HARDCOPYII_IO_REGISTER
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_io_register is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_io_register : entity is TRUE;
end hardcopyii_io_register;
architecture vital_io_reg of hardcopyii_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--
-- HARDCOPYII_IO_LATCH
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_io_latch is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_io_latch : entity is TRUE;
end hardcopyii_io_latch;
architecture vital_io_latch of hardcopyii_io_latch is
attribute VITAL_LEVEL0 of vital_io_latch : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd = '1') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_latch;
--
-- HARDCOPYII_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_asynch_io;
use work.hardcopyii_io_register;
use work.hardcopyii_io_latch;
use work.hardcopyii_mux21;
use work.hardcopyii_and1;
entity hardcopyii_io is
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "hardcopyii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end hardcopyii_io;
architecture structure of hardcopyii_io is
component hardcopyii_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component hardcopyii_io_register
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component hardcopyii_io_latch
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component hardcopyii_mux21
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component hardcopyii_and1
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
begin
not_inclk <= (ddioinclk) WHEN (ddioinclk_input = "dqsb_bus") ELSE (not inclk);
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : hardcopyii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map ( regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio0_reg
in_ddio0_reg : hardcopyii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map (regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio1_latch
in_ddio1_reg : hardcopyii_io_latch
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => "none", -- this register does not have sync_reset
POWER_UP => input_power_up)
port map (regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn);
-- out_reg
out_reg : hardcopyii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- out ddio reg
out_ddio_reg : hardcopyii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe reg
oe_reg : hardcopyii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe_pulse reg
oe_pulse_reg : hardcopyii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : hardcopyii_and1
port map (Y => outclk_delayed,
IN1 => outclk);
ddio_data_mux : hardcopyii_mux21
port map (MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : hardcopyii_asynch_io
generic map ( OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
dqs_input_frequency => dqs_input_frequency,
dqs_out_mode => dqs_out_mode,
dqs_delay_buffer_mode => dqs_delay_buffer_mode,
dqs_phase_shift => dqs_phase_shift,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
dqs_edge_detect_enable => dqs_edge_detect_enable,
gated_dqs => gated_dqs,
sim_dqs_intrinsic_delay => sim_dqs_intrinsic_delay,
sim_dqs_delay_increment => sim_dqs_delay_increment,
sim_dqs_offset_increment => sim_dqs_offset_increment)
port map( datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
padio => padio,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
dqsbusout => dqsbusout,
combout => combout,
regout => regout,
ddioregout => ddioregout);
end structure;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_m_cntr
--
-- Description : Timing simulation model for the M counter. M is the loop
-- feedback counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyii_m_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END hardcopyii_m_cntr;
ARCHITECTURE behave of hardcopyii_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_n_cntr
--
-- Description : Timing simulation model for the N counter. N is the
-- input counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyii_n_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END hardcopyii_n_cntr;
ARCHITECTURE behave of hardcopyii_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END hardcopyii_scale_cntr;
ARCHITECTURE behave of hardcopyii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY hardcopyii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end hardcopyii_pll_reg;
ARCHITECTURE behave of hardcopyii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.hardcopyii_atom_pack.all;
USE work.hardcopyii_pllpack.all;
USE work.hardcopyii_m_cntr;
USE work.hardcopyii_n_cntr;
USE work.hardcopyii_scale_cntr;
USE work.hardcopyii_dffe;
USE work.hardcopyii_pll_reg;
ENTITY hardcopyii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyii_pll";
-- Simulation only generics
family_name : string := "StratixII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
-- lvds specific ports
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END hardcopyii_pll;
ARCHITECTURE vital_pll of hardcopyii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT GATE_LOCK_CYCLES : integer := 7;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_out_last_value : std_logic_vector(7 downto 0);
signal vco_tap_last_value : std_logic_vector(7 downto 0);
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
--signal tap0_is_active : boolean := true;
signal sig_quiet_time : time := 0 ps;
signal sig_slowest_clk_old : time := 0 ps;
signal sig_slowest_clk_new : time := 0 ps;
signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
COMPONENT hardcopyii_m_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyii_n_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT hardcopyii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanread_ipd, scanread, tipd_scanread);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (scanwrite_ipd, scanwrite, tipd_scanwrite);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
inclk_m <= clkin when m_test_source = 0 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or
c1_test_source /= 5 or c2_test_source /= 5 or
c3_test_source /= 5 or c4_test_source /= 5 or
c5_test_source /= 5 else
false;
m1 : hardcopyii_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : hardcopyii_n_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= clkin when c0_test_source = 0 else
refclk when c0_test_source = 1 else
inclk_c_from_vco(0);
c0 : hardcopyii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= clkin when c1_test_source = 0 else
fbclk when c1_test_source = 2 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : hardcopyii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= clkin when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : hardcopyii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : hardcopyii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : hardcopyii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : hardcopyii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (sim_gate_lock_device_behavior = "on") then
if (count = gate_lock_counter) then
output := '1';
end if;
elsif (count = GATE_LOCK_CYCLES) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
if (refclk_int > (refclk_int * max_modulus / m_mod)) then
q_period := refclk_int * 1 ps;
else
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
sig_m_val_tmp <= m_val_tmp;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0),
c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5),
sig_refclk_period, m_val_tmp(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
sig_quiet_time <= quiet_time;
sig_slowest_clk_old <= slowest_clk_old;
sig_slowest_clk_new <= slowest_clk_new;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanwrite_enabled = '1') then
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = x) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end loop;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x)) then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
inclk_c_from_vco(i) <= vco_tap(x);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
end if;
end loop;
if (m_ph_val = x) then
inclk_m_from_vco <= vco_tap(x);
end if;
vco_tap_last_value(x) <= vco_tap(x);
end if;
end loop;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_posedge,
SetupLow => tsetup_scandata_scanclk_noedge_posedge,
HoldHigh => thold_scandata_scanclk_noedge_posedge,
HoldLow => thold_scandata_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanread_scanclk,
TimingData => TimingData_scanread_scanclk,
TestSignal => scanread_ipd,
TestSignalName => "scanread",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanread_scanclk_noedge_posedge,
SetupLow => tsetup_scanread_scanclk_noedge_posedge,
HoldHigh => thold_scanread_scanclk_noedge_posedge,
HoldLow => thold_scanread_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanwrite_scanclk,
TimingData => TimingData_scanwrite_scanclk,
TestSignal => scanwrite_ipd,
TestSignalName => "scanwrite",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanwrite_scanclk_noedge_posedge,
SetupLow => tsetup_scanwrite_scanclk_noedge_posedge,
HoldHigh => thold_scanwrite_scanclk_noedge_posedge,
HoldLow => thold_scanwrite_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable pll_is_disabled : boolean := false;
variable next_vco_sched_time : time := 0 ps;
variable tap0_is_active : boolean := true;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
pll_is_in_reset := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
pll_is_disabled := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
if (ena_ipd'event and ena_ipd = '1') then
assert false report family_name & " PLL is enabled" severity note;
pll_is_disabled := false;
if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- illegal value on areset_ipd
if (areset_ipd'event and areset_ipd = 'X') then
assert false report "Illegal value 'X' detected on ARESET input" severity warning;
end if;
if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
-- first_schedule := true;
-- vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
-- reset all counter phase taps to POF programmed values
end if;
if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap0
vco_out(0) <= transport vco_val after sched_time;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap 0
vco_out(0) <= transport vco_val after sched_time;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
next_vco_sched_time := now + sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- now schedule the other taps with the appropriate phase-shift
if (vco_out(0)'event) then
for k in 1 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_out(0) after phase_shift(k);
end loop;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped : do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
-- check which vco_tap has event
for x in 0 to 7 loop
if (vco_out(x) /= vco_out_last_value(x)) then
-- TAP X has event
if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then
if (vco_out(0) = '1') then
tap0_is_active := true;
end if;
if (tap0_is_active) then
vco_tap(0) <= vco_out(0);
end if;
elsif (tap0_is_active) then
vco_tap(x) <= vco_out(x);
end if;
if (sig_stop_vco = '1') then
vco_tap(x) <= '0';
end if;
vco_out_last_value(x) <= vco_out(x);
end if;
end loop;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process SCHEDULE;
clk0_tmp <= c_clk(i_clk0_counter);
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
scandataout <= scandataout_tmp;
scandone <= scandone_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyii_mac_bit_register
--
-- Description : a single bit register. This is used for registering all
-- single bit input ports.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_bit_register IS
GENERIC (
power_up : std_logic := '0';
tipd_data : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0'
);
END hardcopyii_mac_bit_register;
ARCHITECTURE arch OF hardcopyii_mac_bit_register IS
SIGNAL data_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic := '0';
SIGNAL viol_notifier : std_logic := '0';
SIGNAL data_dly : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
clk_delay: process (data_ipd)
begin
data_dly <= data_ipd;
end process;
PROCESS (data_dly, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_reg : STD_LOGIC := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg := data_dly;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg := '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
end if;
end if;
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_REGISTER
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_register IS
GENERIC (
data_width : integer := 18;
power_up : std_logic := '0';
tipd_data : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END hardcopyii_mac_register;
ARCHITECTURE arch OF hardcopyii_mac_register IS
SIGNAL data_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL viol_notifier : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
PROCESS (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg <= data_ipd;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg <= (others => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
end if;
end if;
END PROCESS;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_reg(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_reg(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_RS_BLOCK
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_rs_block IS
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END hardcopyii_mac_rs_block;
ARCHITECTURE arch OF hardcopyii_mac_rs_block IS
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tbuf : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_mult : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dly : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturated : std_logic := '0';
SIGNAL min : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL max : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL msb : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
round_ipd <= round ;
saturate_ipd <= saturate ;
addnsub_ipd <= addnsub ;
signa_ipd <= signa ;
signb_ipd <= signb ;
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
datain_ipd(71 downto 0) <= datain(71 downto 0) ;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
addnsub_ipd,
round_ipd)
VARIABLE dataout_round_tmp2 : std_logic_vector(71 DOWNTO 0);
BEGIN
IF (round_ipd = '1') THEN
dataout_round_tmp2 := datain_ipd + (2 **(conv_integer(dataoutsize - signsize - roundsize - "00000001")));
ELSE
dataout_round_tmp2 := datain_ipd;
END IF;
dataout_round <= dataout_round_tmp2;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
addnsub_ipd,
dataout_round)
VARIABLE dataout_saturate_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE saturated_tmp4 : std_logic := '0';
VARIABLE gnd : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE min_tmp5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE max_tmp6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE msb_tmp7 : std_logic := '0';
VARIABLE i : integer;
BEGIN
IF (saturate_ipd = '1') THEN
IF (block_type = "mac_mult") THEN
IF (dataout_round(dataa_width + datab_width - 1) = '0' AND dataout_round(dataa_width + datab_width - 2) = '1') THEN
dataout_saturate_tmp3 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN dataa_width + datab_width - 2 TO (72 - 1) LOOP
dataout_saturate_tmp3(i) := '0';
END LOOP;
saturated_tmp4 := '1';
ELSE
dataout_saturate_tmp3 := dataout_round;
saturated_tmp4 := '0';
END IF;
min_tmp5 := dataout_saturate_tmp3;
max_tmp6 := dataout_saturate_tmp3;
ELSE
IF ((operation(2) = '1') AND ((block_type = "ab") OR (block_type = "cd"))) THEN
saturated_tmp4 := '0';
i := datab_width - 2;
WHILE (i < (datab_width + signsize - 2)) LOOP
IF (dataout_round(datab_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
IF (saturated_tmp4 = '1') THEN
min_tmp5 := "111111111111111111111111111111111111111111111111111111111111111111111111";
max_tmp6 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN 0 TO ((datab_width - 2) - 1) LOOP
max_tmp6(i) := '0';
END LOOP;
FOR i IN datab_width - 2 TO (72 - 1) LOOP
min_tmp5(i) := '0';
END LOOP;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
msb_tmp7 := dataout_round(datab_width + 15);
ELSE
IF ((signa_ipd OR signb_ipd OR NOT addnsub_ipd) = '1') THEN
min_tmp5 := gnd + (2 **(conv_integer(dataa_width)));
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width))) - 1);
ELSE
min_tmp5 := "000000000000000000000000000000000000000000000000000000000000000000000000";
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width + 1))) - 1);
END IF;
saturated_tmp4 := '0';
i := dataa_width - 2;
WHILE (i < (dataa_width + signsize - 1)) LOOP
IF (dataout_round(dataa_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
msb_tmp7 := dataout_round(i);
END IF;
IF (saturated_tmp4 = '1') THEN
IF (msb_tmp7 = '1') THEN
dataout_saturate_tmp3 := max_tmp6;
ELSE
dataout_saturate_tmp3 := min_tmp5;
END IF;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
END IF;
ELSE
saturated_tmp4 := '0';
dataout_saturate_tmp3 := dataout_round;
END IF;
dataout_saturate <= dataout_saturate_tmp3;
saturated <= saturated_tmp4;
min <= min_tmp5;
max <= max_tmp6;
msb <= msb_tmp7;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
dataout_round,
dataout_saturate)
VARIABLE dataout_dly_tmp8 : std_logic_vector(71 DOWNTO 0);
VARIABLE i : integer;
VARIABLE width_tmp : integer;
BEGIN
IF (round_ipd = '1') THEN
dataout_dly_tmp8 := dataout_saturate;
width_tmp := conv_integer(dataoutsize) - conv_integer(signsize) - conv_integer(roundsize);
i := 0;
WHILE (i < width_tmp) LOOP
dataout_dly_tmp8(i) := '0';
i := i + 1;
END LOOP;
ELSE
dataout_dly_tmp8 := dataout_saturate;
END IF;
dataout_dly <= dataout_dly_tmp8;
END PROCESS;
dataout_tbuf <= datain WHEN (operation = 0) OR (operation = 7) ELSE rs_saturate ;
rs_saturate <= rs_mac_mult WHEN (saturate_ipd = '1') ELSE rs_mac_out ;
rs_mac_mult <= (dataout_dly(71 DOWNTO 3) & "00" & saturated)
WHEN ((saturate_ipd = '1') AND (saturated = '1') AND (block_type = "mac_mult")) ELSE rs_mac_out ;
rs_mac_out <= (dataout_dly(71 DOWNTO 3) & saturated & datain_ipd(1 DOWNTO 0))
WHEN ((saturate_ipd = '1') AND (block_type /= "mac_mult")) ELSE dataout_dly ;
pathDelay : BLOCK
BEGIN
g1 : for i in dataout'range generate
PROCESS (dataout_tbuf)
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(i),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END GENERATE;
END BLOCK;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_MULT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_mult_internal IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : integer := 36;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0) := (others => '0')
);
END hardcopyii_mac_mult_internal;
ARCHITECTURE arch OF hardcopyii_mac_mult_internal IS
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL neg : std_logic := '0';
SIGNAL dataout_pre_bypass : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_output : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
BEGIN
neg <= (dataa_ipd(dataa_width - 1) AND signa) XOR (datab_ipd(datab_width - 1) AND signb) ;
abs_a <= (NOT dataa_ipd(dataa_width - 1 DOWNTO 0) + 1) WHEN (signa AND dataa_ipd(dataa_width - 1)) = '1' ELSE dataa_ipd(dataa_width - 1 DOWNTO 0) ;
abs_b <= (NOT datab_ipd(datab_width - 1 DOWNTO 0) + 1) WHEN (signb AND datab_ipd(datab_width - 1)) = '1' ELSE datab_ipd(datab_width - 1 DOWNTO 0) ;
abs_output((dataa_width + datab_width) - 1 DOWNTO 0) <= abs_a(dataa_width-1 downto 0) * abs_b(datab_width-1 downto 0) ;
dataout_pre_bypass((dataa_width + datab_width) - 1 DOWNTO 0) <= (NOT abs_output + 1) WHEN neg = '1' ELSE abs_output ;
dataout_tmp((dataa_width + datab_width) - 1 DOWNTO 0) <= datab(datab_width-1 downto 0) & dataa(dataa_width-1 downto 0) when ((dynamic_mode = "yes") and (bypass = '1')) else dataa(dataa_width-1 downto 0) & datab(datab_width-1 downto 0) WHEN (bypass = '1') ELSE dataout_pre_bypass ;
PathDelay : block
begin
do:for i in dataout_tmp'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
sa: for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
PROCESS(dataa_ipd)
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sa;
sb: for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
PROCESS(datab_ipd)
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sb;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_MULT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_mac_mult_internal;
use work.hardcopyii_mac_bit_register;
use work.hardcopyii_mac_register;
use work.hardcopyii_mac_rs_block;
ENTITY hardcopyii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_mac_mult;
ARCHITECTURE arch OF hardcopyii_mac_mult IS
COMPONENT hardcopyii_mac_mult_internal
GENERIC (
dataout_width : integer := 36;
dataa_width : integer := 18;
datab_width : integer := 18;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0));
END COMPONENT;
COMPONENT hardcopyii_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT hardcopyii_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT hardcopyii_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL mult_output : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL round_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL mode_out : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_rs : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_src : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_dataa : std_logic := '0';
SIGNAL clear_dataa : std_logic := '0';
SIGNAL aclr_dataa : std_logic := '0';
SIGNAL ena_dataa : std_logic := '0';
SIGNAL async_dataa : std_logic := '0';
SIGNAL clk_datab : std_logic := '0';
SIGNAL clear_datab : std_logic := '0';
SIGNAL aclr_datab : std_logic := '0';
SIGNAL ena_datab : std_logic := '0';
SIGNAL async_datab : std_logic := '0';
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_round : std_logic := '0';
SIGNAL clear_round : std_logic := '0';
SIGNAL aclr_round : std_logic := '0';
SIGNAL ena_round : std_logic := '0';
SIGNAL async_round : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode : std_logic := '0';
SIGNAL clear_mode : std_logic := '0';
SIGNAL aclr_mode : std_logic := '0';
SIGNAL ena_mode : std_logic := '0';
SIGNAL async_mode : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL signa_internal : std_logic := '0';
SIGNAL signb_internal : std_logic := '0';
SIGNAL bypass : std_logic := '0';
SIGNAL mac_mult_dataoutsize : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_60 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp62 : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL port_tmp63 : std_logic := '0';
SIGNAL port_tmp64 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp65 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp2 : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp3 : std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
SIGNAL mode : std_logic := '0';
SIGNAL zeroacc : std_logic := '0';
BEGIN
dataout <= dataout_tmp1(dataout'range);
scanouta <= scanouta_tmp2;
scanoutb <= scanoutb_tmp3;
dataout_tmp1 <= dataout_tmp(35 DOWNTO 0) ;
dataa_src <= scanina WHEN (sourcea = '1') ELSE dataa ;
datab_src <= scaninb WHEN (sourceb = '1') ELSE datab ;
dataa_mac_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => dataa_width,
power_up => '0')
PORT MAP (
data => dataa_src,
clk => clk_dataa,
aclr => aclr_dataa,
if_aclr => clear_dataa,
ena => ena_dataa,
dataout => scanouta_tmp,
async => async_dataa);
async_dataa <= '1' WHEN (dataa_clock = "none") ELSE '0' ;
clear_dataa <= '1' WHEN (dataa_clear /= "none") ELSE '0' ;
clk_dataa <= '1' WHEN clk(conv_integer(dataa_clk)) = '1' ELSE '0' ;
aclr_dataa <= '1' WHEN (aclr(conv_integer(dataa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_dataa <= '1' WHEN ena(conv_integer(dataa_clk)) = '1' ELSE '0' ;
dataa_clk <= "0000" WHEN ((dataa_clock = "0") OR (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ;
dataa_aclr <= "0000" WHEN ((dataa_clear = "0") OR (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ;
datab_mac_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => datab_width,
power_up => '0')
PORT MAP (
data => datab_src,
clk => clk_datab,
aclr => aclr_datab,
if_aclr => clear_datab,
ena => ena_datab,
dataout => scanoutb_tmp,
async => async_datab);
async_datab <= '1' WHEN (datab_clock = "none") ELSE '0' ;
clear_datab <= '1' WHEN (datab_clear /= "none") ELSE '0' ;
clk_datab <= '1' WHEN clk(conv_integer(datab_clk)) = '1' ELSE '0' ;
aclr_datab <= '1' WHEN (aclr(conv_integer(datab_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_datab <= '1' WHEN ena(conv_integer(datab_clk)) = '1' ELSE '0' ;
datab_clk <= "0000" WHEN ((datab_clock = "0") OR (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ;
datab_aclr <= "0000" WHEN ((datab_clear = "0") OR (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ;
signa_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_out,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_out,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
round_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round,
clk => clk_round,
aclr => aclr_round,
if_aclr => clear_round,
ena => ena_round,
dataout => round_out,
async => async_round);
async_round <= '1' WHEN (round_clock = "none") ELSE '0' ;
clear_round <= '1' WHEN (round_clear /= "none") ELSE '0' ;
clk_round <= '1' WHEN clk(conv_integer(round_clk)) = '1' ELSE '0' ;
aclr_round <= '1' WHEN (aclr(conv_integer(round_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round <= '1' WHEN ena(conv_integer(round_clk)) = '1' ELSE '0' ;
round_clk <= "0000" WHEN ((round_clock = "0") OR (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ;
round_aclr <= "0000" WHEN ((round_clear = "0") OR (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ;
saturate_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_out,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode,
clk => clk_mode,
aclr => aclr_mode,
if_aclr => clear_mode,
ena => ena_mode,
dataout => mode_out,
async => async_mode);
async_mode <= '1' WHEN (mode_clock = "none") ELSE '0' ;
clear_mode <= '1' WHEN (mode_clear /= "none") ELSE '0' ;
clk_mode <= '1' WHEN clk(conv_integer(mode_clk)) = '1' ELSE '0' ;
aclr_mode <= '1' WHEN (aclr(conv_integer(mode_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode <= '1' WHEN ena(conv_integer(mode_clk)) = '1' ELSE '0' ;
mode_clk <= "0000" WHEN ((mode_clock = "0") OR (mode_clock = "none")) ELSE "0001" WHEN (mode_clock = "1") ELSE "0010" WHEN (mode_clock = "2") ELSE "0011" WHEN (mode_clock = "3") ELSE "0000" ;
mode_aclr <= "0000" WHEN ((mode_clear = "0") OR (mode_clear = "none")) ELSE "0001" WHEN (mode_clear = "1") ELSE "0010" WHEN (mode_clear = "2") ELSE "0011" WHEN (mode_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_out,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
mac_multiply : hardcopyii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
dataout_width => dataa_width + datab_width,
dynamic_mode => dynamic_mode)
PORT MAP (
dataa => scanouta_tmp,
datab => scanoutb_tmp,
signa => signa_internal,
signb => signb_internal,
bypass => bypass,
scanouta => scanouta_tmp2,
scanoutb => scanoutb_tmp3,
dataout => mult_output);
signa_internal <= '0' WHEN ((signa_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signa_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signa_out ;
signb_internal <= '0' WHEN ((signb_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signb_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signb_out ;
bypass <= '1' WHEN ((bypass_multiplier = "yes") AND (dynamic_mode = "no")) OR (((bypass_multiplier = "yes") AND (mode_out = '1')) AND (dynamic_mode = "yes")) ELSE '0' ;
tmp_60 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & mult_output(35 DOWNTO 0);
port_tmp62 <= "1111";
port_tmp63 <= '0';
port_tmp64 <= "00000010";
port_tmp65 <= "00001111";
mac_rs_block : hardcopyii_mac_rs_block
GENERIC MAP (
block_type => "mac_mult",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => port_tmp62,
round => round_out,
saturate => saturate_out,
addnsub => port_tmp63,
signa => signa_out,
signb => signb_out,
signsize => port_tmp64,
roundsize => port_tmp65,
dataoutsize => mac_mult_dataoutsize,
dataa => scanouta_tmp,
datab => scanoutb_tmp,
datain => tmp_60,
dataout => dataout_rs);
mac_mult_dataoutsize <= CONV_STD_LOGIC_VECTOR(dataa_width + datab_width, 8) ;
dataout_reg <= tmp_60 when bypass = '1' else dataout_rs;
dataout_mac_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => dataa_width + datab_width,
power_up => '0')
PORT MAP (
data => dataout_reg((dataa_width + datab_width) -1 downto 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_tmp((dataa_width + datab_width) -1 downto 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
END arch;
--////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_ADDNSUB
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_addnsub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
block_type : string := "ab");
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END hardcopyii_mac_addnsub;
ARCHITECTURE arch OF hardcopyii_mac_addnsub IS
-- REGULAR ADD/SUB
SIGNAL sa : std_logic := '0';
SIGNAL sb : std_logic := '0';
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
-- 36 BIT MULT
SIGNAL dataa_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
--SIGNAL z36 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--SIGNAL z18 : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
overflow <= overflow_tmp2;
PROCESS (dataa, datab, datac, datad, signa, signb, operation, addnsub)
--VARIABLE z36_tmp3 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--VARIABLE z18_tmp4 : std_logic_vector(17 DOWNTO 0) := (others => '0');
VARIABLE dataout_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE overflow_tmp_tmp13 : std_logic;
VARIABLE sa_tmp14 : std_logic;
VARIABLE sb_tmp15 : std_logic;
VARIABLE abs_a_tmp16 : std_logic_vector(71 DOWNTO 0);
VARIABLE abs_b_tmp17 : std_logic_vector(71 DOWNTO 0);
VARIABLE dataout_t : std_logic_vector(72 downto 0) := (others => '0');
VARIABLE dataa_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_s : std_logic_vector(71 downto 0) := (others => '0');
BEGIN
IF ((unsigned(operation) = 7) AND (block_type /= "sum")) THEN
dataa_u := (others => '0');
datab_u := (others => '0');
datac_u := (others => '0');
datad_u := (others => '0');
datab_s := (others => '0');
datac_s := (others => '0');
dataa_u(35 downto 0) := dataa(35 downto 0);
datab_u(71 downto 36) := datab(35 downto 0);
datab_s(71 downto 36) := datab(35 downto 0);
datac_u(53 downto 18) := datac(35 downto 0);
datac_s(71 downto 18) := sxt(datac(datac_width-1 downto 0), 54);
datad_u(53 downto 18) := datad(35 downto 0);
datad_s(71 downto 18) := sxt(datad(datad_width-1 downto 0), 54);
if((signa = '0') and (signb = '0')) then
dataout_tmp_tmp12 := unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signa = '0') and (signb = '1')) then
dataout_t := signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '0')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '1')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF ((operation(2) = '1') AND (block_type = "ab")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16) XOR dataout_tmp_tmp12(datab_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16);
END IF;
ELSE
IF ((operation(2) = '1') AND (block_type = "cd")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16) XOR dataout_tmp_tmp12(datad_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16);
END IF;
ELSE
IF (block_type = "sum") THEN
if ((signa = '1') and (signb = '0')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(ext(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '0') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(ext(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '1') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
else
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
unsigned(ext(dataa(dataa_width downto 0), dataa_width+2)) +
unsigned(ext(datab(datab_width downto 0), dataa_width+2));
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF (block_type = "cd") THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1) XOR dataout_tmp_tmp12(datac_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1);
END IF;
ELSE
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1) XOR dataout_tmp_tmp12(dataa_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1);
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
--z36 <= z36_tmp3;
--z18 <= z18_tmp4;
dataout_tmp <= dataout_tmp_tmp12;
overflow_tmp <= overflow_tmp_tmp13;
sa <= sa_tmp14;
sb <= sb_tmp15;
abs_a <= abs_a_tmp16;
abs_b <= abs_b_tmp17;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
overflow_tmp2 <= overflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_DYNAMIC_SRC
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_dynamic_src IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0'
);
END hardcopyii_mac_dynamic_src;
ARCHITECTURE arch OF hardcopyii_mac_dynamic_src IS
SIGNAL outa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp : std_logic := '0';
SIGNAL satb_tmp : std_logic := '0';
SIGNAL satc_tmp : std_logic := '0';
SIGNAL satd_tmp : std_logic := '0';
SIGNAL satab_tmp : std_logic := '0';
SIGNAL satcd_tmp : std_logic := '0';
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL outa_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp5 : std_logic := '0';
SIGNAL satb_tmp6 : std_logic := '0';
SIGNAL satc_tmp7 : std_logic := '0';
SIGNAL satd_tmp8 : std_logic := '0';
SIGNAL satab_tmp9 : std_logic := '0';
SIGNAL satcd_tmp10 : std_logic := '0';
SIGNAL dynamic_dataa_width : integer := 36;
SIGNAL dynamic_datab_width : integer := 36;
SIGNAL dynamic_datac_width : integer := 36;
SIGNAL dynamic_datad_width : integer := 36;
BEGIN
outa <= outa_tmp1;
outb <= outb_tmp2;
outc <= outc_tmp3;
outd <= outd_tmp4;
sata <= sata_tmp5;
satb <= satb_tmp6;
satc <= satc_tmp7;
satd <= satd_tmp8;
satab <= satab_tmp9;
satcd <= satcd_tmp10;
dynamic_dataa_width <= dataa_width WHEN (dataa_width > 0) ELSE 36;
dynamic_datab_width <= datab_width WHEN (datab_width > 0) ELSE 36;
dynamic_datac_width <= datac_width WHEN (datac_width > 0) ELSE 36;
dynamic_datad_width <= datad_width WHEN (datad_width > 0) ELSE 36;
PROCESS (accuma, accumc, dataa, datab, datac, datad, multabsaturate, multcdsaturate, signa, signb, zeroacc, zeroacc1, operation)
VARIABLE outa_tmp_tmp11 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outb_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outc_tmp_tmp13 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outd_tmp_tmp14 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE j_tmp15 : integer;
VARIABLE temp_tmp16 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE sata_tmp_tmp17 : std_logic := '0';
VARIABLE satb_tmp_tmp18 : std_logic := '0';
VARIABLE satc_tmp_tmp19 : std_logic := '0';
VARIABLE satd_tmp_tmp20 : std_logic := '0';
VARIABLE satab_tmp_tmp21 : std_logic := '0';
VARIABLE satcd_tmp_tmp22 : std_logic := '0';
BEGIN
CASE operation IS
WHEN "0000" =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') then
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "0100" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11:= sxt(dataa(datab_width+15 downto 0), 72);
ELSE
outa_tmp_tmp11:= ext(dataa(datab_width+15 downto 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
j_tmp15 := dataa_width - 1;
FOR i IN (datab_width + 15) DOWNTO 0 LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 - 1;
END LOOP;
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1100" =>
temp_tmp16 := zeroacc1 & zeroacc;
CASE temp_tmp16 IS
WHEN "00" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "01" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "10" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "11" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN OTHERS =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
WHEN "1101" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1110" =>
IF (zeroacc1 = '1') THEN
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN OTHERS =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signa = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signa = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
IF (multabsaturate = '1') THEN
IF ((outa_tmp_tmp11(0) AND ((zeroacc AND operation(2)) OR NOT operation(2))) = '1') THEN
sata_tmp_tmp17 := '1';
outa_tmp_tmp11(0) := '0';
ELSE
sata_tmp_tmp17 := '0';
END IF;
IF (outb_tmp_tmp12(0) = '1') THEN
satb_tmp_tmp18 := '1';
outb_tmp_tmp12(0) := '0';
ELSE
satb_tmp_tmp18 := '0';
END IF;
ELSE
sata_tmp_tmp17 := '0';
satb_tmp_tmp18 := '0';
END IF;
IF (multcdsaturate = '1') THEN
IF ((outc_tmp_tmp13(0) AND ((zeroacc1 AND operation(2)) OR NOT operation(2))) = '1') THEN
satc_tmp_tmp19 := '1';
outc_tmp_tmp13(0) := '0';
ELSE
satc_tmp_tmp19 := '0';
END IF;
IF (outd_tmp_tmp14(0) = '1') THEN
satd_tmp_tmp20 := '1';
outd_tmp_tmp14(0) := '0';
ELSE
satd_tmp_tmp20 := '0';
END IF;
ELSE
satc_tmp_tmp19 := '0';
satd_tmp_tmp20 := '0';
END IF;
IF ((sata_tmp_tmp17 OR satb_tmp_tmp18) = '1') THEN
satab_tmp_tmp21 := '1';
ELSE
satab_tmp_tmp21 := '0';
END IF;
IF ((satc_tmp_tmp19 OR satd_tmp_tmp20) = '1') THEN
satcd_tmp_tmp22 := '1';
ELSE
satcd_tmp_tmp22 := '0';
END IF;
outa_tmp <= outa_tmp_tmp11;
outb_tmp <= outb_tmp_tmp12;
outc_tmp <= outc_tmp_tmp13;
outd_tmp <= outd_tmp_tmp14;
j <= j_tmp15;
sata_tmp <= sata_tmp_tmp17;
satb_tmp <= satb_tmp_tmp18;
satc_tmp <= satc_tmp_tmp19;
satd_tmp <= satd_tmp_tmp20;
satab_tmp <= satab_tmp_tmp21;
satcd_tmp <= satcd_tmp_tmp22;
END PROCESS;
outa_tmp1 <= outa_tmp ;
outb_tmp2 <= outb_tmp ;
outc_tmp3 <= outc_tmp ;
outd_tmp4 <= outd_tmp ;
sata_tmp5 <= sata_tmp ;
satb_tmp6 <= satb_tmp ;
satc_tmp7 <= satc_tmp ;
satd_tmp8 <= satd_tmp ;
satab_tmp9 <= satab_tmp ;
satcd_tmp10 <= satcd_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_DYNAMIC_MUX
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_dynamic_mux IS
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END hardcopyii_mac_dynamic_mux;
ARCHITECTURE arch OF hardcopyii_mac_dynamic_mux IS
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
accoverflow <= accoverflow_tmp2;
PROCESS (ab, cd, sata, satb, satc, satd, multsatab, multsatcd, outsatab, outsatcd, multabsaturate, multcdsaturate, saturateab, saturatecd, overab, overcd, sum, m36, bypass, operation)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
VARIABLE accoverflow_tmp_tmp4 : std_logic := '0';
VARIABLE temp_tmp5 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp6 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp7 : std_logic_vector(3 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp8 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp9 : std_logic_vector(1 DOWNTO 0) := (others => '0');
BEGIN
CASE operation IS
WHEN "0000" =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
WHEN "0100" =>
temp_tmp5 := saturateab & multabsaturate;
CASE temp_tmp5 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "0001" =>
IF (multabsaturate = '1') THEN
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 2) & satb & sata;
ELSE
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 0);
END IF;
accoverflow_tmp_tmp4 := '0';
WHEN "0010" =>
temp_tmp6 := multsatcd & multsatab;
CASE temp_tmp6 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 2) & satb & sata;
accoverflow_tmp_tmp4 := '0';
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & sum(1 DOWNTO 0);
accoverflow_tmp_tmp4 := satd;
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & satb & sata;
accoverflow_tmp_tmp4 := satd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
END CASE;
WHEN "0111" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & m36;
accoverflow_tmp_tmp4 := '0';
WHEN "1100" =>
temp_tmp7 := saturatecd & saturateab & multsatcd & multsatab;
CASE temp_tmp7 IS
WHEN "0000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "0110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1101" =>
temp_tmp8 := saturateab & multabsaturate;
CASE temp_tmp8 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1110" =>
temp_tmp9 := saturatecd & multcdsaturate;
CASE temp_tmp9 IS
WHEN "00" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN "10" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overcd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
END CASE;
dataout_tmp <= dataout_tmp_tmp3;
accoverflow_tmp <= accoverflow_tmp_tmp4;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
accoverflow_tmp2 <= accoverflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_OUT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_mac_addnsub;
use work.hardcopyii_mac_dynamic_mux;
use work.hardcopyii_mac_dynamic_src;
use work.hardcopyii_mac_rs_block;
ENTITY hardcopyii_mac_out_internal IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width -1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0'
);
END hardcopyii_mac_out_internal;
ARCHITECTURE arch OF hardcopyii_mac_out_internal IS
COMPONENT hardcopyii_mac_addnsub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
block_type : string := "ab";
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT hardcopyii_mac_dynamic_mux
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT hardcopyii_mac_dynamic_src
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0');
END COMPONENT;
COMPONENT hardcopyii_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataa_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata : std_logic := '0';
SIGNAL satb : std_logic := '0';
SIGNAL satc : std_logic := '0';
SIGNAL satd : std_logic := '0';
SIGNAL satab : std_logic := '0';
SIGNAL satcd : std_logic := '0';
SIGNAL addnsub_ab_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_cd_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_sum : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_ab : std_logic := '0';
SIGNAL overflow_cd : std_logic := '0';
SIGNAL overflow_sum : std_logic := '0';
SIGNAL rs_block_ab_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_ab_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL feedback_ipd : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL saturateab_ipd : std_logic := '0';
SIGNAL saturatecd_ipd : std_logic := '0';
SIGNAL multabsaturate_ipd : std_logic := '0';
SIGNAL multcdsaturate_ipd : std_logic := '0';
SIGNAL dataout_tbuf : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tbuf : std_logic;
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signx_or_y : std_logic;
SIGNAL addnsub_signa_input : std_logic;
SIGNAL addnsub_signb_input : std_logic;
SIGNAL feedback_accuma : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL feedback_accumc : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL xory_addnsub0 : std_logic := '0';
SIGNAL xory_addnsub1 : std_logic := '0';
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_8 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_10 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp38 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp43 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp50 : std_logic := '0';
SIGNAL tmp_59 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataa_ipd(dataa_width -1 downto 0) <= dataa;
datab_ipd(datab_width -1 downto 0) <= datab;
datac_ipd(datac_width -1 downto 0) <= datac;
datad_ipd(datad_width -1 downto 0) <= datad;
WireDelay : block
begin
loopbits : FOR i in feedback'RANGE GENERATE
VitalWireDelay (feedback_ipd(i), feedback(i), tipd_feedback(i));
END GENERATE;
end block;
multabsaturate_ipd <= multabsaturate ;
multcdsaturate_ipd <= multcdsaturate ;
saturateab_ipd <= saturateab ;
saturatecd_ipd <= saturatecd ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '0')) AND (zeroacc1 = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE "0000" ;
addnsub_signa_input <= signx WHEN (operation_mode = "36_bit_multiply") ELSE signx WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
addnsub_signb_input <= signy WHEN (operation_mode = "36_bit_multiply") ELSE signy WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
tmp_4(dataa_ipd'range) <= dataa_ipd;
tmp_6(datab_ipd'range) <= datab_ipd;
tmp_8(datac_ipd'range) <= datac_ipd;
tmp_10(datad_ipd'range) <= datad_ipd;
dynamic_src : hardcopyii_mac_dynamic_src
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
accuma => feedback_accuma,
accumc => feedback_accumc,
dataa => tmp_4,
datab => tmp_6,
datac => tmp_8,
datad => tmp_10,
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
zeroacc => zeroacc,
zeroacc1 => zeroacc1,
signa => signx,
signb => signy,
operation => operation,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
satab => satab,
satcd => satcd,
outa => dataa_src,
outb => datab_src,
outc => datac_src,
outd => datad_src);
signx_or_y <= signx OR signy ;
feedback_accuma <= feedback(52 DOWNTO 37) & feedback(35 DOWNTO 0) WHEN (operation_mode = "dynamic") ELSE feedback(51 DOWNTO 0) ;
feedback_accumc <= feedback(124 DOWNTO 109) & feedback(107 DOWNTO 72) WHEN (operation_mode = "dynamic") ELSE feedback(123 DOWNTO 72) ;
addnsub_ab : hardcopyii_mac_addnsub
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => addnsub_signa_input,
signb => addnsub_signb_input,
operation => operation,
addnsub => addnsub0,
dataout => addnsub_ab_out,
overflow => overflow_ab);
addnsub_cd : hardcopyii_mac_addnsub
GENERIC MAP (
block_type => "cd",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => signx_or_y,
signb => signx_or_y,
operation => operation,
addnsub => addnsub1,
dataout => addnsub_cd_out,
overflow => overflow_cd);
port_tmp38 <= "00001111";
mac_rs_block_low : hardcopyii_mac_rs_block
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => operation,
round => roundab,
saturate => saturateab_ipd,
addnsub => addnsub0,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_ab_sign_size,
roundsize => port_tmp38,
dataoutsize => rs_block_ab_size,
dataa => dataa_src(dataa_width-1 downto 0),
datab => datab_src(datab_width-1 downto 0),
datain => addnsub_ab_out,
dataout => dataout_low);
rs_block_ab_size <= CONV_STD_LOGIC_VECTOR((datab_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_ab_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp43 <= "00001111";
mac_rs_block_high : hardcopyii_mac_rs_block
GENERIC MAP (
block_type => "cd",
dataa_width => datac_width,
datab_width => datad_width)
PORT MAP (
operation => operation,
round => roundcd,
saturate => saturatecd_ipd,
addnsub => addnsub1,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_cd_sign_size,
roundsize => port_tmp43,
dataoutsize => rs_block_cd_size,
dataa => datac_src(datac_width -1 downto 0),
datab => datad_src(datad_width -1 downto 0),
datain => addnsub_cd_out,
dataout => dataout_high);
rs_block_cd_size <= CONV_STD_LOGIC_VECTOR((datad_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_cd_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp50 <= '1';
addnsub_sum_abcd : hardcopyii_mac_addnsub
GENERIC MAP (
block_type => "sum",
dataa_width => dataa_width,
datab_width => dataa_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataout_low,
datab => dataout_high,
datac => datac_src,
datad => datad_src,
signa => xory_addnsub0,
signb => xory_addnsub1,
operation => operation,
addnsub => port_tmp50,
dataout => addnsub_sum,
overflow => overflow_sum);
xory_addnsub0 <= signx_or_y OR NOT addnsub0 ;
xory_addnsub1 <= signx_or_y OR NOT addnsub1 ;
tmp_59 <= datad_ipd & datac_ipd & datab_ipd & dataa_ipd;
dynamic_mux : hardcopyii_mac_dynamic_mux
PORT MAP (
ab => dataout_low,
cd => dataout_high,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
multsatab => satab,
multsatcd => satcd,
outsatab => dataout_low(2),
outsatcd => dataout_high(2),
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
saturateab => saturateab_ipd,
saturatecd => saturatecd_ipd,
overab => overflow_ab,
overcd => overflow_cd,
sum => addnsub_sum,
m36 => addnsub_ab_out,
bypass => tmp_59,
operation => operation,
dataout => dataout_tmp,
accoverflow => accoverflow_tmp);
PathDelay: for i in dataout'range generate
PROCESS(dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc'last_event, tpd_zeroacc_dataout(i), TRUE),
10 => (zeroacc1'last_event, tpd_zeroacc1_dataout(i), TRUE),
11 => (mode0'last_event, tpd_mode0_dataout(i), TRUE),
12 => (mode1'last_event, tpd_mode1_dataout(i), TRUE),
13 => (multabsaturate'last_event, tpd_multabsaturate_dataout(i), TRUE),
14 => (multcdsaturate'last_event, tpd_multcdsaturate_dataout(i), TRUE),
15 => (feedback'last_event, tpd_feedback_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate PathDelay;
acc: for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc'last_event, tpd_zeroacc_accoverflow, TRUE),
7 => (zeroacc1'last_event, tpd_zeroacc1_accoverflow, TRUE),
8 => (mode0'last_event, tpd_mode0_accoverflow, TRUE),
9 => (mode1'last_event, tpd_mode1_accoverflow, TRUE),
10 => (feedback'last_event, tpd_feedback_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
END GENERATE acc;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_PIN_MAP
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_mac_pin_map IS
GENERIC (
tipd_addnsub : VitalDelayType01 := DefPropDelay01;
data_width : integer := 144;
tipd_datain : VitalDelayArrayType01(143 downto 0) := (OTHERS => (20 ps,20 ps));
operation_mode : string := "output_only";
pinmap : string := "map");
PORT (
datain : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END hardcopyii_mac_pin_map;
ARCHITECTURE arch OF hardcopyii_mac_pin_map IS
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL datain_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp2 : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (addnsub_ipd, addnsub, tipd_addnsub);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
dataout <= dataout_tmp2(dataout'range);
PROCESS (datain_ipd, addnsub_ipd)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
BEGIN
IF (operation_mode = "dynamic") THEN
IF (pinmap = "map") THEN
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) &
'X' & datain_ipd(107 DOWNTO 72) &
"XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) &
'X' & datain_ipd(35 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := datain_ipd(143 DOWNTO 72)& "XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) & 'X' & datain_ipd(35 DOWNTO 0);
WHEN "1110" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) & 'X' & datain_ipd(107 DOWNTO 0);
WHEN "0111" =>
IF (addnsub_ipd = '1') THEN
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
ELSE
dataout_tmp_tmp3(17 DOWNTO 0) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(35 DOWNTO 18) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(53 DOWNTO 36) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(71 DOWNTO 54) := "XXXXXXXXXXXXXXXXXX";
END IF;
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
ELSE
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "1101" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(143 DOWNTO 72) := datain_ipd(143 DOWNTO 72);
WHEN "1110" =>
dataout_tmp_tmp3(107 DOWNTO 0) := datain_ipd(107 DOWNTO 0);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "0111" =>
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
END IF;
ELSE
dataout_tmp_tmp3 := datain_ipd;
END IF;
dataout_tmp <= dataout_tmp_tmp3;
END PROCESS;
dataout_tmp2 <= dataout_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- HARDCOPYII_MAC_OUT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
use work.hardcopyii_mac_out_internal;
use work.hardcopyii_mac_pin_map;
use work.hardcopyii_mac_bit_register;
use work.hardcopyii_mac_register;
ENTITY hardcopyii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_mac_out;
ARCHITECTURE arch OF hardcopyii_mac_out IS
COMPONENT hardcopyii_mac_out_internal
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width-1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic);
END COMPONENT;
COMPONENT hardcopyii_mac_pin_map
GENERIC (
pinmap : string := "map";
data_width : integer := 144;
operation_mode : string := "output_only");
PORT (
datain : IN std_logic_vector(data_width-1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width-1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT hardcopyii_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT hardcopyii_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataa_f : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL datac_f : std_logic_vector(datac_width-1 DOWNTO 0) := (others => '0');
SIGNAL signa_pipe : std_logic := '0';
SIGNAL signb_pipe : std_logic := '0';
SIGNAL multabsaturate_pipe : std_logic := '0';
SIGNAL multcdsaturate_pipe : std_logic := '0';
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL multabsaturate_out : std_logic := '0';
SIGNAL multcdsaturate_out : std_logic := '0';
SIGNAL addnsub0_pipe : std_logic := '0';
SIGNAL addnsub1_pipe : std_logic := '0';
SIGNAL addnsub0_out : std_logic := '0';
SIGNAL addnsub1_out : std_logic := '0';
SIGNAL zeroacc_pipe : std_logic := '0';
SIGNAL zeroacc1_pipe : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL zeroacc1_out : std_logic := '0';
SIGNAL dataout_feedback : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_map : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_mapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_unmapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_non_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic7 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_to_reg : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_reg : std_logic := '0';
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipe : std_logic := '0';
SIGNAL round1_pipe : std_logic := '0';
SIGNAL saturate_pipe : std_logic := '0';
SIGNAL saturate1_pipe : std_logic := '0';
SIGNAL mode0_pipe : std_logic := '0';
SIGNAL mode1_pipe : std_logic := '0';
SIGNAL round0_out : std_logic := '0';
SIGNAL round1_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL saturate1_out : std_logic := '0';
SIGNAL mode0_out : std_logic := '0';
SIGNAL mode1_out : std_logic := '0';
SIGNAL addnsub0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_zeroacc1 : std_logic := '0';
SIGNAL clear_zeroacc1 : std_logic := '0';
SIGNAL aclr_zeroacc1 : std_logic := '0';
SIGNAL ena_zeroacc1 : std_logic := '0';
SIGNAL async_zeroacc1 : std_logic := '0';
SIGNAL clk_addnsub0 : std_logic := '0';
SIGNAL clear_addnsub0 : std_logic := '0';
SIGNAL aclr_addnsub0 : std_logic := '0';
SIGNAL ena_addnsub0 : std_logic := '0';
SIGNAL async_addnsub0 : std_logic := '0';
SIGNAL clk_addnsub1 : std_logic := '0';
SIGNAL clear_addnsub1 : std_logic := '0';
SIGNAL aclr_addnsub1 : std_logic := '0';
SIGNAL ena_addnsub1 : std_logic := '0';
SIGNAL async_addnsub1 : std_logic := '0';
SIGNAL clk_round0 : std_logic := '0';
SIGNAL clear_round0 : std_logic := '0';
SIGNAL aclr_round0 : std_logic := '0';
SIGNAL ena_round0 : std_logic := '0';
SIGNAL async_round0 : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode0 : std_logic := '0';
SIGNAL clear_mode0 : std_logic := '0';
SIGNAL aclr_mode0 : std_logic := '0';
SIGNAL ena_mode0 : std_logic := '0';
SIGNAL async_mode0 : std_logic := '0';
SIGNAL clk_round1 : std_logic := '0';
SIGNAL clear_round1 : std_logic := '0';
SIGNAL aclr_round1 : std_logic := '0';
SIGNAL ena_round1 : std_logic := '0';
SIGNAL async_round1 : std_logic := '0';
SIGNAL clk_saturate1 : std_logic := '0';
SIGNAL clear_saturate1 : std_logic := '0';
SIGNAL aclr_saturate1 : std_logic := '0';
SIGNAL ena_saturate1 : std_logic := '0';
SIGNAL async_saturate1 : std_logic := '0';
SIGNAL clk_mode1 : std_logic := '0';
SIGNAL clear_mode1 : std_logic := '0';
SIGNAL aclr_mode1 : std_logic := '0';
SIGNAL ena_mode1 : std_logic := '0';
SIGNAL async_mode1 : std_logic := '0';
SIGNAL clk_multabsaturate : std_logic := '0';
SIGNAL clear_multabsaturate : std_logic := '0';
SIGNAL aclr_multabsaturate : std_logic := '0';
SIGNAL ena_multabsaturate : std_logic := '0';
SIGNAL async_multabsaturate : std_logic := '0';
SIGNAL clk_multcdsaturate : std_logic := '0';
SIGNAL clear_multcdsaturate : std_logic := '0';
SIGNAL aclr_multcdsaturate : std_logic := '0';
SIGNAL ena_multcdsaturate : std_logic := '0';
SIGNAL async_multcdsaturate : std_logic := '0';
SIGNAL clk_signa_pipeline : std_logic := '0';
SIGNAL clear_signa_pipeline : std_logic := '0';
SIGNAL aclr_signa_pipeline : std_logic := '0';
SIGNAL ena_signa_pipeline : std_logic := '0';
SIGNAL async_signa_pipeline : std_logic := '0';
SIGNAL clk_signb_pipeline : std_logic := '0';
SIGNAL clear_signb_pipeline : std_logic := '0';
SIGNAL aclr_signb_pipeline : std_logic := '0';
SIGNAL ena_signb_pipeline : std_logic := '0';
SIGNAL async_signb_pipeline : std_logic := '0';
SIGNAL clk_zeroacc_pipeline : std_logic := '0';
SIGNAL clear_zeroacc_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc_pipeline : std_logic := '0';
SIGNAL ena_zeroacc_pipeline : std_logic := '0';
SIGNAL async_zeroacc_pipeline : std_logic := '0';
SIGNAL clk_zeroacc1_pipeline : std_logic := '0';
SIGNAL clear_zeroacc1_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc1_pipeline : std_logic := '0';
SIGNAL ena_zeroacc1_pipeline : std_logic := '0';
SIGNAL async_zeroacc1_pipeline : std_logic := '0';
SIGNAL clk_addnsub0_pipeline : std_logic := '0';
SIGNAL clear_addnsub0_pipeline : std_logic := '0';
SIGNAL aclr_addnsub0_pipeline : std_logic := '0';
SIGNAL ena_addnsub0_pipeline : std_logic := '0';
SIGNAL async_addnsub0_pipeline : std_logic := '0';
SIGNAL clk_addnsub1_pipeline : std_logic := '0';
SIGNAL clear_addnsub1_pipeline : std_logic := '0';
SIGNAL aclr_addnsub1_pipeline : std_logic := '0';
SIGNAL ena_addnsub1_pipeline : std_logic := '0';
SIGNAL async_addnsub1_pipeline : std_logic := '0';
SIGNAL clk_round0_pipeline : std_logic := '0';
SIGNAL clear_round0_pipeline : std_logic := '0';
SIGNAL aclr_round0_pipeline : std_logic := '0';
SIGNAL ena_round0_pipeline : std_logic := '0';
SIGNAL async_round0_pipeline : std_logic := '0';
SIGNAL clk_saturate_pipeline : std_logic := '0';
SIGNAL clear_saturate_pipeline : std_logic := '0';
SIGNAL aclr_saturate_pipeline : std_logic := '0';
SIGNAL ena_saturate_pipeline : std_logic := '0';
SIGNAL async_saturate_pipeline : std_logic := '0';
SIGNAL clk_mode0_pipeline : std_logic := '0';
SIGNAL clear_mode0_pipeline : std_logic := '0';
SIGNAL aclr_mode0_pipeline : std_logic := '0';
SIGNAL ena_mode0_pipeline : std_logic := '0';
SIGNAL async_mode0_pipeline : std_logic := '0';
SIGNAL clk_round1_pipeline : std_logic := '0';
SIGNAL clear_round1_pipeline : std_logic := '0';
SIGNAL aclr_round1_pipeline : std_logic := '0';
SIGNAL ena_round1_pipeline : std_logic := '0';
SIGNAL async_round1_pipeline : std_logic := '0';
SIGNAL clk_saturate1_pipeline : std_logic := '0';
SIGNAL clear_saturate1_pipeline : std_logic := '0';
SIGNAL aclr_saturate1_pipeline : std_logic := '0';
SIGNAL ena_saturate1_pipeline : std_logic := '0';
SIGNAL async_saturate1_pipeline : std_logic := '0';
SIGNAL clk_mode1_pipeline : std_logic := '0';
SIGNAL clear_mode1_pipeline : std_logic := '0';
SIGNAL aclr_mode1_pipeline : std_logic := '0';
SIGNAL ena_mode1_pipeline : std_logic := '0';
SIGNAL async_mode1_pipeline : std_logic := '0';
SIGNAL clk_multabsaturate_pipeline : std_logic := '0';
SIGNAL clear_multabsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multabsaturate_pipeline : std_logic := '0';
SIGNAL ena_multabsaturate_pipeline : std_logic := '0';
SIGNAL async_multabsaturate_pipeline : std_logic := '0';
SIGNAL clk_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clear_multcdsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multcdsaturate_pipeline : std_logic := '0';
SIGNAL ena_multcdsaturate_pipeline : std_logic := '0';
SIGNAL async_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL clk_output1 : std_logic := '0';
SIGNAL clear_output1 : std_logic := '0';
SIGNAL aclr_output1 : std_logic := '0';
SIGNAL ena_output1 : std_logic := '0';
SIGNAL async_output1 : std_logic := '0';
SIGNAL clk_output2 : std_logic := '0';
SIGNAL clear_output2 : std_logic := '0';
SIGNAL aclr_output2 : std_logic := '0';
SIGNAL ena_output2 : std_logic := '0';
SIGNAL async_output2 : std_logic := '0';
SIGNAL clk_output3 : std_logic := '0';
SIGNAL clear_output3 : std_logic := '0';
SIGNAL aclr_output3 : std_logic := '0';
SIGNAL ena_output3 : std_logic := '0';
SIGNAL async_output3 : std_logic := '0';
SIGNAL clk_output4 : std_logic := '0';
SIGNAL clear_output4 : std_logic := '0';
SIGNAL aclr_output4 : std_logic := '0';
SIGNAL ena_output4 : std_logic := '0';
SIGNAL async_output4 : std_logic := '0';
SIGNAL clk_output5 : std_logic := '0';
SIGNAL clear_output5 : std_logic := '0';
SIGNAL aclr_output5 : std_logic := '0';
SIGNAL ena_output5 : std_logic := '0';
SIGNAL async_output5 : std_logic := '0';
SIGNAL clk_output6 : std_logic := '0';
SIGNAL clear_output6 : std_logic := '0';
SIGNAL aclr_output6 : std_logic := '0';
SIGNAL ena_output6 : std_logic := '0';
SIGNAL async_output6 : std_logic := '0';
SIGNAL clk_output7 : std_logic := '0';
SIGNAL clear_output7 : std_logic := '0';
SIGNAL aclr_output7 : std_logic := '0';
SIGNAL ena_output7 : std_logic := '0';
SIGNAL async_output7 : std_logic := '0';
SIGNAL tmp_186 : std_logic := '0';
SIGNAL tmp_189 : std_logic := '0';
SIGNAL accoverflow_tmp2 : std_logic := '0';
SIGNAL pin_map_addnsub : std_logic := '0';
SIGNAL mode0 : std_logic := '0';
SIGNAL mode1 : std_logic := '0';
SIGNAL zeroacc1 : std_logic := '0';
SIGNAL saturate1 : std_logic := '0';
BEGIN
dataout <= dataout_tmp(dataout'range);
accoverflow <= accoverflow_tmp2;
signa_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_pipe,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_pipe,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_pipe,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
zeroacc1_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1,
clk => clk_zeroacc1,
aclr => aclr_zeroacc1,
if_aclr => clear_zeroacc1,
ena => ena_zeroacc1,
dataout => zeroacc1_pipe,
async => async_zeroacc1);
async_zeroacc1 <= '1' WHEN (zeroacc1_clock = "none") ELSE '0' ;
clear_zeroacc1 <= '1' WHEN (zeroacc1_clear /= "none") ELSE '0' ;
clk_zeroacc1 <= '1' WHEN clk(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
aclr_zeroacc1 <= '1' WHEN (aclr(conv_integer(zeroacc1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1 <= '1' WHEN ena(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
zeroacc1_clk <= "0000" WHEN ((zeroacc1_clock = "0") OR (zeroacc1_clock = "none")) ELSE "0001" WHEN (zeroacc1_clock = "1") ELSE "0010" WHEN (zeroacc1_clock = "2") ELSE "0011" WHEN (zeroacc1_clock = "3") ELSE "0000" ;
zeroacc1_aclr <= "0000" WHEN ((zeroacc1_clear = "0") OR (zeroacc1_clear = "none")) ELSE "0001" WHEN (zeroacc1_clear = "1") ELSE "0010" WHEN (zeroacc1_clear = "2") ELSE "0011" WHEN (zeroacc1_clear = "3") ELSE "0000" ;
addnsub0_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
if_aclr => clear_addnsub0,
ena => ena_addnsub0,
dataout => addnsub0_pipe,
async => async_addnsub0);
async_addnsub0 <= '1' WHEN (addnsub0_clock = "none") ELSE '0' ;
clear_addnsub0 <= '1' WHEN (addnsub0_clear /= "none") ELSE '0' ;
clk_addnsub0 <= '1' WHEN clk(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
aclr_addnsub0 <= '1' WHEN (aclr(conv_integer(addnsub0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0 <= '1' WHEN ena(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
addnsub0_clk <= "0000" WHEN ((addnsub0_clock = "0") OR (addnsub0_clock = "none")) ELSE "0001" WHEN (addnsub0_clock = "1") ELSE "0010" WHEN (addnsub0_clock = "2") ELSE "0011" WHEN (addnsub0_clock = "3") ELSE "0000" ;
addnsub0_aclr <= "0000" WHEN ((addnsub0_clear = "0") OR (addnsub0_clear = "none")) ELSE "0001" WHEN (addnsub0_clear = "1") ELSE "0010" WHEN (addnsub0_clear = "2") ELSE "0011" WHEN (addnsub0_clear = "3") ELSE "0000" ;
addnsub1_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
if_aclr => clear_addnsub1,
ena => ena_addnsub1,
dataout => addnsub1_pipe,
async => async_addnsub1);
async_addnsub1 <= '1' WHEN (addnsub1_clock = "none") ELSE '0' ;
clear_addnsub1 <= '1' WHEN (addnsub1_clear /= "none") ELSE '0' ;
clk_addnsub1 <= '1' WHEN clk(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
aclr_addnsub1 <= '1' WHEN (aclr(conv_integer(addnsub1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1 <= '1' WHEN ena(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
addnsub1_clk <= "0000" WHEN ((addnsub1_clock = "0") OR (addnsub1_clock = "none")) ELSE "0001" WHEN (addnsub1_clock = "1") ELSE "0010" WHEN (addnsub1_clock = "2") ELSE "0011" WHEN (addnsub1_clock = "3") ELSE "0000" ;
addnsub1_aclr <= "0000" WHEN ((addnsub1_clear = "0") OR (addnsub1_clear = "none")) ELSE "0001" WHEN (addnsub1_clear = "1") ELSE "0010" WHEN (addnsub1_clear = "2") ELSE "0011" WHEN (addnsub1_clear = "3") ELSE "0000" ;
round0_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0,
clk => clk_round0,
aclr => aclr_round0,
if_aclr => clear_round0,
ena => ena_round0,
dataout => round0_pipe,
async => async_round0);
async_round0 <= '1' WHEN (round0_clock = "none") ELSE '0' ;
clear_round0 <= '1' WHEN (round0_clear /= "none") ELSE '0' ;
clk_round0 <= '1' WHEN clk(conv_integer(round0_clk)) = '1' ELSE '0' ;
aclr_round0 <= '1' WHEN (aclr(conv_integer(round0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0 <= '1' WHEN ena(conv_integer(round0_clk)) = '1' ELSE '0' ;
round0_clk <= "0000" WHEN ((round0_clock = "0") OR (round0_clock = "none")) ELSE "0001" WHEN (round0_clock = "1") ELSE "0010" WHEN (round0_clock = "2") ELSE "0011" WHEN (round0_clock = "3") ELSE "0000" ;
round0_aclr <= "0000" WHEN ((round0_clear = "0") OR (round0_clear = "none")) ELSE "0001" WHEN (round0_clear = "1") ELSE "0010" WHEN (round0_clear = "2") ELSE "0011" WHEN (round0_clear = "3") ELSE "0000" ;
saturate_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_pipe,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode0_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0,
clk => clk_mode0,
aclr => aclr_mode0,
if_aclr => clear_mode0,
ena => ena_mode0,
dataout => mode0_pipe,
async => async_mode0);
async_mode0 <= '1' WHEN (mode0_clock = "none") ELSE '0' ;
clear_mode0 <= '1' WHEN (mode0_clear /= "none") ELSE '0' ;
clk_mode0 <= '1' WHEN clk(conv_integer(mode0_clk)) = '1' ELSE '0' ;
aclr_mode0 <= '1' WHEN (aclr(conv_integer(mode0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0 <= '1' WHEN ena(conv_integer(mode0_clk)) = '1' ELSE '0' ;
mode0_clk <= "0000" WHEN ((mode0_clock = "0") OR (mode0_clock = "none")) ELSE "0001" WHEN (mode0_clock = "1") ELSE "0010" WHEN (mode0_clock = "2") ELSE "0011" WHEN (mode0_clock = "3") ELSE "0000" ;
mode0_aclr <= "0000" WHEN ((mode0_clear = "0") OR (mode0_clear = "none")) ELSE "0001" WHEN (mode0_clear = "1") ELSE "0010" WHEN (mode0_clear = "2") ELSE "0011" WHEN (mode0_clear = "3") ELSE "0000" ;
round1_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1,
clk => clk_round1,
aclr => aclr_round1,
if_aclr => clear_round1,
ena => ena_round1,
dataout => round1_pipe,
async => async_round1);
async_round1 <= '1' WHEN (round1_clock = "none") ELSE '0' ;
clear_round1 <= '1' WHEN (round1_clear /= "none") ELSE '0' ;
clk_round1 <= '1' WHEN clk(conv_integer(round1_clk)) = '1' ELSE '0' ;
aclr_round1 <= '1' WHEN (aclr(conv_integer(round1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1 <= '1' WHEN ena(conv_integer(round1_clk)) = '1' ELSE '0' ;
round1_clk <= "0000" WHEN ((round1_clock = "0") OR (round1_clock = "none")) ELSE "0001" WHEN (round1_clock = "1") ELSE "0010" WHEN (round1_clock = "2") ELSE "0011" WHEN (round1_clock = "3") ELSE "0000" ;
round1_aclr <= "0000" WHEN ((round1_clear = "0") OR (round1_clear = "none")) ELSE "0001" WHEN (round1_clear = "1") ELSE "0010" WHEN (round1_clear = "2") ELSE "0011" WHEN (round1_clear = "3") ELSE "0000" ;
saturate1_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1,
clk => clk_saturate1,
aclr => aclr_saturate1,
if_aclr => clear_saturate1,
ena => ena_saturate1,
dataout => saturate1_pipe,
async => async_saturate1);
async_saturate1 <= '1' WHEN (saturate1_clock = "none") ELSE '0' ;
clear_saturate1 <= '1' WHEN (saturate1_clear /= "none") ELSE '0' ;
clk_saturate1 <= '1' WHEN clk(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
aclr_saturate1 <= '1' WHEN (aclr(conv_integer(saturate1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1 <= '1' WHEN ena(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
saturate1_clk <= "0000" WHEN ((saturate1_clock = "0") OR (saturate1_clock = "none")) ELSE "0001" WHEN (saturate1_clock = "1") ELSE "0010" WHEN (saturate1_clock = "2") ELSE "0011" WHEN (saturate1_clock = "3") ELSE "0000" ;
saturate1_aclr <= "0000" WHEN ((saturate1_clear = "0") OR (saturate1_clear = "none")) ELSE "0001" WHEN (saturate1_clear = "1") ELSE "0010" WHEN (saturate1_clear = "2") ELSE "0011" WHEN (saturate1_clear = "3") ELSE "0000" ;
mode1_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1,
clk => clk_mode1,
aclr => aclr_mode1,
if_aclr => clear_mode1,
ena => ena_mode1,
dataout => mode1_pipe,
async => async_mode1);
async_mode1 <= '1' WHEN (mode1_clock = "none") ELSE '0' ;
clear_mode1 <= '1' WHEN (mode1_clear /= "none") ELSE '0' ;
clk_mode1 <= '1' WHEN clk(conv_integer(mode1_clk)) = '1' ELSE '0' ;
aclr_mode1 <= '1' WHEN (aclr(conv_integer(mode1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1 <= '1' WHEN ena(conv_integer(mode1_clk)) = '1' ELSE '0' ;
mode1_clk <= "0000" WHEN ((mode1_clock = "0") OR (mode1_clock = "none")) ELSE "0001" WHEN (mode1_clock = "1") ELSE "0010" WHEN (mode1_clock = "2") ELSE "0011" WHEN (mode1_clock = "3") ELSE "0000" ;
mode1_aclr <= "0000" WHEN ((mode1_clear = "0") OR (mode1_clear = "none")) ELSE "0001" WHEN (mode1_clear = "1") ELSE "0010" WHEN (mode1_clear = "2") ELSE "0011" WHEN (mode1_clear = "3") ELSE "0000" ;
multabsaturate_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate,
clk => clk_multabsaturate,
aclr => aclr_multabsaturate,
if_aclr => clear_multabsaturate,
ena => ena_multabsaturate,
dataout => multabsaturate_pipe,
async => async_multabsaturate);
async_multabsaturate <= '1' WHEN (multabsaturate_clock = "none") ELSE '0' ;
clear_multabsaturate <= '1' WHEN (multabsaturate_clear /= "none") ELSE '0' ;
clk_multabsaturate <= '1' WHEN clk(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
aclr_multabsaturate <= '1' WHEN (aclr(conv_integer(multabsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate <= '1' WHEN ena(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
multabsaturate_clk <= "0000" WHEN ((multabsaturate_clock = "0") OR (multabsaturate_clock = "none")) ELSE "0001" WHEN (multabsaturate_clock = "1") ELSE "0010" WHEN (multabsaturate_clock = "2") ELSE "0011" WHEN (multabsaturate_clock = "3") ELSE "0000" ;
multabsaturate_aclr <= "0000" WHEN ((multabsaturate_clear = "0") OR (multabsaturate_clear = "none")) ELSE "0001" WHEN (multabsaturate_clear = "1") ELSE "0010" WHEN (multabsaturate_clear = "2") ELSE "0011" WHEN (multabsaturate_clear = "3") ELSE "0000" ;
multcdsaturate_mac_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate,
clk => clk_multcdsaturate,
aclr => aclr_multcdsaturate,
if_aclr => clear_multcdsaturate,
ena => ena_multcdsaturate,
dataout => multcdsaturate_pipe,
async => async_multcdsaturate);
async_multcdsaturate <= '1' WHEN (multcdsaturate_clock = "none") ELSE '0' ;
clear_multcdsaturate <= '1' WHEN (multcdsaturate_clear /= "none") ELSE '0' ;
clk_multcdsaturate <= '1' WHEN clk(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate <= '1' WHEN (aclr(conv_integer(multcdsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate <= '1' WHEN ena(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
multcdsaturate_clk <= "0000" WHEN ((multcdsaturate_clock = "0") OR (multcdsaturate_clock = "none")) ELSE "0001" WHEN (multcdsaturate_clock = "1") ELSE "0010" WHEN (multcdsaturate_clock = "2") ELSE "0011" WHEN (multcdsaturate_clock = "3") ELSE "0000" ;
multcdsaturate_aclr <= "0000" WHEN ((multcdsaturate_clear = "0") OR (multcdsaturate_clear = "none")) ELSE "0001" WHEN (multcdsaturate_clear = "1") ELSE "0010" WHEN (multcdsaturate_clear = "2") ELSE "0011" WHEN (multcdsaturate_clear = "3") ELSE "0000" ;
signa_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
if_aclr => clear_signa_pipeline,
ena => ena_signa_pipeline,
dataout => signa_out,
async => async_signa_pipeline);
async_signa_pipeline <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0' ;
clear_signa_pipeline <= '1' WHEN (signa_pipeline_clear /= "none") ELSE '0' ;
clk_signa_pipeline <= '1' WHEN clk(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
aclr_signa_pipeline <= '1' WHEN (aclr(conv_integer(signa_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa_pipeline <= '1' WHEN ena(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
signa_pipeline_clk <= "0000" WHEN ((signa_pipeline_clock = "0") OR (signa_pipeline_clock = "none")) ELSE "0001" WHEN (signa_pipeline_clock = "1") ELSE "0010" WHEN (signa_pipeline_clock = "2") ELSE "0011" WHEN (signa_pipeline_clock = "3") ELSE "0000" ;
signa_pipeline_aclr <= "0000" WHEN ((signa_pipeline_clear = "0") OR (signa_pipeline_clear = "none")) ELSE "0001" WHEN (signa_pipeline_clear = "1") ELSE "0010" WHEN (signa_pipeline_clear = "2") ELSE "0011" WHEN (signa_pipeline_clear = "3") ELSE "0000" ;
signb_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
if_aclr => clear_signb_pipeline,
ena => ena_signb_pipeline,
dataout => signb_out,
async => async_signb_pipeline);
async_signb_pipeline <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0' ;
clear_signb_pipeline <= '1' WHEN (signb_pipeline_clear /= "none") ELSE '0' ;
clk_signb_pipeline <= '1' WHEN clk(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
aclr_signb_pipeline <= '1' WHEN (aclr(conv_integer(signb_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb_pipeline <= '1' WHEN ena(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
signb_pipeline_clk <= "0000" WHEN ((signb_pipeline_clock = "0") OR (signb_pipeline_clock = "none")) ELSE "0001" WHEN (signb_pipeline_clock = "1") ELSE "0010" WHEN (signb_pipeline_clock = "2") ELSE "0011" WHEN (signb_pipeline_clock = "3") ELSE "0000" ;
signb_pipeline_aclr <= "0000" WHEN ((signb_pipeline_clear = "0") OR (signb_pipeline_clear = "none")) ELSE "0001" WHEN (signb_pipeline_clear = "1") ELSE "0010" WHEN (signb_pipeline_clear = "2") ELSE "0011" WHEN (signb_pipeline_clear = "3") ELSE "0000" ;
zeroacc_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
if_aclr => clear_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
dataout => zeroacc_out,
async => async_zeroacc_pipeline);
async_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc_pipeline <= '1' WHEN clk(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc_pipeline <= '1' WHEN ena(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
zeroacc_pipeline_clk <= "0000" WHEN ((zeroacc_pipeline_clock = "0") OR (zeroacc_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc_pipeline_clock = "3") ELSE "0000" ;
zeroacc_pipeline_aclr <= "0000" WHEN ((zeroacc_pipeline_clear = "0") OR (zeroacc_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc_pipeline_clear = "3") ELSE "0000" ;
zeroacc1_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1_pipe,
clk => clk_zeroacc1_pipeline,
aclr => aclr_zeroacc1_pipeline,
if_aclr => clear_zeroacc1_pipeline,
ena => ena_zeroacc1_pipeline,
dataout => zeroacc1_out,
async => async_zeroacc1_pipeline);
async_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc1_pipeline <= '1' WHEN clk(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc1_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1_pipeline <= '1' WHEN ena(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
zeroacc1_pipeline_clk <= "0000" WHEN ((zeroacc1_pipeline_clock = "0") OR (zeroacc1_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clock = "3") ELSE "0000" ;
zeroacc1_pipeline_aclr <= "0000" WHEN ((zeroacc1_pipeline_clear = "0") OR (zeroacc1_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clear = "3") ELSE "0000" ;
addnsub0_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
if_aclr => clear_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
dataout => addnsub0_out,
async => async_addnsub0_pipeline);
async_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clock = "none") ELSE '0' ;
clear_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub0_pipeline <= '1' WHEN clk(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub0_pipeline <= '1' WHEN (aclr(conv_integer(addnsub0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0_pipeline <= '1' WHEN ena(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
addnsub0_pipeline_clk <= "0000" WHEN ((addnsub0_pipeline_clock = "0") OR (addnsub0_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clock = "1") ELSE "0010" WHEN (addnsub0_pipeline_clock = "2") ELSE "0011" WHEN (addnsub0_pipeline_clock = "3") ELSE "0000" ;
addnsub0_pipeline_aclr <= "0000" WHEN ((addnsub0_pipeline_clear = "0") OR (addnsub0_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clear = "1") ELSE "0010" WHEN (addnsub0_pipeline_clear = "2") ELSE "0011" WHEN (addnsub0_pipeline_clear = "3") ELSE "0000" ;
addnsub1_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
if_aclr => clear_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
dataout => addnsub1_out,
async => async_addnsub1_pipeline);
async_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clock = "none") ELSE '0' ;
clear_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub1_pipeline <= '1' WHEN clk(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub1_pipeline <= '1' WHEN (aclr(conv_integer(addnsub1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1_pipeline <= '1' WHEN ena(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
addnsub1_pipeline_clk <= "0000" WHEN ((addnsub1_pipeline_clock = "0") OR (addnsub1_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clock = "1") ELSE "0010" WHEN (addnsub1_pipeline_clock = "2") ELSE "0011" WHEN (addnsub1_pipeline_clock = "3") ELSE "0000" ;
addnsub1_pipeline_aclr <= "0000" WHEN ((addnsub1_pipeline_clear = "0") OR (addnsub1_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clear = "1") ELSE "0010" WHEN (addnsub1_pipeline_clear = "2") ELSE "0011" WHEN (addnsub1_pipeline_clear = "3") ELSE "0000" ;
round0_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0_pipe,
clk => clk_round0_pipeline,
aclr => aclr_round0_pipeline,
if_aclr => clear_round0_pipeline,
ena => ena_round0_pipeline,
dataout => round0_out,
async => async_round0_pipeline);
async_round0_pipeline <= '1' WHEN (round0_pipeline_clock = "none") ELSE '0' ;
clear_round0_pipeline <= '1' WHEN (round0_pipeline_clear /= "none") ELSE '0' ;
clk_round0_pipeline <= '1' WHEN clk(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
aclr_round0_pipeline <= '1' WHEN (aclr(conv_integer(round0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0_pipeline <= '1' WHEN ena(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
round0_pipeline_clk <= "0000" WHEN ((round0_pipeline_clock = "0") OR (round0_pipeline_clock = "none")) ELSE "0001" WHEN (round0_pipeline_clock = "1") ELSE "0010" WHEN (round0_pipeline_clock = "2") ELSE "0011" WHEN (round0_pipeline_clock = "3") ELSE "0000" ;
round0_pipeline_aclr <= "0000" WHEN ((round0_pipeline_clear = "0") OR (round0_pipeline_clear = "none")) ELSE "0001" WHEN (round0_pipeline_clear = "1") ELSE "0010" WHEN (round0_pipeline_clear = "2") ELSE "0011" WHEN (round0_pipeline_clear = "3") ELSE "0000" ;
saturate_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate_pipe,
clk => clk_saturate_pipeline,
aclr => aclr_saturate_pipeline,
if_aclr => clear_saturate_pipeline,
ena => ena_saturate_pipeline,
dataout => saturate_out,
async => async_saturate_pipeline);
async_saturate_pipeline <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0' ;
clear_saturate_pipeline <= '1' WHEN (saturate_pipeline_clear /= "none") ELSE '0' ;
clk_saturate_pipeline <= '1' WHEN clk(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate_pipeline <= '1' WHEN (aclr(conv_integer(saturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate_pipeline <= '1' WHEN ena(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
saturate_pipeline_clk <= "0000" WHEN ((saturate_pipeline_clock = "0") OR (saturate_pipeline_clock = "none")) ELSE "0001" WHEN (saturate_pipeline_clock = "1") ELSE "0010" WHEN (saturate_pipeline_clock = "2") ELSE "0011" WHEN (saturate_pipeline_clock = "3") ELSE "0000" ;
saturate_pipeline_aclr <= "0000" WHEN ((saturate_pipeline_clear = "0") OR (saturate_pipeline_clear = "none")) ELSE "0001" WHEN (saturate_pipeline_clear = "1") ELSE "0010" WHEN (saturate_pipeline_clear = "2") ELSE "0011" WHEN (saturate_pipeline_clear = "3") ELSE "0000" ;
mode0_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0_pipe,
clk => clk_mode0_pipeline,
aclr => aclr_mode0_pipeline,
if_aclr => clear_mode0_pipeline,
ena => ena_mode0_pipeline,
dataout => mode0_out,
async => async_mode0_pipeline);
async_mode0_pipeline <= '1' WHEN (mode0_pipeline_clock = "none") ELSE '0' ;
clear_mode0_pipeline <= '1' WHEN (mode0_pipeline_clear /= "none") ELSE '0' ;
clk_mode0_pipeline <= '1' WHEN clk(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode0_pipeline <= '1' WHEN (aclr(conv_integer(mode0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0_pipeline <= '1' WHEN ena(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
mode0_pipeline_clk <= "0000" WHEN ((mode0_pipeline_clock = "0") OR (mode0_pipeline_clock = "none")) ELSE "0001" WHEN (mode0_pipeline_clock = "1") ELSE "0010" WHEN (mode0_pipeline_clock = "2") ELSE "0011" WHEN (mode0_pipeline_clock = "3") ELSE "0000" ;
mode0_pipeline_aclr <= "0000" WHEN ((mode0_pipeline_clear = "0") OR (mode0_pipeline_clear = "none")) ELSE "0001" WHEN (mode0_pipeline_clear = "1") ELSE "0010" WHEN (mode0_pipeline_clear = "2") ELSE "0011" WHEN (mode0_pipeline_clear = "3") ELSE "0000" ;
round1_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1_pipe,
clk => clk_round1_pipeline,
aclr => aclr_round1_pipeline,
if_aclr => clear_round1_pipeline,
ena => ena_round1_pipeline,
dataout => round1_out,
async => async_round1_pipeline);
async_round1_pipeline <= '1' WHEN (round1_pipeline_clock = "none") ELSE '0' ;
clear_round1_pipeline <= '1' WHEN (round1_pipeline_clear /= "none") ELSE '0' ;
clk_round1_pipeline <= '1' WHEN clk(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
aclr_round1_pipeline <= '1' WHEN (aclr(conv_integer(round1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1_pipeline <= '1' WHEN ena(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
round1_pipeline_clk <= "0000" WHEN ((round1_pipeline_clock = "0") OR (round1_pipeline_clock = "none")) ELSE "0001" WHEN (round1_pipeline_clock = "1") ELSE "0010" WHEN (round1_pipeline_clock = "2") ELSE "0011" WHEN (round1_pipeline_clock = "3") ELSE "0000" ;
round1_pipeline_aclr <= "0000" WHEN ((round1_pipeline_clear = "0") OR (round1_pipeline_clear = "none")) ELSE "0001" WHEN (round1_pipeline_clear = "1") ELSE "0010" WHEN (round1_pipeline_clear = "2") ELSE "0011" WHEN (round1_pipeline_clear = "3") ELSE "0000" ;
saturate1_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1_pipe,
clk => clk_saturate1_pipeline,
aclr => aclr_saturate1_pipeline,
if_aclr => clear_saturate1_pipeline,
ena => ena_saturate1_pipeline,
dataout => saturate1_out,
async => async_saturate1_pipeline);
async_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clock = "none") ELSE '0' ;
clear_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clear /= "none") ELSE '0' ;
clk_saturate1_pipeline <= '1' WHEN clk(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate1_pipeline <= '1' WHEN (aclr(conv_integer(saturate1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1_pipeline <= '1' WHEN ena(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
saturate1_pipeline_clk <= "0000" WHEN ((saturate1_pipeline_clock = "0") OR (saturate1_pipeline_clock = "none")) ELSE "0001" WHEN (saturate1_pipeline_clock = "1") ELSE "0010" WHEN (saturate1_pipeline_clock = "2") ELSE "0011" WHEN (saturate1_pipeline_clock = "3") ELSE "0000" ;
saturate1_pipeline_aclr <= "0000" WHEN ((saturate1_pipeline_clear = "0") OR (saturate1_pipeline_clear = "none")) ELSE "0001" WHEN (saturate1_pipeline_clear = "1") ELSE "0010" WHEN (saturate1_pipeline_clear = "2") ELSE "0011" WHEN (saturate1_pipeline_clear = "3") ELSE "0000" ;
mode1_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1_pipe,
clk => clk_mode1_pipeline,
aclr => aclr_mode1_pipeline,
if_aclr => clear_mode1_pipeline,
ena => ena_mode1_pipeline,
dataout => mode1_out,
async => async_mode1_pipeline);
async_mode1_pipeline <= '1' WHEN (mode1_pipeline_clock = "none") ELSE '0' ;
clear_mode1_pipeline <= '1' WHEN (mode1_pipeline_clear /= "none") ELSE '0' ;
clk_mode1_pipeline <= '1' WHEN clk(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode1_pipeline <= '1' WHEN (aclr(conv_integer(mode1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1_pipeline <= '1' WHEN ena(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
mode1_pipeline_clk <= "0000" WHEN ((mode1_pipeline_clock = "0") OR (mode1_pipeline_clock = "none")) ELSE "0001" WHEN (mode1_pipeline_clock = "1") ELSE "0010" WHEN (mode1_pipeline_clock = "2") ELSE "0011" WHEN (mode1_pipeline_clock = "3") ELSE "0000" ;
mode1_pipeline_aclr <= "0000" WHEN ((mode1_pipeline_clear = "0") OR (mode1_pipeline_clear = "none")) ELSE "0001" WHEN (mode1_pipeline_clear = "1") ELSE "0010" WHEN (mode1_pipeline_clear = "2") ELSE "0011" WHEN (mode1_pipeline_clear = "3") ELSE "0000" ;
multabsaturate_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate_pipe,
clk => clk_multabsaturate_pipeline,
aclr => aclr_multabsaturate_pipeline,
if_aclr => clear_multabsaturate_pipeline,
ena => ena_multabsaturate_pipeline,
dataout => multabsaturate_out,
async => async_multabsaturate_pipeline);
async_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multabsaturate_pipeline <= '1' WHEN clk(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multabsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multabsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate_pipeline <= '1' WHEN ena(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
multabsaturate_pipeline_clk <= "0000" WHEN ((multabsaturate_pipeline_clock = "0") OR (multabsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clock = "3") ELSE "0000" ;
multabsaturate_pipeline_aclr <= "0000" WHEN ((multabsaturate_pipeline_clear = "0") OR (multabsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clear = "3") ELSE "0000" ;
multcdsaturate_mac_pipeline_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate_pipe,
clk => clk_multcdsaturate_pipeline,
aclr => aclr_multcdsaturate_pipeline,
if_aclr => clear_multcdsaturate_pipeline,
ena => ena_multcdsaturate_pipeline,
dataout => multcdsaturate_out,
async => async_multcdsaturate_pipeline);
async_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multcdsaturate_pipeline <= '1' WHEN clk(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multcdsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate_pipeline <= '1' WHEN ena(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
multcdsaturate_pipeline_clk <= "0000" WHEN ((multcdsaturate_pipeline_clock = "0") OR (multcdsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clock = "3") ELSE "0000" ;
multcdsaturate_pipeline_aclr <= "0000" WHEN ((multcdsaturate_pipeline_clear = "0") OR (multcdsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clear = "3") ELSE "0000" ;
dataa_f <= (others => '0') WHEN (dataa_forced_to_zero = "yes") ELSE dataa ;
datac_f <= (others => '0') WHEN (datac_forced_to_zero = "yes") ELSE datac ;
mac_adder : hardcopyii_mac_out_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
operation_mode => operation_mode)
PORT MAP (
dataa => dataa_f,
datab => datab,
datac => datac_f,
datad => datad,
zeroacc => zeroacc_out,
roundab => round0_out,
roundcd => round1_out,
saturateab => saturate_out,
saturatecd => saturate1_out,
multabsaturate => multabsaturate_out,
multcdsaturate => multcdsaturate_out,
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
feedback => dataout_feedback,
dataout => dataout_map(dataout_width -1 downto 0),
accoverflow => accoverflow_reg);
pin_map_addnsub <= addnsub0_out AND addnsub1_out;
mac_pin_map : hardcopyii_mac_pin_map
GENERIC MAP (
operation_mode => operation_mode,
data_width => tmp_width,
pinmap => "map")
PORT MAP (
datain => dataout_map,
operation => operation,
addnsub => pin_map_addnsub,
dataout => dataout_to_reg);
output0_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => dataout_width,
power_up => '0')
PORT MAP (
data => dataout_to_reg(dataout_width -1 DOWNTO 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_non_dynamic(dataout_width -1 DOWNTO 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
output1_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(35 DOWNTO 18),
clk => clk_output1,
aclr => aclr_output1,
if_aclr => clear_output1,
ena => ena_output1,
dataout => dataout_dynamic1(17 downto 0),
async => async_output1);
async_output1 <= '1' WHEN (output1_clock = "none") ELSE '0' ;
clear_output1 <= '1' WHEN (output1_clear /= "none") ELSE '0' ;
clk_output1 <= '1' WHEN clk(conv_integer(output1_clk)) = '1' ELSE '0' ;
aclr_output1 <= '1' WHEN (aclr(conv_integer(output1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output1 <= '1' WHEN ena(conv_integer(output1_clk)) = '1' ELSE '0' ;
output1_clk <= "0000" WHEN ((output1_clock = "0") OR (output1_clock = "none")) ELSE "0001" WHEN (output1_clock = "1") ELSE "0010" WHEN (output1_clock = "2") ELSE "0011" WHEN (output1_clock = "3") ELSE "0000" ;
output1_aclr <= "0000" WHEN ((output1_clear = "0") OR (output1_clear = "none")) ELSE "0001" WHEN (output1_clear = "1") ELSE "0010" WHEN (output1_clear = "2") ELSE "0011" WHEN (output1_clear = "3") ELSE "0000" ;
output2_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(53 DOWNTO 36),
clk => clk_output2,
aclr => aclr_output2,
if_aclr => clear_output2,
ena => ena_output2,
dataout => dataout_dynamic2(17 downto 0),
async => async_output2);
async_output2 <= '1' WHEN (output2_clock = "none") ELSE '0' ;
clear_output2 <= '1' WHEN (output2_clear /= "none") ELSE '0' ;
clk_output2 <= '1' WHEN clk(conv_integer(output2_clk)) = '1' ELSE '0' ;
aclr_output2 <= '1' WHEN (aclr(conv_integer(output2_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output2 <= '1' WHEN ena(conv_integer(output2_clk)) = '1' ELSE '0' ;
output2_clk <= "0000" WHEN ((output2_clock = "0") OR (output2_clock = "none")) ELSE "0001" WHEN (output2_clock = "1") ELSE "0010" WHEN (output2_clock = "2") ELSE "0011" WHEN (output2_clock = "3") ELSE "0000" ;
output2_aclr <= "0000" WHEN ((output2_clear = "0") OR (output2_clear = "none")) ELSE "0001" WHEN (output2_clear = "1") ELSE "0010" WHEN (output2_clear = "2") ELSE "0011" WHEN (output2_clear = "3") ELSE "0000" ;
output3_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(71 DOWNTO 54),
clk => clk_output3,
aclr => aclr_output3,
if_aclr => clear_output3,
ena => ena_output3,
dataout => dataout_dynamic3(17 downto 0),
async => async_output3);
async_output3 <= '1' WHEN (output3_clock = "none") ELSE '0' ;
clear_output3 <= '1' WHEN (output3_clear /= "none") ELSE '0' ;
clk_output3 <= '1' WHEN clk(conv_integer(output3_clk)) = '1' ELSE '0' ;
aclr_output3 <= '1' WHEN (aclr(conv_integer(output3_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output3 <= '1' WHEN ena(conv_integer(output3_clk)) = '1' ELSE '0' ;
output3_clk <= "0000" WHEN ((output3_clock = "0") OR (output3_clock = "none")) ELSE "0001" WHEN (output3_clock = "1") ELSE "0010" WHEN (output3_clock = "2") ELSE "0011" WHEN (output3_clock = "3") ELSE "0000" ;
output3_aclr <= "0000" WHEN ((output3_clear = "0") OR (output3_clear = "none")) ELSE "0001" WHEN (output3_clear = "1") ELSE "0010" WHEN (output3_clear = "2") ELSE "0011" WHEN (output3_clear = "3") ELSE "0000" ;
output4_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(89 DOWNTO 72),
clk => clk_output4,
aclr => aclr_output4,
if_aclr => clear_output4,
ena => ena_output4,
dataout => dataout_dynamic4(17 downto 0),
async => async_output4);
async_output4 <= '1' WHEN (output4_clock = "none") ELSE '0' ;
clear_output4 <= '1' WHEN (output4_clear /= "none") ELSE '0' ;
clk_output4 <= '1' WHEN clk(conv_integer(output4_clk)) = '1' ELSE '0' ;
aclr_output4 <= '1' WHEN (aclr(conv_integer(output4_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output4 <= '1' WHEN ena(conv_integer(output4_clk)) = '1' ELSE '0' ;
output4_clk <= "0000" WHEN ((output4_clock = "0") OR (output4_clock = "none")) ELSE "0001" WHEN (output4_clock = "1") ELSE "0010" WHEN (output4_clock = "2") ELSE "0011" WHEN (output4_clock = "3") ELSE "0000" ;
output4_aclr <= "0000" WHEN ((output4_clear = "0") OR (output4_clear = "none")) ELSE "0001" WHEN (output4_clear = "1") ELSE "0010" WHEN (output4_clear = "2") ELSE "0011" WHEN (output4_clear = "3") ELSE "0000" ;
output5_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(107 DOWNTO 90),
clk => clk_output5,
aclr => aclr_output5,
if_aclr => clear_output5,
ena => ena_output5,
dataout => dataout_dynamic5(17 downto 0),
async => async_output5);
async_output5 <= '1' WHEN (output5_clock = "none") ELSE '0' ;
clear_output5 <= '1' WHEN (output5_clear /= "none") ELSE '0' ;
clk_output5 <= '1' WHEN clk(conv_integer(output5_clk)) = '1' ELSE '0' ;
aclr_output5 <= '1' WHEN (aclr(conv_integer(output5_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output5 <= '1' WHEN ena(conv_integer(output5_clk)) = '1' ELSE '0' ;
output5_clk <= "0000" WHEN ((output5_clock = "0") OR (output5_clock = "none")) ELSE "0001" WHEN (output5_clock = "1") ELSE "0010" WHEN (output5_clock = "2") ELSE "0011" WHEN (output5_clock = "3") ELSE "0000" ;
output5_aclr <= "0000" WHEN ((output5_clear = "0") OR (output5_clear = "none")) ELSE "0001" WHEN (output5_clear = "1") ELSE "0010" WHEN (output5_clear = "2") ELSE "0011" WHEN (output5_clear = "3") ELSE "0000" ;
output6_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(125 DOWNTO 108),
clk => clk_output6,
aclr => aclr_output6,
if_aclr => clear_output6,
ena => ena_output6,
dataout => dataout_dynamic6(17 downto 0),
async => async_output6);
async_output6 <= '1' WHEN (output6_clock = "none") ELSE '0' ;
clear_output6 <= '1' WHEN (output6_clear /= "none") ELSE '0' ;
clk_output6 <= '1' WHEN clk(conv_integer(output6_clk)) = '1' ELSE '0' ;
aclr_output6 <= '1' WHEN (aclr(conv_integer(output6_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output6 <= '1' WHEN ena(conv_integer(output6_clk)) = '1' ELSE '0' ;
output6_clk <= "0000" WHEN ((output6_clock = "0") OR (output6_clock = "none")) ELSE "0001" WHEN (output6_clock = "1") ELSE "0010" WHEN (output6_clock = "2") ELSE "0011" WHEN (output6_clock = "3") ELSE "0000" ;
output6_aclr <= "0000" WHEN ((output6_clear = "0") OR (output6_clear = "none")) ELSE "0001" WHEN (output6_clear = "1") ELSE "0010" WHEN (output6_clear = "2") ELSE "0011" WHEN (output6_clear = "3") ELSE "0000" ;
output7_reg : hardcopyii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(tmp_width-1 DOWNTO 126),
clk => clk_output7,
aclr => aclr_output7,
if_aclr => clear_output7,
ena => ena_output7,
dataout => dataout_dynamic7(17 downto 0),
async => async_output7);
async_output7 <= '1' WHEN (output7_clock = "none") ELSE '0' ;
clear_output7 <= '1' WHEN (output7_clear /= "none") ELSE '0' ;
clk_output7 <= '1' WHEN clk(conv_integer(output7_clk)) = '1' ELSE '0' ;
aclr_output7 <= '1' WHEN (aclr(conv_integer(output7_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output7 <= '1' WHEN ena(conv_integer(output7_clk)) = '1' ELSE '0' ;
output7_clk <= "0000" WHEN ((output7_clock = "0") OR (output7_clock = "none")) ELSE "0001" WHEN (output7_clock = "1") ELSE "0010" WHEN (output7_clock = "2") ELSE "0011" WHEN (output7_clock = "3") ELSE "0000" ;
output7_aclr <= "0000" WHEN ((output7_clear = "0") OR (output7_clear = "none")) ELSE "0001" WHEN (output7_clear = "1") ELSE "0010" WHEN (output7_clear = "2") ELSE "0011" WHEN (output7_clear = "3") ELSE "0000" ;
tmp_186 <= '1' when (output_clear /= "none") else '0';
tmp_189 <= '1' when (output_clock = "none") else '0';
accoverflow_out_reg : hardcopyii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => accoverflow_reg,
clk => clk_output,
aclr => aclr_output,
if_aclr => tmp_186,
ena => ena_output,
dataout => accoverflow_tmp,
async => tmp_189);
dataout_dynamic(tmp_width-1 DOWNTO 0) <= dataout_dynamic7(17 DOWNTO 0) & dataout_dynamic6(17 DOWNTO 0) & dataout_dynamic5(17 DOWNTO 0) & dataout_dynamic4(17 DOWNTO 0) & dataout_dynamic3(17 DOWNTO 0) & dataout_dynamic2(17 DOWNTO 0) & dataout_dynamic1(17 DOWNTO 0) & dataout_non_dynamic(17 DOWNTO 0) ;
dataout_tmp <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '0')) AND (zeroacc1_out = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '1')) AND (zeroacc1_out = '1')) ELSE "0000" ;
dataout_feedback <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
accoverflow_tmp2 <= accoverflow_tmp;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_lvds_tx_reg : ENTITY is TRUE;
END hardcopyii_lvds_tx_reg;
ARCHITECTURE vital_hardcopyii_lvds_tx_reg of hardcopyii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_hardcopyii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the HardCopy II
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END hardcopyii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of hardcopyii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END hardcopyii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of hardcopyii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyii_lvds_transmitter
--
-- Description : Timing simulation model for the HardCopy II LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) HardCopy II_lvds_tx_parallel_register and
-- 3) HardCopy II_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE std.textio.all;
USE work.hardcopyii_lvds_tx_parallel_register;
USE work.hardcopyii_lvds_tx_out_block;
USE work.hardcopyii_lvds_tx_reg;
ENTITY hardcopyii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end hardcopyii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of hardcopyii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT hardcopyii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT hardcopyii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT hardcopyii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: hardcopyii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: hardcopyii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: hardcopyii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END hardcopyii_lvds_reg;
ARCHITECTURE vital_hardcopyii_lvds_reg of hardcopyii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF hardcopyii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE work.hardcopyii_lvds_rx_fifo_sync_ram;
ENTITY hardcopyii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of hardcopyii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT hardcopyii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : hardcopyii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE work.hardcopyii_lvds_reg;
ENTITY hardcopyii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END hardcopyii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF hardcopyii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT hardcopyii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : hardcopyii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Bit Slip shift register
-- process (clk0_in, bsliprst_in)
-- begin
-- if (bsliprst_in = '1') then
-- elsif (clk0_in'event and clk0_in = '1' and clk0'last_value = '0') then
-- bitslip_arr(0) <= datain_in;
-- for i in 0 to (bitslip_rollover - 1) loop
-- bitslip_arr(i + 1) <= bitslip_arr(i);
-- end loop;
--
-- if (start_corrupt_bits = '1') then
-- num_corrupt_bits <= num_corrupt_bits + 1;
-- end if;
-- if (num_corrupt_bits+1 = 3) then
-- start_corrupt_bits <= '0';
-- end if;
-- end if;
-- end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : hardcopyii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_rx_deser
--
-- Description : Timing simulation model for the HARDCOPYII LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF hardcopyii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the HARDCOPYII LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF hardcopyii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : HARDCOPYII_LVDS_RECEIVER
--
-- Description : Timing simulation model for the HARDCOPYII LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) hardcopyii_lvds_rx_fifo
-- 2) hardcopyii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) hardcopyii_lvds_rx_parallel_reg
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyii_atom_pack.all;
USE work.hardcopyii_lvds_rx_bitslip;
USE work.hardcopyii_lvds_rx_fifo;
USE work.hardcopyii_lvds_rx_deser;
USE work.hardcopyii_lvds_rx_parallel_reg;
USE work.hardcopyii_lvds_reg;
ENTITY hardcopyii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF hardcopyii_lvds_receiver IS
COMPONENT hardcopyii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal first_dpa_lock : std_logic;
signal loadreg_datain : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_int : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal clk0_dly : std_logic;
signal datain_tmp : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
-- INTERNAL PARAMETERS
CONSTANT DPA_CYCLES_TO_LOCK : integer := 2;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpareg1_out WHEN (enable_dpa = "on") ELSE gnd ;
reset_int <= (NOT devpor) OR (NOT devclrn) ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpareset_ipd OR reset_fifo ;
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_dly <= clk0_ipd;
xhdl_12 <= devclrn OR devpor;
-- SUB-MODULE INSTANTIATION
-- input register in non-DPA mode for sampling incoming data
in_reg : hardcopyii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => clk0_dly,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
datain_reg_tmp <= datain_reg;
dpa_clk <= clk0_ipd when (enable_dpa = "on") else '0' ;
dpa_rst <= dpareset_ipd when (enable_dpa = "on") else '0' ;
process (dpa_clk, dpa_rst)
variable dpa_lock_count : integer := 0;
variable dparst_msg : boolean := false;
variable dpa_is_locked : std_logic := '0';
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
if (enable_dpa = "on") then
ASSERT false report "DPA Phase tracking is not modeled, and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the StratixII device handbook for further details." severity warning;
end if;
initial := false;
end if;
if (dpa_rst = '1') then
dpa_is_locked := '0';
dpa_lock_count := 0;
if (not dparst_msg) then
ASSERT false report "DPA was reset" severity note;
dparst_msg := true;
end if;
elsif (dpa_clk'event and dpa_clk = '1') then
dparst_msg := false;
if (dpa_is_locked = '0') then
dpa_lock_count := dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK) then
dpa_is_locked := '1';
ASSERT false report "DPA locked" severity note;
reset_fifo <= '0';
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- ?????????? insert delay to mimic DPLL dataout ?????????
-- DPA registers
dpareg0 : hardcopyii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : hardcopyii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
s_fifo : hardcopyii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => fifo_wclk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= slip_datain_tmp;
s_bitslip_clk <= clk0_dly;
s_bslip : hardcopyii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
--********* DESERIALISER *********//
loaden <= enable0_ipd;
-- only 1 enable signal used for HardCopy II
rxload_reg : hardcopyii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
s_deser : hardcopyii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : hardcopyii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
postdpaserialdataout <= dpareg1_out ;
serialdataout <= datain_ipd;
END vital_arm_lvds_receiver;
-------------------------------------------------------------------------------
--
-- Entity Name : HardCopy II_dll
--
-- Outputs : delayctrlout - current delay chain settings for DQS pin
-- offsetctrlout - current delay offset setting
-- dqsupdate - update enable signal for delay setting latces
-- upndnout - raw output of the phase comparator
--
-- Inputs : clk - reference clock matching in frequency to DQS clock
-- aload - asychronous load signal for delay setting counter
-- when asserted, counter is loaded with initial value
-- offset - offset added/subtracted from delayctrlout
-- upndnin - up/down input port for delay setting counter in
-- use_updndnin mode (user control mode)
-- upndninclkena - clock enable for the delaying setting counter
-- addnsub - dynamically control +/- on offsetctrlout
--
-- Formulae : delay (input_period) = sim_loop_intrinsic_delay +
-- sim_loop_delay_increment * dllcounter;
--
-- Latency : 3 (clk8 cycles) = pc + dc + dr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
USE work.hardcopyii_pllpack.all;
ENTITY hardcopyii_dll is
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "hardcopyii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyii_dll;
ARCHITECTURE vital_armdll of hardcopyii_dll is
-- tuncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal addnsub_in : std_logic := '0';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal dqsupdate_out : std_logic := '1';
signal upndn_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_offsetctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_offset : integer := 0;
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : integer := 0;
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_int : integer := 0;
signal dr_offset_in : integer := 0;
signal dr_dllcount_in : integer := 0;
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_offset : integer := 0;
signal dr_reg_dllcount : integer := 0;
signal dr_delayctrl_out_tmp : integer := 0;
-- delay chain setting counter
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_offset <= dqs_str2int(static_offset);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "offset_only" ELSE "10" WHEN delayctrlout_mode="normal_offset" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
para_offsetctrlout_mode <= "11" WHEN offsetctrlout_mode = "dynamic_addnsub" ELSE "10" WHEN offsetctrlout_mode = "dynamic_sub" ELSE "01" WHEN offsetctrlout_mode = "dynamic_add" ELSE "00";
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetctrl_out <= dr_offsetctrl_out;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_offset_in <= (64 - alt_conv_integer(offset_in)) WHEN ((offset_in /= "000000") AND ((offsetctrlout_mode = "dynamic_addnsub" AND addnsub_in = '0') or (offsetctrlout_mode = "dynamic_sub"))) ELSE
alt_conv_integer(offset_in);
dr_dllcount_in <= dc_dllcount_out;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in;
-- outputs
dr_delayctrl_out <= dll_unsigned2bin(dr_delayctrl_out_tmp);
dr_offsetctrl_out <= dll_unsigned2bin(dr_reg_offset);
dr_delayctrl_out_tmp <= dr_offset_in WHEN (delayctrlout_mode = "offset_only") ELSE
dr_reg_offset WHEN (delayctrlout_mode = "normal_offset") ELSE
dr_reg_dllcount;
dr_delayctrl_int <= para_static_delay_ctrl WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
dr_offsetctrl_int <= para_static_offset WHEN (offsetctrlout_mode = "static") ELSE
dr_offset_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= 0;
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= 0;
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (offsetctrlout_mode = "dynamic_addnsub") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
end if;
elsif (offsetctrlout_mode = "dynamic_sub") then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
elsif (offsetctrlout_mode = "dynamic_add") then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (offsetctrlout_mode = "static") then
if (para_static_offset >= 0) then
if ((para_static_offset < 64) AND (para_static_offset < 64 - dr_delayctrl_int)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 64;
end if;
else
if ((para_static_offset > -63) AND (dr_delayctrl_int > (-1)*para_static_offset)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 0;
end if;
end if;
else
dr_reg_offset <= 14; -- error
end if; -- modes
end if; -- rising clock
end process ; -- generating dr_reg_offset
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount;
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
pc_delay <= pc_var_delay;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, upndn_in, upndninclkena_in, addnsub_in,
delayctrl_out, offsetctrl_out, dqsupdate_out, upndn_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/SRRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetctrlout <= offsetctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_armdll;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyii_termination
--
-- Outputs : incrup and incrdn - output of voltage comparator
-- terminationcontrol - to I/O, cannot wired to PLD
-- terminationcontrolprobe - internal testing outputs only
--
-- Descriptions : the Atom represent On Chip Termination calibration block.
-- The block has no digital outputs that can be observed in PLD.
-- Therefore we do not have simulation model other than entity
-- declaration.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
ENTITY hardcopyii_termination is
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "hardcopyii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END hardcopyii_termination;
ARCHITECTURE vital_armtermination of hardcopyii_termination is
begin
--------------------
-- INPUT PATH DELAYS
--------------------
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
end vital_armtermination;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyii_lcell_hsadder
--
-- Description : HardCopy II LCELL_HSADDER VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyii_atom_pack.all;
entity hardcopyii_lcell_hsadder is
generic (
use_cin1_for_sumout : string := "on";
lpm_type : string := "hardcopyii_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '0';
sumout0 : out std_logic;
sumout1 : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyii_lcell_hsadder : entity is TRUE;
end hardcopyii_lcell_hsadder;
architecture vital_lcell_hsadder of hardcopyii_lcell_hsadder is
attribute VITAL_LEVEL0 of vital_lcell_hsadder : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin0_ipd : std_logic;
signal cin1_ipd : std_logic;
signal cin_sel : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
end block;
cin_sel <= cin0_ipd WHEN (use_cin1_for_sumout = "off") ELSE cin1_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_sel, cin0_ipd)
variable sumout0_VitalGlitchData : VitalGlitchDataType;
variable sumout1_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
-- internal cout variable
variable cmid0 : std_logic;
variable cmid1 : std_logic;
-- output variables
variable sumout0_tmp : std_logic;
variable sumout1_tmp : std_logic;
variable cout_tmp : std_logic;
begin
------------------------
-- Timing Check Section
------------------------
cmid0 := (dataa_ipd AND datab_ipd) OR
(dataa_ipd AND cin0_ipd) OR
(datab_ipd AND cin0_ipd);
cmid1 := (dataa_ipd AND datab_ipd) OR
(dataa_ipd AND cin_sel) OR
(datab_ipd AND cin_sel);
sumout0_tmp := dataa_ipd XOR datab_ipd XOR cin_sel;
sumout1_tmp := datac_ipd XOR datad_ipd XOR cmid1;
cout_tmp := (datac_ipd AND datad_ipd) OR
(datac_ipd AND cmid0) OR
(datad_ipd AND cmid0);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => sumout0,
OutSignalName => "SUMOUT0",
OutTemp => sumout0_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout0, TRUE),
1 => (datac_ipd'last_event, tpd_datab_sumout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_sumout0, TRUE),
3 => (cin1_ipd'last_event, tpd_cin1_sumout0, TRUE)),
GlitchData => sumout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout1,
OutSignalName => "SUMOUT1",
OutTemp => sumout1_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout1, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout1, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout1, TRUE),
4 => (cin0_ipd'last_event, tpd_cin0_sumout1, TRUE),
5 => (cin1_ipd'last_event, tpd_cin1_sumout1, TRUE)),
GlitchData => sumout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout0, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout0, TRUE),
4 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout1, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout1, TRUE),
4 => (cin0_ipd'last_event, tpd_cin0_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_hsadder;
| gpl-3.0 | 7b604a02ec2d926fc210c1814caaaadf | 0.495515 | 3.874184 | false | false | false | false |
keith-epidev/md2x | build/code/timer.vhdl | 1 | 2,069 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity timer is
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
output : out std_logic_vector(26 downto 0)
);
end timer;
architecture arch of timer is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
component modn is
generic(
n:integer := 4
);
port (
clk : in std_logic;
inc : in std_logic;
enable: in std_logic;
reset: in std_logic;
overflow: out std_logic;
output : out std_logic_vector(f_log2(n)-1 downto 0)
);
end component;
signal timer_clk: std_logic;
signal seconds_hundrendth_overflow : std_logic;
signal seconds_tenths_overflow : std_logic;
signal seconds_ones_overflow : std_logic;
signal seconds_units_overflow : std_logic;
signal seconds_tens_overflow : std_logic;
signal mins_units_overflow : std_logic;
signal mins_tens_overflow : std_logic;
begin
p1: pulser generic map(delay=>50000) port map(clk,enable,timer_clk);
seconds_hundredth: modn generic map(n=>10) port map(clk,timer_clk,enable,reset,seconds_hundrendth_overflow,output(3 downto 0));
seconds_tenths: modn generic map(n=>10) port map(clk,seconds_hundrendth_overflow,enable,reset,seconds_tenths_overflow,output(7 downto 4));
seconds_ones: modn generic map(n=>10) port map(clk,seconds_tenths_overflow,enable,reset,seconds_ones_overflow,output(11 downto 8));
seconds_units: modn generic map(n=>10) port map(clk,seconds_ones_overflow,enable,reset,seconds_units_overflow,output(15 downto 12));
seconds_tens: modn generic map(n=>6) port map(clk,seconds_units_overflow,enable,reset,seconds_tens_overflow,output(18 downto 16)); --padd '0'
mins_units: modn generic map(n=>10) port map(clk,seconds_tens_overflow,enable,reset,mins_units_overflow,output(23 downto 20));
mins_tens: modn generic map(n=>6) port map(clk,mins_units_overflow,enable,reset,open,output(26 downto 24)); --padd '0'
end arch;
| gpl-2.0 | 9b9fb01eb9916594d1be9cb4f7413933 | 0.722088 | 2.959943 | false | false | false | false |
freecores/t400 | rtl/tech/t400_tech_comp_pack-p.vhd | 1 | 1,771 | -------------------------------------------------------------------------------
--
-- $Id: t400_tech_comp_pack-p.vhd,v 1.2 2006-06-05 20:31:00 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t400_tech_comp_pack is
component t400_por
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end component;
component generic_ram
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end component;
component generic_ram_ena
generic (
addr_width_g : integer := 10;
data_width_g : integer := 8
);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(addr_width_g-1 downto 0);
we_i : in std_logic;
ena_i : in std_logic;
d_i : in std_logic_vector(data_width_g-1 downto 0);
d_o : out std_logic_vector(data_width_g-1 downto 0)
);
end component;
end t400_tech_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 24f4dc165dea209b40bd79328dfe30f3 | 0.47205 | 3.418919 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/ALU.vhd | 1 | 2,917 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 19:03:40 09/24/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port (
En: in STD_LOGIC;
LM: in STD_LOGIC; --Logical operation mode
A : in STD_LOGIC_VECTOR (11 downto 0);
B : in STD_LOGIC_VECTOR (11 downto 0);
Func: in STD_LOGIC_VECTOR (3 downto 0);
Output : out STD_LOGIC_VECTOR (11 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process (En, A, B, Func, LM)
begin
if(En = '1') then
if(LM = '0') then
if(Func = "0000") then
Output <= (A) + (B);
elsif(Func = "0001") then
Output <= (A) - (B);
elsif(Func = "0010") then
Output <= (B) - (A);
elsif(Func = "0011") then
Output <= (B) - 1;
elsif(Func = "0100") then
Output <= (B) + 1;
elsif(Func = "0101") then
Output <= 0 - (B);
elsif(Func = "0110") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
elsif(Func = "0111") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
else
if(Func = "0000") then
Output <= not B;
elsif(Func = "0001") then
Output <= A nor B;
elsif(Func = "0010") then
Output <= (not B) and A;
elsif(Func = "0011") then
Output <= "000000000000";
elsif(Func = "0100") then
Output <= B nand A;
elsif(Func = "0101") then
Output <= not A;
elsif(Func = "0110") then
Output <= B xor A;
elsif(Func = "0111") then
Output <= B and (not A);
elsif(Func = "1000") then
Output <= (not B) or A;
elsif(Func = "1001") then
Output <= B xnor A;
elsif(Func = "1010") then
Output <= A;
elsif(Func = "1011") then
Output <= B and A;
elsif(Func = "1100") then
Output <= "000000000001";
elsif(Func = "1101") then
Output <= B or (not A);
elsif(Func = "1110") then
Output <= B or A;
elsif(Func = "1111") then
if(B = 0) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
end if;
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
end process;
end Behavioral;
| bsd-3-clause | 70d1da31b15656222333dce2d68e23ae | 0.513884 | 3.153514 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/phpe_mod.vhd | 1 | 15,340 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity PHPE_MOD is
generic (
-- IO-REQ: 15 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000110";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
CLK100: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of PHPE_MOD is
signal wb_data_mux : std_logic_vector(31 downto 0);
signal pe_reg_top : std_logic_vector(15 downto 0);
signal pe_reg_scan : std_logic_vector(15 downto 0);
signal pe_reg_disch : std_logic_vector(15 downto 0);
signal pe_reg_take : std_logic_vector(15 downto 0);
signal pe_pos_capt_a : std_logic;
signal pe_pos_cnt_a : std_logic_vector(31 downto 0);
signal pe_pos_sin_a : std_logic_vector(31 downto 0);
signal pe_pos_cos_a : std_logic_vector(31 downto 0);
signal pe_area_cnt_a : std_logic_vector(31 downto 0);
signal pe_area_sin_a : std_logic_vector(31 downto 0);
signal pe_area_cos_a : std_logic_vector(31 downto 0);
signal pe_area_pol_a : std_logic;
signal pe_area_flag_a : std_logic;
signal pe_area_state_a : std_logic;
signal pe_pos_capt_b : std_logic;
signal pe_pos_cnt_b : std_logic_vector(31 downto 0);
signal pe_pos_sin_b : std_logic_vector(31 downto 0);
signal pe_pos_cos_b : std_logic_vector(31 downto 0);
signal pe_area_cnt_b : std_logic_vector(31 downto 0);
signal pe_area_sin_b : std_logic_vector(31 downto 0);
signal pe_area_cos_b : std_logic_vector(31 downto 0);
signal pe_area_pol_b : std_logic;
signal pe_area_flag_b : std_logic;
signal pe_area_state_b : std_logic;
signal pe_scan_cnt : std_logic_vector(15 downto 0);
signal pe_scan_cnt_ena : std_logic;
signal pe_scan_cnt_top : std_logic;
signal pe_scan_cnt_disch : std_logic;
signal pe_scan_cnt_take : std_logic;
signal pe_scan_cnt_scan : std_logic;
signal pe_scan_ovs_top : std_logic;
signal pe_scan_ovs : std_logic;
signal pe_trars_cnt : std_logic_vector(4 downto 0);
signal pe_trars_cnt_bot : std_logic;
signal pe_trars_cnt_top : std_logic;
signal pe_scan : std_logic;
signal pe_disch : std_logic;
signal pe_disch_sync : std_logic_vector(2 downto 0);
signal pe_disch_int : std_logic;
signal pe_disch_ack : std_logic;
signal pe_disch_ack_sync : std_logic_vector(1 downto 0);
signal pe_disch_ack_int : std_logic;
signal pe_take : std_logic;
signal pe_take_sync : std_logic_vector(2 downto 0);
signal pe_take_int : std_logic;
signal pe_take_ack : std_logic;
signal pe_take_ack_sync : std_logic_vector(1 downto 0);
signal pe_take_ack_int : std_logic;
signal pe_trars : std_logic;
signal pe_sin : signed(15 downto 0);
signal pe_cos : signed(15 downto 0);
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR, WB_STB_RD, pe_reg_top, pe_reg_scan, pe_reg_disch, pe_reg_take,
pe_pos_cnt_a, pe_pos_sin_a, pe_pos_cos_a, pe_area_cnt_a, pe_area_sin_a, pe_area_cos_a, pe_area_pol_a, pe_area_flag_a, pe_area_state_a,
pe_pos_cnt_b, pe_pos_sin_b, pe_pos_cos_b, pe_area_cnt_b, pe_area_sin_b, pe_area_cos_b, pe_area_pol_b, pe_area_flag_b, pe_area_state_b)
begin
pe_pos_capt_a <= '0';
pe_pos_capt_b <= '0';
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= (others => '0');
wb_data_mux(0) <= pe_area_pol_a;
wb_data_mux(1) <= pe_area_state_a;
wb_data_mux(2) <= pe_area_flag_a;
wb_data_mux(8) <= pe_area_pol_b;
wb_data_mux(9) <= pe_area_state_b;
wb_data_mux(10) <= pe_area_flag_b;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux(15 downto 0) <= pe_reg_top;
wb_data_mux(31 downto 16) <= pe_reg_scan;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux(15 downto 0) <= pe_reg_disch;
wb_data_mux(31 downto 16) <= pe_reg_take;
when WB_ADDR_OFFSET + 3 =>
pe_pos_capt_a <= WB_STB_RD;
wb_data_mux <= pe_pos_cnt_a;
when WB_ADDR_OFFSET + 4 =>
wb_data_mux <= pe_pos_sin_a;
when WB_ADDR_OFFSET + 5 =>
wb_data_mux <= pe_pos_cos_a;
when WB_ADDR_OFFSET + 6 =>
wb_data_mux <= pe_area_cnt_a;
when WB_ADDR_OFFSET + 7 =>
wb_data_mux <= pe_area_sin_a;
when WB_ADDR_OFFSET + 8 =>
wb_data_mux <= pe_area_cos_a;
when WB_ADDR_OFFSET + 9 =>
pe_pos_capt_b <= WB_STB_RD;
wb_data_mux <= pe_pos_cnt_b;
when WB_ADDR_OFFSET + 10 =>
wb_data_mux <= pe_pos_sin_b;
when WB_ADDR_OFFSET + 11 =>
wb_data_mux <= pe_pos_cos_b;
when WB_ADDR_OFFSET + 12 =>
wb_data_mux <= pe_area_cnt_b;
when WB_ADDR_OFFSET + 13 =>
wb_data_mux <= pe_area_sin_b;
when WB_ADDR_OFFSET + 14 =>
wb_data_mux <= pe_area_cos_b;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
pe_reg_top <= (others => '0');
pe_reg_scan <= (others => '0');
pe_reg_disch <= (others => '0');
pe_reg_take <= (others => '0');
pe_area_pol_a <= '0';
pe_area_pol_b <= '0';
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
pe_area_pol_a <= WB_DATA_IN(0);
pe_area_pol_b <= WB_DATA_IN(8);
when WB_ADDR_OFFSET + 1 =>
pe_reg_top <= WB_DATA_IN(15 downto 0);
pe_reg_scan <= WB_DATA_IN(31 downto 16);
when WB_ADDR_OFFSET + 2 =>
pe_reg_disch <= WB_DATA_IN(15 downto 0);
pe_reg_take <= WB_DATA_IN(31 downto 16);
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- cycle counter
----------------------------------------------------------
P_PE_SCAN_CNT : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_scan_cnt <= (others => '0');
elsif rising_edge(wb_clk) then
if pe_scan_cnt_top = '1' then
pe_scan_cnt <= (others => '0');
else
pe_scan_cnt <= pe_scan_cnt + 1;
end if;
end if;
end process;
pe_scan_cnt_ena <= '1' when pe_reg_top /= 0 else '0';
pe_scan_cnt_top <= '1' when pe_scan_cnt = pe_reg_top else '0';
pe_scan_cnt_disch <= '1' when pe_scan_cnt = pe_reg_disch else '0';
pe_scan_cnt_take <= '1' when pe_scan_cnt = pe_reg_take else '0';
pe_scan_cnt_scan <= '1' when pe_scan_cnt = pe_reg_scan else '0';
pe_scan_ovs_top <= '1' when pe_scan_cnt = ("0" & pe_reg_top(15 downto 1)) else '0';
pe_scan_ovs <= pe_scan_cnt_top or pe_scan_ovs_top;
P_PE_TRARS_CNT : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_trars_cnt <= (others => '0');
elsif rising_edge(wb_clk) then
if pe_scan_cnt_ena = '0' then
pe_trars_cnt <= (others => '0');
elsif pe_scan_ovs = '1' then
if pe_trars_cnt_top = '1' then
if pe_scan_cnt_top = '1' then
pe_trars_cnt <= (others => '0');
end if;
else
pe_trars_cnt <= pe_trars_cnt + 1;
end if;
end if;
end if;
end process;
pe_trars_cnt_bot <= '1' when pe_trars_cnt = "00000" else '0';
pe_trars_cnt_top <= '1' when pe_trars_cnt = "10011" else '0';
pe_trars <= pe_trars_cnt(4);
----------------------------------------------------------
--- pulse generator
----------------------------------------------------------
P_PE_DISCH : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_disch <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_disch = '1' then
pe_disch <= '1';
elsif pe_disch_ack = '1' then
pe_disch <= '0';
end if;
end if;
end process;
P_PE_TAKE : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_take <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_take = '1' then
pe_take <= '1';
elsif pe_take_ack = '1' then
pe_take <= '0';
end if;
end if;
end process;
P_PE_SCAN : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_scan <= '0';
elsif rising_edge(wb_clk) then
if pe_scan_cnt_scan = '1' then
pe_scan <= '1';
end if;
if pe_scan_cnt_top = '1' then
pe_scan <= '0';
end if;
end if;
end process;
----------------------------------------------------------
--- whichbone <-> pulse with count syncer
----------------------------------------------------------
P_PE_SYNC_WB : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
pe_disch_ack_sync <= (others => '0');
pe_take_ack_sync <= (others => '0');
elsif rising_edge(wb_clk) then
pe_disch_ack_sync <= pe_disch_ack_int & pe_disch_ack_sync(1);
pe_take_ack_sync <= pe_take_ack_int & pe_take_ack_sync(1);
end if;
end process;
pe_disch_ack <= pe_disch_ack_sync(0);
pe_take_ack <= pe_take_ack_sync(0);
P_PE_SYNC_INT : process(wb_rst, clk100)
begin
if wb_rst = '1' then
pe_disch_sync <= (others => '0');
pe_take_sync <= (others => '0');
elsif rising_edge(clk100) then
pe_disch_sync <= pe_disch & pe_disch_sync(2 downto 1);
pe_take_sync <= pe_take & pe_take_sync(2 downto 1);
end if;
end process;
pe_disch_int <= '1' when pe_disch_sync(1 downto 0) = "10" else '0';
pe_disch_ack_int <= pe_disch_sync(0);
pe_take_int <= '1' when pe_take_sync(1 downto 0) = "10" else '0';
pe_take_ack_int <= pe_take_sync(0);
----------------------------------------------------------
--- sincos generator
----------------------------------------------------------
P_PE_SIN_COS : process(pe_trars_cnt)
begin
case pe_trars_cnt is
when "00000" =>
pe_sin <= conv_signed( 0, pe_sin'length);
pe_cos <= conv_signed( 32767, pe_cos'length);
when "00001" =>
pe_sin <= conv_signed( 10126, pe_sin'length);
pe_cos <= conv_signed( 31163, pe_cos'length);
when "00010" =>
pe_sin <= conv_signed( 19260, pe_sin'length);
pe_cos <= conv_signed( 26509, pe_cos'length);
when "00011" =>
pe_sin <= conv_signed( 26509, pe_sin'length);
pe_cos <= conv_signed( 19260, pe_cos'length);
when "00100" =>
pe_sin <= conv_signed( 31163, pe_sin'length);
pe_cos <= conv_signed( 10126, pe_cos'length);
when "00101" =>
pe_sin <= conv_signed( 32767, pe_sin'length);
pe_cos <= conv_signed( 0, pe_cos'length);
when "00110" =>
pe_sin <= conv_signed( 31163, pe_sin'length);
pe_cos <= conv_signed(-10126, pe_cos'length);
when "00111" =>
pe_sin <= conv_signed( 26509, pe_sin'length);
pe_cos <= conv_signed(-19260, pe_cos'length);
when "01000" =>
pe_sin <= conv_signed( 19260, pe_sin'length);
pe_cos <= conv_signed(-26509, pe_cos'length);
when "01001" =>
pe_sin <= conv_signed( 10126, pe_sin'length);
pe_cos <= conv_signed(-31163, pe_cos'length);
when "01010" =>
pe_sin <= conv_signed( 0, pe_sin'length);
pe_cos <= conv_signed(-32767, pe_cos'length);
when "01011" =>
pe_sin <= conv_signed(-10126, pe_sin'length);
pe_cos <= conv_signed(-31163, pe_cos'length);
when "01100" =>
pe_sin <= conv_signed(-19260, pe_sin'length);
pe_cos <= conv_signed(-26509, pe_cos'length);
when "01101" =>
pe_sin <= conv_signed(-26509, pe_sin'length);
pe_cos <= conv_signed(-19260, pe_cos'length);
when "01110" =>
pe_sin <= conv_signed(-31163, pe_sin'length);
pe_cos <= conv_signed(-10126, pe_cos'length);
when "01111" =>
pe_sin <= conv_signed(-32767, pe_sin'length);
pe_cos <= conv_signed( 0, pe_cos'length);
when "10000" =>
pe_sin <= conv_signed(-31163, pe_sin'length);
pe_cos <= conv_signed( 10126, pe_cos'length);
when "10001" =>
pe_sin <= conv_signed(-26509, pe_sin'length);
pe_cos <= conv_signed( 19260, pe_cos'length);
when "10010" =>
pe_sin <= conv_signed(-19260, pe_sin'length);
pe_cos <= conv_signed( 26509, pe_cos'length);
when others =>
pe_sin <= conv_signed(-10126, pe_sin'length);
pe_cos <= conv_signed( 31163, pe_cos'length);
end case;
end process;
----------------------------------------------------------
--- channel instances
----------------------------------------------------------
U_PECHAN_A: entity work.PHPE_CHAN
port map (
RESET => WB_RST,
CLK100 => CLK100,
WB_CLK => WB_CLK,
TRAMS => not SV(8),
AREA => not SV(10),
pe_scan_cnt_top => pe_scan_cnt_top,
pe_scan_ovs_top => pe_scan_ovs_top,
pe_scan_ovs => pe_scan_ovs,
pe_trars_cnt_bot => pe_trars_cnt_bot,
pe_disch_int => pe_disch_int,
pe_take_int => pe_take_int,
pe_sin => pe_sin,
pe_cos => pe_cos,
pe_pos_capt => pe_pos_capt_a,
pe_pos_cnt => pe_pos_cnt_a,
pe_pos_sin => pe_pos_sin_a,
pe_pos_cos => pe_pos_cos_a,
pe_area_pol => pe_area_pol_a,
pe_area_flag => pe_area_flag_a,
pe_area_state => pe_area_state_a,
pe_area_cnt => pe_area_cnt_a,
pe_area_sin => pe_area_sin_a,
pe_area_cos => pe_area_cos_a
);
U_PECHAN_B: entity work.PHPE_CHAN
port map (
RESET => WB_RST,
CLK100 => CLK100,
WB_CLK => WB_CLK,
TRAMS => not SV(7),
AREA => not SV(9),
pe_scan_cnt_top => pe_scan_cnt_top,
pe_scan_ovs_top => pe_scan_ovs_top,
pe_scan_ovs => pe_scan_ovs,
pe_trars_cnt_bot => pe_trars_cnt_bot,
pe_disch_int => pe_disch_int,
pe_take_int => pe_take_int,
pe_sin => pe_sin,
pe_cos => pe_cos,
pe_pos_capt => pe_pos_capt_b,
pe_pos_cnt => pe_pos_cnt_b,
pe_pos_sin => pe_pos_sin_b,
pe_pos_cos => pe_pos_cos_b,
pe_area_pol => pe_area_pol_b,
pe_area_flag => pe_area_flag_b,
pe_area_state => pe_area_state_b,
pe_area_cnt => pe_area_cnt_b,
pe_area_sin => pe_area_sin_b,
pe_area_cos => pe_area_cos_b
);
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
SV(3) <= '0';
SV(4) <= '0';
SV(5) <= pe_scan_cnt_ena and (not pe_scan);
SV(6) <= pe_scan_cnt_ena and (not pe_trars);
end;
| gpl-3.0 | cfe567e8b7ff3d1f21d5c8f824252ce2 | 0.531943 | 2.91635 | false | false | false | false |
alvieboy/xtc-base | tx_unit_sim.vhd | 1 | 5,222 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.pty.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal lixo: integer;
begin
intx_o <= '0';
busy_o <= '0';--load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
variable txint: integer;
variable txresult: integer;
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
else -- reset_i='0'
if load_i='1' then
--report "kkkk";
txint := conv_integer( unsigned(datai_i) );
txresult := pty_transmit(txint);
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
process
variable c: integer;
begin
c := pty_initialize;
wait;
end process;
end architecture Behaviour;
| bsd-3-clause | 787ca151d6fe8f8600a525db5eeae661 | 0.324397 | 5.29078 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/220pack.vhd | 1 | 23,741 | -------------------------------------------------------------------------------
-- LPM 220 Component Declaration Package (Support string type generic)
-- These models are based on LPM version 220 (EIA-IS103 October 1998).
-------------------------------------------------------------------------------
-- Assumptions:
--
-- LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,
-- LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is
-- string "UNUSED".
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package LPM_COMPONENTS is
constant L_CONSTANT : string := "LPM_CONSTANT";
constant L_INV : string := "LPM_INV";
constant L_AND : string := "LPM_AND";
constant L_OR : string := "LPM_OR";
constant L_XOR : string := "LPM_XOR";
constant L_BUSTRI : string := "LPM_BUSTRI";
constant L_MUX : string := "LPM_MUX";
constant L_DECODE : string := "LPM_DECODE";
constant L_CLSHIFT : string := "LPM_CLSHIFT";
constant L_ADD_SUB : string := "LPM_ADD_SUB";
constant L_COMPARE : string := "LPM_COMPARE";
constant L_MULT : string := "LPM_MULT";
constant L_DIVIDE : string := "LPM_DIVIDE";
constant L_ABS : string := "LPM_ABS";
constant L_COUNTER : string := "LPM_COUNTER";
constant L_LATCH : string := "LPM_LATCH";
constant L_FF : string := "LPM_FF";
constant L_SHIFTREG : string := "LPM_SHIFTREG";
constant L_RAM_DQ : string := "LPM_RAM_DQ";
constant L_RAM_DP : string := "LPM_RAM_DP";
constant L_RAM_IO : string := "LPM_RAM_IO";
constant L_ROM : string := "LPM_ROM";
constant L_FIFO : string := "LPM_FIFO";
constant L_FIFO_DC : string := "LPM_FIFO_DC";
constant L_TTABLE : string := "LPM_TTABLE";
constant L_FSM : string := "LPM_FSM";
constant L_INPAD : string := "LPM_INPAD";
constant L_OUTPAD : string := "LPM_OUTPAD";
constant L_BIPAD : string := "LPM_BIPAD";
type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
------------------------------------------------------------------------
-- GATES ---------------------------------------------------------------
------------------------------------------------------------------------
component LPM_CONSTANT
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_CVALUE : natural;
LPM_STRENGTH : string := "UNUSED";
LPM_TYPE : string := L_CONSTANT;
LPM_HINT : string := "UNUSED");
port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_INV
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_INV;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_AND
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_AND;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_OR
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_OR;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_XOR
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_TYPE : string := L_XOR;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_BUSTRI
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_BUSTRI;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLEDT : in std_logic := '1';
ENABLETR : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
TRIDATA : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_MUX
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_SIZE : natural; -- MUST be greater than 0
LPM_WIDTHS : natural; -- MUST be greater than 0
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_MUX;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_2D(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SEL : in std_logic_vector(LPM_WIDTHS-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_DECODE
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_DECODES : natural; -- MUST be greater than 0
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_DECODE;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
ACLR : in std_logic := '0';
ENABLE : in std_logic := '1';
EQ : out std_logic_vector(LPM_DECODES-1 downto 0));
end component;
component LPM_CLSHIFT
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHDIST : natural; -- MUST be greater than 0
LPM_SHIFTTYPE : string := "LOGICAL";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_CLSHIFT;
LPM_HINT : string := "UNUSED");
port (DATA : in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
DISTANCE : in STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 downto 0);
DIRECTION : in STD_LOGIC := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
ACLR : in std_logic := '0';
RESULT : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
UNDERFLOW : out STD_LOGIC;
OVERFLOW : out STD_LOGIC);
end component;
------------------------------------------------------------------------
-- ARITHMETIC COMPONENTS -----------------------------------------------
------------------------------------------------------------------------
component LPM_ADD_SUB
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_DIRECTION : string := "UNUSED";
LPM_REPRESENTATION: string := "SIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_ADD_SUB;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := 'Z';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end component;
component LPM_COMPARE
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_COMPARE;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end component;
component LPM_MULT
generic(LPM_WIDTHA : natural; -- MUST be greater than 0
LPM_WIDTHB : natural; -- MUST be greater than 0
LPM_WIDTHS : natural := 1;
LPM_WIDTHP : natural; -- MUST be greater than 0
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_MULT;
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
component LPM_DIVIDE
generic(LPM_WIDTHN : natural; -- MUST be greater than 0
LPM_WIDTHD : natural; -- MUST be greater than 0
LPM_NREPRESENTATION : string := "UNSIGNED";
LPM_DREPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE : string := L_DIVIDE;
LPM_HINT : string := "LPM_REMAINDERPOSITIVE=TRUE");
port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0);
DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0);
REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0));
end component;
component LPM_ABS
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE: string := L_ABS;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
OVERFLOW : out std_logic);
end component;
component LPM_COUNTER
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_MODULUS : natural := 0;
LPM_DIRECTION : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_PORT_UPDOWN : string := "PORT_CONNECTIVITY";
LPM_TYPE: string := L_COUNTER;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS => '0');
CLOCK : in std_logic ;
CLK_EN : in std_logic := '1';
CNT_EN : in std_logic := '1';
UPDOWN : in std_logic := '1';
SLOAD : in std_logic := '0';
SSET : in std_logic := '0';
SCLR : in std_logic := '0';
ALOAD : in std_logic := '0';
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
CIN : in std_logic := '1';
COUT : out std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
------------------------------------------------------------------------
-- STORAGE COMPONENTS --------------------------------------------------
------------------------------------------------------------------------
component LPM_LATCH
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_TYPE: string := L_LATCH;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
GATE : in std_logic;
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
ACONST : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_FF
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_FFTYPE: string := "DFF";
LPM_TYPE: string := L_FF;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '1');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SLOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ALOAD : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_SHIFTREG
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_DIRECTION: string := "UNUSED";
LPM_TYPE: string := L_SHIFTREG;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SHIFTIN : in std_logic := '1';
LOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
SHIFTOUT : out std_logic);
end component;
component LPM_RAM_DQ
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_DQ;
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_RAM_DP
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_DP;
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_RAM_IO
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_IO;
INTENDED_DEVICE_FAMILY : string := "UNUSED";
USE_EAB : string := "ON";
LPM_HINT : string := "UNUSED");
port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
OUTENAB : in STD_LOGIC := 'Z';
WE : in STD_LOGIC := 'Z';
DIO : inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;
component LPM_ROM
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := L_ROM;
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end component;
component LPM_FIFO
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHU : natural := 1; -- MUST be greater than 0
LPM_NUMWORDS : natural; -- MUST be greater than 0
LPM_SHOWAHEAD : string := "OFF";
LPM_TYPE : string := L_FIFO;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic;
WRREQ : in std_logic;
RDREQ : in std_logic;
ACLR : in std_logic := '0';
SCLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
FULL : out std_logic;
EMPTY : out std_logic);
end component;
component LPM_FIFO_DC
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHU : natural := 1; -- MUST be greater than 0
LPM_NUMWORDS : natural; -- MUST be greater than 0
LPM_SHOWAHEAD : string := "OFF";
LPM_TYPE : string := L_FIFO_DC;
UNDERFLOW_CHECKING : string := "ON";
OVERFLOW_CHECKING : string := "ON";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRCLOCK : in std_logic;
RDCLOCK : in std_logic;
WRREQ : in std_logic;
RDREQ : in std_logic;
ACLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
WRUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
RDUSEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
WRFULL : out std_logic;
RDFULL : out std_logic;
WREMPTY : out std_logic;
RDEMPTY : out std_logic);
end component;
------------------------------------------------------------------------
-- TABLE PRIMITIVES ----------------------------------------------------
------------------------------------------------------------------------
component LPM_TTABLE
generic(LPM_WIDTHIN : natural; -- MUST be greater than 0
LPM_WIDTHOUT : natural; -- MUST be greater than 0
LPM_FILE : string;
LPM_TRUTHTYPE : string := "FD";
LPM_TYPE : string := L_TTABLE;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTHIN-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;
component LPM_FSM
generic(LPM_WIDTHIN : natural; -- MUST be greater than 0
LPM_WIDTHOUT : natural; -- MUST be greater than 0
LPM_WIDTHS : natural := 1; -- MUST be greater than 0
LPM_FILE : string ;
LPM_PVALUE : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_TRUTHTYPE : string := "FD";
LPM_TYPE : string := L_FSM;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTHIN-1 downto 0);
CLOCK : in std_logic;
ASET : in std_logic := '0';
TESTENAB : in std_logic := '0';
TESTIN : in std_logic := '0';
TESTOUT : out std_logic;
STATE : out std_logic_vector(LPM_WIDTHS-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTHOUT-1 downto 0));
end component;
------------------------------------------------------------------------
-- PAD PRIMITIVES ------------------------------------------------------
------------------------------------------------------------------------
component LPM_INPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_INPAD;
LPM_HINT : string := "UNUSED");
port (PAD : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_OUTPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_OUTPAD;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
PAD : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
component LPM_BIPAD
generic(LPM_WIDTH : natural; -- MUST be greater than 0
LPM_TYPE : string := L_BIPAD;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ENABLE : in std_logic;
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
PAD : inout std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
end;
| gpl-3.0 | ce27fb035640511706d4db365c62972e | 0.480645 | 4.168745 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_burst_converter_v1_00_a/hdl/vhdl/reconos_memif_burst_converter.vhd | 2 | 7,327 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF FIFO - FIFO implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The burst converter splits burst transfers into smaller
-- requests which do not go over a page border. This is
-- needed because the MMU does not deal with this problem.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_memif_burst_converter is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
-- page size in bytes
C_PAGE_SIZE : integer := 4096;
-- maximal possible burst size supported
-- by the memory-bus in bytes
-- this MUST be smaller or equal than the page size
C_MAX_BURST_SIZE : integer := 1024
);
port (
-- Input FIFO ports from the transaction control
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to the MMU
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Burst converter ports
BCONV_Clk : in std_logic;
BCONV_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of BCONV_Clk : signal is "Clk";
attribute SIGIS of BCONV_Rst : signal is "Rst";
end entity reconos_memif_burst_converter;
architecture implementation of reconos_memif_burst_converter is
constant C_PAGE_OFFSET_WIDTH : integer := clog2(C_PAGE_SIZE);
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
-- Burst converter signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR, CALC_CHUNK, WRITE_CMD, WRITE_ADDR);
signal state : STATE_TYPE;
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal clk : std_logic;
signal rst : std_logic;
-- calculates remaining bytes to page border
function calc_bytes_rem_page (
start_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0)
) return std_logic_vector is
variable page_offset : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
page_offset := (others => '0');
page_offset(C_PAGE_OFFSET_WIDTH - 1 downto 0) := start_addr(C_PAGE_OFFSET_WIDTH - 1 downto 0);
return C_PAGE_SIZE - page_offset;
end function calc_bytes_rem_page;
-- calculates the size of the chunk from start_addr to max_end_addr
function calc_chunk_length (
start_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
bytes_rem : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
bytes_rem_page : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0)
) return std_logic_vector is
variable length_byte : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
length_byte := bytes_rem_page;
if bytes_rem < length_byte then
length_byte := bytes_rem;
end if;
if C_MAX_BURST_SIZE < length_byte then
length_byte := CONV_STD_LOGIC_VECTOR(C_MAX_BURST_SIZE, C_MEMIF_LENGTH_WIDTH);
end if;
return length_byte;
end function calc_chunk_length;
begin
clk <= BCONV_Clk;
rst <= BCONV_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
burst_converter_proc : process(clk,rst) is
variable bconv_cmd : std_logic_vector(C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable bconv_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable bconv_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
variable bconv_bytes_rem : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable bconv_bytes_rem_page : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
elsif rising_edge(clk) then
case state is
when WAIT_REQUEST =>
-- set RE of FIFO, because of the FIFO specification this is totally fine
ctrl_in_re <= '1';
state <= READ_CMD;
when READ_CMD =>
if CTRL_FIFO_In_Empty = '0' then
-- read cmd and length
ctrl_cmd <= CTRL_FIFO_In_Data(C_CTRL_FIFO_WIDTH - 1 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
bconv_cmd := CTRL_FIFO_In_Data(C_CTRL_FIFO_WIDTH - 1 downto C_MEMIF_LENGTH_WIDTH);
bconv_bytes_rem := CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 2) & "00";
state <= READ_ADDR;
end if;
when READ_ADDR =>
if CTRL_FIFO_In_Empty = '0' then
-- read address
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
bconv_addr := CTRL_FIFO_In_Data;
bconv_bytes_rem_page := calc_bytes_rem_page(bconv_addr);
state <= CALC_CHUNK;
end if;
when CALC_CHUNK =>
bconv_length := calc_chunk_length(bconv_addr, bconv_bytes_rem, bconv_bytes_rem_page);
ctrl_out_empty <= '0';
ctrl_out_data <= bconv_cmd & bconv_length;
ctrl_out_fill <= X"0001";
state <= WRITE_CMD;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_data <= bconv_addr;
ctrl_out_fill <= X"0000";
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
bconv_addr := bconv_addr + bconv_length;
bconv_bytes_rem := bconv_bytes_rem - bconv_length;
bconv_bytes_rem_page := calc_bytes_rem_page(bconv_addr);
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
ctrl_out_data <= (others => '0');
if or_reduce(bconv_bytes_rem) = '0' then
-- last chunk was read and we have nothing more
state <= WAIT_REQUEST;
else
state <= CALC_CHUNK;
end if;
end if;
end case;
end if;
end process burst_converter_proc;
end architecture implementation;
| gpl-2.0 | 37ecfc01de4bc63ec8c8ceecc94cd202 | 0.598144 | 3.109508 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyiv_components.vhd | 1 | 107,620 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiv_atom_pack.all;
package hardcopyiv_components is
--
-- hardcopyiv_jtag
--
COMPONENT hardcopyiv_jtag
generic (
lpm_type : string := "hardcopyiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- hardcopyiv_lcell_comb
--
COMPONENT hardcopyiv_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "hardcopyiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_routing_wire
--
COMPONENT hardcopyiv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_lvds_transmitter
--
COMPONENT hardcopyiv_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- HARDCOPYIV
tx_output_path_delay_engineering_bits : Integer := -1; -- HARDCOPYIV
enable_dpaclk_to_lvdsout : string := "off"; -- HARDCOPYIV
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyiv_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- HARDCOPYIV
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- HARDCOPYIV
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- HARDCOPYIV
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_ram_block
--
COMPONENT hardcopyiv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_ff
--
COMPONENT hardcopyiv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "hardcopyiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_clkselect
--
COMPONENT hardcopyiv_clkselect
generic (
lpm_type : STRING := "hardcopyiv_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_clkena
--
COMPONENT hardcopyiv_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyiv_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_hram
--
COMPONENT hardcopyiv_hram
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tipd_ena0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_devclrn : VitalDelayType01 := DefpropDelay01;
tipd_clr0 : VitalDelayType01 := DefpropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_portabyteenamasks :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portadatain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clr1 : VitalDelayType01 := DefpropDelay01;
tipd_devpor : VitalDelayType01 := DefpropDelay01;
tipd_ena1 : VitalDelayType01 := DefpropDelay01;
tipd_ena2 : VitalDelayType01 := DefpropDelay01;
tipd_portaaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_ena3 : VitalDelayType01 := DefpropDelay01;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01;
logical_ram_name : STRING := "hram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_address_clock : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "hardcopyiv_hram";
lpm_hint : STRING := "true";
mem_init0 : BIT_VECTOR := X"0";
mixed_port_feed_through_mode : STRING := "dont_care"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_io_ibuf
--
COMPONENT hardcopyiv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "hardcopyiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_io_obuf
--
COMPONENT hardcopyiv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "hardcopyiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_ddio_in
--
COMPONENT hardcopyiv_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "hardcopyiv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_ddio_oe
--
COMPONENT hardcopyiv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "hardcopyiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_ddio_out
--
COMPONENT hardcopyiv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "hardcopyiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_termination
--
COMPONENT hardcopyiv_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "hardcopyiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- hardcopyiv_termination_logic
--
COMPONENT hardcopyiv_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "hardcopyiv_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- hardcopyiv_dll
--
COMPONENT hardcopyiv_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "hardcopyiv_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_dll_offset_ctrl
--
COMPONENT hardcopyiv_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "hardcopyiv_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiv_dqs_delay_chain
--
COMPONENT hardcopyiv_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_dqs_enable
--
COMPONENT hardcopyiv_dqs_enable
GENERIC (
lpm_type : string := "hardcopyiv_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_dqs_enable_ctrl
--
COMPONENT hardcopyiv_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_delay_chain
--
COMPONENT hardcopyiv_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "hardcopyiv_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_io_clock_divider
--
COMPONENT hardcopyiv_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_output_phase_alignment
--
COMPONENT hardcopyiv_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "hardcopyiv_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_input_phase_alignment
--
COMPONENT hardcopyiv_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_half_rate_input
--
COMPONENT hardcopyiv_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "hardcopyiv_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_io_config
--
COMPONENT hardcopyiv_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiv_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_dqs_config
--
COMPONENT hardcopyiv_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiv_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_mac_mult
--
COMPONENT hardcopyiv_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_mac_out
--
COMPONENT hardcopyiv_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiv_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_io_pad
--
COMPONENT hardcopyiv_io_pad
GENERIC (
lpm_type : string := "hardcopyiv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- hardcopyiv_pll
--
COMPONENT hardcopyiv_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyiv_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "HARDCOPYIV";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_asmiblock
--
COMPONENT hardcopyiv_asmiblock
generic (
lpm_type : string := "hardcopyiv_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- hardcopyiv_lvds_receiver
--
COMPONENT hardcopyiv_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyiv_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiv_pseudo_diff_out
--
COMPONENT hardcopyiv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "hardcopyiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiv_bias_block
--
COMPONENT hardcopyiv_bias_block
GENERIC (
lpm_type : string := "hardcopyiv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- hardcopyiv_tsdblock
--
COMPONENT hardcopyiv_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "hardcopyiv_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
END COMPONENT;
--
-- hardcopyiv_lcell_hsadder
--
COMPONENT hardcopyiv_lcell_hsadder
generic (
dataa_width : integer := 2;
datab_width : integer := 2;
cin_inverted : string := "off";
lpm_type : string := "hardcopyiv_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_datab_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_cin_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic_vector(dataa_width - 1 downto 0) := (OTHERS => '0');
datab : in std_logic_vector(datab_width - 1 downto 0) := (OTHERS => '0');
cin : in std_logic := '0';
sumout: out std_logic_vector((calc_sum_len(dataa_width, datab_width)) - 2 downto 0);
cout : out std_logic
);
END COMPONENT;
--
-- hardcopyiv_otp
--
COMPONENT hardcopyiv_otp
GENERIC
(
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
TimingChecksOn : Boolean := True;
tipd_otpclken : VitalDelayType01 := DefpropDelay01;
tipd_otpclk : VitalDelayType01 := DefpropDelay01;
tipd_otpshiftnld : VitalDelayType01 := DefpropDelay01;
tpd_otpshiftnld_otpdout : VitalDelayType01 := DefpropDelay01;
tsetup_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
data_width : INTEGER := 128;
init_data : STD_LOGIC_VECTOR(127 DOWNTO 0) := (OTHERS => '0');
init_file : STRING := "init_file.hex";
lpm_type : STRING := "hardcopyiv_otp";
lpm_hint : STRING := "true"
);
PORT
(
otpclken : IN STD_LOGIC := '1';
otpclk : IN STD_LOGIC := '0';
otpshiftnld : IN STD_LOGIC := '0';
otpdout : OUT STD_LOGIC
);
END COMPONENT;
end hardcopyiv_components;
| gpl-3.0 | 4c5848e4b75b70e3267c850012952683 | 0.478443 | 4.37071 | false | false | false | false |
keith-epidev/md2x | build/code/button.vhd | 1 | 2,094 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:29:35 08/22/2012
-- Design Name:
-- Module Name: button - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity button is
generic(
active_high:boolean := true
);
port(
clk: in std_logic;
button: in std_logic;
pulse: out std_logic
);
end button;
architecture Behavioral of button is
signal state: std_logic;
signal clean_signal: std_logic;
signal pulse_val: std_logic;
component debounce is
generic(
delay:integer := 512
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end component;
begin
pulse <= pulse_val;
db_signal:debounce
generic map (
delay => 512
)
port map(
clk => clk,
input => button,
output => clean_signal
);
button_to_pulse:process(clk)
begin
if(clk'event and clk = '1')then
if(not(clean_signal = state) )then
state <= clean_signal;
if((clean_signal = '1' and active_high) or (clean_signal = '0' and not active_high))then
pulse_val <= '1';
end if;
end if;
if(pulse_val = '1')then
pulse_val <='0';
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | 2fc95601c5ac6c0bad707057a5f368b5 | 0.422159 | 4.44586 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_rst_processing_system7_0_100M_0/synth/base_zynq_design_rst_processing_system7_0_100M_0.vhd | 1 | 6,916 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY base_zynq_design_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_rst_processing_system7_0_100M_0;
ARCHITECTURE base_zynq_design_rst_processing_system7_0_100M_0_arch OF base_zynq_design_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "base_zynq_design_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "base_zynq_design_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END base_zynq_design_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | b6fff5d06617e1c330080d03e08196bf | 0.719346 | 3.442509 | false | false | false | false |
thoralt/KCVGA | FPGA/FIFO.vhd | 1 | 6,835 | -------------------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
--
-- Description: Creates a Synchronous FIFO made out of registers.
-- Generic: g_WIDTH sets the width of the FIFO created.
-- Generic: g_DEPTH sets the depth of the FIFO created.
--
-- Total FIFO register usage will be width * depth
-- Note that this fifo should not be used to cross clock domains.
-- (Read and write clocks NEED TO BE the same clock domain)
--
-- FIFO Full Flag will assert as soon as last word is written.
-- FIFO Empty Flag will assert as soon as last word is read.
--
-- FIFO is 100% synthesizable. It uses assert statements which do
-- not synthesize, but will cause your simulation to crash if you
-- are doing something you shouldn't be doing (reading from an
-- empty FIFO or writing to a full FIFO).
--
-- No Flags = No Almost Full (AF)/Almost Empty (AE) Flags
-- There is a separate module that has programmable AF/AE flags.
-------------------------------------------------------------------------------
-- https://www.nandland.com/vhdl/modules/module-fifo-regs-with-flags.html
-------------------------------------------------------------------------------
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity FIFO is
--generic (
-- g_WIDTH : natural := 8;
-- g_DEPTH : integer := 32
--); port (
-- i_rst_sync : in std_logic;
-- i_clk : in std_logic;
--
-- -- FIFO Write Interface
-- i_wr_en : in std_logic;
-- i_wr_data : in std_logic_vector(g_WIDTH-1 downto 0);
-- o_full : out std_logic;
--
-- -- FIFO Read Interface
-- i_rd_en : in std_logic;
-- o_rd_data : out std_logic_vector(g_WIDTH-1 downto 0);
-- o_empty : out std_logic
--);
--end FIFO;
--
--architecture Behavioral of FIFO is
--
-- type t_FIFO_DATA is array (0 to g_DEPTH-1) of std_logic_vector(g_WIDTH-1 downto 0);
-- signal r_FIFO_DATA : t_FIFO_DATA := (others => (others => '0'));
--
-- signal r_WR_INDEX : integer range 0 to g_DEPTH-1 := 0;
-- signal r_RD_INDEX : integer range 0 to g_DEPTH-1 := 0;
--
-- -- # Words in FIFO, has extra range to allow for assert conditions
-- signal r_FIFO_COUNT : integer range -1 to g_DEPTH+1 := 0;
--
-- signal w_FULL : std_logic;
-- signal w_EMPTY : std_logic;
--
-- signal previous_i_rd_en: std_logic;
-- signal previous_i_wr_en: std_logic;
-- signal output_register: std_logic_vector(g_WIDTH-1 downto 0);
--begin
--
-- p_CONTROL : process (i_clk) is
-- begin
-- if rising_edge(i_clk) then
-- if i_rst_sync = '1' then
-- r_FIFO_COUNT <= 0;
-- r_WR_INDEX <= 0;
-- r_RD_INDEX <= 0;
-- previous_i_wr_en <= '0';
-- previous_i_rd_en <= '0';
-- else
--
-- -- Keeps track of the total number of words in the FIFO
-- if (i_wr_en = '1' and i_rd_en = '0') then
-- r_FIFO_COUNT <= r_FIFO_COUNT + 1;
-- elsif (i_wr_en = '0' and i_rd_en = '1') then
-- r_FIFO_COUNT <= r_FIFO_COUNT - 1;
-- end if;
--
-- -- Keeps track of the write index (and controls roll-over)
-- if (i_wr_en = '1' and w_FULL = '0') then
-- if r_WR_INDEX = g_DEPTH-1 then
-- r_WR_INDEX <= 0;
-- else
-- r_WR_INDEX <= r_WR_INDEX + 1;
-- end if;
-- end if;
--
-- -- Keeps track of the read index (and controls roll-over)
-- if (i_rd_en = '1' and w_EMPTY = '0') then
-- if r_RD_INDEX = g_DEPTH-1 then
-- r_RD_INDEX <= 0;
-- else
-- r_RD_INDEX <= r_RD_INDEX + 1;
-- end if;
-- end if;
--
-- -- Registers the input data when there is a write
-- if i_wr_en = '1' and previous_i_wr_en = '0' then
-- r_FIFO_DATA(r_WR_INDEX) <= i_wr_data;
-- end if;
--
-- if i_rd_en = '1' and previous_i_rd_en = '0' then
-- output_register <= r_FIFO_DATA(r_RD_INDEX);
-- end if;
--
-- previous_i_wr_en <= i_wr_en;
-- previous_i_rd_en <= i_rd_en;
-- end if; -- sync reset
-- end if; -- rising_edge(i_clk)
-- end process p_CONTROL;
--
-- o_rd_data <= output_register;
--
-- w_FULL <= '1' when r_FIFO_COUNT = g_DEPTH else '0';
-- w_EMPTY <= '1' when r_FIFO_COUNT = 0 else '0';
--
-- o_full <= w_FULL;
-- o_empty <= w_EMPTY;
--
--end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FIFO IS GENERIC
(RAM_WIDTH, RAM_DEPTH : NATURAL);
PORT
(
clk, rst, wr_en, rd_en : IN STD_LOGIC;
empty, full : OUT STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(RAM_WIDTH - 1 DOWNTO 0);
rd_data : OUT STD_LOGIC_VECTOR(RAM_WIDTH - 1 DOWNTO 0)
);
END FIFO;
ARCHITECTURE Behavioral OF FIFO IS
TYPE ram_type IS ARRAY (0 TO RAM_DEPTH - 1) OF STD_LOGIC_VECTOR(RAM_WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
SIGNAL head, tail, fill_count_i : INTEGER RANGE 0 TO RAM_DEPTH - 1;
SIGNAL previous_rd_en, previous_wr_en : STD_LOGIC;
BEGIN
-- fill_count_i <= 0 when head = tail else
-- head - tail when head > tail else
-- RAM_DEPTH + head - tail;
empty <= '1' WHEN fill_count_i = 0 ELSE
'0';
full <= '1' WHEN fill_count_i = RAM_DEPTH ELSE
'0';
PROCESS (clk, rst)
BEGIN
IF rising_edge(clk) THEN
IF rst = '1' THEN
previous_rd_en <= '0';
previous_wr_en <= '0';
fill_count_i <= 0;
tail <= 0;
head <= 0;
ELSE
IF rd_en = '1' AND previous_rd_en = '0' AND fill_count_i > 0 THEN --not (tail = head) then
rd_data <= ram(tail);
IF tail = RAM_DEPTH - 1 THEN
tail <= 0;
ELSE
tail <= tail + 1;
END IF;
fill_count_i <= fill_count_i - 1;
END IF;
IF wr_en = '1' AND previous_wr_en = '0' AND fill_count_i < RAM_DEPTH THEN
ram(head) <= wr_data;
IF head = RAM_DEPTH - 1 THEN
head <= 0;
ELSE
head <= head + 1;
END IF;
fill_count_i <= fill_count_i + 1;
END IF;
previous_rd_en <= rd_en;
previous_wr_en <= wr_en;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit | ee5294eea7dd702d9ff254e873f21368 | 0.483394 | 3.370316 | false | false | false | false |
freecores/t400 | bench/vhdl/t420_rom-lpm-a.vhd | 1 | 3,515 | -------------------------------------------------------------------------------
--
-- T420 ROM wrapper for lpm_rom.
--
-- $Id: t420_rom-lpm-a.vhd,v 1.1 2006-05-14 22:31:08 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
architecture lpm of t420_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := "LPM_ROM";
LPM_HINT : string := "UNUSED"
);
port (
ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_WIDTHAD => 10,
LPM_OUTDATA => "UNREGISTERED",
LPM_FILE => "rom_42x.hex"
)
port map (
ADDRESS => addr_i,
INCLOCK => ck_i,
OUTCLOCK => ck_i,
MEMENAB => vdd_s,
Q => data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | cbf31d79bcf95130ae5ce5cae5802310 | 0.582077 | 4.388265 | false | false | false | false |
keith-epidev/md2x | build/code/multimux.vhdl | 1 | 1,053 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity multi_mux is
generic(
size:integer := 4;
width:integer := 2
);
port (
s : in std_logic_vector(f_log2(size)-1 downto 0);
input : in std_logic_vector((width*size)-1 downto 0);
output : out std_logic_vector(width-1 downto 0)
);
end multi_mux;
architecture arch of multi_mux is
signal z : std_logic_vector( size*width-1 downto 0 );
component mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(f_log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end component;
begin
GEN_SWIZ1:
for I in 0 to width-1 generate
GEN_SWIZ2:
for J in 0 to size-1 generate
z( I*size + J ) <= input(J*width + I );
end generate GEN_SWIZ2;
end generate GEN_SWIZ1;
GEN_MUX:
for I in 0 to width-1 generate
MUX_X : mux generic map(size=>size) port map ( s, z( I*size +(size-1) downto I*size ) , output(I) ); -- width not correct
end generate ;
end arch;
| gpl-2.0 | ea4f9fd2e6b241427fa5a2249b4c24cc | 0.650522 | 2.665823 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_t421.vhd | 1 | 4,265 | -------------------------------------------------------------------------------
--
-- Testbench for the T421 system toplevel.
--
-- $Id: tb_t421.vhd,v 1.1 2006-06-11 13:49:50 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t421 is
end tb_t421;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t421;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t421 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t421_b : t421
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_cko_g => t400_opt_cko_gpi_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => io_in_s,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 4110755dd15d298565aff1901b4b92b9 | 0.535287 | 3.761023 | false | false | false | false |
google/myelin-acorn-electron-hardware | mega_games_cartridge_mk2/cpld/mega_games_cartridge_v2.vhdl | 1 | 11,358 | -- Copyright 2019 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MGC is
generic (
-- Base resource usage: 26MC
-- Include shift-register based (as well as bit banged) SPI (adds ~20MC)
-- = 8 bit shifter, 4 bit counter, 1 bit spi_start, 1 bit spi_bit_bang_mode
IncludeSPIShifter : boolean := true;
-- Clock the SPI port with CLK16MHz (adds ~8 MC)
UseFastClockForSPI : boolean := false
);
port (
-- Inputs from the cartridge interface
PHI : in std_logic;
CLK16MHz : in std_logic;
nRESET : in std_logic;
nPGFC : in std_logic; -- Low when &FCxx is selected
QA : in std_logic; -- Upper/lower bank select
A : in std_logic_vector(7 downto 0);
D : inout std_logic_vector(7 downto 0);
nMASDET : in std_logic; -- Low on Master, high on Electron
-- In the Electron Plus 1, Pin A2 is called nOE2 or nOE4 depending
-- which cartridge slot is in use. The Plus 1's logic driving nOE2
-- is:
-- nOE2 <= not (A15 and not A14
-- and not FE05(3) and not FE05(2) and FE05(1));
-- i.e. nOE2 is low when the 6502 is reading or writing the sideways
-- area and the cartridge is selected.
-- In the Master 128, Pin A2 is driven by AT13 (IC20 pin 17) or AT15
-- (IC20 pin 15), which are outputs from the memory controller IC.
-- TODO scope this to see how it behaves.
nOE : in std_logic; -- Pin A2
-- Electron: CPU RnW line
-- Master: AA15 line; IC20 pin 19
ERnW_MCS : in std_logic; -- Pin A4
-- Electron: CPU READY line
-- Master: BRnW line
ERDY_MRnW : in std_logic; -- Pin A11
-- Power-on reset; low for ~1ms on startup
nPWRRST : in std_logic;
-- Outputs to ROM and RAM chip
RR_nWE : out std_logic;
RR_nOE : out std_logic;
ROM_nCE : out std_logic;
RAM_nCE : out std_logic;
-- SPI port
SD_CS1 : out std_logic := '1';
SD_CS2 : out std_logic := '1';
-- SD_CS2 : in std_logic; -- Disabled as cartridge has CLK16MHz linked in there
SD_SCK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic
);
end;
architecture rtl of MGC is
signal nRESET_sync : std_logic;
-- High to map ROM into the bank, low to map RAM
signal lower_bank_rom_nram : std_logic := '1';
signal upper_bank_rom_nram : std_logic := '1';
signal lower_rom_unlocked : std_logic := '0';
signal upper_rom_unlocked : std_logic := '0';
signal inhibit_reset : std_logic := '0';
signal spi_shift_register_phi : std_logic_vector(7 downto 0) := (others => '0');
signal spi_shift_register_16 : std_logic_vector(7 downto 0) := (others => '0');
signal spi_start : std_logic := '0';
signal spi_start_16 : std_logic := '0';
signal last_spi_start_16 : std_logic := '0';
signal spi_counter_phi : std_logic_vector(3 downto 0) := (others => '1');
signal spi_counter_16 : std_logic_vector(3 downto 0) := (others => '1');
signal spi_bit_bang_mode : std_logic := '1';
signal spi_bit_bang_MOSI : std_logic := '1';
signal spi_bit_bang_SCK : std_logic := '0';
signal spi_fast_SCK : std_logic := '0';
signal spi_fast_MOSI : std_logic := '0';
signal RnW : std_logic;
begin
-- DEBUG
-- SD_CS2 <= spi_bit_bang_MOSI;
-- SD_CS2 <= spi_bit_bang_SCK;
-- SD_CS2 <= nPGFC;
-- SD_CS2 <= '1' when nPGFC = '0' and PHI = '1' and RnW = '0' else '0'; -- writing to &FCxx
-- SD_CS2 <= D(1);
-- Derive RnW signal
RnW <= ERnW_MCS when nMASDET = '1' else ERDY_MRnW;
-- ROM/RAM output enable
RR_nOE <= '0' when
nOE = '0' -- cartridge selected
and RnW = '1' -- cpu is reading
else '1';
-- ROM/RAM write strobe
-- /WE is also gated with the high clock period, as D isn't held for
-- long past the falling edge. It should go low when PHI0 is high and
-- RnW is low.
RR_nWE <= '0' when
nOE = '0' -- cartridge selected
and RnW = '0' -- cpu is writing
and PHI = '1' -- high clock period
and ((QA = '0' and lower_rom_unlocked = '1') -- lower bank unlocked
or (QA = '1' and upper_rom_unlocked = '1')) -- upper bank unlocked
else '1';
-- ROM chip select
ROM_nCE <= '0' when
nOE = '0' -- cartridge selected
and ((QA = '0' and lower_bank_rom_nram = '1') -- lower bank is ROM
or (QA = '1' and upper_bank_rom_nram = '1')) -- upper bank is ROM
else '1';
-- RAM chip select
RAM_nCE <= '0' when
nOE = '0' -- cartridge selected
and ((QA = '0' and lower_bank_rom_nram = '0') -- lower bank is RAM
or (QA = '1' and upper_bank_rom_nram = '0')) -- upper bank is RAM
else '1';
-- Handle reads from registers
D <=
-- Never drive the bus for CPU writes
"ZZZZZZZZ" when RnW = '0'
-- Read machine type
else "0000000" & nMASDET when nPGFC = '0' and A = x"D2"
-- Read shift register
else spi_shift_register_phi when nPGFC = '0' and A = x"D4" and IncludeSPIShifter and not UseFastClockForSPI
else spi_shift_register_16 when nPGFC = '0' and A = x"D4" and IncludeSPIShifter and UseFastClockForSPI
-- Read MISO
else SD_MISO & "00000" & spi_bit_bang_SCK & spi_bit_bang_MOSI when nPGFC = '0' and A = x"D8"
-- Catchall
else "ZZZZZZZZ";
-- Multiplex fast and bitbang SPI
SD_SCK <= spi_bit_bang_SCK when (spi_bit_bang_mode = '1' or not UseFastClockForSPI) else spi_fast_SCK;
SD_MOSI <= spi_bit_bang_MOSI when (spi_bit_bang_mode = '1' or not UseFastClockForSPI) else spi_fast_MOSI;
-- CPU clock process
elk_clock_process : process(PHI)
begin
if falling_edge(PHI) then
-- Synchronize external reset
nRESET_sync <= nRESET;
-- Reset all one pulse outputs
spi_start <= '0';
-- Handle writes to registers
if nPGFC = '0' and A = x"D0" then
lower_bank_rom_nram <= not RnW; -- TODO did I get this right? reading sets it to ram?
end if;
if nPGFC = '0' and A = x"D1" then
upper_bank_rom_nram <= not RnW; -- TODO did I get this right? reading sets it to ram?
end if;
if RnW = '0' then
if nPGFC = '0' and A = x"D3" then
inhibit_reset <= '1';
end if;
if nPGFC = '0' and A = x"D4" and IncludeSPIShifter then
-- Copy D into load register and trigger SPI
if UseFastClockForSPI then
-- Pass contents of D over to CLK16MHz process
spi_shift_register_phi <= D;
spi_start <= '1';
spi_bit_bang_mode <= '0'; -- Output 16MHz SPI registers
else
-- Start shifting immediately; shifter is running off PHI
spi_counter_phi <= "0000";
-- initialize MOSI with the MSB right now, and update it on the falling
-- edge of spi_fast_SCK.
spi_bit_bang_MOSI <= spi_shift_register_phi(7);
end if;
end if;
if nPGFC = '0' and A = x"D8" then
spi_bit_bang_MOSI <= D(0);
spi_bit_bang_SCK <= D(1);
end if;
if nPGFC = '0' and A = x"D9" then
SD_CS1 <= D(0);
-- SD_CS2 <= D(1);
spi_bit_bang_mode <= '1';
end if;
if nPGFC = '0' and A = x"DC" then
lower_rom_unlocked <= '1';
end if;
if nPGFC = '0' and A = x"DD" then
lower_rom_unlocked <= '0';
end if;
if nPGFC = '0' and A = x"DE" then
upper_rom_unlocked <= '1';
end if;
if nPGFC = '0' and A = x"DF" then
upper_rom_unlocked <= '0';
end if;
end if;
if nRESET_sync = '0' then
inhibit_reset <= '0';
lower_bank_rom_nram <= '1';
upper_bank_rom_nram <= '1';
lower_rom_unlocked <= '0';
upper_rom_unlocked <= '0';
end if;
-- 1-2 MHz SPI
if IncludeSPIShifter and not UseFastClockForSPI then
if spi_counter_phi(3) = '0' then
-- spi active!
if spi_bit_bang_SCK = '0' then
spi_bit_bang_SCK <= '1';
spi_shift_register_phi <= spi_shift_register_phi(6 downto 0) & SD_MISO;
else
spi_bit_bang_SCK <= '0';
spi_bit_bang_MOSI <= spi_shift_register_phi(7);
spi_counter_phi <= std_logic_vector(unsigned(spi_counter_phi) + 1);
end if;
end if;
end if;
end if;
end process;
-- High speed (16MHz on Electron, 8MHz on Master) clock process
fast_clock_process : process(CLK16MHZ)
begin
if rising_edge(CLK16MHZ) then
if IncludeSPIShifter and UseFastClockForSPI then
-- Synchronize spi_start
last_spi_start_16 <= spi_start_16;
spi_start_16 <= spi_start;
if spi_start_16 = '1' and last_spi_start_16 = '0' then
-- start spi transaction
spi_counter_16 <= "0000";
-- initialize MOSI with the MSB right now, and update it on the falling
-- edge of spi_fast_SCK.
spi_fast_MOSI <= spi_shift_register_phi(7);
spi_shift_register_16 <= spi_shift_register_phi;
end if;
if spi_counter_16(3) = '0' then
-- spi active!
if spi_fast_SCK = '0' then
spi_fast_SCK <= '1';
spi_shift_register_16 <= spi_shift_register_16(6 downto 0) & SD_MISO;
else
spi_fast_SCK <= '0';
spi_fast_MOSI <= spi_shift_register_16(7);
spi_counter_16 <= std_logic_vector(unsigned(spi_counter_16) + 1);
end if;
end if;
end if;
end if;
end process;
end rtl;
| apache-2.0 | 0d1412ee47112dc7fb00a84b9c4fa29a | 0.516288 | 3.665053 | false | false | false | false |
alvieboy/xtc-base | mux32_4.vhd | 1 | 635 | library ieee;
use ieee.std_logic_1164.all;
entity mux32_4 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
i2: in std_logic_vector(31 downto 0);
i3: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
o: out std_logic_vector(31 downto 0)
);
end entity mux32_4;
architecture behave of mux32_4 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => o <= i0;
when "01" => o <= i1;
when "10" => o <= i2;
when "11" => o <= i3;
when others => o <= (others => 'X');
end case;
end process;
end behave;
| bsd-3-clause | 379a3268c6e6f9a9781a5a120c4a40d3 | 0.587402 | 2.785088 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/RAM.vhd | 1 | 19,246 | ----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 19:49:20 09/22/2011
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity RAM is
Port
(
CLK: in std_logic;
Control: in std_logic_vector(11 downto 0);
ADDR: in std_logic_vector(11 downto 0);
IO: inout std_logic_vector(11 downto 0)
);
end RAM;
architecture Behavioral of RAM is
signal SSR: std_logic;
signal RAMBus: std_logic_vector(11 downto 0) := "000000000000";
begin
SSR <= '0';
process (Control, RAMBus)
begin
if(Control(0) = '1') then
IO <= RAMBus;
else
IO <= "ZZZZZZZZZZZZ";
end if;
end process;
LowNibble : RAMB16_S4
generic map (
INIT => X"A", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
INIT_00 => X"F00000000000000000000000000000000000A010F5E460F00000000051100001", --Ram contents in hex, higher addresses right most
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 2047
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 2048 to 3071
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 3072 to 4095
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => RAMBus(3 downto 0), -- 4-bit Data Output
ADDR => ADDR, -- 12-bit Address Input
CLK => CLK, -- Clock
DI => IO(3 downto 0), -- 4-bit Data Input
EN => '1', -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => Control(1) -- Write Enable Input
);
MiddleNibble : RAMB16_S4
generic map (
INIT => X"1", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
INIT_00 => X"C000000000000000000000000000000000001010F2230CF00000000000000001",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 2047
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 2048 to 3071
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 3072 to 4095
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => RAMBus(7 downto 4), -- 4-bit Data Output
ADDR => ADDR, -- 12-bit Address Input
CLK => CLK, -- Clock
DI => IO(7 downto 4), -- 4-bit Data Input
EN => '1', -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => Control(1) -- Write Enable Input
);
HighNibble : RAMB16_S4
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
INIT_00 => X"D000000000000000000000000000000000000A0A08080D700000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 2047
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 2048 to 3071
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 3072 to 4095
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => RAMBus(11 downto 8), -- 4-bit Data Output
ADDR => ADDR, -- 12-bit Address Input
CLK => CLK, -- Clock
DI => IO(11 downto 8), -- 4-bit Data Input
EN => '1', -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => Control(1) -- Write Enable Input
);
end Behavioral;
| bsd-3-clause | 7b8f8ad245d1f9f87393a394d454a93d | 0.799179 | 6.575333 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixgx_hssi_components.vhd | 1 | 27,754 |
library IEEE, stratixgx_gxb;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use stratixgx_gxb.hssi_pack.all;
package STRATIXGX_HSSI_COMPONENTS is
-- Beginning of testing section
-- these components are added for testing
component stratixgx_comp_fifo
GENERIC (
use_rate_match_fifo : string := "true";
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : string := "true"; -- new in 3.0 SP2
channel_num : integer := 0
);
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
errdetectinpre : IN std_logic;
syncstatusinpre : IN std_logic;
disperrinpre : IN std_logic;
patterndetectinpre : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
re : IN std_logic;
we : IN std_logic;
fifordin : IN std_logic;
disablefifordin : IN std_logic;
disablefifowrin : IN std_logic;
alignstatus : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
errdetectout : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
codevalid : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostful : OUT std_logic;
fifoempty : OUT std_logic;
fifoalmostempty : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
fifordout : OUT std_logic);
end component;
component stratixgx_deskew_fifo
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
writeclock : IN std_logic;
readclock : IN std_logic;
adetectdeskew : OUT std_logic;
fiforesetrd : IN std_logic;
enabledeskew : IN std_logic;
reset : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
dataoutpre : OUT std_logic_vector(9 DOWNTO 0);
errdetect : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
errdetectpre : OUT std_logic;
syncstatuspre : OUT std_logic;
disperrpre : OUT std_logic;
patterndetectpre : OUT std_logic;
rdalign : OUT std_logic);
END component;
component stratixgx_rx_core
GENERIC (
channel_width : integer := 10;
use_double_data_mode : string := "false";
use_channel_align : string := "false";
use_8b_10b_mode : string := "true";
synchronization_mode : string := "none";
align_pattern : string := "0000000101111100");
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
errdetectin : IN std_logic;
patterndetectin : IN std_logic;
decdatavalid : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
post8b10b : IN std_logic_vector(9 DOWNTO 0);
datain : IN std_logic_vector(9 DOWNTO 0);
xgmctrlin : IN std_logic;
ctrldetectin : IN std_logic;
syncstatusin : IN std_logic;
disparityerrin : IN std_logic;
syncstatus : OUT std_logic_vector(1 DOWNTO 0);
errdetect : OUT std_logic_vector(1 DOWNTO 0);
ctrldetect : OUT std_logic_vector(1 DOWNTO 0);
disparityerr : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(19 DOWNTO 0);
a1a2sizeout : OUT std_logic_vector(1 DOWNTO 0);
clkout : OUT std_logic);
END component;
component stratixgx_tx_core
GENERIC (
use_double_data_mode : string := "false";
use_fifo_mode : string := "true";
transmit_protocol : string := "none";
channel_width : integer := 10;
KCHAR : std_logic := '0';
ECHAR : std_logic := '0');
PORT (
reset : IN std_logic;
datain : IN std_logic_vector(19 DOWNTO 0);
writeclk : IN std_logic;
readclk : IN std_logic;
ctrlena : IN std_logic_vector(1 DOWNTO 0);
forcedisp : IN std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(9 DOWNTO 0);
forcedispout : OUT std_logic;
ctrlenaout : OUT std_logic;
rdenasync : OUT std_logic;
xgmctrlena : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
pre8b10bdataout : OUT std_logic_vector(7 DOWNTO 0));
END component;
component stratixgx_8b10b_encoder
GENERIC (
transmit_protocol : string := "none";
use_8b_10b_mode : string := "true";
force_disparity_mode : string := "false");
PORT (
clk : IN std_logic;
reset : IN std_logic;
xgmctrl : IN std_logic;
kin : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
datain : IN std_logic_vector(7 DOWNTO 0);
forcedisparity : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
parafbkdataout : OUT std_logic_vector(9 DOWNTO 0));
END component;
component stratixgx_8b10b_decoder
PORT (
clk : IN std_logic;
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
datainvalid : IN std_logic;
datain : IN std_logic_vector(9 DOWNTO 0);
valid : OUT std_logic;
dataout : OUT std_logic_vector(7 DOWNTO 0);
tenBdata : OUT std_logic_vector(9 DOWNTO 0);
errdetect : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
kout : OUT std_logic;
rderr : OUT std_logic;
decdatavalid : OUT std_logic;
xgmdatavalid : OUT std_logic;
xgmrunningdisp : OUT std_logic;
xgmctrldet : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0));
end component;
component stratixgx_hssi_rx_serdes
generic (
channel_width : integer := 10;
rlv_length : integer := 1;
run_length_enable : String := "false";
cruclk_period : integer :=5000;
cruclk_multiplier : integer :=4;
use_cruclk_divider : String := "false";
use_double_data_mode : String := "false";
tipd_0 : VitalDelayType01 := DefpropDelay01
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
areset : in std_logic := '0';
feedback : in std_logic := '0';
fbkcntl : in std_logic := '0';
dataout : out std_logic_vector(9 downto 0);
clkout : out std_logic;
rlv : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
signaldetect: out std_logic
);
end component;
component stratixgx_hssi_tx_serdes
generic (
channel_width : integer := 10
);
port (
clk : in std_logic := '0';
clk1 : in std_logic := '0';
datain : in std_logic_vector(9 downto 0) := "0000000000";
serialdatain : in std_logic := '0';
srlpbk : in std_logic := '0';
areset : in std_logic := '0';
dataout : out std_logic
);
end component;
component stratixgx_hssi_word_aligner
generic (
channel_width : integer := 10;
align_pattern_length: integer := 10;
align_pattern : string := "0000000101111100";
synchronization_mode: string := "XAUI";
use_8b_10b_mode : string := "true";
use_auto_bit_slip : string := "true"
);
port (
datain : in std_logic_vector(9 downto 0) := "0000000000";
clk : in std_logic := '0';
softreset : in std_logic := '0';
enacdet : in std_logic := '0';
bitslip : in std_logic := '0';
a1a2size : in std_logic := '0';
aligneddata : out std_logic_vector(9 downto 0);
aligneddatapre : out std_logic_vector(9 downto 0);
invalidcode : out std_logic;
invalidcodepre : out std_logic;
syncstatus : out std_logic;
syncstatusdeskew : out std_logic;
disperr : out std_logic;
disperrpre : out std_logic;
patterndetect : out std_logic;
patterndetectpre : out std_logic
);
end component;
component stratixgx_xgm_rx_sm
port (
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0)
);
end component;
component stratixgx_xgm_tx_sm
port (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
resetall : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0));
end component;
component stratixgx_xgm_dskw_sm
port (
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic);
end component;
-- End of testing section
component stratixgx_hssi_receiver
generic (
channel_num : integer := 1;
channel_width : integer := 20;
deserialization_factor : integer := 10;
run_length : integer := 4;
run_length_enable : String := "false";
use_8b_10b_mode : String := "false";
use_double_data_mode : String := "false";
use_rate_match_fifo : String := "false";
rate_matching_fifo_mode : String := "none";
use_channel_align : String := "false";
use_symbol_align : String := "true";
use_auto_bit_slip : String := "false";
use_parallel_feedback : String := "false";
use_post8b10b_feedback : String := "false";
send_reverse_parallel_feedback : String := "false";
synchronization_mode : String := "none";
align_pattern : String := "0000000000000000";
align_pattern_length : integer := 7;
infiniband_invalid_code : integer := 0;
disparity_mode : String := "false";
clk_out_mode_reference : String := "false";
cruclk_period : integer := 5000;
cruclk_multiplier : integer := 4;
use_cruclk_divider : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
use_equalizer_ctrl_signal : String := "false";
enable_dc_coupling : String := "false";
equalizer_ctrl_setting : integer := 20;
signal_threshold_select : integer := 2;
vco_bypass : String := "false";
force_signal_detect : String := "false";
bandwidth_type : String := "low";
for_engineering_sample_device : String := "true"; -- new in 3.0 SP2
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_cruclk : VitalDelayType01 := DefpropDelay01;
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_parallelfdbk : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_post8b10b : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_slpbk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_enacdet : VitalDelayType01 := DefpropDelay01;
tipd_we : VitalDelayType01 := DefpropDelay01;
tipd_re : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tsetup_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_dataout_posedge : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_syncstatus_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_patterndetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_ctrldetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_errdetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_disperr_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_a1a2sizeout_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_fifofull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoempty_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostfull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostempty_posedge : VitalDelayType01 := DefPropDelay01
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
pllclk : in std_logic := '0';
masterclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
serialfdbk : in std_logic := '0';
parallelfdbk : in std_logic_vector(9 downto 0) := "0000000000";
post8b10b : in std_logic_vector(9 downto 0) := "0000000000";
slpbk : in std_logic := '0';
bitslip : in std_logic := '0';
enacdet : in std_logic := '0';
we : in std_logic := '0';
re : in std_logic := '0';
alignstatus : in std_logic := '0';
disablefifordin : in std_logic := '0';
disablefifowrin : in std_logic := '0';
fifordin : in std_logic := '0';
enabledeskew : in std_logic := '0';
fiforesetrd : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrlin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
a1a2size : in std_logic := '0';
locktorefclk : in std_logic := '0';
locktodata : in std_logic := '0';
equalizerctrl : in std_logic_vector(2 downto 0) := "000";
syncstatus : out std_logic_vector(1 downto 0);
patterndetect : out std_logic_vector(1 downto 0);
ctrldetect : out std_logic_vector(1 downto 0);
errdetect : out std_logic_vector(1 downto 0);
disperr : out std_logic_vector(1 downto 0);
syncstatusdeskew : out std_logic;
adetectdeskew : out std_logic;
rdalign : out std_logic;
dataout : out std_logic_vector(19 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrldet : out std_logic;
xgmrunningdisp : out std_logic;
xgmdatavalid : out std_logic;
fifofull : out std_logic;
fifoalmostfull : out std_logic;
fifoempty : out std_logic;
fifoalmostempty : out std_logic;
disablefifordout : out std_logic;
disablefifowrout : out std_logic;
fifordout : out std_logic;
signaldetect : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
rlv : out std_logic;
clkout : out std_logic;
recovclkout : out std_logic;
bisterr : out std_logic := '0';
bistdone : out std_logic := '1';
a1a2sizeout : out std_logic_vector(1 downto 0)
);
end component;
component stratixgx_hssi_transmitter
generic (
channel_num : integer := 1;
channel_width : integer := 20;
serialization_factor: integer := 10;
use_8b_10b_mode : String := "false";
use_double_data_mode: String := "false";
use_fifo_mode : String := "false";
use_reverse_parallel_feedback : String := "false";
force_disparity_mode: String := "false";
transmit_protocol : String := "none";
use_vod_ctrl_signal : String := "false";
use_preemphasis_ctrl_signal : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
vod_ctrl_setting : integer := 4;
preemphasis_ctrl_setting : integer := 5;
termination : integer := 0;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_fastpllclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_forcedisparity : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_srlpbk : VitalDelayType01 := DefpropDelay01;
tsetup_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_forcedisparity_coreclk_noedge_posedge: VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_forcedisparity_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst)
);
port (
datain : in std_logic_vector(19 downto 0);
pllclk : in std_logic := '0';
fastpllclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
ctrlenable : in std_logic_vector(1 downto 0) := "00";
forcedisparity : in std_logic_vector(1 downto 0) := "00";
serialdatain : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrl : in std_logic := '0';
srlpbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
vodctrl : in std_logic_vector(2 downto 0) := "000";
preemphasisctrl : in std_logic_vector(2 downto 0) := "000";
dataout : out std_logic;
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic;
rdenablesync : out std_logic;
parallelfdbkdata : out std_logic_vector(9 downto 0);
pre8b10bdata : out std_logic_vector(9 downto 0)
);
end component;
component stratixgx_xgm_interface
generic (
use_continuous_calibration_mode : String := "false";
mode_is_xaui : String := "false";
rx_ppm_setting_0 : integer := 0;
rx_ppm_setting_1 : integer := 0;
digital_test_output_select : integer := 0;
analog_test_output_signal_select : integer := 0;
analog_test_output_channel_select : integer := 0;
use_rx_calibration_status : String := "false";
use_global_serial_loopback : String := "false";
rx_calibration_test_write_value : integer := 0;
enable_rx_calibration_test_write : String := "false";
tx_calibration_test_write_value : integer := 0;
enable_tx_calibration_test_write : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_txdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_txctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_rxrunningdisp : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_resetall : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_syncstatus : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdalign : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01
);
PORT (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
devpor : IN std_logic := '0';
devclrn : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
resetout : OUT std_logic;
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
-- NEW MDIO/PE ONLY PORTS
mdioclk : IN std_logic := '0';
mdiodisable : IN std_logic := '0';
mdioin : IN std_logic := '0';
rxppmselect : IN std_logic := '0';
scanclk : IN std_logic := '0';
scanin : IN std_logic := '0';
scanmode : IN std_logic := '0';
scanshift : IN std_logic := '0';
-- NEW MDIO/PE ONLY PORTS
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
digitalsmtest : OUT std_logic_vector(3 DOWNTO 0);
mdiooe : OUT std_logic;
mdioout : OUT std_logic;
scanout : OUT std_logic;
test : OUT std_logic;
-- RESET PORTS
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
pllreset : IN std_logic := '0';
pllenable : IN std_logic := '1';
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
pllresetout : OUT std_logic
);
end component;
end stratixgx_hssi_components;
| gpl-3.0 | b5de2781dbe51818406c200fa6340fae | 0.557541 | 3.754092 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_blk_mem_gen_0_0/synth/base_zynq_design_blk_mem_gen_0_0.vhd | 1 | 14,106 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY base_zynq_design_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END base_zynq_design_blk_mem_gen_0_0;
ARCHITECTURE base_zynq_design_blk_mem_gen_0_0_arch OF base_zynq_design_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_blk_mem_gen_0_0_arch : ARCHITECTURE IS "base_zynq_design_blk_mem_gen_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_blk_mem_gen_0_0_arch: ARCHITECTURE IS "base_zynq_design_blk_mem_gen_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.3746 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.3746 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END base_zynq_design_blk_mem_gen_0_0_arch;
| gpl-3.0 | 69ac365e25a24014ae41c1411dd87886 | 0.632213 | 3.014747 | false | false | false | false |
thoralt/KCVGA | FPGA/CLK.vhd | 1 | 2,801 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.vcomponents.ALL;
ENTITY CLK IS
PORT
(
reset, clk_input : IN STD_LOGIC;
clk_output : OUT STD_LOGIC
);
END CLK;
ARCHITECTURE Behavioral OF clk IS
SIGNAL sig_clk, clkfb : STD_LOGIC;
BEGIN
-- force sig_CLK_108MHZ to use a BUFG for clock distribution
i_CLK_BUFG : BUFG PORT MAP
(I => sig_clk, O => clk_output);
i_DCM_SP : DCM_SP
GENERIC
MAP(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 4, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 9, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.833000, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
PORT
MAP(
CLK0 => clkfb, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
-- CLK2X => CLK2X, -- 2X DCM CLK output
-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sig_CLK, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
-- LOCKED => LOCKED, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clk_input, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => PSCLK, -- Dynamic phase adjust clock input
-- PSEN => PSEN, -- Dynamic phase adjust enable input
-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => reset -- DCM asynchronous reset input
);
END ARCHITECTURE;
| mit | fad557ee0fba2d4b5b7d713100d55656 | 0.56694 | 3.591026 | false | false | false | false |
keith-epidev/md2x | build/code/mux.vhdl | 1 | 1,170 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(f_log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end mux;
architecture arch of mux is
signal y : std_logic_vector(size-1 downto 0);
signal z : std_logic_vector( ( size * (s'length+1) ) -1 downto 0);
component or_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component and_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
begin
ORX: or_gate generic map(width=>size) port map(y,output);
GEN_REG:
for I in 0 to size-1 generate
z(I*(s'length+1)+s'length downto I*(s'length+1)) <= (s xor std_logic_vector(to_unsigned(I,s'length))) & input(size-1-I);
REGX : and_gate generic map(width=> s'length+1 ) port map ( z(I*(s'length+1)+s'length downto I*(s'length+1)) ,y(I) );
end generate ;
end arch;
| gpl-2.0 | 7b688547dd6637a2d4738cec42868459 | 0.636752 | 2.689655 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_timer.vhd | 1 | 3,807 | -------------------------------------------------------------------------------
--
-- The timer unit.
--
-- $Id: t400_timer.vhd,v 1.1 2006-05-20 02:47:12 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
entity t400_timer is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
-- Skip Interface ---------------------------------------------------------
op_i : in skip_op_t;
c_o : out boolean
);
end t400_timer;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_timer is
signal cnt_q : unsigned(9 downto 0);
signal c_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements:
-- * timer counter
-- * carry (underflow) marker flag
--
seq: process (ck_i, por_i)
begin
if por_i then
cnt_q <= (others => '1');
c_q <= false;
elsif ck_i'event and ck_i = '1' then
if icyc_en_i then
if cnt_q = 0 then
-- counter underflow:
-- * reload counter
-- * set marker flag
cnt_q <= (others => '1');
c_q <= true;
else
cnt_q <= cnt_q - 1;
end if;
end if;
if ck_en_i and op_i = SKIP_TIMER then
c_q <= false;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
c_o <= c_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 25e2a1f63ef69c24382834eccd257106 | 0.560284 | 4.396074 | false | false | false | false |
lerwys/hdl-make2 | test/top_module_tb.vhd | 1 | 2,637 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity top_module_tb is -- entity declaration
end top_module_tb;
architecture sim of top_module_tb is
-- 100.00 MHz clock
constant c_clk_period : time := 10.00 ns;
constant c_sim_time : time := 1000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
signal clk100 : std_logic := '0';
signal s_locked : std_logic;
signal s_blink : std_logic_vector(7 downto 0);
-- Components
component top_module
port(
clk_i : in std_logic;
locked_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end component;
-- Functions
--function calculate_next_input_sample(sample_number : in integer) return std_logic_vector is
-- variable A : real := 1.0; -- Amplitude for wave
-- variable F : real := 100.0; -- Frequency for wave
-- variable P : real := 0.0; -- Phase for wave
-- variable theta : real;
-- variable y : real; -- The calculated value as a real
-- variable y_int : integer; -- The calculated value as an integer
-- variable result : std_logic_vector(c_ip_width-1 downto 0);
-- variable number_of_samples : real := 100.0 * real(47);
--begin
-- theta := (2.0 * MATH_PI * F * real(sample_number mod integer(number_of_samples))) / number_of_samples;
--y := A * sin(theta + P);
--y_int := integer(round(y * real(2**(c_ip_width-2))));
--result := std_logic_vector(to_signed(y_int, c_ip_width));
--return result;
--end function calculate_next_input_sample;
begin
cmp_top_module : top_module
port map
(
clk_i => clk100,
locked_i => s_locked,
blink_o => s_blink
);
--p_locked : process
--begin
-- s_locked <= '0';
-- wait for 20 ns;
--wait until rising_edge(clk100);
--wait until rising_edge(clk100);
--wait until rising_edge(clk100);
-- s_locked <= '1';
--end process p_locked;
p_clk_gen : process is
begin
while g_end_simulation = false loop
wait for c_clk_period/2;
clk100 <= not clk100;
wait for c_clk_period/2;
clk100 <= not clk100;
end loop;
wait; -- simulation stops here
end process p_clk_gen;
p_main_simulation : process is
begin
-- wait for c_sim_time;
-- g_end_simulation <= true;
-- wait;
s_locked <= '0';
wait for 2*c_clk_period;
s_locked <= '1';
wait for 100*c_clk_period;
-- End simualtion
g_end_simulation <= true;
end process p_main_simulation;
end sim;
| gpl-2.0 | 4712ced4e259a72a262af6e0bd75f27c | 0.602958 | 2.94308 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_axi_gpio_0_0/sim/base_zynq_design_axi_gpio_0_0.vhd | 1 | 9,162 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY base_zynq_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END base_zynq_design_axi_gpio_0_0;
ARCHITECTURE base_zynq_design_axi_gpio_0_0_arch OF base_zynq_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 5,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END base_zynq_design_axi_gpio_0_0_arch;
| gpl-3.0 | 4d448a72637850d9da48b3f9a88ecf28 | 0.681183 | 3.226056 | false | false | false | false |
alvieboy/xtc-base | vga_320_240_idx.vhd | 1 | 16,714 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity vga_320_240_idx is
port(
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 2);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
-- Wishbone MASTER interface
mi_wb_dat_i: in std_logic_vector(31 downto 0);
mi_wb_dat_o: out std_logic_vector(31 downto 0);
mi_wb_adr_o: out std_logic_vector(31 downto 0);
mi_wb_sel_o: out std_logic_vector(3 downto 0);
mi_wb_cti_o: out std_logic_vector(2 downto 0);
mi_wb_we_o: out std_logic;
mi_wb_cyc_o: out std_logic;
mi_wb_stb_o: out std_logic;
mi_wb_ack_i: in std_logic;
mi_wb_stall_i: in std_logic;
-- VGA signals
vgaclk: in std_logic;
vga_hsync: out std_logic;
vga_vsync: out std_logic;
vga_b: out std_logic_vector(4 downto 0);
vga_r: out std_logic_vector(4 downto 0);
vga_g: out std_logic_vector(4 downto 0);
blank: out std_logic
);
end entity;
architecture behave of vga_320_240_idx is
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component gh_fifo_async_rrd_sr_wf is
GENERIC (add_width: INTEGER :=8; -- min value is 2 (4 memory locations)
data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
qfull : out STD_LOGIC;
hfull : out STD_LOGIC;
qqqfull : out STD_LOGIC;
afull : out STD_LOGIC;
full : out STD_LOGIC);
end component;
signal fifo_full: std_logic;
signal fifo_almost_full: std_logic;
signal fifo_write_enable: std_logic;
signal fifo_quad_full: std_logic;
signal fifo_half_full: std_logic;
-- signal readclk: std_logic:='0';
signal fifo_clear: std_logic:='0';
signal read_enable: std_logic:='0';
signal fifo_write, read: std_logic_vector(31 downto 0);
signal fifo_empty: std_logic;
signal char_wb_dat_o: std_logic_vector(31 downto 0);
signal char_wb_dat_i: std_logic_vector(31 downto 0);
signal char_wb_adr_i: std_logic_vector(31 downto 2);
signal char_wb_cyc_i: std_logic;
signal char_wb_stb_i: std_logic;
signal char_wb_ack_o: std_logic;
-- Mem size: 614400 bytes.
-- Page:
signal membase: std_logic_vector(31 downto 0) := (others => '0');
--signal palletebase: std_logic_vector(31 downto 0) := (others => '0');
type state_type is (
idle,
fill
);
type vgaregs_type is record
state: state_type;
chars: std_logic_vector(31 downto 0);
hptr: integer range 0 to 639; -- horizontal counter
hoff: unsigned(4 downto 0);
voff: unsigned(4 downto 0);
memptr: unsigned(31 downto 0);
-- read_memptr: unsigned(31 downto 0);
rburst, wburst: integer;
bcnt: integer;-- range 0 to 4; -- 5 bursts of 16 = 80 words = 320 bytes.
-- Wishbone
cyc: std_logic;
stb: std_logic;
adr: std_logic_vector(31 downto 0);
odd: std_logic;
end record;
signal r: vgaregs_type;
--# 640x480 @ 72Hz (VESA) hsync: 37.9kHz
--ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
--# 640x480 @ 75Hz (VESA) hsync: 37.5kHz
--ModeLine "640x480" 31.5 640 656 720 840 480 481 484 500 -hsync -vsync
--# 640x480 @ 85Hz (VESA) hsync: 43.3kHz
--ModeLine "640x480" 36.0 640 696 752 832 480 481 484 509 -hsync -vsync
--# 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
--ModeLine "640x480" 25.2 640 656 752 800 480 490 492 525 -hsync -vsync
constant VGA_H_BORDER: integer := 0;
--constant VGA_H_SYNC: integer := 40;
constant VGA_H_SYNC: integer := 96;
--constant VGA_H_FRONTPORCH: integer := 24+VGA_H_BORDER;
constant VGA_H_FRONTPORCH: integer := 16+VGA_H_BORDER;
constant VGA_H_DISPLAY: integer := 640 - (2*VGA_H_BORDER);
--constant VGA_H_BACKPORCH: integer := 128+VGA_H_BORDER;
constant VGA_H_BACKPORCH: integer := 48+VGA_H_BORDER;
constant VGA_V_BORDER: integer := 0;
--constant VGA_V_FRONTPORCH: integer := 29+VGA_V_BORDER;
constant VGA_V_FRONTPORCH: integer := 10+VGA_V_BORDER;
constant VGA_V_SYNC: integer := 2;
constant VGA_V_DISPLAY: integer := 480 - (2*VGA_V_BORDER);
constant VGA_V_BACKPORCH: integer := 33+VGA_V_BORDER;
-- constant VGA_H_BORDER: integer := 0;
-- constant VGA_H_SYNC: integer := 2;
-- constant VGA_H_FRONTPORCH: integer := 2;
-- constant VGA_H_DISPLAY: integer := 128;
-- constant VGA_H_BACKPORCH: integer := 2;
-- constant VGA_V_BORDER: integer := 0;
-- constant VGA_V_FRONTPORCH: integer := 2;
-- constant VGA_V_SYNC: integer := 2;
-- constant VGA_V_DISPLAY: integer := 192;
-- constant VGA_V_BACKPORCH: integer := 2;
constant VGA_HCOUNT: integer :=
VGA_H_SYNC + VGA_H_FRONTPORCH + VGA_H_DISPLAY + VGA_H_BACKPORCH;
constant VGA_VCOUNT: integer :=
VGA_V_SYNC + VGA_V_FRONTPORCH + VGA_V_DISPLAY + VGA_V_BACKPORCH;
constant v_polarity: std_logic := '1';
constant h_polarity: std_logic := '1';
-- Pixel counters
signal hcount_q: integer range 0 to VGA_HCOUNT;
signal vcount_q: integer range 0 to VGA_VCOUNT;
signal h_sync_tick: std_logic;
signal vgarst: std_logic := '0';
signal rstq1: std_logic:='1';
signal rstq2: std_logic;
signal v_display: std_logic;
signal v_display_in_wbclk: std_logic;
signal v_display_q: std_logic;
--signal v_border: std_logic;
signal cache_clear: std_logic;
signal vga_reset_q1, vga_reset_q2: std_logic;
signal rdly: std_logic;
signal hdup: std_logic := '1';
signal hflip: std_logic;
constant BURST_SIZE: integer := 16;
signal palleteen_wb: std_logic;
signal palleteread_wb: std_logic_vector(23 downto 0);
signal palleteen: std_logic;
signal pallete_address: std_logic_vector(7 downto 0);
signal pallete_data: std_logic_vector(23 downto 0);
signal rsel: unsigned(1 downto 0);
begin
palleteinst: generic_dp_ram
generic map (
address_bits => 8,
data_bits => 24
)
port map (
clka => wb_clk_i,
ena => palleteen_wb,
wea => wb_we_i,
addra => wb_adr_i(9 downto 2),
dia => wb_dat_i(23 downto 0),
doa => palleteread_wb,
clkb => vgaclk,
enb => palleteen,
web => '0',
addrb => pallete_address,
dib => (others =>'X'),
dob => pallete_data
);
-- Wishbone register access
--id <= x"08" & x"1A"; -- Vendor: ZPUIno Product: VGA 640x480 16-bit
mi_wb_dat_o <= (others => 'X');
mi_wb_we_o <= '0';
process(wb_adr_i)
variable r: unsigned(15 downto 0);
begin
wb_dat_o(31 downto 0) <= (others => '0');
if wb_adr_i(10)='1' then
wb_dat_o(23 downto 0) <= palleteread_wb;
else
case wb_adr_i(3 downto 2) is
when "00" =>
wb_dat_o(0) <= v_display_in_wbclk;
when "01" =>
r := to_unsigned(VGA_H_DISPLAY,16);
wb_dat_o(31 downto 16) <= std_logic_vector(r);
r := to_unsigned(VGA_V_DISPLAY,16);
wb_dat_o(15 downto 0) <= std_logic_vector(r);
when "10" =>
-- Pixel format
when others =>
end case;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
rdly<='0';
wb_ack_o<='0';
else
palleteen_wb<='0';
if rdly='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
if wb_we_i='1' then
if wb_adr_i(10)='0' then
case wb_adr_i(3 downto 2) is
when "00" =>
membase(31 downto 0) <= wb_dat_i(31 downto 0);
when "01" =>
--palletebase(maxAddrBit downto 0) <= wb_dat_i(maxAddrBit downto 0);
when others =>
end case;
else
-- Pallete access
palleteen_wb<='1';
end if;
end if;
wb_ack_o<='1';
rdly <= '1';
end if;
else
rdly <= '0';
wb_ack_o<='0';
end if;
end if;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (vcount_q < VGA_V_DISPLAY) then
v_display_in_wbclk <= '1';
else
v_display_in_wbclk <= '0';
end if;
end if;
end process;
mi_wb_stb_o <= r.stb;
mi_wb_cyc_o <= r.cyc;
-- mi_wb_adr_o <= r.adr;
mi_wb_adr_o <= std_logic_vector( r.memptr(31 downto 0) );
process(wb_clk_i, wb_rst_i, r, mi_wb_ack_i, mi_wb_dat_i,membase)
variable w: vgaregs_type;
begin
fifo_write_enable<='0';
w := r;
if wb_rst_i='1' then
w.state := idle;
fifo_clear <='1';
w.hptr := 0;
w.hoff := (others =>'0');
w.voff := (others =>'0');
w.cyc := '0';
w.stb := '0';
w.adr := (others => 'X');
w.odd := '0';
w.bcnt := 4;
else
fifo_clear<='0';
case r.state is
when idle =>
-- If we can proceed to FIFO fill, do it
if fifo_almost_full='0' and vga_reset_q1='0'then
w.state := fill;
w.rburst := BURST_SIZE-1;
w.wburst := BURST_SIZE;
w.stb :='1';
w.cyc :='1';
end if;
if vga_reset_q1='1' then
fifo_clear<='1';
w.odd := '0';
w.bcnt := 4;
w.memptr := unsigned(membase);
end if;
when fill =>
w.cyc := '1';
if r.wburst/=0 then
w.stb := '1';
else
w.stb := '0';
end if;
fifo_write_enable <= mi_wb_ack_i;
if (mi_wb_stall_i='0' and r.wburst/=0) then
w.memptr := r.memptr + 4; -- 160
w.wburst := r.wburst - 1;
end if;
if mi_wb_ack_i='1' then
w.rburst := r.rburst -1;
if r.rburst=0 then
w.state := idle;
w.stb := '0';
w.cyc := '0';
w.bcnt := r.bcnt - 1;
-- End of line burst ?
if r.bcnt=0 then
-- Yes, reset address.
w.bcnt := 4;
w.odd := not r.odd;
if r.odd='0' then
w.memptr := r.memptr - 320;
end if;
end if;
end if;
end if;
when others =>
end case;
end if;
fifo_write <= mi_wb_dat_i;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
--
--
-- VGA part
--
--
process(vgaclk, wb_rst_i)
begin
if wb_rst_i='1' then
rstq1 <= '1';
rstq2 <= '1';
elsif rising_edge(vgaclk) then
rstq1 <= rstq2;
rstq2 <= '0';
end if;
end process;
vgarst <= rstq1;
hcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
hcount_q <= VGA_H_DISPLAY + VGA_H_BACKPORCH - 1;
else
if hcount_q = VGA_HCOUNT then
hcount_q <= 0;
else
hcount_q <= hcount_q + 1;
end if;
end if;
end if;
end process;
process(hcount_q, vcount_q)
begin
if hcount_q < VGA_H_DISPLAY and vcount_q < VGA_V_DISPLAY then
v_display<='1';
else
v_display<='0';
end if;
end process;
process(vgaclk)
begin
if rising_edge(vgaclk) then
v_display_q <= v_display;
end if;
end process;
hsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_hsync<=h_polarity;
else
h_sync_tick <= '0';
if hcount_q = (VGA_H_DISPLAY + VGA_H_FRONTPORCH) then
h_sync_tick <= '1';
vga_hsync <= not h_polarity;
elsif hcount_q = (VGA_HCOUNT - VGA_H_BACKPORCH) then
vga_hsync <= h_polarity;
end if;
end if;
end if;
end process;
vcounter: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vcount_q <= VGA_V_DISPLAY + VGA_V_BACKPORCH - 1;
else
if vcount_q = VGA_VCOUNT then
vcount_q <= 0;
report "V finished" severity note;
else
if h_sync_tick='1' then
vcount_q <= vcount_q + 1;
end if;
end if;
end if;
end if;
end process;
-- Cache clear.
vclear: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
cache_clear <= '1';
else
cache_clear<='0';
if not (vcount_q < VGA_V_DISPLAY) then
cache_clear <='1';
end if;
end if;
end if;
end process;
vsyncgen: process(vgaclk)
begin
if rising_edge(vgaclk) then
if vgarst='1' then
vga_vsync<=v_polarity;
else
if vcount_q = (VGA_V_DISPLAY + VGA_V_FRONTPORCH) then
vga_vsync <= not v_polarity;
elsif vcount_q = (VGA_VCOUNT - VGA_V_BACKPORCH) then
vga_vsync <= v_polarity;
end if;
end if;
end if;
end process;
-- Synchronous output
process(vgaclk)
begin
if rising_edge(vgaclk) then
if v_display='0' then
vga_b <= (others => '0');
vga_r <= (others => '0');
vga_g <= (others => '0');
blank <= '1';
else
blank <= '0';
--if hflip='1' then
vga_r <= pallete_data(7 downto 0+3);
vga_g <= pallete_data(15 downto 8+3);
vga_b <= pallete_data(23 downto 16+3);
-- synthesis translate_off
vga_b <= pallete_data(7-3 downto 0);
vga_r <= pallete_data(15-3 downto 8);
vga_g <= pallete_data(23-3 downto 16);
-- synthesis translate_on
--else
--vga_b <= read(19 downto 15);
--vga_r <= read(24 downto 20);
--vga_g <= read(29 downto 25);
--end if;
end if;
end if;
end process;
process(wb_clk_i,cache_clear)
begin
if cache_clear='1' then
vga_reset_q1<='1';
vga_reset_q2<='1';
elsif rising_edge(wb_clk_i) then
vga_reset_q2<='0';
vga_reset_q1<=vga_reset_q2;
end if;
end process;
-- read_enable <= v_display and not hflip;
read_enable<='1' when (v_display='1' and hflip='1' and rsel="11") else '0';
palleteen <= '1';
process(read,rsel)
begin
case rsel is
when "00" => pallete_address<=read(31 downto 24);
when "01" => pallete_address<=read(23 downto 16);
when "10" => pallete_address<=read(15 downto 8);
when "11" => pallete_address<=read(7 downto 0);
when others => null;
end case;
end process;
process(vgaclk)
begin
if rising_edge(vgaclk) then
if v_display='1' and v_display_q='0' then
hflip <= '1';
else
if v_display='0' then
hflip <='0';
rsel<="00";
else
hflip <= hflip xor hdup;
if hflip='0' then
if rsel="11" then
rsel<="00";
else
rsel<=rsel+1;
end if;
end if;
end if;
end if;
end if;
end process;
myfifo: gh_fifo_async_rrd_sr_wf
generic map (
data_width => 32,
add_width => 8
)
port map (
clk_WR => wb_clk_i,
clk_RD => vgaclk,
rst => '0',
srst => fifo_clear,
WR => fifo_write_enable,
RD => read_enable,
D => fifo_write,
Q => read,
empty => fifo_empty,
qfull => fifo_quad_full,
hfull => fifo_half_full,
qqqfull => fifo_almost_full,
full => fifo_full
);
end behave;
| bsd-3-clause | 85cca06aae2c67d58cd5f3cd97933c54 | 0.539847 | 3.128205 | false | false | false | false |
keith-epidev/md2x | build/code/logic_unit.vhdl | 1 | 640 | library ieee;
use ieee.std_logic_1164.all;
entity logic_unit is
port (
A,B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0)
);
end logic_unit;
architecture arch of logic_unit is
signal F_buffer: std_logic_vector(7 downto 0);
begin
process(mode,A,B)
begin
case(mode) is
when "00" =>
F_buffer <= A;
when "01" =>
F_buffer <= A or B;
when "10" =>
F_buffer <= A xor B;
when others =>
F_buffer <= A and B;
end case;
end process;
with Cin select
F <= not F_buffer when '1',
F_buffer when others;
end arch;
| gpl-2.0 | e4e4b252ce9725533e12cda91cc1252e | 0.620313 | 2.612245 | false | false | false | false |
alvieboy/xtc-base | wb_singleport_ram.vhd | 1 | 2,973 | --
-- Wishbone VGA controller character RAM.
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity wb_singleport_ram is
generic (
bits: natural := 8
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end entity wb_singleport_ram;
architecture behave of wb_singleport_ram is
subtype ramword is std_logic_vector(31 downto 0);
type ramtype is array(0 to ((2**bits)-1)) of ramword;
shared variable ram: ramtype;
signal selected: std_logic;
signal ack: std_logic;
begin
selected <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0';
wb_inta_o <= '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack<='0';
else
ack <= '0';
if selected='1' and ack='0' then
ack <= '1';
end if;
end if;
end if;
end process;
wb_ack_o <= ack;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if selected='1' then
if wb_we_i='1' then
ram(conv_integer(wb_adr_i(bits+1 downto 2))):=wb_dat_i;
end if;
wb_dat_o <= ram(conv_integer(wb_adr_i(bits+1 downto 2)));
end if;
end if;
end process;
end behave;
| bsd-3-clause | 45b09fecd4e40cb9c9cc0e21e3ba8296 | 0.664985 | 3.389966 | false | false | false | false |
EPiCS/reconos | demos/reconf_sort_matrix/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/matrixmultiplier.vhd | 2 | 4,381 | ------------------------------------------------------------------------------
-- matrixmultiplier - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: matrixmultiplier
-- Version: 2.00.a
-- Description: matrix multiplier(VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to 31);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to 31);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to 31);
o_RAM_C_WE : out std_logic
);
--attribute USE_DSP48 : string;
--attribute USE_DSP48 of matrixmultiplier : entity is "no";
end matrixmultiplier;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture Behavioral of matrixmultiplier is
type STATE_TYPE is (
STATE_IDLE,
STATE_LOAD,
STATE_LOAD_WAIT,
STATE_SUM,
STATE_DELAY_1,
STATE_DELAY_2,
STATE_STORE,
STATE_STORE_WAIT,
STATE_FINISH_CYCLE
);
signal state : STATE_TYPE;
signal temp : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
signal prod,delay : std_logic_vector(0 to G_RAM_DATA_WIDTH-1);
begin
multiply : process(clk, reset, start) is
variable j : integer := 0;
variable k : integer := 0;
begin
if (reset = '1') then
done <= '0';
o_RAM_A_Addr <= (others=>'0');
o_RAM_B_Addr <= (others=>'0');
o_RAM_C_Addr <= (others=>'0');
o_RAM_C_Data <= (others=>'0');
o_RAM_C_WE <= '0';
state <= STATE_IDLE;
elsif (clk'event and clk = '1') then
o_RAM_C_WE <= '0';
o_RAM_C_Data <= (others=>'0');
case state is
when STATE_IDLE =>
done <= '0';
if (start = '1') then
j := 0;
k := 0;
temp <= (others=>'0');
state <= STATE_LOAD;
end if;
when STATE_LOAD =>
o_RAM_A_Addr <= conv_std_logic_vector(integer(k), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_B_Addr <= conv_std_logic_vector(integer(k*G_LINE_LEN_MATRIX+j), G_RAM_ADDR_WIDTH_MATRIX_B);
k := k + 1;
state <= STATE_LOAD_WAIT;
when STATE_LOAD_WAIT =>
state <= STATE_DELAY_1;
when STATE_DELAY_1 =>
state <= STATE_DELAY_2;
when STATE_DELAY_2 =>
state <= STATE_SUM;
when STATE_SUM =>
temp <= temp + prod;
if (k = G_LINE_LEN_MATRIX) then
k := 0;
state <= STATE_STORE;
else
state <= STATE_LOAD;
end if;
when STATE_STORE =>
o_RAM_C_Addr <= conv_std_logic_vector(integer(j), G_RAM_ADDR_WIDTH_MATRIX_A_C);
o_RAM_C_WE <= '1';
o_RAM_C_Data <= temp;
state <= STATE_STORE_WAIT;
when STATE_STORE_WAIT =>
o_RAM_C_WE <= '0';
state <= STATE_FINISH_CYCLE;
when STATE_FINISH_CYCLE =>
j := j + 1;
if (j = G_LINE_LEN_MATRIX) then
j := 0;
done <= '1';
state <= STATE_IDLE;
else
temp <= (others => '0');
state <= STATE_LOAD;
end if;
end case;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
delay <= conv_std_logic_vector(signed(i_RAM_A_Data)*signed(i_RAM_B_Data),G_RAM_DATA_WIDTH);
prod <= delay;
end if;
end process;
end Behavioral;
| gpl-2.0 | 76505c9957e6382bdf2ee5eed13dd8da | 0.505821 | 3.021379 | false | false | false | false |
alvieboy/xtc-base | tracer.vhd | 1 | 1,536 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.xtcpkg.all;
use work.txt_util.all;
entity tracer is
generic (
trace_file: string := "trace.txt"
);
port (
clk: in std_logic;
dbgi: in execute_debug_type
);
end entity tracer;
architecture sim of tracer is
file t_file : TEXT open write_mode is trace_file;
signal clock: unsigned(31 downto 0) := (others => '0');
begin
logger: process(clk)
variable executed: string(1 to 1);
variable op: string(1 to 8);
begin
if rising_edge(clk) then
clock <= clock + 1;
if dbgi.valid then
if dbgi.executed then
executed := "E";
else
executed := " ";
end if;
if dbgi.dual then
op := hstr(dbgi.opcode2) & hstr(dbgi.opcode1);
else
op := hstr(dbgi.opcode2) & " ";
end if;
if TRACECLOCK then
print( t_file, executed & " 0x" & hstr(std_logic_vector(clock)) & " 0x" &
hstr(std_logic_vector(dbgi.pc)) & " 0x" & op & " 0x"
& hstr(std_logic_vector(dbgi.lhs))
& " 0x" & hstr(std_logic_vector(dbgi.rhs))
);
else
print( t_file, executed & " 0x" &
hstr(std_logic_vector(dbgi.pc)) & " 0x" & op & " 0x"
& hstr(std_logic_vector(dbgi.lhs))
& " 0x" & hstr(std_logic_vector(dbgi.rhs))
);
end if;
end if;
end if;
end process;
end sim;
| bsd-3-clause | 56b645c6d6620028402d2257c606f967 | 0.540365 | 3.226891 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriagx_atoms.vhd | 1 | 672,016 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package arriagx_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE arriagx_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end arriagx_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body arriagx_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end arriagx_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package arriagx_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end arriagx_pllpack;
package body arriagx_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end arriagx_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
entity arriagx_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriagx_dffe : entity is TRUE;
end arriagx_dffe;
-- architecture body --
architecture behave of arriagx_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- arriagx_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriagx_atom_pack.all;
entity arriagx_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of arriagx_mux21 : entity is TRUE;
end arriagx_mux21;
architecture AltVITAL of arriagx_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriagx_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriagx_atom_pack.all;
entity arriagx_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_mux41 : entity is TRUE;
end arriagx_mux41;
architecture AltVITAL of arriagx_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriagx_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriagx_atom_pack.all;
-- entity declaration --
entity arriagx_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriagx_and1 : entity is TRUE;
end arriagx_and1;
-- architecture body --
architecture AltVITAL of arriagx_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : arriagx_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END arriagx_ram_register;
ARCHITECTURE reg_arch OF arriagx_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : arriagx_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF arriagx_ram_pulse_generator:ENTITY IS TRUE;
END arriagx_ram_pulse_generator;
ARCHITECTURE pgen_arch OF arriagx_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE work.arriagx_ram_register;
USE work.arriagx_ram_pulse_generator;
ENTITY arriagx_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriagx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END arriagx_ram_block;
ARCHITECTURE block_arch OF arriagx_ram_block IS
COMPONENT arriagx_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriagx_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : arriagx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : arriagx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : arriagx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : arriagx_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : arriagx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : arriagx_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : arriagx_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : arriagx_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : arriagx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : arriagx_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : arriagx_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : arriagx_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : arriagx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : arriagx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : arriagx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : arriagx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : arriagx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : arriagx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-------------------------------------------------------------------
--
-- Entity Name : arriagx_jtag
--
-- Description : StratixIIGXLITE JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriagx_atom_pack.all;
entity arriagx_jtag is
generic (
lpm_type : string := "arriagx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end arriagx_jtag;
architecture architecture_jtag of arriagx_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : arriagx_crcblock
--
-- Description : StratixIIGXLITE CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriagx_atom_pack.all;
entity arriagx_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "arriagx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end arriagx_crcblock;
architecture architecture_crcblock of arriagx_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : arriagx_asmiblock
--
-- Description : StratixIIGXLITEIIGXLITE ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriagx_atom_pack.all;
entity arriagx_asmiblock is
generic (
lpm_type : string := "arriagx_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end arriagx_asmiblock;
architecture architecture_asmiblock of arriagx_asmiblock is
begin
process(dclkin, scein, sdoin, oe)
begin
end process;
end architecture_asmiblock; -- end of arriagx_asmiblock
---------------------------------------------------------------------
--
-- Entity Name : arriagx_lcell_ff
--
-- Description : StratixIIGXLITE LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_and1;
entity arriagx_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "arriagx_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_lcell_ff : entity is TRUE;
end arriagx_lcell_ff;
architecture vital_lcell_ff of arriagx_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal adatasdata_ipd : std_logic;
signal adatasdata_dly : std_logic;
signal adatasdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component arriagx_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: arriagx_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
adatasdatadelaybuffer: arriagx_and1
port map(IN1 => adatasdata_ipd,
Y => adatasdata_dly);
adatasdatadelaybuffer1: arriagx_and1
port map(IN1 => adatasdata_dly,
Y => adatasdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (adatasdata_ipd, adatasdata, tipd_adatasdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, adatasdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_adatasdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_adatasdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(aload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_adatasdata_clk,
TimingData => TimingData_adatasdata_clk,
TestSignal => adatasdata_ipd,
TestSignalName => "ADATASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_adatasdata_clk_noedge_posedge,
SetupLow => tsetup_adatasdata_clk_noedge_posedge,
HoldHigh => thold_adatasdata_clk_noedge_posedge,
HoldLow => thold_adatasdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_adatasdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (aload_ipd = '1') then
iregout := adatasdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := adatasdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (adatasdata_ipd'last_event, tpd_adatasdata_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : arriagx_lcell_comb
--
-- Description : StratixIIGXLITE LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
entity arriagx_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "arriagx_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_lcell_comb : entity is TRUE;
end arriagx_lcell_comb;
architecture vital_lcell_comb of arriagx_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_ena_reg : entity is TRUE;
end arriagx_ena_reg;
ARCHITECTURE behave of arriagx_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/ENA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for StratixIIGXLITE CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- ARRIAGX_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_ena_reg;
entity arriagx_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriagx_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_clkctrl : entity is TRUE;
end arriagx_clkctrl;
architecture vital_clkctrl of arriagx_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component arriagx_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : arriagx_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
outclk <= cereg_out AND clkmux_out;
end vital_clkctrl;
--
--
-- ARRIAGX_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
entity arriagx_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
dqs_input_frequency : STRING := "10000 ps";
dqs_out_mode : STRING := "none";
dqs_delay_buffer_mode : STRING := "low";
dqs_phase_shift : INTEGER := 0;
dqs_offsetctrl_enable : STRING := "false";
dqs_ctrl_latches_enable : STRING := "false";
dqs_edge_detect_enable : STRING := "false";
gated_dqs : STRING := "false";
sim_dqs_intrinsic_delay : INTEGER := 0;
sim_dqs_delay_increment : INTEGER := 0;
sim_dqs_offset_increment : INTEGER := 0;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_regin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_dqsupdateen : VitalDelayType01 := DefPropDelay01;
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01));
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of arriagx_asynch_io : entity is TRUE;
end arriagx_asynch_io;
architecture behave of arriagx_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_in : std_logic_vector(5 downto 0);
signal offsetctrlin_in : std_logic_vector(5 downto 0);
signal dqsupdateen_in : std_logic;
signal dqs_delay_int : integer := 0;
signal tmp_dqsbusout : std_logic;
signal dqs_ctrl_latches_ena : std_logic := '1';
signal combout_tmp_sig : std_logic := '0';
signal dqsbusout_tmp_sig : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_in(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (delayctrlin_in(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_in(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_in(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_in(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_in(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
VitalWireDelay (offsetctrlin_in(5), offsetctrlin(5), tipd_offsetctrlin(5));
VitalWireDelay (offsetctrlin_in(4), offsetctrlin(4), tipd_offsetctrlin(4));
VitalWireDelay (offsetctrlin_in(3), offsetctrlin(3), tipd_offsetctrlin(3));
VitalWireDelay (offsetctrlin_in(2), offsetctrlin(2), tipd_offsetctrlin(2));
VitalWireDelay (offsetctrlin_in(1), offsetctrlin(1), tipd_offsetctrlin(1));
VitalWireDelay (offsetctrlin_in(0), offsetctrlin(0), tipd_offsetctrlin(0));
end block;
dqs_ctrl_latches_ena <= '1' when dqs_ctrl_latches_enable = "false" ELSE
dqsupdateen_in when dqs_edge_detect_enable = "false" ELSE
(not (combout_tmp_sig xor tmp_dqsbusout) and dqsupdateen_in);
process(delayctrlin_in, offsetctrlin_in, dqs_ctrl_latches_ena)
variable tmp_delayctrl : integer := 0;
variable tmp_offsetctrl : integer := 0;
begin
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
tmp_delayctrl := 31;
else
tmp_delayctrl := alt_conv_integer(delayctrlin_in);
end if;
if (dqs_offsetctrl_enable = "true") then
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
tmp_offsetctrl := 31;
else
tmp_offsetctrl := alt_conv_integer(offsetctrlin_in);
end if;
else
tmp_offsetctrl := 0;
end if;
if (dqs_ctrl_latches_ena = '1') THEN
dqs_delay_int <= sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
end if;
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
assert false report "OFFSETCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
end process;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, tmp_dqsbusout)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable dqsbusout_tmp : std_logic;
variable combout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
tmp_dqsbusout <= transport tmp_combout after (dqs_delay_int * 1 ps);
if (gated_dqs = "true") then
dqsbusout_tmp := tmp_dqsbusout AND regin;
else
dqsbusout_tmp := tmp_dqsbusout;
end if;
-- for dqs delay ctrl latches enable
dqsbusout_tmp_sig <= dqsbusout_tmp;
combout_tmp_sig <= tmp_combout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => dqsbusout_tmp,
Paths => (1 => (tmp_dqsbusout'last_event, tpd_padio_dqsbusout, TRUE),
2 => (regin'last_event, tpd_regin_dqsbusout, gated_dqs = "true")),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- ARRIAGX_IO_REGISTER
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
entity arriagx_io_register is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_io_register : entity is TRUE;
end arriagx_io_register;
architecture vital_io_reg of arriagx_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--
-- ARRIAGX_IO_LATCH
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
entity arriagx_io_latch is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_io_latch : entity is TRUE;
end arriagx_io_latch;
architecture vital_io_latch of arriagx_io_latch is
attribute VITAL_LEVEL0 of vital_io_latch : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd = '1') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_latch;
--
-- ARRIAGX_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_asynch_io;
use work.arriagx_io_register;
use work.arriagx_io_latch;
use work.arriagx_mux21;
use work.arriagx_and1;
entity arriagx_io is
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "arriagx_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end arriagx_io;
architecture structure of arriagx_io is
component arriagx_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component arriagx_io_register
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component arriagx_io_latch
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component arriagx_mux21
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component arriagx_and1
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
begin
not_inclk <= (ddioinclk) WHEN (ddioinclk_input = "dqsb_bus") ELSE (not inclk);
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : arriagx_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map ( regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio0_reg
in_ddio0_reg : arriagx_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map (regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio1_latch
in_ddio1_reg : arriagx_io_latch
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => "none", -- this register does not have sync_reset
POWER_UP => input_power_up)
port map (regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn);
-- out_reg
out_reg : arriagx_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- out ddio reg
out_ddio_reg : arriagx_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe reg
oe_reg : arriagx_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe_pulse reg
oe_pulse_reg : arriagx_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : arriagx_and1
port map (Y => outclk_delayed,
IN1 => outclk);
ddio_data_mux : arriagx_mux21
port map (MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : arriagx_asynch_io
generic map ( OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
dqs_input_frequency => dqs_input_frequency,
dqs_out_mode => dqs_out_mode,
dqs_delay_buffer_mode => dqs_delay_buffer_mode,
dqs_phase_shift => dqs_phase_shift,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
dqs_edge_detect_enable => dqs_edge_detect_enable,
gated_dqs => gated_dqs,
sim_dqs_intrinsic_delay => sim_dqs_intrinsic_delay,
sim_dqs_delay_increment => sim_dqs_delay_increment,
sim_dqs_offset_increment => sim_dqs_offset_increment)
port map( datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
padio => padio,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
dqsbusout => dqsbusout,
combout => combout,
regout => regout,
ddioregout => ddioregout);
end structure;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_m_cntr
--
-- Description : Timing simulation model for the M counter. M is the loop
-- feedback counter of the StratixIIGXLITE PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriagx_m_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END arriagx_m_cntr;
ARCHITECTURE behave of arriagx_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_n_cntr
--
-- Description : Timing simulation model for the N counter. N is the
-- input counter of the StratixIIGXLITE PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriagx_n_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END arriagx_n_cntr;
ARCHITECTURE behave of arriagx_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixIIGXLITE PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriagx_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END arriagx_scale_cntr;
ARCHITECTURE behave of arriagx_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY arriagx_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end arriagx_pll_reg;
ARCHITECTURE behave of arriagx_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_pll
--
-- Description : Timing simulation model for the StratixIIGXLITE PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.arriagx_atom_pack.all;
USE work.arriagx_pllpack.all;
USE work.arriagx_m_cntr;
USE work.arriagx_n_cntr;
USE work.arriagx_scale_cntr;
USE work.arriagx_dffe;
USE work.arriagx_pll_reg;
ENTITY arriagx_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriagx_pll";
-- Simulation only generics
family_name : string := "StratixIIGXLITE";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
-- lvds specific ports
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END arriagx_pll;
ARCHITECTURE vital_pll of arriagx_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT GATE_LOCK_CYCLES : integer := 7;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_out_last_value : std_logic_vector(7 downto 0);
signal vco_tap_last_value : std_logic_vector(7 downto 0);
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
--signal tap0_is_active : boolean := true;
signal sig_quiet_time : time := 0 ps;
signal sig_slowest_clk_old : time := 0 ps;
signal sig_slowest_clk_new : time := 0 ps;
signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
COMPONENT arriagx_m_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT arriagx_n_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT arriagx_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT arriagx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT arriagx_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanread_ipd, scanread, tipd_scanread);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (scanwrite_ipd, scanwrite, tipd_scanwrite);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
inclk_m <= clkin when m_test_source = 0 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or
c1_test_source /= 5 or c2_test_source /= 5 or
c3_test_source /= 5 or c4_test_source /= 5 or
c5_test_source /= 5 else
false;
m1 : arriagx_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : arriagx_n_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= clkin when c0_test_source = 0 else
refclk when c0_test_source = 1 else
inclk_c_from_vco(0);
c0 : arriagx_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= clkin when c1_test_source = 0 else
fbclk when c1_test_source = 2 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : arriagx_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= clkin when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : arriagx_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : arriagx_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : arriagx_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : arriagx_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (sim_gate_lock_device_behavior = "on") then
if (count = gate_lock_counter) then
output := '1';
end if;
elsif (count = GATE_LOCK_CYCLES) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
if (refclk_int > (refclk_int * max_modulus / m_mod)) then
q_period := refclk_int * 1 ps;
else
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
sig_m_val_tmp <= m_val_tmp;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0),
c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5),
sig_refclk_period, m_val_tmp(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
sig_quiet_time <= quiet_time;
sig_slowest_clk_old <= slowest_clk_old;
sig_slowest_clk_new <= slowest_clk_new;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanwrite_enabled = '1') then
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = x) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end loop;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x)) then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
inclk_c_from_vco(i) <= vco_tap(x);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
end if;
end loop;
if (m_ph_val = x) then
inclk_m_from_vco <= vco_tap(x);
end if;
vco_tap_last_value(x) <= vco_tap(x);
end if;
end loop;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_posedge,
SetupLow => tsetup_scandata_scanclk_noedge_posedge,
HoldHigh => thold_scandata_scanclk_noedge_posedge,
HoldLow => thold_scandata_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriagx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanread_scanclk,
TimingData => TimingData_scanread_scanclk,
TestSignal => scanread_ipd,
TestSignalName => "scanread",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanread_scanclk_noedge_posedge,
SetupLow => tsetup_scanread_scanclk_noedge_posedge,
HoldHigh => thold_scanread_scanclk_noedge_posedge,
HoldLow => thold_scanread_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriagx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanwrite_scanclk,
TimingData => TimingData_scanwrite_scanclk,
TestSignal => scanwrite_ipd,
TestSignalName => "scanwrite",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanwrite_scanclk_noedge_posedge,
SetupLow => tsetup_scanwrite_scanclk_noedge_posedge,
HoldHigh => thold_scanwrite_scanclk_noedge_posedge,
HoldLow => thold_scanwrite_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriagx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable pll_is_disabled : boolean := false;
variable next_vco_sched_time : time := 0 ps;
variable tap0_is_active : boolean := true;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
pll_is_in_reset := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
pll_is_disabled := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
if (ena_ipd'event and ena_ipd = '1') then
assert false report family_name & " PLL is enabled" severity note;
pll_is_disabled := false;
if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- illegal value on areset_ipd
if (areset_ipd'event and areset_ipd = 'X') then
assert false report "Illegal value 'X' detected on ARESET input" severity warning;
end if;
if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
-- first_schedule := true;
-- vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
-- reset all counter phase taps to POF programmed values
end if;
if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap0
vco_out(0) <= transport vco_val after sched_time;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap 0
vco_out(0) <= transport vco_val after sched_time;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
next_vco_sched_time := now + sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- now schedule the other taps with the appropriate phase-shift
if (vco_out(0)'event) then
for k in 1 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_out(0) after phase_shift(k);
end loop;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped : do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
-- check which vco_tap has event
for x in 0 to 7 loop
if (vco_out(x) /= vco_out_last_value(x)) then
-- TAP X has event
if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then
if (vco_out(0) = '1') then
tap0_is_active := true;
end if;
if (tap0_is_active) then
vco_tap(0) <= vco_out(0);
end if;
elsif (tap0_is_active) then
vco_tap(x) <= vco_out(x);
end if;
if (sig_stop_vco = '1') then
vco_tap(x) <= '0';
end if;
vco_out_last_value(x) <= vco_out(x);
end if;
end loop;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process SCHEDULE;
clk0_tmp <= c_clk(i_clk0_counter);
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
scandataout <= scandataout_tmp;
scandone <= scandone_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriagx_mac_bit_register
--
-- Description : a single bit register. This is used for registering all
-- single bit input ports.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_bit_register IS
GENERIC (
power_up : std_logic := '0';
tipd_data : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0'
);
END arriagx_mac_bit_register;
ARCHITECTURE arch OF arriagx_mac_bit_register IS
SIGNAL data_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic := '0';
SIGNAL viol_notifier : std_logic := '0';
SIGNAL data_dly : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
clk_delay: process (data_ipd)
begin
data_dly <= data_ipd;
end process;
PROCESS (data_dly, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_reg : STD_LOGIC := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg := data_dly;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg := '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
end if;
end if;
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_REGISTER
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_register IS
GENERIC (
data_width : integer := 18;
power_up : std_logic := '0';
tipd_data : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END arriagx_mac_register;
ARCHITECTURE arch OF arriagx_mac_register IS
SIGNAL data_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL viol_notifier : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
PROCESS (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg <= data_ipd;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg <= (others => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
end if;
end if;
END PROCESS;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_reg(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_reg(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_RS_BLOCK
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_rs_block IS
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END arriagx_mac_rs_block;
ARCHITECTURE arch OF arriagx_mac_rs_block IS
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tbuf : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_mult : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dly : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturated : std_logic := '0';
SIGNAL min : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL max : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL msb : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
round_ipd <= round ;
saturate_ipd <= saturate ;
addnsub_ipd <= addnsub ;
signa_ipd <= signa ;
signb_ipd <= signb ;
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
datain_ipd(71 downto 0) <= datain(71 downto 0) ;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
addnsub_ipd,
round_ipd)
VARIABLE dataout_round_tmp2 : std_logic_vector(71 DOWNTO 0);
BEGIN
IF (round_ipd = '1') THEN
dataout_round_tmp2 := datain_ipd + (2 **(conv_integer(dataoutsize - signsize - roundsize - "00000001")));
ELSE
dataout_round_tmp2 := datain_ipd;
END IF;
dataout_round <= dataout_round_tmp2;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
addnsub_ipd,
dataout_round)
VARIABLE dataout_saturate_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE saturated_tmp4 : std_logic := '0';
VARIABLE gnd : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE min_tmp5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE max_tmp6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE msb_tmp7 : std_logic := '0';
VARIABLE i : integer;
BEGIN
IF (saturate_ipd = '1') THEN
IF (block_type = "mac_mult") THEN
IF (dataout_round(dataa_width + datab_width - 1) = '0' AND dataout_round(dataa_width + datab_width - 2) = '1') THEN
dataout_saturate_tmp3 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN dataa_width + datab_width - 2 TO (72 - 1) LOOP
dataout_saturate_tmp3(i) := '0';
END LOOP;
saturated_tmp4 := '1';
ELSE
dataout_saturate_tmp3 := dataout_round;
saturated_tmp4 := '0';
END IF;
min_tmp5 := dataout_saturate_tmp3;
max_tmp6 := dataout_saturate_tmp3;
ELSE
IF ((operation(2) = '1') AND ((block_type = "ab") OR (block_type = "cd"))) THEN
saturated_tmp4 := '0';
i := datab_width - 2;
WHILE (i < (datab_width + signsize - 2)) LOOP
IF (dataout_round(datab_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
IF (saturated_tmp4 = '1') THEN
min_tmp5 := "111111111111111111111111111111111111111111111111111111111111111111111111";
max_tmp6 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN 0 TO ((datab_width - 2) - 1) LOOP
max_tmp6(i) := '0';
END LOOP;
FOR i IN datab_width - 2 TO (72 - 1) LOOP
min_tmp5(i) := '0';
END LOOP;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
msb_tmp7 := dataout_round(datab_width + 15);
ELSE
IF ((signa_ipd OR signb_ipd OR NOT addnsub_ipd) = '1') THEN
min_tmp5 := gnd + (2 **(conv_integer(dataa_width)));
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width))) - 1);
ELSE
min_tmp5 := "000000000000000000000000000000000000000000000000000000000000000000000000";
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width + 1))) - 1);
END IF;
saturated_tmp4 := '0';
i := dataa_width - 2;
WHILE (i < (dataa_width + signsize - 1)) LOOP
IF (dataout_round(dataa_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
msb_tmp7 := dataout_round(i);
END IF;
IF (saturated_tmp4 = '1') THEN
IF (msb_tmp7 = '1') THEN
dataout_saturate_tmp3 := max_tmp6;
ELSE
dataout_saturate_tmp3 := min_tmp5;
END IF;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
END IF;
ELSE
saturated_tmp4 := '0';
dataout_saturate_tmp3 := dataout_round;
END IF;
dataout_saturate <= dataout_saturate_tmp3;
saturated <= saturated_tmp4;
min <= min_tmp5;
max <= max_tmp6;
msb <= msb_tmp7;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
dataout_round,
dataout_saturate)
VARIABLE dataout_dly_tmp8 : std_logic_vector(71 DOWNTO 0);
VARIABLE i : integer;
VARIABLE width_tmp : integer;
BEGIN
IF (round_ipd = '1') THEN
dataout_dly_tmp8 := dataout_saturate;
width_tmp := conv_integer(dataoutsize) - conv_integer(signsize) - conv_integer(roundsize);
i := 0;
WHILE (i < width_tmp) LOOP
dataout_dly_tmp8(i) := '0';
i := i + 1;
END LOOP;
ELSE
dataout_dly_tmp8 := dataout_saturate;
END IF;
dataout_dly <= dataout_dly_tmp8;
END PROCESS;
dataout_tbuf <= datain WHEN (operation = 0) OR (operation = 7) ELSE rs_saturate ;
rs_saturate <= rs_mac_mult WHEN (saturate_ipd = '1') ELSE rs_mac_out ;
rs_mac_mult <= (dataout_dly(71 DOWNTO 3) & "00" & saturated)
WHEN ((saturate_ipd = '1') AND (saturated = '1') AND (block_type = "mac_mult")) ELSE rs_mac_out ;
rs_mac_out <= (dataout_dly(71 DOWNTO 3) & saturated & datain_ipd(1 DOWNTO 0))
WHEN ((saturate_ipd = '1') AND (block_type /= "mac_mult")) ELSE dataout_dly ;
pathDelay : BLOCK
BEGIN
g1 : for i in dataout'range generate
PROCESS (dataout_tbuf)
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(i),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END GENERATE;
END BLOCK;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_MULT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_mult_internal IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : integer := 36;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0) := (others => '0')
);
END arriagx_mac_mult_internal;
ARCHITECTURE arch OF arriagx_mac_mult_internal IS
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL neg : std_logic := '0';
SIGNAL dataout_pre_bypass : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_output : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
BEGIN
neg <= (dataa_ipd(dataa_width - 1) AND signa) XOR (datab_ipd(datab_width - 1) AND signb) ;
abs_a <= (NOT dataa_ipd(dataa_width - 1 DOWNTO 0) + 1) WHEN (signa AND dataa_ipd(dataa_width - 1)) = '1' ELSE dataa_ipd(dataa_width - 1 DOWNTO 0) ;
abs_b <= (NOT datab_ipd(datab_width - 1 DOWNTO 0) + 1) WHEN (signb AND datab_ipd(datab_width - 1)) = '1' ELSE datab_ipd(datab_width - 1 DOWNTO 0) ;
abs_output((dataa_width + datab_width) - 1 DOWNTO 0) <= abs_a(dataa_width-1 downto 0) * abs_b(datab_width-1 downto 0) ;
dataout_pre_bypass((dataa_width + datab_width) - 1 DOWNTO 0) <= (NOT abs_output + 1) WHEN neg = '1' ELSE abs_output ;
dataout_tmp((dataa_width + datab_width) - 1 DOWNTO 0) <= datab(datab_width-1 downto 0) & dataa(dataa_width-1 downto 0) when ((dynamic_mode = "yes") and (bypass = '1')) else dataa(dataa_width-1 downto 0) & datab(datab_width-1 downto 0) WHEN (bypass = '1') ELSE dataout_pre_bypass ;
PathDelay : block
begin
do:for i in dataout_tmp'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
sa: for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
PROCESS(dataa_ipd)
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sa;
sb: for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
PROCESS(datab_ipd)
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sb;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_MULT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_mac_mult_internal;
use work.arriagx_mac_bit_register;
use work.arriagx_mac_register;
use work.arriagx_mac_rs_block;
ENTITY arriagx_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_mac_mult;
ARCHITECTURE arch OF arriagx_mac_mult IS
COMPONENT arriagx_mac_mult_internal
GENERIC (
dataout_width : integer := 36;
dataa_width : integer := 18;
datab_width : integer := 18;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0));
END COMPONENT;
COMPONENT arriagx_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT arriagx_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT arriagx_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL mult_output : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL round_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL mode_out : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_rs : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_src : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_dataa : std_logic := '0';
SIGNAL clear_dataa : std_logic := '0';
SIGNAL aclr_dataa : std_logic := '0';
SIGNAL ena_dataa : std_logic := '0';
SIGNAL async_dataa : std_logic := '0';
SIGNAL clk_datab : std_logic := '0';
SIGNAL clear_datab : std_logic := '0';
SIGNAL aclr_datab : std_logic := '0';
SIGNAL ena_datab : std_logic := '0';
SIGNAL async_datab : std_logic := '0';
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_round : std_logic := '0';
SIGNAL clear_round : std_logic := '0';
SIGNAL aclr_round : std_logic := '0';
SIGNAL ena_round : std_logic := '0';
SIGNAL async_round : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode : std_logic := '0';
SIGNAL clear_mode : std_logic := '0';
SIGNAL aclr_mode : std_logic := '0';
SIGNAL ena_mode : std_logic := '0';
SIGNAL async_mode : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL signa_internal : std_logic := '0';
SIGNAL signb_internal : std_logic := '0';
SIGNAL bypass : std_logic := '0';
SIGNAL mac_mult_dataoutsize : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_60 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp62 : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL port_tmp63 : std_logic := '0';
SIGNAL port_tmp64 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp65 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp2 : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp3 : std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
BEGIN
dataout <= dataout_tmp1(dataout'range);
scanouta <= scanouta_tmp2;
scanoutb <= scanoutb_tmp3;
dataout_tmp1 <= dataout_tmp(35 DOWNTO 0) ;
dataa_src <= scanina WHEN (sourcea = '1') ELSE dataa ;
datab_src <= scaninb WHEN (sourceb = '1') ELSE datab ;
dataa_mac_reg : arriagx_mac_register
GENERIC MAP (
data_width => dataa_width,
power_up => '0')
PORT MAP (
data => dataa_src,
clk => clk_dataa,
aclr => aclr_dataa,
if_aclr => clear_dataa,
ena => ena_dataa,
dataout => scanouta_tmp,
async => async_dataa);
async_dataa <= '1' WHEN (dataa_clock = "none") ELSE '0' ;
clear_dataa <= '1' WHEN (dataa_clear /= "none") ELSE '0' ;
clk_dataa <= '1' WHEN clk(conv_integer(dataa_clk)) = '1' ELSE '0' ;
aclr_dataa <= '1' WHEN (aclr(conv_integer(dataa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_dataa <= '1' WHEN ena(conv_integer(dataa_clk)) = '1' ELSE '0' ;
dataa_clk <= "0000" WHEN ((dataa_clock = "0") OR (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ;
dataa_aclr <= "0000" WHEN ((dataa_clear = "0") OR (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ;
datab_mac_reg : arriagx_mac_register
GENERIC MAP (
data_width => datab_width,
power_up => '0')
PORT MAP (
data => datab_src,
clk => clk_datab,
aclr => aclr_datab,
if_aclr => clear_datab,
ena => ena_datab,
dataout => scanoutb_tmp,
async => async_datab);
async_datab <= '1' WHEN (datab_clock = "none") ELSE '0' ;
clear_datab <= '1' WHEN (datab_clear /= "none") ELSE '0' ;
clk_datab <= '1' WHEN clk(conv_integer(datab_clk)) = '1' ELSE '0' ;
aclr_datab <= '1' WHEN (aclr(conv_integer(datab_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_datab <= '1' WHEN ena(conv_integer(datab_clk)) = '1' ELSE '0' ;
datab_clk <= "0000" WHEN ((datab_clock = "0") OR (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ;
datab_aclr <= "0000" WHEN ((datab_clear = "0") OR (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ;
signa_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_out,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_out,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
round_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round,
clk => clk_round,
aclr => aclr_round,
if_aclr => clear_round,
ena => ena_round,
dataout => round_out,
async => async_round);
async_round <= '1' WHEN (round_clock = "none") ELSE '0' ;
clear_round <= '1' WHEN (round_clear /= "none") ELSE '0' ;
clk_round <= '1' WHEN clk(conv_integer(round_clk)) = '1' ELSE '0' ;
aclr_round <= '1' WHEN (aclr(conv_integer(round_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round <= '1' WHEN ena(conv_integer(round_clk)) = '1' ELSE '0' ;
round_clk <= "0000" WHEN ((round_clock = "0") OR (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ;
round_aclr <= "0000" WHEN ((round_clear = "0") OR (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ;
saturate_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_out,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode,
clk => clk_mode,
aclr => aclr_mode,
if_aclr => clear_mode,
ena => ena_mode,
dataout => mode_out,
async => async_mode);
async_mode <= '1' WHEN (mode_clock = "none") ELSE '0' ;
clear_mode <= '1' WHEN (mode_clear /= "none") ELSE '0' ;
clk_mode <= '1' WHEN clk(conv_integer(mode_clk)) = '1' ELSE '0' ;
aclr_mode <= '1' WHEN (aclr(conv_integer(mode_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode <= '1' WHEN ena(conv_integer(mode_clk)) = '1' ELSE '0' ;
mode_clk <= "0000" WHEN ((mode_clock = "0") OR (mode_clock = "none")) ELSE "0001" WHEN (mode_clock = "1") ELSE "0010" WHEN (mode_clock = "2") ELSE "0011" WHEN (mode_clock = "3") ELSE "0000" ;
mode_aclr <= "0000" WHEN ((mode_clear = "0") OR (mode_clear = "none")) ELSE "0001" WHEN (mode_clear = "1") ELSE "0010" WHEN (mode_clear = "2") ELSE "0011" WHEN (mode_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_out,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
mac_multiply : arriagx_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
dataout_width => dataa_width + datab_width,
dynamic_mode => dynamic_mode)
PORT MAP (
dataa => scanouta_tmp,
datab => scanoutb_tmp,
signa => signa_internal,
signb => signb_internal,
bypass => bypass,
scanouta => scanouta_tmp2,
scanoutb => scanoutb_tmp3,
dataout => mult_output);
signa_internal <= '0' WHEN ((signa_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signa_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signa_out ;
signb_internal <= '0' WHEN ((signb_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signb_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signb_out ;
bypass <= '1' WHEN ((bypass_multiplier = "yes") AND (dynamic_mode = "no")) OR (((bypass_multiplier = "yes") AND (mode_out = '1')) AND (dynamic_mode = "yes")) ELSE '0' ;
tmp_60 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & mult_output(35 DOWNTO 0);
port_tmp62 <= "1111";
port_tmp63 <= '0';
port_tmp64 <= "00000010";
port_tmp65 <= "00001111";
mac_rs_block : arriagx_mac_rs_block
GENERIC MAP (
block_type => "mac_mult",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => port_tmp62,
round => round_out,
saturate => saturate_out,
addnsub => port_tmp63,
signa => signa_out,
signb => signb_out,
signsize => port_tmp64,
roundsize => port_tmp65,
dataoutsize => mac_mult_dataoutsize,
dataa => scanouta_tmp,
datab => scanoutb_tmp,
datain => tmp_60,
dataout => dataout_rs);
mac_mult_dataoutsize <= CONV_STD_LOGIC_VECTOR(dataa_width + datab_width, 8) ;
dataout_reg <= tmp_60 when bypass = '1' else dataout_rs;
dataout_mac_reg : arriagx_mac_register
GENERIC MAP (
data_width => dataa_width + datab_width,
power_up => '0')
PORT MAP (
data => dataout_reg((dataa_width + datab_width) -1 downto 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_tmp((dataa_width + datab_width) -1 downto 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
END arch;
--////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_ADDNSUB
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_addnsub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
block_type : string := "ab");
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END arriagx_mac_addnsub;
ARCHITECTURE arch OF arriagx_mac_addnsub IS
-- REGULAR ADD/SUB
SIGNAL sa : std_logic := '0';
SIGNAL sb : std_logic := '0';
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
-- 36 BIT MULT
SIGNAL dataa_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
--SIGNAL z36 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--SIGNAL z18 : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
overflow <= overflow_tmp2;
PROCESS (dataa, datab, datac, datad, signa, signb, operation, addnsub)
--VARIABLE z36_tmp3 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--VARIABLE z18_tmp4 : std_logic_vector(17 DOWNTO 0) := (others => '0');
VARIABLE dataout_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE overflow_tmp_tmp13 : std_logic;
VARIABLE sa_tmp14 : std_logic;
VARIABLE sb_tmp15 : std_logic;
VARIABLE abs_a_tmp16 : std_logic_vector(71 DOWNTO 0);
VARIABLE abs_b_tmp17 : std_logic_vector(71 DOWNTO 0);
VARIABLE dataout_t : std_logic_vector(72 downto 0) := (others => '0');
VARIABLE dataa_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_s : std_logic_vector(71 downto 0) := (others => '0');
BEGIN
IF ((unsigned(operation) = 7) AND (block_type /= "sum")) THEN
dataa_u := (others => '0');
datab_u := (others => '0');
datac_u := (others => '0');
datad_u := (others => '0');
datab_s := (others => '0');
datac_s := (others => '0');
dataa_u(35 downto 0) := dataa(35 downto 0);
datab_u(71 downto 36) := datab(35 downto 0);
datab_s(71 downto 36) := datab(35 downto 0);
datac_u(53 downto 18) := datac(35 downto 0);
datac_s(71 downto 18) := sxt(datac(datac_width-1 downto 0), 54);
datad_u(53 downto 18) := datad(35 downto 0);
datad_s(71 downto 18) := sxt(datad(datad_width-1 downto 0), 54);
if((signa = '0') and (signb = '0')) then
dataout_tmp_tmp12 := unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signa = '0') and (signb = '1')) then
dataout_t := signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '0')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '1')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF ((operation(2) = '1') AND (block_type = "ab")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16) XOR dataout_tmp_tmp12(datab_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16);
END IF;
ELSE
IF ((operation(2) = '1') AND (block_type = "cd")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16) XOR dataout_tmp_tmp12(datad_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16);
END IF;
ELSE
IF (block_type = "sum") THEN
if ((signa = '1') and (signb = '0')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(ext(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '0') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(ext(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '1') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
else
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
unsigned(ext(dataa(dataa_width downto 0), dataa_width+2)) +
unsigned(ext(datab(datab_width downto 0), dataa_width+2));
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF (block_type = "cd") THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1) XOR dataout_tmp_tmp12(datac_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1);
END IF;
ELSE
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1) XOR dataout_tmp_tmp12(dataa_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1);
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
--z36 <= z36_tmp3;
--z18 <= z18_tmp4;
dataout_tmp <= dataout_tmp_tmp12;
overflow_tmp <= overflow_tmp_tmp13;
sa <= sa_tmp14;
sb <= sb_tmp15;
abs_a <= abs_a_tmp16;
abs_b <= abs_b_tmp17;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
overflow_tmp2 <= overflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_DYNAMIC_SRC
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_dynamic_src IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0'
);
END arriagx_mac_dynamic_src;
ARCHITECTURE arch OF arriagx_mac_dynamic_src IS
SIGNAL outa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp : std_logic := '0';
SIGNAL satb_tmp : std_logic := '0';
SIGNAL satc_tmp : std_logic := '0';
SIGNAL satd_tmp : std_logic := '0';
SIGNAL satab_tmp : std_logic := '0';
SIGNAL satcd_tmp : std_logic := '0';
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL outa_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp5 : std_logic := '0';
SIGNAL satb_tmp6 : std_logic := '0';
SIGNAL satc_tmp7 : std_logic := '0';
SIGNAL satd_tmp8 : std_logic := '0';
SIGNAL satab_tmp9 : std_logic := '0';
SIGNAL satcd_tmp10 : std_logic := '0';
SIGNAL dynamic_dataa_width : integer := 36;
SIGNAL dynamic_datab_width : integer := 36;
SIGNAL dynamic_datac_width : integer := 36;
SIGNAL dynamic_datad_width : integer := 36;
BEGIN
outa <= outa_tmp1;
outb <= outb_tmp2;
outc <= outc_tmp3;
outd <= outd_tmp4;
sata <= sata_tmp5;
satb <= satb_tmp6;
satc <= satc_tmp7;
satd <= satd_tmp8;
satab <= satab_tmp9;
satcd <= satcd_tmp10;
dynamic_dataa_width <= dataa_width WHEN (dataa_width > 0) ELSE 36;
dynamic_datab_width <= datab_width WHEN (datab_width > 0) ELSE 36;
dynamic_datac_width <= datac_width WHEN (datac_width > 0) ELSE 36;
dynamic_datad_width <= datad_width WHEN (datad_width > 0) ELSE 36;
PROCESS (accuma, accumc, dataa, datab, datac, datad, multabsaturate, multcdsaturate, signa, signb, zeroacc, zeroacc1, operation)
VARIABLE outa_tmp_tmp11 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outb_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outc_tmp_tmp13 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outd_tmp_tmp14 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE j_tmp15 : integer;
VARIABLE temp_tmp16 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE sata_tmp_tmp17 : std_logic := '0';
VARIABLE satb_tmp_tmp18 : std_logic := '0';
VARIABLE satc_tmp_tmp19 : std_logic := '0';
VARIABLE satd_tmp_tmp20 : std_logic := '0';
VARIABLE satab_tmp_tmp21 : std_logic := '0';
VARIABLE satcd_tmp_tmp22 : std_logic := '0';
BEGIN
CASE operation IS
WHEN "0000" =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') then
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "0100" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11:= sxt(dataa(datab_width+15 downto 0), 72);
ELSE
outa_tmp_tmp11:= ext(dataa(datab_width+15 downto 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
j_tmp15 := dataa_width - 1;
FOR i IN (datab_width + 15) DOWNTO 0 LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 - 1;
END LOOP;
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1100" =>
temp_tmp16 := zeroacc1 & zeroacc;
CASE temp_tmp16 IS
WHEN "00" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "01" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "10" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "11" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN OTHERS =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
WHEN "1101" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1110" =>
IF (zeroacc1 = '1') THEN
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN OTHERS =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signa = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signa = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
IF (multabsaturate = '1') THEN
IF ((outa_tmp_tmp11(0) AND ((zeroacc AND operation(2)) OR NOT operation(2))) = '1') THEN
sata_tmp_tmp17 := '1';
outa_tmp_tmp11(0) := '0';
ELSE
sata_tmp_tmp17 := '0';
END IF;
IF (outb_tmp_tmp12(0) = '1') THEN
satb_tmp_tmp18 := '1';
outb_tmp_tmp12(0) := '0';
ELSE
satb_tmp_tmp18 := '0';
END IF;
ELSE
sata_tmp_tmp17 := '0';
satb_tmp_tmp18 := '0';
END IF;
IF (multcdsaturate = '1') THEN
IF ((outc_tmp_tmp13(0) AND ((zeroacc1 AND operation(2)) OR NOT operation(2))) = '1') THEN
satc_tmp_tmp19 := '1';
outc_tmp_tmp13(0) := '0';
ELSE
satc_tmp_tmp19 := '0';
END IF;
IF (outd_tmp_tmp14(0) = '1') THEN
satd_tmp_tmp20 := '1';
outd_tmp_tmp14(0) := '0';
ELSE
satd_tmp_tmp20 := '0';
END IF;
ELSE
satc_tmp_tmp19 := '0';
satd_tmp_tmp20 := '0';
END IF;
IF ((sata_tmp_tmp17 OR satb_tmp_tmp18) = '1') THEN
satab_tmp_tmp21 := '1';
ELSE
satab_tmp_tmp21 := '0';
END IF;
IF ((satc_tmp_tmp19 OR satd_tmp_tmp20) = '1') THEN
satcd_tmp_tmp22 := '1';
ELSE
satcd_tmp_tmp22 := '0';
END IF;
outa_tmp <= outa_tmp_tmp11;
outb_tmp <= outb_tmp_tmp12;
outc_tmp <= outc_tmp_tmp13;
outd_tmp <= outd_tmp_tmp14;
j <= j_tmp15;
sata_tmp <= sata_tmp_tmp17;
satb_tmp <= satb_tmp_tmp18;
satc_tmp <= satc_tmp_tmp19;
satd_tmp <= satd_tmp_tmp20;
satab_tmp <= satab_tmp_tmp21;
satcd_tmp <= satcd_tmp_tmp22;
END PROCESS;
outa_tmp1 <= outa_tmp ;
outb_tmp2 <= outb_tmp ;
outc_tmp3 <= outc_tmp ;
outd_tmp4 <= outd_tmp ;
sata_tmp5 <= sata_tmp ;
satb_tmp6 <= satb_tmp ;
satc_tmp7 <= satc_tmp ;
satd_tmp8 <= satd_tmp ;
satab_tmp9 <= satab_tmp ;
satcd_tmp10 <= satcd_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_DYNAMIC_MUX
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_dynamic_mux IS
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END arriagx_mac_dynamic_mux;
ARCHITECTURE arch OF arriagx_mac_dynamic_mux IS
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
accoverflow <= accoverflow_tmp2;
PROCESS (ab, cd, sata, satb, satc, satd, multsatab, multsatcd, outsatab, outsatcd, multabsaturate, multcdsaturate, saturateab, saturatecd, overab, overcd, sum, m36, bypass, operation)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
VARIABLE accoverflow_tmp_tmp4 : std_logic := '0';
VARIABLE temp_tmp5 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp6 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp7 : std_logic_vector(3 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp8 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp9 : std_logic_vector(1 DOWNTO 0) := (others => '0');
BEGIN
CASE operation IS
WHEN "0000" =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
WHEN "0100" =>
temp_tmp5 := saturateab & multabsaturate;
CASE temp_tmp5 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "0001" =>
IF (multabsaturate = '1') THEN
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 2) & satb & sata;
ELSE
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 0);
END IF;
accoverflow_tmp_tmp4 := '0';
WHEN "0010" =>
temp_tmp6 := multsatcd & multsatab;
CASE temp_tmp6 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 2) & satb & sata;
accoverflow_tmp_tmp4 := '0';
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & sum(1 DOWNTO 0);
accoverflow_tmp_tmp4 := satd;
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & satb & sata;
accoverflow_tmp_tmp4 := satd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
END CASE;
WHEN "0111" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & m36;
accoverflow_tmp_tmp4 := '0';
WHEN "1100" =>
temp_tmp7 := saturatecd & saturateab & multsatcd & multsatab;
CASE temp_tmp7 IS
WHEN "0000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "0110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1101" =>
temp_tmp8 := saturateab & multabsaturate;
CASE temp_tmp8 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1110" =>
temp_tmp9 := saturatecd & multcdsaturate;
CASE temp_tmp9 IS
WHEN "00" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN "10" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overcd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
END CASE;
dataout_tmp <= dataout_tmp_tmp3;
accoverflow_tmp <= accoverflow_tmp_tmp4;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
accoverflow_tmp2 <= accoverflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_OUT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_mac_addnsub;
use work.arriagx_mac_dynamic_mux;
use work.arriagx_mac_dynamic_src;
use work.arriagx_mac_rs_block;
ENTITY arriagx_mac_out_internal IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width -1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0'
);
END arriagx_mac_out_internal;
ARCHITECTURE arch OF arriagx_mac_out_internal IS
COMPONENT arriagx_mac_addnsub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
block_type : string := "ab";
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT arriagx_mac_dynamic_mux
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT arriagx_mac_dynamic_src
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0');
END COMPONENT;
COMPONENT arriagx_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataa_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata : std_logic := '0';
SIGNAL satb : std_logic := '0';
SIGNAL satc : std_logic := '0';
SIGNAL satd : std_logic := '0';
SIGNAL satab : std_logic := '0';
SIGNAL satcd : std_logic := '0';
SIGNAL addnsub_ab_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_cd_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_sum : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_ab : std_logic := '0';
SIGNAL overflow_cd : std_logic := '0';
SIGNAL overflow_sum : std_logic := '0';
SIGNAL rs_block_ab_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_ab_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL feedback_ipd : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL saturateab_ipd : std_logic := '0';
SIGNAL saturatecd_ipd : std_logic := '0';
SIGNAL multabsaturate_ipd : std_logic := '0';
SIGNAL multcdsaturate_ipd : std_logic := '0';
SIGNAL dataout_tbuf : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tbuf : std_logic;
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signx_or_y : std_logic;
SIGNAL addnsub_signa_input : std_logic;
SIGNAL addnsub_signb_input : std_logic;
SIGNAL feedback_accuma : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL feedback_accumc : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL xory_addnsub0 : std_logic := '0';
SIGNAL xory_addnsub1 : std_logic := '0';
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_8 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_10 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp38 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp43 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp50 : std_logic := '0';
SIGNAL tmp_59 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataa_ipd(dataa_width -1 downto 0) <= dataa;
datab_ipd(datab_width -1 downto 0) <= datab;
datac_ipd(datac_width -1 downto 0) <= datac;
datad_ipd(datad_width -1 downto 0) <= datad;
WireDelay : block
begin
loopbits : FOR i in feedback'RANGE GENERATE
VitalWireDelay (feedback_ipd(i), feedback(i), tipd_feedback(i));
END GENERATE;
end block;
multabsaturate_ipd <= multabsaturate ;
multcdsaturate_ipd <= multcdsaturate ;
saturateab_ipd <= saturateab ;
saturatecd_ipd <= saturatecd ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '0')) AND (zeroacc1 = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE "0000" ;
addnsub_signa_input <= signx WHEN (operation_mode = "36_bit_multiply") ELSE signx WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
addnsub_signb_input <= signy WHEN (operation_mode = "36_bit_multiply") ELSE signy WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
tmp_4(dataa_ipd'range) <= dataa_ipd;
tmp_6(datab_ipd'range) <= datab_ipd;
tmp_8(datac_ipd'range) <= datac_ipd;
tmp_10(datad_ipd'range) <= datad_ipd;
dynamic_src : arriagx_mac_dynamic_src
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
accuma => feedback_accuma,
accumc => feedback_accumc,
dataa => tmp_4,
datab => tmp_6,
datac => tmp_8,
datad => tmp_10,
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
zeroacc => zeroacc,
zeroacc1 => zeroacc1,
signa => signx,
signb => signy,
operation => operation,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
satab => satab,
satcd => satcd,
outa => dataa_src,
outb => datab_src,
outc => datac_src,
outd => datad_src);
signx_or_y <= signx OR signy ;
feedback_accuma <= feedback(52 DOWNTO 37) & feedback(35 DOWNTO 0) WHEN (operation_mode = "dynamic") ELSE feedback(51 DOWNTO 0) ;
feedback_accumc <= feedback(124 DOWNTO 109) & feedback(107 DOWNTO 72) WHEN (operation_mode = "dynamic") ELSE feedback(123 DOWNTO 72) ;
addnsub_ab : arriagx_mac_addnsub
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => addnsub_signa_input,
signb => addnsub_signb_input,
operation => operation,
addnsub => addnsub0,
dataout => addnsub_ab_out,
overflow => overflow_ab);
addnsub_cd : arriagx_mac_addnsub
GENERIC MAP (
block_type => "cd",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => signx_or_y,
signb => signx_or_y,
operation => operation,
addnsub => addnsub1,
dataout => addnsub_cd_out,
overflow => overflow_cd);
port_tmp38 <= "00001111";
mac_rs_block_low : arriagx_mac_rs_block
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => operation,
round => roundab,
saturate => saturateab_ipd,
addnsub => addnsub0,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_ab_sign_size,
roundsize => port_tmp38,
dataoutsize => rs_block_ab_size,
dataa => dataa_src(dataa_width-1 downto 0),
datab => datab_src(datab_width-1 downto 0),
datain => addnsub_ab_out,
dataout => dataout_low);
rs_block_ab_size <= CONV_STD_LOGIC_VECTOR((datab_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_ab_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp43 <= "00001111";
mac_rs_block_high : arriagx_mac_rs_block
GENERIC MAP (
block_type => "cd",
dataa_width => datac_width,
datab_width => datad_width)
PORT MAP (
operation => operation,
round => roundcd,
saturate => saturatecd_ipd,
addnsub => addnsub1,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_cd_sign_size,
roundsize => port_tmp43,
dataoutsize => rs_block_cd_size,
dataa => datac_src(datac_width -1 downto 0),
datab => datad_src(datad_width -1 downto 0),
datain => addnsub_cd_out,
dataout => dataout_high);
rs_block_cd_size <= CONV_STD_LOGIC_VECTOR((datad_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_cd_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp50 <= '1';
addnsub_sum_abcd : arriagx_mac_addnsub
GENERIC MAP (
block_type => "sum",
dataa_width => dataa_width,
datab_width => dataa_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataout_low,
datab => dataout_high,
datac => datac_src,
datad => datad_src,
signa => xory_addnsub0,
signb => xory_addnsub1,
operation => operation,
addnsub => port_tmp50,
dataout => addnsub_sum,
overflow => overflow_sum);
xory_addnsub0 <= signx_or_y OR NOT addnsub0 ;
xory_addnsub1 <= signx_or_y OR NOT addnsub1 ;
tmp_59 <= datad_ipd & datac_ipd & datab_ipd & dataa_ipd;
dynamic_mux : arriagx_mac_dynamic_mux
PORT MAP (
ab => dataout_low,
cd => dataout_high,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
multsatab => satab,
multsatcd => satcd,
outsatab => dataout_low(2),
outsatcd => dataout_high(2),
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
saturateab => saturateab_ipd,
saturatecd => saturatecd_ipd,
overab => overflow_ab,
overcd => overflow_cd,
sum => addnsub_sum,
m36 => addnsub_ab_out,
bypass => tmp_59,
operation => operation,
dataout => dataout_tmp,
accoverflow => accoverflow_tmp);
PathDelay: for i in dataout'range generate
PROCESS(dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc'last_event, tpd_zeroacc_dataout(i), TRUE),
10 => (zeroacc1'last_event, tpd_zeroacc1_dataout(i), TRUE),
11 => (mode0'last_event, tpd_mode0_dataout(i), TRUE),
12 => (mode1'last_event, tpd_mode1_dataout(i), TRUE),
13 => (multabsaturate'last_event, tpd_multabsaturate_dataout(i), TRUE),
14 => (multcdsaturate'last_event, tpd_multcdsaturate_dataout(i), TRUE),
15 => (feedback'last_event, tpd_feedback_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate PathDelay;
acc: for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc'last_event, tpd_zeroacc_accoverflow, TRUE),
7 => (zeroacc1'last_event, tpd_zeroacc1_accoverflow, TRUE),
8 => (mode0'last_event, tpd_mode0_accoverflow, TRUE),
9 => (mode1'last_event, tpd_mode1_accoverflow, TRUE),
10 => (feedback'last_event, tpd_feedback_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
END GENERATE acc;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_PIN_MAP
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_mac_pin_map IS
GENERIC (
tipd_addnsub : VitalDelayType01 := DefPropDelay01;
data_width : integer := 144;
tipd_datain : VitalDelayArrayType01(143 downto 0) := (OTHERS => (20 ps,20 ps));
operation_mode : string := "output_only";
pinmap : string := "map");
PORT (
datain : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END arriagx_mac_pin_map;
ARCHITECTURE arch OF arriagx_mac_pin_map IS
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL datain_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp2 : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (addnsub_ipd, addnsub, tipd_addnsub);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
dataout <= dataout_tmp2(dataout'range);
PROCESS (datain_ipd, addnsub_ipd)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
BEGIN
IF (operation_mode = "dynamic") THEN
IF (pinmap = "map") THEN
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) &
'X' & datain_ipd(107 DOWNTO 72) &
"XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) &
'X' & datain_ipd(35 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := datain_ipd(143 DOWNTO 72)& "XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) & 'X' & datain_ipd(35 DOWNTO 0);
WHEN "1110" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) & 'X' & datain_ipd(107 DOWNTO 0);
WHEN "0111" =>
IF (addnsub_ipd = '1') THEN
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
ELSE
dataout_tmp_tmp3(17 DOWNTO 0) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(35 DOWNTO 18) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(53 DOWNTO 36) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(71 DOWNTO 54) := "XXXXXXXXXXXXXXXXXX";
END IF;
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
ELSE
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "1101" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(143 DOWNTO 72) := datain_ipd(143 DOWNTO 72);
WHEN "1110" =>
dataout_tmp_tmp3(107 DOWNTO 0) := datain_ipd(107 DOWNTO 0);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "0111" =>
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
END IF;
ELSE
dataout_tmp_tmp3 := datain_ipd;
END IF;
dataout_tmp <= dataout_tmp_tmp3;
END PROCESS;
dataout_tmp2 <= dataout_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- ARRIAGX_MAC_OUT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
use work.arriagx_mac_out_internal;
use work.arriagx_mac_pin_map;
use work.arriagx_mac_bit_register;
use work.arriagx_mac_register;
ENTITY arriagx_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_mac_out;
ARCHITECTURE arch OF arriagx_mac_out IS
COMPONENT arriagx_mac_out_internal
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width-1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic);
END COMPONENT;
COMPONENT arriagx_mac_pin_map
GENERIC (
pinmap : string := "map";
data_width : integer := 144;
operation_mode : string := "output_only");
PORT (
datain : IN std_logic_vector(data_width-1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width-1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT arriagx_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT arriagx_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataa_f : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL datac_f : std_logic_vector(datac_width-1 DOWNTO 0) := (others => '0');
SIGNAL signa_pipe : std_logic := '0';
SIGNAL signb_pipe : std_logic := '0';
SIGNAL multabsaturate_pipe : std_logic := '0';
SIGNAL multcdsaturate_pipe : std_logic := '0';
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL multabsaturate_out : std_logic := '0';
SIGNAL multcdsaturate_out : std_logic := '0';
SIGNAL addnsub0_pipe : std_logic := '0';
SIGNAL addnsub1_pipe : std_logic := '0';
SIGNAL addnsub0_out : std_logic := '0';
SIGNAL addnsub1_out : std_logic := '0';
SIGNAL zeroacc_pipe : std_logic := '0';
SIGNAL zeroacc1_pipe : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL zeroacc1_out : std_logic := '0';
SIGNAL dataout_feedback : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_map : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_mapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_unmapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_non_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic7 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_to_reg : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_reg : std_logic := '0';
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipe : std_logic := '0';
SIGNAL round1_pipe : std_logic := '0';
SIGNAL saturate_pipe : std_logic := '0';
SIGNAL saturate1_pipe : std_logic := '0';
SIGNAL mode0_pipe : std_logic := '0';
SIGNAL mode1_pipe : std_logic := '0';
SIGNAL round0_out : std_logic := '0';
SIGNAL round1_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL saturate1_out : std_logic := '0';
SIGNAL mode0_out : std_logic := '0';
SIGNAL mode1_out : std_logic := '0';
SIGNAL addnsub0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_zeroacc1 : std_logic := '0';
SIGNAL clear_zeroacc1 : std_logic := '0';
SIGNAL aclr_zeroacc1 : std_logic := '0';
SIGNAL ena_zeroacc1 : std_logic := '0';
SIGNAL async_zeroacc1 : std_logic := '0';
SIGNAL clk_addnsub0 : std_logic := '0';
SIGNAL clear_addnsub0 : std_logic := '0';
SIGNAL aclr_addnsub0 : std_logic := '0';
SIGNAL ena_addnsub0 : std_logic := '0';
SIGNAL async_addnsub0 : std_logic := '0';
SIGNAL clk_addnsub1 : std_logic := '0';
SIGNAL clear_addnsub1 : std_logic := '0';
SIGNAL aclr_addnsub1 : std_logic := '0';
SIGNAL ena_addnsub1 : std_logic := '0';
SIGNAL async_addnsub1 : std_logic := '0';
SIGNAL clk_round0 : std_logic := '0';
SIGNAL clear_round0 : std_logic := '0';
SIGNAL aclr_round0 : std_logic := '0';
SIGNAL ena_round0 : std_logic := '0';
SIGNAL async_round0 : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode0 : std_logic := '0';
SIGNAL clear_mode0 : std_logic := '0';
SIGNAL aclr_mode0 : std_logic := '0';
SIGNAL ena_mode0 : std_logic := '0';
SIGNAL async_mode0 : std_logic := '0';
SIGNAL clk_round1 : std_logic := '0';
SIGNAL clear_round1 : std_logic := '0';
SIGNAL aclr_round1 : std_logic := '0';
SIGNAL ena_round1 : std_logic := '0';
SIGNAL async_round1 : std_logic := '0';
SIGNAL clk_saturate1 : std_logic := '0';
SIGNAL clear_saturate1 : std_logic := '0';
SIGNAL aclr_saturate1 : std_logic := '0';
SIGNAL ena_saturate1 : std_logic := '0';
SIGNAL async_saturate1 : std_logic := '0';
SIGNAL clk_mode1 : std_logic := '0';
SIGNAL clear_mode1 : std_logic := '0';
SIGNAL aclr_mode1 : std_logic := '0';
SIGNAL ena_mode1 : std_logic := '0';
SIGNAL async_mode1 : std_logic := '0';
SIGNAL clk_multabsaturate : std_logic := '0';
SIGNAL clear_multabsaturate : std_logic := '0';
SIGNAL aclr_multabsaturate : std_logic := '0';
SIGNAL ena_multabsaturate : std_logic := '0';
SIGNAL async_multabsaturate : std_logic := '0';
SIGNAL clk_multcdsaturate : std_logic := '0';
SIGNAL clear_multcdsaturate : std_logic := '0';
SIGNAL aclr_multcdsaturate : std_logic := '0';
SIGNAL ena_multcdsaturate : std_logic := '0';
SIGNAL async_multcdsaturate : std_logic := '0';
SIGNAL clk_signa_pipeline : std_logic := '0';
SIGNAL clear_signa_pipeline : std_logic := '0';
SIGNAL aclr_signa_pipeline : std_logic := '0';
SIGNAL ena_signa_pipeline : std_logic := '0';
SIGNAL async_signa_pipeline : std_logic := '0';
SIGNAL clk_signb_pipeline : std_logic := '0';
SIGNAL clear_signb_pipeline : std_logic := '0';
SIGNAL aclr_signb_pipeline : std_logic := '0';
SIGNAL ena_signb_pipeline : std_logic := '0';
SIGNAL async_signb_pipeline : std_logic := '0';
SIGNAL clk_zeroacc_pipeline : std_logic := '0';
SIGNAL clear_zeroacc_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc_pipeline : std_logic := '0';
SIGNAL ena_zeroacc_pipeline : std_logic := '0';
SIGNAL async_zeroacc_pipeline : std_logic := '0';
SIGNAL clk_zeroacc1_pipeline : std_logic := '0';
SIGNAL clear_zeroacc1_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc1_pipeline : std_logic := '0';
SIGNAL ena_zeroacc1_pipeline : std_logic := '0';
SIGNAL async_zeroacc1_pipeline : std_logic := '0';
SIGNAL clk_addnsub0_pipeline : std_logic := '0';
SIGNAL clear_addnsub0_pipeline : std_logic := '0';
SIGNAL aclr_addnsub0_pipeline : std_logic := '0';
SIGNAL ena_addnsub0_pipeline : std_logic := '0';
SIGNAL async_addnsub0_pipeline : std_logic := '0';
SIGNAL clk_addnsub1_pipeline : std_logic := '0';
SIGNAL clear_addnsub1_pipeline : std_logic := '0';
SIGNAL aclr_addnsub1_pipeline : std_logic := '0';
SIGNAL ena_addnsub1_pipeline : std_logic := '0';
SIGNAL async_addnsub1_pipeline : std_logic := '0';
SIGNAL clk_round0_pipeline : std_logic := '0';
SIGNAL clear_round0_pipeline : std_logic := '0';
SIGNAL aclr_round0_pipeline : std_logic := '0';
SIGNAL ena_round0_pipeline : std_logic := '0';
SIGNAL async_round0_pipeline : std_logic := '0';
SIGNAL clk_saturate_pipeline : std_logic := '0';
SIGNAL clear_saturate_pipeline : std_logic := '0';
SIGNAL aclr_saturate_pipeline : std_logic := '0';
SIGNAL ena_saturate_pipeline : std_logic := '0';
SIGNAL async_saturate_pipeline : std_logic := '0';
SIGNAL clk_mode0_pipeline : std_logic := '0';
SIGNAL clear_mode0_pipeline : std_logic := '0';
SIGNAL aclr_mode0_pipeline : std_logic := '0';
SIGNAL ena_mode0_pipeline : std_logic := '0';
SIGNAL async_mode0_pipeline : std_logic := '0';
SIGNAL clk_round1_pipeline : std_logic := '0';
SIGNAL clear_round1_pipeline : std_logic := '0';
SIGNAL aclr_round1_pipeline : std_logic := '0';
SIGNAL ena_round1_pipeline : std_logic := '0';
SIGNAL async_round1_pipeline : std_logic := '0';
SIGNAL clk_saturate1_pipeline : std_logic := '0';
SIGNAL clear_saturate1_pipeline : std_logic := '0';
SIGNAL aclr_saturate1_pipeline : std_logic := '0';
SIGNAL ena_saturate1_pipeline : std_logic := '0';
SIGNAL async_saturate1_pipeline : std_logic := '0';
SIGNAL clk_mode1_pipeline : std_logic := '0';
SIGNAL clear_mode1_pipeline : std_logic := '0';
SIGNAL aclr_mode1_pipeline : std_logic := '0';
SIGNAL ena_mode1_pipeline : std_logic := '0';
SIGNAL async_mode1_pipeline : std_logic := '0';
SIGNAL clk_multabsaturate_pipeline : std_logic := '0';
SIGNAL clear_multabsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multabsaturate_pipeline : std_logic := '0';
SIGNAL ena_multabsaturate_pipeline : std_logic := '0';
SIGNAL async_multabsaturate_pipeline : std_logic := '0';
SIGNAL clk_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clear_multcdsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multcdsaturate_pipeline : std_logic := '0';
SIGNAL ena_multcdsaturate_pipeline : std_logic := '0';
SIGNAL async_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL clk_output1 : std_logic := '0';
SIGNAL clear_output1 : std_logic := '0';
SIGNAL aclr_output1 : std_logic := '0';
SIGNAL ena_output1 : std_logic := '0';
SIGNAL async_output1 : std_logic := '0';
SIGNAL clk_output2 : std_logic := '0';
SIGNAL clear_output2 : std_logic := '0';
SIGNAL aclr_output2 : std_logic := '0';
SIGNAL ena_output2 : std_logic := '0';
SIGNAL async_output2 : std_logic := '0';
SIGNAL clk_output3 : std_logic := '0';
SIGNAL clear_output3 : std_logic := '0';
SIGNAL aclr_output3 : std_logic := '0';
SIGNAL ena_output3 : std_logic := '0';
SIGNAL async_output3 : std_logic := '0';
SIGNAL clk_output4 : std_logic := '0';
SIGNAL clear_output4 : std_logic := '0';
SIGNAL aclr_output4 : std_logic := '0';
SIGNAL ena_output4 : std_logic := '0';
SIGNAL async_output4 : std_logic := '0';
SIGNAL clk_output5 : std_logic := '0';
SIGNAL clear_output5 : std_logic := '0';
SIGNAL aclr_output5 : std_logic := '0';
SIGNAL ena_output5 : std_logic := '0';
SIGNAL async_output5 : std_logic := '0';
SIGNAL clk_output6 : std_logic := '0';
SIGNAL clear_output6 : std_logic := '0';
SIGNAL aclr_output6 : std_logic := '0';
SIGNAL ena_output6 : std_logic := '0';
SIGNAL async_output6 : std_logic := '0';
SIGNAL clk_output7 : std_logic := '0';
SIGNAL clear_output7 : std_logic := '0';
SIGNAL aclr_output7 : std_logic := '0';
SIGNAL ena_output7 : std_logic := '0';
SIGNAL async_output7 : std_logic := '0';
SIGNAL tmp_186 : std_logic := '0';
SIGNAL tmp_189 : std_logic := '0';
SIGNAL accoverflow_tmp2 : std_logic := '0';
SIGNAL pin_map_addnsub : std_logic := '0';
BEGIN
dataout <= dataout_tmp(dataout'range);
accoverflow <= accoverflow_tmp2;
signa_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_pipe,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_pipe,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_pipe,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
zeroacc1_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1,
clk => clk_zeroacc1,
aclr => aclr_zeroacc1,
if_aclr => clear_zeroacc1,
ena => ena_zeroacc1,
dataout => zeroacc1_pipe,
async => async_zeroacc1);
async_zeroacc1 <= '1' WHEN (zeroacc1_clock = "none") ELSE '0' ;
clear_zeroacc1 <= '1' WHEN (zeroacc1_clear /= "none") ELSE '0' ;
clk_zeroacc1 <= '1' WHEN clk(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
aclr_zeroacc1 <= '1' WHEN (aclr(conv_integer(zeroacc1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1 <= '1' WHEN ena(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
zeroacc1_clk <= "0000" WHEN ((zeroacc1_clock = "0") OR (zeroacc1_clock = "none")) ELSE "0001" WHEN (zeroacc1_clock = "1") ELSE "0010" WHEN (zeroacc1_clock = "2") ELSE "0011" WHEN (zeroacc1_clock = "3") ELSE "0000" ;
zeroacc1_aclr <= "0000" WHEN ((zeroacc1_clear = "0") OR (zeroacc1_clear = "none")) ELSE "0001" WHEN (zeroacc1_clear = "1") ELSE "0010" WHEN (zeroacc1_clear = "2") ELSE "0011" WHEN (zeroacc1_clear = "3") ELSE "0000" ;
addnsub0_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
if_aclr => clear_addnsub0,
ena => ena_addnsub0,
dataout => addnsub0_pipe,
async => async_addnsub0);
async_addnsub0 <= '1' WHEN (addnsub0_clock = "none") ELSE '0' ;
clear_addnsub0 <= '1' WHEN (addnsub0_clear /= "none") ELSE '0' ;
clk_addnsub0 <= '1' WHEN clk(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
aclr_addnsub0 <= '1' WHEN (aclr(conv_integer(addnsub0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0 <= '1' WHEN ena(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
addnsub0_clk <= "0000" WHEN ((addnsub0_clock = "0") OR (addnsub0_clock = "none")) ELSE "0001" WHEN (addnsub0_clock = "1") ELSE "0010" WHEN (addnsub0_clock = "2") ELSE "0011" WHEN (addnsub0_clock = "3") ELSE "0000" ;
addnsub0_aclr <= "0000" WHEN ((addnsub0_clear = "0") OR (addnsub0_clear = "none")) ELSE "0001" WHEN (addnsub0_clear = "1") ELSE "0010" WHEN (addnsub0_clear = "2") ELSE "0011" WHEN (addnsub0_clear = "3") ELSE "0000" ;
addnsub1_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
if_aclr => clear_addnsub1,
ena => ena_addnsub1,
dataout => addnsub1_pipe,
async => async_addnsub1);
async_addnsub1 <= '1' WHEN (addnsub1_clock = "none") ELSE '0' ;
clear_addnsub1 <= '1' WHEN (addnsub1_clear /= "none") ELSE '0' ;
clk_addnsub1 <= '1' WHEN clk(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
aclr_addnsub1 <= '1' WHEN (aclr(conv_integer(addnsub1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1 <= '1' WHEN ena(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
addnsub1_clk <= "0000" WHEN ((addnsub1_clock = "0") OR (addnsub1_clock = "none")) ELSE "0001" WHEN (addnsub1_clock = "1") ELSE "0010" WHEN (addnsub1_clock = "2") ELSE "0011" WHEN (addnsub1_clock = "3") ELSE "0000" ;
addnsub1_aclr <= "0000" WHEN ((addnsub1_clear = "0") OR (addnsub1_clear = "none")) ELSE "0001" WHEN (addnsub1_clear = "1") ELSE "0010" WHEN (addnsub1_clear = "2") ELSE "0011" WHEN (addnsub1_clear = "3") ELSE "0000" ;
round0_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0,
clk => clk_round0,
aclr => aclr_round0,
if_aclr => clear_round0,
ena => ena_round0,
dataout => round0_pipe,
async => async_round0);
async_round0 <= '1' WHEN (round0_clock = "none") ELSE '0' ;
clear_round0 <= '1' WHEN (round0_clear /= "none") ELSE '0' ;
clk_round0 <= '1' WHEN clk(conv_integer(round0_clk)) = '1' ELSE '0' ;
aclr_round0 <= '1' WHEN (aclr(conv_integer(round0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0 <= '1' WHEN ena(conv_integer(round0_clk)) = '1' ELSE '0' ;
round0_clk <= "0000" WHEN ((round0_clock = "0") OR (round0_clock = "none")) ELSE "0001" WHEN (round0_clock = "1") ELSE "0010" WHEN (round0_clock = "2") ELSE "0011" WHEN (round0_clock = "3") ELSE "0000" ;
round0_aclr <= "0000" WHEN ((round0_clear = "0") OR (round0_clear = "none")) ELSE "0001" WHEN (round0_clear = "1") ELSE "0010" WHEN (round0_clear = "2") ELSE "0011" WHEN (round0_clear = "3") ELSE "0000" ;
saturate_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_pipe,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode0_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0,
clk => clk_mode0,
aclr => aclr_mode0,
if_aclr => clear_mode0,
ena => ena_mode0,
dataout => mode0_pipe,
async => async_mode0);
async_mode0 <= '1' WHEN (mode0_clock = "none") ELSE '0' ;
clear_mode0 <= '1' WHEN (mode0_clear /= "none") ELSE '0' ;
clk_mode0 <= '1' WHEN clk(conv_integer(mode0_clk)) = '1' ELSE '0' ;
aclr_mode0 <= '1' WHEN (aclr(conv_integer(mode0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0 <= '1' WHEN ena(conv_integer(mode0_clk)) = '1' ELSE '0' ;
mode0_clk <= "0000" WHEN ((mode0_clock = "0") OR (mode0_clock = "none")) ELSE "0001" WHEN (mode0_clock = "1") ELSE "0010" WHEN (mode0_clock = "2") ELSE "0011" WHEN (mode0_clock = "3") ELSE "0000" ;
mode0_aclr <= "0000" WHEN ((mode0_clear = "0") OR (mode0_clear = "none")) ELSE "0001" WHEN (mode0_clear = "1") ELSE "0010" WHEN (mode0_clear = "2") ELSE "0011" WHEN (mode0_clear = "3") ELSE "0000" ;
round1_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1,
clk => clk_round1,
aclr => aclr_round1,
if_aclr => clear_round1,
ena => ena_round1,
dataout => round1_pipe,
async => async_round1);
async_round1 <= '1' WHEN (round1_clock = "none") ELSE '0' ;
clear_round1 <= '1' WHEN (round1_clear /= "none") ELSE '0' ;
clk_round1 <= '1' WHEN clk(conv_integer(round1_clk)) = '1' ELSE '0' ;
aclr_round1 <= '1' WHEN (aclr(conv_integer(round1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1 <= '1' WHEN ena(conv_integer(round1_clk)) = '1' ELSE '0' ;
round1_clk <= "0000" WHEN ((round1_clock = "0") OR (round1_clock = "none")) ELSE "0001" WHEN (round1_clock = "1") ELSE "0010" WHEN (round1_clock = "2") ELSE "0011" WHEN (round1_clock = "3") ELSE "0000" ;
round1_aclr <= "0000" WHEN ((round1_clear = "0") OR (round1_clear = "none")) ELSE "0001" WHEN (round1_clear = "1") ELSE "0010" WHEN (round1_clear = "2") ELSE "0011" WHEN (round1_clear = "3") ELSE "0000" ;
saturate1_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1,
clk => clk_saturate1,
aclr => aclr_saturate1,
if_aclr => clear_saturate1,
ena => ena_saturate1,
dataout => saturate1_pipe,
async => async_saturate1);
async_saturate1 <= '1' WHEN (saturate1_clock = "none") ELSE '0' ;
clear_saturate1 <= '1' WHEN (saturate1_clear /= "none") ELSE '0' ;
clk_saturate1 <= '1' WHEN clk(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
aclr_saturate1 <= '1' WHEN (aclr(conv_integer(saturate1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1 <= '1' WHEN ena(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
saturate1_clk <= "0000" WHEN ((saturate1_clock = "0") OR (saturate1_clock = "none")) ELSE "0001" WHEN (saturate1_clock = "1") ELSE "0010" WHEN (saturate1_clock = "2") ELSE "0011" WHEN (saturate1_clock = "3") ELSE "0000" ;
saturate1_aclr <= "0000" WHEN ((saturate1_clear = "0") OR (saturate1_clear = "none")) ELSE "0001" WHEN (saturate1_clear = "1") ELSE "0010" WHEN (saturate1_clear = "2") ELSE "0011" WHEN (saturate1_clear = "3") ELSE "0000" ;
mode1_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1,
clk => clk_mode1,
aclr => aclr_mode1,
if_aclr => clear_mode1,
ena => ena_mode1,
dataout => mode1_pipe,
async => async_mode1);
async_mode1 <= '1' WHEN (mode1_clock = "none") ELSE '0' ;
clear_mode1 <= '1' WHEN (mode1_clear /= "none") ELSE '0' ;
clk_mode1 <= '1' WHEN clk(conv_integer(mode1_clk)) = '1' ELSE '0' ;
aclr_mode1 <= '1' WHEN (aclr(conv_integer(mode1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1 <= '1' WHEN ena(conv_integer(mode1_clk)) = '1' ELSE '0' ;
mode1_clk <= "0000" WHEN ((mode1_clock = "0") OR (mode1_clock = "none")) ELSE "0001" WHEN (mode1_clock = "1") ELSE "0010" WHEN (mode1_clock = "2") ELSE "0011" WHEN (mode1_clock = "3") ELSE "0000" ;
mode1_aclr <= "0000" WHEN ((mode1_clear = "0") OR (mode1_clear = "none")) ELSE "0001" WHEN (mode1_clear = "1") ELSE "0010" WHEN (mode1_clear = "2") ELSE "0011" WHEN (mode1_clear = "3") ELSE "0000" ;
multabsaturate_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate,
clk => clk_multabsaturate,
aclr => aclr_multabsaturate,
if_aclr => clear_multabsaturate,
ena => ena_multabsaturate,
dataout => multabsaturate_pipe,
async => async_multabsaturate);
async_multabsaturate <= '1' WHEN (multabsaturate_clock = "none") ELSE '0' ;
clear_multabsaturate <= '1' WHEN (multabsaturate_clear /= "none") ELSE '0' ;
clk_multabsaturate <= '1' WHEN clk(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
aclr_multabsaturate <= '1' WHEN (aclr(conv_integer(multabsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate <= '1' WHEN ena(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
multabsaturate_clk <= "0000" WHEN ((multabsaturate_clock = "0") OR (multabsaturate_clock = "none")) ELSE "0001" WHEN (multabsaturate_clock = "1") ELSE "0010" WHEN (multabsaturate_clock = "2") ELSE "0011" WHEN (multabsaturate_clock = "3") ELSE "0000" ;
multabsaturate_aclr <= "0000" WHEN ((multabsaturate_clear = "0") OR (multabsaturate_clear = "none")) ELSE "0001" WHEN (multabsaturate_clear = "1") ELSE "0010" WHEN (multabsaturate_clear = "2") ELSE "0011" WHEN (multabsaturate_clear = "3") ELSE "0000" ;
multcdsaturate_mac_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate,
clk => clk_multcdsaturate,
aclr => aclr_multcdsaturate,
if_aclr => clear_multcdsaturate,
ena => ena_multcdsaturate,
dataout => multcdsaturate_pipe,
async => async_multcdsaturate);
async_multcdsaturate <= '1' WHEN (multcdsaturate_clock = "none") ELSE '0' ;
clear_multcdsaturate <= '1' WHEN (multcdsaturate_clear /= "none") ELSE '0' ;
clk_multcdsaturate <= '1' WHEN clk(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate <= '1' WHEN (aclr(conv_integer(multcdsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate <= '1' WHEN ena(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
multcdsaturate_clk <= "0000" WHEN ((multcdsaturate_clock = "0") OR (multcdsaturate_clock = "none")) ELSE "0001" WHEN (multcdsaturate_clock = "1") ELSE "0010" WHEN (multcdsaturate_clock = "2") ELSE "0011" WHEN (multcdsaturate_clock = "3") ELSE "0000" ;
multcdsaturate_aclr <= "0000" WHEN ((multcdsaturate_clear = "0") OR (multcdsaturate_clear = "none")) ELSE "0001" WHEN (multcdsaturate_clear = "1") ELSE "0010" WHEN (multcdsaturate_clear = "2") ELSE "0011" WHEN (multcdsaturate_clear = "3") ELSE "0000" ;
signa_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
if_aclr => clear_signa_pipeline,
ena => ena_signa_pipeline,
dataout => signa_out,
async => async_signa_pipeline);
async_signa_pipeline <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0' ;
clear_signa_pipeline <= '1' WHEN (signa_pipeline_clear /= "none") ELSE '0' ;
clk_signa_pipeline <= '1' WHEN clk(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
aclr_signa_pipeline <= '1' WHEN (aclr(conv_integer(signa_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa_pipeline <= '1' WHEN ena(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
signa_pipeline_clk <= "0000" WHEN ((signa_pipeline_clock = "0") OR (signa_pipeline_clock = "none")) ELSE "0001" WHEN (signa_pipeline_clock = "1") ELSE "0010" WHEN (signa_pipeline_clock = "2") ELSE "0011" WHEN (signa_pipeline_clock = "3") ELSE "0000" ;
signa_pipeline_aclr <= "0000" WHEN ((signa_pipeline_clear = "0") OR (signa_pipeline_clear = "none")) ELSE "0001" WHEN (signa_pipeline_clear = "1") ELSE "0010" WHEN (signa_pipeline_clear = "2") ELSE "0011" WHEN (signa_pipeline_clear = "3") ELSE "0000" ;
signb_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
if_aclr => clear_signb_pipeline,
ena => ena_signb_pipeline,
dataout => signb_out,
async => async_signb_pipeline);
async_signb_pipeline <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0' ;
clear_signb_pipeline <= '1' WHEN (signb_pipeline_clear /= "none") ELSE '0' ;
clk_signb_pipeline <= '1' WHEN clk(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
aclr_signb_pipeline <= '1' WHEN (aclr(conv_integer(signb_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb_pipeline <= '1' WHEN ena(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
signb_pipeline_clk <= "0000" WHEN ((signb_pipeline_clock = "0") OR (signb_pipeline_clock = "none")) ELSE "0001" WHEN (signb_pipeline_clock = "1") ELSE "0010" WHEN (signb_pipeline_clock = "2") ELSE "0011" WHEN (signb_pipeline_clock = "3") ELSE "0000" ;
signb_pipeline_aclr <= "0000" WHEN ((signb_pipeline_clear = "0") OR (signb_pipeline_clear = "none")) ELSE "0001" WHEN (signb_pipeline_clear = "1") ELSE "0010" WHEN (signb_pipeline_clear = "2") ELSE "0011" WHEN (signb_pipeline_clear = "3") ELSE "0000" ;
zeroacc_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
if_aclr => clear_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
dataout => zeroacc_out,
async => async_zeroacc_pipeline);
async_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc_pipeline <= '1' WHEN clk(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc_pipeline <= '1' WHEN ena(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
zeroacc_pipeline_clk <= "0000" WHEN ((zeroacc_pipeline_clock = "0") OR (zeroacc_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc_pipeline_clock = "3") ELSE "0000" ;
zeroacc_pipeline_aclr <= "0000" WHEN ((zeroacc_pipeline_clear = "0") OR (zeroacc_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc_pipeline_clear = "3") ELSE "0000" ;
zeroacc1_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1_pipe,
clk => clk_zeroacc1_pipeline,
aclr => aclr_zeroacc1_pipeline,
if_aclr => clear_zeroacc1_pipeline,
ena => ena_zeroacc1_pipeline,
dataout => zeroacc1_out,
async => async_zeroacc1_pipeline);
async_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc1_pipeline <= '1' WHEN clk(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc1_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1_pipeline <= '1' WHEN ena(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
zeroacc1_pipeline_clk <= "0000" WHEN ((zeroacc1_pipeline_clock = "0") OR (zeroacc1_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clock = "3") ELSE "0000" ;
zeroacc1_pipeline_aclr <= "0000" WHEN ((zeroacc1_pipeline_clear = "0") OR (zeroacc1_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clear = "3") ELSE "0000" ;
addnsub0_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
if_aclr => clear_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
dataout => addnsub0_out,
async => async_addnsub0_pipeline);
async_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clock = "none") ELSE '0' ;
clear_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub0_pipeline <= '1' WHEN clk(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub0_pipeline <= '1' WHEN (aclr(conv_integer(addnsub0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0_pipeline <= '1' WHEN ena(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
addnsub0_pipeline_clk <= "0000" WHEN ((addnsub0_pipeline_clock = "0") OR (addnsub0_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clock = "1") ELSE "0010" WHEN (addnsub0_pipeline_clock = "2") ELSE "0011" WHEN (addnsub0_pipeline_clock = "3") ELSE "0000" ;
addnsub0_pipeline_aclr <= "0000" WHEN ((addnsub0_pipeline_clear = "0") OR (addnsub0_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clear = "1") ELSE "0010" WHEN (addnsub0_pipeline_clear = "2") ELSE "0011" WHEN (addnsub0_pipeline_clear = "3") ELSE "0000" ;
addnsub1_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
if_aclr => clear_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
dataout => addnsub1_out,
async => async_addnsub1_pipeline);
async_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clock = "none") ELSE '0' ;
clear_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub1_pipeline <= '1' WHEN clk(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub1_pipeline <= '1' WHEN (aclr(conv_integer(addnsub1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1_pipeline <= '1' WHEN ena(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
addnsub1_pipeline_clk <= "0000" WHEN ((addnsub1_pipeline_clock = "0") OR (addnsub1_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clock = "1") ELSE "0010" WHEN (addnsub1_pipeline_clock = "2") ELSE "0011" WHEN (addnsub1_pipeline_clock = "3") ELSE "0000" ;
addnsub1_pipeline_aclr <= "0000" WHEN ((addnsub1_pipeline_clear = "0") OR (addnsub1_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clear = "1") ELSE "0010" WHEN (addnsub1_pipeline_clear = "2") ELSE "0011" WHEN (addnsub1_pipeline_clear = "3") ELSE "0000" ;
round0_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0_pipe,
clk => clk_round0_pipeline,
aclr => aclr_round0_pipeline,
if_aclr => clear_round0_pipeline,
ena => ena_round0_pipeline,
dataout => round0_out,
async => async_round0_pipeline);
async_round0_pipeline <= '1' WHEN (round0_pipeline_clock = "none") ELSE '0' ;
clear_round0_pipeline <= '1' WHEN (round0_pipeline_clear /= "none") ELSE '0' ;
clk_round0_pipeline <= '1' WHEN clk(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
aclr_round0_pipeline <= '1' WHEN (aclr(conv_integer(round0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0_pipeline <= '1' WHEN ena(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
round0_pipeline_clk <= "0000" WHEN ((round0_pipeline_clock = "0") OR (round0_pipeline_clock = "none")) ELSE "0001" WHEN (round0_pipeline_clock = "1") ELSE "0010" WHEN (round0_pipeline_clock = "2") ELSE "0011" WHEN (round0_pipeline_clock = "3") ELSE "0000" ;
round0_pipeline_aclr <= "0000" WHEN ((round0_pipeline_clear = "0") OR (round0_pipeline_clear = "none")) ELSE "0001" WHEN (round0_pipeline_clear = "1") ELSE "0010" WHEN (round0_pipeline_clear = "2") ELSE "0011" WHEN (round0_pipeline_clear = "3") ELSE "0000" ;
saturate_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate_pipe,
clk => clk_saturate_pipeline,
aclr => aclr_saturate_pipeline,
if_aclr => clear_saturate_pipeline,
ena => ena_saturate_pipeline,
dataout => saturate_out,
async => async_saturate_pipeline);
async_saturate_pipeline <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0' ;
clear_saturate_pipeline <= '1' WHEN (saturate_pipeline_clear /= "none") ELSE '0' ;
clk_saturate_pipeline <= '1' WHEN clk(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate_pipeline <= '1' WHEN (aclr(conv_integer(saturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate_pipeline <= '1' WHEN ena(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
saturate_pipeline_clk <= "0000" WHEN ((saturate_pipeline_clock = "0") OR (saturate_pipeline_clock = "none")) ELSE "0001" WHEN (saturate_pipeline_clock = "1") ELSE "0010" WHEN (saturate_pipeline_clock = "2") ELSE "0011" WHEN (saturate_pipeline_clock = "3") ELSE "0000" ;
saturate_pipeline_aclr <= "0000" WHEN ((saturate_pipeline_clear = "0") OR (saturate_pipeline_clear = "none")) ELSE "0001" WHEN (saturate_pipeline_clear = "1") ELSE "0010" WHEN (saturate_pipeline_clear = "2") ELSE "0011" WHEN (saturate_pipeline_clear = "3") ELSE "0000" ;
mode0_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0_pipe,
clk => clk_mode0_pipeline,
aclr => aclr_mode0_pipeline,
if_aclr => clear_mode0_pipeline,
ena => ena_mode0_pipeline,
dataout => mode0_out,
async => async_mode0_pipeline);
async_mode0_pipeline <= '1' WHEN (mode0_pipeline_clock = "none") ELSE '0' ;
clear_mode0_pipeline <= '1' WHEN (mode0_pipeline_clear /= "none") ELSE '0' ;
clk_mode0_pipeline <= '1' WHEN clk(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode0_pipeline <= '1' WHEN (aclr(conv_integer(mode0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0_pipeline <= '1' WHEN ena(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
mode0_pipeline_clk <= "0000" WHEN ((mode0_pipeline_clock = "0") OR (mode0_pipeline_clock = "none")) ELSE "0001" WHEN (mode0_pipeline_clock = "1") ELSE "0010" WHEN (mode0_pipeline_clock = "2") ELSE "0011" WHEN (mode0_pipeline_clock = "3") ELSE "0000" ;
mode0_pipeline_aclr <= "0000" WHEN ((mode0_pipeline_clear = "0") OR (mode0_pipeline_clear = "none")) ELSE "0001" WHEN (mode0_pipeline_clear = "1") ELSE "0010" WHEN (mode0_pipeline_clear = "2") ELSE "0011" WHEN (mode0_pipeline_clear = "3") ELSE "0000" ;
round1_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1_pipe,
clk => clk_round1_pipeline,
aclr => aclr_round1_pipeline,
if_aclr => clear_round1_pipeline,
ena => ena_round1_pipeline,
dataout => round1_out,
async => async_round1_pipeline);
async_round1_pipeline <= '1' WHEN (round1_pipeline_clock = "none") ELSE '0' ;
clear_round1_pipeline <= '1' WHEN (round1_pipeline_clear /= "none") ELSE '0' ;
clk_round1_pipeline <= '1' WHEN clk(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
aclr_round1_pipeline <= '1' WHEN (aclr(conv_integer(round1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1_pipeline <= '1' WHEN ena(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
round1_pipeline_clk <= "0000" WHEN ((round1_pipeline_clock = "0") OR (round1_pipeline_clock = "none")) ELSE "0001" WHEN (round1_pipeline_clock = "1") ELSE "0010" WHEN (round1_pipeline_clock = "2") ELSE "0011" WHEN (round1_pipeline_clock = "3") ELSE "0000" ;
round1_pipeline_aclr <= "0000" WHEN ((round1_pipeline_clear = "0") OR (round1_pipeline_clear = "none")) ELSE "0001" WHEN (round1_pipeline_clear = "1") ELSE "0010" WHEN (round1_pipeline_clear = "2") ELSE "0011" WHEN (round1_pipeline_clear = "3") ELSE "0000" ;
saturate1_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1_pipe,
clk => clk_saturate1_pipeline,
aclr => aclr_saturate1_pipeline,
if_aclr => clear_saturate1_pipeline,
ena => ena_saturate1_pipeline,
dataout => saturate1_out,
async => async_saturate1_pipeline);
async_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clock = "none") ELSE '0' ;
clear_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clear /= "none") ELSE '0' ;
clk_saturate1_pipeline <= '1' WHEN clk(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate1_pipeline <= '1' WHEN (aclr(conv_integer(saturate1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1_pipeline <= '1' WHEN ena(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
saturate1_pipeline_clk <= "0000" WHEN ((saturate1_pipeline_clock = "0") OR (saturate1_pipeline_clock = "none")) ELSE "0001" WHEN (saturate1_pipeline_clock = "1") ELSE "0010" WHEN (saturate1_pipeline_clock = "2") ELSE "0011" WHEN (saturate1_pipeline_clock = "3") ELSE "0000" ;
saturate1_pipeline_aclr <= "0000" WHEN ((saturate1_pipeline_clear = "0") OR (saturate1_pipeline_clear = "none")) ELSE "0001" WHEN (saturate1_pipeline_clear = "1") ELSE "0010" WHEN (saturate1_pipeline_clear = "2") ELSE "0011" WHEN (saturate1_pipeline_clear = "3") ELSE "0000" ;
mode1_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1_pipe,
clk => clk_mode1_pipeline,
aclr => aclr_mode1_pipeline,
if_aclr => clear_mode1_pipeline,
ena => ena_mode1_pipeline,
dataout => mode1_out,
async => async_mode1_pipeline);
async_mode1_pipeline <= '1' WHEN (mode1_pipeline_clock = "none") ELSE '0' ;
clear_mode1_pipeline <= '1' WHEN (mode1_pipeline_clear /= "none") ELSE '0' ;
clk_mode1_pipeline <= '1' WHEN clk(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode1_pipeline <= '1' WHEN (aclr(conv_integer(mode1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1_pipeline <= '1' WHEN ena(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
mode1_pipeline_clk <= "0000" WHEN ((mode1_pipeline_clock = "0") OR (mode1_pipeline_clock = "none")) ELSE "0001" WHEN (mode1_pipeline_clock = "1") ELSE "0010" WHEN (mode1_pipeline_clock = "2") ELSE "0011" WHEN (mode1_pipeline_clock = "3") ELSE "0000" ;
mode1_pipeline_aclr <= "0000" WHEN ((mode1_pipeline_clear = "0") OR (mode1_pipeline_clear = "none")) ELSE "0001" WHEN (mode1_pipeline_clear = "1") ELSE "0010" WHEN (mode1_pipeline_clear = "2") ELSE "0011" WHEN (mode1_pipeline_clear = "3") ELSE "0000" ;
multabsaturate_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate_pipe,
clk => clk_multabsaturate_pipeline,
aclr => aclr_multabsaturate_pipeline,
if_aclr => clear_multabsaturate_pipeline,
ena => ena_multabsaturate_pipeline,
dataout => multabsaturate_out,
async => async_multabsaturate_pipeline);
async_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multabsaturate_pipeline <= '1' WHEN clk(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multabsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multabsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate_pipeline <= '1' WHEN ena(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
multabsaturate_pipeline_clk <= "0000" WHEN ((multabsaturate_pipeline_clock = "0") OR (multabsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clock = "3") ELSE "0000" ;
multabsaturate_pipeline_aclr <= "0000" WHEN ((multabsaturate_pipeline_clear = "0") OR (multabsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clear = "3") ELSE "0000" ;
multcdsaturate_mac_pipeline_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate_pipe,
clk => clk_multcdsaturate_pipeline,
aclr => aclr_multcdsaturate_pipeline,
if_aclr => clear_multcdsaturate_pipeline,
ena => ena_multcdsaturate_pipeline,
dataout => multcdsaturate_out,
async => async_multcdsaturate_pipeline);
async_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multcdsaturate_pipeline <= '1' WHEN clk(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multcdsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate_pipeline <= '1' WHEN ena(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
multcdsaturate_pipeline_clk <= "0000" WHEN ((multcdsaturate_pipeline_clock = "0") OR (multcdsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clock = "3") ELSE "0000" ;
multcdsaturate_pipeline_aclr <= "0000" WHEN ((multcdsaturate_pipeline_clear = "0") OR (multcdsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clear = "3") ELSE "0000" ;
dataa_f <= (others => '0') WHEN (dataa_forced_to_zero = "yes") ELSE dataa ;
datac_f <= (others => '0') WHEN (datac_forced_to_zero = "yes") ELSE datac ;
mac_adder : arriagx_mac_out_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
operation_mode => operation_mode)
PORT MAP (
dataa => dataa_f,
datab => datab,
datac => datac_f,
datad => datad,
mode0 => mode0_out,
mode1 => mode1_out,
zeroacc => zeroacc_out,
zeroacc1 => zeroacc1_out,
roundab => round0_out,
roundcd => round1_out,
saturateab => saturate_out,
saturatecd => saturate1_out,
multabsaturate => multabsaturate_out,
multcdsaturate => multcdsaturate_out,
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
feedback => dataout_feedback,
dataout => dataout_map(dataout_width -1 downto 0),
accoverflow => accoverflow_reg);
pin_map_addnsub <= addnsub0_out AND addnsub1_out;
mac_pin_map : arriagx_mac_pin_map
GENERIC MAP (
operation_mode => operation_mode,
data_width => tmp_width,
pinmap => "map")
PORT MAP (
datain => dataout_map,
operation => operation,
addnsub => pin_map_addnsub,
dataout => dataout_to_reg);
output0_reg : arriagx_mac_register
GENERIC MAP (
data_width => dataout_width,
power_up => '0')
PORT MAP (
data => dataout_to_reg(dataout_width -1 DOWNTO 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_non_dynamic(dataout_width -1 DOWNTO 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
output1_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(35 DOWNTO 18),
clk => clk_output1,
aclr => aclr_output1,
if_aclr => clear_output1,
ena => ena_output1,
dataout => dataout_dynamic1(17 downto 0),
async => async_output1);
async_output1 <= '1' WHEN (output1_clock = "none") ELSE '0' ;
clear_output1 <= '1' WHEN (output1_clear /= "none") ELSE '0' ;
clk_output1 <= '1' WHEN clk(conv_integer(output1_clk)) = '1' ELSE '0' ;
aclr_output1 <= '1' WHEN (aclr(conv_integer(output1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output1 <= '1' WHEN ena(conv_integer(output1_clk)) = '1' ELSE '0' ;
output1_clk <= "0000" WHEN ((output1_clock = "0") OR (output1_clock = "none")) ELSE "0001" WHEN (output1_clock = "1") ELSE "0010" WHEN (output1_clock = "2") ELSE "0011" WHEN (output1_clock = "3") ELSE "0000" ;
output1_aclr <= "0000" WHEN ((output1_clear = "0") OR (output1_clear = "none")) ELSE "0001" WHEN (output1_clear = "1") ELSE "0010" WHEN (output1_clear = "2") ELSE "0011" WHEN (output1_clear = "3") ELSE "0000" ;
output2_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(53 DOWNTO 36),
clk => clk_output2,
aclr => aclr_output2,
if_aclr => clear_output2,
ena => ena_output2,
dataout => dataout_dynamic2(17 downto 0),
async => async_output2);
async_output2 <= '1' WHEN (output2_clock = "none") ELSE '0' ;
clear_output2 <= '1' WHEN (output2_clear /= "none") ELSE '0' ;
clk_output2 <= '1' WHEN clk(conv_integer(output2_clk)) = '1' ELSE '0' ;
aclr_output2 <= '1' WHEN (aclr(conv_integer(output2_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output2 <= '1' WHEN ena(conv_integer(output2_clk)) = '1' ELSE '0' ;
output2_clk <= "0000" WHEN ((output2_clock = "0") OR (output2_clock = "none")) ELSE "0001" WHEN (output2_clock = "1") ELSE "0010" WHEN (output2_clock = "2") ELSE "0011" WHEN (output2_clock = "3") ELSE "0000" ;
output2_aclr <= "0000" WHEN ((output2_clear = "0") OR (output2_clear = "none")) ELSE "0001" WHEN (output2_clear = "1") ELSE "0010" WHEN (output2_clear = "2") ELSE "0011" WHEN (output2_clear = "3") ELSE "0000" ;
output3_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(71 DOWNTO 54),
clk => clk_output3,
aclr => aclr_output3,
if_aclr => clear_output3,
ena => ena_output3,
dataout => dataout_dynamic3(17 downto 0),
async => async_output3);
async_output3 <= '1' WHEN (output3_clock = "none") ELSE '0' ;
clear_output3 <= '1' WHEN (output3_clear /= "none") ELSE '0' ;
clk_output3 <= '1' WHEN clk(conv_integer(output3_clk)) = '1' ELSE '0' ;
aclr_output3 <= '1' WHEN (aclr(conv_integer(output3_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output3 <= '1' WHEN ena(conv_integer(output3_clk)) = '1' ELSE '0' ;
output3_clk <= "0000" WHEN ((output3_clock = "0") OR (output3_clock = "none")) ELSE "0001" WHEN (output3_clock = "1") ELSE "0010" WHEN (output3_clock = "2") ELSE "0011" WHEN (output3_clock = "3") ELSE "0000" ;
output3_aclr <= "0000" WHEN ((output3_clear = "0") OR (output3_clear = "none")) ELSE "0001" WHEN (output3_clear = "1") ELSE "0010" WHEN (output3_clear = "2") ELSE "0011" WHEN (output3_clear = "3") ELSE "0000" ;
output4_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(89 DOWNTO 72),
clk => clk_output4,
aclr => aclr_output4,
if_aclr => clear_output4,
ena => ena_output4,
dataout => dataout_dynamic4(17 downto 0),
async => async_output4);
async_output4 <= '1' WHEN (output4_clock = "none") ELSE '0' ;
clear_output4 <= '1' WHEN (output4_clear /= "none") ELSE '0' ;
clk_output4 <= '1' WHEN clk(conv_integer(output4_clk)) = '1' ELSE '0' ;
aclr_output4 <= '1' WHEN (aclr(conv_integer(output4_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output4 <= '1' WHEN ena(conv_integer(output4_clk)) = '1' ELSE '0' ;
output4_clk <= "0000" WHEN ((output4_clock = "0") OR (output4_clock = "none")) ELSE "0001" WHEN (output4_clock = "1") ELSE "0010" WHEN (output4_clock = "2") ELSE "0011" WHEN (output4_clock = "3") ELSE "0000" ;
output4_aclr <= "0000" WHEN ((output4_clear = "0") OR (output4_clear = "none")) ELSE "0001" WHEN (output4_clear = "1") ELSE "0010" WHEN (output4_clear = "2") ELSE "0011" WHEN (output4_clear = "3") ELSE "0000" ;
output5_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(107 DOWNTO 90),
clk => clk_output5,
aclr => aclr_output5,
if_aclr => clear_output5,
ena => ena_output5,
dataout => dataout_dynamic5(17 downto 0),
async => async_output5);
async_output5 <= '1' WHEN (output5_clock = "none") ELSE '0' ;
clear_output5 <= '1' WHEN (output5_clear /= "none") ELSE '0' ;
clk_output5 <= '1' WHEN clk(conv_integer(output5_clk)) = '1' ELSE '0' ;
aclr_output5 <= '1' WHEN (aclr(conv_integer(output5_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output5 <= '1' WHEN ena(conv_integer(output5_clk)) = '1' ELSE '0' ;
output5_clk <= "0000" WHEN ((output5_clock = "0") OR (output5_clock = "none")) ELSE "0001" WHEN (output5_clock = "1") ELSE "0010" WHEN (output5_clock = "2") ELSE "0011" WHEN (output5_clock = "3") ELSE "0000" ;
output5_aclr <= "0000" WHEN ((output5_clear = "0") OR (output5_clear = "none")) ELSE "0001" WHEN (output5_clear = "1") ELSE "0010" WHEN (output5_clear = "2") ELSE "0011" WHEN (output5_clear = "3") ELSE "0000" ;
output6_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(125 DOWNTO 108),
clk => clk_output6,
aclr => aclr_output6,
if_aclr => clear_output6,
ena => ena_output6,
dataout => dataout_dynamic6(17 downto 0),
async => async_output6);
async_output6 <= '1' WHEN (output6_clock = "none") ELSE '0' ;
clear_output6 <= '1' WHEN (output6_clear /= "none") ELSE '0' ;
clk_output6 <= '1' WHEN clk(conv_integer(output6_clk)) = '1' ELSE '0' ;
aclr_output6 <= '1' WHEN (aclr(conv_integer(output6_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output6 <= '1' WHEN ena(conv_integer(output6_clk)) = '1' ELSE '0' ;
output6_clk <= "0000" WHEN ((output6_clock = "0") OR (output6_clock = "none")) ELSE "0001" WHEN (output6_clock = "1") ELSE "0010" WHEN (output6_clock = "2") ELSE "0011" WHEN (output6_clock = "3") ELSE "0000" ;
output6_aclr <= "0000" WHEN ((output6_clear = "0") OR (output6_clear = "none")) ELSE "0001" WHEN (output6_clear = "1") ELSE "0010" WHEN (output6_clear = "2") ELSE "0011" WHEN (output6_clear = "3") ELSE "0000" ;
output7_reg : arriagx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(tmp_width-1 DOWNTO 126),
clk => clk_output7,
aclr => aclr_output7,
if_aclr => clear_output7,
ena => ena_output7,
dataout => dataout_dynamic7(17 downto 0),
async => async_output7);
async_output7 <= '1' WHEN (output7_clock = "none") ELSE '0' ;
clear_output7 <= '1' WHEN (output7_clear /= "none") ELSE '0' ;
clk_output7 <= '1' WHEN clk(conv_integer(output7_clk)) = '1' ELSE '0' ;
aclr_output7 <= '1' WHEN (aclr(conv_integer(output7_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output7 <= '1' WHEN ena(conv_integer(output7_clk)) = '1' ELSE '0' ;
output7_clk <= "0000" WHEN ((output7_clock = "0") OR (output7_clock = "none")) ELSE "0001" WHEN (output7_clock = "1") ELSE "0010" WHEN (output7_clock = "2") ELSE "0011" WHEN (output7_clock = "3") ELSE "0000" ;
output7_aclr <= "0000" WHEN ((output7_clear = "0") OR (output7_clear = "none")) ELSE "0001" WHEN (output7_clear = "1") ELSE "0010" WHEN (output7_clear = "2") ELSE "0011" WHEN (output7_clear = "3") ELSE "0000" ;
tmp_186 <= '1' when (output_clear /= "none") else '0';
tmp_189 <= '1' when (output_clock = "none") else '0';
accoverflow_out_reg : arriagx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => accoverflow_reg,
clk => clk_output,
aclr => aclr_output,
if_aclr => tmp_186,
ena => ena_output,
dataout => accoverflow_tmp,
async => tmp_189);
dataout_dynamic(tmp_width-1 DOWNTO 0) <= dataout_dynamic7(17 DOWNTO 0) & dataout_dynamic6(17 DOWNTO 0) & dataout_dynamic5(17 DOWNTO 0) & dataout_dynamic4(17 DOWNTO 0) & dataout_dynamic3(17 DOWNTO 0) & dataout_dynamic2(17 DOWNTO 0) & dataout_dynamic1(17 DOWNTO 0) & dataout_non_dynamic(17 DOWNTO 0) ;
dataout_tmp <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '0')) AND (zeroacc1_out = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '1')) AND (zeroacc1_out = '1')) ELSE "0000" ;
dataout_feedback <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
accoverflow_tmp2 <= accoverflow_tmp;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of arriagx_lvds_tx_reg : ENTITY is TRUE;
END arriagx_lvds_tx_reg;
ARCHITECTURE vital_arriagx_lvds_tx_reg of arriagx_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_arriagx_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriagx_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriagx_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriagx_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the StratixIIGXLITE
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE std.textio.all;
ENTITY arriagx_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END arriagx_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of arriagx_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/arriagx_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriagx_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE std.textio.all;
ENTITY arriagx_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END arriagx_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of arriagx_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriagx_lvds_transmitter
--
-- Description : Timing simulation model for the StratixIIGXLITE LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) StratixIIGXLITE_lvds_tx_parallel_register and
-- 3) StratixIIGXLITE_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE std.textio.all;
USE work.arriagx_lvds_tx_parallel_register;
USE work.arriagx_lvds_tx_out_block;
USE work.arriagx_lvds_tx_reg;
ENTITY arriagx_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriagx_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end arriagx_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of arriagx_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT arriagx_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT arriagx_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT arriagx_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: arriagx_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: arriagx_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: arriagx_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END arriagx_lvds_reg;
ARCHITECTURE vital_arriagx_lvds_reg of arriagx_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriagx_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END arriagx_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF arriagx_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE work.arriagx_lvds_rx_fifo_sync_ram;
ENTITY arriagx_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END arriagx_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of arriagx_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT arriagx_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : arriagx_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE work.arriagx_lvds_reg;
ENTITY arriagx_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END arriagx_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF arriagx_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT arriagx_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : arriagx_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Bit Slip shift register
-- process (clk0_in, bsliprst_in)
-- begin
-- if (bsliprst_in = '1') then
-- elsif (clk0_in'event and clk0_in = '1' and clk0'last_value = '0') then
-- bitslip_arr(0) <= datain_in;
-- for i in 0 to (bitslip_rollover - 1) loop
-- bitslip_arr(i + 1) <= bitslip_arr(i);
-- end loop;
--
-- if (start_corrupt_bits = '1') then
-- num_corrupt_bits <= num_corrupt_bits + 1;
-- end if;
-- if (num_corrupt_bits+1 = 3) then
-- start_corrupt_bits <= '0';
-- end if;
-- end if;
-- end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : arriagx_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_rx_deser
--
-- Description : Timing simulation model for the ARRIAGX LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF arriagx_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriagx_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the ARRIAGX LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
ENTITY arriagx_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF arriagx_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : ARRIAGX_LVDS_RECEIVER
--
-- Description : Timing simulation model for the ARRIAGX LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) arriagx_lvds_rx_fifo
-- 2) arriagx_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) arriagx_lvds_rx_parallel_reg
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriagx_atom_pack.all;
USE work.arriagx_lvds_rx_bitslip;
USE work.arriagx_lvds_rx_fifo;
USE work.arriagx_lvds_rx_deser;
USE work.arriagx_lvds_rx_parallel_reg;
USE work.arriagx_lvds_reg;
ENTITY arriagx_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "arriagx_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF arriagx_lvds_receiver IS
COMPONENT arriagx_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriagx_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriagx_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriagx_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriagx_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal first_dpa_lock : std_logic;
signal loadreg_datain : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_int : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal clk0_dly : std_logic;
signal datain_tmp : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
-- INTERNAL PARAMETERS
CONSTANT DPA_CYCLES_TO_LOCK : integer := 2;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpareg1_out WHEN (enable_dpa = "on") ELSE gnd ;
reset_int <= (NOT devpor) OR (NOT devclrn) ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpareset_ipd OR reset_fifo ;
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_dly <= clk0_ipd;
xhdl_12 <= devclrn OR devpor;
-- SUB-MODULE INSTANTIATION
-- input register in non-DPA mode for sampling incoming data
in_reg : arriagx_lvds_reg
PORT MAP ( d => in_reg_data,
clk => clk0_dly,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
datain_reg_tmp <= datain_reg;
dpa_clk <= clk0_ipd when (enable_dpa = "on") else '0' ;
dpa_rst <= dpareset_ipd when (enable_dpa = "on") else '0' ;
process (dpa_clk, dpa_rst)
variable dpa_lock_count : integer := 0;
variable dparst_msg : boolean := false;
variable dpa_is_locked : std_logic := '0';
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
if (enable_dpa = "on") then
ASSERT false report "DPA Phase tracking is not modeled, and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the StratixIIGXLITE device handbook for further details." severity warning;
end if;
initial := false;
end if;
if (dpa_rst = '1') then
dpa_is_locked := '0';
dpa_lock_count := 0;
if (not dparst_msg) then
ASSERT false report "DPA was reset" severity note;
dparst_msg := true;
end if;
elsif (dpa_clk'event and dpa_clk = '1') then
dparst_msg := false;
if (dpa_is_locked = '0') then
dpa_lock_count := dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK) then
dpa_is_locked := '1';
ASSERT false report "DPA locked" severity note;
reset_fifo <= '0';
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- ?????????? insert delay to mimic DPLL dataout ?????????
-- DPA registers
dpareg0 : arriagx_lvds_reg
PORT MAP ( d => in_reg_data,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : arriagx_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
s_fifo : arriagx_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => fifo_wclk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= slip_datain_tmp;
s_bitslip_clk <= clk0_dly;
s_bslip : arriagx_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
--********* DESERIALISER *********//
loaden <= enable0_ipd;
-- only 1 enable signal used for StratixIIGXLITE
rxload_reg : arriagx_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
s_deser : arriagx_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : arriagx_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
postdpaserialdataout <= dpareg1_out ;
serialdataout <= datain_ipd;
END vital_arm_lvds_receiver;
-------------------------------------------------------------------------------
--
-- Entity Name : StratixIIGXLITE_dll
--
-- Outputs : delayctrlout - current delay chain settings for DQS pin
-- offsetctrlout - current delay offset setting
-- dqsupdate - update enable signal for delay setting latces
-- upndnout - raw output of the phase comparator
--
-- Inputs : clk - reference clock matching in frequency to DQS clock
-- aload - asychronous load signal for delay setting counter
-- when asserted, counter is loaded with initial value
-- offset - offset added/subtracted from delayctrlout
-- upndnin - up/down input port for delay setting counter in
-- use_updndnin mode (user control mode)
-- upndninclkena - clock enable for the delaying setting counter
-- addnsub - dynamically control +/- on offsetctrlout
--
-- Formulae : delay (input_period) = sim_loop_intrinsic_delay +
-- sim_loop_delay_increment * dllcounter;
--
-- Latency : 3 (clk8 cycles) = pc + dc + dr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
USE work.arriagx_pllpack.all;
ENTITY arriagx_dll is
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "arriagx_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriagx_dll;
ARCHITECTURE vital_armdll of arriagx_dll is
-- tuncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal addnsub_in : std_logic := '0';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal dqsupdate_out : std_logic := '1';
signal upndn_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_offsetctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_offset : integer := 0;
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : integer := 0;
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_int : integer := 0;
signal dr_offset_in : integer := 0;
signal dr_dllcount_in : integer := 0;
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_offset : integer := 0;
signal dr_reg_dllcount : integer := 0;
signal dr_delayctrl_out_tmp : integer := 0;
-- delay chain setting counter
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_offset <= dqs_str2int(static_offset);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "offset_only" ELSE "10" WHEN delayctrlout_mode="normal_offset" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
para_offsetctrlout_mode <= "11" WHEN offsetctrlout_mode = "dynamic_addnsub" ELSE "10" WHEN offsetctrlout_mode = "dynamic_sub" ELSE "01" WHEN offsetctrlout_mode = "dynamic_add" ELSE "00";
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetctrl_out <= dr_offsetctrl_out;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_offset_in <= (64 - alt_conv_integer(offset_in)) WHEN ((offset_in /= "000000") AND ((offsetctrlout_mode = "dynamic_addnsub" AND addnsub_in = '0') or (offsetctrlout_mode = "dynamic_sub"))) ELSE
alt_conv_integer(offset_in);
dr_dllcount_in <= dc_dllcount_out;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in;
-- outputs
dr_delayctrl_out <= dll_unsigned2bin(dr_delayctrl_out_tmp);
dr_offsetctrl_out <= dll_unsigned2bin(dr_reg_offset);
dr_delayctrl_out_tmp <= dr_offset_in WHEN (delayctrlout_mode = "offset_only") ELSE
dr_reg_offset WHEN (delayctrlout_mode = "normal_offset") ELSE
dr_reg_dllcount;
dr_delayctrl_int <= para_static_delay_ctrl WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
dr_offsetctrl_int <= para_static_offset WHEN (offsetctrlout_mode = "static") ELSE
dr_offset_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= 0;
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= 0;
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (offsetctrlout_mode = "dynamic_addnsub") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
end if;
elsif (offsetctrlout_mode = "dynamic_sub") then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
elsif (offsetctrlout_mode = "dynamic_add") then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (offsetctrlout_mode = "static") then
if (para_static_offset >= 0) then
if ((para_static_offset < 64) AND (para_static_offset < 64 - dr_delayctrl_int)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 64;
end if;
else
if ((para_static_offset > -63) AND (dr_delayctrl_int > (-1)*para_static_offset)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 0;
end if;
end if;
else
dr_reg_offset <= 14; -- error
end if; -- modes
end if; -- rising clock
end process ; -- generating dr_reg_offset
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount;
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
pc_delay <= pc_var_delay;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, upndn_in, upndninclkena_in, addnsub_in,
delayctrl_out, offsetctrl_out, dqsupdate_out, upndn_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/SRRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetctrlout <= offsetctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_armdll;
--
--
-- ARRIAGX_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.arriagx_atom_pack.all;
entity arriagx_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriagx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end arriagx_rublock;
architecture architecture_rublock of arriagx_rublock is
signal update_reg : std_logic_vector(20 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(25 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is output of shift-reg bit 0
-- note that in Stratix, there is an inverter to regout.
-- but in Stratix II, there is no inverter.
regout <= shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(20 downto 9) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(8) <= '1';
else
update_reg(8) <= '0';
end if;
-- PGM[] field
update_reg(7 downto 1) <= conv_std_logic_vector(sim_init_page_select, 7);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
--report " -> Field User Watchdog is set to %s", update_reg[8] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 24 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(25) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and
(operation_mode = "remote" or operation_mode = "active_serial_remote")) then
-- every bit in Update Reg gets updated
update_reg(20 downto 0) <= shift_reg(25 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[12:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[13] == 1) ? "Enableds" : (shift_reg[13] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[25:14];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
elsif (operation_mode = "remote") then
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
else
pgmout_update <= (others => 'X');
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1];
--report " -> Field User Watchdog is set to %s", (update_reg[8] == 1) ? "Enabled" : (update_reg[8] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
-------------------------------------------------------------------------------
--
-- Entity Name : arriagx_termination
--
-- Outputs : incrup and incrdn - output of voltage comparator
-- terminationcontrol - to I/O, cannot wired to PLD
-- terminationcontrolprobe - internal testing outputs only
--
-- Descriptions : the Atom represent On Chip Termination calibration block.
-- The block has no digital outputs that can be observed in PLD.
-- Therefore we do not have simulation model other than entity
-- declaration.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_termination is
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "arriagx_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END arriagx_termination;
ARCHITECTURE vital_armtermination of arriagx_termination is
begin
--------------------
-- INPUT PATH DELAYS
--------------------
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
end vital_armtermination;
---------------------------------------------------------------------
--
-- Entity Name : arriagx_routing_wire
--
-- Description : StratixIIGXLITE Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriagx_atom_pack.all;
ENTITY arriagx_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of arriagx_routing_wire : entity is TRUE;
end arriagx_routing_wire;
ARCHITECTURE behave of arriagx_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | e984555d8ed09c70a8d691cb4bd7e2ce | 0.494936 | 3.86012 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixii_components.vhd | 1 | 50,971 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
package stratixii_components is
--
-- stratixii_ram_block
--
COMPONENT stratixii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixii_jtag
--
COMPONENT stratixii_jtag
generic (
lpm_type : string := "stratixii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixii_crcblock
--
COMPONENT stratixii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixii_asmiblock
--
COMPONENT stratixii_asmiblock
generic (
lpm_type : string := "stratixii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- stratixii_lcell_ff
--
COMPONENT stratixii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- stratixii_lcell_comb
--
COMPONENT stratixii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixii_clkctrl
--
COMPONENT stratixii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- stratixii_io
--
COMPONENT stratixii_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- stratixii_pll
--
COMPONENT stratixii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixii_pll";
family_name : string := "StratixII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- stratixii_mac_mult
--
COMPONENT stratixii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixii_mac_out
--
COMPONENT stratixii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixii_lvds_transmitter
--
COMPONENT stratixii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- stratixii_lvds_receiver
--
COMPONENT stratixii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixii_dll
--
COMPONENT stratixii_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixii_rublock
--
COMPONENT stratixii_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratixii_termination
--
COMPONENT stratixii_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- stratixii_routing_wire
--
COMPONENT stratixii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end stratixii_components;
| gpl-3.0 | be03c1f9f32589d870959dab782b018d | 0.477134 | 4.28004 | false | false | false | false |
alvieboy/xtc-base | execute.vhd | 1 | 14,479 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity execute is
port (
clk: in std_logic;
rst: in std_logic;
mem_busy: in std_logic;
busy: out std_logic;
refetch: in std_logic;
wb_busy: in std_logic;
int: in std_logic;
intline: in std_logic_vector(7 downto 0);
nmi: in std_logic;
nmiack: out std_logic;
-- Input for previous stages
fdui: in fetchdata_output_type;
-- Output for next stages
euo: out execute_output_type;
-- Input from memory unit, for SPR update
mui: in memory_output_type;
-- Coprocessor interface
co: out copifo;
ci: in copifi;
-- Other data (usually from coprocessor)
trapbase: in std_logic_vector(31 downto 0);
trappc: in std_logic_vector(31 downto 0);
trapaddr: out std_logic_vector(31 downto 0);
istrap: out std_logic;
-- Debugging
dbgo: out execute_debug_type
);
end entity execute;
architecture behave of execute is
signal alu_a_a, alu_a_b: std_logic_vector(31 downto 0);
signal alu_a_r, alu_a_y: unsigned(31 downto 0);
signal alu1_ci, alu1_co, alu1_busy, alu1_ovf, alu1_sign, alu1_zero: std_logic;
signal er: execute_regs_type;
signal dbg_do_interrupt: boolean;
signal enable_alu: std_logic;
signal lhs,rhs: std_logic_vector(31 downto 0);
signal cop_busy, cop_en: std_logic;
signal do_trap: std_logic;
signal mult_valid: std_logic;
signal dbg_passes_condition: std_logic;
begin
lhs<=fdui.rr1 when fdui.alufwa='0' else std_logic_vector(er.alur);
rhs<=fdui.rr2 when fdui.alufwb='0' else std_logic_vector(er.alur);
euo.r <= er;
alu_a_a <= lhs;
alu_a_b <= rhs when fdui.r.drq.alu_source = alu_source_reg else std_logic_vector(fdui.r.drq.imreg);
dbgo.lhs <= unsigned(alu_a_a);
dbgo.rhs <= unsigned(alu_a_b);
dbgo.lhs <= unsigned(alu_a_a);
dbgo.rhs <= unsigned(alu_a_b);
dbgo.dbgen <= er.psr(2);
myalu: entity work.alu
port map (
clk => clk,
rst => rst,
a => unsigned(alu_a_a),
b => unsigned(alu_a_b),
o => alu_a_r,
y => alu_a_y,
en => enable_alu, -- Check...
op => fdui.r.drq.alu_op,
ci => er.psr(30),
cen => fdui.r.drq.use_carry,
busy => alu1_busy,
valid => mult_valid,
co => alu1_co,
zero => alu1_zero,
ovf => alu1_ovf,
sign => alu1_sign
);
co.o.en <= cop_en;
cop_busy<='1' when cop_en='1' and ci.i.valid/='1' else '0';
process(clk,fdui,er,rst,alu_a_r,
alu1_co, alu1_sign,alu1_zero,alu1_ovf,
mem_busy,wb_busy,int,cop_busy,lhs,alu1_busy,ci,rhs,mult_valid)
variable ew: execute_regs_type;
variable busy_int: std_logic;
constant reg_zero: unsigned(31 downto 0) := (others => '0');
variable im8_fill: unsigned(31 downto 0);
variable invalid_instr: boolean;
variable spr: unsigned(31 downto 0);
variable can_interrupt: boolean;
variable do_interrupt: boolean;
variable passes_condition: std_logic;
variable reg_add_immed: unsigned(31 downto 0);
alias psr_carry: std_logic is er.psr(30);
alias psr_sign: std_logic is er.psr(31);
alias psr_ovf: std_logic is er.psr(28);
alias psr_zero: std_logic is er.psr(29);
alias psr_svc: std_logic is er.psr(0);
alias psr_ien: std_logic is er.psr(1);
alias psr_dbg: std_logic is er.psr(2);
-- alias psr_fad: std_logic_vector(3 downto 0) is er.psr(7 downto 4);
variable trap: boolean;
variable do_fault: boolean;
variable fault_address: unsigned(3 downto 0);
begin
ew := er;
ew.valid := fdui.valid;
-- Note: with delay slots, we must only reset JUMP when
-- we finished executing the slot.
if fdui.valid='1' then
ew.jump := '0';
ew.jumpaddr := (others => 'X');
end if;
can_interrupt := true;
do_interrupt := false;
do_fault := false;
fault_address:=(others => 'X');
trap:=false;
nmiack <= '0';
if wb_busy='0' then
ew.regwe := '0';
end if;
enable_alu <= '0';
invalid_instr := false;
reg_add_immed := unsigned(lhs) + fdui.r.drq.imreg;
-- Conditional execution
case fdui.r.drq.condition_clause is
when CONDITION_UNCONDITIONAL => passes_condition := '1';
when CONDITION_NE => passes_condition := not er.psr(29);
when CONDITION_E => passes_condition := er.psr(29);
when CONDITION_GE => passes_condition := not er.psr(31);
when CONDITION_G => passes_condition := not er.psr(31) and not er.psr(29);
when CONDITION_LE => passes_condition := er.psr(31) or er.psr(29);
when CONDITION_L => passes_condition := er.psr(31);
when CONDITION_UGE => passes_condition := not er.psr(30);
when CONDITION_UG => passes_condition := not er.psr(30) and not er.psr(29);
when CONDITION_ULE => passes_condition := er.psr(30) or er.psr(29);
when CONDITION_UL => passes_condition := er.psr(30);
when others => passes_condition := 'X';
end case;
if mem_busy='1' or cop_busy='1' then
busy_int := '1';
else
busy_int := wb_busy;
end if;
if busy_int='1' then
--ew.jump:='0';
end if;
-- synthesis translate_off
if DEBUG_OPCODES then
if rising_edge(clk) then
if fdui.valid='1' and busy_int='0' then
if fdui.r.drq.dual then
report hstr(std_logic_vector(fdui.r.drq.pc)) & " " & hstr(fdui.r.drq.opcode)&hstr(fdui.r.drq.opcode_low);
else
report hstr(std_logic_vector(fdui.r.drq.pc)) & " " & hstr(fdui.r.drq.opcode);
end if;
elsif fdui.valid='0' then
report hstr(std_logic_vector(fdui.r.drq.pc)) & " <NOT VALID>" ;
elsif busy_int='1' then
report hstr(std_logic_vector(fdui.r.drq.pc)) & " <BUSY>" ;
--elsif er.intjmp then
-- report hstr(std_logic_vector(fdui.r.drq.pc)) & " <JUMP>" ;
end if;
end if;
end if;
-- synthesis translate_on
euo.reg_source <= fdui.r.drq.reg_source;
euo.dreg <= fdui.r.drq.dreg;
dbgo.valid <= false;
dbgo.executed <= false;
euo.executed <= false;
dbgo.dual <= fdui.r.drq.dual;
dbgo.opcode1 <= fdui.r.drq.opcode_low;
dbgo.opcode2 <= fdui.r.drq.opcode;
dbgo.pc <= fdui.r.drq.pc;
dbgo.hold <= fdui.r.hold;
dbgo.multvalid <= mult_valid;
if fdui.valid='1' and passes_condition='1' then
enable_alu <= fdui.r.drq.enable_alu;
end if;
cop_en <= '0';
co.o.wr <= 'X';
co.o.reg <= fdui.r.drq.cop_reg;
co.id <= fdui.r.drq.cop_id;
co.o.data <= lhs;
-- Note: if this happens in a delay slot.... the result is
-- undefined.
if fdui.valid='1' and (fdui.r.drq.priv='1' and er.psr(0)='0') then
trap:=true;
do_fault:=true;
can_interrupt:=false;
fault_address:=x"1";
end if;
if ci.i.fault='1' then
trap:=true;
do_fault:=true;
can_interrupt:=false;
fault_address:=x"1";
end if;
-- Traps and interrupts.
if can_interrupt and fdui.valid='1' and fdui.r.drq.decoded=O_SWI then
do_interrupt := true;
do_fault:=true;
fault_address:=x"2";
end if;
if can_interrupt and int='1' and er.psr(1)='1' and fdui.valid='1' and er.jump='0' then
do_interrupt := true;
do_fault:=true;
fault_address:=x"0";
end if;
if mui.fault='1' then
do_fault:=true;
fault_address:=x"3";
end if;
if nmi='1' and er.innmi='0' then --and er.jump='0' and fdui.valid='1' then
do_fault:=true;
fault_address:=x"4";
ew.innmi :='1';
nmiack<='1';
end if;
if fdui.valid='1' and busy_int='0' then
dbgo.valid <= true;
if passes_condition='1' then
dbgo.executed <= true;
euo.executed <= true;
end if;
end if;
do_trap<='0';
ew.trapq:='0';
dbgo.trap<='0';
if do_fault then
passes_condition := '0';
do_trap<='1';
ew.trapq := '1';
dbgo.trap <= '1';
dbgo.valid <= false;
end if;
if fdui.valid='1' and passes_condition='1' then
cop_en <= fdui.r.drq.cop_en;
co.o.wr <= fdui.r.drq.cop_wr;
end if;
if fdui.valid='1' and passes_condition='0' and fdui.r.drq.blocks='1' then
euo.clrreg <= '1';
else
euo.clrreg <= '0';
end if;
if fdui.valid='1' and busy_int='0' then
if passes_condition='1' then
ew.alur := alu_a_r(31 downto 0);
ew.wb_is_data_address := fdui.r.drq.wb_is_data_address;
if fdui.r.drq.modify_flags then
ew.psr(30) := alu1_co;
ew.psr(31) := alu1_sign;
ew.psr(28) := alu1_ovf;
ew.psr(29) := alu1_zero;
end if;
ew.reg_source := fdui.r.drq.reg_source;
ew.regwe := fdui.r.drq.regwe;
ew.dreg := fdui.r.drq.dreg;
ew.npc := fdui.r.drq.fpc;
if fdui.r.drq.is_jump then
ew.jump:='1';
else
ew.jump:='0';
end if;
case fdui.r.drq.jump is
--when JUMP_RI_PCREL => ew.jumpaddr := reg_add_immed + fdui.r.drq.npc(31 downto 0);
when JUMP_I_PCREL => ew.jumpaddr := fdui.r.drq.imreg + fdui.r.drq.npc(31 downto 0);
when JUMP_RI_ABS => ew.jumpaddr := reg_add_immed;
when others => ew.jumpaddr := (others => 'X');
end case;
-- Never jump if busy
--if busy_int='1' then
-- ew.jump := '0';
--end if;
end if; -- passes condition
ew.jumppriv := er.psr(0);
if fdui.r.drq.sprwe='1' and fdui.r.drq.memory_access='0' then
case fdui.r.drq.sra2(2 downto 0) is
when "000" => -- Y
ew.y := unsigned(lhs);
when "001" => -- PSR
ew.psr(7 downto 0) := unsigned(lhs(7 downto 0));
ew.psr(31 downto 28) := unsigned(lhs(31 downto 28));
when "010" => -- SPSR
ew.spsr(7 downto 0) := unsigned(lhs(7 downto 0));
ew.spsr(31 downto 28) := unsigned(lhs(31 downto 28));
--when "011" => -- TTR
-- ew.trapvector := unsigned(lhs);
-- when "100" => -- TPC
-- ew.trappc := unsigned(lhs);
--when "101" => -- SR
when "011" => -- SR
ew.scratch := unsigned(lhs);
when others =>
end case;
end if;
if ew.jump='1' and fdui.r.drq.except_return then
-- Restore PSR, BR
ew.psr(7 downto 0) := er.spsr(7 downto 0);
ew.psr(31 downto 28) := er.spsr(31 downto 28);
ew.jumpaddr := unsigned(trappc);
ew.jumppriv := er.spsr(0);
ew.innmi:='0';
end if;
else
-- Instruction is not being processed.
enable_alu<='0';
end if;
trapaddr <= std_logic_vector(fdui.r.drq.tpc);
istrap<='0';
if do_fault then
--ew.jump:='1';
ew.jumpaddr(31 downto 2):= unsigned(trapbase(31 downto 2));
-- ew.jumpaddr(7 downto 4) := fault_address;
ew.jumpaddr(1 downto 0) := "00";
ew.spsr := ew.psr; -- Save PSR
ew.psr(2) := '0'; -- Debug enabled.
ew.psr(1) := '0'; -- Interrupt enable
ew.psr(0) := '1'; -- Supervisor mode
ew.psr(7 downto 4) := fault_address;
istrap<='1';
ew.jumppriv := er.psr(0);
--ew.psr(1) := fdui.r.drq.imflag;
end if;
busy <= busy_int or (fdui.r.hold and not mult_valid);
-- Fast writeback
euo.alur <= alu_a_r(31 downto 0);
-- SPRVAL...
case fdui.r.drq.sra2(2 downto 0) is
when "000" => ew.sprval := er.y;
when "001" =>
ew.sprval(7 downto 0) := er.psr(7 downto 0);
ew.sprval(27 downto 8) := (others => '0');
ew.sprval(31 downto 28) := er.psr(31 downto 28);
when "010" =>
ew.sprval(7 downto 0) := er.spsr(7 downto 0);
ew.sprval(27 downto 8) := (others => '0');
ew.sprval(31 downto 28) := er.spsr(31 downto 28);
--when "011" => ew.sprval := er.trapvector;
-- when "100" => ew.sprval := er.trappc;
--when "101" => ew.sprval := er.scratch;
when "011" => ew.sprval := er.scratch;
when others => ew.sprval := (others => 'X');
end case;
euo.sprval <= ew.sprval;
euo.imreg <= fdui.r.drq.imreg;
euo.sr <= ew.sr;
euo.cop <= ci.i.data;
-- Memory lines
euo.sprwe <= fdui.r.drq.sprwe;
euo.mwreg <= fdui.r.drq.sra2;
euo.sr <= fdui.r.drq.sr;
euo.macc <= fdui.r.drq.macc;
euo.npc <= fdui.r.drq.fpc; -- NOTE: This is due to delay slot
euo.data_write <= rhs; -- Memory always go through Alu2
euo.data_address <= std_logic_vector(reg_add_immed);
euo.data_access <= fdui.r.drq.memory_access;
euo.data_writeenable <= fdui.r.drq.memory_write;
if fdui.valid='0' or passes_condition='0' then
euo.data_access <= '0';
euo.sprwe <= '0';--fdui.r.drq.sprwe;
end if;
if mult_valid='1' then
ew.y := alu_a_y;
end if;
if rst='1' then
ew.psr(0) := '1'; -- Supervisor
ew.psr(31 downto 1) := (others =>'0'); -- Interrupts disabled
--ew.trapvector := RESETADDRESS;--others => '0');
-- Debug.
--ew.trappc := fdui.r.drq.npc;
ew.jump := '0';
ew.jumppriv := '1';
ew.regwe := '0';
ew.valid := '0';
ew.trapq := '0';
ew.innmi := '0';
ew.y := (others => 'X');
ew.sprval := (others => 'X');
ew.npc := (others => 'X');
ew.scratch := (others => 'X');
ew.alur := (others => 'X');
ew.jumpaddr:= (others => 'X');
--euo.data_access <= '0';
end if;
if rising_edge(clk) then
if invalid_instr then
report "Invalid instruction" severity failure;
end if;
if trap then
report "TRAP";
end if;
er <= ew;
end if;
-- synthesis translate_off
dbg_do_interrupt <= do_interrupt;
dbg_passes_condition <= passes_condition;
-- synthesis translate_on
end process;
euo.jump <= (er.jump and fdui.valid) or (er.trapq);
euo.jumppriv <= er.jumppriv;
euo.trap <= do_trap;
euo.clrhold <= mult_valid or (er.jump and fdui.valid) or (er.trapq) ;
end behave;
| bsd-3-clause | a028c46603d69196cf63061ebab32758 | 0.549693 | 2.995242 | false | false | false | false |
alvieboy/xtc-base | regbank_5p.vhd | 1 | 3,035 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
entity regbank_5p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw_wr: in std_logic_vector(31 downto 0);
rbw_we: in std_logic;
rbw_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end entity regbank_5p;
architecture behave of regbank_5p is
component regbank_2p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
begin
rba: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb1_addr,
rb1_en => rb1_en,
rb1_rd => rb1_rd,
rb2_addr => rbw_addr,
rb2_wr => rbw_wr,
rb2_we => rbw_we,
rb2_en => rbw_en,
dbg_addr => dbg_addr,
dbg_do => dbg_do
);
rbb: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb2_addr,
rb1_en => rb2_en,
rb1_rd => rb2_rd,
rb2_addr => rbw_addr,
rb2_wr => rbw_wr,
rb2_we => rbw_we,
rb2_en => rbw_en
);
rbc: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb3_addr,
rb1_en => rb3_en,
rb1_rd => rb3_rd,
rb2_addr => rbw_addr,
rb2_wr => rbw_wr,
rb2_we => rbw_we,
rb2_en => rbw_en
);
rbd: regbank_2p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb4_addr,
rb1_en => rb4_en,
rb1_rd => rb4_rd,
rb2_addr => rbw_addr,
rb2_wr => rbw_wr,
rb2_we => rbw_we,
rb2_en => rbw_en
);
end behave;
| bsd-3-clause | 8518439549c07f47dfbf33ccf7b9e7d8 | 0.558814 | 2.756585 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_prod.vhd | 1 | 10,212 | -------------------------------------------------------------------------------
--
-- Testbench for the production test as proposed by
-- "Testing of COP400 Familiy Devices"
-- National Semiconductor
-- COP Note 7
-- April 1991
--
-- $Id: tb_prod.vhd,v 1.1 2006-06-10 18:50:51 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_prod is
end tb_prod;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.all;
use work.t400_opt_pack.all;
architecture behav of tb_prod is
-- 5 MHz clock
constant period_c : time := 200 ns;
signal ck_s : std_logic;
signal en_ck_s : std_logic := '0';
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s,
d_s : std_logic_vector(3 downto 0);
signal exp_d_s : std_logic_vector(3 downto 0) := "0000";
signal io_g_s,
g_s : std_logic_vector(3 downto 0);
signal exp_g_s : std_logic_vector(3 downto 0) := "0000";
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
signal tb_io_l_s : std_logic_vector(7 downto 0);
signal disable_s : boolean := true;
signal pass_s : std_logic := 'L';
signal fail_s : std_logic := 'L';
signal vdd4_s : std_logic_vector(3 downto 0);
begin
vdd4_s <= (others => '1');
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c
)
port map (
ck_i => ck_s,
ck_en_i => en_ck_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'L');
io_g_s <= (others => 'L');
io_in_s <= (others => 'H');
io_in_s <= io_g_s; -- feedthrough for production test
d_s <= to_X01(io_d_s);
g_s <= to_X01(io_g_s);
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => tb_io_l_s,
io_d_i => vdd4_s,
io_g_i => vdd4_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Generates the en_ck_s signal from the high frequency clock.
--
ck_div: process (ck_s)
variable cnt_v : natural := 0;
begin
if ck_s'event and ck_s = '1' then
en_ck_s <= '0';
if cnt_v = 25 then
cnt_v := 0;
en_ck_s <= '1';
else
cnt_v := cnt_v + 1;
end if;
end if;
end process ck_div;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process exp
--
-- Purpose:
-- Sets the expected values for D and G ports.
--
exp: process
procedure w_p(signal sig : in std_logic_vector) is
begin
wait until sig'event;
end;
procedure exp_d_p(exp : in natural) is
begin
w_p(d_s);
exp_d_s <= std_logic_vector(to_unsigned(exp, 4));
end;
procedure exp_g_p(exp : in natural) is
begin
w_p(g_s);
exp_g_s <= std_logic_vector(to_unsigned(exp, 4));
end;
begin
-- default settings
pass_s <= 'L';
exp_d_s <= (others => '0');
exp_g_s <= (others => '0');
wait for 1 us;
disable_s <= false;
-- G(0 > 9)
exp_g_p(9);
-- G(9 > 6)
exp_g_p(6);
-- D(0 > 13)
exp_d_p(13);
-- D(13 > 3)
exp_d_p(3);
-- D(3 > 2)
exp_d_p(2);
-- D(2 > 3)
exp_d_p(3);
-- G(6 > 7)
exp_g_p(7);
-- G(7 > 8)
exp_g_p(8);
-- G(8 > 9)
exp_g_p(9);
-- G(9 > 11)
exp_g_p(11);
-- G(11 > 7)
exp_g_p(7);
-- G(7 > 1)
exp_g_p(1);
-- D(2 > 0)
exp_d_p(0);
-- G(1 > 5)
exp_g_p(5);
-- D(0 > 15)
exp_d_p(15);
-- G(5 > 9)
exp_g_p(9);
-- D(15 > 0)
exp_d_p(0);
-- G(9 > 10)
exp_g_p(10);
-- G(10 > 9)
exp_g_p(9);
-- G(9 > 1)
exp_g_p(1);
-- G(1 > 4)
exp_g_p(4);
-- G(4 > 14)
exp_g_p(14);
-- G(14 > 3)
exp_g_p(3);
-- G(3 > 14)
exp_g_p(14);
-- G(14 > 7)
exp_g_p(7);
-- G(7 > 9)
exp_g_p(9);
-- G(9 > 10)
exp_g_p(10);
-- G (10 > 7)
exp_g_p(7);
-- G(7 > 10)
exp_g_p(10);
-- G(10 > 7)
exp_g_p(7);
-- G(7 > 10)
exp_g_p(10);
-- G(10 > 0)
exp_g_p(0);
-- G(0 > 10)
exp_g_p(10);
-- G(10 > 7)
exp_g_p(7);
-- G(7 > 10)
exp_g_p(10);
-- D was at 15 before
-- -- D(15 > 0)
-- exp_d_p(0);
-- G(10 > 1)
exp_g_p(1);
-- G(1 > 0)
exp_g_p(0);
-- D(0 > 11)
exp_d_p(11);
-- G(10 > 9)
exp_g_p(9);
---------------------------------------------------------------------------
-- RAM tests
--
for reg in 0 to 3 loop
exp_g_p(7);
exp_g_p(14);
exp_g_p(5);
exp_g_p(12);
exp_g_p(3);
exp_g_p(10);
exp_g_p(1);
exp_g_p(8);
exp_g_p(15);
exp_g_p(6);
exp_g_p(13);
exp_g_p(4);
exp_g_p(11);
exp_g_p(2);
exp_g_p(9);
exp_g_p(0);
end loop;
wait for 1 us;
if fail_s /= '1' then
pass_s <= '1';
end if;
wait;
end process exp;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process exp_d
--
-- Purpose:
-- Checks the expected value for the D port.
--
exp_d: process (ck_s)
begin
if disable_s then
fail_s <= 'L';
elsif ck_s'event and ck_s = '0' then
if d_s /= exp_d_s then
fail_s <= '1';
end if;
end if;
end process exp_d;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process exp_g
--
-- Purpose:
-- Checks the expected value for the G port.
--
exp_g: process (ck_s)
begin
if disable_s then
fail_s <= 'L';
elsif ck_s'event and ck_s = '0' then
if g_s /= exp_g_s then
fail_s <= '1';
end if;
end if;
end process exp_g;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process pass_fail
--
-- Purpose:
-- Collects the pass/fail signal and generates the respective sequence
-- on tb_io_l_s.
--
pass_fail: process
procedure tb_pass_fail(pass : in boolean) is
begin
tb_io_l_s <= "00000000";
wait for 1 us;
tb_io_l_s <= "10100000";
wait for 1 us;
tb_io_l_s <= "01010000";
wait for 1 us;
if pass then
tb_io_l_s <= "00000000";
else
tb_io_l_s <= "11110000";
end if;
wait for 1 us;
end;
begin
tb_io_l_s <= (others => '0');
loop
wait until pass_s'event or fail_s'event;
if fail_s = '1' then
tb_pass_fail(pass => false);
elsif pass_s = '1' then
tb_pass_fail(pass => true);
end if;
end loop;
end process pass_fail;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | ad9117d09a71f831290b34d9caaeac92 | 0.444085 | 3.285714 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_io_l.vhd | 1 | 8,016 | -------------------------------------------------------------------------------
--
-- The L port controller.
--
-- $Id: t400_io_l.vhd,v 1.4 2006-06-05 20:33:24 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_l is
generic (
opt_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_l_op_t;
en2_i : in std_logic;
m_i : in dw_t;
a_i : in dw_t;
pm_data_i : in byte_t;
q_o : out byte_t;
-- Microbus Interface -----------------------------------------------------
cs_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port L Interface -------------------------------------------------------
io_l_i : in byte_t;
io_l_o : out byte_t;
io_l_en_o : out byte_t
);
end t400_io_l;
use work.t400_io_pack.all;
architecture rtl of t400_io_l is
signal q_q : byte_t;
signal en2_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process q_reg
--
-- Purpose:
-- Implements the Q register.
--
q_reg: process (ck_i, por_i)
begin
if por_i then
q_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
case op_i is
-- Load Q from accumulator and data memory --------------------------
when IOL_LOAD_AM =>
q_q(7 downto 4) <= a_i;
q_q(3 downto 0) <= m_i;
-- Load Q from program memory ---------------------------------------
when IOL_LOAD_PM =>
q_q <= pm_data_i;
when others =>
null;
end case;
end if;
-- Microbus functionality
if opt_microbus_g = t400_opt_microbus_c and
cs_n_i = '0' and wr_n_i = '0' then
q_q <= to_X01(io_l_i);
end if;
end if;
end process q_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Multiplexer providing read data to the system.
-----------------------------------------------------------------------------
q_o <= to_X01(io_l_i)
when op_i = IOL_OUTPUT_L else
q_q;
-----------------------------------------------------------------------------
-- Dedicated output enable when in Microbus mode
-----------------------------------------------------------------------------
en2_s <= cs_n_i nor rd_n_i
when opt_microbus_g = t400_opt_microbus_c else
en2_i;
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (en2_s,
q_q)
begin
-- bit 7
io_l_o(7) <= io_out_f(dat => q_q(7),
opt => opt_out_type_7_g);
io_l_en_o(7) <= io_en_f (en => en2_s, dat => q_q(7),
opt => opt_out_type_7_g);
-- bit 6
io_l_o(6) <= io_out_f(dat => q_q(6),
opt => opt_out_type_6_g);
io_l_en_o(6) <= io_en_f (en => en2_s, dat => q_q(6),
opt => opt_out_type_6_g);
-- bit 5
io_l_o(5) <= io_out_f(dat => q_q(5),
opt => opt_out_type_5_g);
io_l_en_o(5) <= io_en_f (en => en2_s, dat => q_q(5),
opt => opt_out_type_5_g);
-- bit 4
io_l_o(4) <= io_out_f(dat => q_q(4),
opt => opt_out_type_4_g);
io_l_en_o(4) <= io_en_f (en => en2_s, dat => q_q(4),
opt => opt_out_type_4_g);
-- bit 3
io_l_o(3) <= io_out_f(dat => q_q(3),
opt => opt_out_type_3_g);
io_l_en_o(3) <= io_en_f (en => en2_s, dat => q_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_l_o(2) <= io_out_f(dat => q_q(2),
opt => opt_out_type_2_g);
io_l_en_o(2) <= io_en_f (en => en2_s, dat => q_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_l_o(1) <= io_out_f(dat => q_q(1),
opt => opt_out_type_1_g);
io_l_en_o(1) <= io_en_f (en => en2_s, dat => q_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_l_o(0) <= io_out_f(dat => q_q(0),
opt => opt_out_type_0_g);
io_l_en_o(0) <= io_en_f (en => en2_s, dat => q_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/06/05 14:21:21 arniml
-- latch io_l_i upon input enable trigger
--
-- Revision 1.2 2006/05/23 01:14:28 arniml
-- use to_X01 for primary input bus
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 9cd584744c8f27eafa3d501c5c1d501f | 0.46507 | 3.494333 | false | false | false | false |
alvieboy/xtc-base | wbarb2_1.vhd | 1 | 2,618 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_syscon: in wb_syscon_type;
-- Master 0 signals
m0_wbi: in wb_mosi_type;
m0_wbo: out wb_miso_type;
-- Master 1 signals
m1_wbi: in wb_mosi_type;
m1_wbo: out wb_miso_type;
-- Slave signals
s0_wbi: in wb_miso_type;
s0_wbo: out wb_mosi_type
);
end entity wbarb2_1;
architecture behave of wbarb2_1 is
signal current_master: std_logic;
signal next_master: std_logic;
begin
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
current_master <= '0';
else
current_master <= next_master;
end if;
end if;
end process;
process(current_master, m0_wbi.cyc, m1_wbi.cyc)
begin
next_master <= current_master;
case current_master is
when '0' =>
if m0_wbi.cyc='0' then
if m1_wbi.cyc='1' then
next_master <= '1';
end if;
end if;
when '1' =>
if m1_wbi.cyc='0' then
if m0_wbi.cyc='1' then
next_master <= '0';
end if;
end if;
when others =>
end case;
end process;
-- Muxers for slave
process(current_master, m0_wbi, m1_wbi)
begin
case current_master is
when '0' =>
s0_wbo.dat <= m0_wbi.dat;
s0_wbo.adr <= m0_wbi.adr;
s0_wbo.sel <= m0_wbi.sel;
s0_wbo.we <= m0_wbi.we;
s0_wbo.cyc <= m0_wbi.cyc;
s0_wbo.stb <= m0_wbi.stb;
s0_wbo.tag <= m0_wbi.tag;
s0_wbo.cti <= m0_wbi.cti;
s0_wbo.bte <= m0_wbi.bte;
when '1' =>
s0_wbo.dat <= m1_wbi.dat;
s0_wbo.adr <= m1_wbi.adr;
s0_wbo.sel <= m1_wbi.sel;
s0_wbo.we <= m1_wbi.we;
s0_wbo.cyc <= m1_wbi.cyc;
s0_wbo.stb <= m1_wbi.stb;
s0_wbo.tag <= m1_wbi.tag;
s0_wbo.cti <= m1_wbi.cti;
s0_wbo.bte <= m1_wbi.bte;
when others =>
null;
end case;
end process;
-- Muxers/sel for masters
m0_wbo.dat <= s0_wbi.dat;
m1_wbo.dat <= s0_wbi.dat;
m0_wbo.tag <= s0_wbi.tag;
m1_wbo.tag <= s0_wbi.tag;
-- Ack
m0_wbo.ack <= s0_wbi.ack when current_master='0' else '0';
m1_wbo.ack <= s0_wbi.ack when current_master='1' else '0';
m0_wbo.err <= s0_wbi.err when current_master='0' else '0';
m1_wbo.err <= s0_wbi.err when current_master='1' else '0';
m0_wbo.stall <= s0_wbi.stall when current_master='0' else '1';
m1_wbo.stall <= s0_wbi.stall when current_master='1' else '1';
end behave;
| bsd-3-clause | be66e21606f4d2b20e72ae7ec3bf4c1c | 0.582124 | 2.576772 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/maxii_components.vhd | 1 | 9,572 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxii_atom_pack.all;
package maxii_components is
--
-- maxii_jtag
--
COMPONENT maxii_jtag
generic (
lpm_type : string := "maxii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- maxii_lcell
--
COMPONENT maxii_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "maxii_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- maxii_ufm
--
COMPONENT maxii_ufm
generic (
address_width : integer := 9;
init_file : string := "none";
lpm_type : string := "maxii_ufm";
mem1 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem2 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem3 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem4 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem5 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem6 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem7 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem8 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem9 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem10 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem11 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem12 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem13 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem14 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem15 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem16 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
osc_sim_setting : integer := 180000; -- default osc frequency to 5.56MHz
program_time : integer := 1600000; -- default program_time is 1600ns
erase_time : integer := 500000000; -- default erase time is 500us
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_program_busy_posedge: VitalDelayType01 := DefPropDelay01;
tpd_erase_busy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_drclk_drdout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_oscena_osc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sbdin_sbdout : VitalDelayType01 := DefPropDelay01;
tsetup_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_program_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_erase_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_program_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_erase_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_program_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_erase_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_program_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_erase_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tipd_program : VitalDelayType01 := DefPropDelay01;
tipd_erase : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01;
tipd_arclk : VitalDelayType01 := DefPropDelay01;
tipd_arshft : VitalDelayType01 := DefPropDelay01;
tipd_ardin : VitalDelayType01 := DefPropDelay01;
tipd_drclk : VitalDelayType01 := DefPropDelay01;
tipd_drshft : VitalDelayType01 := DefPropDelay01;
tipd_drdin : VitalDelayType01 := DefPropDelay01;
tipd_sbdin : VitalDelayType01 := DefPropDelay01
);
port (
program : in std_logic := '0';
erase : in std_logic := '0';
oscena : in std_logic;
arclk : in std_logic;
arshft : in std_logic;
ardin : in std_logic;
drclk : in std_logic;
drshft : in std_logic;
drdin : in std_logic := '0';
sbdin : in std_logic := '0';
devclrn : in std_logic := '1'; -- simulation only port
devpor : in std_logic := '1'; -- simulation only port
ctrl_bgpbusy : in std_logic := '0'; -- simulation only port, to control
busy : out std_logic;
osc : out std_logic := 'X';
drdout : out std_logic;
sbdout : out std_logic;
bgpbusy : out std_logic);
END COMPONENT;
--
-- maxii_io
--
COMPONENT maxii_io
generic(
lpm_type : STRING := "maxii_io";
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01
);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
padio : inout STD_LOGIC;
combout : out STD_LOGIC
);
END COMPONENT;
--
-- maxii_routing_wire
--
COMPONENT maxii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end maxii_components;
| gpl-3.0 | 235bdb4a0242ddb4874752366f02f762 | 0.567906 | 3.931006 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiigx_components.vhd | 1 | 51,079 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiigx_atom_pack.all;
package stratixiigx_components is
--
-- stratixiigx_ram_block
--
COMPONENT stratixiigx_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiigx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiigx_jtag
--
COMPONENT stratixiigx_jtag
generic (
lpm_type : string := "stratixiigx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixiigx_crcblock
--
COMPONENT stratixiigx_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixiigx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiigx_asmiblock
--
COMPONENT stratixiigx_asmiblock
generic (
lpm_type : string := "stratixiigx_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- stratixiigx_lcell_ff
--
COMPONENT stratixiigx_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixiigx_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- stratixiigx_lcell_comb
--
COMPONENT stratixiigx_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixiigx_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixiigx_clkctrl
--
COMPONENT stratixiigx_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiigx_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiigx_io
--
COMPONENT stratixiigx_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixiigx_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- stratixiigx_pll
--
COMPONENT stratixiigx_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiigx_pll";
family_name : string := "StratixIIGX";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- stratixiigx_mac_mult
--
COMPONENT stratixiigx_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixiigx_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiigx_mac_out
--
COMPONENT stratixiigx_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixiigx_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiigx_lvds_transmitter
--
COMPONENT stratixiigx_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiigx_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- stratixiigx_lvds_receiver
--
COMPONENT stratixiigx_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixiigx_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiigx_dll
--
COMPONENT stratixiigx_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixiigx_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiigx_rublock
--
COMPONENT stratixiigx_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiigx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratixiigx_termination
--
COMPONENT stratixiigx_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixiigx_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiigx_routing_wire
--
COMPONENT stratixiigx_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end stratixiigx_components;
| gpl-3.0 | 2a6d3c7f7e04b7e14f93a79af819f178 | 0.47824 | 4.250915 | false | false | false | false |
shvorin/pcie-emu | hdllib/emu/emu_top256.vhd | 1 | 5,188 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
-- Toplevel module with empty interface used for emulation via GHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
use work.util.all;
use work.ast256.all;
entity emu_top256 is
end emu_top256;
architecture emu_top256 of emu_top256 is
constant period : time := 1 ns;
signal clk, reset : std_logic;
signal ast_rx, ast_tx : ast_t;
signal ast_tx_bp : ast_bp_t;
signal rx_st_bardec : std_logic_vector(7 downto 0);
signal ast_tx_bp_1, ast_tx_bp_2 : ast_bp_t;
-- data representation for foreing calls
type foreign_tlp128_data_t is array (integer range 0 to 3) of integer;
type foreign_half_ast is record
data : foreign_tlp128_data_t;
sop, eop, empty : std_logic;
end record;
type foreign_half_ast_array is array (half_idx) of foreign_half_ast;
type foreign_ast is record
half : foreign_half_ast_array;
valid : std_logic;
end record;
function wrap(data : qqword) return foreign_tlp128_data_t is
variable result : foreign_tlp128_data_t;
begin
for i in result'range loop
result(i) := conv_integer(data(32*(i+1) - 1 downto 32*i));
end loop;
return result;
end;
function unwrap(a : foreign_tlp128_data_t) return qqword is
variable result : qqword;
begin
for i in a'range loop
result(32*(i+1) - 1 downto 32*i) := conv_std_logic_vector(a(i), 32);
end loop;
return result;
end;
function wrap(a : ast_t) return foreign_ast is
function wrap(h : ast256half_t) return foreign_half_ast is
begin
return (data => wrap(h.data),
sop => h.sop,
eop => h.eop,
empty => h.empty);
end;
begin
return (half => (wrap(a.half(lo)), wrap(a.half(hi))),
valid => a.valid);
end;
function unwrap(f : foreign_ast) return ast_t is
function unwrap(h : foreign_half_ast) return ast256half_t is
begin
return (data => unwrap(h.data),
sop => h.sop,
eop => h.eop,
empty => h.empty);
end;
begin
return (half => (unwrap(f.half(lo)), unwrap(f.half(hi))),
valid => f.valid);
end;
-- About linking with foreign functions see
-- http://ghdl.free.fr/ghdl/Restrictions-on-foreign-declarations.html
procedure line256mp_up(foreign_ast_tx : foreign_ast)
is
begin
assert false severity failure;
end;
attribute foreign of line256mp_up : procedure is "VHPIDIRECT line256mp_up";
-- NB: corresponding C prototype is:
-- void line256mp_down(struct scalar_params *, ast256_t *, ast_bp_t *)
procedure line256mp_down(bar_num : out integer;
foreign_ast_rx : out foreign_ast;
ast_tx_bp : out ast_bp_t)
is
begin
assert false severity failure;
end;
attribute foreign of line256mp_down : procedure is "VHPIDIRECT line256mp_down";
begin
cg : entity work.clock_gen
generic map (period)
port map (clk, reset);
app : ast_io
port map (
clk => clk,
reset => reset,
ast_rx => ast_rx,
ast_tx => ast_tx,
ast_tx_bp => ast_tx_bp,
rx_st_bardec => rx_st_bardec);
data_down : process (clk, reset)
variable v_bar_num : integer;
variable foreign_ast_rx : foreign_ast;
variable v_ast_tx_bp : ast_bp_t;
function decode(bar_num : integer) return std_logic_vector is
variable result : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in result'range loop
if bar_num = i then
result(i) := '1';
end if;
end loop;
return result;
end;
begin
if reset = '1' then
ast_rx <= nothing;
ast_tx_bp <= (ready => '0');
elsif rising_edge(clk) then
line256mp_down(v_bar_num, foreign_ast_rx, v_ast_tx_bp);
ast_rx <= unwrap(foreign_ast_rx);
ast_tx_bp <= v_ast_tx_bp;
rx_st_bardec <= decode(v_bar_num);
end if;
end process;
data_up : process (clk)
begin
if rising_edge(clk) then
line256mp_up(wrap(ast_tx));
end if;
end process;
check_protocol : process(clk, reset)
begin
if reset = '1' then
ast_tx_bp_1.ready <= '1';
ast_tx_bp_2.ready <= '1';
elsif rising_edge(clk) then
ast_tx_bp_1 <= ast_tx_bp;
ast_tx_bp_2 <= ast_tx_bp_1;
assert (ast_tx_bp_2.ready or not ast_tx.valid) = '1' report "AST protocol violation";
end if;
end process;
end emu_top256;
| bsd-3-clause | cb519fdf43d178db305f115118738b97 | 0.54549 | 3.553425 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_clkgen.vhd | 1 | 5,136 | -------------------------------------------------------------------------------
--
-- The clock generation unit.
-- PHI1 clock and input/output clock enables are generated here.
--
-- $Id: t400_clkgen.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t400_clkgen is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Clock Interface --------------------------------------------------------
phi1_o : out std_logic;
out_en_o : out boolean;
in_en_o : out boolean;
icyc_en_o : out boolean
);
end t400_clkgen;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_clkgen is
subtype ck_div_t is unsigned(5 downto 0);
type ck_div_a_t is array(natural range t400_opt_ck_div_32_c
downto t400_opt_ck_div_4_c) of
ck_div_t;
-- reload values for the CK dividing counter
constant ck_div_a_c : ck_div_a_t := (
t400_opt_ck_div_32_c => to_unsigned(31, ck_div_t'length),
t400_opt_ck_div_16_c => to_unsigned(15, ck_div_t'length),
t400_opt_ck_div_8_c => to_unsigned( 7, ck_div_t'length),
t400_opt_ck_div_4_c => to_unsigned( 3, ck_div_t'length));
signal ck_div_cnt_q : ck_div_t;
signal ck_div_zero_s,
ck_div_half_s : boolean;
signal phi1_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Divide the incoming clock on ck_i and generate the derived clock
-- enable for the core.
--
ck_div: process (ck_i, por_i)
begin
if por_i then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
if ck_div_zero_s then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
else
ck_div_cnt_q <= ck_div_cnt_q - 1;
if ck_div_half_s then
phi1_q <= '1';
end if;
end if;
end if;
end if;
end process ck_div;
--
ck_div_zero_s <= ck_div_cnt_q = 0;
ck_div_half_s <= ck_div_cnt_q = SHIFT_RIGHT(ck_div_a_c(opt_ck_div_g), 1) + 1;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
phi1_o <= phi1_q;
-- Instruction cycle enable
icyc_en_o <= ck_en_i and ck_div_zero_s;
-- Output update enable
out_en_o <= ck_en_i and ck_div_zero_s;
-- Input sample enable
in_en_o <= ck_en_i and ck_div_half_s;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 996ea624ee13f228acdcc38c94d71962 | 0.54926 | 3.790406 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_flash/synthesis/internal_flash.vhd | 1 | 9,175 | -- internal_flash.vhd
-- Generated using ACDS version 17.1 590
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity internal_flash is
port (
clock : in std_logic := '0'; -- clk.clk
avmm_csr_addr : in std_logic := '0'; -- csr.address
avmm_csr_read : in std_logic := '0'; -- .read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_csr_write : in std_logic := '0'; -- .write
avmm_csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_addr : in std_logic_vector(11 downto 0) := (others => '0'); -- data.address
avmm_data_read : in std_logic := '0'; -- .read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avmm_data_write : in std_logic := '0'; -- .write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- .readdata
avmm_data_waitrequest : out std_logic; -- .waitrequest
avmm_data_readdatavalid : out std_logic; -- .readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
reset_n : in std_logic := '0' -- nreset.reset_n
);
end entity internal_flash;
architecture rtl of internal_flash is
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
begin
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "C:/Users/phil2/Dropbox/myelin-acorn-electron-hardware/bga_in_two_layers/10m04_cpu_socket/rom_one.hex",
INIT_FILENAME_SIM => "altera_onchip_flash.dat",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M04SCU169C8G",
DEVICE_ID => "04",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 0,
SECTOR2_END_ADDR => 0,
SECTOR3_START_ADDR => 0,
SECTOR3_END_ADDR => 0,
SECTOR4_START_ADDR => 0,
SECTOR4_END_ADDR => 0,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 4095,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 4095,
SECTOR1_MAP => 2,
SECTOR2_MAP => 0,
SECTOR3_MAP => 0,
SECTOR4_MAP => 0,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 4095,
ADDR_RANGE1_OFFSET => 4608,
ADDR_RANGE2_OFFSET => 0,
AVMM_DATA_ADDR_WIDTH => 12,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 30,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 4,
FLASH_RESET_CYCLE_MAX_INDEX => 29,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 139,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40600000,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35380,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => true,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "False"
)
port map (
clock => clock, -- clk.clk
reset_n => reset_n, -- nreset.reset_n
avmm_data_addr => avmm_data_addr, -- data.address
avmm_data_read => avmm_data_read, -- .read
avmm_data_writedata => avmm_data_writedata, -- .writedata
avmm_data_write => avmm_data_write, -- .write
avmm_data_readdata => avmm_data_readdata, -- .readdata
avmm_data_waitrequest => avmm_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => avmm_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => avmm_data_burstcount, -- .burstcount
avmm_csr_addr => avmm_csr_addr, -- csr.address
avmm_csr_read => avmm_csr_read, -- .read
avmm_csr_writedata => avmm_csr_writedata, -- .writedata
avmm_csr_write => avmm_csr_write, -- .write
avmm_csr_readdata => avmm_csr_readdata -- .readdata
);
end architecture rtl; -- of internal_flash
| apache-2.0 | 5e3cf21ca1dedb8d83c28ab340473890 | 0.444796 | 3.808634 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/phpe_chan.vhd | 1 | 7,033 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity PHPE_CHAN is
port (
RESET: in std_logic;
CLK100: in std_logic;
WB_CLK: in std_logic;
TRAMS: in std_logic;
AREA: in std_logic;
pe_scan_cnt_top: in std_logic;
pe_scan_ovs_top: in std_logic;
pe_scan_ovs: in std_logic;
pe_trars_cnt_bot: in std_logic;
pe_disch_int: in std_logic;
pe_take_int: in std_logic;
pe_sin: in signed(15 downto 0);
pe_cos: in signed(15 downto 0);
pe_pos_capt: in std_logic;
pe_pos_cnt: out std_logic_vector(31 downto 0);
pe_pos_sin: out std_logic_vector(31 downto 0);
pe_pos_cos: out std_logic_vector(31 downto 0);
pe_area_pol: in std_logic;
pe_area_flag: out std_logic;
pe_area_state: out std_logic;
pe_area_cnt: out std_logic_vector(31 downto 0);
pe_area_sin: out std_logic_vector(31 downto 0);
pe_area_cos: out std_logic_vector(31 downto 0)
);
end;
architecture rtl of PHPE_CHAN is
signal pe_trams_sync : std_logic_vector(1 downto 0);
signal pe_area_sync : std_logic_vector(1 downto 0);
signal pe_int_cnt : std_logic_vector(15 downto 0);
signal pe_int_reg : std_logic_vector(15 downto 0);
signal pe_take_reg : std_logic_vector(15 downto 0);
signal pe_ipol_reg : std_logic_vector(15 downto 0);
signal pe_ipol_step : std_logic_vector(16 downto 0);
signal pe_enc_cnt: std_logic_vector(31 downto 0);
signal pe_sin_prod : signed(33 downto 0);
signal pe_cos_prod : signed(33 downto 0);
signal pe_sin_accu : signed(33 downto 0);
signal pe_cos_accu : signed(33 downto 0);
signal pe_sin_reg : std_logic_vector(31 downto 0);
signal pe_cos_reg : std_logic_vector(31 downto 0);
signal pe_area_int: std_logic;
signal pe_area_dly: std_logic;
signal pe_area_done: std_logic;
signal pe_area_cnt_reg: std_logic_vector(31 downto 0);
signal pe_area_sin_reg: std_logic_vector(31 downto 0);
signal pe_area_cos_reg: std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
--- input syncer
----------------------------------------------------------
P_PE_TRAMS_SYNC : process(RESET, CLK100)
begin
if RESET = '1' then
pe_trams_sync <= (others => '0');
elsif rising_edge(CLK100) then
pe_trams_sync <= TRAMS & pe_trams_sync(1);
end if;
end process;
pe_area_int <= AREA xor pe_area_pol;
P_PE_AREA_SYNC : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_area_sync <= (others => '0');
elsif rising_edge(WB_CLK) then
pe_area_sync <= pe_area_int & pe_area_sync(1);
end if;
end process;
----------------------------------------------------------
--- pulse width messure
----------------------------------------------------------
P_PE_INT : process(RESET, CLK100)
begin
if RESET = '1' then
pe_int_cnt <= (others => '0');
pe_int_reg <= (others => '0');
elsif rising_edge(CLK100) then
if pe_disch_int = '1' then
pe_int_cnt <= (others => '0');
elsif pe_take_int = '1' then
pe_int_reg <= pe_int_cnt;
elsif pe_trams_sync(0) = '1' then
pe_int_cnt <= pe_int_cnt + 1;
end if;
end if;
end process;
----------------------------------------------------------
--- whisbone clock syncer
----------------------------------------------------------
P_PE_SYNC_WB : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_take_reg <= (others => '0');
elsif rising_edge(WB_CLK) then
if pe_scan_cnt_top = '1' then
pe_take_reg <= pe_int_reg;
end if;
end if;
end process;
----------------------------------------------------------
--- oversampling interpolator
----------------------------------------------------------
P_PE_IPOL : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_ipol_reg <= (others => '0');
elsif rising_edge(WB_CLK) then
if pe_scan_cnt_top = '1' then
pe_ipol_reg <= pe_take_reg;
elsif pe_scan_ovs_top = '1' then
pe_ipol_reg <= pe_ipol_step(16 downto 1);
end if;
end if;
end process;
pe_ipol_step <= pe_take_reg + pe_ipol_reg;
----------------------------------------------------------
--- sincos correlator
----------------------------------------------------------
P_PE_CORREL : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_enc_cnt <= (others => '0');
pe_sin_reg <= (others => '0');
pe_cos_reg <= (others => '0');
pe_sin_accu <= (others => '0');
pe_cos_accu <= (others => '0');
elsif rising_edge(WB_CLK) then
if pe_scan_ovs = '1' then
if pe_trars_cnt_bot = '1' then
pe_sin_reg <= std_logic_vector(pe_sin_accu(31 downto 0));
pe_cos_reg <= std_logic_vector(pe_cos_accu(31 downto 0));
if pe_cos_accu(31) = '1' then
if pe_sin_reg(31) = '0' and pe_sin_accu(31) = '1' then
pe_enc_cnt <= pe_enc_cnt + 1;
end if;
if pe_sin_reg(31) = '1' and pe_sin_accu(31) = '0' then
pe_enc_cnt <= pe_enc_cnt - 1;
end if;
end if;
pe_sin_accu <= pe_sin_prod;
pe_cos_accu <= pe_cos_prod;
else
pe_sin_accu <= pe_sin_accu + pe_sin_prod;
pe_cos_accu <= pe_cos_accu + pe_cos_prod;
end if;
end if;
end if;
end process;
pe_sin_prod <= unsigned(pe_ipol_reg) * pe_sin;
pe_cos_prod <= unsigned(pe_ipol_reg) * pe_cos;
pe_pos_cnt <= pe_enc_cnt;
P_PE_POS_CAPT : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_pos_sin <= (others => '0');
pe_pos_cos <= (others => '0');
pe_area_cnt <= (others => '0');
pe_area_sin <= (others => '0');
pe_area_cos <= (others => '0');
elsif rising_edge(WB_CLK) then
if pe_pos_capt = '1' then
pe_pos_sin <= pe_sin_reg;
pe_pos_cos <= pe_cos_reg;
pe_area_flag <= pe_area_done;
pe_area_cnt <= pe_area_cnt_reg;
pe_area_sin <= pe_area_sin_reg;
pe_area_cos <= pe_area_cos_reg;
end if;
end if;
end process;
----------------------------------------------------------
--- area edge detector
----------------------------------------------------------
P_PE_AREA : process(RESET, WB_CLK)
begin
if RESET = '1' then
pe_area_dly <= '0';
pe_area_done <= '0';
pe_area_cnt_reg <= (others => '0');
pe_area_sin_reg <= (others => '0');
pe_area_cos_reg <= (others => '0');
elsif rising_edge(WB_CLK) then
pe_area_dly <= pe_area_sync(0);
if pe_pos_capt = '1' then
pe_area_done <= '0';
elsif pe_area_done = '0' and pe_area_dly = '0' and pe_area_sync(0) = '1' then
pe_area_done <= '1';
pe_area_cnt_reg <= pe_enc_cnt;
pe_area_sin_reg <= pe_sin_reg;
pe_area_cos_reg <= pe_cos_reg;
end if;
end if;
end process;
pe_area_state <= pe_area_sync(0);
end;
| gpl-3.0 | 2f35def2e5422958f8d3ebf99eac4a35 | 0.512299 | 3.146756 | false | false | false | false |
thoralt/KCVGA | FPGA/SRAM_Controller.vhd | 1 | 3,754 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SRAM_Controller IS
PORT
(
clk, reset : IN STD_LOGIC;
-- to/from main system
mem : IN STD_LOGIC;
rw : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
data_f2s : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_s2f_r : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ready : OUT STD_LOGIC;
-- to/from chip
ad : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
we_n, oe_n : OUT STD_LOGIC;
-- SRAM chip
dio : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
ce_n, ub_n, lb_n : OUT STD_LOGIC
);
END SRAM_Controller;
ARCHITECTURE arch OF SRAM_Controller IS
TYPE state_type IS (idle, rd1, rd2, wr1, wr2);
SIGNAL state_reg, state_next : state_type;
SIGNAL data_f2s_reg, data_f2s_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL data_s2f_reg, data_s2f_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL addr_reg, addr_next : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL we_buf, oe_buf, tri_buf : STD_LOGIC;
SIGNAL we_reg, oe_reg, tri_reg : STD_LOGIC;
BEGIN
-- state & data registers
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN
state_reg <= idle;
addr_reg <= (OTHERS => '0');
data_f2s_reg <= (OTHERS => '0');
data_s2f_reg <= (OTHERS => '0');
tri_reg <= '1';
we_reg <= '1';
oe_reg <= '1';
ELSIF (clk'event AND clk = '1') THEN
state_reg <= state_next;
addr_reg <= addr_next;
data_f2s_reg <= data_f2s_next;
data_s2f_reg <= data_s2f_next;
tri_reg <= tri_buf;
we_reg <= we_buf;
oe_reg <= oe_buf;
END IF;
END PROCESS;
-- next-state logic
PROCESS (state_reg, mem, rw, dio, addr, data_f2s,
data_f2s_reg, data_s2f_reg, addr_reg)
BEGIN
addr_next <= addr_reg;
data_f2s_next <= data_f2s_reg;
data_s2f_next <= data_s2f_reg;
-- ready <= '0';
CASE state_reg IS
WHEN idle =>
IF mem = '0' THEN
state_next <= idle;
ELSE
addr_next <= addr;
IF rw = '0' THEN --write
state_next <= wr1;
data_f2s_next <= data_f2s;
ELSE -- read
state_next <= rd1;
END IF;
END IF;
-- ready <= '1';
WHEN wr1 =>
state_next <= wr2;
WHEN wr2 =>
state_next <= idle;
WHEN rd1 =>
state_next <= rd2;
WHEN rd2 =>
data_s2f_next <= dio;
state_next <= idle;
END CASE;
END PROCESS;
-- next-state logic
PROCESS (state_next)
BEGIN
tri_buf <= '1'; -- signals are active low
we_buf <= '1';
oe_buf <= '1';
CASE state_next IS
WHEN idle =>
WHEN wr1 =>
tri_buf <= '0';
we_buf <= '0';
WHEN wr2 =>
tri_buf <= '0';
WHEN rd1 =>
oe_buf <= '0';
WHEN rd2 =>
oe_buf <= '0';
END CASE;
END PROCESS;
-- to main system
data_s2f_r <= data_s2f_reg;
-- to sram
we_n <= we_reg;
oe_n <= oe_reg;
ad <= addr_reg;
--i/o for SRAM chip a
ce_n <= '0';
ub_n <= '0';
lb_n <= '0';
dio <= data_f2s_reg WHEN tri_reg = '0' ELSE
(OTHERS => 'Z');
END arch;
| mit | 41342a89960bd39ef72271562ea666e8 | 0.435535 | 3.459908 | false | false | false | false |
google/myelin-acorn-electron-hardware | minus_one/cpld/minus_one.vhd | 1 | 3,415 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity minus_one is
Port (
-- can't use a std_logic_vector here because we're missing A7-4 :(
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
D : in std_logic_vector(7 downto 0);
nRST : in std_logic;
PHI0 : in std_logic;
RnW : in std_logic;
cart0_nOE : out std_logic;
cart2_nOE : out std_logic;
cart4_nOE : out std_logic;
cart_nOE2 : out std_logic;
cart_ROMQA : out std_logic;
cart_nINFC : out std_logic;
cart_nINFD : out std_logic;
cart_nROMSTB : out std_logic;
GPIO1 : in std_logic;
GPIO2 : in std_logic;
GPIO3 : in std_logic
);
end minus_one;
architecture Behavioural of minus_one is
-- '1' when A = &8000-BFFF, i.e. sideways address space
signal sideways_select : std_logic;
-- high byte on the address bus
signal A_high : std_logic_vector(7 downto 0);
-- low nybble on the address bus
signal A_low : std_logic_vector(3 downto 0);
-- register: currently selected bank
signal bank : std_logic_vector(3 downto 0) := "1101";
begin
A_high <= A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8;
A_low <= A3 & A2 & A1 & A0;
-- '1' when A = &8000-BFFF
sideways_select <= '1' when (A15 & A14 = "10") else '0';
-- nOE for all cartridges
cart0_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "000") else '1';
cart2_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "001") else '1';
cart4_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "010") else '1';
-- bank select within cartridge address space
cart_ROMQA <= bank(0);
-- nOE2 (shared by all cartridges)
cart_nOE2 <= '0' when sideways_select = '1' and bank = "1101" else '1';
-- '0' when A = FCxx
cart_nINFC <= '0' when (A_high = x"FC") else '1';
-- '0' when A = FDxx
cart_nINFD <= '0' when (A_high = x"FD") else '1';
-- nROMSTB is not implemented
cart_nROMSTB <= '1';
process (PHI0)
begin
if nRST = '0' then
-- default to something that'll deactivate all cartridges
bank <= "1010";
elsif falling_edge(PHI0) then
-- ROM bank is selected by writing "0000xxxx" to &FEx5
if RnW = '0' and A_high = x"FE" and A_low = x"5" and D(7 downto 4) = "0000" then
bank <= D(3 downto 0);
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 33d059d1a59ce7bac6c8b0958e28d141 | 0.583895 | 3.246198 | false | false | false | false |
keith-epidev/md2x | build/code/sr_unit.vhdl | 1 | 901 | library ieee;
use ieee.std_logic_1164.all;
entity sr_unit is
port (
A : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0);
Cout : out std_logic
);
end sr_unit;
architecture arch of sr_unit is
begin
process(mode,A,Cin) begin
case(mode) is
when "00" =>
--shift left once
F <= A(6 downto 0) & Cin;
Cout <= A(7);
when "01" =>
--shift right once
F <= Cin & A(7 downto 1) ;
Cout <= A(0);
when "10" =>
--rotate left
Cout <= '0';
if Cin = '0' then
--once
F <= A(6 downto 0) & A(7);
else
--double
F <= A(5 downto 0) & A(6) & A(7);
end if;
when others =>
--rotate right
Cout <= '0';
if Cin = '0' then
--once
F <= A(0) & A(7 downto 1);
else
--double
F <= A(0) & A(1) & A(7 downto 2);
end if;
end case;
end process;
end arch;
| gpl-2.0 | 0ffe7cfe06bdb7b7e22666a6ae742916 | 0.539401 | 2.468493 | false | false | false | false |
google/myelin-acorn-electron-hardware | elk_pi_tube_direct/cpld/elk_pi_tube_direct.vhd | 1 | 2,956 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity elk_pi_tube_direct is
Port (
elk_D : inout std_logic_vector(7 downto 0);
elk_nINFC : in std_logic;
elk_A7 : in std_logic;
elk_A6 : in std_logic;
elk_A5 : in std_logic;
elk_A4 : in std_logic;
elk_A2 : in std_logic;
elk_A1 : in std_logic;
elk_A0 : in std_logic;
elk_nRST : in std_logic;
elk_RnW : in std_logic;
elk_PHI0 : in std_logic;
tube_A0 : out std_logic;
tube_A1 : out std_logic;
tube_A2 : out std_logic;
tube_D : inout std_logic_vector(7 downto 0);
tube_nRST : out std_logic;
tube_nTUBE : out std_logic;
tube_RnW : out std_logic;
tube_PHI0 : out std_logic
);
end elk_pi_tube_direct;
architecture Behavioural of elk_pi_tube_direct is
-- '0' when A = &FCEx: Tube memory space
signal nTUBE : std_logic;
-- '0' when A = &FCFx, for debugging
signal nDEBUG : std_logic;
-- Debug counter that is incremented any time the Electron writes to &FCFx
signal counter : std_logic_vector(4 downto 0) := "00000";
begin
-- tube /CE signal: A = &FCEx
nTUBE <= '0' when (elk_nINFC = '0' and elk_A7 = '1' and elk_A6 = '1' and elk_A5 = '1' and elk_A4 = '0') else '1';
tube_nTUBE <= nTUBE;
-- debug /CE signal: A = &FCFx
nDEBUG <= '0' when (elk_nINFC = '0' and elk_A7 = '1' and elk_A6 = '1' and elk_A5 = '1' and elk_A4 = '1') else '1';
-- copy across other signals
tube_nRST <= elk_nRST;
tube_RnW <= elk_RnW;
tube_PHI0 <= elk_PHI0;
tube_A0 <= elk_A0;
tube_A1 <= elk_A1;
tube_A2 <= elk_A2;
-- data goes both ways
tube_D <=
elk_D when (nTUBE = '0' and elk_RnW = '0') else
"ZZZZZZZZ";
elk_D <=
tube_D when (nTUBE = '0' and elk_RnW = '1') else
counter(3 downto 0) & '0' & elk_A2 & elk_A1 & elk_A0 when (nDEBUG = '0' and elk_RnW = '1') else
"ZZZZZZZZ";
-- increment debug counter
process (elk_PHI0)
begin
if falling_edge(elk_PHI0) then
if nDEBUG = '0' and elk_RnW = '0' then
-- writing one of the debug registers
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 1580bc5f781c7bf80161bd706fc00edd | 0.588633 | 2.982846 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyiv_atoms.vhd | 1 | 953,344 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package hardcopyiv_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE hardcopyiv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end hardcopyiv_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hardcopyiv_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end hardcopyiv_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package hardcopyiv_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end hardcopyiv_pllpack;
package body hardcopyiv_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end hardcopyiv_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiv_dffe : entity is TRUE;
end hardcopyiv_dffe;
-- architecture body --
architecture behave of hardcopyiv_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- hardcopyiv_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of hardcopyiv_mux21 : entity is TRUE;
end hardcopyiv_mux21;
architecture AltVITAL of hardcopyiv_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyiv_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_mux41 : entity is TRUE;
end hardcopyiv_mux41;
architecture AltVITAL of hardcopyiv_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- hardcopyiv_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiv_atom_pack.all;
-- entity declaration --
entity hardcopyiv_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiv_and1 : entity is TRUE;
end hardcopyiv_and1;
-- architecture body --
architecture AltVITAL of hardcopyiv_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_jtag
--
-- Description : HARDCOPYIV JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_jtag is
generic (
lpm_type : string := "hardcopyiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end hardcopyiv_jtag;
architecture architecture_jtag of hardcopyiv_jtag is
begin
end architecture_jtag;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_lcell_comb
--
-- Description : HARDCOPYIV LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "hardcopyiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_lcell_comb : entity is TRUE;
end hardcopyiv_lcell_comb;
architecture vital_lcell_comb of hardcopyiv_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_routing_wire
--
-- Description : HARDCOPYIV Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_routing_wire : entity is TRUE;
end hardcopyiv_routing_wire;
ARCHITECTURE behave of hardcopyiv_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_lvds_tx_reg : ENTITY is TRUE;
END hardcopyiv_lvds_tx_reg;
ARCHITECTURE vital_hardcopyiv_lvds_tx_reg of hardcopyiv_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_hardcopyiv_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiv_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiv_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the HARDCOPYIV
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyiv_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END hardcopyiv_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of hardcopyiv_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiv_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE std.textio.all;
ENTITY hardcopyiv_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END hardcopyiv_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of hardcopyiv_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : hardcopyiv_lvds_transmitter
--
-- Description : Timing simulation model for the HARDCOPYIV LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) HARDCOPYIV_lvds_tx_parallel_register and
-- 3) HARDCOPYIV_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE std.textio.all;
USE work.hardcopyiv_lvds_tx_parallel_register;
USE work.hardcopyiv_lvds_tx_out_block;
USE work.hardcopyiv_lvds_tx_reg;
ENTITY hardcopyiv_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- HARDCOPYIV
tx_output_path_delay_engineering_bits : Integer := -1; -- HARDCOPYIV
enable_dpaclk_to_lvdsout : string := "off"; -- HARDCOPYIV
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyiv_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- HARDCOPYIV
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- HARDCOPYIV
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- HARDCOPYIV
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end hardcopyiv_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of hardcopyiv_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;-- HARDCOPYIV
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT hardcopyiv_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);-- HARDCOPYIV
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: hardcopyiv_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: hardcopyiv_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: hardcopyiv_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd, -- HARDCOPYIV
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then-- HARDCOPYIV
dataout_tmp := dpaclkin_ipd;-- HARDCOPYIV
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then -- HARDCOPYIV
VitalPathDelay01 ( -- HARDCOPYIV
OutSignal => dataout, -- HARDCOPYIV
OutSignalName => "DATAOUT", -- HARDCOPYIV
OutTemp => dataout_tmp, -- HARDCOPYIV
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)), -- HARDCOPYIV
GlitchData => dataout_VitalGlitchData, -- HARDCOPYIV
Mode => DefGlitchMode, -- HARDCOPYIV
XOn => XOn, -- HARDCOPYIV
MsgOn => MsgOn ); -- HARDCOPYIV
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
----------------------------------------------------------------------------
-- Module Name : hardcopyiv_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END hardcopyiv_ram_register;
ARCHITECTURE reg_arch OF hardcopyiv_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : hardcopyiv_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF hardcopyiv_ram_pulse_generator:ENTITY IS TRUE;
END hardcopyiv_ram_pulse_generator;
ARCHITECTURE pgen_arch OF hardcopyiv_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_ram_register;
USE work.hardcopyiv_ram_pulse_generator;
ENTITY hardcopyiv_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END hardcopyiv_ram_block;
ARCHITECTURE block_arch OF hardcopyiv_ram_block IS
COMPONENT hardcopyiv_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiv_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : hardcopyiv_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : hardcopyiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : hardcopyiv_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : hardcopyiv_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : hardcopyiv_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : hardcopyiv_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : hardcopyiv_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_ff
--
-- Description : HARDCOPYIV FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_and1;
entity hardcopyiv_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "hardcopyiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_ff : entity is TRUE;
end hardcopyiv_ff;
architecture vital_lcell_ff of hardcopyiv_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component hardcopyiv_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: hardcopyiv_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: hardcopyiv_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: hardcopyiv_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for HARDCOPYIV CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- HARDCOPYIV_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_clkselect is
generic (
lpm_type : STRING := "hardcopyiv_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_clkselect : entity is TRUE;
end hardcopyiv_clkselect;
architecture vital_clkselect of hardcopyiv_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- hardcopyiv_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiv_atom_pack.all;
-- entity declaration --
entity hardcopyiv_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of hardcopyiv_and2 : entity is TRUE;
end hardcopyiv_and2;
-- architecture body --
architecture AltVITAL of hardcopyiv_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiv_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_ena_reg : entity is TRUE;
end hardcopyiv_ena_reg;
ARCHITECTURE behave of hardcopyiv_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for HARDCOPYIV CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- HARDCOPYIV_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ena_reg;
use work.hardcopyiv_and2;
entity hardcopyiv_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyiv_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_clkena : entity is TRUE;
end hardcopyiv_clkena;
architecture vital_clkena of hardcopyiv_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component hardcopyiv_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component hardcopyiv_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : hardcopyiv_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : hardcopyiv_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : hardcopyiv_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : hardcopyiv_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Entity Name : hardcopyiv_hram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiv_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_hram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF hardcopyiv_hram_pulse_generator:ENTITY IS TRUE;
END hardcopyiv_hram_pulse_generator;
ARCHITECTURE pgen_arch OF hardcopyiv_hram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
----------------------------------------------------------------------------
-- Entity Name : hardcopyiv_hram
-- Description : HRAM VHDL Simulation Model
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_hram_pulse_generator;
USE work.hardcopyiv_ram_register;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_hram IS
GENERIC (
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tipd_ena0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_devclrn : VitalDelayType01 := DefpropDelay01;
tipd_clr0 : VitalDelayType01 := DefpropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_portabyteenamasks :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portadatain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clr1 : VitalDelayType01 := DefpropDelay01;
tipd_devpor : VitalDelayType01 := DefpropDelay01;
tipd_ena1 : VitalDelayType01 := DefpropDelay01;
tipd_ena2 : VitalDelayType01 := DefpropDelay01;
tipd_portaaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_ena3 : VitalDelayType01 := DefpropDelay01;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01;
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "hram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_address_clock : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "hardcopyiv_hram";
lpm_hint : STRING := "true";
mem_init0 : BIT_VECTOR := X"0";
mixed_port_feed_through_mode : STRING := "dont_care"
);
PORT (
-- -------- PORT DECLARATIONS ---------
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END hardcopyiv_hram;
ARCHITECTURE trans OF hardcopyiv_hram IS
CONSTANT port_byte_size : INTEGER := (data_width / byte_enable_mask_width) + (data_width rem byte_enable_mask_width);
CONSTANT num_rows : INTEGER := 2**address_width;
CONSTANT num_cols : INTEGER := 1;
signal ena0_ipd :STD_LOGIC;
signal clk1_ipd :STD_LOGIC;
signal devclrn_ipd :STD_LOGIC;
signal clr0_ipd :STD_LOGIC;
signal clk0_ipd :STD_LOGIC;
signal portabyteenamasks_ipd :STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
signal portadatain_ipd :STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
signal clr1_ipd :STD_LOGIC;
signal devpor_ipd :STD_LOGIC;
signal ena1_ipd :STD_LOGIC;
signal ena2_ipd :STD_LOGIC;
signal portaaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
signal portbaddr_ipd :STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
signal ena3_ipd :STD_LOGIC;
COMPONENT hardcopyiv_hram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiv_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
TYPE type_xhdl0 IS ARRAY (num_rows - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0' ;
SIGNAL ena1_reg : STD_LOGIC := '0' ;
SIGNAL ena2_reg : STD_LOGIC := '0' ;
SIGNAL ena3_reg : STD_LOGIC := '0' ;
SIGNAL viol_notifier : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
-- -------- INTERNAL signals ---------
-- clock / clock enable
SIGNAL clk_a_in : STD_LOGIC;
SIGNAL clk_b_in : STD_LOGIC;
SIGNAL clk_b_out : STD_LOGIC;
-- asynch clear
SIGNAL addr_b_clr_in : STD_LOGIC;
SIGNAL dataout_b_clr_in : STD_LOGIC;
SIGNAL dataout_b_clr : STD_LOGIC;
SIGNAL addr_b_clr : STD_LOGIC;
SIGNAL addr_a_clr : STD_LOGIC;
SIGNAL datain_a_clr : STD_LOGIC;
SIGNAL byteena_a_clr : STD_LOGIC;
-- port A registers
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
-- port B registers
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL portbdataout_tmp : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- placeholders for read/written data
SIGNAL read_data_latch : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL mem_data : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- pulses for A/B ports (no read pulse)
SIGNAL write_pulse : STD_LOGIC;
SIGNAL write_cycle : STD_LOGIC;
-- memory core
SIGNAL mem : type_xhdl0;
-- byte enable
SIGNAL mask_vector : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL mask_vector_int : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
-- memory initialization
SIGNAL init_mem : BOOLEAN := FALSE;
-- port active for read/write
SIGNAL active_a : STD_LOGIC;
SIGNAL active_a_in : STD_LOGIC;
SIGNAL active_write_a : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl1 : STD_LOGIC;
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk1_ipd,clk1, tipd_clk1);
VitalWireDelay (ena0_ipd,ena0, tipd_ena0);
bits_portadatain : FOR i in portadatain'RANGE GENERATE
VitalWireDelay (portadatain_ipd(i),portadatain(i), tipd_portadatain(i));
END GENERATE;
bits_portabyteenamasks : FOR i in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(i),portabyteenamasks(i), tipd_portabyteenamasks(i));
END GENERATE;
VitalWireDelay (clk0_ipd,clk0, tipd_clk0);
VitalWireDelay (clr0_ipd,clr0, tipd_clr0);
VitalWireDelay (devclrn_ipd,devclrn, tipd_devclrn);
VitalWireDelay (clr1_ipd,clr1, tipd_clr1);
VitalWireDelay (ena1_ipd,ena1, tipd_ena1);
VitalWireDelay (devpor_ipd,devpor, tipd_devpor);
bits_portaaddr : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i),portaaddr(i), tipd_portaaddr(i));
END GENERATE;
VitalWireDelay (ena2_ipd,ena2, tipd_ena2);
bits_portbaddr : FOR i in portbaddr'RANGE GENERATE
VitalWireDelay (portbaddr_ipd(i),portbaddr(i), tipd_portbaddr(i));
END GENERATE;
VitalWireDelay (ena3_ipd,ena3, tipd_ena3);
END BLOCK;
------------------------
-- Functionality Section --
------------------------
reset <= ena0_reg;
init_mem <= TRUE;
clk_a_in <= clk0_ipd;
clk_b_in <= clk0_ipd WHEN (port_b_address_clock = ("clock0")) ELSE
clk1_ipd WHEN (port_b_address_clock = ("clock1")) ELSE
'0';
clk_b_out <= clk1_ipd WHEN (port_b_data_out_clock = ("clock1")) ELSE
'0';
PROCESS (clk_a_in)
BEGIN
IF (clk_a_in'EVENT AND clk_a_in = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
PROCESS (clk_b_out)
BEGIN
IF (clk_b_out'EVENT AND clk_b_out = '1') THEN
ena1_reg <= ena1_ipd;
END IF;
END PROCESS;
PROCESS (clk_a_in)
BEGIN
IF (clk_a_in'EVENT AND clk_a_in = '1') THEN
ena2_reg <= ena2_ipd;
END IF;
END PROCESS;
PROCESS (clk_b_in)
BEGIN
IF (clk_b_in'EVENT AND clk_b_in = '1') THEN
ena3_reg <= ena3_ipd;
END IF;
END PROCESS;
addr_b_clr_in <= clr0_ipd WHEN (port_b_address_clear = ("clear0")) ELSE
'0';
dataout_b_clr_in <= clr1_ipd WHEN (port_b_data_out_clear = ("clear1")) ELSE
'0';
-- Port A registers
-- address register
addr_a_register : hardcopyiv_ram_register
GENERIC MAP (
width => address_width
)
PORT MAP (
d => portaaddr_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data register
datain_a_register : hardcopyiv_ram_register
GENERIC MAP (
width => data_width
)
PORT MAP (
d => portadatain_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable register
byteena_a_register : hardcopyiv_ram_register
GENERIC MAP (
width => byte_enable_mask_width
)
PORT MAP (
d => portabyteenamasks_ipd,
clk => clk_a_in,
aclr => '0',
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena2,
stall => '0',
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- Port B registers
-- address register
addr_b_register : hardcopyiv_ram_register
GENERIC MAP (
width => address_width
)
PORT MAP (
d => portbaddr_ipd,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena3,
stall => '0',
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data register
data_b_register : hardcopyiv_ram_register
GENERIC MAP (
width => data_width
)
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_in,
devclrn =>devclrn_ipd,
devpor =>devpor_ipd,
ena => ena1,
stall => '0',
q => dataout_b_reg,
aclrout => dataout_b_clr
);
-- Write pulse generation
xhdl1 <= NOT(clk_a_in);
wpgen_a : hardcopyiv_hram_pulse_generator
PORT MAP (
clk => xhdl1,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Read pulse generation
-- -- none --
-- Create internal masks for byte enable processing
PROCESS (byteena_a_reg)
BEGIN
FOR i IN 0 TO data_width-1 LOOP
IF (byteena_a_reg(i / port_byte_size) = '1') THEN
mask_vector(i) <= '0';
ELSE
mask_vector(i) <= 'X';
END IF;
IF (byteena_a_reg(i / port_byte_size) = '0') THEN
mask_vector_int(i) <= '0';
ELSE
mask_vector_int(i) <= 'X';
END IF;
END LOOP;
END PROCESS;
PROCESS (init_mem, write_pulse)
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : type_xhdl0;
VARIABLE mem_data_p : STD_LOGIC_VECTOR(data_width-1 downto 0);
BEGIN
-- powerup output to 0
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "NONE" AND init_file /= "none") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(bin2int(addr_a_reg));
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector_int(i);
END LOOP;
mem(bin2int(addr_a_reg)) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(bin2int(addr_a_reg));
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(i) = '0') THEN
mem(bin2int(addr_a_reg))(i) <= datain_a_reg(i);
mem_data_p(i) := datain_a_reg(i);
ELSIF (mask_vector_int(i) = 'X') THEN
mem(bin2int(addr_a_reg))(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS;
-- Read stage : asynchronous continuous read
dataout_b <= mem(bin2int(portbaddr_ipd)) WHEN (port_b_address_clock = ("none")) ELSE
mem(bin2int(addr_b_reg));
portbdataout_tmp <= dataout_b_reg WHEN (port_b_data_out_clock = ("clock1")) ELSE
dataout_b;
--portbdataout <= portbdataout_tmp;
------------------------
-- Path Delay Section --
------------------------
PathDelay_portbdataout : BLOCK
BEGIN
portbdataout_GEN : FOR i IN portbdataout'RANGE GENERATE
PROCESS(portbdataout_tmp)
variable portbdataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => portbdataout(i),
OutSignalName => "portbdataout",
OutTemp => portbdataout_tmp(i),
Paths => (
0 => (portbaddr_ipd'last_event, tpd_portbaddr_portbdataout, TRUE)),
GlitchData => portbdataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS;
END GENERATE;
END BLOCK;
END trans;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_io_ibuf
--
-- Description : HARDCOPYIV IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "hardcopyiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END hardcopyiv_io_ibuf;
ARCHITECTURE arch OF hardcopyiv_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_io_obuf
--
-- Description : HARDCOPYIV IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "hardcopyiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END hardcopyiv_io_obuf;
ARCHITECTURE arch OF hardcopyiv_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_ddio_in
--
-- Description : HARDCOPYIV DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "hardcopyiv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_ddio_in;
ARCHITECTURE arch OF hardcopyiv_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_ddio_oe
--
-- Description : HARDCOPYIV DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "hardcopyiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_ddio_oe;
ARCHITECTURE arch OF hardcopyiv_ddio_oe IS
component hardcopyiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : hardcopyiv_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_ddio_out
--
-- Description : HARDCOPYIV DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "hardcopyiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_ddio_out;
ARCHITECTURE arch OF hardcopyiv_ddio_out IS
component hardcopyiv_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : hardcopyiv_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: hardcopyiv_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY hardcopyiv_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END hardcopyiv_rt_sm;
ARCHITECTURE hardcopyiv_rt_sm_rtl OF hardcopyiv_rt_sm IS
CONSTANT HARDCOPYIV_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT HARDCOPYIV_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT HARDCOPYIV_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT HARDCOPYIV_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT HARDCOPYIV_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT HARDCOPYIV_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT HARDCOPYIV_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT HARDCOPYIV_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT HARDCOPYIV_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= HARDCOPYIV_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN HARDCOPYIV_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= HARDCOPYIV_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIV_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIV_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= HARDCOPYIV_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= HARDCOPYIV_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= HARDCOPYIV_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN HARDCOPYIV_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= HARDCOPYIV_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN HARDCOPYIV_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN HARDCOPYIV_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIV_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIV_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN HARDCOPYIV_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= HARDCOPYIV_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN HARDCOPYIV_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN HARDCOPYIV_RTOCT_DONE =>
next_state <= HARDCOPYIV_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= HARDCOPYIV_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END hardcopyiv_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiv_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY hardcopyiv_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END hardcopyiv_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF hardcopyiv_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_termination
--
-- Description : HARDCOPYIV Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.hardcopyiv_atom_pack.all;
USE WORK.hardcopyiv_termination_aux_clock_div;
USE WORK.hardcopyiv_rt_sm;
ENTITY hardcopyiv_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "hardcopyiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END hardcopyiv_termination;
ARCHITECTURE hardcopyiv_oct_arch OF hardcopyiv_termination IS
COMPONENT hardcopyiv_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiv_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : hardcopyiv_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : hardcopyiv_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END hardcopyiv_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_termination_logic
--
-- Description : HARDCOPYIV Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "hardcopyiv_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END hardcopyiv_termination_logic;
ARCHITECTURE hardcopyiv_oct_logic_arch OF hardcopyiv_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END hardcopyiv_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package hardcopyiv_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end hardcopyiv_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hardcopyiv_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end hardcopyiv_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY hardcopyiv_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END hardcopyiv_dll_gray_encoder;
ARCHITECTURE hardcopyiv_dll_gray_encoder_arch OF hardcopyiv_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END hardcopyiv_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY hardcopyiv_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END hardcopyiv_dll_gray_decoder;
ARCHITECTURE hardcopyiv_dll_gray_decoder_arch OF hardcopyiv_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END hardcopyiv_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiv_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_dll_gray_decoder;
ENTITY hardcopyiv_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END hardcopyiv_ddr_delay_chain_s;
ARCHITECTURE hardcopyiv_ddr_delay_chain_s_arch OF hardcopyiv_ddr_delay_chain_s IS
COMPONENT hardcopyiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END hardcopyiv_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of hardcopyiv_ddr_io_reg : entity is TRUE;
end hardcopyiv_ddr_io_reg;
architecture vital_hardcopyiv_ddr_io_reg of hardcopyiv_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_hardcopyiv_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/hardcopyiv_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiv_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : HARDCOPYIV_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_pllpack.all;
use work.hardcopyiv_atom_ddr_pack.all;
use work.hardcopyiv_dll_gray_encoder;
ENTITY hardcopyiv_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "hardcopyiv_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END hardcopyiv_dll;
ARCHITECTURE vital_hcxivdll of hardcopyiv_dll is
COMPONENT hardcopyiv_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in hardcopyiv
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in hardcopyiv
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in hardcopyiv
signal pc_comp_range : integer := 0; -- new in hardcopyiv
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : hardcopyiv_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in hardcopyiv
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_hcxivdll;
-------------------------------------------------------------------------------
--
-- Entity Name : HARDCOPYIV_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_pllpack.all;
use work.hardcopyiv_atom_ddr_pack.all;
use work.hardcopyiv_dll_gray_encoder;
use work.hardcopyiv_dll_gray_decoder;
ENTITY hardcopyiv_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "hardcopyiv_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END hardcopyiv_dll_offset_ctrl;
ARCHITECTURE vital_hcxivoffset of hardcopyiv_dll_offset_ctrl is
COMPONENT hardcopyiv_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : hardcopyiv_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_hcxivoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_dll_gray_decoder;
ENTITY hardcopyiv_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_dqs_delay_chain_arch OF hardcopyiv_dqs_delay_chain IS
-- component section
COMPONENT hardcopyiv_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : hardcopyiv_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiv_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_dqs_enable IS
GENERIC (
lpm_type : string := "hardcopyiv_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_dqs_enable_arch OF hardcopyiv_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiv_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ddr_io_reg;
use work.hardcopyiv_ddr_delay_chain_s;
ENTITY hardcopyiv_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_dqs_enable_ctrl_arch OF hardcopyiv_dqs_enable_ctrl IS
-- component section
COMPONENT hardcopyiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : hardcopyiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : hardcopyiv_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : hardcopyiv_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : hardcopyiv_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : hardcopyiv_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiv_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "hardcopyiv_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_delay_chain_arch OF hardcopyiv_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END hardcopyiv_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ddr_delay_chain_s;
ENTITY hardcopyiv_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_io_clock_divider_arch OF hardcopyiv_io_clock_divider IS
-- component section
COMPONENT hardcopyiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : hardcopyiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END hardcopyiv_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ddr_io_reg;
use work.hardcopyiv_ddr_delay_chain_s;
ENTITY hardcopyiv_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "hardcopyiv_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_output_phase_alignment_arch OF hardcopyiv_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT hardcopyiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : hardcopyiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : hardcopyiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiv_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ddr_io_reg;
use work.hardcopyiv_ddr_delay_chain_s;
ENTITY hardcopyiv_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiv_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_input_phase_alignment_arch OF hardcopyiv_input_phase_alignment IS
-- component section
COMPONENT hardcopyiv_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component hardcopyiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : hardcopyiv_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END hardcopyiv_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
use work.hardcopyiv_ddr_io_reg;
ENTITY hardcopyiv_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "hardcopyiv_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_half_rate_input_arch OF hardcopyiv_half_rate_input IS
-- component section
component hardcopyiv_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : hardcopyiv_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END hardcopyiv_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiv_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_io_config_arch OF hardcopyiv_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiv_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiv_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE hardcopyiv_dqs_config_arch OF hardcopyiv_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/HARDCOPYIV_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END hardcopyiv_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiv_mac_bit_register --
-- Description: HARDCOPYIV MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiv_mac_bit_register;
ARCHITECTURE arch OF hardcopyiv_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiv_mac_register --
-- Description: HARDCOPYIV MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END hardcopyiv_mac_register;
ARCHITECTURE arch OF hardcopyiv_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: hardcopyiv_mac_multiplier --
-- Description: HARDCOPYIV MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END hardcopyiv_mac_multiplier;
ARCHITECTURE arch OF hardcopyiv_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: hardcopyiv_mac_mult_atom --
-- Description: Simulation model for hardcopyiv mac mult atom. --
-- This model instantiates the following components. --
-- 1.hardcopyiv_mac_bit_register. --
-- 2.hardcopyiv_mac_register. --
-- 3.hardcopyiv_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_mac_mult;
ARCHITECTURE arch OF hardcopyiv_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT hardcopyiv_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : hardcopyiv_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_fsa_isse --
-- Description: HARDCOPYIV first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END hardcopyiv_fsa_isse;
ARCHITECTURE arch OF hardcopyiv_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_first_stage_add_sub --
-- Description: HARDCOPYIV First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiv_first_stage_add_sub;
ARCHITECTURE arch OF hardcopyiv_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_second_stage_add_accum --
-- Description: HARDCOPYIV Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END hardcopyiv_second_stage_add_accum;
ARCHITECTURE arch OF hardcopyiv_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_round_block --
-- Description: HARDCOPYIV round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiv_round_block;
ARCHITECTURE arch OF hardcopyiv_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_saturate_block --
-- Description: HARDCOPYIV saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END hardcopyiv_saturate_block;
ARCHITECTURE arch OF hardcopyiv_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_round_saturate_block --
-- Description: HARDCOPYIV round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.hardcopyiv_round_block. --
-- 2.hardcopyiv_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END hardcopyiv_round_saturate_block;
ARCHITECTURE arch OF hardcopyiv_round_saturate_block IS
COMPONENT hardcopyiv_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : hardcopyiv_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : hardcopyiv_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_rotate_shift_block --
-- Description: HARDCOPYIV roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END hardcopyiv_rotate_shift_block;
ARCHITECTURE arch OF hardcopyiv_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: hardcopyiv_carry_chain_adder --
-- Description: HARDCOPYIV carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END hardcopyiv_carry_chain_adder;
ARCHITECTURE arch OF hardcopyiv_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: hardcopyiv_mac_out_atom --
-- Description: Simulation model for hardcopyiv mac out atom --
-- This model instantiates the following components --
-- 1.hardcopyiv_mac_bit_register --
-- 2.hardcopyiv_mac_register --
-- 3.hardcopyiv_fsa_isse --
-- 4.hardcopyiv_first_stage_add_sub --
-- 5.hardcopyiv_second_stage_add_accum --
-- 6.hardcopyiv_round_saturate_block --
-- 7.hardcopyiv_rotate_shift_block --
-- 8.hardcopyiv_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiv_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END hardcopyiv_mac_out;
ARCHITECTURE arch OF hardcopyiv_mac_out IS
COMPONENT hardcopyiv_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT hardcopyiv_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : hardcopyiv_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : hardcopyiv_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : hardcopyiv_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : hardcopyiv_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : hardcopyiv_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : hardcopyiv_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : hardcopyiv_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : hardcopyiv_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : hardcopyiv_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : hardcopyiv_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : hardcopyiv_io_pad
-- Description : Simulation model for hardcopyiv IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_io_pad IS
GENERIC (
lpm_type : string := "hardcopyiv_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END hardcopyiv_io_pad;
ARCHITECTURE arch OF hardcopyiv_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiv_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the HARDCOPYIV PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END hardcopyiv_mn_cntr;
ARCHITECTURE behave of hardcopyiv_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiv_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the HARDCOPYIV PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END hardcopyiv_scale_cntr;
ARCHITECTURE behave of hardcopyiv_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiv_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY hardcopyiv_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end hardcopyiv_pll_reg;
ARCHITECTURE behave of hardcopyiv_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : hardcopyiv_pll
--
-- Description : Timing simulation model for the HARDCOPYIV PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_pllpack.all;
USE work.hardcopyiv_mn_cntr;
USE work.hardcopyiv_scale_cntr;
USE work.hardcopyiv_dffe;
USE work.hardcopyiv_pll_reg;
-- New Features : The list below outlines key new features in HARDCOPYIV:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY hardcopyiv_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyiv_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "HARDCOPYIV";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END hardcopyiv_pll;
ARCHITECTURE vital_pll of hardcopyiv_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT hardcopyiv_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyiv_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT hardcopyiv_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT hardcopyiv_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : hardcopyiv_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : hardcopyiv_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : hardcopyiv_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : hardcopyiv_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : hardcopyiv_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : hardcopyiv_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : hardcopyiv_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : hardcopyiv_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : hardcopyiv_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : hardcopyiv_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : hardcopyiv_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : hardcopyiv_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/hardcopyiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/hardcopyiv_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_asmiblock
--
-- Description : HARDCOPYIV ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_asmiblock is
generic (
lpm_type : string := "hardcopyiv_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end hardcopyiv_asmiblock;
architecture architecture_asmiblock of hardcopyiv_asmiblock is
begin
end architecture_asmiblock; -- end of hardcopyiv_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END hardcopyiv_lvds_reg;
ARCHITECTURE vital_hardcopyiv_lvds_reg of hardcopyiv_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_hardcopyiv_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiv_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF hardcopyiv_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_lvds_rx_fifo_sync_ram;
ENTITY hardcopyiv_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END hardcopyiv_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of hardcopyiv_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT hardcopyiv_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : hardcopyiv_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_lvds_reg;
ENTITY hardcopyiv_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END hardcopyiv_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF hardcopyiv_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT hardcopyiv_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : hardcopyiv_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : hardcopyiv_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_rx_deser
--
-- Description : Timing simulation model for the hardcopyiv LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF hardcopyiv_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the hardcopyiv LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF hardcopyiv_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hardcopyiv_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END hardcopyiv_pclk_divider;
ARCHITECTURE arch OF hardcopyiv_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY hardcopyiv_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END hardcopyiv_select_ini_phase_dpaclk;
ARCHITECTURE trans OF hardcopyiv_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY hardcopyiv_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END hardcopyiv_dpa_retime_block;
ARCHITECTURE trans OF hardcopyiv_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : hardcopyiv_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.hardcopyiv_dpa_retime_block;
ENTITY hardcopyiv_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END hardcopyiv_dpa_block;
ARCHITECTURE trans OF hardcopyiv_dpa_block IS
COMPONENT hardcopyiv_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : hardcopyiv_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : hardcopyiv_LVDS_RECEIVER
--
-- Description : Timing simulation model for the hardcopyiv LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) hardcopyiv_lvds_rx_fifo
-- 2) hardcopyiv_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) hardcopyiv_lvds_rx_parallel_reg
-- 5) hardcopyiv_pclk_divider
-- 6) hardcopyiv_select_ini_phase_dpaclk
-- 7) hardcopyiv_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.hardcopyiv_atom_pack.all;
USE work.hardcopyiv_lvds_rx_bitslip;
USE work.hardcopyiv_lvds_rx_fifo;
USE work.hardcopyiv_lvds_rx_deser;
USE work.hardcopyiv_lvds_rx_parallel_reg;
USE work.hardcopyiv_lvds_reg;
USE work.hardcopyiv_pclk_divider;
USE work.hardcopyiv_select_ini_phase_dpaclk;
USE work.hardcopyiv_dpa_block;
ENTITY hardcopyiv_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyiv_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END hardcopyiv_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF hardcopyiv_lvds_receiver IS
COMPONENT hardcopyiv_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiv_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT hardcopyiv_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT hardcopyiv_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT hardcopyiv_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal in_reg_data_dly : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
signal ini_dpa_clk_dly : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
process(in_reg_data)
begin
if(dpaswitch_ipd = '1') then
if(rx_input_path_delay_engineering_bits = 1) then
in_reg_data_dly <= TRANSPORT in_reg_data after 60 ps;
elsif(rx_input_path_delay_engineering_bits = 2) then
in_reg_data_dly <= TRANSPORT in_reg_data after 120 ps;
elsif(rx_input_path_delay_engineering_bits = 3) then
in_reg_data_dly <= TRANSPORT in_reg_data after 180 ps;
else
in_reg_data_dly <= in_reg_data;
end if;
else
in_reg_data_dly <= in_reg_data;
end if;
end process;
xhdl_12 <= devclrn OR devpor;
process(ini_dpa_clk)
begin
ini_dpa_clk_dly <= ini_dpa_clk;
end process;
-- input register in non-DPA mode for sampling incoming data
in_reg : hardcopyiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : hardcopyiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: hardcopyiv_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : hardcopyiv_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => ini_dpa_clk_dly,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : hardcopyiv_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: hardcopyiv_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: hardcopyiv_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : hardcopyiv_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : hardcopyiv_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" ) else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : hardcopyiv_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : hardcopyiv_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : hardcopyiv_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: hardcopyiv_pseudo_diff_out --
--Description: Simulation model for HARDCOPYIV Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "hardcopyiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END hardcopyiv_pseudo_diff_out;
ARCHITECTURE arch OF hardcopyiv_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiv_bias_logic
--
-- Description : HARDCOPYIV Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiv_bias_logic : ENTITY IS TRUE;
end hardcopyiv_bias_logic;
ARCHITECTURE vital_bias_logic of hardcopyiv_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiv_bias_generator
--
-- Description : HARDCOPYIV Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiv_bias_generator : ENTITY IS TRUE;
end hardcopyiv_bias_generator;
ARCHITECTURE vital_bias_generator of hardcopyiv_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 100;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : hardcopyiv_bias_block
--
-- Description : HARDCOPYIV Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
ENTITY hardcopyiv_bias_block IS
GENERIC (
lpm_type : string := "hardcopyiv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of hardcopyiv_bias_block : ENTITY IS TRUE;
end hardcopyiv_bias_block;
ARCHITECTURE vital_bias_block of hardcopyiv_bias_block IS
COMPONENT hardcopyiv_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT hardcopyiv_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : hardcopyiv_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : hardcopyiv_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_tsdblock
--
-- Description : HARDCOPYIV TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "hardcopyiv_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end hardcopyiv_tsdblock;
architecture architecture_tsdblock of hardcopyiv_tsdblock is
begin
end architecture_tsdblock; -- end of hardcopyiv_tsdblock
---------------------------------------------------------------------
--
-- Entity Name : hardcopyiv_lcell_hsadder
--
-- Description : HARDCOPYIII LCELL_HSADDER VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.hardcopyiv_atom_pack.all;
entity hardcopyiv_lcell_hsadder is
generic (
dataa_width : integer := 2;
datab_width : integer := 2;
cin_inverted : string := "off";
lpm_type : string := "hardcopyiv_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_datab_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_cin_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic_vector(dataa_width - 1 downto 0) := (OTHERS => '0');
datab : in std_logic_vector(datab_width - 1 downto 0) := (OTHERS => '0');
cin : in std_logic := '0';
sumout: out std_logic_vector((calc_sum_len(dataa_width, datab_width)) - 2 downto 0);
cout : out std_logic
);
--attribute VITAL_LEVEL0 of hardcopyiv_lcell_hsadder : entity is TRUE;
end hardcopyiv_lcell_hsadder;
architecture vital_lcell_hsadder of hardcopyiv_lcell_hsadder is
-- attribute VITAL_LEVEL0 of vital_lcell_hsadder : architecture is TRUE;
constant sumout_width : integer := calc_sum_len(dataa_width, datab_width);
signal dataa_ipd : std_logic_vector(dataa_width - 1 downto 0);
signal datab_ipd : std_logic_vector(datab_width - 1 downto 0);
signal cin_ipd : std_logic := '0';
signal idataa_ipd : std_logic_vector(sumout_width - 1 downto 0);
signal idatab_ipd : std_logic_vector(sumout_width - 1 downto 0);
-- internal signal
signal cin_sel : std_logic;
-- output signal
signal sumout_tmp : std_logic_vector(sumout_width - 1 DOWNTO 0) := (OTHERS => '0');
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
loopa : FOR i in dataa'RANGE GENERATE
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
END GENERATE;
loopb : FOR i in datab'RANGE GENERATE
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
END GENERATE;
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
idataa_ipd <= ('0' & dataa_ipd);
idatab_ipd <= ('0' & datab_ipd);
cin_sel <= (NOT cin_ipd) WHEN cin_inverted = "on" ELSE cin_ipd;
sumout_tmp <= (idataa_ipd + idatab_ipd + 1) WHEN cin_sel = '1' ELSE
(idataa_ipd + idatab_ipd);
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
do1 : for i in sumout'RANGE generate
process(sumout_tmp(i))
VARIABLE sumout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => sumout(i),
OutSignalName => "sumout",
OutTemp => sumout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout(i),
TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout(i),
TRUE),
2 => (cin_ipd'last_event, tpd_cin_sumout(i), TRUE))
,
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(sumout_tmp(sumout_width - 1))
VARIABLE cout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "cout",
OutTemp => sumout_tmp(sumout_width - 1),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout,TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout,TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout,TRUE))
,
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end block;
end vital_lcell_hsadder;
---------------------------------------------------------------------------------------
--
-- Entity Name: hardcopyiv_otp
--
-- Description: VHDL Simulation model for HARDCOPYIII OTP (One Time Programmable)
--
---------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY STD;
USE STD.textio.ALL;
USE work.hardcopyiv_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY hardcopyiv_otp IS
GENERIC
(
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
TimingChecksOn : Boolean := True;
tipd_otpclken : VitalDelayType01 := DefpropDelay01;
tipd_otpclk : VitalDelayType01 := DefpropDelay01;
tipd_otpshiftnld : VitalDelayType01 := DefpropDelay01;
tpd_otpshiftnld_otpdout : VitalDelayType01 := DefpropDelay01;
tsetup_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
data_width : INTEGER := 128;
init_data : STD_LOGIC_VECTOR(127 DOWNTO 0) := (OTHERS => '0');
init_file : STRING := "init_file.hex";
lpm_type : STRING := "hardcopyiv_otp";
lpm_hint : STRING := "true"
);
---------- PORT DECLARATIONS ---------
PORT
(
otpclken : IN STD_LOGIC := '1';
otpclk : IN STD_LOGIC := '0';
otpshiftnld : IN STD_LOGIC := '0';
otpdout : OUT STD_LOGIC
);
END hardcopyiv_otp;
ARCHITECTURE arch OF hardcopyiv_otp IS
SIGNAL otpclken_ipd : STD_LOGIC := '1';
SIGNAL otpclk_ipd : STD_LOGIC := '0';
SIGNAL otpshiftnld_ipd : STD_LOGIC := '0';
SIGNAL otpdout_tmp : STD_LOGIC := '0';
SIGNAL viol_notifier : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL prev_loc : INTEGER := -1;
SIGNAL current_loc : INTEGER := 0;
SIGNAL first_use : STD_LOGIC := '1';
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (otpclken_ipd, otpclken, tipd_otpclken);
VitalWireDelay (otpclk_ipd, otpclk, tipd_otpclk);
VitalWireDelay (otpshiftnld_ipd, otpshiftnld, tipd_otpshiftnld);
END BLOCK;
---------------------------
-- Timing check section --
---------------------------
TimingChecks: PROCESS(otpclk_ipd, otpshiftnld_ipd)
VARIABLE Tviol_otpshiftnld_otpclk : STD_ULOGIC := '0';
VARIABLE TimingData_otpshiftnld_otpclk : VitalTimingDataType:= VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck
(
TestSignal => otpshiftnld_ipd,
TestSignalName => "otpshiftnld",
RefSignal => otpclk_ipd,
RefSignalName => "otpclk",
SetupHigh => tsetup_otpshiftnld_otpclk_noedge_posedge,
SetupLow => tsetup_otpshiftnld_otpclk_noedge_posedge,
HoldHigh => thold_otpshiftnld_otpclk_noedge_posedge,
HoldLow => thold_otpshiftnld_otpclk_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
MsgOn => MsgOn,
XOn => XOn,
HeaderMsg => "/hardcopyiv_otp",
TimingData => TimingData_otpshiftnld_otpclk,
Violation => Tviol_otpshiftnld_otpclk
);
END IF;
END PROCESS TimingChecks;
----------------------------
-- Functionality Section --
----------------------------
PROCESS(prev_loc)
BEGIN
current_loc <= prev_loc + 1;
END PROCESS;
PROCESS(otpclk_ipd)
BEGIN
IF (otpclk_ipd'EVENT and otpclk_ipd = '1') THEN
-- operation only if clock enable is high
IF (otpclken_ipd = '1') THEN
-- shift data
IF (otpshiftnld_ipd = '1' AND first_use = '0') THEN
-- shifting out '0' if otpclken and otpshiftnld is high beyond 128 clock cycles
IF (prev_loc = 127) THEN
otpdout_tmp <= '0';
-- shifting the data bit by bit
ELSE
otpdout_tmp <= init_data(current_loc);
prev_loc <= current_loc;
END IF;
-- load data
ELSIF (otpshiftnld_ipd = '0') THEN
otpdout_tmp <= init_data(0);
first_use <= '0';
prev_loc <= 0;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------
-- Path Delay Section --
-------------------------
PathDelay : BLOCK
BEGIN
PROCESS(otpdout_tmp)
VARIABLE otpdout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01
(
OutSignal => otpdout,
OutSignalName => "otpdout",
OutTemp => otpdout_tmp,
Paths => ( 0 => (otpshiftnld_ipd'last_event, tpd_otpshiftnld_otpdout, TRUE)),
GlitchData => otpdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END BLOCK;
END arch;
| gpl-3.0 | 41ce1fb0a714bb1a16fe48f5ba27e144 | 0.469019 | 4.162493 | false | false | false | false |
alvieboy/xtc-base | icache.vhd | 1 | 15,186 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity icache is
generic (
ADDRESS_HIGH: integer := 31
);
port (
syscon: in wb_syscon_type;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
seq: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
mwbo: out wb_mosi_type;
mwbi: in wb_miso_type
);
end icache;
architecture behave of icache is
constant ADDRESS_LOW: integer := 0;
constant CACHE_MAX_BITS: integer := 13; -- 8 Kb
constant CACHE_LINE_SIZE_BITS: integer := 6; -- 64 bytes
constant CACHE_LINE_SIZE: integer := 2**CACHE_LINE_SIZE_BITS;
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
-- memory max width: 19 bits (18 downto 0)
-- cache line size: 64 bytes
-- cache lines: 128
alias line: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0)
is address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
alias line_offset: std_logic_vector(CACHE_LINE_SIZE_BITS-1 downto 2)
is address(CACHE_LINE_SIZE_BITS-1 downto 2);
signal ctag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal miss: std_logic;
signal ack: std_logic;
type state_type is (
flushing,
running,
filling,
--waitwrite,
ending
);
constant offcnt_zero: unsigned(line_offset'HIGH downto 2) := (others => '0');
signal tag_match: std_logic;
signal cache_addr_read,cache_addr_write: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal access_i: std_logic;
signal stall_i, valid_i: std_logic;
signal hit: std_logic;
signal tag_mem_enable: std_logic;
signal cache_mem_enable: std_logic;
signal exttag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
signal tag_mem_data: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+1 downto 0);
signal tag_mem_addr: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
constant dignore: std_logic_vector(ctag'RANGE) := (others => DontCareValue);
constant dignore32: std_logic_vector(31 downto 0) := (others => DontCareValue);
signal valid_while_filling: std_logic;
type icache_regs_type is record
cyc, stb: std_logic;
busy: std_logic;
state: state_type;
fill_success: std_logic;
flushcnt: unsigned(line'RANGE);
tag_mem_wen: std_logic;
wbaddr: std_logic_vector(31 downto CACHE_MAX_BITS);
offcnt: unsigned(line_offset'HIGH downto 2);
offcnt_write: unsigned(line_offset'HIGH downto 2);
stbcount: unsigned(line_offset'HIGH downto 2);
access_q: std_logic;
queued_address: std_logic;
save_addr: std_logic_vector(address'RANGE);
line_save: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
enable_q: std_logic;
iwfready: std_logic;
fault: std_logic;
flush: std_logic;
end record;
signal r: icache_regs_type;
alias tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
alias address_tag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0)
is r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
signal ctag_address: std_logic_vector(address_tag'RANGE);
signal wrcachea: std_logic;
signal cmem_enable: std_logic;
signal cmem_wren: std_logic;
signal access_to_same_line: std_logic;
begin
ctag_address<=ctag(address_tag'HIGH downto address_tag'LOW);
tagmem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+2
)
port map (
clka => syscon.clk,
ena => tag_mem_enable,
addra => cache_addr_read(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS),--line,
doa => ctag,
clkb => syscon.clk,
enb => '1',
web => r.tag_mem_wen,
addrb => tag_mem_addr,
dib => tag_mem_data,
dob => open
);
cachemem: entity work.generic_dp_ram_1r1w
generic map (
address_bits => cache_addr_read'LENGTH,
data_bits => 32
)
port map (
clka => syscon.clk,
ena => cache_mem_enable,
addra => cache_addr_read,
doa => data,
clkb => syscon.clk,
enb => cmem_enable,
web => cmem_wren,
addrb => cache_addr_write,
dib => mwbi.dat,
dob => open
);
cmem_enable <= '1';
cmem_wren <= mwbi.ack;
valid_i <= ctag(ctag'HIGH);
process(r.state, r.flushcnt, tagen, exttag_save)
variable wrtag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
begin
if tagen='1' then
wrtag := exttag_save;
else
wrtag := tag_save;
end if;
if r.state=flushing then
tag_mem_data <= '0' & wrtag;
tag_mem_addr <= std_logic_vector(r.flushcnt);
else
tag_mem_data <= '1' & wrtag;
tag_mem_addr <= r.line_save;
end if;
end process;
process(ctag_address, address_tag, tag, tagen)
begin
if tagen='0' then
if ctag_address=address_tag then
tag_match<='1';
else
tag_match<='0';
end if;
else
if ctag_address=tag(ADDRESS_HIGH downto CACHE_MAX_BITS) then
tag_match<='1';
else
tag_match<='0';
end if;
end if;
end process;
cache_addr_write <= r.line_save & mwbi.tag(CACHE_LINE_SIZE_BITS-3 downto 0);
access_to_same_line<='1' when r.line_save = r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) and
r.tag_save = r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS) else '0';
process(r,strobe,enable,miss,syscon,line,line_offset,hit,flush,mwbi,valid_while_filling,abort)
variable ett: std_logic_vector(exttag_save'RANGE);
variable w: icache_regs_type;
variable data_valid: std_logic;
variable stall_input: std_logic;
begin
w:=r;
w.busy := '0';
w.cyc := '0';
-- w.stb := 'X';
w.tag_mem_wen := '0';
w.fill_success :='0';
w.flushcnt := (others => 'X');
data_valid := '0';
tag_mem_enable <= enable and strobe;
cache_mem_enable <= enable and strobe;
cache_addr_read <= line & line_offset;
case r.state is
when flushing =>
w.busy := '1';
w.flushcnt := r.flushcnt - 1;
w.tag_mem_wen := '1';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.iwfready := '0';
stall_input := '1';
if r.flushcnt=0 then
w.tag_mem_wen:='0';
--w.state := running;
if r.queued_address='1' and r.fault='1' then
w.state := filling;
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
end if;
when running =>
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.iwfready:='0';
stall_input := '0';
data_valid := hit;
w.stb := 'X';
if r.access_q='1' then
-- We had a cache access in last clock cycle.
if r.enable_q='1' then
if miss='1' and abort='0' then -- And it was a miss...
stall_input := '1';
data_valid := '0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.state := filling;
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.cyc := '1';
w.stb := '1';
w.busy := '1';
else
data_valid := '1';
end if;
end if;
end if;
if flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
-- TODO: check if this is correct...
stall_input:='1';
end if;
w.queued_address := '0';
if r.access_q='1' and data_valid='0' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
w.fault := '0';
when filling =>
stall_input := '1';
w.busy:= '1';
w.cyc := '1';
tag_mem_enable <= '1';
cache_mem_enable <= enable and strobe;
if mwbi.ack='1' then
w.iwfready := enable;
w.offcnt_write := r.offcnt_write - 1;
-- This will go to 0, but we check before and switch state
if r.offcnt_write=offcnt_zero then
w.tag_mem_wen := '1';
w.state := ending;
end if;
end if;
if mwbi.stall='0' then
w.offcnt := r.offcnt + 1;
-- this needed ??
if r.stbcount/=offcnt_zero then
w.stbcount := w.stbcount - 1;
else
w.stb := '0';
end if;
end if;
if true then
if r.iwfready='0' then
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
end if;
if enable='1' then
stall_input := not r.iwfready;
data_valid := r.iwfready;
if r.iwfready='1' and strobe='1' then
w.iwfready:='0';
end if;
if seq='0' and strobe='1' and stall_input='0' then
--stall_input := '1';
data_valid:='0';
w.fault :='1';
end if;
if r.access_q='1' and access_to_same_line='0' then
data_valid:='0';
stall_input:='1';
w.fault := '1';
end if;
end if;
if r.fault='1' then
stall_input:='1';
data_valid:='0';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if flush='1' then
w.fault:='1';
data_valid:='0';
stall_input:='1';
w.flush:='1';
end if;
if stall_input='0' then
if enable='1' and strobe='1' then
w.queued_address:='1';
else
w.queued_address:='0';
end if;
end if;
if abort='1' then
w.fault:='1';
end if;
end if; -- IWF
when ending =>
w.busy :='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
w.iwfready:='0';
tag_mem_enable <= '1';
cache_mem_enable <='1';
cache_addr_read <= r.save_addr(CACHE_MAX_BITS-1 downto 2);
stall_input := '1';
w.fault:='0';
if enable='1' then
w.fill_success := '1';
end if;
if r.queued_address='1' then--and r.fault='1' then
w.state := filling;
w.cyc := '1';
w.stb := '1';
w.busy := '1';
w.queued_address:='0';
w.wbaddr(31 downto CACHE_MAX_BITS) := r.save_addr(31 downto CACHE_MAX_BITS);
w.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2) := unsigned(r.save_addr(CACHE_LINE_SIZE_BITS-1 downto 2));
w.offcnt_write := (others => '1');
w.stbcount := (others => '1');
w.line_save := r.save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := r.save_addr(ADDRESS_HIGH downto CACHE_MAX_BITS);
else
w.state := running;
end if;
w.flush:='0';
if r.flush='1' then
w.state := flushing;
w.flushcnt := (others => '1');
w.tag_mem_wen := '1';
w.cyc :='0';
end if;
end case;
if strobe='1' and enable='1' then
if stall_input='0' then
w.save_addr := address;
w.access_q := '1';
if r.state=running then
w.line_save := address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
w.tag_save := address(ADDRESS_HIGH downto CACHE_MAX_BITS);
end if;
end if;
else
if stall_input='0' then
w.access_q := '0';
end if;
end if;
if abort='1' then
w.access_q:='0';
w.queued_address:='0';
end if;
w.enable_q := enable;
valid <= data_valid;
stall <= stall_input;
if syscon.rst='1' then
w.state := flushing;
w.busy := '1';
w.fill_success :='0';
w.flushcnt := (others => '1');
w.tag_mem_wen := '1'; -- this needed ??
w.cyc := '0';
w.stb := 'X';
w.wbaddr(31 downto CACHE_MAX_BITS) := (others => 'X');
w.offcnt := (others => 'X');
w.offcnt_write := (others => 'X');
w.access_q := '0';
w.enable_q := '0';
w.queued_address:='0';
w.iwfready:='0';
w.flush := '0';
w.fault := '0';
w.stbcount := (others => 'X');
w.line_save:= (others => 'X');
w.tag_save:= (others => 'X');
end if;
if rising_edge(syscon.clk) then
r <= w;
end if;
end process;
hit <= '1' when tag_match='1' and valid_i='1' else '0';
miss <= not hit;
mwbo.cyc <= r.cyc;
mwbo.stb <= r.stb;
mwbo.we <= '0';
mwbo.dat <= (others => 'X');
mwbo.bte <= BTE_BURST_16BEATWRAP;
mwbo.cti <= CTI_CYCLE_INCRADDR; -- BUg: we need to signal eof
mwbo.adr(31 downto CACHE_MAX_BITS) <= r.wbaddr(31 downto CACHE_MAX_BITS);
mwbo.adr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS) <= r.line_save;
mwbo.adr(CACHE_LINE_SIZE_BITS-1 downto 2) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.tag(CACHE_LINE_SIZE_BITS-3 downto 0) <= std_logic_vector(r.offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
mwbo.adr(1 downto 0) <= "00";
end behave;
| bsd-3-clause | 4504989863e17baa3c1db250bad4c7fa | 0.532859 | 3.254608 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_io_in.vhd | 1 | 6,150 | -------------------------------------------------------------------------------
--
-- The IN port controller.
--
-- $Id: t400_io_in.vhd,v 1.3 2006-05-27 19:14:18 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
entity t400_io_in is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_in_op_t;
en1_i : in std_logic;
-- Port Interface ---------------------------------------------------------
io_in_i : in dw_t;
in_o : out dw_t;
int_o : out boolean
);
end t400_io_in;
architecture rtl of t400_io_in is
constant idx_in3_c : natural := 2;
constant idx_in0_c : natural := 1;
constant idx_int_c : natural := 0;
type neg_edge_t is array (natural range 1 downto 0) of
std_logic_vector(2 downto 0);
signal neg_edge_q : neg_edge_t;
signal neg_edge_s : std_logic_vector(2 downto 0);
signal il_q : std_logic_vector(1 downto 0);
signal int_q,
int_icyc_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (ck_i, por_i)
variable neg_edge_v : std_logic_vector(2 downto 0);
begin
if por_i then
neg_edge_q <= (others => (others => '0'));
il_q <= (others => '0');
int_q <= false;
int_icyc_q <= false;
elsif ck_i'event and ck_i = '1' then
-- negative edge detector filp-flops ------------------------------------
neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
neg_edge_v(idx_int_c) := to_X01(io_in_i(1));
if in_en_i then
neg_edge_q(0) <= neg_edge_v;
neg_edge_q(1) <= neg_edge_q(0) or neg_edge_v;
end if;
-- IL latches -----------------------------------------------------------
if in_en_i then
if neg_edge_q(1)(idx_in3_c) = '1' and
((neg_edge_q(0)(idx_in3_c) or neg_edge_v(idx_in3_c)) = '0') then
il_q(1) <= '1';
end if;
if neg_edge_q(1)(idx_in0_c) = '1' and
((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
il_q(0) <= '1';
end if;
end if;
-- Interrupt trigger ----------------------------------------------------
if in_en_i then
if neg_edge_q(1)(idx_int_c) = '1' and
((neg_edge_q(0)(idx_int_c) or neg_edge_v(idx_int_c)) = '0') then
int_q <= true;
end if;
end if;
if icyc_en_i then
-- delay interrupt request until end of current instruction
-- this ensures that the interrupt is valid for a full instruction
-- (i.e. the next one)
int_icyc_q <= int_q;
end if;
if ck_en_i then
if op_i = IOIN_INIL then
il_q <= (others => '0');
end if;
if op_i = IOIN_INTACK then
int_q <= false;
int_icyc_q <= false;
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
in_o <= il_q(1) & "00" & il_q(0)
when op_i = IOIN_INIL else
io_in_i;
int_o <= int_icyc_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/23 01:13:28 arniml
-- + reset neg_edge flip-flops to '1'
-- -> after por, a 1-to-0 edge is required to trigger the latches initially
-- + use to_X01
--
-- Revision 1.1 2006/05/22 00:00:55 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | adc06b68fb1d57f0169a03cd70eaacf3 | 0.514309 | 3.766075 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixgx_hssi_atoms.vhd | 1 | 723,627 |
-- package for Boolean vector
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package hssi_pack is
TYPE boolean_vec IS ARRAY (0 to 3) of BOOLEAN;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- function to convert align_pattern to binary
function pattern_conversion (align_pattern : string) return std_logic_vector;
end hssi_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body hssi_pack is
function pattern_conversion
(
align_pattern : string
)
return std_logic_vector is
variable i : integer;
variable j : integer := 15;
variable bin_pat : std_logic_vector(15 downto 0) := (OTHERS => '0');
begin
for i in 1 to align_pattern'length loop
case align_pattern(i) is
when '0' => bin_pat(j) := '0';
when '1' => bin_pat(j) := '1';
when others => bin_pat(j) := '0';
end case;
j := j - 1;
end loop;
return (bin_pat);
end pattern_conversion;
end hssi_pack;
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
--synthesis_resources = lut 81 mux21 43
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_8b10b_decoder IS
PORT
(
clk : IN STD_LOGIC;
datain : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datainvalid : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
decdatavalid : OUT STD_LOGIC;
disperr : OUT STD_LOGIC;
disperrin : IN STD_LOGIC;
errdetect : OUT STD_LOGIC;
errdetectin : IN STD_LOGIC;
kout : OUT STD_LOGIC;
patterndetect : OUT STD_LOGIC;
patterndetectin : IN STD_LOGIC;
rderr : OUT STD_LOGIC;
reset : IN STD_LOGIC;
syncstatus : OUT STD_LOGIC;
syncstatusin : IN STD_LOGIC;
tenBdata : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
valid : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END stratixgx_8b10b_decoder;
ARCHITECTURE RTL OF stratixgx_8b10b_decoder IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL n0iOl43 : STD_LOGIC := '0';
SIGNAL n0iOl44 : STD_LOGIC := '0';
SIGNAL n0l0l39 : STD_LOGIC := '0';
SIGNAL n0l0l40 : STD_LOGIC := '0';
SIGNAL n0l1l41 : STD_LOGIC := '0';
SIGNAL n0l1l42 : STD_LOGIC := '0';
SIGNAL n0lii37 : STD_LOGIC := '0';
SIGNAL n0lii38 : STD_LOGIC := '0';
SIGNAL wire_n0lii38_w_lg_q151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0liO35 : STD_LOGIC := '0';
SIGNAL n0liO36 : STD_LOGIC := '0';
SIGNAL n0lll33 : STD_LOGIC := '0';
SIGNAL n0lll34 : STD_LOGIC := '0';
SIGNAL n0lOi31 : STD_LOGIC := '0';
SIGNAL n0lOi32 : STD_LOGIC := '0';
SIGNAL wire_n0lOi32_w_lg_q136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0lOO29 : STD_LOGIC := '0';
SIGNAL n0lOO30 : STD_LOGIC := '0';
SIGNAL n0O0l25 : STD_LOGIC := '0';
SIGNAL n0O0l26 : STD_LOGIC := '0';
SIGNAL n0O1l27 : STD_LOGIC := '0';
SIGNAL n0O1l28 : STD_LOGIC := '0';
SIGNAL n0Oil23 : STD_LOGIC := '0';
SIGNAL n0Oil24 : STD_LOGIC := '0';
SIGNAL n0Oli21 : STD_LOGIC := '0';
SIGNAL n0Oli22 : STD_LOGIC := '0';
SIGNAL n0OOi19 : STD_LOGIC := '0';
SIGNAL n0OOi20 : STD_LOGIC := '0';
SIGNAL n0OOO17 : STD_LOGIC := '0';
SIGNAL n0OOO18 : STD_LOGIC := '0';
SIGNAL ni00i5 : STD_LOGIC := '0';
SIGNAL ni00i6 : STD_LOGIC := '0';
SIGNAL ni0il3 : STD_LOGIC := '0';
SIGNAL ni0il4 : STD_LOGIC := '0';
SIGNAL ni0ll1 : STD_LOGIC := '0';
SIGNAL ni0ll2 : STD_LOGIC := '0';
SIGNAL ni10l13 : STD_LOGIC := '0';
SIGNAL ni10l14 : STD_LOGIC := '0';
SIGNAL ni11O15 : STD_LOGIC := '0';
SIGNAL ni11O16 : STD_LOGIC := '0';
SIGNAL ni1ii11 : STD_LOGIC := '0';
SIGNAL ni1ii12 : STD_LOGIC := '0';
SIGNAL ni1iO10 : STD_LOGIC := '0';
SIGNAL ni1iO9 : STD_LOGIC := '0';
SIGNAL ni1ll7 : STD_LOGIC := '0';
SIGNAL ni1ll8 : STD_LOGIC := '0';
SIGNAL n0O : STD_LOGIC := '0';
SIGNAL nii : STD_LOGIC := '0';
SIGNAL niO : STD_LOGIC := '0';
SIGNAL nlll : STD_LOGIC := '0';
SIGNAL nllO : STD_LOGIC := '0';
SIGNAL nlOi : STD_LOGIC := '0';
SIGNAL nlOl : STD_LOGIC := '0';
SIGNAL nlOO : STD_LOGIC := '0';
SIGNAL wire_nil_CLRN : STD_LOGIC;
SIGNAL n0i : STD_LOGIC := '0';
SIGNAL n0l : STD_LOGIC := '0';
SIGNAL n1i : STD_LOGIC := '0';
SIGNAL n1l : STD_LOGIC := '0';
SIGNAL n1O : STD_LOGIC := '0';
SIGNAL ni : STD_LOGIC := '0';
SIGNAL niii : STD_LOGIC := '0';
SIGNAL niil : STD_LOGIC := '0';
SIGNAL niiO : STD_LOGIC := '0';
SIGNAL nili : STD_LOGIC := '0';
SIGNAL nill : STD_LOGIC := '0';
SIGNAL nilO : STD_LOGIC := '0';
SIGNAL niOi : STD_LOGIC := '0';
SIGNAL niOl : STD_LOGIC := '0';
SIGNAL niOO : STD_LOGIC := '0';
SIGNAL nl0i : STD_LOGIC := '0';
SIGNAL nl0l : STD_LOGIC := '0';
SIGNAL nl0O : STD_LOGIC := '0';
SIGNAL nl1i : STD_LOGIC := '0';
SIGNAL nl1l : STD_LOGIC := '0';
SIGNAL nl1O : STD_LOGIC := '0';
SIGNAL nli : STD_LOGIC := '0';
SIGNAL nlii : STD_LOGIC := '0';
SIGNAL nlil : STD_LOGIC := '0';
SIGNAL nliO : STD_LOGIC := '0';
SIGNAL nll : STD_LOGIC := '0';
SIGNAL nlli : STD_LOGIC := '0';
SIGNAL nlO : STD_LOGIC := '0';
SIGNAL nO : STD_LOGIC := '0';
SIGNAL wire_nl_CLRN : STD_LOGIC;
SIGNAL wire_niO0i_dataout : STD_LOGIC;
SIGNAL wire_niO0l_dataout : STD_LOGIC;
SIGNAL wire_niO0O_dataout : STD_LOGIC;
SIGNAL wire_niO1l_dataout : STD_LOGIC;
SIGNAL wire_niO1O_dataout : STD_LOGIC;
SIGNAL wire_niOii_dataout : STD_LOGIC;
SIGNAL wire_niOil_dataout : STD_LOGIC;
SIGNAL wire_niOiO_dataout : STD_LOGIC;
SIGNAL wire_niOli_dataout : STD_LOGIC;
SIGNAL wire_niOll_dataout : STD_LOGIC;
SIGNAL wire_niOlO_dataout : STD_LOGIC;
SIGNAL wire_niOOi_dataout : STD_LOGIC;
SIGNAL wire_niOOl_dataout : STD_LOGIC;
SIGNAL wire_niOOO_dataout : STD_LOGIC;
SIGNAL wire_nl10i_dataout : STD_LOGIC;
SIGNAL wire_nl10l_dataout : STD_LOGIC;
SIGNAL wire_nl10O_dataout : STD_LOGIC;
SIGNAL wire_nl11i_dataout : STD_LOGIC;
SIGNAL wire_nl11l_dataout : STD_LOGIC;
SIGNAL wire_nl11O_dataout : STD_LOGIC;
SIGNAL wire_nl1il_dataout : STD_LOGIC;
SIGNAL wire_nl1iO_dataout : STD_LOGIC;
SIGNAL wire_nl1li_dataout : STD_LOGIC;
SIGNAL wire_nli0i_dataout : STD_LOGIC;
SIGNAL wire_nli0i_w_lg_w_lg_w_lg_dataout89w134w137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_w_lg_dataout82w152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_w_lg_dataout89w186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_w_lg_dataout89w144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_w_lg_dataout89w134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_dataout82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_dataout89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0i_w_lg_dataout165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0l_dataout : STD_LOGIC;
SIGNAL wire_nli0l_w_lg_dataout80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0O_dataout : STD_LOGIC;
SIGNAL wire_nli0O_w_lg_w_lg_dataout79w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0O_w_lg_w_lg_dataout79w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0O_w_lg_dataout176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0O_w_lg_dataout79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli0O_w_lg_dataout164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1l_dataout : STD_LOGIC;
SIGNAL wire_nli1l_w_lg_dataout109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O_dataout : STD_LOGIC;
SIGNAL wire_nli1O_w_lg_dataout138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O_w_lg_dataout153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O_w_lg_dataout187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O_w_lg_dataout145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O_w_lg_dataout88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlill_dataout : STD_LOGIC;
SIGNAL wire_nlilO_dataout : STD_LOGIC;
SIGNAL wire_nliOi_dataout : STD_LOGIC;
SIGNAL wire_nliOl_dataout : STD_LOGIC;
SIGNAL wire_nliOO_dataout : STD_LOGIC;
SIGNAL wire_nll0i_dataout : STD_LOGIC;
SIGNAL wire_nll0l_dataout : STD_LOGIC;
SIGNAL wire_nll0O_dataout : STD_LOGIC;
SIGNAL wire_nll1i_dataout : STD_LOGIC;
SIGNAL wire_nll1l_dataout : STD_LOGIC;
SIGNAL wire_nll1O_dataout : STD_LOGIC;
SIGNAL wire_nllii_dataout : STD_LOGIC;
SIGNAL wire_nllli_dataout : STD_LOGIC;
SIGNAL wire_nllli_w_lg_dataout63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nllll_dataout : STD_LOGIC;
SIGNAL wire_nllll_w_lg_dataout68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlllO_dataout : STD_LOGIC;
SIGNAL wire_nlllO_w_lg_w_lg_dataout61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlllO_w_lg_dataout69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlllO_w_lg_dataout61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_ni1Oi55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n0ilO174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_ni01O54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_ni01l56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0ill : STD_LOGIC;
SIGNAL n0ilO : STD_LOGIC;
SIGNAL n0iOi : STD_LOGIC;
SIGNAL n0l0i : STD_LOGIC;
SIGNAL n0l1i : STD_LOGIC;
SIGNAL n0O0i : STD_LOGIC;
SIGNAL n0Oii : STD_LOGIC;
SIGNAL n0OlO : STD_LOGIC;
SIGNAL ni01i : STD_LOGIC;
SIGNAL ni01l : STD_LOGIC;
SIGNAL ni01O : STD_LOGIC;
SIGNAL ni0ii : STD_LOGIC;
SIGNAL ni0iO : STD_LOGIC;
SIGNAL ni11l : STD_LOGIC;
SIGNAL ni1Oi : STD_LOGIC;
SIGNAL ni1Ol : STD_LOGIC;
SIGNAL ni1OO : STD_LOGIC;
BEGIN
wire_w_lg_ni1Oi55w(0) <= ni1Oi AND ni1OO;
wire_w_lg_n0ilO174w(0) <= NOT n0ilO;
wire_w_lg_ni01O54w(0) <= NOT ni01O;
wire_w_lg_reset2w(0) <= NOT reset;
wire_w_lg_ni01l56w(0) <= ni01l OR wire_w_lg_ni1Oi55w(0);
dataout <= ( nO & ni & nlO & nll & nli & niO & nii & n0O);
decdatavalid <= nl0i;
disperr <= nl0l;
errdetect <= nliO;
kout <= nllO;
n0ill <= wire_nli0O_w_lg_w_lg_dataout79w81w(0);
n0ilO <= (wire_nli0l_dataout AND wire_nli0i_dataout);
n0iOi <= ((wire_nli0l_w_lg_dataout80w(0) AND wire_nli0i_w_lg_dataout89w(0)) AND (n0iOl44 XOR n0iOl43));
n0l0i <= ((((wire_nli1O_w_lg_dataout88w(0) AND (wire_nli0i_w_lg_dataout89w(0) AND wire_nli0O_w_lg_dataout176w(0))) OR (wire_nli1O_w_lg_dataout88w(0) AND (wire_nli0i_w_lg_dataout89w(0) AND wire_nli0O_w_lg_w_lg_dataout79w177w(0)))) OR (wire_nli1O_w_lg_dataout88w(0) AND (wire_nli0i_dataout AND n0ill))) OR wire_nli1O_w_lg_dataout187w(0));
n0l1i <= ((((wire_nli1l_w_lg_dataout109w(0) AND ((((((((((wire_nli1O_w_lg_dataout88w(0) AND ((wire_nli0i_w_lg_dataout89w(0) AND (wire_nli0O_dataout AND wire_nli0l_dataout)) AND (n0Oli22 XOR n0Oli21))) AND (n0Oil24 XOR n0Oil23)) OR (wire_nli1O_w_lg_dataout88w(0) AND (wire_nli0i_dataout AND n0Oii))) OR (NOT (n0O0l26 XOR n0O0l25))) OR ((wire_nli1O_w_lg_dataout88w(0) AND (wire_nli0i_dataout AND n0O0i)) AND (n0O1l28 XOR n0O1l27))) OR (NOT (n0lOO30 XOR n0lOO29))) OR wire_nli1O_w_lg_dataout138w(0)) OR (NOT (n0lll34 XOR n0lll33))) OR (wire_nli1O_w_lg_dataout145w(0) AND (n0liO36 XOR n0liO35))) OR wire_nli1O_w_lg_dataout153w(0))) AND (n0l0l40 XOR n0l0l39)) OR ((wire_nli1l_dataout AND n0l0i) AND (n0l1l42 XOR n0l1l41))) AND wire_nli0i_w_lg_dataout165w(0));
n0O0i <= wire_nli0O_w_lg_w_lg_dataout79w177w(0);
n0Oii <= wire_nli0O_w_lg_dataout176w(0);
n0OlO <= (wire_nli1l_dataout AND (((wire_nli0O_dataout XOR wire_nli0l_dataout) XOR (NOT (n0OOO18 XOR n0OOO17))) AND ((wire_nli0i_dataout XOR wire_nli1O_dataout) XOR (NOT (n0OOi20 XOR n0OOi19)))));
ni01i <= ((NOT datain(5)) AND ni01l);
ni01l <= (wire_nli1l_dataout AND (wire_nli1O_dataout AND (wire_nli0i_w_lg_dataout82w(0) AND (ni10l14 XOR ni10l13))));
ni01O <= ((datain(6) XOR datain(7)) XOR (NOT (ni00i6 XOR ni00i5)));
ni0ii <= (wire_w_lg_ni01l56w(0) OR (NOT (ni1ll8 XOR ni1ll7)));
ni0iO <= '1';
ni11l <= (wire_nli1l_dataout AND (wire_nli1O_w_lg_dataout88w(0) AND ((wire_nli0i_w_lg_dataout89w(0) AND (wire_nli0O_dataout AND wire_nli0l_dataout)) AND (ni11O16 XOR ni11O15))));
ni1Oi <= (wire_nli1l_w_lg_dataout109w(0) AND n0l0i);
ni1Ol <= ((wire_nlllO_w_lg_w_lg_dataout61w62w(0) AND wire_nllli_w_lg_dataout63w(0)) AND (ni1iO10 XOR ni1iO9));
ni1OO <= ((wire_nlllO_w_lg_dataout69w(0) AND wire_nllli_w_lg_dataout63w(0)) AND (ni1ii12 XOR ni1ii11));
patterndetect <= nl0O;
rderr <= nlil;
syncstatus <= nlii;
tenBdata <= ( nl1i & niOO & niOl & niOi & nilO & nill & nili & niiO & niil & niii);
valid <= nlli;
xgmctrldet <= nlll;
xgmdataout <= ( n0l & n0i & n1O & n1l & n1i & nlOO & nlOl & nlOi);
xgmdatavalid <= nl1O;
xgmrunningdisp <= nl1l;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0iOl43 <= n0iOl44;
END IF;
if (now = 0 ns) then
n0iOl43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0iOl44 <= n0iOl43;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0l0l39 <= n0l0l40;
END IF;
if (now = 0 ns) then
n0l0l39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0l0l40 <= n0l0l39;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0l1l41 <= n0l1l42;
END IF;
if (now = 0 ns) then
n0l1l41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0l1l42 <= n0l1l41;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lii37 <= n0lii38;
END IF;
if (now = 0 ns) then
n0lii37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lii38 <= n0lii37;
END IF;
END PROCESS;
wire_n0lii38_w_lg_q151w(0) <= n0lii38 XOR n0lii37;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0liO35 <= n0liO36;
END IF;
if (now = 0 ns) then
n0liO35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0liO36 <= n0liO35;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lll33 <= n0lll34;
END IF;
if (now = 0 ns) then
n0lll33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lll34 <= n0lll33;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lOi31 <= n0lOi32;
END IF;
if (now = 0 ns) then
n0lOi31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lOi32 <= n0lOi31;
END IF;
END PROCESS;
wire_n0lOi32_w_lg_q136w(0) <= n0lOi32 XOR n0lOi31;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lOO29 <= n0lOO30;
END IF;
if (now = 0 ns) then
n0lOO29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0lOO30 <= n0lOO29;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0O0l25 <= n0O0l26;
END IF;
if (now = 0 ns) then
n0O0l25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0O0l26 <= n0O0l25;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0O1l27 <= n0O1l28;
END IF;
if (now = 0 ns) then
n0O1l27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0O1l28 <= n0O1l27;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0Oil23 <= n0Oil24;
END IF;
if (now = 0 ns) then
n0Oil23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0Oil24 <= n0Oil23;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0Oli21 <= n0Oli22;
END IF;
if (now = 0 ns) then
n0Oli21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0Oli22 <= n0Oli21;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0OOi19 <= n0OOi20;
END IF;
if (now = 0 ns) then
n0OOi19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0OOi20 <= n0OOi19;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0OOO17 <= n0OOO18;
END IF;
if (now = 0 ns) then
n0OOO17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN n0OOO18 <= n0OOO17;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni00i5 <= ni00i6;
END IF;
if (now = 0 ns) then
ni00i5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni00i6 <= ni00i5;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni0il3 <= ni0il4;
END IF;
if (now = 0 ns) then
ni0il3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni0il4 <= ni0il3;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni0ll1 <= ni0ll2;
END IF;
if (now = 0 ns) then
ni0ll1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni0ll2 <= ni0ll1;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni10l13 <= ni10l14;
END IF;
if (now = 0 ns) then
ni10l13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni10l14 <= ni10l13;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni11O15 <= ni11O16;
END IF;
if (now = 0 ns) then
ni11O15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni11O16 <= ni11O15;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1ii11 <= ni1ii12;
END IF;
if (now = 0 ns) then
ni1ii11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1ii12 <= ni1ii11;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1iO10 <= ni1iO9;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1iO9 <= ni1iO10;
END IF;
if (now = 0 ns) then
ni1iO9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1ll7 <= ni1ll8;
END IF;
if (now = 0 ns) then
ni1ll7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk = '1' AND clk'event) THEN ni1ll8 <= ni1ll7;
END IF;
END PROCESS;
PROCESS (clk, reset, wire_nil_CLRN)
BEGIN
IF (reset = '1') THEN
n0O <= '1';
nii <= '1';
niO <= '1';
nlll <= '1';
nllO <= '1';
nlOi <= '1';
nlOl <= '1';
nlOO <= '1';
ELSIF (wire_nil_CLRN = '0') THEN
n0O <= '0';
nii <= '0';
niO <= '0';
nlll <= '0';
nllO <= '0';
nlOi <= '0';
nlOl <= '0';
nlOO <= '0';
ELSIF (clk = '1' AND clk'event) THEN
n0O <= wire_niO0O_dataout;
nii <= wire_niO0l_dataout;
niO <= wire_niO0i_dataout;
nlll <= ni0ii;
nllO <= ni0ii;
nlOi <= wire_niO0O_dataout;
nlOl <= wire_niO0l_dataout;
nlOO <= wire_niO0i_dataout;
END IF;
if (now = 0 ns) then
n0O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nii <= '1' after 1 ps;
end if;
if (now = 0 ns) then
niO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlll <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nllO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOi <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOl <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOO <= '1' after 1 ps;
end if;
END PROCESS;
wire_nil_CLRN <= (ni0il4 XOR ni0il3);
PROCESS (clk, wire_nl_CLRN)
BEGIN
IF (wire_nl_CLRN = '0') THEN
n0i <= '0';
n0l <= '0';
n1i <= '0';
n1l <= '0';
n1O <= '0';
ni <= '0';
niii <= '0';
niil <= '0';
niiO <= '0';
nili <= '0';
nill <= '0';
nilO <= '0';
niOi <= '0';
niOl <= '0';
niOO <= '0';
nl0i <= '0';
nl0l <= '0';
nl0O <= '0';
nl1i <= '0';
nl1l <= '0';
nl1O <= '0';
nli <= '0';
nlii <= '0';
nlil <= '0';
nliO <= '0';
nll <= '0';
nlli <= '0';
nlO <= '0';
nO <= '0';
ELSIF (clk = '1' AND clk'event) THEN
n0i <= wire_nlilO_dataout;
n0l <= wire_nlill_dataout;
n1i <= wire_niO1O_dataout;
n1l <= wire_niO1l_dataout;
n1O <= wire_nliOi_dataout;
ni <= wire_nlilO_dataout;
niii <= datain(0);
niil <= datain(1);
niiO <= datain(2);
nili <= datain(3);
nill <= datain(4);
nilO <= datain(5);
niOi <= datain(6);
niOl <= datain(7);
niOO <= datain(8);
nl0i <= datainvalid;
nl0l <= disperrin;
nl0O <= patterndetectin;
nl1i <= datain(9);
nl1l <= disperrin;
nl1O <= datainvalid;
nli <= wire_niO1O_dataout;
nlii <= syncstatusin;
nlil <= disperrin;
nliO <= errdetectin;
nll <= wire_niO1l_dataout;
nlli <= datainvalid;
nlO <= wire_nliOi_dataout;
nO <= wire_nlill_dataout;
END IF;
END PROCESS;
wire_nl_CLRN <= ((ni0ll2 XOR ni0ll1) AND wire_w_lg_reset2w(0));
wire_niO0i_dataout <= wire_niOiO_dataout OR ni01l;
wire_niO0l_dataout <= wire_niOli_dataout AND NOT(ni01l);
wire_niO0O_dataout <= wire_niOll_dataout AND NOT(ni01l);
wire_niO1l_dataout <= wire_niOii_dataout OR ni01l;
wire_niO1O_dataout <= wire_niOil_dataout OR ni01l;
wire_niOii_dataout <= wire_niOlO_dataout OR ni11l;
wire_niOil_dataout <= wire_niOOi_dataout OR ni11l;
wire_niOiO_dataout <= wire_niOOl_dataout AND NOT(ni11l);
wire_niOli_dataout <= wire_niOOO_dataout AND NOT(ni11l);
wire_niOll_dataout <= wire_nl11i_dataout AND NOT(ni11l);
wire_niOlO_dataout <= wire_nl1il_dataout WHEN n0OlO = '1' ELSE wire_nl11l_dataout;
wire_niOOi_dataout <= wire_nl1iO_dataout WHEN n0OlO = '1' ELSE wire_nl11O_dataout;
wire_niOOl_dataout <= wire_nl1iO_dataout WHEN n0OlO = '1' ELSE wire_nl10i_dataout;
wire_niOOO_dataout <= wire_nl1iO_dataout WHEN n0OlO = '1' ELSE wire_nl10l_dataout;
wire_nl10i_dataout <= datain(2) WHEN n0l1i = '1' ELSE wire_nli0i_w_lg_dataout89w(0);
wire_nl10l_dataout <= datain(1) WHEN n0l1i = '1' ELSE wire_nli0l_w_lg_dataout80w(0);
wire_nl10O_dataout <= datain(0) WHEN n0l1i = '1' ELSE wire_nli0O_w_lg_dataout79w(0);
wire_nl11i_dataout <= wire_nl1iO_dataout WHEN n0OlO = '1' ELSE wire_nl10O_dataout;
wire_nl11l_dataout <= datain(4) WHEN n0l1i = '1' ELSE ni1Oi;
wire_nl11O_dataout <= datain(3) WHEN n0l1i = '1' ELSE wire_nli1O_w_lg_dataout88w(0);
wire_nl1il_dataout <= wire_nl1li_dataout AND NOT(n0iOi);
wire_nl1iO_dataout <= wire_w_lg_n0ilO174w(0) AND NOT(n0iOi);
wire_nl1li_dataout <= (NOT (wire_nli0l_dataout AND wire_nli0i_w_lg_dataout89w(0))) OR n0ilO;
wire_nli0i_dataout <= datain(2) WHEN datain(5) = '1' ELSE (NOT datain(2));
wire_nli0i_w_lg_w_lg_w_lg_dataout89w134w137w(0) <= wire_nli0i_w_lg_w_lg_dataout89w134w(0) AND wire_n0lOi32_w_lg_q136w(0);
wire_nli0i_w_lg_w_lg_dataout82w152w(0) <= wire_nli0i_w_lg_dataout82w(0) AND wire_n0lii38_w_lg_q151w(0);
wire_nli0i_w_lg_w_lg_dataout89w186w(0) <= wire_nli0i_w_lg_dataout89w(0) AND n0ill;
wire_nli0i_w_lg_w_lg_dataout89w144w(0) <= wire_nli0i_w_lg_dataout89w(0) AND n0O0i;
wire_nli0i_w_lg_w_lg_dataout89w134w(0) <= wire_nli0i_w_lg_dataout89w(0) AND n0Oii;
wire_nli0i_w_lg_dataout82w(0) <= wire_nli0i_dataout AND wire_nli0O_w_lg_w_lg_dataout79w81w(0);
wire_nli0i_w_lg_dataout89w(0) <= NOT wire_nli0i_dataout;
wire_nli0i_w_lg_dataout165w(0) <= wire_nli0i_dataout OR wire_nli0O_w_lg_dataout164w(0);
wire_nli0l_dataout <= datain(1) WHEN datain(5) = '1' ELSE (NOT datain(1));
wire_nli0l_w_lg_dataout80w(0) <= NOT wire_nli0l_dataout;
wire_nli0O_dataout <= datain(0) WHEN datain(5) = '1' ELSE (NOT datain(0));
wire_nli0O_w_lg_w_lg_dataout79w81w(0) <= wire_nli0O_w_lg_dataout79w(0) AND wire_nli0l_w_lg_dataout80w(0);
wire_nli0O_w_lg_w_lg_dataout79w177w(0) <= wire_nli0O_w_lg_dataout79w(0) AND wire_nli0l_dataout;
wire_nli0O_w_lg_dataout176w(0) <= wire_nli0O_dataout AND wire_nli0l_w_lg_dataout80w(0);
wire_nli0O_w_lg_dataout79w(0) <= NOT wire_nli0O_dataout;
wire_nli0O_w_lg_dataout164w(0) <= wire_nli0O_dataout OR wire_nli0l_dataout;
wire_nli1l_dataout <= datain(4) WHEN datain(5) = '1' ELSE (NOT datain(4));
wire_nli1l_w_lg_dataout109w(0) <= NOT wire_nli1l_dataout;
wire_nli1O_dataout <= datain(3) WHEN datain(5) = '1' ELSE (NOT datain(3));
wire_nli1O_w_lg_dataout138w(0) <= wire_nli1O_dataout AND wire_nli0i_w_lg_w_lg_w_lg_dataout89w134w137w(0);
wire_nli1O_w_lg_dataout153w(0) <= wire_nli1O_dataout AND wire_nli0i_w_lg_w_lg_dataout82w152w(0);
wire_nli1O_w_lg_dataout187w(0) <= wire_nli1O_dataout AND wire_nli0i_w_lg_w_lg_dataout89w186w(0);
wire_nli1O_w_lg_dataout145w(0) <= wire_nli1O_dataout AND wire_nli0i_w_lg_w_lg_dataout89w144w(0);
wire_nli1O_w_lg_dataout88w(0) <= NOT wire_nli1O_dataout;
wire_nlill_dataout <= wire_nliOl_dataout AND NOT(ni1Ol);
wire_nlilO_dataout <= wire_nliOO_dataout AND NOT(ni1Ol);
wire_nliOi_dataout <= wire_nll1i_dataout AND NOT(ni1Ol);
wire_nliOl_dataout <= wire_nll1l_dataout OR ni1OO;
wire_nliOO_dataout <= wire_nll1O_dataout OR ni1OO;
wire_nll0i_dataout <= wire_nlllO_dataout WHEN wire_w_lg_ni01O54w(0) = '1' ELSE wire_nllii_dataout;
wire_nll0l_dataout <= (NOT datain(8)) WHEN ni01i = '1' ELSE datain(8);
wire_nll0O_dataout <= (NOT datain(7)) WHEN ni01i = '1' ELSE datain(7);
wire_nll1i_dataout <= wire_nll0i_dataout OR ni1OO;
wire_nll1l_dataout <= wire_nllli_dataout WHEN wire_w_lg_ni01O54w(0) = '1' ELSE wire_nll0l_dataout;
wire_nll1O_dataout <= wire_nllll_dataout WHEN wire_w_lg_ni01O54w(0) = '1' ELSE wire_nll0O_dataout;
wire_nllii_dataout <= (NOT datain(6)) WHEN ni01i = '1' ELSE datain(6);
wire_nllli_dataout <= (NOT datain(8)) WHEN datain(9) = '1' ELSE datain(8);
wire_nllli_w_lg_dataout63w(0) <= NOT wire_nllli_dataout;
wire_nllll_dataout <= (NOT datain(7)) WHEN datain(9) = '1' ELSE datain(7);
wire_nllll_w_lg_dataout68w(0) <= NOT wire_nllll_dataout;
wire_nlllO_dataout <= (NOT datain(6)) WHEN datain(9) = '1' ELSE datain(6);
wire_nlllO_w_lg_w_lg_dataout61w62w(0) <= wire_nlllO_w_lg_dataout61w(0) AND wire_nllll_dataout;
wire_nlllO_w_lg_dataout69w(0) <= wire_nlllO_dataout AND wire_nllll_w_lg_dataout68w(0);
wire_nlllO_w_lg_dataout61w(0) <= NOT wire_nlllO_dataout;
END RTL; --stratixgx_8b10b_decoder
--synopsys translate_on
--VALID FILE
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_COMP_FIFO_CORE
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY ieee, stratixgx_gxb,std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixgx_comp_fifo_core IS
GENERIC (
use_rate_match_fifo : string := "true";
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : string := "true";
channel_num : integer := 0
);
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
underflow : IN std_logic;
overflow : IN std_logic;
errdetectin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
disablefifowrin : IN std_logic;
disablefifordin : IN std_logic;
re : IN std_logic;
we : IN std_logic;
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
syncstatusin : IN std_logic;
disperr : OUT std_logic;
alignstatus : IN std_logic;
fifordin : IN std_logic;
fifordout : OUT std_logic;
decsync : OUT std_logic;
fifocntlt5 : OUT std_logic;
fifocntgt9 : OUT std_logic;
done : OUT std_logic;
fifoalmostful : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostempty : OUT std_logic;
fifoempty : OUT std_logic;
alignsyncstatus : OUT std_logic;
smenable : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
codevalid : OUT std_logic;
errdetectout : OUT std_logic;
patterndetect : OUT std_logic;
syncstatus : OUT std_logic);
END stratixgx_comp_fifo_core;
ARCHITECTURE arch_stratixgx_comp_fifo_core OF stratixgx_comp_fifo_core IS
SIGNAL ge_xaui_sel : std_logic;
SIGNAL decsync_1 : std_logic;
SIGNAL fifo_cnt_lt_8 : std_logic;
SIGNAL fifo_cnt_lt_9 : std_logic;
SIGNAL fifo_cnt_lt_7 : std_logic;
SIGNAL fifo_cnt_lt_12 : std_logic;
SIGNAL fifo_cnt_lt_4 : std_logic;
SIGNAL fifo_cnt_gt_10 : std_logic;
SIGNAL fifo_cnt_gt_8 : std_logic;
SIGNAL fifo_cnt_gt_13 : std_logic;
SIGNAL fifo_cnt_gt_5 : std_logic;
SIGNAL fifo_cnt_gt_6 : std_logic;
SIGNAL almostfull_1 : std_logic;
SIGNAL almostfull_sync : std_logic;
SIGNAL almostempty_1 : std_logic;
SIGNAL almostempty_sync : std_logic;
SIGNAL full_1 : std_logic;
SIGNAL full_sync : std_logic;
SIGNAL empty_1 : std_logic;
SIGNAL empty_sync : std_logic;
SIGNAL rdenable_sync_1 : std_logic;
SIGNAL rdenable_sync : std_logic;
SIGNAL write_enable_sync : std_logic;
SIGNAL write_enable_sync_1 : std_logic;
SIGNAL fifo_dec_dly : std_logic;
SIGNAL count : std_logic_vector(3 DOWNTO 0);
SIGNAL count_read : std_logic_vector(1 DOWNTO 0);
SIGNAL comp_write_d : std_logic;
SIGNAL comp_write_pre : std_logic;
SIGNAL comp_write : std_logic;
SIGNAL write_detect_d : std_logic;
SIGNAL write_detect_pre : std_logic;
SIGNAL write_detect : std_logic;
SIGNAL comp_read_d : std_logic;
SIGNAL comp_read : std_logic;
SIGNAL detect_read_d : std_logic;
SIGNAL detect_read : std_logic;
SIGNAL comp_read_ext : std_logic;
SIGNAL read_eco : std_logic;
SIGNAL read_eco_dly : std_logic;
SIGNAL reset_fifo_dec : std_logic;
SIGNAL read_sync_int_1 : std_logic;
SIGNAL read_sync_int : std_logic;
SIGNAL read_sync : std_logic;
SIGNAL fifo_dec : std_logic;
SIGNAL done_write : std_logic;
SIGNAL done_read : std_logic;
SIGNAL underflow_sync_1 : std_logic;
SIGNAL underflow_sync : std_logic;
SIGNAL done_read_sync_1 : std_logic;
SIGNAL done_read_sync : std_logic;
SIGNAL alignsyncstatus_sync : std_logic;
SIGNAL alignstatus_sync_1 : std_logic;
SIGNAL alignstatus_sync : std_logic;
SIGNAL alignstatus_dly : std_logic;
SIGNAL re_dly : std_logic;
SIGNAL syncstatus_sync_1 : std_logic;
SIGNAL syncstatus_sync : std_logic;
SIGNAL write_ptr : integer := 0 ;
SIGNAL read_ptr1 : integer := 0 ;
SIGNAL read_ptr2 : integer := 0 ;
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL k : integer;
SIGNAL fifo : std_logic_vector(14 * 12 - 1 DOWNTO 0);
SIGNAL fifo_errdetectin : std_logic;
SIGNAL fifo_errdetectin_dly : std_logic;
SIGNAL fifo_disperrin : std_logic;
SIGNAL fifo_disperrin_dly : std_logic;
SIGNAL fifo_patterndetectin : std_logic;
SIGNAL fifo_patterndetectin_dly : std_logic;
SIGNAL fifo_syncstatusin : std_logic;
SIGNAL fifo_syncstatusin_dly : std_logic;
SIGNAL fifo_data_in : std_logic_vector(10 DOWNTO 0);
SIGNAL fifo_data_in_dly : std_logic_vector(10 DOWNTO 0);
SIGNAL comp_pat1 : std_logic_vector(11 DOWNTO 0);
SIGNAL comp_pat2 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_data_in_pre : std_logic_vector(12 DOWNTO 0);
SIGNAL fifo_data_out1_sync : std_logic_vector(13 DOWNTO 0);
SIGNAL fifo_data_out1_sync_dly : std_logic_vector(13 DOWNTO 0);
SIGNAL fifo_data_out1_sync_valid: std_logic;
SIGNAL fifo_data_out2_sync : std_logic_vector(13 DOWNTO 0);
SIGNAL fifo_data_out1_tmp : std_logic_vector(13 DOWNTO 0);
SIGNAL fifo_data_out2_tmp : std_logic_vector(12 DOWNTO 0);
SIGNAL fifo_data_out1 : std_logic_vector(13 DOWNTO 0);
SIGNAL fifo_data_out2 : std_logic_vector(13 DOWNTO 0);
SIGNAL genericfifo_sync_clk2_1 : std_logic;
SIGNAL genericfifo_sync_clk2 : std_logic;
SIGNAL genericfifo_sync_clk1_1 : std_logic;
SIGNAL genericfifo_sync_clk1 : std_logic;
SIGNAL onechannel : std_logic;
SIGNAL deskewenable : std_logic;
SIGNAL matchenable : std_logic;
SIGNAL menable : std_logic;
SIGNAL genericfifo : std_logic;
SIGNAL globalenable : std_logic;
SIGNAL fifordout_tmp1 : std_logic;
SIGNAL fifoalmostful_tmp2 : std_logic;
SIGNAL fifofull_tmp3 : std_logic;
SIGNAL fifoalmostempty_tmp4 : std_logic;
SIGNAL fifoempty_tmp5 : std_logic;
SIGNAL decsync_tmp6 : std_logic;
SIGNAL fifocntlt5_tmp7 : std_logic;
SIGNAL fifocntgt9_tmp8 : std_logic;
SIGNAL done_tmp9 : std_logic;
SIGNAL alignsyncstatus_tmp10 : std_logic;
SIGNAL smenable_tmp11 : std_logic;
SIGNAL disablefifordout_tmp12 : std_logic;
SIGNAL disablefifowrout_tmp13 : std_logic;
SIGNAL dataout_tmp14 : std_logic_vector(9 DOWNTO 0);
SIGNAL codevalid_tmp15 : std_logic;
SIGNAL errdetectout_tmp16 : std_logic;
SIGNAL syncstatus_tmp17 : std_logic;
SIGNAL patterndetect_tmp18 : std_logic;
SIGNAL disperr_tmp19 : std_logic;
SIGNAL count_less3_tmp : std_logic;
SIGNAL count_2_tmp : std_logic;
SIGNAL count_read_tmp : std_logic;
SIGNAL writeclk_dly : std_logic;
SIGNAL write_done : std_logic := '0';
BEGIN
fifordout <= fifordout_tmp1;
fifoalmostful <= fifoalmostful_tmp2;
fifofull <= fifofull_tmp3;
fifoalmostempty <= fifoalmostempty_tmp4;
fifoempty <= fifoempty_tmp5;
decsync <= decsync_tmp6;
fifocntlt5 <= fifocntlt5_tmp7;
fifocntgt9 <= fifocntgt9_tmp8;
done <= done_tmp9;
alignsyncstatus <= alignsyncstatus_tmp10;
smenable <= smenable_tmp11;
disablefifordout <= disablefifordout_tmp12;
disablefifowrout <= disablefifowrout_tmp13;
dataout <= dataout_tmp14;
codevalid <= codevalid_tmp15;
errdetectout <= errdetectout_tmp16;
syncstatus <= syncstatus_tmp17;
patterndetect <= patterndetect_tmp18;
disperr <= disperr_tmp19;
onechannel <= '1' WHEN (channel_num = 0) ELSE '0' ;
deskewenable <= '1' WHEN (use_channel_align = "true") ELSE '0' ;
matchenable <= '1' WHEN (use_rate_match_fifo = "true") ELSE '0' ;
menable <= matchenable AND NOT deskewenable ;
genericfifo <= '1' WHEN (rate_matching_fifo_mode = "none") ELSE '0' ;
globalenable <= matchenable AND deskewenable ;
ge_xaui_sel <= '1' WHEN (rate_matching_fifo_mode = "gige") ELSE '0' ;
PROCESS (writeclk)
BEGIN
writeclk_dly <= writeclk;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
comp_write_pre <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF ((alignsyncstatus_tmp10 AND (write_detect OR NOT ge_xaui_sel)) = '1') THEN
comp_write_pre <= comp_write_d;
ELSE
comp_write_pre <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
write_detect_pre <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF ((alignsyncstatus_tmp10 AND ge_xaui_sel) = '1') THEN
write_detect_pre <= write_detect_d;
ELSE
write_detect_pre <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
comp_read <= '0';
comp_read_ext <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
comp_read_ext <= (underflow_sync AND comp_read) AND ge_xaui_sel;
IF ((alignsyncstatus_sync AND (detect_read OR NOT ge_xaui_sel)) = '1') THEN
comp_read <= (comp_read_d AND NOT fifo_data_out2_sync(10)) AND NOT fifo_data_out2_sync(12);
ELSE
comp_read <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
detect_read <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF ((alignsyncstatus_sync AND ge_xaui_sel) = '1') THEN
detect_read <= (detect_read_d AND NOT fifo_data_out2_sync(10)) AND NOT fifo_data_out2_sync(12);
ELSE
detect_read <= '0';
END IF;
END IF;
END PROCESS;
fifo_cnt_lt_4 <= '1' when (count <4) else '0';
fifocntlt5_tmp7 <= '1' when (count < 5) else '0';
fifo_cnt_lt_7 <= '1' when (count < 7) else '0';
fifo_cnt_lt_8 <= '1' when (count < 8) else '0'; -- added in REV-C
fifo_cnt_lt_9 <= '1' when (count < 9) else '0';
fifo_cnt_lt_12 <= '1' when (count < 12) else '0';
fifo_cnt_gt_5 <= '1' when (count > 5) else '0';
fifo_cnt_gt_6 <= '1' when (count > 6) else '0'; -- added in REV-C
fifo_cnt_gt_8 <= '1' when (count > 8) else '0';
fifocntgt9_tmp8 <= '1' when (count > 9) else '0';
fifo_cnt_gt_10 <= '1' when (count > 10) else '0';
fifo_cnt_gt_13 <= '1' when (count > 13) else '0';
disablefifowrout_tmp13 <= disablefifowrin WHEN (globalenable AND NOT onechannel) = '1' ELSE ((overflow AND comp_write) AND NOT done_write) ;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
count <= "0000";
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF (genericfifo_sync_clk1 = '1') THEN
IF ((write_enable_sync AND NOT decsync_tmp6) = '1') THEN
count <= count + "0001";
ELSE
IF ((write_enable_sync AND decsync_tmp6) = '1') THEN
count <= count - "0010";
ELSE
IF ((NOT write_enable_sync AND decsync_tmp6) = '1') THEN
count <= count - "0011";
ELSE
count <= count;
END IF;
END IF;
END IF;
ELSE
IF (NOT alignsyncstatus_tmp10 = '1') THEN
count <= "0000";
ELSE
IF ((NOT decsync_tmp6 AND NOT disablefifowrout_tmp13) = '1') THEN
count <= count + "0001";
ELSE
IF ((decsync_tmp6 AND NOT disablefifowrout_tmp13) = '1') THEN
count <= count - "0010";
ELSE
IF (((NOT ge_xaui_sel AND decsync_tmp6) AND disablefifowrout_tmp13) = '1') THEN
count <= count - "0011";
ELSE
IF (((ge_xaui_sel AND decsync_tmp6) AND disablefifowrout_tmp13) = '1') THEN
count <= count - "0100";
ELSE
IF (((ge_xaui_sel AND NOT decsync_tmp6) AND disablefifowrout_tmp13) = '1') THEN
count <= count - "0001";
ELSE
count <= count;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
done_write <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
done_write <= overflow AND comp_write;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
almostfull_1 <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF (almostfull_1 = '1') THEN
almostfull_1 <= NOT fifo_cnt_lt_8;
ELSE
almostfull_1 <= fifocntgt9_tmp8;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
almostempty_1 <= '1';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF (almostempty_1 = '1') THEN
almostempty_1 <= NOT fifo_cnt_gt_6;
ELSE
almostempty_1 <= fifocntlt5_tmp7;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
full_1 <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF (full_1 = '1') THEN
full_1 <= NOT fifo_cnt_lt_12;
ELSE
full_1 <= fifo_cnt_gt_13;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
empty_1 <= '1';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF (empty_1 = '1') THEN
empty_1 <= NOT fifo_cnt_gt_5;
ELSE
empty_1 <= fifo_cnt_lt_4;
END IF;
END IF;
END PROCESS;
read_sync <= fifordin WHEN (globalenable AND NOT onechannel) = '1' ELSE fifordout_tmp1 ;
fifordout_tmp1 <= read_sync_int ;
count_less3_tmp <= '1' when (count <= 2) else '0';
count_2_tmp <= '1' when (count = 2) else '0';
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
read_eco <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF ((read_eco AND count_less3_tmp) = '1') THEN
read_eco <= '0';
ELSE
IF ((NOT read_eco AND count_2_tmp) = '1') THEN
read_eco <= '1';
END IF;
END IF;
END IF;
END PROCESS;
alignstatus_dly <= alignstatus after 1 ps;
read_eco_dly <= read_eco after 1 ps;
re_dly <= re after 1 ps;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
read_sync_int_1 <= '0';
read_sync_int <= '0';
underflow_sync_1 <= '0';
underflow_sync <= '0';
alignstatus_sync_1 <= '0';
alignstatus_sync <= '0';
syncstatus_sync_1 <= '0';
syncstatus_sync <= '0';
rdenable_sync_1 <= '0';
rdenable_sync <= '0';
fifo_data_out1_sync_valid <= '0';
fifo_dec_dly <= '0';
almostfull_sync <= '0';
almostempty_sync <= '1';
full_sync <= '0';
empty_sync <= '1';
fifoalmostful_tmp2 <= '0';
fifoalmostempty_tmp4 <= '1';
fifofull_tmp3 <= '0';
fifoempty_tmp5 <= '1';
genericfifo_sync_clk2_1 <= '0';
genericfifo_sync_clk2 <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
read_sync_int_1 <= read_eco_dly AND NOT genericfifo_sync_clk2;
read_sync_int <= read_sync_int_1;
underflow_sync_1 <= underflow;
underflow_sync <= underflow_sync_1;
alignstatus_sync_1 <= alignstatus_dly;
alignstatus_sync <= alignstatus_sync_1;
syncstatus_sync_1 <= syncstatusin;
syncstatus_sync <= syncstatus_sync_1;
rdenable_sync_1 <= re_dly AND genericfifo;
rdenable_sync <= rdenable_sync_1;
fifo_data_out1_sync_valid <= ((NOT genericfifo_sync_clk2 AND alignsyncstatus_sync) AND read_sync) OR (genericfifo_sync_clk2 AND rdenable_sync);
fifo_dec_dly <= fifo_dec;
almostfull_sync <= almostfull_1;
almostempty_sync <= almostempty_1;
full_sync <= full_1;
empty_sync <= empty_1;
fifoalmostful_tmp2 <= almostfull_sync;
fifoalmostempty_tmp4 <= almostempty_sync;
fifofull_tmp3 <= full_sync;
fifoempty_tmp5 <= empty_sync;
genericfifo_sync_clk2_1 <= genericfifo;
genericfifo_sync_clk2 <= genericfifo_sync_clk2_1;
END IF;
END PROCESS;
disablefifordout_tmp12 <= disablefifordin WHEN (globalenable AND NOT onechannel) = '1' ELSE ((underflow_sync AND (comp_read OR comp_read_ext)) AND NOT done_read) ;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
count_read <= "00";
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF ((NOT alignsyncstatus_sync AND NOT genericfifo_sync_clk2) = '1') THEN
count_read <= "00";
ELSE
IF (((read_sync AND NOT disablefifordout_tmp12) OR rdenable_sync) = '1') THEN
IF (count_read = 2) THEN
count_read <= "00";
ELSE
count_read <= count_read + "01";
END IF;
ELSE
count_read <= count_read;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
done_read <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF ((underflow_sync AND ((comp_read AND NOT ge_xaui_sel) OR (comp_read_ext AND ge_xaui_sel))) = '1') THEN
done_read <= '1';
ELSE
IF (NOT underflow_sync = '1') THEN
done_read <= '0';
ELSE
done_read <= done_read;
END IF;
END IF;
END IF;
END PROCESS;
reset_fifo_dec <= reset OR NOT (NOT fifo_dec_dly OR readclk) ;
-- count_read_tmp <= '1' when (count_read = 2) else '0';
count_read_tmp <= '1' when (count_read = 1) else '0';
PROCESS (reset_fifo_dec, readclk)
BEGIN
IF (reset_fifo_dec = '1') THEN
fifo_dec <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF ((count_read_tmp AND ((NOT disablefifordout_tmp12 AND NOT genericfifo_sync_clk2) OR (rdenable_sync AND genericfifo_sync_clk2))) = '1') THEN
fifo_dec <= '1';
ELSE
fifo_dec <= fifo_dec;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
decsync_1 <= '0';
decsync_tmp6 <= '0';
done_read_sync_1 <= '0';
done_read_sync <= '0';
write_enable_sync_1 <= '0';
write_enable_sync <= '0';
genericfifo_sync_clk1_1 <= '0';
genericfifo_sync_clk1 <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
decsync_1 <= fifo_dec;
decsync_tmp6 <= decsync_1 AND NOT decsync_tmp6;
done_read_sync_1 <= done_read;
done_read_sync <= done_read_sync_1;
write_enable_sync_1 <= we AND genericfifo;
write_enable_sync <= write_enable_sync_1;
genericfifo_sync_clk1_1 <= genericfifo;
genericfifo_sync_clk1 <= genericfifo_sync_clk1_1;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') then
write_ptr <= 0;
write_done <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
IF ((NOT alignsyncstatus_tmp10 AND NOT genericfifo_sync_clk1) = '1') THEN
write_ptr <= 0;
ELSE
IF (((write_enable_sync AND genericfifo_sync_clk1) OR (NOT disablefifowrout_tmp13 AND NOT genericfifo_sync_clk1)) = '1') THEN
IF (write_ptr /= 11) THEN
write_ptr <= write_ptr + 1;
ELSE
write_ptr <= 0;
END IF;
ELSE
IF (((disablefifowrout_tmp13 AND ge_xaui_sel) AND NOT genericfifo_sync_clk1) = '1') THEN
IF (write_ptr /= 0) THEN
write_ptr <= write_ptr - 1;
ELSE
write_ptr <= 11;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
read_ptr1 <= 0;
read_ptr2 <= 1;
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF ((NOT alignsyncstatus_sync AND NOT genericfifo_sync_clk2) = '1') THEN
read_ptr1 <= 0;
read_ptr2 <= 1;
ELSE
IF ((((read_sync AND NOT disablefifordout_tmp12) AND NOT genericfifo_sync_clk2) OR (rdenable_sync AND genericfifo_sync_clk2)) = '1') THEN
IF (read_ptr1 /= 11) THEN
read_ptr1 <= read_ptr1 + 1;
ELSE
read_ptr1 <= 0;
END IF;
IF (read_ptr2 /= 11) THEN
read_ptr2 <= read_ptr2 + 1;
ELSE
read_ptr2 <= 0;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(fifo_data_in)
BEGIN
fifo_data_in_dly <= fifo_data_in;
END PROCESS;
PROCESS(fifo_errdetectin, fifo_disperrin, fifo_patterndetectin, fifo_syncstatusin)
BEGIN
fifo_errdetectin_dly <= fifo_errdetectin;
fifo_disperrin_dly <= fifo_disperrin;
fifo_patterndetectin_dly <= fifo_patterndetectin;
fifo_syncstatusin_dly <= fifo_syncstatusin;
END PROCESS;
PROCESS(write_ptr, fifo_data_in_dly, fifo_errdetectin_dly, fifo_syncstatusin_dly, fifo_disperrin_dly, fifo_patterndetectin_dly, reset)
VARIABLE fifo_tmp : std_logic_vector(14 * 12 - 1 DOWNTO 0);
BEGIN
IF (reset = '1') THEN
FOR i IN 0 TO (168 - 1) LOOP
fifo_tmp(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (10 - 1) LOOP
fifo_tmp(write_ptr * 14 + i) := fifo_data_in_dly(i);
END LOOP;
fifo_tmp(write_ptr * 14 + 10) := fifo_errdetectin_dly;
fifo_tmp(write_ptr * 14 + 11) := fifo_syncstatusin_dly;
fifo_tmp(write_ptr * 14 + 12) := fifo_disperrin_dly;
fifo_tmp(write_ptr * 14 + 13) := fifo_patterndetectin_dly;
END IF;
fifo <= fifo_tmp;
END PROCESS;
PROCESS (writeclk_dly, reset, read_ptr1, read_ptr2)
VARIABLE fifo_data_out1_tmp_tmp21 : std_logic_vector(13 DOWNTO 0);
VARIABLE fifo_data_out2_tmp_tmp22 : std_logic_vector(12 DOWNTO 0);
BEGIN
IF ((writeclk_dly = '1') OR read_ptr1'event OR read_ptr2'event) THEN
FOR j IN 0 TO (14 - 1) LOOP
fifo_data_out1_tmp_tmp21(j) := fifo(read_ptr1 * 14 + j);
END LOOP;
FOR k IN 0 TO (13 - 1) LOOP
fifo_data_out2_tmp_tmp22(k) := fifo(read_ptr2 * 14 + k);
END LOOP;
END IF;
fifo_data_out1_tmp <= fifo_data_out1_tmp_tmp21;
fifo_data_out2_tmp <= fifo_data_out2_tmp_tmp22;
END PROCESS;
fifo_data_out1 <= fifo_data_out1_tmp after 1 ps;
fifo_data_out2 <= '0' & fifo_data_out2_tmp after 1 ps;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
fifo_data_out1_sync <= "00000000000000";
fifo_data_out1_sync_dly <= "00000000000000";
fifo_data_out2_sync <= "00000000000000";
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF (ge_xaui_sel = '1') THEN
fifo_data_out1_sync_dly <= fifo_data_out1_sync;
ELSE
fifo_data_out1_sync_dly <= "00000000000000";
END IF;
IF (NOT disablefifordout_tmp12 = '1') THEN
fifo_data_out1_sync <= fifo_data_out1;
fifo_data_out2_sync <= fifo_data_out2;
ELSE
IF (ge_xaui_sel = '1') THEN
fifo_data_out1_sync <= fifo_data_out1_sync_dly;
END IF;
END IF;
END IF;
END PROCESS;
done_tmp9 <= done_write OR done_read_sync ;
smenable_tmp11 <= '1' WHEN ((menable OR (globalenable AND onechannel)) AND NOT genericfifo_sync_clk1) = '1' ELSE '0' ;
comp_pat1 <= "001010110110" WHEN (ge_xaui_sel) = '1' ELSE "000010111100" ;
comp_pat2 <= "001101000011" WHEN (ge_xaui_sel) = '0' ELSE "001010001010" WHEN (for_engineering_sample_device) = "true" ELSE "001010001001";
comp_write_d <= '1' WHEN (fifo_data_in_pre(9 DOWNTO 0) = CONV_INTEGER(comp_pat1)) OR (fifo_data_in_pre(9 DOWNTO 0) = CONV_INTEGER(comp_pat2)) ELSE '0' ;
comp_read_d <= '1' WHEN (fifo_data_out2_sync(9 DOWNTO 0) = CONV_INTEGER(comp_pat1)) OR (fifo_data_out2_sync(9 DOWNTO 0) = CONV_INTEGER(comp_pat2)) ELSE '0' ;
write_detect_d <= '1' WHEN (fifo_data_in_pre(9 DOWNTO 0) = CONV_INTEGER("0101111100")) OR (fifo_data_in_pre(9 DOWNTO 0) = CONV_INTEGER("1010000011")) ELSE '0' ;
detect_read_d <= '1' WHEN (fifo_data_out2_sync(9 DOWNTO 0) = CONV_INTEGER("0101111100")) OR (fifo_data_out2_sync(9 DOWNTO 0) = CONV_INTEGER("1010000011")) ELSE '0' ;
dataout_tmp14 <= fifo_data_out1_sync(9 DOWNTO 0) WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE datain ;
errdetectout_tmp16 <= fifo_data_out1_sync(10) WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE errdetectin ;
syncstatus_tmp17 <= fifo_data_out1_sync(11) WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE syncstatusin ;
disperr_tmp19 <= fifo_data_out1_sync(12) WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE disperrin ;
patterndetect_tmp18 <= fifo_data_out1_sync(13) WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE patterndetectin ;
codevalid_tmp15 <= fifo_data_out1_sync_valid WHEN (matchenable OR genericfifo_sync_clk2) = '1' ELSE alignstatus_dly WHEN (deskewenable) = '1' ELSE syncstatusin ;
alignsyncstatus_tmp10 <= '0' WHEN (NOT matchenable OR genericfifo_sync_clk1) = '1' ELSE alignstatus_dly WHEN (deskewenable) = '1' ELSE syncstatusin ;
alignsyncstatus_sync <= '0' WHEN (NOT matchenable OR genericfifo_sync_clk2) = '1' ELSE alignstatus_sync WHEN (deskewenable) = '1' ELSE syncstatus_sync ;
fifo_data_in <= '0' & datain ;
fifo_data_in_pre <= "000" & datainpre ;
fifo_errdetectin <= errdetectin ;
fifo_disperrin <= disperrin ;
fifo_patterndetectin <= patterndetectin ;
fifo_syncstatusin <= syncstatusin ;
comp_write <= (comp_write_pre AND NOT errdetectin) AND NOT disperrin ;
write_detect <= (write_detect_pre AND NOT errdetectin) AND NOT disperrin ;
END arch_stratixgx_comp_fifo_core;
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY sgate;
USE sgate.sgate_pack.all;
--synthesis_resources = lut 30 mux21 14 oper_selector 6
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_comp_fifo_sm IS
PORT
(
alignsyncstatus : IN STD_LOGIC;
decsync : IN STD_LOGIC;
done : IN STD_LOGIC;
fifocntgt9 : IN STD_LOGIC;
fifocntlt5 : IN STD_LOGIC;
overflow : OUT STD_LOGIC;
reset : IN STD_LOGIC;
smenable : IN STD_LOGIC;
underflow : OUT STD_LOGIC;
writeclk : IN STD_LOGIC
);
END stratixgx_comp_fifo_sm;
ARCHITECTURE RTL OF stratixgx_comp_fifo_sm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL n00i15 : STD_LOGIC := '0';
SIGNAL n00i16 : STD_LOGIC := '0';
SIGNAL wire_n00i16_w_lg_w_lg_q47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n00i16_w_lg_q47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n00O13 : STD_LOGIC := '0';
SIGNAL n00O14 : STD_LOGIC := '0';
SIGNAL wire_n00O14_w_lg_w_lg_q39w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n00O14_w_lg_q39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n01i19 : STD_LOGIC := '0';
SIGNAL n01i20 : STD_LOGIC := '0';
SIGNAL wire_n01i20_w_lg_w_lg_q60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01i20_w_lg_q60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n01l17 : STD_LOGIC := '0';
SIGNAL n01l18 : STD_LOGIC := '0';
SIGNAL wire_n01l18_w_lg_w_lg_q57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01l18_w_lg_q57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0ii11 : STD_LOGIC := '0';
SIGNAL n0ii12 : STD_LOGIC := '0';
SIGNAL wire_n0ii12_w_lg_w_lg_q28w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0ii12_w_lg_q28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0il10 : STD_LOGIC := '0';
SIGNAL wire_n0il10_w_lg_w_lg_q22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0il10_w_lg_q22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0il9 : STD_LOGIC := '0';
SIGNAL n0iO7 : STD_LOGIC := '0';
SIGNAL n0iO8 : STD_LOGIC := '0';
SIGNAL wire_n0iO8_w_lg_w_lg_q18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0iO8_w_lg_q18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0lO5 : STD_LOGIC := '0';
SIGNAL n0lO6 : STD_LOGIC := '0';
SIGNAL n0OO3 : STD_LOGIC := '0';
SIGNAL n0OO4 : STD_LOGIC := '0';
SIGNAL n1Ol23 : STD_LOGIC := '0';
SIGNAL n1Ol24 : STD_LOGIC := '0';
SIGNAL wire_n1Ol24_w_lg_w_lg_q77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1Ol24_w_lg_q77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1OO21 : STD_LOGIC := '0';
SIGNAL n1OO22 : STD_LOGIC := '0';
SIGNAL wire_n1OO22_w_lg_w_lg_q63w64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1OO22_w_lg_q63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ni1O1 : STD_LOGIC := '0';
SIGNAL ni1O2 : STD_LOGIC := '0';
SIGNAL nO : STD_LOGIC := '0';
SIGNAL wire_nl_CLRN : STD_LOGIC;
SIGNAL wire_nl_w_lg_nO14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl_w_lg_w_lg_nO55w59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl_w_lg_nO55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ni : STD_LOGIC := '0';
SIGNAL nil : STD_LOGIC := '0';
SIGNAL niO : STD_LOGIC := '0';
SIGNAL nli : STD_LOGIC := '0';
SIGNAL nll : STD_LOGIC := '0';
SIGNAL wire_nlO_CLRN : STD_LOGIC;
SIGNAL wire_n0l_dataout : STD_LOGIC;
SIGNAL wire_n0O_dataout : STD_LOGIC;
SIGNAL wire_n1i_dataout : STD_LOGIC;
SIGNAL wire_n1l_dataout : STD_LOGIC;
SIGNAL wire_n1O_dataout : STD_LOGIC;
SIGNAL wire_nlii_dataout : STD_LOGIC;
SIGNAL wire_nlil_dataout : STD_LOGIC;
SIGNAL wire_nliO_dataout : STD_LOGIC;
SIGNAL wire_nlli_dataout : STD_LOGIC;
SIGNAL wire_nlll_dataout : STD_LOGIC;
SIGNAL wire_nllO_dataout : STD_LOGIC;
SIGNAL wire_nlOi_dataout : STD_LOGIC;
SIGNAL wire_nlOl_dataout : STD_LOGIC;
SIGNAL wire_nlOO_dataout : STD_LOGIC;
SIGNAL wire_niOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_niOl_o : STD_LOGIC;
SIGNAL wire_niOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_niOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_niOO_o : STD_LOGIC;
SIGNAL wire_niOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nl0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nl0i_o : STD_LOGIC;
SIGNAL wire_nl0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nl0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl0l_o : STD_LOGIC;
SIGNAL wire_nl0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl0O_data : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_nl0O_o : STD_LOGIC;
SIGNAL wire_nl0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_nl1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nl1l_o : STD_LOGIC;
SIGNAL wire_nl1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_w_lg_alignsyncstatus10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_decsync9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_done13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n0li12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n0ll23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n00l : STD_LOGIC;
SIGNAL n0li : STD_LOGIC;
SIGNAL n0ll : STD_LOGIC;
SIGNAL ni1i : STD_LOGIC;
BEGIN
wire_w_lg_alignsyncstatus10w(0) <= NOT alignsyncstatus;
wire_w_lg_decsync9w(0) <= NOT decsync;
wire_w_lg_done13w(0) <= NOT done;
wire_w_lg_n0li12w(0) <= NOT n0li;
wire_w_lg_n0ll23w(0) <= NOT n0ll;
wire_w_lg_reset2w(0) <= NOT reset;
n00l <= (nO OR ni);
n0li <= (fifocntlt5 OR fifocntgt9);
n0ll <= ((alignsyncstatus AND smenable) AND (n0lO6 XOR n0lO5));
ni1i <= '1';
overflow <= nil;
underflow <= niO;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n00i15 <= n00i16;
END IF;
if (now = 0 ns) then
n00i15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n00i16 <= n00i15;
END IF;
END PROCESS;
wire_n00i16_w_lg_w_lg_q47w48w(0) <= wire_n00i16_w_lg_q47w(0) AND wire_n1i_dataout;
wire_n00i16_w_lg_q47w(0) <= n00i16 XOR n00i15;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n00O13 <= n00O14;
END IF;
if (now = 0 ns) then
n00O13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n00O14 <= n00O13;
END IF;
END PROCESS;
wire_n00O14_w_lg_w_lg_q39w40w(0) <= wire_n00O14_w_lg_q39w(0) AND nll;
wire_n00O14_w_lg_q39w(0) <= n00O14 XOR n00O13;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n01i19 <= n01i20;
END IF;
if (now = 0 ns) then
n01i19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n01i20 <= n01i19;
END IF;
END PROCESS;
wire_n01i20_w_lg_w_lg_q60w61w(0) <= wire_n01i20_w_lg_q60w(0) AND wire_nl_w_lg_w_lg_nO55w59w(0);
wire_n01i20_w_lg_q60w(0) <= n01i20 XOR n01i19;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n01l17 <= n01l18;
END IF;
if (now = 0 ns) then
n01l17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n01l18 <= n01l17;
END IF;
END PROCESS;
wire_n01l18_w_lg_w_lg_q57w58w(0) <= NOT wire_n01l18_w_lg_q57w(0);
wire_n01l18_w_lg_q57w(0) <= n01l18 XOR n01l17;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0ii11 <= n0ii12;
END IF;
if (now = 0 ns) then
n0ii11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0ii12 <= n0ii11;
END IF;
END PROCESS;
wire_n0ii12_w_lg_w_lg_q28w29w(0) <= wire_n0ii12_w_lg_q28w(0) AND nli;
wire_n0ii12_w_lg_q28w(0) <= n0ii12 XOR n0ii11;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0il10 <= n0il9;
END IF;
END PROCESS;
wire_n0il10_w_lg_w_lg_q22w24w(0) <= wire_n0il10_w_lg_q22w(0) AND wire_w_lg_n0ll23w(0);
wire_n0il10_w_lg_q22w(0) <= n0il10 XOR n0il9;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0il9 <= n0il10;
END IF;
if (now = 0 ns) then
n0il9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0iO7 <= n0iO8;
END IF;
if (now = 0 ns) then
n0iO7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0iO8 <= n0iO7;
END IF;
END PROCESS;
wire_n0iO8_w_lg_w_lg_q18w19w(0) <= wire_n0iO8_w_lg_q18w(0) AND wire_w_lg_alignsyncstatus10w(0);
wire_n0iO8_w_lg_q18w(0) <= n0iO8 XOR n0iO7;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0lO5 <= n0lO6;
END IF;
if (now = 0 ns) then
n0lO5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0lO6 <= n0lO5;
END IF;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0OO3 <= n0OO4;
END IF;
if (now = 0 ns) then
n0OO3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n0OO4 <= n0OO3;
END IF;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n1Ol23 <= n1Ol24;
END IF;
if (now = 0 ns) then
n1Ol23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n1Ol24 <= n1Ol23;
END IF;
END PROCESS;
wire_n1Ol24_w_lg_w_lg_q77w78w(0) <= wire_n1Ol24_w_lg_q77w(0) AND wire_nlOl_dataout;
wire_n1Ol24_w_lg_q77w(0) <= n1Ol24 XOR n1Ol23;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n1OO21 <= n1OO22;
END IF;
if (now = 0 ns) then
n1OO21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN n1OO22 <= n1OO21;
END IF;
END PROCESS;
wire_n1OO22_w_lg_w_lg_q63w64w(0) <= wire_n1OO22_w_lg_q63w(0) AND wire_nlOO_dataout;
wire_n1OO22_w_lg_q63w(0) <= n1OO22 XOR n1OO21;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN ni1O1 <= ni1O2;
END IF;
if (now = 0 ns) then
ni1O1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (writeclk)
BEGIN
IF (writeclk = '1' AND writeclk'event) THEN ni1O2 <= ni1O1;
END IF;
END PROCESS;
PROCESS (writeclk, reset, wire_nl_CLRN)
BEGIN
IF (reset = '1') THEN
nO <= '1';
ELSIF (wire_nl_CLRN = '0') THEN
nO <= '0';
ELSIF (writeclk = '1' AND writeclk'event) THEN
nO <= wire_nl0O_o;
END IF;
if (now = 0 ns) then
nO <= '1' after 1 ps;
end if;
END PROCESS;
wire_nl_CLRN <= (ni1O2 XOR ni1O1);
wire_nl_w_lg_nO14w(0) <= NOT nO;
wire_nl_w_lg_w_lg_nO55w59w(0) <= wire_nl_w_lg_nO55w(0) OR wire_n01l18_w_lg_w_lg_q57w58w(0);
wire_nl_w_lg_nO55w(0) <= nO OR nll;
PROCESS (writeclk, wire_nlO_CLRN)
BEGIN
IF (wire_nlO_CLRN = '0') THEN
ni <= '0';
nil <= '0';
niO <= '0';
nli <= '0';
nll <= '0';
ELSIF (writeclk = '1' AND writeclk'event) THEN
ni <= wire_nl0l_o;
nil <= wire_niOl_o;
niO <= wire_niOO_o;
nli <= wire_nl1l_o;
nll <= wire_nl0i_o;
END IF;
END PROCESS;
wire_nlO_CLRN <= ((n0OO4 XOR n0OO3) AND wire_w_lg_reset2w(0));
wire_n0l_dataout <= decsync AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_n0O_dataout <= wire_w_lg_decsync9w(0) AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_n1i_dataout <= n0li AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_n1l_dataout <= fifocntgt9 WHEN n0li = '1' ELSE nil;
wire_n1O_dataout <= fifocntlt5 WHEN n0li = '1' ELSE niO;
wire_nlii_dataout <= wire_w_lg_done13w(0) AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_nlil_dataout <= done AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_nliO_dataout <= wire_nlll_dataout AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_nlli_dataout <= wire_nllO_dataout AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_nlll_dataout <= niO AND NOT(done);
wire_nllO_dataout <= nil AND NOT(done);
wire_nlOi_dataout <= nil WHEN wire_w_lg_alignsyncstatus10w(0) = '1' ELSE wire_n1l_dataout;
wire_nlOl_dataout <= niO WHEN wire_w_lg_alignsyncstatus10w(0) = '1' ELSE wire_n1O_dataout;
wire_nlOO_dataout <= wire_w_lg_n0li12w(0) AND NOT(wire_w_lg_alignsyncstatus10w(0));
wire_niOl_data <= ( nil & wire_nlOi_dataout & wire_nlli_dataout);
wire_niOl_sel <= ( n00l & nli & nll);
niOl : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_niOl_data,
o => wire_niOl_o,
sel => wire_niOl_sel
);
wire_niOO_data <= ( niO & wire_n1Ol24_w_lg_w_lg_q77w78w & wire_nliO_dataout);
wire_niOO_sel <= ( n00l & nli & nll);
niOO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_niOO_data,
o => wire_niOO_o,
sel => wire_niOO_sel
);
wire_nl0i_data <= ( "0" & wire_n00i16_w_lg_w_lg_q47w48w & wire_nlii_dataout);
wire_nl0i_sel <= ( n00l & nli & wire_n00O14_w_lg_w_lg_q39w40w);
nl0i : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nl0i_data,
o => wire_nl0i_o,
sel => wire_nl0i_sel
);
wire_nl0l_data <= ( n0ll & wire_n0O_dataout & "0" & wire_nlil_dataout);
wire_nl0l_sel <= ( nO & ni & wire_n0ii12_w_lg_w_lg_q28w29w & nll);
nl0l : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_nl0l_data,
o => wire_nl0l_o,
sel => wire_nl0l_sel
);
wire_nl0O_data <= ( wire_n0il10_w_lg_w_lg_q22w24w & wire_n0iO8_w_lg_w_lg_q18w19w);
wire_nl0O_sel <= ( nO & wire_nl_w_lg_nO14w);
nl0O : oper_selector
GENERIC MAP (
width_data => 2,
width_sel => 2
)
PORT MAP (
data => wire_nl0O_data,
o => wire_nl0O_o,
sel => wire_nl0O_sel
);
wire_nl1l_data <= ( "0" & wire_n0l_dataout & wire_n1OO22_w_lg_w_lg_q63w64w);
wire_nl1l_sel <= ( wire_n01i20_w_lg_w_lg_q60w61w & ni & nli);
nl1l : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nl1l_data,
o => wire_nl1l_o,
sel => wire_nl1l_sel
);
END RTL; --stratixgx_comp_fifo_sm
--synopsys translate_on
--VALID FILE
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_COMP_FIFO
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY ieee, stratixgx_gxb,std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixgx_comp_fifo IS
GENERIC (
use_rate_match_fifo : string := "true";
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : String := "true"; -- new in 3.0 SP2
channel_num : integer := 0
);
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
errdetectinpre : IN std_logic;
syncstatusinpre : IN std_logic;
disperrinpre : IN std_logic;
patterndetectinpre : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
re : IN std_logic;
we : IN std_logic;
fifordin : IN std_logic;
disablefifordin : IN std_logic;
disablefifowrin : IN std_logic;
alignstatus : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
errdetectout : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
codevalid : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostful : OUT std_logic;
fifoempty : OUT std_logic;
fifoalmostempty : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
fifordout : OUT std_logic);
end stratixgx_comp_fifo;
ARCHITECTURE arch_stratixgx_comp_fifo OF stratixgx_comp_fifo IS
COMPONENT stratixgx_comp_fifo_core
GENERIC (
channel_num : integer := 0;
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : string := "true"; -- new in 3.0 SP2
use_rate_match_fifo : string := "true");
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
underflow : IN std_logic;
overflow : IN std_logic;
errdetectin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
disablefifowrin : IN std_logic;
disablefifordin : IN std_logic;
re : IN std_logic;
we : IN std_logic;
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
syncstatusin : IN std_logic;
disperr : OUT std_logic;
alignstatus : IN std_logic;
fifordin : IN std_logic;
fifordout : OUT std_logic;
decsync : OUT std_logic;
fifocntlt5 : OUT std_logic;
fifocntgt9 : OUT std_logic;
done : OUT std_logic;
fifoalmostful : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostempty : OUT std_logic;
fifoempty : OUT std_logic;
alignsyncstatus : OUT std_logic;
smenable : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
codevalid : OUT std_logic;
errdetectout : OUT std_logic;
patterndetect : OUT std_logic;
syncstatus : OUT std_logic);
END COMPONENT;
COMPONENT stratixgx_comp_fifo_sm
PORT (
writeclk : IN std_logic;
alignsyncstatus : IN std_logic;
reset : IN std_logic;
smenable : IN std_logic;
done : IN std_logic;
decsync : IN std_logic;
fifocntlt5 : IN std_logic;
fifocntgt9 : IN std_logic;
underflow : OUT std_logic;
overflow : OUT std_logic);
END COMPONENT;
SIGNAL done : std_logic;
SIGNAL fifocntgt9 : std_logic;
SIGNAL fifocntlt5 : std_logic;
SIGNAL decsync : std_logic;
SIGNAL alignsyncstatus : std_logic;
SIGNAL smenable : std_logic;
SIGNAL overflow : std_logic;
SIGNAL underflow : std_logic;
SIGNAL dataout_tmp1 : std_logic_vector(9 DOWNTO 0);
SIGNAL errdetectout_tmp2 : std_logic;
SIGNAL syncstatus_tmp3 : std_logic;
SIGNAL disperr_tmp4 : std_logic;
SIGNAL patterndetect_tmp5 : std_logic;
SIGNAL codevalid_tmp6 : std_logic;
SIGNAL fifofull_tmp7 : std_logic;
SIGNAL fifoalmostful_tmp8 : std_logic;
SIGNAL fifoempty_tmp9 : std_logic;
SIGNAL fifoalmostempty_tmp10 : std_logic;
SIGNAL disablefifordout_tmp11 : std_logic;
SIGNAL disablefifowrout_tmp12 : std_logic;
SIGNAL fifordout_tmp13 : std_logic;
BEGIN
dataout <= dataout_tmp1;
errdetectout <= errdetectout_tmp2;
syncstatus <= syncstatus_tmp3;
disperr <= disperr_tmp4;
patterndetect <= patterndetect_tmp5;
codevalid <= codevalid_tmp6;
fifofull <= fifofull_tmp7;
fifoalmostful <= fifoalmostful_tmp8;
fifoempty <= fifoempty_tmp9;
fifoalmostempty <= fifoalmostempty_tmp10;
disablefifordout <= disablefifordout_tmp11;
disablefifowrout <= disablefifowrout_tmp12;
fifordout <= fifordout_tmp13;
comp_fifo_core : stratixgx_comp_fifo_core
GENERIC MAP (
channel_num => channel_num,
rate_matching_fifo_mode => rate_matching_fifo_mode,
use_channel_align => use_channel_align,
for_engineering_sample_device => for_engineering_sample_device, -- new in 3.0 SP2
use_rate_match_fifo => use_rate_match_fifo)
PORT MAP (
reset => reset,
writeclk => writeclk,
readclk => readclk,
underflow => underflow,
overflow => overflow,
errdetectin => errdetectin,
disperrin => disperrin,
patterndetectin => patterndetectin,
disablefifordin => disablefifordin,
disablefifowrin => disablefifowrin,
re => re,
we => we,
datain => datain,
datainpre => datainpre,
syncstatusin => syncstatusin,
disperr => disperr_tmp4,
alignstatus => alignstatus,
fifordin => fifordin,
fifordout => fifordout_tmp13,
fifoalmostful => fifoalmostful_tmp8,
fifofull => fifofull_tmp7,
fifoalmostempty => fifoalmostempty_tmp10,
fifoempty => fifoempty_tmp9,
decsync => decsync,
fifocntlt5 => fifocntlt5,
fifocntgt9 => fifocntgt9,
done => done,
alignsyncstatus => alignsyncstatus,
smenable => smenable,
disablefifordout => disablefifordout_tmp11,
disablefifowrout => disablefifowrout_tmp12,
dataout => dataout_tmp1,
codevalid => codevalid_tmp6,
errdetectout => errdetectout_tmp2,
patterndetect => patterndetect_tmp5,
syncstatus => syncstatus_tmp3);
comp_fifo_sm : stratixgx_comp_fifo_sm
PORT MAP (
writeclk => writeclk,
alignsyncstatus => alignsyncstatus,
reset => reset,
smenable => smenable,
done => done,
decsync => decsync,
fifocntlt5 => fifocntlt5,
fifocntgt9 => fifocntgt9,
underflow => underflow,
overflow => overflow);
END arch_stratixgx_comp_fifo;
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY sgate;
USE sgate.sgate_pack.all;
--synthesis_resources = lut 283 mux21 302 oper_add 5 oper_less_than 1 oper_mux 18 oper_selector 42
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_hssi_rx_wal_rtl IS
PORT
(
A1A2_SIZE : IN STD_LOGIC;
AUTOBYTEALIGN_DIS : IN STD_LOGIC;
BITSLIP : IN STD_LOGIC;
cg_comma : OUT STD_LOGIC;
DISABLE_RX_DISP : IN STD_LOGIC;
DWIDTH : IN STD_LOGIC;
encdet_prbs : IN STD_LOGIC;
ENCDT : IN STD_LOGIC;
GE_XAUI_SEL : IN STD_LOGIC;
IB_INVALID_CODE : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
LP10BEN : IN STD_LOGIC;
PMADATAWIDTH : IN STD_LOGIC;
prbs_en : IN STD_LOGIC;
PUDI : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
PUDR : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rcvd_clk : IN STD_LOGIC;
RLV : OUT STD_LOGIC;
RLV_EN : IN STD_LOGIC;
RLV_lt : OUT STD_LOGIC;
RUNDISP_SEL : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal_detect : IN STD_LOGIC;
signal_detect_sync : OUT STD_LOGIC;
soft_reset : IN STD_LOGIC;
SUDI : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
SUDI_pre : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
SYNC_COMP_PAT : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
SYNC_COMP_SIZE : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
sync_curr_st : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
SYNC_SM_DIS : IN STD_LOGIC;
sync_status : OUT STD_LOGIC
);
END stratixgx_hssi_rx_wal_rtl;
ARCHITECTURE RTL OF stratixgx_hssi_rx_wal_rtl IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL n1l0OO53 : STD_LOGIC := '0';
SIGNAL n1l0OO54 : STD_LOGIC := '0';
SIGNAL n1li0l49 : STD_LOGIC := '0';
SIGNAL n1li0l50 : STD_LOGIC := '0';
SIGNAL n1li1i51 : STD_LOGIC := '0';
SIGNAL n1li1i52 : STD_LOGIC := '0';
SIGNAL n1llOl47 : STD_LOGIC := '0';
SIGNAL n1llOl48 : STD_LOGIC := '0';
SIGNAL wire_n1llOl48_w_lg_q221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1lO0l43 : STD_LOGIC := '0';
SIGNAL n1lO0l44 : STD_LOGIC := '0';
SIGNAL wire_n1lO0l44_w_lg_q208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1lO1i45 : STD_LOGIC := '0';
SIGNAL n1lO1i46 : STD_LOGIC := '0';
SIGNAL n1lOii41 : STD_LOGIC := '0';
SIGNAL n1lOii42 : STD_LOGIC := '0';
SIGNAL n1lOiO39 : STD_LOGIC := '0';
SIGNAL n1lOiO40 : STD_LOGIC := '0';
SIGNAL n1lOOi37 : STD_LOGIC := '0';
SIGNAL n1lOOi38 : STD_LOGIC := '0';
SIGNAL n1lOOO35 : STD_LOGIC := '0';
SIGNAL n1lOOO36 : STD_LOGIC := '0';
SIGNAL wire_n1lOOO36_w_lg_q186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O00i17 : STD_LOGIC := '0';
SIGNAL n1O00i18 : STD_LOGIC := '0';
SIGNAL wire_n1O00i18_w_lg_w_lg_q79w80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O00i18_w_lg_q79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O00l15 : STD_LOGIC := '0';
SIGNAL n1O00l16 : STD_LOGIC := '0';
SIGNAL wire_n1O00l16_w_lg_w_lg_q68w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O00l16_w_lg_q68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O01i23 : STD_LOGIC := '0';
SIGNAL n1O01i24 : STD_LOGIC := '0';
SIGNAL wire_n1O01i24_w_lg_w_lg_q99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O01i24_w_lg_q99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O01l21 : STD_LOGIC := '0';
SIGNAL n1O01l22 : STD_LOGIC := '0';
SIGNAL wire_n1O01l22_w_lg_w_lg_q96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O01l22_w_lg_q96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O01O19 : STD_LOGIC := '0';
SIGNAL n1O01O20 : STD_LOGIC := '0';
SIGNAL wire_n1O01O20_w_lg_w_lg_q88w89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O01O20_w_lg_q88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1O0ii13 : STD_LOGIC := '0';
SIGNAL n1O0ii14 : STD_LOGIC := '0';
SIGNAL n1O0iO11 : STD_LOGIC := '0';
SIGNAL n1O0iO12 : STD_LOGIC := '0';
SIGNAL n1O10i33 : STD_LOGIC := '0';
SIGNAL n1O10i34 : STD_LOGIC := '0';
SIGNAL n1O10O31 : STD_LOGIC := '0';
SIGNAL n1O10O32 : STD_LOGIC := '0';
SIGNAL n1O1il29 : STD_LOGIC := '0';
SIGNAL n1O1il30 : STD_LOGIC := '0';
SIGNAL n1O1Ol27 : STD_LOGIC := '0';
SIGNAL n1O1Ol28 : STD_LOGIC := '0';
SIGNAL n1O1OO25 : STD_LOGIC := '0';
SIGNAL n1O1OO26 : STD_LOGIC := '0';
SIGNAL n1Oi0l7 : STD_LOGIC := '0';
SIGNAL n1Oi0l8 : STD_LOGIC := '0';
SIGNAL n1Oi0O5 : STD_LOGIC := '0';
SIGNAL n1Oi0O6 : STD_LOGIC := '0';
SIGNAL n1Oi1i10 : STD_LOGIC := '0';
SIGNAL n1Oi1i9 : STD_LOGIC := '0';
SIGNAL n1Oill3 : STD_LOGIC := '0';
SIGNAL n1Oill4 : STD_LOGIC := '0';
SIGNAL n1OiOi1 : STD_LOGIC := '0';
SIGNAL n1OiOi2 : STD_LOGIC := '0';
SIGNAL n10li : STD_LOGIC := '0';
SIGNAL n10lO : STD_LOGIC := '0';
SIGNAL n10Oi : STD_LOGIC := '0';
SIGNAL n10OO : STD_LOGIC := '0';
SIGNAL wire_n10Ol_CLRN : STD_LOGIC;
SIGNAL wire_n10Ol_PRN : STD_LOGIC;
SIGNAL wire_n10Ol_w_lg_n10li1496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n10Ol_w_lg_n10lO1494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n10Ol_w_lg_n10Oi1492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n10Ol_w_lg_n10OO1491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1lOi : STD_LOGIC := '0';
SIGNAL n1lOl : STD_LOGIC := '0';
SIGNAL n1lOO : STD_LOGIC := '0';
SIGNAL n1O1l : STD_LOGIC := '0';
SIGNAL wire_n1O1i_CLRN : STD_LOGIC;
SIGNAL n0001i : STD_LOGIC := '0';
SIGNAL n0010i : STD_LOGIC := '0';
SIGNAL n0010l : STD_LOGIC := '0';
SIGNAL n0010O : STD_LOGIC := '0';
SIGNAL n0011O : STD_LOGIC := '0';
SIGNAL n001ii : STD_LOGIC := '0';
SIGNAL n001il : STD_LOGIC := '0';
SIGNAL n001iO : STD_LOGIC := '0';
SIGNAL n001li : STD_LOGIC := '0';
SIGNAL n001ll : STD_LOGIC := '0';
SIGNAL n001lO : STD_LOGIC := '0';
SIGNAL n001Oi : STD_LOGIC := '0';
SIGNAL n001OO : STD_LOGIC := '0';
SIGNAL n0101l : STD_LOGIC := '0';
SIGNAL n1lli : STD_LOGIC := '0';
SIGNAL n1lll : STD_LOGIC := '0';
SIGNAL n1O1O : STD_LOGIC := '0';
SIGNAL n1Ol0i : STD_LOGIC := '0';
SIGNAL n1Ol0O : STD_LOGIC := '0';
SIGNAL n1Olli : STD_LOGIC := '0';
SIGNAL n1Olll : STD_LOGIC := '0';
SIGNAL ni0iOl : STD_LOGIC := '0';
SIGNAL ni0iOO : STD_LOGIC := '0';
SIGNAL ni0l0i : STD_LOGIC := '0';
SIGNAL ni0l0O : STD_LOGIC := '0';
SIGNAL ni0l1i : STD_LOGIC := '0';
SIGNAL ni0l1l : STD_LOGIC := '0';
SIGNAL ni0l1O : STD_LOGIC := '0';
SIGNAL ni0O0O : STD_LOGIC := '0';
SIGNAL ni0Oii : STD_LOGIC := '0';
SIGNAL ni0Oil : STD_LOGIC := '0';
SIGNAL ni0OiO : STD_LOGIC := '0';
SIGNAL ni0OOO : STD_LOGIC := '0';
SIGNAL ni1liO : STD_LOGIC := '0';
SIGNAL ni1lli : STD_LOGIC := '0';
SIGNAL ni1lll : STD_LOGIC := '0';
SIGNAL ni1llO : STD_LOGIC := '0';
SIGNAL ni1lOi : STD_LOGIC := '0';
SIGNAL ni1lOl : STD_LOGIC := '0';
SIGNAL ni1lOO : STD_LOGIC := '0';
SIGNAL ni1O1i : STD_LOGIC := '0';
SIGNAL ni1Oli : STD_LOGIC := '0';
SIGNAL nii11i : STD_LOGIC := '0';
SIGNAL nii11l : STD_LOGIC := '0';
SIGNAL nii11O : STD_LOGIC := '0';
SIGNAL niii0i : STD_LOGIC := '0';
SIGNAL niii0l : STD_LOGIC := '0';
SIGNAL niii0O : STD_LOGIC := '0';
SIGNAL niii1l : STD_LOGIC := '0';
SIGNAL niii1O : STD_LOGIC := '0';
SIGNAL niiiii : STD_LOGIC := '0';
SIGNAL niiiil : STD_LOGIC := '0';
SIGNAL niiiiO : STD_LOGIC := '0';
SIGNAL niiili : STD_LOGIC := '0';
SIGNAL niiill : STD_LOGIC := '0';
SIGNAL niiilO : STD_LOGIC := '0';
SIGNAL niiiOi : STD_LOGIC := '0';
SIGNAL niiiOl : STD_LOGIC := '0';
SIGNAL niiiOO : STD_LOGIC := '0';
SIGNAL niil1i : STD_LOGIC := '0';
SIGNAL niiO0i : STD_LOGIC := '0';
SIGNAL niiO0l : STD_LOGIC := '0';
SIGNAL niiO0O : STD_LOGIC := '0';
SIGNAL niiO1l : STD_LOGIC := '0';
SIGNAL niiO1O : STD_LOGIC := '0';
SIGNAL niiOii : STD_LOGIC := '0';
SIGNAL niiOil : STD_LOGIC := '0';
SIGNAL niiOiO : STD_LOGIC := '0';
SIGNAL niiOli : STD_LOGIC := '0';
SIGNAL niiOll : STD_LOGIC := '0';
SIGNAL niiOlO : STD_LOGIC := '0';
SIGNAL niiOOi : STD_LOGIC := '0';
SIGNAL niiOOl : STD_LOGIC := '0';
SIGNAL nil0i : STD_LOGIC := '0';
SIGNAL nil0l : STD_LOGIC := '0';
SIGNAL nil0O : STD_LOGIC := '0';
SIGNAL nilii : STD_LOGIC := '0';
SIGNAL nilil : STD_LOGIC := '0';
SIGNAL niliO : STD_LOGIC := '0';
SIGNAL nilli : STD_LOGIC := '0';
SIGNAL nilll : STD_LOGIC := '0';
SIGNAL nilOi : STD_LOGIC := '0';
SIGNAL nlll0l : STD_LOGIC := '0';
SIGNAL nlll0O : STD_LOGIC := '0';
SIGNAL nlllll : STD_LOGIC := '0';
SIGNAL nllllO : STD_LOGIC := '0';
SIGNAL nlllOi : STD_LOGIC := '0';
SIGNAL nlllOl : STD_LOGIC := '0';
SIGNAL nlllOO : STD_LOGIC := '0';
SIGNAL nllO0i : STD_LOGIC := '0';
SIGNAL nllO0l : STD_LOGIC := '0';
SIGNAL nllO0O : STD_LOGIC := '0';
SIGNAL nllO1i : STD_LOGIC := '0';
SIGNAL nllO1l : STD_LOGIC := '0';
SIGNAL nllO1O : STD_LOGIC := '0';
SIGNAL nllOii : STD_LOGIC := '0';
SIGNAL nllOil : STD_LOGIC := '0';
SIGNAL nllOiO : STD_LOGIC := '0';
SIGNAL nllOli : STD_LOGIC := '0';
SIGNAL nllOll : STD_LOGIC := '0';
SIGNAL nllOlO : STD_LOGIC := '0';
SIGNAL nllOOi : STD_LOGIC := '0';
SIGNAL nllOOl : STD_LOGIC := '0';
SIGNAL nllOOO : STD_LOGIC := '0';
SIGNAL nlO00i : STD_LOGIC := '0';
SIGNAL nlO00l : STD_LOGIC := '0';
SIGNAL nlO00O : STD_LOGIC := '0';
SIGNAL nlO01i : STD_LOGIC := '0';
SIGNAL nlO01l : STD_LOGIC := '0';
SIGNAL nlO01O : STD_LOGIC := '0';
SIGNAL nlO0ii : STD_LOGIC := '0';
SIGNAL nlO0il : STD_LOGIC := '0';
SIGNAL nlO0iO : STD_LOGIC := '0';
SIGNAL nlO0li : STD_LOGIC := '0';
SIGNAL nlO10i : STD_LOGIC := '0';
SIGNAL nlO10l : STD_LOGIC := '0';
SIGNAL nlO10O : STD_LOGIC := '0';
SIGNAL nlO11i : STD_LOGIC := '0';
SIGNAL nlO11l : STD_LOGIC := '0';
SIGNAL nlO11O : STD_LOGIC := '0';
SIGNAL nlO1ii : STD_LOGIC := '0';
SIGNAL nlO1il : STD_LOGIC := '0';
SIGNAL nlO1iO : STD_LOGIC := '0';
SIGNAL nlO1li : STD_LOGIC := '0';
SIGNAL nlO1ll : STD_LOGIC := '0';
SIGNAL nlO1lO : STD_LOGIC := '0';
SIGNAL nlO1Oi : STD_LOGIC := '0';
SIGNAL nlO1Ol : STD_LOGIC := '0';
SIGNAL nlO1OO : STD_LOGIC := '0';
SIGNAL wire_nillO_PRN : STD_LOGIC;
SIGNAL wire_nillO_w_lg_w_lg_w_lg_w2399w2400w2401w2402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w2399w2400w2401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w2399w2400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w2399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w2398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_nlO0il883w2447w2448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nilli1648w1653w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nilOi1646w1651w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il2449w2450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_n1O1O2083w2396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO00i855w2583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO00i855w856w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO00O2567w2588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01l2560w2562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01l2560w2597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01O2569w2625w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01O2569w2620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01O2569w2608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO01O2569w2605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0ii2442w2476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0ii2442w2443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il883w2458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il883w2512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il883w2447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il883w884w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0il883w2495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO882w2459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO882w2506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO882w2533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO882w2528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO882w2509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0li881w2482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_n1O1O2416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilli1648w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilOi1646w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlll0l858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2626w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i2632w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00O2589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01l2598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01O2563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01O2628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01O2631w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0ii865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il2455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il2496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il2449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il888w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO2513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO2536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO2456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO2539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO889w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li2540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_w_lg_nilli1561w1568w1575w1576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nilli1561w1562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_n0001i2740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_n1lli1498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_n1O1O2083w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_n1Ol0i2743w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nii11i2011w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_niii1l2179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_niii1O2185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_niiO1l2180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nil0i2075w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nil0l2067w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nil0O2065w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilii2063w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilil2061w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_niliO2059w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilli2089w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilll2087w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilOi2382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlll0l845w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlll0O2741w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlllll2714w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00i855w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00l2568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO00O2567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01i2561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01l2560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO01O2569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0ii2442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0il883w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0iO882w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nlO0li881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_w_lg_nlO0il883w2447w2448w2451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nlO0iO2456w2460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_w_lg_nilli1561w1568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nillO_w_lg_nilli1561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nilOl : STD_LOGIC := '0';
SIGNAL nilOO : STD_LOGIC := '0';
SIGNAL niO1i : STD_LOGIC := '0';
SIGNAL nl1ll : STD_LOGIC := '0';
SIGNAL nl1Oi : STD_LOGIC := '0';
SIGNAL wire_nl1lO_PRN : STD_LOGIC;
SIGNAL n0000i : STD_LOGIC := '0';
SIGNAL n0000l : STD_LOGIC := '0';
SIGNAL n0000O : STD_LOGIC := '0';
SIGNAL n0001O : STD_LOGIC := '0';
SIGNAL n00OlO : STD_LOGIC := '0';
SIGNAL n00OOi : STD_LOGIC := '0';
SIGNAL n00OOl : STD_LOGIC := '0';
SIGNAL n00OOO : STD_LOGIC := '0';
SIGNAL n0i0OO : STD_LOGIC := '0';
SIGNAL n0i10i : STD_LOGIC := '0';
SIGNAL n0i10l : STD_LOGIC := '0';
SIGNAL n0i10O : STD_LOGIC := '0';
SIGNAL n0i11i : STD_LOGIC := '0';
SIGNAL n0i11l : STD_LOGIC := '0';
SIGNAL n0i11O : STD_LOGIC := '0';
SIGNAL n0i1ii : STD_LOGIC := '0';
SIGNAL n0i1il : STD_LOGIC := '0';
SIGNAL n0i1iO : STD_LOGIC := '0';
SIGNAL n0i1li : STD_LOGIC := '0';
SIGNAL n0i1ll : STD_LOGIC := '0';
SIGNAL n0i1lO : STD_LOGIC := '0';
SIGNAL n0i1Oi : STD_LOGIC := '0';
SIGNAL n0ii0i : STD_LOGIC := '0';
SIGNAL n0ii0l : STD_LOGIC := '0';
SIGNAL n0ii0O : STD_LOGIC := '0';
SIGNAL n0ii1i : STD_LOGIC := '0';
SIGNAL n0ii1l : STD_LOGIC := '0';
SIGNAL n0ii1O : STD_LOGIC := '0';
SIGNAL n10ii : STD_LOGIC := '0';
SIGNAL n10il : STD_LOGIC := '0';
SIGNAL n10iO : STD_LOGIC := '0';
SIGNAL n110i : STD_LOGIC := '0';
SIGNAL n110l : STD_LOGIC := '0';
SIGNAL n110O : STD_LOGIC := '0';
SIGNAL n111l : STD_LOGIC := '0';
SIGNAL n111O : STD_LOGIC := '0';
SIGNAL n11ii : STD_LOGIC := '0';
SIGNAL n11il : STD_LOGIC := '0';
SIGNAL n11iO : STD_LOGIC := '0';
SIGNAL n11li : STD_LOGIC := '0';
SIGNAL n11ll : STD_LOGIC := '0';
SIGNAL n1i1i : STD_LOGIC := '0';
SIGNAL n1iOi : STD_LOGIC := '0';
SIGNAL n1iOO : STD_LOGIC := '0';
SIGNAL n1l0i : STD_LOGIC := '0';
SIGNAL n1l0l : STD_LOGIC := '0';
SIGNAL n1l1i : STD_LOGIC := '0';
SIGNAL n1l1l : STD_LOGIC := '0';
SIGNAL n1l1O : STD_LOGIC := '0';
SIGNAL n1llO : STD_LOGIC := '0';
SIGNAL niO0i : STD_LOGIC := '0';
SIGNAL niO0l : STD_LOGIC := '0';
SIGNAL niO0O : STD_LOGIC := '0';
SIGNAL niO1l : STD_LOGIC := '0';
SIGNAL niO1O : STD_LOGIC := '0';
SIGNAL niOii : STD_LOGIC := '0';
SIGNAL niOil : STD_LOGIC := '0';
SIGNAL niOiO : STD_LOGIC := '0';
SIGNAL niOli : STD_LOGIC := '0';
SIGNAL niOll : STD_LOGIC := '0';
SIGNAL niOlO : STD_LOGIC := '0';
SIGNAL niOOi : STD_LOGIC := '0';
SIGNAL niOOl : STD_LOGIC := '0';
SIGNAL niOOO : STD_LOGIC := '0';
SIGNAL nl10i : STD_LOGIC := '0';
SIGNAL nl10l : STD_LOGIC := '0';
SIGNAL nl10O : STD_LOGIC := '0';
SIGNAL nl11i : STD_LOGIC := '0';
SIGNAL nl11l : STD_LOGIC := '0';
SIGNAL nl11O : STD_LOGIC := '0';
SIGNAL nl1ii : STD_LOGIC := '0';
SIGNAL nl1il : STD_LOGIC := '0';
SIGNAL nl1iO : STD_LOGIC := '0';
SIGNAL nl1li : STD_LOGIC := '0';
SIGNAL nllil : STD_LOGIC := '0';
SIGNAL nllli : STD_LOGIC := '0';
SIGNAL nlO0ll : STD_LOGIC := '0';
SIGNAL wire_nlliO_w_lg_w_lg_n0i10O219w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0000l60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n00OOi254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n00OOO246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i10i230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i10O219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i11l238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1il205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1li183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1lO168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0000l72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n00OlO253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n00OOl245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i10l218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i11i237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i11O229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1ii204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1iO182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n0i1ll167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n10ii771w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlliO_w_lg_n1iOO161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n001Ol : STD_LOGIC := '0';
SIGNAL n1Ol0l : STD_LOGIC := '0';
SIGNAL ni0l0l : STD_LOGIC := '0';
SIGNAL nlllil : STD_LOGIC := '0';
SIGNAL wire_nlllii_w_lg_nlllil2715w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0001l : STD_LOGIC := '0';
SIGNAL n1l0O : STD_LOGIC := '0';
SIGNAL n1lii : STD_LOGIC := '0';
SIGNAL n1lil : STD_LOGIC := '0';
SIGNAL n1liO : STD_LOGIC := '0';
SIGNAL nlllO : STD_LOGIC := '0';
SIGNAL wire_nllll_CLRN : STD_LOGIC;
SIGNAL wire_nllll_PRN : STD_LOGIC;
SIGNAL wire_nllll_w_lg_w_lg_w_lg_n1liO362w363w364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nllll_w_lg_w_lg_n1liO362w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nllll_w_lg_n1liO362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n000O_dataout : STD_LOGIC;
SIGNAL wire_n000O_w_lg_dataout274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0011i_dataout : STD_LOGIC;
SIGNAL wire_n001O_dataout : STD_LOGIC;
SIGNAL wire_n001O_w_lg_dataout269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n00i0O_dataout : STD_LOGIC;
SIGNAL wire_n00ill_dataout : STD_LOGIC;
SIGNAL wire_n00iO_dataout : STD_LOGIC;
SIGNAL wire_n00iO_w_lg_dataout280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n00l0O_dataout : STD_LOGIC;
SIGNAL wire_n00l1i_dataout : STD_LOGIC;
SIGNAL wire_n00lll_dataout : STD_LOGIC;
SIGNAL wire_n00lO_dataout : STD_LOGIC;
SIGNAL wire_n00lO_w_lg_dataout287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n00O0O_dataout : STD_LOGIC;
SIGNAL wire_n00O1i_dataout : STD_LOGIC;
SIGNAL wire_n00Oll_dataout : STD_LOGIC;
SIGNAL wire_n00OO_dataout : STD_LOGIC;
SIGNAL wire_n00OO_w_lg_dataout295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0100i_dataout : STD_LOGIC;
SIGNAL wire_n0100l_dataout : STD_LOGIC;
SIGNAL wire_n0101i_dataout : STD_LOGIC;
SIGNAL wire_n0101O_dataout : STD_LOGIC;
SIGNAL wire_n010i_dataout : STD_LOGIC;
SIGNAL wire_n010ii_dataout : STD_LOGIC;
SIGNAL wire_n010il_dataout : STD_LOGIC;
SIGNAL wire_n010iO_dataout : STD_LOGIC;
SIGNAL wire_n010l_dataout : STD_LOGIC;
SIGNAL wire_n010li_dataout : STD_LOGIC;
SIGNAL wire_n010ll_dataout : STD_LOGIC;
SIGNAL wire_n010lO_dataout : STD_LOGIC;
SIGNAL wire_n010O_dataout : STD_LOGIC;
SIGNAL wire_n010Oi_dataout : STD_LOGIC;
SIGNAL wire_n010Ol_dataout : STD_LOGIC;
SIGNAL wire_n010OO_dataout : STD_LOGIC;
SIGNAL wire_n011Oi_dataout : STD_LOGIC;
SIGNAL wire_n011Ol_dataout : STD_LOGIC;
SIGNAL wire_n011OO_dataout : STD_LOGIC;
SIGNAL wire_n01i0i_dataout : STD_LOGIC;
SIGNAL wire_n01i0l_dataout : STD_LOGIC;
SIGNAL wire_n01i0O_dataout : STD_LOGIC;
SIGNAL wire_n01i1i_dataout : STD_LOGIC;
SIGNAL wire_n01ii_dataout : STD_LOGIC;
SIGNAL wire_n01iii_dataout : STD_LOGIC;
SIGNAL wire_n01iil_dataout : STD_LOGIC;
SIGNAL wire_n01il_dataout : STD_LOGIC;
SIGNAL wire_n01il_w_lg_dataout1489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01il_w_lg_dataout305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01ili_dataout : STD_LOGIC;
SIGNAL wire_n01ill_dataout : STD_LOGIC;
SIGNAL wire_n01ilO_dataout : STD_LOGIC;
SIGNAL wire_n01iOi_dataout : STD_LOGIC;
SIGNAL wire_n01iOO_dataout : STD_LOGIC;
SIGNAL wire_n01l0i_dataout : STD_LOGIC;
SIGNAL wire_n01l1i_dataout : STD_LOGIC;
SIGNAL wire_n01l1l_dataout : STD_LOGIC;
SIGNAL wire_n01l1O_dataout : STD_LOGIC;
SIGNAL wire_n01li_dataout : STD_LOGIC;
SIGNAL wire_n01li_w_lg_dataout260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01lO_dataout : STD_LOGIC;
SIGNAL wire_n01lO_w_lg_dataout262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01lOi_dataout : STD_LOGIC;
SIGNAL wire_n01lOl_dataout : STD_LOGIC;
SIGNAL wire_n01lOO_dataout : STD_LOGIC;
SIGNAL wire_n01O0l_dataout : STD_LOGIC;
SIGNAL wire_n01O0O_dataout : STD_LOGIC;
SIGNAL wire_n01O1i_dataout : STD_LOGIC;
SIGNAL wire_n01O1l_dataout : STD_LOGIC;
SIGNAL wire_n01Oii_dataout : STD_LOGIC;
SIGNAL wire_n01Oil_dataout : STD_LOGIC;
SIGNAL wire_n01OiO_dataout : STD_LOGIC;
SIGNAL wire_n01Oli_dataout : STD_LOGIC;
SIGNAL wire_n01Oll_dataout : STD_LOGIC;
SIGNAL wire_n01OlO_dataout : STD_LOGIC;
SIGNAL wire_n01OO_dataout : STD_LOGIC;
SIGNAL wire_n01OO_w_lg_dataout265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n01OOO_dataout : STD_LOGIC;
SIGNAL wire_n0i0O_dataout : STD_LOGIC;
SIGNAL wire_n0i1O_dataout : STD_LOGIC;
SIGNAL wire_n0i1O_w_lg_dataout1481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0iii_dataout : STD_LOGIC;
SIGNAL wire_n0iil_dataout : STD_LOGIC;
SIGNAL wire_n0iiO_dataout : STD_LOGIC;
SIGNAL wire_n0ili_dataout : STD_LOGIC;
SIGNAL wire_n0ill_dataout : STD_LOGIC;
SIGNAL wire_n0ilO_dataout : STD_LOGIC;
SIGNAL wire_n0iOi_dataout : STD_LOGIC;
SIGNAL wire_n0iOl_dataout : STD_LOGIC;
SIGNAL wire_n0iOO_dataout : STD_LOGIC;
SIGNAL wire_n0l0i_dataout : STD_LOGIC;
SIGNAL wire_n0l0ii_dataout : STD_LOGIC;
SIGNAL wire_n0l0ii_w_lg_w_lg_dataout862w2579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0l0ii_w_lg_dataout862w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0l0l_dataout : STD_LOGIC;
SIGNAL wire_n0l0O_dataout : STD_LOGIC;
SIGNAL wire_n0l1i_dataout : STD_LOGIC;
SIGNAL wire_n0l1l_dataout : STD_LOGIC;
SIGNAL wire_n0l1O_dataout : STD_LOGIC;
SIGNAL wire_n0lii_dataout : STD_LOGIC;
SIGNAL wire_n0lil_dataout : STD_LOGIC;
SIGNAL wire_n0liO_dataout : STD_LOGIC;
SIGNAL wire_n0lli_dataout : STD_LOGIC;
SIGNAL wire_n0lll_dataout : STD_LOGIC;
SIGNAL wire_n0llO_dataout : STD_LOGIC;
SIGNAL wire_n0lOi_dataout : STD_LOGIC;
SIGNAL wire_n0lOl_dataout : STD_LOGIC;
SIGNAL wire_n0lOO_dataout : STD_LOGIC;
SIGNAL wire_n0O0i_dataout : STD_LOGIC;
SIGNAL wire_n0O0l_dataout : STD_LOGIC;
SIGNAL wire_n0O0O_dataout : STD_LOGIC;
SIGNAL wire_n0O1i_dataout : STD_LOGIC;
SIGNAL wire_n0O1l_dataout : STD_LOGIC;
SIGNAL wire_n0O1O_dataout : STD_LOGIC;
SIGNAL wire_n0Oii_dataout : STD_LOGIC;
SIGNAL wire_n0Oil_dataout : STD_LOGIC;
SIGNAL wire_n0OiO_dataout : STD_LOGIC;
SIGNAL wire_n0Oli_dataout : STD_LOGIC;
SIGNAL wire_n0Oll_dataout : STD_LOGIC;
SIGNAL wire_n0OlO_dataout : STD_LOGIC;
SIGNAL wire_n0OOi_dataout : STD_LOGIC;
SIGNAL wire_n0OOl_dataout : STD_LOGIC;
SIGNAL wire_n0OOlO_dataout : STD_LOGIC;
SIGNAL wire_n0OOO_dataout : STD_LOGIC;
SIGNAL wire_n1i0i_dataout : STD_LOGIC;
SIGNAL wire_n1i0l_dataout : STD_LOGIC;
SIGNAL wire_n1i0O_dataout : STD_LOGIC;
SIGNAL wire_n1i1l_dataout : STD_LOGIC;
SIGNAL wire_n1i1O_dataout : STD_LOGIC;
SIGNAL wire_n1iii_dataout : STD_LOGIC;
SIGNAL wire_n1iil_dataout : STD_LOGIC;
SIGNAL wire_n1iiO_dataout : STD_LOGIC;
SIGNAL wire_n1Olii_dataout : STD_LOGIC;
SIGNAL wire_n1Olil_dataout : STD_LOGIC;
SIGNAL wire_n1OliO_dataout : STD_LOGIC;
SIGNAL wire_ni000i_dataout : STD_LOGIC;
SIGNAL wire_ni000l_dataout : STD_LOGIC;
SIGNAL wire_ni000O_dataout : STD_LOGIC;
SIGNAL wire_ni001l_dataout : STD_LOGIC;
SIGNAL wire_ni001O_dataout : STD_LOGIC;
SIGNAL wire_ni00i_dataout : STD_LOGIC;
SIGNAL wire_ni00ii_dataout : STD_LOGIC;
SIGNAL wire_ni00il_dataout : STD_LOGIC;
SIGNAL wire_ni00iO_dataout : STD_LOGIC;
SIGNAL wire_ni00l_dataout : STD_LOGIC;
SIGNAL wire_ni00li_dataout : STD_LOGIC;
SIGNAL wire_ni00ll_dataout : STD_LOGIC;
SIGNAL wire_ni00lO_dataout : STD_LOGIC;
SIGNAL wire_ni00O_dataout : STD_LOGIC;
SIGNAL wire_ni00OO_dataout : STD_LOGIC;
SIGNAL wire_ni01i_dataout : STD_LOGIC;
SIGNAL wire_ni01l_dataout : STD_LOGIC;
SIGNAL wire_ni01lO_dataout : STD_LOGIC;
SIGNAL wire_ni01O_dataout : STD_LOGIC;
SIGNAL wire_ni0i0l_dataout : STD_LOGIC;
SIGNAL wire_ni0i0O_dataout : STD_LOGIC;
SIGNAL wire_ni0i1i_dataout : STD_LOGIC;
SIGNAL wire_ni0i1l_dataout : STD_LOGIC;
SIGNAL wire_ni0i1O_dataout : STD_LOGIC;
SIGNAL wire_ni0ii_dataout : STD_LOGIC;
SIGNAL wire_ni0iii_dataout : STD_LOGIC;
SIGNAL wire_ni0iil_dataout : STD_LOGIC;
SIGNAL wire_ni0iiO_dataout : STD_LOGIC;
SIGNAL wire_ni0il_dataout : STD_LOGIC;
SIGNAL wire_ni0ilO_dataout : STD_LOGIC;
SIGNAL wire_ni0iO_dataout : STD_LOGIC;
SIGNAL wire_ni0iOi_dataout : STD_LOGIC;
SIGNAL wire_ni0li_dataout : STD_LOGIC;
SIGNAL wire_ni0lii_dataout : STD_LOGIC;
SIGNAL wire_ni0lii_w_lg_dataout2438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lil_dataout : STD_LOGIC;
SIGNAL wire_ni0lil_w_lg_dataout2436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0liO_dataout : STD_LOGIC;
SIGNAL wire_ni0ll_dataout : STD_LOGIC;
SIGNAL wire_ni0lli_dataout : STD_LOGIC;
SIGNAL wire_ni0lli_w_lg_dataout2433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lll_dataout : STD_LOGIC;
SIGNAL wire_ni0lll_w_lg_dataout2431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0llO_dataout : STD_LOGIC;
SIGNAL wire_ni0llO_w_lg_dataout2429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lO_dataout : STD_LOGIC;
SIGNAL wire_ni0lOi_dataout : STD_LOGIC;
SIGNAL wire_ni0lOi_w_lg_dataout2427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_dataout : STD_LOGIC;
SIGNAL wire_ni0lOl_w_lg_w2434w2435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_w2434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_w_lg_w_lg_w_lg_w_lg_dataout2426w2428w2430w2432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_w_lg_w_lg_w_lg_dataout2426w2428w2430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_w_lg_w_lg_dataout2426w2428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0lOl_w_lg_dataout2426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0Oi_dataout : STD_LOGIC;
SIGNAL wire_ni0Ol_dataout : STD_LOGIC;
SIGNAL wire_ni0Oli_dataout : STD_LOGIC;
SIGNAL wire_ni0Oll_dataout : STD_LOGIC;
SIGNAL wire_ni0OlO_dataout : STD_LOGIC;
SIGNAL wire_ni0OO_dataout : STD_LOGIC;
SIGNAL wire_ni0OOi_dataout : STD_LOGIC;
SIGNAL wire_ni10i_dataout : STD_LOGIC;
SIGNAL wire_ni10l_dataout : STD_LOGIC;
SIGNAL wire_ni10O_dataout : STD_LOGIC;
SIGNAL wire_ni11i_dataout : STD_LOGIC;
SIGNAL wire_ni11l_dataout : STD_LOGIC;
SIGNAL wire_ni11O_dataout : STD_LOGIC;
SIGNAL wire_ni1ii_dataout : STD_LOGIC;
SIGNAL wire_ni1il_dataout : STD_LOGIC;
SIGNAL wire_ni1iO_dataout : STD_LOGIC;
SIGNAL wire_ni1li_dataout : STD_LOGIC;
SIGNAL wire_ni1ll_dataout : STD_LOGIC;
SIGNAL wire_ni1lO_dataout : STD_LOGIC;
SIGNAL wire_ni1O0i_dataout : STD_LOGIC;
SIGNAL wire_ni1O0l_dataout : STD_LOGIC;
SIGNAL wire_ni1O1l_dataout : STD_LOGIC;
SIGNAL wire_ni1O1O_dataout : STD_LOGIC;
SIGNAL wire_ni1Oi_dataout : STD_LOGIC;
SIGNAL wire_ni1Oil_dataout : STD_LOGIC;
SIGNAL wire_ni1OiO_dataout : STD_LOGIC;
SIGNAL wire_ni1Ol_dataout : STD_LOGIC;
SIGNAL wire_ni1Oll_dataout : STD_LOGIC;
SIGNAL wire_ni1OlO_dataout : STD_LOGIC;
SIGNAL wire_ni1OO_dataout : STD_LOGIC;
SIGNAL wire_nii0i_dataout : STD_LOGIC;
SIGNAL wire_nii0l_dataout : STD_LOGIC;
SIGNAL wire_nii0O_dataout : STD_LOGIC;
SIGNAL wire_nii1i_dataout : STD_LOGIC;
SIGNAL wire_nii1l_dataout : STD_LOGIC;
SIGNAL wire_nii1O_dataout : STD_LOGIC;
SIGNAL wire_niii1i_dataout : STD_LOGIC;
SIGNAL wire_niii1i_w_lg_dataout2009w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiii_dataout : STD_LOGIC;
SIGNAL wire_niiil_dataout : STD_LOGIC;
SIGNAL wire_niiiO_dataout : STD_LOGIC;
SIGNAL wire_niil0i_dataout : STD_LOGIC;
SIGNAL wire_niil0l_dataout : STD_LOGIC;
SIGNAL wire_niil0O_dataout : STD_LOGIC;
SIGNAL wire_niil1l_dataout : STD_LOGIC;
SIGNAL wire_niil1O_dataout : STD_LOGIC;
SIGNAL wire_niili_dataout : STD_LOGIC;
SIGNAL wire_niilii_dataout : STD_LOGIC;
SIGNAL wire_niilil_dataout : STD_LOGIC;
SIGNAL wire_niiliO_dataout : STD_LOGIC;
SIGNAL wire_niill_dataout : STD_LOGIC;
SIGNAL wire_niilli_dataout : STD_LOGIC;
SIGNAL wire_niilll_dataout : STD_LOGIC;
SIGNAL wire_niillO_dataout : STD_LOGIC;
SIGNAL wire_niilO_dataout : STD_LOGIC;
SIGNAL wire_niilOi_dataout : STD_LOGIC;
SIGNAL wire_niilOl_dataout : STD_LOGIC;
SIGNAL wire_niilOO_dataout : STD_LOGIC;
SIGNAL wire_niiO1i_dataout : STD_LOGIC;
SIGNAL wire_niiOi_dataout : STD_LOGIC;
SIGNAL wire_niiOl_dataout : STD_LOGIC;
SIGNAL wire_niiOO_dataout : STD_LOGIC;
SIGNAL wire_niiOOO_dataout : STD_LOGIC;
SIGNAL wire_nil10i_dataout : STD_LOGIC;
SIGNAL wire_nil10l_dataout : STD_LOGIC;
SIGNAL wire_nil10O_dataout : STD_LOGIC;
SIGNAL wire_nil11i_dataout : STD_LOGIC;
SIGNAL wire_nil11l_dataout : STD_LOGIC;
SIGNAL wire_nil11O_dataout : STD_LOGIC;
SIGNAL wire_nil1i_dataout : STD_LOGIC;
SIGNAL wire_nil1ii_dataout : STD_LOGIC;
SIGNAL wire_nil1il_dataout : STD_LOGIC;
SIGNAL wire_nil1iO_dataout : STD_LOGIC;
SIGNAL wire_nil1l_dataout : STD_LOGIC;
SIGNAL wire_nil1li_dataout : STD_LOGIC;
SIGNAL wire_nil1ll_dataout : STD_LOGIC;
SIGNAL wire_nil1lO_dataout : STD_LOGIC;
SIGNAL wire_nil1O_dataout : STD_LOGIC;
SIGNAL wire_nil1Oi_dataout : STD_LOGIC;
SIGNAL wire_nl00i_dataout : STD_LOGIC;
SIGNAL wire_nl00l_dataout : STD_LOGIC;
SIGNAL wire_nl00O_dataout : STD_LOGIC;
SIGNAL wire_nl01i_dataout : STD_LOGIC;
SIGNAL wire_nl01l_dataout : STD_LOGIC;
SIGNAL wire_nl01O_dataout : STD_LOGIC;
SIGNAL wire_nl0ii_dataout : STD_LOGIC;
SIGNAL wire_nl0il_dataout : STD_LOGIC;
SIGNAL wire_nl0iO_dataout : STD_LOGIC;
SIGNAL wire_nl0li_dataout : STD_LOGIC;
SIGNAL wire_nl0ll_dataout : STD_LOGIC;
SIGNAL wire_nl0lO_dataout : STD_LOGIC;
SIGNAL wire_nl0Oi_dataout : STD_LOGIC;
SIGNAL wire_nl0Ol_dataout : STD_LOGIC;
SIGNAL wire_nl0OO_dataout : STD_LOGIC;
SIGNAL wire_nl1Ol_dataout : STD_LOGIC;
SIGNAL wire_nl1OO_dataout : STD_LOGIC;
SIGNAL wire_nli0i_dataout : STD_LOGIC;
SIGNAL wire_nli0l_dataout : STD_LOGIC;
SIGNAL wire_nli0O_dataout : STD_LOGIC;
SIGNAL wire_nli1i_dataout : STD_LOGIC;
SIGNAL wire_nli1l_dataout : STD_LOGIC;
SIGNAL wire_nli1O_dataout : STD_LOGIC;
SIGNAL wire_nliii_dataout : STD_LOGIC;
SIGNAL wire_nliil_dataout : STD_LOGIC;
SIGNAL wire_nliiO_dataout : STD_LOGIC;
SIGNAL wire_nliOl_dataout : STD_LOGIC;
SIGNAL wire_nliOO_dataout : STD_LOGIC;
SIGNAL wire_nll0i_dataout : STD_LOGIC;
SIGNAL wire_nll1i_dataout : STD_LOGIC;
SIGNAL wire_nll1l_dataout : STD_LOGIC;
SIGNAL wire_nll1O_dataout : STD_LOGIC;
SIGNAL wire_nlOi0O_dataout : STD_LOGIC;
SIGNAL wire_nlOiii_dataout : STD_LOGIC;
SIGNAL wire_nlOiil_dataout : STD_LOGIC;
SIGNAL wire_nlOiiO_dataout : STD_LOGIC;
SIGNAL wire_nlOili_dataout : STD_LOGIC;
SIGNAL wire_nlOill_dataout : STD_LOGIC;
SIGNAL wire_nlOilO_dataout : STD_LOGIC;
SIGNAL wire_nlOiOi_dataout : STD_LOGIC;
SIGNAL wire_nlOiOl_dataout : STD_LOGIC;
SIGNAL wire_nlOiOO_dataout : STD_LOGIC;
SIGNAL wire_nlOl0i_dataout : STD_LOGIC;
SIGNAL wire_nlOl0l_dataout : STD_LOGIC;
SIGNAL wire_nlOl0O_dataout : STD_LOGIC;
SIGNAL wire_nlOl1i_dataout : STD_LOGIC;
SIGNAL wire_nlOl1l_dataout : STD_LOGIC;
SIGNAL wire_nlOl1O_dataout : STD_LOGIC;
SIGNAL wire_nlOlii_dataout : STD_LOGIC;
SIGNAL wire_nlOlil_dataout : STD_LOGIC;
SIGNAL wire_nlOliO_dataout : STD_LOGIC;
SIGNAL wire_nlOlli_dataout : STD_LOGIC;
SIGNAL wire_nlOlOO_dataout : STD_LOGIC;
SIGNAL wire_nlOO0i_dataout : STD_LOGIC;
SIGNAL wire_nlOO0l_dataout : STD_LOGIC;
SIGNAL wire_nlOO0O_dataout : STD_LOGIC;
SIGNAL wire_nlOO1i_dataout : STD_LOGIC;
SIGNAL wire_nlOO1l_dataout : STD_LOGIC;
SIGNAL wire_nlOO1O_dataout : STD_LOGIC;
SIGNAL wire_nlOOii_dataout : STD_LOGIC;
SIGNAL wire_n01iiO_a : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n01iiO_b : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_n01iiO_o : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n1ili_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n1ili_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n1ili_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni0lOO_a : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_ni0lOO_b : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_ni0lOO_o : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_ni1O0O_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1O0O_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1O0O_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1Oii_a : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni1Oii_b : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni1Oii_o : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni0OOl_a : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_ni0OOl_b : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_ni0OOl_o : STD_LOGIC;
SIGNAL wire_n00i0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00i0l_o : STD_LOGIC;
SIGNAL wire_n00i0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00ili_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00ili_o : STD_LOGIC;
SIGNAL wire_n00ili_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00iOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00iOO_o : STD_LOGIC;
SIGNAL wire_n00iOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00l0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00l0l_o : STD_LOGIC;
SIGNAL wire_n00l0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00lli_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00lli_o : STD_LOGIC;
SIGNAL wire_n00lli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00lOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00lOO_o : STD_LOGIC;
SIGNAL wire_n00lOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00O0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00O0l_o : STD_LOGIC;
SIGNAL wire_n00O0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n00Oli_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00Oli_o : STD_LOGIC;
SIGNAL wire_n00Oli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n100i_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n100i_o : STD_LOGIC;
SIGNAL wire_n100i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n100l_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n100l_o : STD_LOGIC;
SIGNAL wire_n100l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n100O_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n100O_o : STD_LOGIC;
SIGNAL wire_n100O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n101i_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n101i_o : STD_LOGIC;
SIGNAL wire_n101i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n101l_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n101l_o : STD_LOGIC;
SIGNAL wire_n101l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n101O_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n101O_o : STD_LOGIC;
SIGNAL wire_n101O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n11lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n11lO_o : STD_LOGIC;
SIGNAL wire_n11lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n11Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n11Oi_o : STD_LOGIC;
SIGNAL wire_n11Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n11Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n11Ol_o : STD_LOGIC;
SIGNAL wire_n11Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n11OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_n11OO_o : STD_LOGIC;
SIGNAL wire_n11OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_n0110i_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0110i_o : STD_LOGIC;
SIGNAL wire_n0110i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0110O_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n0110O_o : STD_LOGIC;
SIGNAL wire_n0110O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n0111l_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0111l_o : STD_LOGIC;
SIGNAL wire_n0111l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n011il_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n011il_o : STD_LOGIC;
SIGNAL wire_n011il_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n011li_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n011li_o : STD_LOGIC;
SIGNAL wire_n011li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n011lO_data : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n011lO_o : STD_LOGIC;
SIGNAL wire_n011lO_sel : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n1OllO_data : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_n1OllO_o : STD_LOGIC;
SIGNAL wire_n1OllO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_n1OlOi_data : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_n1OlOi_o : STD_LOGIC;
SIGNAL wire_n1OlOi_sel : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_n1OlOO_data : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_n1OlOO_o : STD_LOGIC;
SIGNAL wire_n1OlOO_sel : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_n1OO0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OO0i_o : STD_LOGIC;
SIGNAL wire_n1OO0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OO0O_data : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n1OO0O_o : STD_LOGIC;
SIGNAL wire_n1OO0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_n1OO1l_data : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n1OO1l_o : STD_LOGIC;
SIGNAL wire_n1OO1l_sel : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n1OO1O_data : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n1OO1O_o : STD_LOGIC;
SIGNAL wire_n1OO1O_sel : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_n1OOii_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOii_o : STD_LOGIC;
SIGNAL wire_n1OOii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OOiO_o : STD_LOGIC;
SIGNAL wire_n1OOiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OOll_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOll_o : STD_LOGIC;
SIGNAL wire_n1OOll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOOi_o : STD_LOGIC;
SIGNAL wire_n1OOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1OOOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OOOO_o : STD_LOGIC;
SIGNAL wire_n1OOOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni010i_data : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni010i_o : STD_LOGIC;
SIGNAL wire_ni010i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni010l_data : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni010l_o : STD_LOGIC;
SIGNAL wire_ni010l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni010O_data : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni010O_o : STD_LOGIC;
SIGNAL wire_ni010O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni011i_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni011i_o : STD_LOGIC;
SIGNAL wire_ni011i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni011O_data : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni011O_o : STD_LOGIC;
SIGNAL wire_ni011O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_ni01iO_data : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_ni01iO_o : STD_LOGIC;
SIGNAL wire_ni01iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_ni01ll_data : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ni01ll_o : STD_LOGIC;
SIGNAL wire_ni01ll_sel : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ni01Oi_data : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_ni01Oi_o : STD_LOGIC;
SIGNAL wire_ni01Oi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_ni01OO_data : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ni01OO_o : STD_LOGIC;
SIGNAL wire_ni01OO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ni1OOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OOi_o : STD_LOGIC;
SIGNAL wire_ni1OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OOl_o : STD_LOGIC;
SIGNAL wire_ni1OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OOO_o : STD_LOGIC;
SIGNAL wire_ni1OOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlili_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlili_o : STD_LOGIC;
SIGNAL wire_nlili_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlill_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlill_o : STD_LOGIC;
SIGNAL wire_nlill_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlilO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlilO_o : STD_LOGIC;
SIGNAL wire_nlilO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nliOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nliOi_o : STD_LOGIC;
SIGNAL wire_nliOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOil_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOil_o : STD_LOGIC;
SIGNAL wire_nlOOil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOiO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOiO_o : STD_LOGIC;
SIGNAL wire_nlOOiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOli_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOli_o : STD_LOGIC;
SIGNAL wire_nlOOli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOll_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOll_o : STD_LOGIC;
SIGNAL wire_nlOOll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOlO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOlO_o : STD_LOGIC;
SIGNAL wire_nlOOlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOi_o : STD_LOGIC;
SIGNAL wire_nlOOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOl_o : STD_LOGIC;
SIGNAL wire_nlOOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOOOO_o : STD_LOGIC;
SIGNAL wire_nlOOOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1lOll206w209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1O0Ol52w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1O11l184w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_GE_XAUI_SEL2752w2753w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1011l2772w2773w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1678w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1663w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w1953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_SYNC_SM_DIS876w877w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1l1iO867w868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_GE_XAUI_SEL2751w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l00l2548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l00l848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l01O850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l10i2457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l10l2454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ll0O255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1llil247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1llli239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lllO231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lO1O223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lOll206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O0Ol52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O11l184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O1li169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1659w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1649w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH874w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1598w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH1584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_SYNC_SM_DIS873w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_IB_INVALID_CODE_range2446w2452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_IB_INVALID_CODE_range2453w2461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_SYNC_COMP_SIZE_range895w900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_DISABLE_RX_DISP844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_GE_XAUI_SEL2752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1001l2475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n100lO2238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n100Oi2210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n100OO2188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1011i2824w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1011l2772w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1011O2750w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10i0l2156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10i1O2183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iil1997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iiO1996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10ili1995w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10ill1994w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10ilO1993w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iOi1992w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iOl1991w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iOO1961w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l0i1957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l0l1956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l0O1955w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l1i1960w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l1l1959w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10l1O1958w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10lli1926w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10lll1924w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10llO1986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10lOi1930w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10lOl1922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10lOO1920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10O0l1871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10O0O1869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10O1i1928w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10Oii1976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10Oil1875w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10OiO1867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10Oli1865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10Oll1873w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10OOO1816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11lli2976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11O0l2776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11O0O2761w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11Oii2759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11OiO2992w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11Oli2749w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11Oll2746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i00l1881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i00O1885w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i01i1764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i01l2424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i01O1879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0ii1890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0il1896w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0iO1903w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0li1911w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0ll2414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0Oi1824w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0OO1969w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i10i1812w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i10l1810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i10O1818w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i11i1814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i11l1951w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i11O1820w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1li1762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1ll1760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1lO1942w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1Oi1766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1Ol1758w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i1OO1756w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ii0O1830w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ii1i1979w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ii1O1826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iiiO1835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iilO1841w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iiOi1848w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iiOl1856w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il0i1642w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il0l1776w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il0O1781w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il1l2404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il1O1770w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ilii1787w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ilil1794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iliO1802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1illl2394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1illO1611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ilOi1715w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ilOl1608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ilOO1935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO0i1597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO0l1595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO0O1721w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO1i1604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO1l1602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iO1O1717w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOii1590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOil1588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOiO1726w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOli1583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOll1581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOlO1732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOOi1739w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1iOOl1747w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0ll842w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0lO774w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l10O879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1liii321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1liiO318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lili316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lill314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1lilO312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1liOi310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1liOl308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1liOO306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1ll1i304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O00O64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O0ll54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1O0OO65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1Oi1O59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1OiiO39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rcvd_clk43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_soft_reset46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_SYNC_SM_DIS876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_SYNC_COMP_SIZE_range897w898w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1iO1i1604w1775w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1iO1i1604w1780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1iO1i1604w1786w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1iO1i1604w1793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1iO1i1604w1801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w2020w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w2013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH131w2004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2020w2021w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2013w2014w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2004w2005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2022w2023w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2015w2016w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2006w2007w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2022w2023w2024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2015w2016w2017w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2006w2007w2008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w852w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2054w2055w2056w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2046w2047w2048w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2038w2039w2040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w2030w2031w2032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w852w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2054w2055w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2046w2047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2038w2039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2030w2031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1l0il846w847w849w851w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2054w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2046w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w2030w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_n1l0il846w847w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH2051w2052w2053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH2043w2044w2045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH2035w2036w2037w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_PMADATAWIDTH2027w2028w2029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1l0il846w847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH2051w2052w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH2043w2044w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH2035w2036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_PMADATAWIDTH2027w2028w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1000i2549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1000i2464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1000l2465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i01l1921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i01l1978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0ll1866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1i0ll1968w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il1l1811w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1il1l1944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1illl1934w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1illl1757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l01i2468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0ii2467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0il2466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0il846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l10i2486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l10l2485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l1iO867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l1ll860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l1lO861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l1Ol857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2097w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2051w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2043w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_PMADATAWIDTH2027w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1000i : STD_LOGIC;
SIGNAL n1000l : STD_LOGIC;
SIGNAL n1000O : STD_LOGIC;
SIGNAL n1001i : STD_LOGIC;
SIGNAL n1001l : STD_LOGIC;
SIGNAL n1001O : STD_LOGIC;
SIGNAL n100ii : STD_LOGIC;
SIGNAL n100il : STD_LOGIC;
SIGNAL n100iO : STD_LOGIC;
SIGNAL n100li : STD_LOGIC;
SIGNAL n100ll : STD_LOGIC;
SIGNAL n100lO : STD_LOGIC;
SIGNAL n100Oi : STD_LOGIC;
SIGNAL n100Ol : STD_LOGIC;
SIGNAL n100OO : STD_LOGIC;
SIGNAL n1010i : STD_LOGIC;
SIGNAL n1010l : STD_LOGIC;
SIGNAL n1010O : STD_LOGIC;
SIGNAL n1011i : STD_LOGIC;
SIGNAL n1011l : STD_LOGIC;
SIGNAL n1011O : STD_LOGIC;
SIGNAL n101ii : STD_LOGIC;
SIGNAL n101il : STD_LOGIC;
SIGNAL n101iO : STD_LOGIC;
SIGNAL n101li : STD_LOGIC;
SIGNAL n101ll : STD_LOGIC;
SIGNAL n101lO : STD_LOGIC;
SIGNAL n101Oi : STD_LOGIC;
SIGNAL n101Ol : STD_LOGIC;
SIGNAL n101OO : STD_LOGIC;
SIGNAL n10i0i : STD_LOGIC;
SIGNAL n10i0l : STD_LOGIC;
SIGNAL n10i0O : STD_LOGIC;
SIGNAL n10i1i : STD_LOGIC;
SIGNAL n10i1l : STD_LOGIC;
SIGNAL n10i1O : STD_LOGIC;
SIGNAL n10iii : STD_LOGIC;
SIGNAL n10iil : STD_LOGIC;
SIGNAL n10iiO : STD_LOGIC;
SIGNAL n10ili : STD_LOGIC;
SIGNAL n10ill : STD_LOGIC;
SIGNAL n10ilO : STD_LOGIC;
SIGNAL n10iOi : STD_LOGIC;
SIGNAL n10iOl : STD_LOGIC;
SIGNAL n10iOO : STD_LOGIC;
SIGNAL n10l0i : STD_LOGIC;
SIGNAL n10l0l : STD_LOGIC;
SIGNAL n10l0O : STD_LOGIC;
SIGNAL n10l1i : STD_LOGIC;
SIGNAL n10l1l : STD_LOGIC;
SIGNAL n10l1O : STD_LOGIC;
SIGNAL n10lii : STD_LOGIC;
SIGNAL n10lil : STD_LOGIC;
SIGNAL n10liO : STD_LOGIC;
SIGNAL n10lli : STD_LOGIC;
SIGNAL n10lll : STD_LOGIC;
SIGNAL n10llO : STD_LOGIC;
SIGNAL n10lOi : STD_LOGIC;
SIGNAL n10lOl : STD_LOGIC;
SIGNAL n10lOO : STD_LOGIC;
SIGNAL n10O0i : STD_LOGIC;
SIGNAL n10O0l : STD_LOGIC;
SIGNAL n10O0O : STD_LOGIC;
SIGNAL n10O1i : STD_LOGIC;
SIGNAL n10O1l : STD_LOGIC;
SIGNAL n10O1O : STD_LOGIC;
SIGNAL n10Oii : STD_LOGIC;
SIGNAL n10Oil : STD_LOGIC;
SIGNAL n10OiO : STD_LOGIC;
SIGNAL n10Oli : STD_LOGIC;
SIGNAL n10Oll : STD_LOGIC;
SIGNAL n10OlO : STD_LOGIC;
SIGNAL n10OOi : STD_LOGIC;
SIGNAL n10OOl : STD_LOGIC;
SIGNAL n10OOO : STD_LOGIC;
SIGNAL n11lii : STD_LOGIC;
SIGNAL n11lil : STD_LOGIC;
SIGNAL n11liO : STD_LOGIC;
SIGNAL n11lli : STD_LOGIC;
SIGNAL n11lll : STD_LOGIC;
SIGNAL n11llO : STD_LOGIC;
SIGNAL n11lOi : STD_LOGIC;
SIGNAL n11lOl : STD_LOGIC;
SIGNAL n11lOO : STD_LOGIC;
SIGNAL n11O0i : STD_LOGIC;
SIGNAL n11O0l : STD_LOGIC;
SIGNAL n11O0O : STD_LOGIC;
SIGNAL n11O1i : STD_LOGIC;
SIGNAL n11O1l : STD_LOGIC;
SIGNAL n11O1O : STD_LOGIC;
SIGNAL n11Oii : STD_LOGIC;
SIGNAL n11Oil : STD_LOGIC;
SIGNAL n11OiO : STD_LOGIC;
SIGNAL n11Oli : STD_LOGIC;
SIGNAL n11Oll : STD_LOGIC;
SIGNAL n11OlO : STD_LOGIC;
SIGNAL n11OOi : STD_LOGIC;
SIGNAL n11OOl : STD_LOGIC;
SIGNAL n11OOO : STD_LOGIC;
SIGNAL n1i00i : STD_LOGIC;
SIGNAL n1i00l : STD_LOGIC;
SIGNAL n1i00O : STD_LOGIC;
SIGNAL n1i01i : STD_LOGIC;
SIGNAL n1i01l : STD_LOGIC;
SIGNAL n1i01O : STD_LOGIC;
SIGNAL n1i0ii : STD_LOGIC;
SIGNAL n1i0il : STD_LOGIC;
SIGNAL n1i0iO : STD_LOGIC;
SIGNAL n1i0li : STD_LOGIC;
SIGNAL n1i0ll : STD_LOGIC;
SIGNAL n1i0lO : STD_LOGIC;
SIGNAL n1i0Oi : STD_LOGIC;
SIGNAL n1i0Ol : STD_LOGIC;
SIGNAL n1i0OO : STD_LOGIC;
SIGNAL n1i10i : STD_LOGIC;
SIGNAL n1i10l : STD_LOGIC;
SIGNAL n1i10O : STD_LOGIC;
SIGNAL n1i11i : STD_LOGIC;
SIGNAL n1i11l : STD_LOGIC;
SIGNAL n1i11O : STD_LOGIC;
SIGNAL n1i1ii : STD_LOGIC;
SIGNAL n1i1il : STD_LOGIC;
SIGNAL n1i1iO : STD_LOGIC;
SIGNAL n1i1li : STD_LOGIC;
SIGNAL n1i1ll : STD_LOGIC;
SIGNAL n1i1lO : STD_LOGIC;
SIGNAL n1i1Oi : STD_LOGIC;
SIGNAL n1i1Ol : STD_LOGIC;
SIGNAL n1i1OO : STD_LOGIC;
SIGNAL n1ii0i : STD_LOGIC;
SIGNAL n1ii0l : STD_LOGIC;
SIGNAL n1ii0O : STD_LOGIC;
SIGNAL n1ii1i : STD_LOGIC;
SIGNAL n1ii1l : STD_LOGIC;
SIGNAL n1ii1O : STD_LOGIC;
SIGNAL n1iiii : STD_LOGIC;
SIGNAL n1iiil : STD_LOGIC;
SIGNAL n1iiiO : STD_LOGIC;
SIGNAL n1iili : STD_LOGIC;
SIGNAL n1iill : STD_LOGIC;
SIGNAL n1iilO : STD_LOGIC;
SIGNAL n1iiOi : STD_LOGIC;
SIGNAL n1iiOl : STD_LOGIC;
SIGNAL n1iiOO : STD_LOGIC;
SIGNAL n1il0i : STD_LOGIC;
SIGNAL n1il0l : STD_LOGIC;
SIGNAL n1il0O : STD_LOGIC;
SIGNAL n1il1i : STD_LOGIC;
SIGNAL n1il1l : STD_LOGIC;
SIGNAL n1il1O : STD_LOGIC;
SIGNAL n1ilii : STD_LOGIC;
SIGNAL n1ilil : STD_LOGIC;
SIGNAL n1iliO : STD_LOGIC;
SIGNAL n1illi : STD_LOGIC;
SIGNAL n1illl : STD_LOGIC;
SIGNAL n1illO : STD_LOGIC;
SIGNAL n1ilOi : STD_LOGIC;
SIGNAL n1ilOl : STD_LOGIC;
SIGNAL n1ilOO : STD_LOGIC;
SIGNAL n1iO0i : STD_LOGIC;
SIGNAL n1iO0l : STD_LOGIC;
SIGNAL n1iO0O : STD_LOGIC;
SIGNAL n1iO1i : STD_LOGIC;
SIGNAL n1iO1l : STD_LOGIC;
SIGNAL n1iO1O : STD_LOGIC;
SIGNAL n1iOii : STD_LOGIC;
SIGNAL n1iOil : STD_LOGIC;
SIGNAL n1iOiO : STD_LOGIC;
SIGNAL n1iOli : STD_LOGIC;
SIGNAL n1iOll : STD_LOGIC;
SIGNAL n1iOlO : STD_LOGIC;
SIGNAL n1iOOi : STD_LOGIC;
SIGNAL n1iOOl : STD_LOGIC;
SIGNAL n1iOOO : STD_LOGIC;
SIGNAL n1l00i : STD_LOGIC;
SIGNAL n1l00l : STD_LOGIC;
SIGNAL n1l00O : STD_LOGIC;
SIGNAL n1l01i : STD_LOGIC;
SIGNAL n1l01l : STD_LOGIC;
SIGNAL n1l01O : STD_LOGIC;
SIGNAL n1l0ii : STD_LOGIC;
SIGNAL n1l0il : STD_LOGIC;
SIGNAL n1l0iO : STD_LOGIC;
SIGNAL n1l0li : STD_LOGIC;
SIGNAL n1l0ll : STD_LOGIC;
SIGNAL n1l0lO : STD_LOGIC;
SIGNAL n1l0Oi : STD_LOGIC;
SIGNAL n1l0Ol : STD_LOGIC;
SIGNAL n1l10i : STD_LOGIC;
SIGNAL n1l10l : STD_LOGIC;
SIGNAL n1l10O : STD_LOGIC;
SIGNAL n1l11i : STD_LOGIC;
SIGNAL n1l11l : STD_LOGIC;
SIGNAL n1l11O : STD_LOGIC;
SIGNAL n1l1ii : STD_LOGIC;
SIGNAL n1l1il : STD_LOGIC;
SIGNAL n1l1iO : STD_LOGIC;
SIGNAL n1l1li : STD_LOGIC;
SIGNAL n1l1ll : STD_LOGIC;
SIGNAL n1l1lO : STD_LOGIC;
SIGNAL n1l1Oi : STD_LOGIC;
SIGNAL n1l1Ol : STD_LOGIC;
SIGNAL n1l1OO : STD_LOGIC;
SIGNAL n1li0i : STD_LOGIC;
SIGNAL n1li0O : STD_LOGIC;
SIGNAL n1li1l : STD_LOGIC;
SIGNAL n1li1O : STD_LOGIC;
SIGNAL n1liii : STD_LOGIC;
SIGNAL n1liil : STD_LOGIC;
SIGNAL n1liiO : STD_LOGIC;
SIGNAL n1lili : STD_LOGIC;
SIGNAL n1lill : STD_LOGIC;
SIGNAL n1lilO : STD_LOGIC;
SIGNAL n1liOi : STD_LOGIC;
SIGNAL n1liOl : STD_LOGIC;
SIGNAL n1liOO : STD_LOGIC;
SIGNAL n1ll0i : STD_LOGIC;
SIGNAL n1ll0l : STD_LOGIC;
SIGNAL n1ll0O : STD_LOGIC;
SIGNAL n1ll1i : STD_LOGIC;
SIGNAL n1ll1l : STD_LOGIC;
SIGNAL n1ll1O : STD_LOGIC;
SIGNAL n1llii : STD_LOGIC;
SIGNAL n1llil : STD_LOGIC;
SIGNAL n1lliO : STD_LOGIC;
SIGNAL n1llli : STD_LOGIC;
SIGNAL n1llll : STD_LOGIC;
SIGNAL n1lllO : STD_LOGIC;
SIGNAL n1llOi : STD_LOGIC;
SIGNAL n1lO0i : STD_LOGIC;
SIGNAL n1lO1O : STD_LOGIC;
SIGNAL n1lOll : STD_LOGIC;
SIGNAL n1lOlO : STD_LOGIC;
SIGNAL n1O00O : STD_LOGIC;
SIGNAL n1O0ll : STD_LOGIC;
SIGNAL n1O0lO : STD_LOGIC;
SIGNAL n1O0Oi : STD_LOGIC;
SIGNAL n1O0Ol : STD_LOGIC;
SIGNAL n1O0OO : STD_LOGIC;
SIGNAL n1O11l : STD_LOGIC;
SIGNAL n1O11O : STD_LOGIC;
SIGNAL n1O1li : STD_LOGIC;
SIGNAL n1O1ll : STD_LOGIC;
SIGNAL n1O1lO : STD_LOGIC;
SIGNAL n1O1Oi : STD_LOGIC;
SIGNAL n1Oi0i : STD_LOGIC;
SIGNAL n1Oi1O : STD_LOGIC;
SIGNAL n1Oiii : STD_LOGIC;
SIGNAL n1Oiil : STD_LOGIC;
SIGNAL n1OiiO : STD_LOGIC;
SIGNAL n1Oili : STD_LOGIC;
SIGNAL n1Ol1l : STD_LOGIC;
SIGNAL wire_w_IB_INVALID_CODE_range2446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_IB_INVALID_CODE_range2453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_SYNC_COMP_SIZE_range895w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_SYNC_COMP_SIZE_range897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_gnd <= '0';
wire_w_lg_w_lg_n1lOll206w209w(0) <= wire_w_lg_n1lOll206w(0) AND wire_n1lO0l44_w_lg_q208w(0);
wire_w_lg_w_lg_n1O0Ol52w53w(0) <= wire_w_lg_n1O0Ol52w(0) AND n1O0lO;
wire_w_lg_w_lg_n1O11l184w187w(0) <= wire_w_lg_n1O11l184w(0) AND wire_n1lOOO36_w_lg_q186w(0);
wire_w_lg_w_lg_GE_XAUI_SEL2752w2753w(0) <= wire_w_lg_GE_XAUI_SEL2752w(0) AND nlllil;
wire_w_lg_w_lg_n1011l2772w2773w(0) <= wire_w_lg_n1011l2772w(0) AND n0001i;
wire_w_lg_w_lg_PMADATAWIDTH131w1988w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1i01l;
wire_w_lg_w_lg_PMADATAWIDTH131w1673w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1ii0l;
wire_w_lg_w_lg_PMADATAWIDTH131w1678w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1ii1l;
wire_w_lg_w_lg_PMADATAWIDTH131w1668w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1iiil;
wire_w_lg_w_lg_PMADATAWIDTH131w1663w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1iill;
wire_w_lg_w_lg_PMADATAWIDTH131w1953w(0) <= wire_w_lg_PMADATAWIDTH131w(0) AND n1il1l;
wire_w_lg_w_lg_SYNC_SM_DIS876w877w(0) <= wire_w_lg_SYNC_SM_DIS876w(0) AND n0101l;
wire_w_lg_w_lg_n1l1iO867w868w(0) <= wire_w_lg_n1l1iO867w(0) AND wire_n0l0ii_dataout;
wire_w_lg_GE_XAUI_SEL2751w(0) <= GE_XAUI_SEL AND wire_w_lg_n1011O2750w(0);
wire_w_lg_n1l00l2548w(0) <= n1l00l AND n101li;
wire_w_lg_n1l00l848w(0) <= n1l00l AND n1l00i;
wire_w_lg_n1l01O850w(0) <= n1l01O AND n1l01l;
wire_w_lg_n1l10i2457w(0) <= n1l10i AND n1l1il;
wire_w_lg_n1l10l2454w(0) <= n1l10l AND n1l1il;
wire_w_lg_n1ll0O255w(0) <= n1ll0O AND wire_nlliO_w_lg_n00OOi254w(0);
wire_w_lg_n1llil247w(0) <= n1llil AND wire_nlliO_w_lg_n00OOO246w(0);
wire_w_lg_n1llli239w(0) <= n1llli AND wire_nlliO_w_lg_n0i11l238w(0);
wire_w_lg_n1lllO231w(0) <= n1lllO AND wire_nlliO_w_lg_n0i10i230w(0);
wire_w_lg_n1lO1O223w(0) <= n1lO1O AND wire_nlliO_w_lg_w_lg_n0i10O219w222w(0);
wire_w_lg_n1lOll206w(0) <= n1lOll AND wire_nlliO_w_lg_n0i1il205w(0);
wire_w_lg_n1O0Ol52w(0) <= n1O0Ol AND n1O0Oi;
wire_w_lg_n1O11l184w(0) <= n1O11l AND wire_nlliO_w_lg_n0i1li183w(0);
wire_w_lg_n1O1li169w(0) <= n1O1li AND wire_nlliO_w_lg_n0i1lO168w(0);
wire_w_lg_PMADATAWIDTH1659w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0);
wire_w_lg_PMADATAWIDTH1654w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_w_lg_nilli1648w1653w(0);
wire_w_lg_PMADATAWIDTH1649w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_nilli1648w(0);
wire_w_lg_PMADATAWIDTH874w(0) <= PMADATAWIDTH AND wire_w_lg_SYNC_SM_DIS873w(0);
wire_w_lg_PMADATAWIDTH1577w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_w_lg_w_lg_w_lg_nilli1561w1568w1575w1576w(0);
wire_w_lg_PMADATAWIDTH1570w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1569w(0);
wire_w_lg_PMADATAWIDTH1563w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_w_lg_nilli1561w1562w(0);
wire_w_lg_PMADATAWIDTH1598w(0) <= PMADATAWIDTH AND wire_w_lg_n1iO0i1597w(0);
wire_w_lg_PMADATAWIDTH1605w(0) <= PMADATAWIDTH AND wire_w_lg_n1iO1i1604w(0);
wire_w_lg_PMADATAWIDTH1591w(0) <= PMADATAWIDTH AND wire_w_lg_n1iOii1590w(0);
wire_w_lg_PMADATAWIDTH1584w(0) <= PMADATAWIDTH AND wire_w_lg_n1iOli1583w(0);
wire_w_lg_PMADATAWIDTH2384w(0) <= PMADATAWIDTH AND wire_nillO_w_lg_nilli2089w(0);
wire_w_lg_SYNC_SM_DIS873w(0) <= SYNC_SM_DIS AND nllllO;
wire_w_lg_w_IB_INVALID_CODE_range2446w2452w(0) <= wire_w_IB_INVALID_CODE_range2446w(0) AND wire_nillO_w_lg_w_lg_w_lg_w_lg_nlO0il883w2447w2448w2451w(0);
wire_w_lg_w_IB_INVALID_CODE_range2453w2461w(0) <= wire_w_IB_INVALID_CODE_range2453w(0) AND wire_nillO_w_lg_w_lg_nlO0iO2456w2460w(0);
wire_w_lg_w_SYNC_COMP_SIZE_range895w900w(0) <= wire_w_SYNC_COMP_SIZE_range895w(0) AND wire_w_lg_w_SYNC_COMP_SIZE_range897w898w(0);
wire_w_lg_DISABLE_RX_DISP844w(0) <= NOT DISABLE_RX_DISP;
wire_w_lg_GE_XAUI_SEL2752w(0) <= NOT GE_XAUI_SEL;
wire_w_lg_n1001l2475w(0) <= NOT n1001l;
wire_w_lg_n100lO2238w(0) <= NOT n100lO;
wire_w_lg_n100Oi2210w(0) <= NOT n100Oi;
wire_w_lg_n100OO2188w(0) <= NOT n100OO;
wire_w_lg_n1011i2824w(0) <= NOT n1011i;
wire_w_lg_n1011l2772w(0) <= NOT n1011l;
wire_w_lg_n1011O2750w(0) <= NOT n1011O;
wire_w_lg_n10i0l2156w(0) <= NOT n10i0l;
wire_w_lg_n10i1O2183w(0) <= NOT n10i1O;
wire_w_lg_n10iil1997w(0) <= NOT n10iil;
wire_w_lg_n10iiO1996w(0) <= NOT n10iiO;
wire_w_lg_n10ili1995w(0) <= NOT n10ili;
wire_w_lg_n10ill1994w(0) <= NOT n10ill;
wire_w_lg_n10ilO1993w(0) <= NOT n10ilO;
wire_w_lg_n10iOi1992w(0) <= NOT n10iOi;
wire_w_lg_n10iOl1991w(0) <= NOT n10iOl;
wire_w_lg_n10iOO1961w(0) <= NOT n10iOO;
wire_w_lg_n10l0i1957w(0) <= NOT n10l0i;
wire_w_lg_n10l0l1956w(0) <= NOT n10l0l;
wire_w_lg_n10l0O1955w(0) <= NOT n10l0O;
wire_w_lg_n10l1i1960w(0) <= NOT n10l1i;
wire_w_lg_n10l1l1959w(0) <= NOT n10l1l;
wire_w_lg_n10l1O1958w(0) <= NOT n10l1O;
wire_w_lg_n10lli1926w(0) <= NOT n10lli;
wire_w_lg_n10lll1924w(0) <= NOT n10lll;
wire_w_lg_n10llO1986w(0) <= NOT n10llO;
wire_w_lg_n10lOi1930w(0) <= NOT n10lOi;
wire_w_lg_n10lOl1922w(0) <= NOT n10lOl;
wire_w_lg_n10lOO1920w(0) <= NOT n10lOO;
wire_w_lg_n10O0l1871w(0) <= NOT n10O0l;
wire_w_lg_n10O0O1869w(0) <= NOT n10O0O;
wire_w_lg_n10O1i1928w(0) <= NOT n10O1i;
wire_w_lg_n10Oii1976w(0) <= NOT n10Oii;
wire_w_lg_n10Oil1875w(0) <= NOT n10Oil;
wire_w_lg_n10OiO1867w(0) <= NOT n10OiO;
wire_w_lg_n10Oli1865w(0) <= NOT n10Oli;
wire_w_lg_n10Oll1873w(0) <= NOT n10Oll;
wire_w_lg_n10OOO1816w(0) <= NOT n10OOO;
wire_w_lg_n11lli2976w(0) <= NOT n11lli;
wire_w_lg_n11O0l2776w(0) <= NOT n11O0l;
wire_w_lg_n11O0O2761w(0) <= NOT n11O0O;
wire_w_lg_n11Oii2759w(0) <= NOT n11Oii;
wire_w_lg_n11OiO2992w(0) <= NOT n11OiO;
wire_w_lg_n11Oli2749w(0) <= NOT n11Oli;
wire_w_lg_n11Oll2746w(0) <= NOT n11Oll;
wire_w_lg_n1i00l1881w(0) <= NOT n1i00l;
wire_w_lg_n1i00O1885w(0) <= NOT n1i00O;
wire_w_lg_n1i01i1764w(0) <= NOT n1i01i;
wire_w_lg_n1i01l2424w(0) <= NOT n1i01l;
wire_w_lg_n1i01O1879w(0) <= NOT n1i01O;
wire_w_lg_n1i0ii1890w(0) <= NOT n1i0ii;
wire_w_lg_n1i0il1896w(0) <= NOT n1i0il;
wire_w_lg_n1i0iO1903w(0) <= NOT n1i0iO;
wire_w_lg_n1i0li1911w(0) <= NOT n1i0li;
wire_w_lg_n1i0ll2414w(0) <= NOT n1i0ll;
wire_w_lg_n1i0Oi1824w(0) <= NOT n1i0Oi;
wire_w_lg_n1i0OO1969w(0) <= NOT n1i0OO;
wire_w_lg_n1i10i1812w(0) <= NOT n1i10i;
wire_w_lg_n1i10l1810w(0) <= NOT n1i10l;
wire_w_lg_n1i10O1818w(0) <= NOT n1i10O;
wire_w_lg_n1i11i1814w(0) <= NOT n1i11i;
wire_w_lg_n1i11l1951w(0) <= NOT n1i11l;
wire_w_lg_n1i11O1820w(0) <= NOT n1i11O;
wire_w_lg_n1i1li1762w(0) <= NOT n1i1li;
wire_w_lg_n1i1ll1760w(0) <= NOT n1i1ll;
wire_w_lg_n1i1lO1942w(0) <= NOT n1i1lO;
wire_w_lg_n1i1Oi1766w(0) <= NOT n1i1Oi;
wire_w_lg_n1i1Ol1758w(0) <= NOT n1i1Ol;
wire_w_lg_n1i1OO1756w(0) <= NOT n1i1OO;
wire_w_lg_n1ii0O1830w(0) <= NOT n1ii0O;
wire_w_lg_n1ii1i1979w(0) <= NOT n1ii1i;
wire_w_lg_n1ii1O1826w(0) <= NOT n1ii1O;
wire_w_lg_n1iiiO1835w(0) <= NOT n1iiiO;
wire_w_lg_n1iilO1841w(0) <= NOT n1iilO;
wire_w_lg_n1iiOi1848w(0) <= NOT n1iiOi;
wire_w_lg_n1iiOl1856w(0) <= NOT n1iiOl;
wire_w_lg_n1il0i1642w(0) <= NOT n1il0i;
wire_w_lg_n1il0l1776w(0) <= NOT n1il0l;
wire_w_lg_n1il0O1781w(0) <= NOT n1il0O;
wire_w_lg_n1il1l2404w(0) <= NOT n1il1l;
wire_w_lg_n1il1O1770w(0) <= NOT n1il1O;
wire_w_lg_n1ilii1787w(0) <= NOT n1ilii;
wire_w_lg_n1ilil1794w(0) <= NOT n1ilil;
wire_w_lg_n1iliO1802w(0) <= NOT n1iliO;
wire_w_lg_n1illl2394w(0) <= NOT n1illl;
wire_w_lg_n1illO1611w(0) <= NOT n1illO;
wire_w_lg_n1ilOi1715w(0) <= NOT n1ilOi;
wire_w_lg_n1ilOl1608w(0) <= NOT n1ilOl;
wire_w_lg_n1ilOO1935w(0) <= NOT n1ilOO;
wire_w_lg_n1iO0i1597w(0) <= NOT n1iO0i;
wire_w_lg_n1iO0l1595w(0) <= NOT n1iO0l;
wire_w_lg_n1iO0O1721w(0) <= NOT n1iO0O;
wire_w_lg_n1iO1i1604w(0) <= NOT n1iO1i;
wire_w_lg_n1iO1l1602w(0) <= NOT n1iO1l;
wire_w_lg_n1iO1O1717w(0) <= NOT n1iO1O;
wire_w_lg_n1iOii1590w(0) <= NOT n1iOii;
wire_w_lg_n1iOil1588w(0) <= NOT n1iOil;
wire_w_lg_n1iOiO1726w(0) <= NOT n1iOiO;
wire_w_lg_n1iOli1583w(0) <= NOT n1iOli;
wire_w_lg_n1iOll1581w(0) <= NOT n1iOll;
wire_w_lg_n1iOlO1732w(0) <= NOT n1iOlO;
wire_w_lg_n1iOOi1739w(0) <= NOT n1iOOi;
wire_w_lg_n1iOOl1747w(0) <= NOT n1iOOl;
wire_w_lg_n1l0ll842w(0) <= NOT n1l0ll;
wire_w_lg_n1l0lO774w(0) <= NOT n1l0lO;
wire_w_lg_n1l10O879w(0) <= NOT n1l10O;
wire_w_lg_n1liii321w(0) <= NOT n1liii;
wire_w_lg_n1liiO318w(0) <= NOT n1liiO;
wire_w_lg_n1lili316w(0) <= NOT n1lili;
wire_w_lg_n1lill314w(0) <= NOT n1lill;
wire_w_lg_n1lilO312w(0) <= NOT n1lilO;
wire_w_lg_n1liOi310w(0) <= NOT n1liOi;
wire_w_lg_n1liOl308w(0) <= NOT n1liOl;
wire_w_lg_n1liOO306w(0) <= NOT n1liOO;
wire_w_lg_n1ll1i304w(0) <= NOT n1ll1i;
wire_w_lg_n1O00O64w(0) <= NOT n1O00O;
wire_w_lg_n1O0ll54w(0) <= NOT n1O0ll;
wire_w_lg_n1O0OO65w(0) <= NOT n1O0OO;
wire_w_lg_n1Oi1O59w(0) <= NOT n1Oi1O;
wire_w_lg_n1OiiO39w(0) <= NOT n1OiiO;
wire_w_lg_PMADATAWIDTH131w(0) <= NOT PMADATAWIDTH;
wire_w_lg_rcvd_clk43w(0) <= NOT rcvd_clk;
wire_w_lg_soft_reset46w(0) <= NOT soft_reset;
wire_w_lg_SYNC_SM_DIS876w(0) <= NOT SYNC_SM_DIS;
wire_w_lg_w_SYNC_COMP_SIZE_range897w898w(0) <= NOT wire_w_SYNC_COMP_SIZE_range897w(0);
wire_w_lg_w_lg_n1iO1i1604w1775w(0) <= wire_w_lg_n1iO1i1604w(0) OR n1il0O;
wire_w_lg_w_lg_n1iO1i1604w1780w(0) <= wire_w_lg_n1iO1i1604w(0) OR n1ilii;
wire_w_lg_w_lg_n1iO1i1604w1786w(0) <= wire_w_lg_n1iO1i1604w(0) OR n1ilil;
wire_w_lg_w_lg_n1iO1i1604w1793w(0) <= wire_w_lg_n1iO1i1604w(0) OR n1iliO;
wire_w_lg_w_lg_n1iO1i1604w1801w(0) <= wire_w_lg_n1iO1i1604w(0) OR n1illi;
wire_w_lg_w_lg_PMADATAWIDTH131w2020w(0) <= wire_w_lg_PMADATAWIDTH131w(0) OR nilii;
wire_w_lg_w_lg_PMADATAWIDTH131w2013w(0) <= wire_w_lg_PMADATAWIDTH131w(0) OR nilil;
wire_w_lg_w_lg_PMADATAWIDTH131w2004w(0) <= wire_w_lg_PMADATAWIDTH131w(0) OR niliO;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2020w2021w(0) <= wire_w_lg_w_lg_PMADATAWIDTH131w2020w(0) OR nil0O;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2013w2014w(0) <= wire_w_lg_w_lg_PMADATAWIDTH131w2013w(0) OR nilii;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2004w2005w(0) <= wire_w_lg_w_lg_PMADATAWIDTH131w2004w(0) OR nilil;
wire_w2022w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2020w2021w(0) OR nil0l;
wire_w2015w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2013w2014w(0) OR nil0O;
wire_w2006w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH131w2004w2005w(0) OR nilii;
wire_w_lg_w2022w2023w(0) <= wire_w2022w(0) OR nil0i;
wire_w_lg_w2015w2016w(0) <= wire_w2015w(0) OR nil0l;
wire_w_lg_w2006w2007w(0) <= wire_w2006w(0) OR nil0O;
wire_w_lg_w_lg_w2022w2023w2024w(0) <= wire_w_lg_w2022w2023w(0) OR n1O1O;
wire_w_lg_w_lg_w2015w2016w2017w(0) <= wire_w_lg_w2015w2016w(0) OR nil0i;
wire_w_lg_w_lg_w2006w2007w2008w(0) <= wire_w_lg_w2006w2007w(0) OR nil0l;
wire_w_lg_w852w853w(0) <= wire_w852w(0) OR n1l1OO;
wire_w_lg_w_lg_w2054w2055w2056w(0) <= wire_w_lg_w2054w2055w(0) OR n1O1O;
wire_w_lg_w_lg_w2046w2047w2048w(0) <= wire_w_lg_w2046w2047w(0) OR nil0i;
wire_w_lg_w_lg_w2038w2039w2040w(0) <= wire_w_lg_w2038w2039w(0) OR nil0l;
wire_w_lg_w_lg_w2030w2031w2032w(0) <= wire_w_lg_w2030w2031w(0) OR nil0O;
wire_w852w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1l0il846w847w849w851w(0) OR n1l01i;
wire_w_lg_w2054w2055w(0) <= wire_w2054w(0) OR nil0i;
wire_w_lg_w2046w2047w(0) <= wire_w2046w(0) OR nil0l;
wire_w_lg_w2038w2039w(0) <= wire_w2038w(0) OR nil0O;
wire_w_lg_w2030w2031w(0) <= wire_w2030w(0) OR nilii;
wire_w_lg_w_lg_w_lg_w_lg_n1l0il846w847w849w851w(0) <= wire_w_lg_w_lg_w_lg_n1l0il846w847w849w(0) OR wire_w_lg_n1l01O850w(0);
wire_w2054w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH2051w2052w2053w(0) OR nil0l;
wire_w2046w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH2043w2044w2045w(0) OR nil0O;
wire_w2038w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH2035w2036w2037w(0) OR nilii;
wire_w2030w(0) <= wire_w_lg_w_lg_w_lg_PMADATAWIDTH2027w2028w2029w(0) OR nilil;
wire_w_lg_w_lg_w_lg_n1l0il846w847w849w(0) <= wire_w_lg_w_lg_n1l0il846w847w(0) OR wire_w_lg_n1l00l848w(0);
wire_w_lg_w_lg_w_lg_PMADATAWIDTH2051w2052w2053w(0) <= wire_w_lg_w_lg_PMADATAWIDTH2051w2052w(0) OR nil0O;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH2043w2044w2045w(0) <= wire_w_lg_w_lg_PMADATAWIDTH2043w2044w(0) OR nilii;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH2035w2036w2037w(0) <= wire_w_lg_w_lg_PMADATAWIDTH2035w2036w(0) OR nilil;
wire_w_lg_w_lg_w_lg_PMADATAWIDTH2027w2028w2029w(0) <= wire_w_lg_w_lg_PMADATAWIDTH2027w2028w(0) OR niliO;
wire_w_lg_w_lg_n1l0il846w847w(0) <= wire_w_lg_n1l0il846w(0) OR n1l00O;
wire_w_lg_w_lg_PMADATAWIDTH2051w2052w(0) <= wire_w_lg_PMADATAWIDTH2051w(0) OR nilii;
wire_w_lg_w_lg_PMADATAWIDTH2043w2044w(0) <= wire_w_lg_PMADATAWIDTH2043w(0) OR nilil;
wire_w_lg_w_lg_PMADATAWIDTH2035w2036w(0) <= wire_w_lg_PMADATAWIDTH2035w(0) OR niliO;
wire_w_lg_w_lg_PMADATAWIDTH2027w2028w(0) <= wire_w_lg_PMADATAWIDTH2027w(0) OR nilli;
wire_w_lg_n1000i2549w(0) <= n1000i OR wire_w_lg_n1l00l2548w(0);
wire_w_lg_n1000i2464w(0) <= n1000i OR n1001O;
wire_w_lg_n1000l2465w(0) <= n1000l OR wire_w_lg_n1000i2464w(0);
wire_w_lg_n1i01l1921w(0) <= n1i01l OR wire_w_lg_n10lOO1920w(0);
wire_w_lg_n1i01l1978w(0) <= n1i01l OR wire_w_lg_n10O1i1928w(0);
wire_w_lg_n1i0ll1866w(0) <= n1i0ll OR wire_w_lg_n10Oli1865w(0);
wire_w_lg_n1i0ll1968w(0) <= n1i0ll OR wire_w_lg_n10Oll1873w(0);
wire_w_lg_n1il1l1811w(0) <= n1il1l OR wire_w_lg_n1i10l1810w(0);
wire_w_lg_n1il1l1944w(0) <= n1il1l OR wire_w_lg_n1i10O1818w(0);
wire_w_lg_n1illl1934w(0) <= n1illl OR wire_w_lg_n1i01i1764w(0);
wire_w_lg_n1illl1757w(0) <= n1illl OR wire_w_lg_n1i1OO1756w(0);
wire_w_lg_n1l01i2468w(0) <= n1l01i OR wire_w_lg_n1l0ii2467w(0);
wire_w_lg_n1l0ii2467w(0) <= n1l0ii OR wire_w_lg_n1l0il2466w(0);
wire_w_lg_n1l0il2466w(0) <= n1l0il OR n1l00O;
wire_w_lg_n1l0il846w(0) <= n1l0il OR n1l0ii;
wire_w_lg_n1l10i2486w(0) <= n1l10i OR wire_w_lg_n1l10l2485w(0);
wire_w_lg_n1l10l2485w(0) <= n1l10l OR n1001l;
wire_w_lg_n1l1iO867w(0) <= n1l1iO OR wire_nillO_w_lg_nlO0il866w(0);
wire_w_lg_n1l1ll860w(0) <= n1l1ll OR n1l1li;
wire_w_lg_n1l1lO861w(0) <= n1l1lO OR wire_w_lg_n1l1ll860w(0);
wire_w_lg_n1l1Ol857w(0) <= n1l1Ol OR wire_nillO_w_lg_w_lg_nlO00i855w856w(0);
wire_w_lg_PMADATAWIDTH2113w(0) <= PMADATAWIDTH OR wire_nillO_w_lg_nilil2061w(0);
wire_w_lg_PMADATAWIDTH2105w(0) <= PMADATAWIDTH OR wire_nillO_w_lg_niliO2059w(0);
wire_w_lg_PMADATAWIDTH2097w(0) <= PMADATAWIDTH OR wire_nillO_w_lg_nilli2089w(0);
wire_w_lg_PMADATAWIDTH2088w(0) <= PMADATAWIDTH OR wire_nillO_w_lg_nilll2087w(0);
wire_w_lg_PMADATAWIDTH2051w(0) <= PMADATAWIDTH OR nilil;
wire_w_lg_PMADATAWIDTH2043w(0) <= PMADATAWIDTH OR niliO;
wire_w_lg_PMADATAWIDTH2035w(0) <= PMADATAWIDTH OR nilli;
wire_w_lg_PMADATAWIDTH2027w(0) <= PMADATAWIDTH OR nilll;
cg_comma <= nlll0O;
n1000i <= ((n101ll AND n101li) OR (n101lO AND n101li));
n1000l <= (n101ll AND n1l00i);
n1000O <= (nlO0iO XOR nlO0ii);
n1001i <= wire_nillO_w_lg_w_lg_nlO0il883w2495w(0);
n1001l <= (wire_n0l0ii_w_lg_w_lg_dataout862w2579w(0) OR (wire_n0l0ii_dataout AND n1l00i));
n1001O <= (n101ll AND n1l01l);
n100ii <= (nlO0li AND (nlO0iO AND (nlO0il AND nlO0ii)));
n100il <= ((((wire_nillO_w_lg_nlO0li881w(0) AND (nlO0iO AND n101Oi)) OR wire_nillO_w_lg_nlO0li2534w(0)) OR wire_nillO_w_lg_nlO0li2537w(0)) OR wire_nillO_w_lg_nlO0li2540w(0));
n100iO <= (ni0l1i OR ni1O1i);
n100li <= (ni0iOO OR ni0iOl);
n100ll <= (ni0l1O OR ni0l1l);
n100lO <= ((((ni0l0l OR ni0l0i) OR ni0l1O) OR ni0l1l) OR ni0l1i);
n100Oi <= ((((ni0l0l OR ni0l0i) OR ni0iOO) OR ni0iOl) OR ni1O1i);
n100Ol <= (ni0l0l OR ni0l0i);
n100OO <= (wire_nillO_w_lg_niii1O2185w(0) AND wire_nillO_w_lg_niii1l2179w(0));
n1010i <= (nlO01l AND nlO01i);
n1010l <= wire_nillO_w_lg_w_lg_nlO01l2560w2562w(0);
n1010O <= wire_nillO_w_lg_nlO01l2598w(0);
n1011i <= (wire_nillO_w_lg_n0001i2740w(0) OR wire_nillO_w_lg_nlll0O2741w(0));
n1011l <= (((GE_XAUI_SEL AND nlll0O) AND n1Ol0i) OR nlllil);
n1011O <= (wire_nillO_w_lg_nlllll2714w(0) AND wire_nlllii_w_lg_nlllil2715w(0));
n101ii <= wire_nillO_w_lg_w_lg_nlO01l2560w2597w(0);
n101il <= (n1l01O AND n101li);
n101iO <= (wire_nillO_w_lg_nlO00i855w(0) AND (wire_nillO_w_lg_nlO01O2569w(0) AND wire_nillO_w_lg_w_lg_nlO01l2560w2562w(0)));
n101li <= (nlO00O AND nlO00l);
n101ll <= (nlO00i AND (nlO01O AND (nlO01l AND nlO01i)));
n101lO <= ((((wire_nillO_w_lg_nlO00i855w(0) AND (nlO01O AND n1010i)) OR wire_nillO_w_lg_nlO00i2626w(0)) OR wire_nillO_w_lg_nlO00i2629w(0)) OR wire_nillO_w_lg_nlO00i2632w(0));
n101Oi <= (nlO0il AND nlO0ii);
n101Ol <= wire_nillO_w_lg_w_lg_nlO0il883w2512w(0);
n101OO <= wire_nillO_w_lg_nlO0il2496w(0);
n10i0i <= (wire_nillO_w_lg_niiO1l2180w(0) AND niii1l);
n10i0l <= ((((RUNDISP_SEL(0) OR RUNDISP_SEL(1)) OR RUNDISP_SEL(2)) OR RUNDISP_SEL(3)) OR RUNDISP_SEL(4));
n10i0O <= ((wire_ni0lOl_w_lg_w2434w2435w(0) AND wire_ni0lil_w_lg_dataout2436w(0)) AND wire_ni0lii_w_lg_dataout2438w(0));
n10i1i <= (wire_nillO_w_lg_niii1O2185w(0) AND niii1l);
n10i1l <= (ni1lOO AND ni1lOl);
n10i1O <= (wire_nillO_w_lg_niiO1l2180w(0) AND wire_nillO_w_lg_niii1l2179w(0));
n10iii <= ((wire_ni0lOl_w_lg_w2434w2435w(0) AND wire_ni0lil_w_lg_dataout2436w(0)) AND wire_ni0lii_dataout);
n10iil <= (((((((wire_w_lg_PMADATAWIDTH131w(0) OR wire_nillO_w_lg_nilil2061w(0)) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_nillO_w_lg_nil0i2075w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10iiO <= (((((((wire_w_lg_PMADATAWIDTH131w(0) OR wire_nillO_w_lg_niliO2059w(0)) OR wire_nillO_w_lg_nilil2061w(0)) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10ili <= (((((((wire_w_lg_PMADATAWIDTH131w(0) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_nillO_w_lg_nil0i2075w(0)) OR wire_nillO_w_lg_n1O1O2083w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10ill <= (((((((wire_w_lg_PMADATAWIDTH2088w(0) OR wire_nillO_w_lg_nilli2089w(0)) OR wire_nillO_w_lg_niliO2059w(0)) OR wire_nillO_w_lg_nilil2061w(0)) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10ilO <= (((((((wire_w_lg_PMADATAWIDTH2097w(0) OR wire_nillO_w_lg_niliO2059w(0)) OR wire_nillO_w_lg_nilil2061w(0)) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10iOi <= (((((((wire_w_lg_PMADATAWIDTH2105w(0) OR wire_nillO_w_lg_nilil2061w(0)) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_nillO_w_lg_nil0i2075w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10iOl <= (((((((wire_w_lg_PMADATAWIDTH2113w(0) OR wire_nillO_w_lg_nilii2063w(0)) OR wire_nillO_w_lg_nil0O2065w(0)) OR wire_nillO_w_lg_nil0l2067w(0)) OR wire_nillO_w_lg_nil0i2075w(0)) OR wire_nillO_w_lg_n1O1O2083w(0)) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10iOO <= ((wire_w_lg_w_lg_w2015w2016w2017w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l0i <= ((wire_w_lg_w_lg_w2038w2039w2040w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l0l <= ((wire_w_lg_w_lg_w2046w2047w2048w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l0O <= ((wire_w_lg_w_lg_w2054w2055w2056w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l1i <= ((wire_w_lg_w_lg_w2006w2007w2008w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l1l <= ((wire_w_lg_w_lg_w2022w2023w2024w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10l1O <= ((wire_w_lg_w_lg_w2030w2031w2032w(0) OR wire_niii1i_w_lg_dataout2009w(0)) OR wire_nillO_w_lg_nii11i2011w(0));
n10lii <= ((((wire_w_lg_n10O1i1928w(0) OR wire_w_lg_n10lOO1920w(0)) OR wire_w_lg_n10lOi1930w(0)) OR wire_w_lg_n10lll1924w(0)) OR n10lil);
n10lil <= ((((((((wire_nillO_w_lg_n1O1O2416w(0) AND wire_w_lg_n1i0li1911w(0)) AND wire_w_lg_n1i0iO1903w(0)) AND wire_w_lg_n1i0il1896w(0)) AND wire_w_lg_n1i0ii1890w(0)) AND wire_w_lg_n1i00O1885w(0)) AND wire_w_lg_n1i00l1881w(0)) AND wire_w_lg_n1i01O1879w(0)) AND wire_w_lg_n1i01l2424w(0));
n10liO <= (((wire_w_lg_n1i01l1921w(0) OR wire_w_lg_n10lOl1922w(0)) OR wire_w_lg_n10lll1924w(0)) OR wire_w_lg_n10lli1926w(0));
n10lli <= ((((((((n1ii1i OR wire_w_lg_n1i0li1911w(0)) OR n1i0iO) OR n1i0il) OR n1i0ii) OR n1i00O) OR n1i00l) OR n1i01O) OR n1i01l);
n10lll <= (((((((n1ii1i OR wire_w_lg_n1i0iO1903w(0)) OR n1i0il) OR n1i0ii) OR n1i00O) OR n1i00l) OR n1i01O) OR n1i01l);
n10llO <= ((((((n1ii1i OR wire_w_lg_n1i0il1896w(0)) OR n1i0ii) OR n1i00O) OR n1i00l) OR n1i01O) OR n1i01l);
n10lOi <= (((((n1ii1i OR wire_w_lg_n1i0ii1890w(0)) OR n1i00O) OR n1i00l) OR n1i01O) OR n1i01l);
n10lOl <= ((((n1ii1i OR wire_w_lg_n1i00O1885w(0)) OR n1i00l) OR n1i01O) OR n1i01l);
n10lOO <= (((n1ii1i OR wire_w_lg_n1i00l1881w(0)) OR n1i01O) OR n1i01l);
n10O0i <= (((wire_w_lg_n1i0ll1866w(0) OR wire_w_lg_n10OiO1867w(0)) OR wire_w_lg_n10O0O1869w(0)) OR wire_w_lg_n10O0l1871w(0));
n10O0l <= ((((((((wire_w_lg_n1iiOl1856w(0) OR n1iiOi) OR n1iilO) OR n1iiiO) OR n1ii0O) OR n1ii1O) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10O0O <= (((((((wire_w_lg_n1iiOi1848w(0) OR n1iilO) OR n1iiiO) OR n1ii0O) OR n1ii1O) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10O1i <= (wire_w_lg_n1i01O1879w(0) OR n1i01l);
n10O1l <= ((((wire_w_lg_n10Oll1873w(0) OR wire_w_lg_n10Oli1865w(0)) OR wire_w_lg_n10Oil1875w(0)) OR wire_w_lg_n10O0O1869w(0)) OR n10O1O);
n10O1O <= ((((((((((n1il1i OR n1iiOO) AND wire_w_lg_n1iiOl1856w(0)) AND wire_w_lg_n1iiOi1848w(0)) AND wire_w_lg_n1iilO1841w(0)) AND wire_w_lg_n1iiiO1835w(0)) AND wire_w_lg_n1ii0O1830w(0)) AND wire_w_lg_n1ii1O1826w(0)) AND wire_w_lg_n1i0OO1969w(0)) AND wire_w_lg_n1i0Oi1824w(0)) AND wire_w_lg_n1i0ll2414w(0));
n10Oii <= ((((((wire_w_lg_n1iilO1841w(0) OR n1iiiO) OR n1ii0O) OR n1ii1O) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10Oil <= (((((wire_w_lg_n1iiiO1835w(0) OR n1ii0O) OR n1ii1O) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10OiO <= ((((wire_w_lg_n1ii0O1830w(0) OR n1ii1O) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10Oli <= (((wire_w_lg_n1ii1O1826w(0) OR n1i0OO) OR n1i0Oi) OR n1i0ll);
n10Oll <= (wire_w_lg_n1i0Oi1824w(0) OR n1i0ll);
n10OlO <= ((((wire_w_lg_n1i10O1818w(0) OR wire_w_lg_n1i10l1810w(0)) OR wire_w_lg_n1i11O1820w(0)) OR wire_w_lg_n1i11i1814w(0)) OR n10OOi);
n10OOi <= ((wire_nillO_w_lg_w_lg_w_lg_w2399w2400w2401w2402w(0) AND wire_w_lg_n1il1O1770w(0)) AND wire_w_lg_n1il1l2404w(0));
n10OOl <= (((wire_w_lg_n1il1l1811w(0) OR wire_w_lg_n1i10i1812w(0)) OR wire_w_lg_n1i11i1814w(0)) OR wire_w_lg_n10OOO1816w(0));
n10OOO <= (((((((wire_w_lg_w_lg_n1iO1i1604w1801w(0) OR wire_w_lg_n1iliO1802w(0)) OR wire_w_lg_n1ilil1794w(0)) OR wire_w_lg_n1ilii1787w(0)) OR wire_w_lg_n1il0O1781w(0)) OR wire_w_lg_n1il0l1776w(0)) OR n1il1O) OR n1il1l);
n11lii <= ((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001il);
n11lil <= ((((n001Ol OR n001Oi) OR n001lO) OR n001li) OR n001iO);
n11liO <= ((((((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i);
n11lli <= ((((((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001il) OR n001ii) OR n0010O) OR n0011O) OR n1Olll);
n11lll <= (((((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001il) OR n0010l) OR n0010i) OR n0011O);
n11llO <= ((((((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001il) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11lOi <= ((((((((((n001Ol OR n001Oi) OR n001lO) OR n001ll) OR n001li) OR n001iO) OR n001ii) OR n0010O) OR n0010l) OR n0011O) OR n1Olll);
n11lOl <= (((((((((n001Ol OR n001Oi) OR n001lO) OR n001li) OR n001iO) OR n001ii) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11lOO <= ((((((((((n001Ol OR n001Oi) OR n001ll) OR n001li) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11O0i <= ((((((((((n001lO OR n001ll) OR n001li) OR n001iO) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11O0l <= (wire_w_lg_w_lg_n1011l2772w2773w(0) AND (n1Olli AND n1Ol0O));
n11O0O <= (n1011l AND n0001i);
n11O1i <= ((((((((((n001Ol OR n001lO) OR n001ll) OR n001iO) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11O1l <= (((((((((n001Ol OR n001Oi) OR n001li) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11O1O <= (((((((((n001Ol OR n001ll) OR n001iO) OR n001il) OR n001ii) OR n0010O) OR n0010l) OR n0010i) OR n0011O) OR n1Olll);
n11Oii <= (n11OOi OR n11Oll);
n11Oil <= (wire_nillO_w_lg_n0001i2740w(0) OR n11OOO);
n11OiO <= (n1011l OR wire_nillO_w_lg_n0001i2740w(0));
n11Oli <= (n0001i AND (wire_nillO_w_lg_n1Ol0i2743w(0) AND nlll0O));
n11Oll <= (n0001i AND (wire_w_lg_GE_XAUI_SEL2752w(0) AND nlll0O));
n11OlO <= (n0001i AND n11OOi);
n11OOi <= (GE_XAUI_SEL AND n1011O);
n11OOl <= (wire_nillO_w_lg_n0001i2740w(0) OR n11OOO);
n11OOO <= (wire_w_lg_GE_XAUI_SEL2751w(0) OR wire_w_lg_w_lg_GE_XAUI_SEL2752w2753w(0));
n1i00i <= ((((((((nilll AND nilli) AND niliO) AND nilil) AND nilii) AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1i00l <= ((((((niliO AND nilil) AND nilii) AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1i00O <= (((((nilil AND nilii) AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1i01i <= (wire_w_lg_n1ilOi1715w(0) OR n1illl);
n1i01l <= (wire_w_lg_PMADATAWIDTH131w(0) AND n1i0lO);
n1i01O <= (wire_w_lg_PMADATAWIDTH131w(0) AND n1i00i);
n1i0ii <= ((((nilii AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1i0il <= (((nil0O AND nil0l) AND nil0i) AND n1O1O);
n1i0iO <= ((nil0l AND nil0i) AND n1O1O);
n1i0li <= (nil0i AND n1O1O);
n1i0ll <= (wire_w_lg_PMADATAWIDTH131w(0) AND n1i0lO);
n1i0lO <= ((((((wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil) AND nilii) AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1i0Oi <= (wire_w_lg_PMADATAWIDTH131w(0) AND n1i0Ol);
n1i0Ol <= (((((wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil) AND nilii) AND nil0O) AND nil0l) AND nil0i);
n1i0OO <= (wire_w_lg_w_lg_PMADATAWIDTH131w1678w(0) OR (PMADATAWIDTH AND n1ii1i));
n1i10i <= (((wire_w_lg_w_lg_n1iO1i1604w1775w(0) OR wire_w_lg_n1il0l1776w(0)) OR n1il1O) OR n1il1l);
n1i10l <= (((wire_w_lg_n1iO1i1604w(0) OR n1il0l) OR n1il1O) OR n1il1l);
n1i10O <= (wire_w_lg_n1il1O1770w(0) OR n1il1l);
n1i11i <= ((((((wire_w_lg_w_lg_n1iO1i1604w1793w(0) OR wire_w_lg_n1ilil1794w(0)) OR wire_w_lg_n1ilii1787w(0)) OR wire_w_lg_n1il0O1781w(0)) OR wire_w_lg_n1il0l1776w(0)) OR n1il1O) OR n1il1l);
n1i11l <= (((((wire_w_lg_w_lg_n1iO1i1604w1786w(0) OR wire_w_lg_n1ilii1787w(0)) OR wire_w_lg_n1il0O1781w(0)) OR wire_w_lg_n1il0l1776w(0)) OR n1il1O) OR n1il1l);
n1i11O <= ((((wire_w_lg_w_lg_n1iO1i1604w1780w(0) OR wire_w_lg_n1il0O1781w(0)) OR wire_w_lg_n1il0l1776w(0)) OR n1il1O) OR n1il1l);
n1i1ii <= ((((wire_w_lg_n1i01i1764w(0) OR wire_w_lg_n1i1OO1756w(0)) OR wire_w_lg_n1i1Oi1766w(0)) OR wire_w_lg_n1i1ll1760w(0)) OR n1i1il);
n1i1il <= (((((((((((wire_w_lg_PMADATAWIDTH131w(0) AND wire_nillO_w_lg_nilOi2382w(0)) OR wire_w_lg_PMADATAWIDTH2384w(0)) AND wire_w_lg_n1iOOl1747w(0)) AND wire_w_lg_n1iOOi1739w(0)) AND wire_w_lg_n1iOlO1732w(0)) AND wire_w_lg_n1iOiO1726w(0)) AND wire_w_lg_n1iO0O1721w(0)) AND wire_w_lg_n1iO1O1717w(0)) AND wire_w_lg_n1ilOO1935w(0)) AND wire_w_lg_n1ilOi1715w(0)) AND wire_w_lg_n1illl2394w(0));
n1i1iO <= (((wire_w_lg_n1illl1757w(0) OR wire_w_lg_n1i1Ol1758w(0)) OR wire_w_lg_n1i1ll1760w(0)) OR wire_w_lg_n1i1li1762w(0));
n1i1li <= ((((((((wire_w_lg_n1iOOl1747w(0) OR n1iOOi) OR n1iOlO) OR n1iOiO) OR n1iO0O) OR n1iO1O) OR n1ilOO) OR n1ilOi) OR n1illl);
n1i1ll <= (((((((wire_w_lg_n1iOOi1739w(0) OR n1iOlO) OR n1iOiO) OR n1iO0O) OR n1iO1O) OR n1ilOO) OR n1ilOi) OR n1illl);
n1i1lO <= ((((((wire_w_lg_n1iOlO1732w(0) OR n1iOiO) OR n1iO0O) OR n1iO1O) OR n1ilOO) OR n1ilOi) OR n1illl);
n1i1Oi <= (((((wire_w_lg_n1iOiO1726w(0) OR n1iO0O) OR n1iO1O) OR n1ilOO) OR n1ilOi) OR n1illl);
n1i1Ol <= ((((wire_w_lg_n1iO0O1721w(0) OR n1iO1O) OR n1ilOO) OR n1ilOi) OR n1illl);
n1i1OO <= (((wire_w_lg_n1iO1O1717w(0) OR n1ilOO) OR n1ilOi) OR n1illl);
n1ii0i <= (((wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0) AND nil0O) AND nil0l) AND nil0i);
n1ii0l <= (((wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil) AND nilii) AND nil0O);
n1ii0O <= (wire_w_lg_w_lg_PMADATAWIDTH131w1668w(0) OR (PMADATAWIDTH AND n1iiii));
n1ii1i <= ((((wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0) AND nil0O) AND nil0l) AND nil0i) AND n1O1O);
n1ii1l <= ((((wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil) AND nilii) AND nil0O) AND nil0l);
n1ii1O <= (wire_w_lg_w_lg_PMADATAWIDTH131w1673w(0) OR (PMADATAWIDTH AND n1ii0i));
n1iiii <= ((wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0) AND nil0O) AND nil0l);
n1iiil <= ((wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil) AND nilii);
n1iiiO <= (wire_w_lg_w_lg_PMADATAWIDTH131w1663w(0) OR (PMADATAWIDTH AND n1iili));
n1iili <= (wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0) AND nil0O);
n1iill <= (wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) AND nilil);
n1iilO <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0)) OR wire_w_lg_PMADATAWIDTH1659w(0));
n1iiOi <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_nillO_w_lg_w_lg_nilOi1646w1651w(0)) OR wire_w_lg_PMADATAWIDTH1654w(0));
n1iiOl <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_nillO_w_lg_nilOi1646w(0)) OR wire_w_lg_PMADATAWIDTH1649w(0));
n1iiOO <= (PMADATAWIDTH AND nilli);
n1il0i <= ((((((((nilll OR nilli) OR niliO) OR nilil) OR nilii) OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1il0l <= ((((((niliO OR nilil) OR nilii) OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1il0O <= (((((nilil OR nilii) OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1il1i <= (wire_w_lg_PMADATAWIDTH131w(0) AND nilOi);
n1il1l <= (wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1illO1611w(0));
n1il1O <= (wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1il0i1642w(0));
n1ilii <= ((((nilii OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1ilil <= (((nil0O OR nil0l) OR nil0i) OR n1O1O);
n1iliO <= ((nil0l OR nil0i) OR n1O1O);
n1illi <= (nil0i OR n1O1O);
n1illl <= (wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1illO1611w(0));
n1illO <= (((((((((nilOi OR nilll) OR nilli) OR niliO) OR nilil) OR nilii) OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1ilOi <= (wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1ilOl1608w(0));
n1ilOl <= ((((((((nilOi OR nilll) OR nilli) OR niliO) OR nilil) OR nilii) OR nil0O) OR nil0l) OR nil0i);
n1ilOO <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1iO1l1602w(0)) OR wire_w_lg_PMADATAWIDTH1605w(0));
n1iO0i <= (((wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0) OR nil0O) OR nil0l) OR nil0i);
n1iO0l <= ((((((nilOi OR nilll) OR nilli) OR niliO) OR nilil) OR nilii) OR nil0O);
n1iO0O <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1iOil1588w(0)) OR wire_w_lg_PMADATAWIDTH1591w(0));
n1iO1i <= ((((wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0) OR nil0O) OR nil0l) OR nil0i) OR n1O1O);
n1iO1l <= (((((((nilOi OR nilll) OR nilli) OR niliO) OR nilil) OR nilii) OR nil0O) OR nil0l);
n1iO1O <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1iO0l1595w(0)) OR wire_w_lg_PMADATAWIDTH1598w(0));
n1iOii <= ((wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0) OR nil0O) OR nil0l);
n1iOil <= (((((nilOi OR nilll) OR nilli) OR niliO) OR nilil) OR nilii);
n1iOiO <= ((wire_w_lg_PMADATAWIDTH131w(0) AND wire_w_lg_n1iOll1581w(0)) OR wire_w_lg_PMADATAWIDTH1584w(0));
n1iOli <= (wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0) OR nil0O);
n1iOll <= ((((nilOi OR nilll) OR nilli) OR niliO) OR nilil);
n1iOlO <= ((wire_w_lg_PMADATAWIDTH131w(0) AND (NOT (((nilOi OR nilll) OR nilli) OR niliO))) OR wire_w_lg_PMADATAWIDTH1577w(0));
n1iOOi <= ((wire_w_lg_PMADATAWIDTH131w(0) AND (NOT ((nilOi OR nilll) OR nilli))) OR wire_w_lg_PMADATAWIDTH1570w(0));
n1iOOl <= ((wire_w_lg_PMADATAWIDTH131w(0) AND (NOT (nilOi OR nilll))) OR wire_w_lg_PMADATAWIDTH1563w(0));
n1iOOO <= ((((((((((NOT ((NOT SYNC_COMP_PAT(0)) XOR nlO01i)) AND (NOT ((NOT SYNC_COMP_PAT(1)) XOR nlO01l))) AND (NOT ((NOT SYNC_COMP_PAT(2)) XOR nlO01O))) AND (NOT ((NOT SYNC_COMP_PAT(3)) XOR nlO00i))) AND (NOT ((NOT SYNC_COMP_PAT(4)) XOR nlO00l))) AND (NOT ((NOT SYNC_COMP_PAT(5)) XOR nlO00O))) AND (NOT ((NOT SYNC_COMP_PAT(6)) XOR nlO0ii))) AND (NOT ((NOT SYNC_COMP_PAT(7)) XOR nlO0il))) AND (NOT ((NOT SYNC_COMP_PAT(8)) XOR nlO0iO))) AND (NOT ((NOT SYNC_COMP_PAT(9)) XOR nlO0li)));
n1l00i <= (wire_nillO_w_lg_nlO00O2567w(0) AND wire_nillO_w_lg_nlO00l2568w(0));
n1l00l <= ((((((wire_nillO_w_lg_nlO00i855w(0) AND (wire_nillO_w_lg_nlO01O2569w(0) AND (nlO01l AND nlO01i))) OR (wire_nillO_w_lg_nlO00i855w(0) AND (nlO01O AND n101ii))) OR (wire_nillO_w_lg_nlO00i855w(0) AND (nlO01O AND n1010O))) OR wire_nillO_w_lg_nlO00i2606w(0)) OR wire_nillO_w_lg_nlO00i2609w(0)) OR wire_nillO_w_lg_nlO00i2564w(0));
n1l00O <= (n1l01O AND n1l00i);
n1l01i <= (n101iO AND n101li);
n1l01l <= (wire_nillO_w_lg_w_lg_nlO00O2567w2588w(0) OR wire_nillO_w_lg_nlO00O2589w(0));
n1l01O <= ((((wire_nillO_w_lg_nlO00i855w(0) AND (wire_nillO_w_lg_nlO01O2569w(0) AND wire_nillO_w_lg_w_lg_nlO01l2560w2597w(0))) OR (wire_nillO_w_lg_nlO00i855w(0) AND (wire_nillO_w_lg_nlO01O2569w(0) AND wire_nillO_w_lg_nlO01l2598w(0)))) OR (wire_nillO_w_lg_nlO00i855w(0) AND (nlO01O AND n1010l))) OR wire_nillO_w_lg_nlO00i2621w(0));
n1l0ii <= (n101iO AND n1l01l);
n1l0il <= (n101iO AND n1l00i);
n1l0iO <= (PMADATAWIDTH AND wire_w_lg_n1l0ll842w(0));
n1l0li <= (n1lli AND (PMADATAWIDTH AND n1lll));
n1l0ll <= (n1lll AND n1lli);
n1l0lO <= (n1l0Ol OR n1l0Oi);
n1l0Oi <= (n1lll AND wire_nillO_w_lg_n1lli1498w(0));
n1l0Ol <= (n1lll AND n1lli);
n1l10i <= (wire_nillO_w_lg_nlO00O2567w(0) AND (wire_nillO_w_lg_nlO00l2568w(0) AND (wire_nillO_w_lg_nlO00i855w(0) AND (wire_nillO_w_lg_nlO01O2569w(0) AND (nlO01l AND nlO01i)))));
n1l10l <= (nlO00O AND (nlO00l AND wire_nillO_w_lg_nlO00i2564w(0)));
n1l10O <= ((NOT (wire_w_lg_w_IB_INVALID_CODE_range2446w2452w(0) OR wire_w_lg_w_IB_INVALID_CODE_range2453w2461w(0))) AND ((NOT (wire_w_lg_n1000l2465w(0) OR wire_w_lg_n1l01i2468w(0))) AND (NOT (((n100ii OR n1l1li) OR ((NOT (((n1l10l OR n1l10i) OR n1l11l) OR n1l11O)) AND (wire_w_lg_n1001l2475w(0) AND (wire_nillO_w_lg_w_lg_nlO0ii2442w2476w(0) OR (nlO0ii AND n1l1ll))))) OR ((wire_nillO_w_lg_w_lg_nlO0li881w2482w(0) OR (nlO0li AND n1l1ll)) AND wire_w_lg_n1l10i2486w(0))))));
n1l11i <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR nlO01i)) AND (NOT (SYNC_COMP_PAT(1) XOR nlO01l))) AND (NOT (SYNC_COMP_PAT(2) XOR nlO01O))) AND (NOT (SYNC_COMP_PAT(3) XOR nlO00i))) AND (NOT (SYNC_COMP_PAT(4) XOR nlO00l))) AND (NOT (SYNC_COMP_PAT(5) XOR nlO00O))) AND (NOT (SYNC_COMP_PAT(6) XOR nlO0ii))) AND (NOT (SYNC_COMP_PAT(7) XOR nlO0il))) AND (NOT (SYNC_COMP_PAT(8) XOR nlO0iO))) AND (NOT (SYNC_COMP_PAT(9) XOR nlO0li)));
n1l11l <= (nlO00O AND (wire_nillO_w_lg_nlO00l2568w(0) AND n1l01O));
n1l11O <= (wire_nillO_w_lg_nlO00O2567w(0) AND (nlO00l AND n101lO));
n1l1ii <= (wire_w_lg_DISABLE_RX_DISP844w(0) AND ((((wire_nillO_w_lg_nlll0l845w(0) AND wire_w_lg_w852w853w(0)) OR wire_nillO_w_lg_nlll0l858w(0)) OR (wire_w_lg_n1l1lO861w(0) AND wire_n0l0ii_w_lg_dataout862w(0))) OR wire_w_lg_w_lg_n1l1iO867w868w(0)));
n1l1il <= ((((((wire_nillO_w_lg_nlO0li881w(0) AND (wire_nillO_w_lg_nlO0iO882w(0) AND (nlO0il AND nlO0ii))) OR (wire_nillO_w_lg_nlO0li881w(0) AND (nlO0iO AND n1001i))) OR (wire_nillO_w_lg_nlO0li881w(0) AND (nlO0iO AND n101OO))) OR wire_nillO_w_lg_nlO0li2507w(0)) OR wire_nillO_w_lg_nlO0li2510w(0)) OR wire_nillO_w_lg_nlO0li2514w(0));
n1l1iO <= (n100il OR n100ii);
n1l1li <= (wire_nillO_w_lg_nlO0li881w(0) AND (wire_nillO_w_lg_nlO0iO882w(0) AND wire_nillO_w_lg_w_lg_nlO0il883w2512w(0)));
n1l1ll <= ((((wire_nillO_w_lg_nlO0li881w(0) AND (wire_nillO_w_lg_nlO0iO882w(0) AND wire_nillO_w_lg_w_lg_nlO0il883w2495w(0))) OR (wire_nillO_w_lg_nlO0li881w(0) AND (wire_nillO_w_lg_nlO0iO882w(0) AND wire_nillO_w_lg_nlO0il2496w(0)))) OR (wire_nillO_w_lg_nlO0li881w(0) AND (nlO0iO AND n101Ol))) OR wire_nillO_w_lg_nlO0li2529w(0));
n1l1lO <= (wire_nillO_w_lg_nlO0il883w(0) AND wire_nillO_w_lg_w_lg_nlO0ii2442w2443w(0));
n1l1Oi <= (n101lO AND n1l00i);
n1l1Ol <= (((wire_w_lg_n1000i2549w(0) OR (n101lO AND n1l01l)) OR n1001O) OR n1000l);
n1l1OO <= (nlO00i AND n101il);
n1li0i <= (((wire_n10Ol_w_lg_n10OO1491w(0) AND wire_n10Ol_w_lg_n10Oi1492w(0)) AND wire_n10Ol_w_lg_n10lO1494w(0)) AND wire_n10Ol_w_lg_n10li1496w(0));
n1li0O <= (wire_n1Olii_dataout AND (NOT (wire_w_lg_w_lg_n1O0Ol52w53w(0) AND wire_w_lg_n1O0ll54w(0))));
n1li1l <= (PMADATAWIDTH AND n1li0i);
n1li1O <= (wire_w_lg_PMADATAWIDTH131w(0) AND n1li0i);
n1liii <= ((((((((wire_n01il_w_lg_dataout305w(0) OR wire_w_lg_n1liOO306w(0)) OR wire_w_lg_n1liOl308w(0)) OR wire_w_lg_n1liOi310w(0)) OR wire_w_lg_n1lilO312w(0)) OR wire_w_lg_n1lill314w(0)) OR wire_w_lg_n1lili316w(0)) OR wire_w_lg_n1liiO318w(0)) OR n1liil);
n1liil <= ((((((((wire_n0i1O_w_lg_dataout1481w(0) AND wire_n00lO_w_lg_dataout287w(0)) AND wire_n00iO_w_lg_dataout280w(0)) AND wire_n000O_w_lg_dataout274w(0)) AND wire_n001O_w_lg_dataout269w(0)) AND wire_n01OO_w_lg_dataout265w(0)) AND wire_n01lO_w_lg_dataout262w(0)) AND wire_n01li_w_lg_dataout260w(0)) AND wire_n01il_w_lg_dataout1489w(0));
n1liiO <= ((((((((wire_n00OO_w_lg_dataout295w(0) OR wire_n00lO_dataout) OR wire_n00iO_dataout) OR wire_n000O_dataout) OR wire_n001O_dataout) OR wire_n01OO_dataout) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1lili <= (((((((wire_n00lO_w_lg_dataout287w(0) OR wire_n00iO_dataout) OR wire_n000O_dataout) OR wire_n001O_dataout) OR wire_n01OO_dataout) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1lill <= ((((((wire_n00iO_w_lg_dataout280w(0) OR wire_n000O_dataout) OR wire_n001O_dataout) OR wire_n01OO_dataout) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1lilO <= (((((wire_n000O_w_lg_dataout274w(0) OR wire_n001O_dataout) OR wire_n01OO_dataout) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1liOi <= ((((wire_n001O_w_lg_dataout269w(0) OR wire_n01OO_dataout) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1liOl <= (((wire_n01OO_w_lg_dataout265w(0) OR wire_n01lO_dataout) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1liOO <= ((wire_n01lO_w_lg_dataout262w(0) OR wire_n01li_dataout) OR wire_n01il_dataout);
n1ll0i <= ((((((((((NOT (wire_ni0iO_dataout XOR wire_n0lll_dataout)) AND (NOT (wire_ni0li_dataout XOR wire_n0llO_dataout))) AND (NOT (wire_ni0ll_dataout XOR wire_n0lOi_dataout))) AND (NOT (wire_ni0lO_dataout XOR wire_n0lOl_dataout))) AND (NOT (wire_ni0Oi_dataout XOR wire_n0lOO_dataout))) AND (NOT (wire_ni0Ol_dataout XOR wire_n0O1i_dataout))) AND (NOT (wire_ni0OO_dataout XOR wire_n0O1l_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_n0O1O_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_n0O0i_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_n0O0l_dataout)));
n1ll0l <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR wire_n0lll_dataout)) AND (NOT (SYNC_COMP_PAT(1) XOR wire_n0llO_dataout))) AND (NOT (SYNC_COMP_PAT(2) XOR wire_n0lOi_dataout))) AND (NOT (SYNC_COMP_PAT(3) XOR wire_n0lOl_dataout))) AND (NOT (SYNC_COMP_PAT(4) XOR wire_n0lOO_dataout))) AND (NOT (SYNC_COMP_PAT(5) XOR wire_n0O1i_dataout))) AND (NOT (SYNC_COMP_PAT(6) XOR wire_n0O1l_dataout))) AND (NOT (wire_niiOl_dataout XOR wire_n0O1O_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_n0O0i_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_n0O0l_dataout)));
n1ll0O <= ((((((((((NOT (niOll XOR wire_ni0iO_dataout)) AND (NOT (niOlO XOR wire_ni0li_dataout))) AND (NOT (niOOi XOR wire_ni0ll_dataout))) AND (NOT (niOOl XOR wire_ni0lO_dataout))) AND (NOT (niOOO XOR wire_ni0Oi_dataout))) AND (NOT (nl11i XOR wire_ni0Ol_dataout))) AND (NOT (nl11l XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_n0Oii_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_n0Oil_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_n0OiO_dataout)));
n1ll1i <= (wire_n01li_w_lg_dataout260w(0) OR wire_n01il_dataout);
n1ll1l <= ((((((((((NOT (wire_ni0iO_dataout XOR wire_n0i0O_dataout)) AND (NOT (wire_ni0li_dataout XOR wire_n0iii_dataout))) AND (NOT (wire_ni0ll_dataout XOR wire_n0iil_dataout))) AND (NOT (wire_ni0lO_dataout XOR wire_n0iiO_dataout))) AND (NOT (wire_ni0Oi_dataout XOR wire_n0ili_dataout))) AND (NOT (wire_ni0Ol_dataout XOR wire_n0ill_dataout))) AND (NOT (wire_ni0OO_dataout XOR wire_n0ilO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_n0iOi_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_n0iOl_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_n0iOO_dataout)));
n1ll1O <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR wire_n0i0O_dataout)) AND (NOT (SYNC_COMP_PAT(1) XOR wire_n0iii_dataout))) AND (NOT (SYNC_COMP_PAT(2) XOR wire_n0iil_dataout))) AND (NOT (SYNC_COMP_PAT(3) XOR wire_n0iiO_dataout))) AND (NOT (SYNC_COMP_PAT(4) XOR wire_n0ili_dataout))) AND (NOT (SYNC_COMP_PAT(5) XOR wire_n0ill_dataout))) AND (NOT (SYNC_COMP_PAT(6) XOR wire_n0ilO_dataout))) AND (NOT (wire_niiOl_dataout XOR wire_n0iOi_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_n0iOl_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_n0iOO_dataout)));
n1llii <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR niOll)) AND (NOT (SYNC_COMP_PAT(1) XOR niOlO))) AND (NOT (SYNC_COMP_PAT(2) XOR niOOi))) AND (NOT (SYNC_COMP_PAT(3) XOR niOOl))) AND (NOT (SYNC_COMP_PAT(4) XOR niOOO))) AND (NOT (SYNC_COMP_PAT(5) XOR nl11i))) AND (NOT (SYNC_COMP_PAT(6) XOR nl11l))) AND (NOT (wire_niiOl_dataout XOR wire_n0Oii_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_n0Oil_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_n0OiO_dataout)));
n1llil <= ((((((((((NOT (niOlO XOR wire_ni0iO_dataout)) AND (NOT (niOOi XOR wire_ni0li_dataout))) AND (NOT (niOOl XOR wire_ni0ll_dataout))) AND (NOT (niOOO XOR wire_ni0lO_dataout))) AND (NOT (nl11i XOR wire_ni0Oi_dataout))) AND (NOT (nl11l XOR wire_ni0Ol_dataout))) AND (NOT (nl11O XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_n0Oll_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_n0OlO_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_n0OOi_dataout)));
n1lliO <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR niOlO)) AND (NOT (SYNC_COMP_PAT(1) XOR niOOi))) AND (NOT (SYNC_COMP_PAT(2) XOR niOOl))) AND (NOT (SYNC_COMP_PAT(3) XOR niOOO))) AND (NOT (SYNC_COMP_PAT(4) XOR nl11i))) AND (NOT (SYNC_COMP_PAT(5) XOR nl11l))) AND (NOT (SYNC_COMP_PAT(6) XOR nl11O))) AND (NOT (wire_niiOl_dataout XOR wire_n0Oll_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_n0OlO_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_n0OOi_dataout)));
n1llli <= ((((((((((NOT (niOOi XOR wire_ni0iO_dataout)) AND (NOT (niOOl XOR wire_ni0li_dataout))) AND (NOT (niOOO XOR wire_ni0ll_dataout))) AND (NOT (nl11i XOR wire_ni0lO_dataout))) AND (NOT (nl11l XOR wire_ni0Oi_dataout))) AND (NOT (nl11O XOR wire_ni0Ol_dataout))) AND (NOT (nl10i XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_n0OOO_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni11i_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni11l_dataout)));
n1llll <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR niOOi)) AND (NOT (SYNC_COMP_PAT(1) XOR niOOl))) AND (NOT (SYNC_COMP_PAT(2) XOR niOOO))) AND (NOT (SYNC_COMP_PAT(3) XOR nl11i))) AND (NOT (SYNC_COMP_PAT(4) XOR nl11l))) AND (NOT (SYNC_COMP_PAT(5) XOR nl11O))) AND (NOT (SYNC_COMP_PAT(6) XOR nl10i))) AND (NOT (wire_niiOl_dataout XOR wire_n0OOO_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni11i_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni11l_dataout)));
n1lllO <= ((((((((((NOT (niOOl XOR wire_ni0iO_dataout)) AND (NOT (niOOO XOR wire_ni0li_dataout))) AND (NOT (nl11i XOR wire_ni0ll_dataout))) AND (NOT (nl11l XOR wire_ni0lO_dataout))) AND (NOT (nl11O XOR wire_ni0Oi_dataout))) AND (NOT (nl10i XOR wire_ni0Ol_dataout))) AND (NOT (nl10l XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_ni10i_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni10l_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni10O_dataout)));
n1llOi <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR niOOl)) AND (NOT (SYNC_COMP_PAT(1) XOR niOOO))) AND (NOT (SYNC_COMP_PAT(2) XOR nl11i))) AND (NOT (SYNC_COMP_PAT(3) XOR nl11l))) AND (NOT (SYNC_COMP_PAT(4) XOR nl11O))) AND (NOT (SYNC_COMP_PAT(5) XOR nl10i))) AND (NOT (SYNC_COMP_PAT(6) XOR nl10l))) AND (NOT (wire_niiOl_dataout XOR wire_ni10i_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni10l_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni10O_dataout)));
n1lO0i <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR niOOO)) AND (NOT (SYNC_COMP_PAT(1) XOR nl11i))) AND (NOT (SYNC_COMP_PAT(2) XOR nl11l))) AND (NOT (SYNC_COMP_PAT(3) XOR nl11O))) AND (NOT (SYNC_COMP_PAT(4) XOR nl10i))) AND (NOT (SYNC_COMP_PAT(5) XOR nl10l))) AND (NOT (SYNC_COMP_PAT(6) XOR nl10O))) AND (NOT (wire_niiOl_dataout XOR wire_ni1il_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni1iO_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni1li_dataout)));
n1lO1O <= ((((((((((NOT (niOOO XOR wire_ni0iO_dataout)) AND (NOT (nl11i XOR wire_ni0li_dataout))) AND (NOT (nl11l XOR wire_ni0ll_dataout))) AND (NOT (nl11O XOR wire_ni0lO_dataout))) AND (NOT (nl10i XOR wire_ni0Oi_dataout))) AND (NOT (nl10l XOR wire_ni0Ol_dataout))) AND (NOT (nl10O XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_ni1il_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni1iO_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni1li_dataout)));
n1lOll <= ((((((((((NOT (nl11i XOR wire_ni0iO_dataout)) AND (NOT (nl11l XOR wire_ni0li_dataout))) AND (NOT (nl11O XOR wire_ni0ll_dataout))) AND (NOT (nl10i XOR wire_ni0lO_dataout))) AND (NOT (nl10l XOR wire_ni0Oi_dataout))) AND (NOT (nl10O XOR wire_ni0Ol_dataout))) AND (NOT (nl1ii XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_ni1lO_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni1Oi_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni1Ol_dataout)));
n1lOlO <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR nl11i)) AND (NOT (SYNC_COMP_PAT(1) XOR nl11l))) AND (NOT (SYNC_COMP_PAT(2) XOR nl11O))) AND (NOT (SYNC_COMP_PAT(3) XOR nl10i))) AND (NOT (SYNC_COMP_PAT(4) XOR nl10l))) AND (NOT (SYNC_COMP_PAT(5) XOR nl10O))) AND (NOT (SYNC_COMP_PAT(6) XOR nl1ii))) AND (NOT (wire_niiOl_dataout XOR wire_ni1lO_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni1Oi_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni1Ol_dataout)));
n1O00O <= (wire_nlliO_w_lg_n0000l60w(0) AND (n1O0ii14 XOR n1O0ii13));
n1O0ll <= ((((wire_w_lg_n1ll1i304w(0) OR wire_w_lg_n1liOl308w(0)) OR wire_w_lg_n1lilO312w(0)) OR wire_w_lg_n1lili316w(0)) OR n1liil);
n1O0lO <= ((((wire_w_lg_n1liOO306w(0) OR wire_w_lg_n1liOl308w(0)) OR wire_w_lg_n1lill314w(0)) OR wire_w_lg_n1lili316w(0)) OR wire_w_lg_n1liii321w(0));
n1O0Oi <= ((((wire_w_lg_n1liOO306w(0) OR wire_w_lg_n1liOl308w(0)) OR wire_w_lg_n1liOi310w(0)) OR wire_w_lg_n1lilO312w(0)) OR wire_w_lg_n1liii321w(0));
n1O0Ol <= (wire_n01il_w_lg_dataout305w(0) OR wire_w_lg_n1liii321w(0));
n1O0OO <= ((n0000l AND n1Oi1O) AND (n1Oi1i10 XOR n1Oi1i9));
n1O11l <= ((((((((((NOT (nl11l XOR wire_ni0iO_dataout)) AND (NOT (nl11O XOR wire_ni0li_dataout))) AND (NOT (nl10i XOR wire_ni0ll_dataout))) AND (NOT (nl10l XOR wire_ni0lO_dataout))) AND (NOT (nl10O XOR wire_ni0Oi_dataout))) AND (NOT (nl1ii XOR wire_ni0Ol_dataout))) AND (NOT (nl1il XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_ni01i_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni01l_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni01O_dataout)));
n1O11O <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR nl11l)) AND (NOT (SYNC_COMP_PAT(1) XOR nl11O))) AND (NOT (SYNC_COMP_PAT(2) XOR nl10i))) AND (NOT (SYNC_COMP_PAT(3) XOR nl10l))) AND (NOT (SYNC_COMP_PAT(4) XOR nl10O))) AND (NOT (SYNC_COMP_PAT(5) XOR nl1ii))) AND (NOT (SYNC_COMP_PAT(6) XOR nl1il))) AND (NOT (wire_niiOl_dataout XOR wire_ni01i_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni01l_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni01O_dataout)));
n1O1li <= ((((((((((NOT (nl11O XOR wire_ni0iO_dataout)) AND (NOT (nl10i XOR wire_ni0li_dataout))) AND (NOT (nl10l XOR wire_ni0ll_dataout))) AND (NOT (nl10O XOR wire_ni0lO_dataout))) AND (NOT (nl1ii XOR wire_ni0Oi_dataout))) AND (NOT (nl1il XOR wire_ni0Ol_dataout))) AND (NOT (nl1iO XOR wire_ni0OO_dataout))) AND (NOT (wire_nii1i_dataout XOR wire_ni00l_dataout))) AND (NOT (wire_nii1l_dataout XOR wire_ni00O_dataout))) AND (NOT (wire_nii1O_dataout XOR wire_ni0ii_dataout)));
n1O1ll <= ((((((((((NOT (SYNC_COMP_PAT(0) XOR nl11O)) AND (NOT (SYNC_COMP_PAT(1) XOR nl10i))) AND (NOT (SYNC_COMP_PAT(2) XOR nl10l))) AND (NOT (SYNC_COMP_PAT(3) XOR nl10O))) AND (NOT (SYNC_COMP_PAT(4) XOR nl1ii))) AND (NOT (SYNC_COMP_PAT(5) XOR nl1il))) AND (NOT (SYNC_COMP_PAT(6) XOR nl1iO))) AND (NOT (wire_niiOl_dataout XOR wire_ni00l_dataout))) AND (NOT (wire_niiOO_dataout XOR wire_ni00O_dataout))) AND (NOT (wire_nil1i_dataout XOR wire_ni0ii_dataout)));
n1O1lO <= ((NOT SYNC_COMP_SIZE(0)) AND wire_w_lg_w_SYNC_COMP_SIZE_range897w898w(0));
n1O1Oi <= wire_w_lg_w_SYNC_COMP_SIZE_range895w900w(0);
n1Oi0i <= '1';
n1Oi1O <= ((wire_w_lg_w_lg_n1O0Ol52w53w(0) AND wire_w_lg_n1O0ll54w(0)) AND (n1O0iO12 XOR n1O0iO11));
n1Oiii <= ((((n001li OR n001iO) OR n0010i) OR n0011O) OR n1Olll);
n1Oiil <= ((((n001iO OR n001il) OR n001ii) OR n0010O) OR n0010l);
n1OiiO <= (((((n001Ol OR n001Oi) OR n001il) OR n001ii) OR n0010i) OR n0011O);
n1Oili <= (((((n001Oi OR n001ll) OR n001li) OR n001ii) OR n0010l) OR n0011O);
n1Ol1l <= (ni0OiO OR ni0Oil);
RLV <= n1Ol1l;
RLV_lt <= ((((ni0Oii OR ni0O0O) OR (NOT (n1OiOi2 XOR n1OiOi1))) OR (DWIDTH AND ni0l0O)) OR (NOT (n1Oill4 XOR n1Oill3)));
signal_detect_sync <= n0001i;
SUDI <= ( nllOlO & nllOll & nllOli & nllOiO & nllOil & nllOii & nllO0O & nllO0l & nllO0i & nllO1O & nllO1l & nllO1i & nlllOO);
SUDI_pre <= ( nlO0li & nlO0iO & nlO0il & nlO0ii & nlO00O & nlO00l & nlO00i & nlO01O & nlO01l & nlO01i);
sync_curr_st <= ( n1Oiii & n1Oiil & wire_w_lg_n1OiiO39w & n1Oili);
sync_status <= n0101l;
wire_w_IB_INVALID_CODE_range2446w(0) <= IB_INVALID_CODE(0);
wire_w_IB_INVALID_CODE_range2453w(0) <= IB_INVALID_CODE(1);
wire_w_SYNC_COMP_SIZE_range895w(0) <= SYNC_COMP_SIZE(0);
wire_w_SYNC_COMP_SIZE_range897w(0) <= SYNC_COMP_SIZE(1);
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1l0OO53 <= n1l0OO54;
END IF;
if (now = 0 ns) then
n1l0OO53 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1l0OO54 <= n1l0OO53;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1li0l49 <= n1li0l50;
END IF;
if (now = 0 ns) then
n1li0l49 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1li0l50 <= n1li0l49;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1li1i51 <= n1li1i52;
END IF;
if (now = 0 ns) then
n1li1i51 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1li1i52 <= n1li1i51;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1llOl47 <= n1llOl48;
END IF;
if (now = 0 ns) then
n1llOl47 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1llOl48 <= n1llOl47;
END IF;
END PROCESS;
wire_n1llOl48_w_lg_q221w(0) <= n1llOl48 XOR n1llOl47;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lO0l43 <= n1lO0l44;
END IF;
if (now = 0 ns) then
n1lO0l43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lO0l44 <= n1lO0l43;
END IF;
END PROCESS;
wire_n1lO0l44_w_lg_q208w(0) <= n1lO0l44 XOR n1lO0l43;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lO1i45 <= n1lO1i46;
END IF;
if (now = 0 ns) then
n1lO1i45 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lO1i46 <= n1lO1i45;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOii41 <= n1lOii42;
END IF;
if (now = 0 ns) then
n1lOii41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOii42 <= n1lOii41;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOiO39 <= n1lOiO40;
END IF;
if (now = 0 ns) then
n1lOiO39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOiO40 <= n1lOiO39;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOOi37 <= n1lOOi38;
END IF;
if (now = 0 ns) then
n1lOOi37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOOi38 <= n1lOOi37;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOOO35 <= n1lOOO36;
END IF;
if (now = 0 ns) then
n1lOOO35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1lOOO36 <= n1lOOO35;
END IF;
END PROCESS;
wire_n1lOOO36_w_lg_q186w(0) <= n1lOOO36 XOR n1lOOO35;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O00i17 <= n1O00i18;
END IF;
if (now = 0 ns) then
n1O00i17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O00i18 <= n1O00i17;
END IF;
END PROCESS;
wire_n1O00i18_w_lg_w_lg_q79w80w(0) <= wire_n1O00i18_w_lg_q79w(0) AND nllli;
wire_n1O00i18_w_lg_q79w(0) <= n1O00i18 XOR n1O00i17;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O00l15 <= n1O00l16;
END IF;
if (now = 0 ns) then
n1O00l15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O00l16 <= n1O00l15;
END IF;
END PROCESS;
wire_n1O00l16_w_lg_w_lg_q68w69w(0) <= wire_n1O00l16_w_lg_q68w(0) AND nllli;
wire_n1O00l16_w_lg_q68w(0) <= n1O00l16 XOR n1O00l15;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01i23 <= n1O01i24;
END IF;
if (now = 0 ns) then
n1O01i23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01i24 <= n1O01i23;
END IF;
END PROCESS;
wire_n1O01i24_w_lg_w_lg_q99w100w(0) <= wire_n1O01i24_w_lg_q99w(0) AND wire_nll1O_dataout;
wire_n1O01i24_w_lg_q99w(0) <= n1O01i24 XOR n1O01i23;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01l21 <= n1O01l22;
END IF;
if (now = 0 ns) then
n1O01l21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01l22 <= n1O01l21;
END IF;
END PROCESS;
wire_n1O01l22_w_lg_w_lg_q96w97w(0) <= wire_n1O01l22_w_lg_q96w(0) AND n1O00O;
wire_n1O01l22_w_lg_q96w(0) <= n1O01l22 XOR n1O01l21;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01O19 <= n1O01O20;
END IF;
if (now = 0 ns) then
n1O01O19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O01O20 <= n1O01O19;
END IF;
END PROCESS;
wire_n1O01O20_w_lg_w_lg_q88w89w(0) <= wire_n1O01O20_w_lg_q88w(0) AND nllil;
wire_n1O01O20_w_lg_q88w(0) <= n1O01O20 XOR n1O01O19;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O0ii13 <= n1O0ii14;
END IF;
if (now = 0 ns) then
n1O0ii13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O0ii14 <= n1O0ii13;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O0iO11 <= n1O0iO12;
END IF;
if (now = 0 ns) then
n1O0iO11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O0iO12 <= n1O0iO11;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O10i33 <= n1O10i34;
END IF;
if (now = 0 ns) then
n1O10i33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O10i34 <= n1O10i33;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O10O31 <= n1O10O32;
END IF;
if (now = 0 ns) then
n1O10O31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O10O32 <= n1O10O31;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1il29 <= n1O1il30;
END IF;
if (now = 0 ns) then
n1O1il29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1il30 <= n1O1il29;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1Ol27 <= n1O1Ol28;
END IF;
if (now = 0 ns) then
n1O1Ol27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1Ol28 <= n1O1Ol27;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1OO25 <= n1O1OO26;
END IF;
if (now = 0 ns) then
n1O1OO25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1O1OO26 <= n1O1OO25;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi0l7 <= n1Oi0l8;
END IF;
if (now = 0 ns) then
n1Oi0l7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi0l8 <= n1Oi0l7;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi0O5 <= n1Oi0O6;
END IF;
if (now = 0 ns) then
n1Oi0O5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi0O6 <= n1Oi0O5;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi1i10 <= n1Oi1i9;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oi1i9 <= n1Oi1i10;
END IF;
if (now = 0 ns) then
n1Oi1i9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oill3 <= n1Oill4;
END IF;
if (now = 0 ns) then
n1Oill3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1Oill4 <= n1Oill3;
END IF;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1OiOi1 <= n1OiOi2;
END IF;
if (now = 0 ns) then
n1OiOi1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rcvd_clk)
BEGIN
IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n1OiOi2 <= n1OiOi1;
END IF;
END PROCESS;
PROCESS (rcvd_clk, wire_n10Ol_PRN, wire_n10Ol_CLRN)
BEGIN
IF (wire_n10Ol_PRN = '0') THEN
n10li <= '1';
n10lO <= '1';
n10Oi <= '1';
n10OO <= '1';
ELSIF (wire_n10Ol_CLRN = '0') THEN
n10li <= '0';
n10lO <= '0';
n10Oi <= '0';
n10OO <= '0';
ELSIF (rcvd_clk = '0' AND rcvd_clk'event) THEN
IF (n11ll = '1') THEN
n10li <= wire_n1i1l_dataout;
n10lO <= wire_n1i1O_dataout;
n10Oi <= wire_n1i0i_dataout;
n10OO <= wire_n1i0l_dataout;
END IF;
END IF;
END PROCESS;
wire_n10Ol_CLRN <= ((n1li1i52 XOR n1li1i51) AND wire_w_lg_soft_reset46w(0));
wire_n10Ol_PRN <= (n1l0OO54 XOR n1l0OO53);
wire_n10Ol_w_lg_n10li1496w(0) <= NOT n10li;
wire_n10Ol_w_lg_n10lO1494w(0) <= NOT n10lO;
wire_n10Ol_w_lg_n10Oi1492w(0) <= NOT n10Oi;
wire_n10Ol_w_lg_n10OO1491w(0) <= NOT n10OO;
PROCESS (rcvd_clk, wire_n1O1i_CLRN)
BEGIN
IF (wire_n1O1i_CLRN = '0') THEN
n1lOi <= '0';
n1lOl <= '0';
n1lOO <= '0';
n1O1l <= '0';
ELSIF (rcvd_clk = '0' AND rcvd_clk'event) THEN
IF (n1li0O = '1') THEN
n1lOi <= wire_w_lg_n1O0ll54w(0);
n1lOl <= n1O0lO;
n1lOO <= n1O0Oi;
n1O1l <= n1O0Ol;
END IF;
END IF;
END PROCESS;
wire_n1O1i_CLRN <= ((n1li0l50 XOR n1li0l49) AND wire_w_lg_soft_reset46w(0));
PROCESS (rcvd_clk, wire_nillO_PRN, soft_reset)
BEGIN
IF (wire_nillO_PRN = '0') THEN
n0001i <= '1';
n0010i <= '1';
n0010l <= '1';
n0010O <= '1';
n0011O <= '1';
n001ii <= '1';
n001il <= '1';
n001iO <= '1';
n001li <= '1';
n001ll <= '1';
n001lO <= '1';
n001Oi <= '1';
n001OO <= '1';
n0101l <= '1';
n1lli <= '1';
n1lll <= '1';
n1O1O <= '1';
n1Ol0i <= '1';
n1Ol0O <= '1';
n1Olli <= '1';
n1Olll <= '1';
ni0iOl <= '1';
ni0iOO <= '1';
ni0l0i <= '1';
ni0l0O <= '1';
ni0l1i <= '1';
ni0l1l <= '1';
ni0l1O <= '1';
ni0O0O <= '1';
ni0Oii <= '1';
ni0Oil <= '1';
ni0OiO <= '1';
ni0OOO <= '1';
ni1liO <= '1';
ni1lli <= '1';
ni1lll <= '1';
ni1llO <= '1';
ni1lOi <= '1';
ni1lOl <= '1';
ni1lOO <= '1';
ni1O1i <= '1';
ni1Oli <= '1';
nii11i <= '1';
nii11l <= '1';
nii11O <= '1';
niii0i <= '1';
niii0l <= '1';
niii0O <= '1';
niii1l <= '1';
niii1O <= '1';
niiiii <= '1';
niiiil <= '1';
niiiiO <= '1';
niiili <= '1';
niiill <= '1';
niiilO <= '1';
niiiOi <= '1';
niiiOl <= '1';
niiiOO <= '1';
niil1i <= '1';
niiO0i <= '1';
niiO0l <= '1';
niiO0O <= '1';
niiO1l <= '1';
niiO1O <= '1';
niiOii <= '1';
niiOil <= '1';
niiOiO <= '1';
niiOli <= '1';
niiOll <= '1';
niiOlO <= '1';
niiOOi <= '1';
niiOOl <= '1';
nil0i <= '1';
nil0l <= '1';
nil0O <= '1';
nilii <= '1';
nilil <= '1';
niliO <= '1';
nilli <= '1';
nilll <= '1';
nilOi <= '1';
nlll0l <= '1';
nlll0O <= '1';
nlllll <= '1';
nllllO <= '1';
nlllOi <= '1';
nlllOl <= '1';
nlllOO <= '1';
nllO0i <= '1';
nllO0l <= '1';
nllO0O <= '1';
nllO1i <= '1';
nllO1l <= '1';
nllO1O <= '1';
nllOii <= '1';
nllOil <= '1';
nllOiO <= '1';
nllOli <= '1';
nllOll <= '1';
nllOlO <= '1';
nllOOi <= '1';
nllOOl <= '1';
nllOOO <= '1';
nlO00i <= '1';
nlO00l <= '1';
nlO00O <= '1';
nlO01i <= '1';
nlO01l <= '1';
nlO01O <= '1';
nlO0ii <= '1';
nlO0il <= '1';
nlO0iO <= '1';
nlO0li <= '1';
nlO10i <= '1';
nlO10l <= '1';
nlO10O <= '1';
nlO11i <= '1';
nlO11l <= '1';
nlO11O <= '1';
nlO1ii <= '1';
nlO1il <= '1';
nlO1iO <= '1';
nlO1li <= '1';
nlO1ll <= '1';
nlO1lO <= '1';
nlO1Oi <= '1';
nlO1Ol <= '1';
nlO1OO <= '1';
ELSIF (soft_reset = '1') THEN
n0001i <= '0';
n0010i <= '0';
n0010l <= '0';
n0010O <= '0';
n0011O <= '0';
n001ii <= '0';
n001il <= '0';
n001iO <= '0';
n001li <= '0';
n001ll <= '0';
n001lO <= '0';
n001Oi <= '0';
n001OO <= '0';
n0101l <= '0';
n1lli <= '0';
n1lll <= '0';
n1O1O <= '0';
n1Ol0i <= '0';
n1Ol0O <= '0';
n1Olli <= '0';
n1Olll <= '0';
ni0iOl <= '0';
ni0iOO <= '0';
ni0l0i <= '0';
ni0l0O <= '0';
ni0l1i <= '0';
ni0l1l <= '0';
ni0l1O <= '0';
ni0O0O <= '0';
ni0Oii <= '0';
ni0Oil <= '0';
ni0OiO <= '0';
ni0OOO <= '0';
ni1liO <= '0';
ni1lli <= '0';
ni1lll <= '0';
ni1llO <= '0';
ni1lOi <= '0';
ni1lOl <= '0';
ni1lOO <= '0';
ni1O1i <= '0';
ni1Oli <= '0';
nii11i <= '0';
nii11l <= '0';
nii11O <= '0';
niii0i <= '0';
niii0l <= '0';
niii0O <= '0';
niii1l <= '0';
niii1O <= '0';
niiiii <= '0';
niiiil <= '0';
niiiiO <= '0';
niiili <= '0';
niiill <= '0';
niiilO <= '0';
niiiOi <= '0';
niiiOl <= '0';
niiiOO <= '0';
niil1i <= '0';
niiO0i <= '0';
niiO0l <= '0';
niiO0O <= '0';
niiO1l <= '0';
niiO1O <= '0';
niiOii <= '0';
niiOil <= '0';
niiOiO <= '0';
niiOli <= '0';
niiOll <= '0';
niiOlO <= '0';
niiOOi <= '0';
niiOOl <= '0';
nil0i <= '0';
nil0l <= '0';
nil0O <= '0';
nilii <= '0';
nilil <= '0';
niliO <= '0';
nilli <= '0';
nilll <= '0';
nilOi <= '0';
nlll0l <= '0';
nlll0O <= '0';
nlllll <= '0';
nllllO <= '0';
nlllOi <= '0';
nlllOl <= '0';
nlllOO <= '0';
nllO0i <= '0';
nllO0l <= '0';
nllO0O <= '0';
nllO1i <= '0';
nllO1l <= '0';
nllO1O <= '0';
nllOii <= '0';
nllOil <= '0';
nllOiO <= '0';
nllOli <= '0';
nllOll <= '0';
nllOlO <= '0';
nllOOi <= '0';
nllOOl <= '0';
nllOOO <= '0';
nlO00i <= '0';
nlO00l <= '0';
nlO00O <= '0';
nlO01i <= '0';
nlO01l <= '0';
nlO01O <= '0';
nlO0ii <= '0';
nlO0il <= '0';
nlO0iO <= '0';
nlO0li <= '0';
nlO10i <= '0';
nlO10l <= '0';
nlO10O <= '0';
nlO11i <= '0';
nlO11l <= '0';
nlO11O <= '0';
nlO1ii <= '0';
nlO1il <= '0';
nlO1iO <= '0';
nlO1li <= '0';
nlO1ll <= '0';
nlO1lO <= '0';
nlO1Oi <= '0';
nlO1Ol <= '0';
nlO1OO <= '0';
ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN
n0001i <= n001OO;
n0010i <= wire_n1OOii_o;
n0010l <= wire_n1OOiO_o;
n0010O <= wire_n1OOll_o;
n0011O <= wire_n1OO0O_o;
n001ii <= wire_n1OOOi_o;
n001il <= wire_n1OOOO_o;
n001iO <= wire_n0111l_o;
n001li <= wire_n0110i_o;
n001ll <= wire_n0110O_o;
n001lO <= wire_n011il_o;
n001Oi <= wire_n011li_o;
n001OO <= (wire_w_lg_SYNC_SM_DIS876w(0) AND (LP10BEN OR signal_detect));
n0101l <= wire_n1OlOO_o;
n1lli <= n1iOi;
n1lll <= n1llO;
n1O1O <= nl11O;
n1Ol0i <= wire_n1OO1O_o;
n1Ol0O <= wire_n1OllO_o;
n1Olli <= wire_n1OlOi_o;
n1Olll <= wire_n1OO0i_o;
ni0iOl <= wire_ni01ll_o;
ni0iOO <= wire_ni01lO_dataout;
ni0l0i <= wire_ni001O_dataout;
ni0l0O <= wire_ni0Oli_dataout;
ni0l1i <= wire_ni01Oi_o;
ni0l1l <= wire_ni01OO_o;
ni0l1O <= wire_ni001l_dataout;
ni0O0O <= wire_ni0Oll_dataout;
ni0Oii <= wire_ni0OlO_dataout;
ni0Oil <= wire_ni0OOi_dataout;
ni0OiO <= ni0OOO;
ni0OOO <= (niil1i OR nii11O);
ni1liO <= wire_ni1Oii_o(1);
ni1lli <= wire_ni1Oii_o(2);
ni1lll <= wire_ni1Oii_o(3);
ni1llO <= wire_ni1O1l_dataout;
ni1lOi <= wire_ni1O1O_dataout;
ni1lOl <= wire_ni1O0i_dataout;
ni1lOO <= wire_ni1O0l_dataout;
ni1O1i <= wire_ni01iO_o;
ni1Oli <= wire_ni1Oii_o(0);
nii11i <= nii11l;
nii11l <= RLV_EN;
nii11O <= wire_niil1l_dataout;
niii0i <= wire_niil0l_dataout;
niii0l <= wire_niil0O_dataout;
niii0O <= wire_niilii_dataout;
niii1l <= wire_niil1O_dataout;
niii1O <= wire_niil0i_dataout;
niiiii <= wire_niilil_dataout;
niiiil <= wire_niiliO_dataout;
niiiiO <= wire_niilli_dataout;
niiili <= wire_niilll_dataout;
niiill <= wire_niillO_dataout;
niiilO <= wire_niilOi_dataout;
niiiOi <= wire_niilOl_dataout;
niiiOl <= wire_niilOO_dataout;
niiiOO <= wire_niiO1i_dataout;
niil1i <= wire_niiOOO_dataout;
niiO0i <= wire_nil11O_dataout;
niiO0l <= wire_nil10i_dataout;
niiO0O <= wire_nil10l_dataout;
niiO1l <= wire_nil11i_dataout;
niiO1O <= wire_nil11l_dataout;
niiOii <= wire_nil10O_dataout;
niiOil <= wire_nil1ii_dataout;
niiOiO <= wire_nil1il_dataout;
niiOli <= wire_nil1iO_dataout;
niiOll <= wire_nil1li_dataout;
niiOlO <= wire_nil1ll_dataout;
niiOOi <= wire_nil1lO_dataout;
niiOOl <= wire_nil1Oi_dataout;
nil0i <= nl10i;
nil0l <= nl10l;
nil0O <= nl10O;
nilii <= nl1ii;
nilil <= nl1il;
niliO <= nl1iO;
nilli <= nl1li;
nilll <= nl1ll;
nilOi <= nl1Oi;
nlll0l <= wire_n0OOlO_dataout;
nlll0O <= (wire_w_lg_PMADATAWIDTH131w(0) AND (n1l11i OR n1iOOO));
nlllll <= (((n1l10l OR n1l10i) OR (wire_nillO_w_lg_nlO0li881w(0) AND (wire_nillO_w_lg_nlO0iO882w(0) AND wire_nillO_w_lg_w_lg_nlO0il883w884w(0)))) OR wire_nillO_w_lg_nlO0li890w(0));
nllllO <= nlllOi;
nlllOi <= nlllOl;
nlllOl <= n1i1i;
nlllOO <= wire_nlOi0O_dataout;
nllO0i <= wire_nlOili_dataout;
nllO0l <= wire_nlOill_dataout;
nllO0O <= wire_nlOilO_dataout;
nllO1i <= wire_nlOiii_dataout;
nllO1l <= wire_nlOiil_dataout;
nllO1O <= wire_nlOiiO_dataout;
nllOii <= wire_nlOiOi_dataout;
nllOil <= wire_nlOiOl_dataout;
nllOiO <= wire_nlOiOO_dataout;
nllOli <= wire_w_lg_n1l10O879w(0);
nllOll <= (((wire_w_lg_PMADATAWIDTH131w(0) AND (SYNC_SM_DIS AND nlllOl)) OR wire_w_lg_PMADATAWIDTH874w(0)) OR wire_w_lg_w_lg_SYNC_SM_DIS876w877w(0));
nllOlO <= n1l1ii;
nllOOi <= wire_nlOlOO_dataout;
nllOOl <= wire_nlOO1i_dataout;
nllOOO <= wire_nlOO1l_dataout;
nlO00i <= n110i;
nlO00l <= n110l;
nlO00O <= n110O;
nlO01i <= nlO0ll;
nlO01l <= n111l;
nlO01O <= n111O;
nlO0ii <= n11ii;
nlO0il <= n11il;
nlO0iO <= n11iO;
nlO0li <= n11li;
nlO10i <= wire_nlOO0O_dataout;
nlO10l <= wire_nlOOii_dataout;
nlO10O <= nlO1OO;
nlO11i <= wire_nlOO1O_dataout;
nlO11l <= wire_nlOO0i_dataout;
nlO11O <= wire_nlOO0l_dataout;
nlO1ii <= wire_nlOOil_o;
nlO1il <= wire_nlOOiO_o;
nlO1iO <= wire_nlOOli_o;
nlO1li <= wire_nlOOll_o;
nlO1ll <= wire_nlOOlO_o;
nlO1lO <= wire_nlOOOi_o;
nlO1Oi <= wire_nlOOOl_o;
nlO1Ol <= wire_nlOOOO_o;
nlO1OO <= n1lli;
END IF;
END PROCESS;
wire_nillO_PRN <= (n1O1Ol28 XOR n1O1Ol27);
wire_nillO_w_lg_w_lg_w_lg_w2399w2400w2401w2402w(0) <= wire_nillO_w_lg_w_lg_w2399w2400w2401w(0) AND n1il0l;
wire_nillO_w_lg_w_lg_w2399w2400w2401w(0) <= wire_nillO_w_lg_w2399w2400w(0) AND n1il0O;
wire_nillO_w_lg_w2399w2400w(0) <= wire_nillO_w2399w(0) AND n1ilii;
wire_nillO_w2399w(0) <= wire_nillO_w_lg_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w2398w(0) AND n1ilil;
wire_nillO_w_lg_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w2398w(0) <= wire_nillO_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w(0) AND n1iliO;
wire_nillO_w_lg_w_lg_w_lg_nilli1648w1653w1658w(0) <= wire_nillO_w_lg_w_lg_nilli1648w1653w(0) AND nilii;
wire_nillO_w_lg_w_lg_w_lg_nilOi1646w1651w1656w(0) <= wire_nillO_w_lg_w_lg_nilOi1646w1651w(0) AND niliO;
wire_nillO_w_lg_w_lg_w_lg_n1O1O2083w2396w2397w(0) <= wire_nillO_w_lg_w_lg_n1O1O2083w2396w(0) AND n1illi;
wire_nillO_w_lg_w_lg_w_lg_nlO0il883w2447w2448w(0) <= wire_nillO_w_lg_w_lg_nlO0il883w2447w(0) AND n1000O;
wire_nillO_w_lg_w_lg_nilli1648w1653w(0) <= wire_nillO_w_lg_nilli1648w(0) AND nilil;
wire_nillO_w_lg_w_lg_nilOi1646w1651w(0) <= wire_nillO_w_lg_nilOi1646w(0) AND nilli;
wire_nillO_w_lg_w_lg_nlO0il2449w2450w(0) <= wire_nillO_w_lg_nlO0il2449w(0) AND n1000O;
wire_nillO_w_lg_w_lg_n1O1O2083w2396w(0) <= wire_nillO_w_lg_n1O1O2083w(0) AND n1iO1i;
wire_nillO_w_lg_w_lg_nlO00i855w2583w(0) <= wire_nillO_w_lg_nlO00i855w(0) AND n101il;
wire_nillO_w_lg_w_lg_nlO00i855w856w(0) <= wire_nillO_w_lg_nlO00i855w(0) AND n1l1Oi;
wire_nillO_w_lg_w_lg_nlO00O2567w2588w(0) <= wire_nillO_w_lg_nlO00O2567w(0) AND nlO00l;
wire_nillO_w_lg_w_lg_nlO01l2560w2562w(0) <= wire_nillO_w_lg_nlO01l2560w(0) AND wire_nillO_w_lg_nlO01i2561w(0);
wire_nillO_w_lg_w_lg_nlO01l2560w2597w(0) <= wire_nillO_w_lg_nlO01l2560w(0) AND nlO01i;
wire_nillO_w_lg_w_lg_nlO01O2569w2625w(0) <= wire_nillO_w_lg_nlO01O2569w(0) AND n1010i;
wire_nillO_w_lg_w_lg_nlO01O2569w2620w(0) <= wire_nillO_w_lg_nlO01O2569w(0) AND n1010l;
wire_nillO_w_lg_w_lg_nlO01O2569w2608w(0) <= wire_nillO_w_lg_nlO01O2569w(0) AND n1010O;
wire_nillO_w_lg_w_lg_nlO01O2569w2605w(0) <= wire_nillO_w_lg_nlO01O2569w(0) AND n101ii;
wire_nillO_w_lg_w_lg_nlO0ii2442w2476w(0) <= wire_nillO_w_lg_nlO0ii2442w(0) AND n100il;
wire_nillO_w_lg_w_lg_nlO0ii2442w2443w(0) <= wire_nillO_w_lg_nlO0ii2442w(0) AND n1l1il;
wire_nillO_w_lg_w_lg_nlO0il883w2458w(0) <= wire_nillO_w_lg_nlO0il883w(0) AND wire_w_lg_n1l10i2457w(0);
wire_nillO_w_lg_w_lg_nlO0il883w2512w(0) <= wire_nillO_w_lg_nlO0il883w(0) AND wire_nillO_w_lg_nlO0ii2442w(0);
wire_nillO_w_lg_w_lg_nlO0il883w2447w(0) <= wire_nillO_w_lg_nlO0il883w(0) AND n1l10l;
wire_nillO_w_lg_w_lg_nlO0il883w884w(0) <= wire_nillO_w_lg_nlO0il883w(0) AND n1l11O;
wire_nillO_w_lg_w_lg_nlO0il883w2495w(0) <= wire_nillO_w_lg_nlO0il883w(0) AND nlO0ii;
wire_nillO_w_lg_w_lg_nlO0iO882w2459w(0) <= wire_nillO_w_lg_nlO0iO882w(0) AND wire_nillO_w_lg_w_lg_nlO0il883w2458w(0);
wire_nillO_w_lg_w_lg_nlO0iO882w2506w(0) <= wire_nillO_w_lg_nlO0iO882w(0) AND n1001i;
wire_nillO_w_lg_w_lg_nlO0iO882w2533w(0) <= wire_nillO_w_lg_nlO0iO882w(0) AND n101Oi;
wire_nillO_w_lg_w_lg_nlO0iO882w2528w(0) <= wire_nillO_w_lg_nlO0iO882w(0) AND n101Ol;
wire_nillO_w_lg_w_lg_nlO0iO882w2509w(0) <= wire_nillO_w_lg_nlO0iO882w(0) AND n101OO;
wire_nillO_w_lg_w_lg_nlO0li881w2482w(0) <= wire_nillO_w_lg_nlO0li881w(0) AND n100il;
wire_nillO_w_lg_n1O1O2416w(0) <= n1O1O AND wire_w_lg_n1ii1i1979w(0);
wire_nillO_w_lg_nilli1648w(0) <= nilli AND niliO;
wire_nillO_w_lg_nilOi1646w(0) <= nilOi AND nilll;
wire_nillO_w_lg_nlll0l858w(0) <= nlll0l AND wire_w_lg_n1l1Ol857w(0);
wire_nillO_w_lg_nlO00i2626w(0) <= nlO00i AND wire_nillO_w_lg_w_lg_nlO01O2569w2625w(0);
wire_nillO_w_lg_nlO00i2621w(0) <= nlO00i AND wire_nillO_w_lg_w_lg_nlO01O2569w2620w(0);
wire_nillO_w_lg_nlO00i2609w(0) <= nlO00i AND wire_nillO_w_lg_w_lg_nlO01O2569w2608w(0);
wire_nillO_w_lg_nlO00i2606w(0) <= nlO00i AND wire_nillO_w_lg_w_lg_nlO01O2569w2605w(0);
wire_nillO_w_lg_nlO00i2564w(0) <= nlO00i AND wire_nillO_w_lg_nlO01O2563w(0);
wire_nillO_w_lg_nlO00i2629w(0) <= nlO00i AND wire_nillO_w_lg_nlO01O2628w(0);
wire_nillO_w_lg_nlO00i2632w(0) <= nlO00i AND wire_nillO_w_lg_nlO01O2631w(0);
wire_nillO_w_lg_nlO00O2589w(0) <= nlO00O AND wire_nillO_w_lg_nlO00l2568w(0);
wire_nillO_w_lg_nlO01l2598w(0) <= nlO01l AND wire_nillO_w_lg_nlO01i2561w(0);
wire_nillO_w_lg_nlO01O2563w(0) <= nlO01O AND wire_nillO_w_lg_w_lg_nlO01l2560w2562w(0);
wire_nillO_w_lg_nlO01O2628w(0) <= nlO01O AND wire_nillO_w_lg_w_lg_nlO01l2560w2597w(0);
wire_nillO_w_lg_nlO01O2631w(0) <= nlO01O AND wire_nillO_w_lg_nlO01l2598w(0);
wire_nillO_w_lg_nlO0ii865w(0) <= nlO0ii AND n1l1il;
wire_nillO_w_lg_nlO0il2455w(0) <= nlO0il AND wire_w_lg_n1l10l2454w(0);
wire_nillO_w_lg_nlO0il866w(0) <= nlO0il AND wire_nillO_w_lg_nlO0ii865w(0);
wire_nillO_w_lg_nlO0il2496w(0) <= nlO0il AND wire_nillO_w_lg_nlO0ii2442w(0);
wire_nillO_w_lg_nlO0il2449w(0) <= nlO0il AND n1l10i;
wire_nillO_w_lg_nlO0il888w(0) <= nlO0il AND n1l11l;
wire_nillO_w_lg_nlO0iO2513w(0) <= nlO0iO AND wire_nillO_w_lg_w_lg_nlO0il883w2512w(0);
wire_nillO_w_lg_nlO0iO2536w(0) <= nlO0iO AND wire_nillO_w_lg_w_lg_nlO0il883w2495w(0);
wire_nillO_w_lg_nlO0iO2456w(0) <= nlO0iO AND wire_nillO_w_lg_nlO0il2455w(0);
wire_nillO_w_lg_nlO0iO2539w(0) <= nlO0iO AND wire_nillO_w_lg_nlO0il2496w(0);
wire_nillO_w_lg_nlO0iO889w(0) <= nlO0iO AND wire_nillO_w_lg_nlO0il888w(0);
wire_nillO_w_lg_nlO0li2507w(0) <= nlO0li AND wire_nillO_w_lg_w_lg_nlO0iO882w2506w(0);
wire_nillO_w_lg_nlO0li2534w(0) <= nlO0li AND wire_nillO_w_lg_w_lg_nlO0iO882w2533w(0);
wire_nillO_w_lg_nlO0li2529w(0) <= nlO0li AND wire_nillO_w_lg_w_lg_nlO0iO882w2528w(0);
wire_nillO_w_lg_nlO0li2510w(0) <= nlO0li AND wire_nillO_w_lg_w_lg_nlO0iO882w2509w(0);
wire_nillO_w_lg_nlO0li2514w(0) <= nlO0li AND wire_nillO_w_lg_nlO0iO2513w(0);
wire_nillO_w_lg_nlO0li2537w(0) <= nlO0li AND wire_nillO_w_lg_nlO0iO2536w(0);
wire_nillO_w_lg_nlO0li2540w(0) <= nlO0li AND wire_nillO_w_lg_nlO0iO2539w(0);
wire_nillO_w_lg_nlO0li890w(0) <= nlO0li AND wire_nillO_w_lg_nlO0iO889w(0);
wire_nillO_w_lg_w_lg_w_lg_w_lg_nilli1561w1568w1575w1576w(0) <= NOT wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0);
wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1569w(0) <= NOT wire_nillO_w_lg_w_lg_nilli1561w1568w(0);
wire_nillO_w_lg_w_lg_nilli1561w1562w(0) <= NOT wire_nillO_w_lg_nilli1561w(0);
wire_nillO_w_lg_n0001i2740w(0) <= NOT n0001i;
wire_nillO_w_lg_n1lli1498w(0) <= NOT n1lli;
wire_nillO_w_lg_n1O1O2083w(0) <= NOT n1O1O;
wire_nillO_w_lg_n1Ol0i2743w(0) <= NOT n1Ol0i;
wire_nillO_w_lg_nii11i2011w(0) <= NOT nii11i;
wire_nillO_w_lg_niii1l2179w(0) <= NOT niii1l;
wire_nillO_w_lg_niii1O2185w(0) <= NOT niii1O;
wire_nillO_w_lg_niiO1l2180w(0) <= NOT niiO1l;
wire_nillO_w_lg_nil0i2075w(0) <= NOT nil0i;
wire_nillO_w_lg_nil0l2067w(0) <= NOT nil0l;
wire_nillO_w_lg_nil0O2065w(0) <= NOT nil0O;
wire_nillO_w_lg_nilii2063w(0) <= NOT nilii;
wire_nillO_w_lg_nilil2061w(0) <= NOT nilil;
wire_nillO_w_lg_niliO2059w(0) <= NOT niliO;
wire_nillO_w_lg_nilli2089w(0) <= NOT nilli;
wire_nillO_w_lg_nilll2087w(0) <= NOT nilll;
wire_nillO_w_lg_nilOi2382w(0) <= NOT nilOi;
wire_nillO_w_lg_nlll0l845w(0) <= NOT nlll0l;
wire_nillO_w_lg_nlll0O2741w(0) <= NOT nlll0O;
wire_nillO_w_lg_nlllll2714w(0) <= NOT nlllll;
wire_nillO_w_lg_nlO00i855w(0) <= NOT nlO00i;
wire_nillO_w_lg_nlO00l2568w(0) <= NOT nlO00l;
wire_nillO_w_lg_nlO00O2567w(0) <= NOT nlO00O;
wire_nillO_w_lg_nlO01i2561w(0) <= NOT nlO01i;
wire_nillO_w_lg_nlO01l2560w(0) <= NOT nlO01l;
wire_nillO_w_lg_nlO01O2569w(0) <= NOT nlO01O;
wire_nillO_w_lg_nlO0ii2442w(0) <= NOT nlO0ii;
wire_nillO_w_lg_nlO0il883w(0) <= NOT nlO0il;
wire_nillO_w_lg_nlO0iO882w(0) <= NOT nlO0iO;
wire_nillO_w_lg_nlO0li881w(0) <= NOT nlO0li;
wire_nillO_w_lg_w_lg_w_lg_w_lg_nlO0il883w2447w2448w2451w(0) <= wire_nillO_w_lg_w_lg_w_lg_nlO0il883w2447w2448w(0) OR wire_nillO_w_lg_w_lg_nlO0il2449w2450w(0);
wire_nillO_w_lg_w_lg_nlO0iO2456w2460w(0) <= wire_nillO_w_lg_nlO0iO2456w(0) OR wire_nillO_w_lg_w_lg_nlO0iO882w2459w(0);
wire_nillO_w_lg_w_lg_w_lg_nilli1561w1568w1575w(0) <= wire_nillO_w_lg_w_lg_nilli1561w1568w(0) OR nilii;
wire_nillO_w_lg_w_lg_nilli1561w1568w(0) <= wire_nillO_w_lg_nilli1561w(0) OR nilil;
wire_nillO_w_lg_nilli1561w(0) <= nilli OR niliO;
PROCESS (rcvd_clk, wire_nl1lO_PRN, soft_reset)
BEGIN
IF (wire_nl1lO_PRN = '0') THEN
nilOl <= '1';
nilOO <= '1';
niO1i <= '1';
nl1ll <= '1';
nl1Oi <= '1';
ELSIF (soft_reset = '1') THEN
nilOl <= '0';
nilOO <= '0';
niO1i <= '0';
nl1ll <= '0';
nl1Oi <= '0';
ELSIF (rcvd_clk = '0' AND rcvd_clk'event) THEN
IF (PMADATAWIDTH = '0') THEN
nilOl <= niOiO;
nilOO <= niOli;
niO1i <= niOll;
nl1ll <= wire_nliil_dataout;
nl1Oi <= wire_nliiO_dataout;
END IF;
END IF;
END PROCESS;
wire_nl1lO_PRN <= (n1O1OO26 XOR n1O1OO25);
PROCESS (rcvd_clk, soft_reset)
BEGIN
IF (soft_reset = '1') THEN
n0000i <= '0';
n0000l <= '0';
n0000O <= '0';
n0001O <= '0';
n00OlO <= '0';
n00OOi <= '0';
n00OOl <= '0';
n00OOO <= '0';
n0i0OO <= '0';
n0i10i <= '0';
n0i10l <= '0';
n0i10O <= '0';
n0i11i <= '0';
n0i11l <= '0';
n0i11O <= '0';
n0i1ii <= '0';
n0i1il <= '0';
n0i1iO <= '0';
n0i1li <= '0';
n0i1ll <= '0';
n0i1lO <= '0';
n0i1Oi <= '0';
n0ii0i <= '0';
n0ii0l <= '0';
n0ii0O <= '0';
n0ii1i <= '0';
n0ii1l <= '0';
n0ii1O <= '0';
n10ii <= '0';
n10il <= '0';
n10iO <= '0';
n110i <= '0';
n110l <= '0';
n110O <= '0';
n111l <= '0';
n111O <= '0';
n11ii <= '0';
n11il <= '0';
n11iO <= '0';
n11li <= '0';
n11ll <= '0';
n1i1i <= '0';
n1iOi <= '0';
n1iOO <= '0';
n1l0i <= '0';
n1l0l <= '0';
n1l1i <= '0';
n1l1l <= '0';
n1l1O <= '0';
n1llO <= '0';
niO0i <= '0';
niO0l <= '0';
niO0O <= '0';
niO1l <= '0';
niO1O <= '0';
niOii <= '0';
niOil <= '0';
niOiO <= '0';
niOli <= '0';
niOll <= '0';
niOlO <= '0';
niOOi <= '0';
niOOl <= '0';
niOOO <= '0';
nl10i <= '0';
nl10l <= '0';
nl10O <= '0';
nl11i <= '0';
nl11l <= '0';
nl11O <= '0';
nl1ii <= '0';
nl1il <= '0';
nl1iO <= '0';
nl1li <= '0';
nllil <= '0';
nllli <= '0';
nlO0ll <= '0';
ELSIF (rcvd_clk = '0' AND rcvd_clk'event) THEN
n0000i <= prbs_en;
n0000l <= n0000O;
n0000O <= ENCDT;
n0001O <= n0000i;
n00OlO <= n1llii;
n00OOi <= wire_n00Oli_o;
n00OOl <= n1lliO;
n00OOO <= wire_n00O0l_o;
n0i0OO <= n1O11O;
n0i10i <= wire_n00lli_o;
n0i10l <= n1lO0i;
n0i10O <= wire_n00l0l_o;
n0i11i <= n1llll;
n0i11l <= wire_n00lOO_o;
n0i11O <= n1llOi;
n0i1ii <= n1lOlO;
n0i1il <= wire_n00iOO_o;
n0i1iO <= n1O11O;
n0i1li <= wire_n00ili_o;
n0i1ll <= n1O1ll;
n0i1lO <= wire_n00i0l_o;
n0i1Oi <= n1O1ll;
n0ii0i <= n1llll;
n0ii0l <= n1lliO;
n0ii0O <= n1llii;
n0ii1i <= n1lOlO;
n0ii1l <= n1lO0i;
n0ii1O <= n1llOi;
n10ii <= n10il;
n10il <= n10iO;
n10iO <= BITSLIP;
n110i <= wire_n11OO_o;
n110l <= wire_n101i_o;
n110O <= wire_n101l_o;
n111l <= wire_n11Oi_o;
n111O <= wire_n11Ol_o;
n11ii <= wire_n101O_o;
n11il <= wire_n100i_o;
n11iO <= wire_n100l_o;
n11li <= wire_n100O_o;
n11ll <= (n10il AND wire_nlliO_w_lg_n10ii771w(0));
n1i1i <= (NOT (wire_nllll_w_lg_w_lg_w_lg_n1liO362w363w364w(0) OR ((((NOT (n1l0O XOR n1l1l)) AND (NOT (n1lii XOR n1l1O))) AND (NOT (n1lil XOR n1l0i))) AND (NOT (n1liO XOR n1l0l)))));
n1iOi <= n1iOO;
n1iOO <= n1l1i;
n1l0i <= n1lOO;
n1l0l <= n1O1l;
n1l1i <= A1A2_SIZE;
n1l1l <= n1lOi;
n1l1O <= n1lOl;
n1llO <= n1li0O;
niO0i <= wire_nl01i_dataout;
niO0l <= wire_nl01l_dataout;
niO0O <= wire_nl01O_dataout;
niO1l <= wire_nl1Ol_dataout;
niO1O <= wire_nl1OO_dataout;
niOii <= wire_nl00i_dataout;
niOil <= wire_nl00l_dataout;
niOiO <= wire_nl00O_dataout;
niOli <= wire_nl0ii_dataout;
niOll <= wire_nl0il_dataout;
niOlO <= wire_nl0iO_dataout;
niOOi <= wire_nl0li_dataout;
niOOl <= wire_nl0ll_dataout;
niOOO <= wire_nl0lO_dataout;
nl10i <= wire_nli1i_dataout;
nl10l <= wire_nli1l_dataout;
nl10O <= wire_nli1O_dataout;
nl11i <= wire_nl0Oi_dataout;
nl11l <= wire_nl0Ol_dataout;
nl11O <= wire_nl0OO_dataout;
nl1ii <= wire_nli0i_dataout;
nl1il <= wire_nli0l_dataout;
nl1iO <= wire_nli0O_dataout;
nl1li <= wire_nliii_dataout;
nllil <= wire_nlill_o;
nllli <= wire_nlilO_o;
nlO0ll <= wire_n11lO_o;
END IF;
END PROCESS;
wire_nlliO_w_lg_w_lg_n0i10O219w222w(0) <= wire_nlliO_w_lg_n0i10O219w(0) AND wire_n1llOl48_w_lg_q221w(0);
wire_nlliO_w_lg_n0000l60w(0) <= n0000l AND wire_w_lg_n1Oi1O59w(0);
wire_nlliO_w_lg_n00OOi254w(0) <= n00OOi AND wire_nlliO_w_lg_n00OlO253w(0);
wire_nlliO_w_lg_n00OOO246w(0) <= n00OOO AND wire_nlliO_w_lg_n00OOl245w(0);
wire_nlliO_w_lg_n0i10i230w(0) <= n0i10i AND wire_nlliO_w_lg_n0i11O229w(0);
wire_nlliO_w_lg_n0i10O219w(0) <= n0i10O AND wire_nlliO_w_lg_n0i10l218w(0);
wire_nlliO_w_lg_n0i11l238w(0) <= n0i11l AND wire_nlliO_w_lg_n0i11i237w(0);
wire_nlliO_w_lg_n0i1il205w(0) <= n0i1il AND wire_nlliO_w_lg_n0i1ii204w(0);
wire_nlliO_w_lg_n0i1li183w(0) <= n0i1li AND wire_nlliO_w_lg_n0i1iO182w(0);
wire_nlliO_w_lg_n0i1lO168w(0) <= n0i1lO AND wire_nlliO_w_lg_n0i1ll167w(0);
wire_nlliO_w_lg_n1iOO210w(0) <= n1iOO AND wire_w_lg_w_lg_n1lOll206w209w(0);
wire_nlliO_w_lg_n1iOO188w(0) <= n1iOO AND wire_w_lg_w_lg_n1O11l184w187w(0);
wire_nlliO_w_lg_n1iOO256w(0) <= n1iOO AND wire_w_lg_n1ll0O255w(0);
wire_nlliO_w_lg_n1iOO248w(0) <= n1iOO AND wire_w_lg_n1llil247w(0);
wire_nlliO_w_lg_n1iOO240w(0) <= n1iOO AND wire_w_lg_n1llli239w(0);
wire_nlliO_w_lg_n1iOO232w(0) <= n1iOO AND wire_w_lg_n1lllO231w(0);
wire_nlliO_w_lg_n1iOO224w(0) <= n1iOO AND wire_w_lg_n1lO1O223w(0);
wire_nlliO_w_lg_n1iOO170w(0) <= n1iOO AND wire_w_lg_n1O1li169w(0);
wire_nlliO_w_lg_n0000l72w(0) <= NOT n0000l;
wire_nlliO_w_lg_n00OlO253w(0) <= NOT n00OlO;
wire_nlliO_w_lg_n00OOl245w(0) <= NOT n00OOl;
wire_nlliO_w_lg_n0i10l218w(0) <= NOT n0i10l;
wire_nlliO_w_lg_n0i11i237w(0) <= NOT n0i11i;
wire_nlliO_w_lg_n0i11O229w(0) <= NOT n0i11O;
wire_nlliO_w_lg_n0i1ii204w(0) <= NOT n0i1ii;
wire_nlliO_w_lg_n0i1iO182w(0) <= NOT n0i1iO;
wire_nlliO_w_lg_n0i1ll167w(0) <= NOT n0i1ll;
wire_nlliO_w_lg_n10ii771w(0) <= NOT n10ii;
wire_nlliO_w_lg_n1iOO161w(0) <= NOT n1iOO;
PROCESS (rcvd_clk, soft_reset)
BEGIN
IF (soft_reset = '1') THEN
n001Ol <= '1';
n1Ol0l <= '1';
ni0l0l <= '1';
nlllil <= '1';
ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN
n001Ol <= wire_n011lO_o;
n1Ol0l <= wire_n1OO1l_o;
ni0l0l <= wire_nillO_w_lg_nii11i2011w(0);
nlllil <= (n1l1ii OR wire_w_lg_n1l10O879w(0));
END IF;
if (now = 0 ns) then
n001Ol <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1Ol0l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
ni0l0l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlllil <= '1' after 1 ps;
end if;
END PROCESS;
wire_nlllii_w_lg_nlllil2715w(0) <= NOT nlllil;
PROCESS (rcvd_clk, wire_nllll_PRN, wire_nllll_CLRN)
BEGIN
IF (wire_nllll_PRN = '0') THEN
n0001l <= '1';
n1l0O <= '1';
n1lii <= '1';
n1lil <= '1';
n1liO <= '1';
nlllO <= '1';
ELSIF (wire_nllll_CLRN = '0') THEN
n0001l <= '0';
n1l0O <= '0';
n1lii <= '0';
n1lil <= '0';
n1liO <= '0';
nlllO <= '0';
ELSIF (rcvd_clk = '0' AND rcvd_clk'event) THEN
n0001l <= n1Ol0l;
n1l0O <= wire_w_lg_n1O0ll54w(0);
n1lii <= n1O0lO;
n1lil <= n1O0Oi;
n1liO <= n1O0Ol;
nlllO <= wire_nliOi_o;
END IF;
if (now = 0 ns) then
n0001l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1l0O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1lii <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1lil <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1liO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlllO <= '1' after 1 ps;
end if;
END PROCESS;
wire_nllll_CLRN <= (n1Oi0O6 XOR n1Oi0O5);
wire_nllll_PRN <= ((n1Oi0l8 XOR n1Oi0l7) AND wire_w_lg_soft_reset46w(0));
wire_nllll_w_lg_w_lg_w_lg_n1liO362w363w364w(0) <= wire_nllll_w_lg_w_lg_n1liO362w363w(0) AND n1l0O;
wire_nllll_w_lg_w_lg_n1liO362w363w(0) <= wire_nllll_w_lg_n1liO362w(0) AND n1lii;
wire_nllll_w_lg_n1liO362w(0) <= n1liO AND n1lil;
wire_n000O_dataout <= ((wire_nlliO_w_lg_n1iOO161w(0) AND (n1lllO AND n0ii1O)) OR wire_nlliO_w_lg_n1iOO232w(0)) WHEN PMADATAWIDTH = '1' ELSE (n1llOi OR n1lllO);
wire_n000O_w_lg_dataout274w(0) <= NOT wire_n000O_dataout;
wire_n0011i_dataout <= wire_nillO_w_lg_n1Ol0i2743w(0) OR NOT(n1011i);
wire_n001O_dataout <= ((wire_nlliO_w_lg_n1iOO161w(0) AND (n1llli AND n0ii0i)) OR wire_nlliO_w_lg_n1iOO240w(0)) WHEN PMADATAWIDTH = '1' ELSE (n1llll OR n1llli);
wire_n001O_w_lg_dataout269w(0) <= NOT wire_n001O_dataout;
wire_n00i0O_dataout <= n1O1li OR n1O1ll;
wire_n00ill_dataout <= n1O11l OR n1O11O;
wire_n00iO_dataout <= (((wire_nlliO_w_lg_n1iOO161w(0) AND (n1lO1O AND n0ii1l)) AND (n1lO1i46 XOR n1lO1i45)) OR wire_nlliO_w_lg_n1iOO224w(0)) WHEN PMADATAWIDTH = '1' ELSE (n1lO0i OR n1lO1O);
wire_n00iO_w_lg_dataout280w(0) <= NOT wire_n00iO_dataout;
wire_n00l0O_dataout <= n1lO1O OR n1lO0i;
wire_n00l1i_dataout <= n1lOll OR n1lOlO;
wire_n00lll_dataout <= n1lllO OR n1llOi;
wire_n00lO_dataout <= ((wire_nlliO_w_lg_n1iOO161w(0) AND ((n1lOll AND n0ii1i) AND (n1lOii42 XOR n1lOii41))) OR wire_nlliO_w_lg_n1iOO210w(0)) WHEN PMADATAWIDTH = '1' ELSE ((n1lOlO OR n1lOll) OR (NOT (n1lOiO40 XOR n1lOiO39)));
wire_n00lO_w_lg_dataout287w(0) <= NOT wire_n00lO_dataout;
wire_n00O0O_dataout <= n1llil OR n1lliO;
wire_n00O1i_dataout <= n1llli OR n1llll;
wire_n00Oll_dataout <= n1ll0O OR n1llii;
wire_n00OO_dataout <= (((wire_nlliO_w_lg_n1iOO161w(0) AND (n1O11l AND n0i0OO)) OR wire_nlliO_w_lg_n1iOO188w(0)) OR (NOT (n1lOOi38 XOR n1lOOi37))) WHEN PMADATAWIDTH = '1' ELSE (n1O11O OR n1O11l);
wire_n00OO_w_lg_dataout295w(0) <= NOT wire_n00OO_dataout;
wire_n0100i_dataout <= wire_n01iiO_o(1) AND NOT(n11OiO);
wire_n0100l_dataout <= n0101l AND NOT(n11OiO);
wire_n0101i_dataout <= n11O0l AND NOT(n11OiO);
wire_n0101O_dataout <= wire_n01iiO_o(0) AND NOT(n11OiO);
wire_n010i_dataout <= n10li WHEN AUTOBYTEALIGN_DIS = '1' ELSE n1lOi;
wire_n010ii_dataout <= wire_n010ll_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n010il_dataout <= wire_n010lO_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n010iO_dataout <= wire_n010Oi_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n010l_dataout <= n10lO WHEN AUTOBYTEALIGN_DIS = '1' ELSE n1lOl;
wire_n010li_dataout <= wire_n010Ol_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n010ll_dataout <= wire_n010OO_dataout AND NOT(n11O0O);
wire_n010lO_dataout <= wire_n01i1i_dataout AND NOT(n11O0O);
wire_n010O_dataout <= n10Oi WHEN AUTOBYTEALIGN_DIS = '1' ELSE n1lOO;
wire_n010Oi_dataout <= wire_w_lg_n11O0l2776w(0) AND NOT(n11O0O);
wire_n010Ol_dataout <= n11O0l AND NOT(n11O0O);
wire_n010OO_dataout <= wire_n01iiO_o(0) AND NOT(n11O0l);
wire_n011Oi_dataout <= wire_n010OO_dataout AND NOT(n11OiO);
wire_n011Ol_dataout <= wire_n01i1i_dataout AND NOT(n11OiO);
wire_n011OO_dataout <= wire_w_lg_n11O0l2776w(0) AND NOT(n11OiO);
wire_n01i0i_dataout <= wire_n01iii_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01i0l_dataout <= wire_n01iil_dataout AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01i0O_dataout <= wire_w_lg_n11O0O2761w(0) AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01i1i_dataout <= wire_n01iiO_o(1) AND NOT(n11O0l);
wire_n01ii_dataout <= n10OO WHEN AUTOBYTEALIGN_DIS = '1' ELSE n1O1l;
wire_n01iii_dataout <= wire_n01iiO_o(0) AND NOT(n11O0O);
wire_n01iil_dataout <= wire_n01iiO_o(1) AND NOT(n11O0O);
wire_n01il_dataout <= (n1ll1O OR n1ll1l) AND NOT(PMADATAWIDTH);
wire_n01il_w_lg_dataout1489w(0) <= NOT wire_n01il_dataout;
wire_n01il_w_lg_dataout305w(0) <= wire_n01il_dataout OR wire_w_lg_n1ll1i304w(0);
wire_n01ili_dataout <= n1Ol0l OR wire_nillO_w_lg_n0001i2740w(0);
wire_n01ill_dataout <= n0101l AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01ilO_dataout <= n11O0O AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01iOi_dataout <= wire_w_lg_n11O0O2761w(0) AND NOT(wire_nillO_w_lg_n0001i2740w(0));
wire_n01iOO_dataout <= n0101l WHEN n11Oil = '1' ELSE wire_n01l0i_dataout;
wire_n01l0i_dataout <= n0101l OR n11Oii;
wire_n01l1i_dataout <= n1Ol0l OR n11Oil;
wire_n01l1l_dataout <= n11Oii AND NOT(n11Oil);
wire_n01l1O_dataout <= wire_w_lg_n11Oii2759w(0) AND NOT(n11Oil);
wire_n01li_dataout <= (n1ll0l OR n1ll0i) AND NOT(PMADATAWIDTH);
wire_n01li_w_lg_dataout260w(0) <= NOT wire_n01li_dataout;
wire_n01lO_dataout <= ((wire_nlliO_w_lg_n1iOO161w(0) AND (n1ll0O AND n0ii0O)) OR wire_nlliO_w_lg_n1iOO256w(0)) WHEN PMADATAWIDTH = '1' ELSE (n1llii OR n1ll0O);
wire_n01lO_w_lg_dataout262w(0) <= NOT wire_n01lO_dataout;
wire_n01lOi_dataout <= wire_nillO_w_lg_n1Ol0i2743w(0) WHEN n11OiO = '1' ELSE wire_n01O1l_dataout;
wire_n01lOl_dataout <= n1Ol0l OR n11OiO;
wire_n01lOO_dataout <= wire_w_lg_n11Oli2749w(0) AND NOT(n11OiO);
wire_n01O0l_dataout <= wire_nillO_w_lg_n1Ol0i2743w(0) WHEN n11OOl = '1' ELSE wire_n01Oli_dataout;
wire_n01O0O_dataout <= n1Ol0l OR n11OOl;
wire_n01O1i_dataout <= n11Oli AND NOT(n11OiO);
wire_n01O1l_dataout <= wire_nillO_w_lg_n1Ol0i2743w(0) OR n11Oli;
wire_n01Oii_dataout <= n11OlO AND NOT(n11OOl);
wire_n01Oil_dataout <= wire_n01Oll_dataout AND NOT(n11OOl);
wire_n01OiO_dataout <= wire_n01OlO_dataout AND NOT(n11OOl);
wire_n01Oli_dataout <= wire_nillO_w_lg_n1Ol0i2743w(0) WHEN n11OlO = '1' ELSE n1Ol0i;
wire_n01Oll_dataout <= n11Oll AND NOT(n11OlO);
wire_n01OlO_dataout <= wire_w_lg_n11Oll2746w(0) AND NOT(n11OlO);
wire_n01OO_dataout <= ((wire_nlliO_w_lg_n1iOO161w(0) AND (n1llil AND n0ii0l)) OR wire_nlliO_w_lg_n1iOO248w(0)) WHEN PMADATAWIDTH = '1' ELSE (n1lliO OR n1llil);
wire_n01OO_w_lg_dataout265w(0) <= NOT wire_n01OO_dataout;
wire_n01OOO_dataout <= n1Ol0l AND n1011i;
wire_n0i0O_dataout <= niOiO WHEN n1O1lO = '1' ELSE wire_n0l1i_dataout;
wire_n0i1O_dataout <= ((((wire_nlliO_w_lg_n1iOO161w(0) AND (n1O1li AND n0i1Oi)) AND (n1O1il30 XOR n1O1il29)) OR (wire_nlliO_w_lg_n1iOO170w(0) AND (n1O10O32 XOR n1O10O31))) OR (NOT (n1O10i34 XOR n1O10i33))) WHEN PMADATAWIDTH = '1' ELSE (n1O1ll OR n1O1li);
wire_n0i1O_w_lg_dataout1481w(0) <= wire_n0i1O_dataout AND wire_n00OO_w_lg_dataout295w(0);
wire_n0iii_dataout <= niOli WHEN n1O1lO = '1' ELSE wire_n0l1l_dataout;
wire_n0iil_dataout <= niOll WHEN n1O1lO = '1' ELSE wire_n0l1O_dataout;
wire_n0iiO_dataout <= niOlO WHEN n1O1lO = '1' ELSE wire_n0l0i_dataout;
wire_n0ili_dataout <= niOOi WHEN n1O1lO = '1' ELSE wire_n0l0l_dataout;
wire_n0ill_dataout <= niOOl WHEN n1O1lO = '1' ELSE wire_n0l0O_dataout;
wire_n0ilO_dataout <= niOOO WHEN n1O1lO = '1' ELSE wire_n0lii_dataout;
wire_n0iOi_dataout <= wire_n0lil_dataout AND NOT(n1O1lO);
wire_n0iOl_dataout <= wire_n0liO_dataout AND NOT(n1O1lO);
wire_n0iOO_dataout <= wire_n0lli_dataout AND NOT(n1O1lO);
wire_n0l0i_dataout <= niOlO AND NOT(n1O1Oi);
wire_n0l0ii_dataout <= nlll0l WHEN ((wire_nillO_w_lg_w_lg_nlO00i855w2583w(0) OR (nlO00i AND n1l1Oi)) OR (n1l00l AND n1l01l)) = '1' ELSE (n1l1Ol OR n1l1OO);
wire_n0l0ii_w_lg_w_lg_dataout862w2579w(0) <= wire_n0l0ii_w_lg_dataout862w(0) AND n101li;
wire_n0l0ii_w_lg_dataout862w(0) <= NOT wire_n0l0ii_dataout;
wire_n0l0l_dataout <= niOOi AND NOT(n1O1Oi);
wire_n0l0O_dataout <= niOOl AND NOT(n1O1Oi);
wire_n0l1i_dataout <= niOiO AND NOT(n1O1Oi);
wire_n0l1l_dataout <= niOli AND NOT(n1O1Oi);
wire_n0l1O_dataout <= niOll AND NOT(n1O1Oi);
wire_n0lii_dataout <= niOOO AND NOT(n1O1Oi);
wire_n0lil_dataout <= nl11i AND NOT(n1O1Oi);
wire_n0liO_dataout <= nl11l AND NOT(n1O1Oi);
wire_n0lli_dataout <= nl11O AND NOT(n1O1Oi);
wire_n0lll_dataout <= niOli WHEN n1O1lO = '1' ELSE wire_n0l1l_dataout;
wire_n0llO_dataout <= niOll WHEN n1O1lO = '1' ELSE wire_n0l1O_dataout;
wire_n0lOi_dataout <= niOlO WHEN n1O1lO = '1' ELSE wire_n0l0i_dataout;
wire_n0lOl_dataout <= niOOi WHEN n1O1lO = '1' ELSE wire_n0l0l_dataout;
wire_n0lOO_dataout <= niOOl WHEN n1O1lO = '1' ELSE wire_n0l0O_dataout;
wire_n0O0i_dataout <= wire_n0lli_dataout AND NOT(n1O1lO);
wire_n0O0l_dataout <= wire_n0O0O_dataout AND NOT(n1O1lO);
wire_n0O0O_dataout <= nl10i AND NOT(n1O1Oi);
wire_n0O1i_dataout <= niOOO WHEN n1O1lO = '1' ELSE wire_n0lii_dataout;
wire_n0O1l_dataout <= nl11i WHEN n1O1lO = '1' ELSE wire_n0lil_dataout;
wire_n0O1O_dataout <= wire_n0liO_dataout AND NOT(n1O1lO);
wire_n0Oii_dataout <= nl11O AND NOT(n1O1lO);
wire_n0Oil_dataout <= wire_n0O0O_dataout AND NOT(n1O1lO);
wire_n0OiO_dataout <= wire_n0Oli_dataout AND NOT(n1O1lO);
wire_n0Oli_dataout <= nl10l AND NOT(n1O1Oi);
wire_n0Oll_dataout <= nl10i AND NOT(n1O1lO);
wire_n0OlO_dataout <= wire_n0Oli_dataout AND NOT(n1O1lO);
wire_n0OOi_dataout <= wire_n0OOl_dataout AND NOT(n1O1lO);
wire_n0OOl_dataout <= nl10O AND NOT(n1O1Oi);
wire_n0OOlO_dataout <= wire_n0l0ii_dataout WHEN ((nlO0il XOR nlO0ii) AND n1l1il) = '1' ELSE (n1l1iO OR n1l1lO);
wire_n0OOO_dataout <= nl10l AND NOT(n1O1lO);
wire_n1i0i_dataout <= wire_n1iil_dataout AND NOT(n1li1O);
wire_n1i0l_dataout <= wire_n1iiO_dataout OR n1li1O;
wire_n1i0O_dataout <= wire_n1ili_o(1) OR n1li1l;
wire_n1i1l_dataout <= wire_n1i0O_dataout OR n1li1O;
wire_n1i1O_dataout <= wire_n1iii_dataout AND NOT(n1li1O);
wire_n1iii_dataout <= wire_n1ili_o(2) OR n1li1l;
wire_n1iil_dataout <= wire_n1ili_o(3) OR n1li1l;
wire_n1iiO_dataout <= wire_n1ili_o(4) AND NOT(n1li1l);
wire_n1Olii_dataout <= encdet_prbs WHEN n0001O = '1' ELSE wire_n1Olil_dataout;
wire_n1Olil_dataout <= wire_n1OliO_dataout WHEN SYNC_SM_DIS = '1' ELSE n0001l;
wire_n1OliO_dataout <= wire_nlili_o WHEN PMADATAWIDTH = '1' ELSE n0000l;
wire_ni000i_dataout <= niii0i AND NOT(n10i1l);
wire_ni000l_dataout <= niii0l AND NOT(n10i1l);
wire_ni000O_dataout <= niii0O AND NOT(n10i1l);
wire_ni001l_dataout <= wire_ni0iOi_dataout AND ni0l0i;
wire_ni001O_dataout <= nii11i AND ni0l0l;
wire_ni00i_dataout <= nl1ll AND NOT(n1O1Oi);
wire_ni00ii_dataout <= niiiii AND NOT(n10i1l);
wire_ni00il_dataout <= wire_ni00ll_dataout AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni00iO_dataout <= n10i1i AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni00l_dataout <= nl1li AND NOT(n1O1lO);
wire_ni00li_dataout <= wire_ni00lO_dataout AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni00ll_dataout <= wire_w_lg_n100OO2188w(0) AND NOT(n10i1i);
wire_ni00lO_dataout <= n100OO AND NOT(n10i1i);
wire_ni00O_dataout <= wire_ni00i_dataout AND NOT(n1O1lO);
wire_ni00OO_dataout <= niiO1O AND NOT(n10i1l);
wire_ni01i_dataout <= nl1iO AND NOT(n1O1lO);
wire_ni01l_dataout <= wire_ni1OO_dataout AND NOT(n1O1lO);
wire_ni01lO_dataout <= wire_ni0ilO_dataout AND ni0l0i;
wire_ni01O_dataout <= wire_ni00i_dataout AND NOT(n1O1lO);
wire_ni0i0l_dataout <= n10i0i AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni0i0O_dataout <= wire_ni0iil_dataout AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni0i1i_dataout <= niiO0i AND NOT(n10i1l);
wire_ni0i1l_dataout <= niiO0l AND NOT(n10i1l);
wire_ni0i1O_dataout <= niiO0O AND NOT(n10i1l);
wire_ni0ii_dataout <= wire_ni0il_dataout AND NOT(n1O1lO);
wire_ni0iii_dataout <= wire_ni0iiO_dataout AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni0iil_dataout <= wire_w_lg_n10i1O2183w(0) AND NOT(n10i0i);
wire_ni0iiO_dataout <= n10i1O AND NOT(n10i0i);
wire_ni0il_dataout <= nl1Oi AND NOT(n1O1Oi);
wire_ni0ilO_dataout <= niii1l AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni0iO_dataout <= (NOT SYNC_COMP_PAT(0)) WHEN n1O1lO = '1' ELSE wire_nii0i_dataout;
wire_ni0iOi_dataout <= wire_nillO_w_lg_niii1l2179w(0) AND NOT(wire_nillO_w_lg_nii11i2011w(0));
wire_ni0li_dataout <= (NOT SYNC_COMP_PAT(1)) WHEN n1O1lO = '1' ELSE wire_nii0l_dataout;
wire_ni0lii_dataout <= RUNDISP_SEL(0) AND NOT(PMADATAWIDTH);
wire_ni0lii_w_lg_dataout2438w(0) <= NOT wire_ni0lii_dataout;
wire_ni0lil_dataout <= RUNDISP_SEL(1) AND NOT(PMADATAWIDTH);
wire_ni0lil_w_lg_dataout2436w(0) <= NOT wire_ni0lil_dataout;
wire_ni0liO_dataout <= RUNDISP_SEL(0) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(0);
wire_ni0ll_dataout <= (NOT SYNC_COMP_PAT(2)) WHEN n1O1lO = '1' ELSE wire_nii0O_dataout;
wire_ni0lli_dataout <= RUNDISP_SEL(1) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(1);
wire_ni0lli_w_lg_dataout2433w(0) <= NOT wire_ni0lli_dataout;
wire_ni0lll_dataout <= RUNDISP_SEL(2) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(2);
wire_ni0lll_w_lg_dataout2431w(0) <= NOT wire_ni0lll_dataout;
wire_ni0llO_dataout <= RUNDISP_SEL(3) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(3);
wire_ni0llO_w_lg_dataout2429w(0) <= NOT wire_ni0llO_dataout;
wire_ni0lO_dataout <= (NOT SYNC_COMP_PAT(3)) WHEN n1O1lO = '1' ELSE wire_niiii_dataout;
wire_ni0lOi_dataout <= RUNDISP_SEL(4) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(4);
wire_ni0lOi_w_lg_dataout2427w(0) <= NOT wire_ni0lOi_dataout;
wire_ni0lOl_dataout <= wire_w_lg_n10i0l2156w(0) WHEN PMADATAWIDTH = '1' ELSE wire_ni0lOO_o(5);
wire_ni0lOl_w_lg_w2434w2435w(0) <= wire_ni0lOl_w2434w(0) AND wire_ni0liO_dataout;
wire_ni0lOl_w2434w(0) <= wire_ni0lOl_w_lg_w_lg_w_lg_w_lg_dataout2426w2428w2430w2432w(0) AND wire_ni0lli_w_lg_dataout2433w(0);
wire_ni0lOl_w_lg_w_lg_w_lg_w_lg_dataout2426w2428w2430w2432w(0) <= wire_ni0lOl_w_lg_w_lg_w_lg_dataout2426w2428w2430w(0) AND wire_ni0lll_w_lg_dataout2431w(0);
wire_ni0lOl_w_lg_w_lg_w_lg_dataout2426w2428w2430w(0) <= wire_ni0lOl_w_lg_w_lg_dataout2426w2428w(0) AND wire_ni0llO_w_lg_dataout2429w(0);
wire_ni0lOl_w_lg_w_lg_dataout2426w2428w(0) <= wire_ni0lOl_w_lg_dataout2426w(0) AND wire_ni0lOi_w_lg_dataout2427w(0);
wire_ni0lOl_w_lg_dataout2426w(0) <= NOT wire_ni0lOl_dataout;
wire_ni0Oi_dataout <= (NOT SYNC_COMP_PAT(4)) WHEN n1O1lO = '1' ELSE wire_niiil_dataout;
wire_ni0Ol_dataout <= (NOT SYNC_COMP_PAT(5)) WHEN n1O1lO = '1' ELSE wire_niiiO_dataout;
wire_ni0Oli_dataout <= ni0O0O AND nii11i;
wire_ni0Oll_dataout <= ni0Oii AND nii11i;
wire_ni0OlO_dataout <= n1Ol1l AND nii11i;
wire_ni0OO_dataout <= (NOT SYNC_COMP_PAT(6)) WHEN n1O1lO = '1' ELSE wire_niili_dataout;
wire_ni0OOi_dataout <= wire_ni0OOl_o AND nii11i;
wire_ni10i_dataout <= nl10O AND NOT(n1O1lO);
wire_ni10l_dataout <= wire_ni11O_dataout AND NOT(n1O1lO);
wire_ni10O_dataout <= wire_ni1ii_dataout AND NOT(n1O1lO);
wire_ni11i_dataout <= wire_n0OOl_dataout AND NOT(n1O1lO);
wire_ni11l_dataout <= wire_ni11O_dataout AND NOT(n1O1lO);
wire_ni11O_dataout <= nl1ii AND NOT(n1O1Oi);
wire_ni1ii_dataout <= nl1il AND NOT(n1O1Oi);
wire_ni1il_dataout <= nl1ii AND NOT(n1O1lO);
wire_ni1iO_dataout <= wire_ni1ii_dataout AND NOT(n1O1lO);
wire_ni1li_dataout <= wire_ni1ll_dataout AND NOT(n1O1lO);
wire_ni1ll_dataout <= nl1iO AND NOT(n1O1Oi);
wire_ni1lO_dataout <= nl1il AND NOT(n1O1lO);
wire_ni1O0i_dataout <= wire_ni1O0O_o(2) WHEN wire_ni1Oii_o(4) = '1' ELSE wire_ni1Oll_dataout;
wire_ni1O0l_dataout <= wire_ni1O0O_o(3) WHEN wire_ni1Oii_o(4) = '1' ELSE wire_ni1OlO_dataout;
wire_ni1O1l_dataout <= wire_ni1O0O_o(0) WHEN wire_ni1Oii_o(4) = '1' ELSE wire_ni1Oil_dataout;
wire_ni1O1O_dataout <= wire_ni1O0O_o(1) WHEN wire_ni1Oii_o(4) = '1' ELSE wire_ni1OiO_dataout;
wire_ni1Oi_dataout <= wire_ni1ll_dataout AND NOT(n1O1lO);
wire_ni1Oil_dataout <= ni1llO AND n100iO;
wire_ni1OiO_dataout <= ni1lOi AND n100iO;
wire_ni1Ol_dataout <= wire_ni1OO_dataout AND NOT(n1O1lO);
wire_ni1Oll_dataout <= ni1lOl AND n100iO;
wire_ni1OlO_dataout <= ni1lOO AND n100iO;
wire_ni1OO_dataout <= nl1li AND NOT(n1O1Oi);
wire_nii0i_dataout <= SYNC_COMP_PAT(8) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(0));
wire_nii0l_dataout <= SYNC_COMP_PAT(9) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(1));
wire_nii0O_dataout <= SYNC_COMP_PAT(10) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(2));
wire_nii1i_dataout <= wire_niill_dataout AND NOT(n1O1lO);
wire_nii1l_dataout <= wire_niilO_dataout AND NOT(n1O1lO);
wire_nii1O_dataout <= wire_niiOi_dataout AND NOT(n1O1lO);
wire_niii1i_dataout <= n10i0O WHEN PMADATAWIDTH = '1' ELSE n10iii;
wire_niii1i_w_lg_dataout2009w(0) <= NOT wire_niii1i_dataout;
wire_niiii_dataout <= SYNC_COMP_PAT(11) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(3));
wire_niiil_dataout <= SYNC_COMP_PAT(12) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(4));
wire_niiiO_dataout <= SYNC_COMP_PAT(13) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(5));
wire_niil0i_dataout <= (wire_w_lg_w_lg_PMADATAWIDTH131w1988w(0) OR (PMADATAWIDTH AND n1ii1i)) AND nii11i;
wire_niil0l_dataout <= n10lii AND nii11i;
wire_niil0O_dataout <= n10liO AND nii11i;
wire_niil1l_dataout <= (wire_w_lg_n10iOl1991w(0) OR (wire_w_lg_n10iOi1992w(0) OR (wire_w_lg_n10ilO1993w(0) OR (wire_w_lg_n10ill1994w(0) OR (wire_w_lg_n10ili1995w(0) OR (wire_w_lg_n10iiO1996w(0) OR wire_w_lg_n10iil1997w(0))))))) AND nii11i;
wire_niil1O_dataout <= (n1il1i OR n1iiOO) AND nii11i;
wire_niili_dataout <= SYNC_COMP_PAT(14) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(6));
wire_niilii_dataout <= (((wire_w_lg_n10lOO1920w(0) OR wire_w_lg_n10lOl1922w(0)) OR wire_w_lg_n10lOi1930w(0)) OR wire_w_lg_n10llO1986w(0)) AND nii11i;
wire_niilil_dataout <= (wire_w_lg_n1i01l1978w(0) OR (NOT ((wire_w_lg_n1ii1i1979w(0) OR n1i01O) OR n1i01l))) AND nii11i;
wire_niiliO_dataout <= niiilO AND nii11i;
wire_niill_dataout <= SYNC_COMP_PAT(15) WHEN n1O1Oi = '1' ELSE (NOT SYNC_COMP_PAT(7));
wire_niilli_dataout <= niiiOi AND nii11i;
wire_niilll_dataout <= niiiOl AND nii11i;
wire_niillO_dataout <= niiiOO AND nii11i;
wire_niilO_dataout <= (NOT SYNC_COMP_PAT(8)) AND NOT(n1O1Oi);
wire_niilOi_dataout <= n10O1l AND nii11i;
wire_niilOl_dataout <= n10O0i AND nii11i;
wire_niilOO_dataout <= (((wire_w_lg_n10Oli1865w(0) OR wire_w_lg_n10OiO1867w(0)) OR wire_w_lg_n10Oil1875w(0)) OR wire_w_lg_n10Oii1976w(0)) AND nii11i;
wire_niiO1i_dataout <= (wire_w_lg_n1i0ll1968w(0) OR (NOT ((wire_w_lg_n1i0OO1969w(0) OR n1i0Oi) OR n1i0ll))) AND nii11i;
wire_niiOi_dataout <= (NOT SYNC_COMP_PAT(9)) AND NOT(n1O1Oi);
wire_niiOl_dataout <= SYNC_COMP_PAT(7) AND NOT(n1O1lO);
wire_niiOO_dataout <= wire_nil1l_dataout AND NOT(n1O1lO);
wire_niiOOO_dataout <= (wire_w_lg_n10l0O1955w(0) OR (wire_w_lg_n10l0l1956w(0) OR (wire_w_lg_n10l0i1957w(0) OR (wire_w_lg_n10l1O1958w(0) OR (wire_w_lg_n10l1l1959w(0) OR (wire_w_lg_n10l1i1960w(0) OR wire_w_lg_n10iOO1961w(0))))))) AND nii11i;
wire_nil10i_dataout <= (((wire_w_lg_n1i10l1810w(0) OR wire_w_lg_n1i10i1812w(0)) OR wire_w_lg_n1i11O1820w(0)) OR wire_w_lg_n1i11l1951w(0)) AND nii11i;
wire_nil10l_dataout <= (wire_w_lg_n1il1l1944w(0) OR (NOT ((n1iO1i OR n1il1O) OR n1il1l))) AND nii11i;
wire_nil10O_dataout <= niiOll AND nii11i;
wire_nil11i_dataout <= (wire_w_lg_w_lg_PMADATAWIDTH131w1953w(0) OR wire_w_lg_PMADATAWIDTH1605w(0)) AND nii11i;
wire_nil11l_dataout <= n10OlO AND nii11i;
wire_nil11O_dataout <= n10OOl AND nii11i;
wire_nil1i_dataout <= wire_nil1O_dataout AND NOT(n1O1lO);
wire_nil1ii_dataout <= niiOlO AND nii11i;
wire_nil1il_dataout <= niiOOi AND nii11i;
wire_nil1iO_dataout <= niiOOl AND nii11i;
wire_nil1l_dataout <= SYNC_COMP_PAT(8) AND NOT(n1O1Oi);
wire_nil1li_dataout <= n1i1ii AND nii11i;
wire_nil1ll_dataout <= n1i1iO AND nii11i;
wire_nil1lO_dataout <= (((wire_w_lg_n1i1OO1756w(0) OR wire_w_lg_n1i1Ol1758w(0)) OR wire_w_lg_n1i1Oi1766w(0)) OR wire_w_lg_n1i1lO1942w(0)) AND nii11i;
wire_nil1O_dataout <= SYNC_COMP_PAT(9) AND NOT(n1O1Oi);
wire_nil1Oi_dataout <= (wire_w_lg_n1illl1934w(0) OR (NOT ((wire_w_lg_n1ilOO1935w(0) OR n1ilOi) OR n1illl))) AND nii11i;
wire_nl00i_dataout <= nl11l WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOOO;
wire_nl00l_dataout <= nl11O WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl11i;
wire_nl00O_dataout <= nl10i WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl11l;
wire_nl01i_dataout <= niOOl WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOlO;
wire_nl01l_dataout <= niOOO WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOOi;
wire_nl01O_dataout <= nl11i WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOOl;
wire_nl0ii_dataout <= nl10l WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl11O;
wire_nl0il_dataout <= nl10O WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl10i;
wire_nl0iO_dataout <= nl1ii WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl10l;
wire_nl0li_dataout <= nl1il WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl10O;
wire_nl0ll_dataout <= nl1iO WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl1ii;
wire_nl0lO_dataout <= nl1li WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl1il;
wire_nl0Oi_dataout <= nl1ll WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl1iO;
wire_nl0Ol_dataout <= nl1Oi WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE nl1li;
wire_nl0OO_dataout <= PUDR(0) WHEN LP10BEN = '1' ELSE PUDI(0);
wire_nl1Ol_dataout <= niOlO WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOli;
wire_nl1OO_dataout <= niOOi WHEN wire_w_lg_PMADATAWIDTH131w(0) = '1' ELSE niOll;
wire_nli0i_dataout <= PUDR(4) WHEN LP10BEN = '1' ELSE PUDI(4);
wire_nli0l_dataout <= PUDR(5) WHEN LP10BEN = '1' ELSE PUDI(5);
wire_nli0O_dataout <= PUDR(6) WHEN LP10BEN = '1' ELSE PUDI(6);
wire_nli1i_dataout <= PUDR(1) WHEN LP10BEN = '1' ELSE PUDI(1);
wire_nli1l_dataout <= PUDR(2) WHEN LP10BEN = '1' ELSE PUDI(2);
wire_nli1O_dataout <= PUDR(3) WHEN LP10BEN = '1' ELSE PUDI(3);
wire_nliii_dataout <= PUDR(7) WHEN LP10BEN = '1' ELSE PUDI(7);
wire_nliil_dataout <= PUDR(8) WHEN LP10BEN = '1' ELSE PUDI(8);
wire_nliiO_dataout <= PUDR(9) WHEN LP10BEN = '1' ELSE PUDI(9);
wire_nliOl_dataout <= n1O0OO OR n1O00O;
wire_nliOO_dataout <= n1O0OO AND NOT(n1O00O);
wire_nll0i_dataout <= wire_w_lg_n1O00O64w(0) AND NOT(n1O0OO);
wire_nll1i_dataout <= wire_w_lg_n1O0OO65w(0) AND NOT(n1O00O);
wire_nll1l_dataout <= n1O00O OR n1O0OO;
wire_nll1O_dataout <= n1O00O AND NOT(n1O0OO);
wire_nlOi0O_dataout <= SYNC_COMP_PAT(0) WHEN n1l0li = '1' ELSE wire_nlOl1i_dataout;
wire_nlOiii_dataout <= SYNC_COMP_PAT(1) WHEN n1l0li = '1' ELSE wire_nlOl1l_dataout;
wire_nlOiil_dataout <= SYNC_COMP_PAT(2) WHEN n1l0li = '1' ELSE wire_nlOl1O_dataout;
wire_nlOiiO_dataout <= SYNC_COMP_PAT(3) WHEN n1l0li = '1' ELSE wire_nlOl0i_dataout;
wire_nlOili_dataout <= SYNC_COMP_PAT(4) WHEN n1l0li = '1' ELSE wire_nlOl0l_dataout;
wire_nlOill_dataout <= SYNC_COMP_PAT(5) WHEN n1l0li = '1' ELSE wire_nlOl0O_dataout;
wire_nlOilO_dataout <= SYNC_COMP_PAT(6) WHEN n1l0li = '1' ELSE wire_nlOlii_dataout;
wire_nlOiOi_dataout <= SYNC_COMP_PAT(7) WHEN n1l0li = '1' ELSE wire_nlOlil_dataout;
wire_nlOiOl_dataout <= nlO10O WHEN n1l0li = '1' ELSE wire_nlOliO_dataout;
wire_nlOiOO_dataout <= wire_nlOlli_dataout AND NOT(n1l0li);
wire_nlOl0i_dataout <= nlO11i WHEN n1l0iO = '1' ELSE nlO00i;
wire_nlOl0l_dataout <= nlO11l WHEN n1l0iO = '1' ELSE nlO00l;
wire_nlOl0O_dataout <= nlO11O WHEN n1l0iO = '1' ELSE nlO00O;
wire_nlOl1i_dataout <= nllOOi WHEN n1l0iO = '1' ELSE nlO01i;
wire_nlOl1l_dataout <= nllOOl WHEN n1l0iO = '1' ELSE nlO01l;
wire_nlOl1O_dataout <= nllOOO WHEN n1l0iO = '1' ELSE nlO01O;
wire_nlOlii_dataout <= nlO10i WHEN n1l0iO = '1' ELSE nlO0ii;
wire_nlOlil_dataout <= nlO10l WHEN n1l0iO = '1' ELSE nlO0il;
wire_nlOliO_dataout <= nlO10O WHEN n1l0iO = '1' ELSE nlO0iO;
wire_nlOlli_dataout <= nlO0li AND NOT(n1l0iO);
wire_nlOlOO_dataout <= SYNC_COMP_PAT(0) WHEN n1l0ll = '1' ELSE nlO1ii;
wire_nlOO0i_dataout <= SYNC_COMP_PAT(4) WHEN n1l0ll = '1' ELSE nlO1ll;
wire_nlOO0l_dataout <= SYNC_COMP_PAT(5) WHEN n1l0ll = '1' ELSE nlO1lO;
wire_nlOO0O_dataout <= SYNC_COMP_PAT(6) WHEN n1l0ll = '1' ELSE nlO1Oi;
wire_nlOO1i_dataout <= SYNC_COMP_PAT(1) WHEN n1l0ll = '1' ELSE nlO1il;
wire_nlOO1l_dataout <= SYNC_COMP_PAT(2) WHEN n1l0ll = '1' ELSE nlO1iO;
wire_nlOO1O_dataout <= SYNC_COMP_PAT(3) WHEN n1l0ll = '1' ELSE nlO1li;
wire_nlOOii_dataout <= SYNC_COMP_PAT(7) WHEN n1l0ll = '1' ELSE nlO1Ol;
wire_n01iiO_a <= ( n1Olli & n1Ol0O);
wire_n01iiO_b <= ( "0" & "1");
n01iiO : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 2,
width_b => 2,
width_o => 2
)
PORT MAP (
a => wire_n01iiO_a,
b => wire_n01iiO_b,
cin => wire_gnd,
o => wire_n01iiO_o
);
wire_n1ili_a <= ( n10OO & n10Oi & n10lO & n10li & "1");
wire_n1ili_b <= ( "1" & "1" & "1" & "0" & "1");
n1ili : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 5,
width_b => 5,
width_o => 5
)
PORT MAP (
a => wire_n1ili_a,
b => wire_n1ili_b,
cin => wire_gnd,
o => wire_n1ili_o
);
wire_ni0lOO_a <= ( "0" & "0" & wire_w_lg_n10i0l2156w & RUNDISP_SEL(4 DOWNTO 2));
wire_ni0lOO_b <= ( wire_w_lg_n10i0l2156w & RUNDISP_SEL(4 DOWNTO 0));
ni0lOO : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 6,
width_b => 6,
width_o => 6
)
PORT MAP (
a => wire_ni0lOO_a,
b => wire_ni0lOO_b,
cin => wire_gnd,
o => wire_ni0lOO_o
);
wire_ni1O0O_a <= ( wire_ni1OlO_dataout & wire_ni1Oll_dataout & wire_ni1OiO_dataout & wire_ni1Oil_dataout);
wire_ni1O0O_b <= ( "0" & "0" & "0" & "1");
ni1O0O : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 4,
width_b => 4,
width_o => 4
)
PORT MAP (
a => wire_ni1O0O_a,
b => wire_ni1O0O_b,
cin => wire_gnd,
o => wire_ni1O0O_o
);
wire_ni1Oii_a <= ( "0" & wire_ni010O_o & wire_ni010l_o & wire_ni010i_o & wire_ni011O_o);
wire_ni1Oii_b <= ( "0" & wire_ni011i_o & wire_ni1OOO_o & wire_ni1OOl_o & wire_ni1OOi_o);
ni1Oii : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 5,
width_b => 5,
width_o => 5
)
PORT MAP (
a => wire_ni1Oii_a,
b => wire_ni1Oii_b,
cin => wire_gnd,
o => wire_ni1Oii_o
);
wire_ni0OOl_a <= ( wire_ni0lOl_dataout & wire_ni0lOi_dataout & wire_ni0llO_dataout & wire_ni0lll_dataout & wire_ni0lli_dataout & wire_ni0liO_dataout & wire_ni0lil_dataout & wire_ni0lii_dataout);
wire_ni0OOl_b <= ( ni1lOO & ni1lOl & ni1lOi & ni1llO & ni1lll & ni1lli & ni1liO & ni1Oli);
ni0OOl : oper_less_than
GENERIC MAP (
sgate_representation => 0,
width_a => 8,
width_b => 8
)
PORT MAP (
a => wire_ni0OOl_a,
b => wire_ni0OOl_b,
cin => wire_gnd,
o => wire_ni0OOl_o
);
wire_n00i0l_data <= ( wire_n00i0O_dataout & "0" & n1O1ll & "0");
wire_n00i0l_sel <= ( n0i1lO & n0i1ll);
n00i0l : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00i0l_data,
o => wire_n00i0l_o,
sel => wire_n00i0l_sel
);
wire_n00ili_data <= ( wire_n00ill_dataout & "0" & n1O11O & "0");
wire_n00ili_sel <= ( n0i1li & n0i1iO);
n00ili : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00ili_data,
o => wire_n00ili_o,
sel => wire_n00ili_sel
);
wire_n00iOO_data <= ( wire_n00l1i_dataout & "0" & n1lOlO & "0");
wire_n00iOO_sel <= ( n0i1il & n0i1ii);
n00iOO : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00iOO_data,
o => wire_n00iOO_o,
sel => wire_n00iOO_sel
);
wire_n00l0l_data <= ( wire_n00l0O_dataout & "0" & n1lO0i & "0");
wire_n00l0l_sel <= ( n0i10O & n0i10l);
n00l0l : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00l0l_data,
o => wire_n00l0l_o,
sel => wire_n00l0l_sel
);
wire_n00lli_data <= ( wire_n00lll_dataout & "0" & n1llOi & "0");
wire_n00lli_sel <= ( n0i10i & n0i11O);
n00lli : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00lli_data,
o => wire_n00lli_o,
sel => wire_n00lli_sel
);
wire_n00lOO_data <= ( wire_n00O1i_dataout & "0" & n1llll & "0");
wire_n00lOO_sel <= ( n0i11l & n0i11i);
n00lOO : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00lOO_data,
o => wire_n00lOO_o,
sel => wire_n00lOO_sel
);
wire_n00O0l_data <= ( wire_n00O0O_dataout & "0" & n1lliO & "0");
wire_n00O0l_sel <= ( n00OOO & n00OOl);
n00O0l : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00O0l_data,
o => wire_n00O0l_o,
sel => wire_n00O0l_sel
);
wire_n00Oli_data <= ( wire_n00Oll_dataout & "0" & n1llii & "0");
wire_n00Oli_sel <= ( n00OOi & n00OlO);
n00Oli : oper_mux
GENERIC MAP (
width_data => 4,
width_sel => 2
)
PORT MAP (
data => wire_n00Oli_data,
o => wire_n00Oli_o,
sel => wire_n00Oli_sel
);
wire_n100i_data <= ( niOOO & niOOO & niOOO & niOOO & niOOO & niOOO & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO & nl11i & nl11l & niOOO & niOOO & niOOO & niOOO & niOOO & niOOO & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO);
wire_n100i_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n100i : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n100i_data,
o => wire_n100i_o,
sel => wire_n100i_sel
);
wire_n100l_data <= ( nl11i & nl11i & nl11i & nl11i & nl11i & nl11i & n11iO & n11iO & n11iO & n11iO & n11iO & n11iO & n11iO & n11iO & n11iO & n11iO & nl11i & nl11i & nl11i & nl11i & nl11i & nl11i & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO & nl11i);
wire_n100l_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n100l : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n100l_data,
o => wire_n100l_o,
sel => wire_n100l_sel
);
wire_n100O_data <= ( nl11l & nl11l & nl11l & nl11l & nl11l & nl11l & n11li & n11li & n11li & n11li & n11li & n11li & n11li & n11li & n11li & n11li & nl11l & nl11l & nl11l & nl11l & nl11l & nl11l & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO & nl11i & nl11l);
wire_n100O_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n100O : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n100O_data,
o => wire_n100O_o,
sel => wire_n100O_sel
);
wire_n101i_data <= ( niOlO & niOlO & niOlO & niOlO & niOlO & niOlO & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOlO & niOlO & niOlO & niOlO & niOlO & niOlO & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO);
wire_n101i_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n101i : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n101i_data,
o => wire_n101i_o,
sel => wire_n101i_sel
);
wire_n101l_data <= ( niOOi & niOOi & niOOi & niOOi & niOOi & niOOi & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO & niOOi & niOOi & niOOi & niOOi & niOOi & niOOi & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi);
wire_n101l_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n101l : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n101l_data,
o => wire_n101l_o,
sel => wire_n101l_sel
);
wire_n101O_data <= ( niOOl & niOOl & niOOl & niOOl & niOOl & niOOl & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl & niOOO & nl11i & niOOl & niOOl & niOOl & niOOl & niOOl & niOOl & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOOl);
wire_n101O_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n101O : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n101O_data,
o => wire_n101O_o,
sel => wire_n101O_sel
);
wire_n11lO_data <= ( niOil & niOil & niOil & niOil & niOil & niOil & niO1i & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOil & niOil & niOil & niOil & niOil & niOil & nilOl & nilOO & niO1i & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil);
wire_n11lO_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n11lO : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n11lO_data,
o => wire_n11lO_o,
sel => wire_n11lO_sel
);
wire_n11Oi_data <= ( niOiO & niOiO & niOiO & niOiO & niOiO & niOiO & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOiO & niOiO & niOiO & niOiO & niOiO & niOiO & nilOO & niO1i & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO);
wire_n11Oi_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n11Oi : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n11Oi_data,
o => wire_n11Oi_o,
sel => wire_n11Oi_sel
);
wire_n11Ol_data <= ( niOli & niOli & niOli & niOli & niOli & niOli & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOli & niOli & niOli & niOli & niOli & niOli & niO1i & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli);
wire_n11Ol_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n11Ol : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n11Ol_data,
o => wire_n11Ol_o,
sel => wire_n11Ol_sel
);
wire_n11OO_data <= ( niOll & niOll & niOll & niOll & niOll & niOll & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll & niOlO & niOOi & niOll & niOll & niOll & niOll & niOll & niOll & niO1l & niO1O & niO0i & niO0l & niO0O & niOii & niOil & niOiO & niOli & niOll);
wire_n11OO_sel <= ( PMADATAWIDTH & wire_n01ii_dataout & wire_n010O_dataout & wire_n010l_dataout & wire_n010i_dataout);
n11OO : oper_mux
GENERIC MAP (
width_data => 32,
width_sel => 5
)
PORT MAP (
data => wire_n11OO_data,
o => wire_n11OO_o,
sel => wire_n11OO_sel
);
wire_n0110i_data <= ( "0" & wire_n01Oii_dataout & wire_n01lOO_dataout);
wire_n0110i_sel <= ( n11O1i & n001Oi & n001li);
n0110i : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n0110i_data,
o => wire_n0110i_o,
sel => wire_n0110i_sel
);
wire_n0110O_data <= ( "0" & wire_n01Oil_dataout & wire_n01O1i_dataout & wire_n01l1O_dataout);
wire_n0110O_sel <= ( n11O1l & n001lO & n001iO & n001ll);
n0110O : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n0110O_data,
o => wire_n0110O_o,
sel => wire_n0110O_sel
);
wire_n0111l_data <= ( "0" & wire_n01Oii_dataout & wire_n01lOO_dataout);
wire_n0111l_sel <= ( n11lOO & n001lO & n001iO);
n0111l : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n0111l_data,
o => wire_n0111l_o,
sel => wire_n0111l_sel
);
wire_n011il_data <= ( "0" & wire_n01Oil_dataout & wire_n01O1i_dataout & wire_n01OiO_dataout);
wire_n011il_sel <= ( n11O1O & n001Oi & n001li & n001lO);
n011il : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n011il_data,
o => wire_n011il_o,
sel => wire_n011il_sel
);
wire_n011li_data <= ( wire_w_lg_n1011i2824w & wire_n01OiO_dataout & "0");
wire_n011li_sel <= ( n001Ol & n001Oi & n11O0i);
n011li : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n011li_data,
o => wire_n011li_o,
sel => wire_n011li_sel
);
wire_n011lO_data <= ( n1011i & n11OOl & n11OiO & n11OOl & n11OiO & n11Oil & wire_nillO_w_lg_n0001i2740w & wire_nillO_w_lg_n0001i2740w & wire_nillO_w_lg_n0001i2740w & wire_nillO_w_lg_n0001i2740w & wire_nillO_w_lg_n0001i2740w & n11OiO & n11OiO);
wire_n011lO_sel <= ( n001Ol & n001Oi & n001li & n001lO & n001iO & n001ll & n001il & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n011lO : oper_selector
GENERIC MAP (
width_data => 13,
width_sel => 13
)
PORT MAP (
data => wire_n011lO_data,
o => wire_n011lO_o,
sel => wire_n011lO_sel
);
wire_n1OllO_data <= ( "0" & wire_n01i0i_dataout & wire_n010ii_dataout & wire_n01i0i_dataout & wire_n010ii_dataout & wire_n0101O_dataout & wire_n011Oi_dataout);
wire_n1OllO_sel <= ( n11lii & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n1OllO : oper_selector
GENERIC MAP (
width_data => 7,
width_sel => 7
)
PORT MAP (
data => wire_n1OllO_data,
o => wire_n1OllO_o,
sel => wire_n1OllO_sel
);
wire_n1OlOi_data <= ( "0" & wire_n01i0l_dataout & wire_n010il_dataout & wire_n01i0l_dataout & wire_n010il_dataout & wire_n0100i_dataout & wire_n011Ol_dataout);
wire_n1OlOi_sel <= ( n11lii & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n1OlOi : oper_selector
GENERIC MAP (
width_data => 7,
width_sel => 7
)
PORT MAP (
data => wire_n1OlOi_data,
o => wire_n1OlOi_o,
sel => wire_n1OlOi_sel
);
wire_n1OlOO_data <= ( n0101l & wire_n01iOO_dataout & wire_n01ill_dataout & wire_n01ill_dataout & wire_n01ill_dataout & wire_n01ill_dataout & wire_n01ill_dataout & wire_n0100l_dataout & wire_n0100l_dataout);
wire_n1OlOO_sel <= ( n11lil & n001ll & n001il & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n1OlOO : oper_selector
GENERIC MAP (
width_data => 9,
width_sel => 9
)
PORT MAP (
data => wire_n1OlOO_data,
o => wire_n1OlOO_o,
sel => wire_n1OlOO_sel
);
wire_n1OO0i_data <= ( "0" & wire_w_lg_n11OiO2992w & wire_n011OO_dataout);
wire_n1OO0i_sel <= ( n11liO & n0011O & n1Olll);
n1OO0i : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n1OO0i_data,
o => wire_n1OO0i_o,
sel => wire_n1OO0i_sel
);
wire_n1OO0O_data <= ( "0" & wire_n01ilO_dataout);
wire_n1OO0O_sel <= ( n11lli & wire_w_lg_n11lli2976w);
n1OO0O : oper_selector
GENERIC MAP (
width_data => 2,
width_sel => 2
)
PORT MAP (
data => wire_n1OO0O_data,
o => wire_n1OO0O_o,
sel => wire_n1OO0O_sel
);
wire_n1OO1l_data <= ( wire_n01OOO_dataout & wire_n01O0O_dataout & wire_n01lOl_dataout & wire_n01O0O_dataout & wire_n01lOl_dataout & wire_n01l1i_dataout & wire_n01ili_dataout & wire_n01ili_dataout & wire_n01ili_dataout & wire_n01ili_dataout & wire_n01ili_dataout & wire_n01lOl_dataout & wire_n01lOl_dataout);
wire_n1OO1l_sel <= ( n001Ol & n001Oi & n001li & n001lO & n001iO & n001ll & n001il & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n1OO1l : oper_selector
GENERIC MAP (
width_data => 13,
width_sel => 13
)
PORT MAP (
data => wire_n1OO1l_data,
o => wire_n1OO1l_o,
sel => wire_n1OO1l_sel
);
wire_n1OO1O_data <= ( wire_n0011i_dataout & wire_n01O0l_dataout & wire_n01lOi_dataout & wire_n01O0l_dataout & wire_n01lOi_dataout & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w & wire_nillO_w_lg_n1Ol0i2743w);
wire_n1OO1O_sel <= ( n001Ol & n001Oi & n001li & n001lO & n001iO & n001ll & n001il & n001ii & n0010O & n0010l & n0010i & n0011O & n1Olll);
n1OO1O : oper_selector
GENERIC MAP (
width_data => 13,
width_sel => 13
)
PORT MAP (
data => wire_n1OO1O_data,
o => wire_n1OO1O_o,
sel => wire_n1OO1O_sel
);
wire_n1OOii_data <= ( "0" & wire_n01i0O_dataout & wire_n010iO_dataout);
wire_n1OOii_sel <= ( n11lli & n0010l & n0010i);
n1OOii : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n1OOii_data,
o => wire_n1OOii_o,
sel => wire_n1OOii_sel
);
wire_n1OOiO_data <= ( "0" & wire_n01ilO_dataout & wire_n01ilO_dataout & wire_n0101i_dataout);
wire_n1OOiO_sel <= ( n11lll & n001ii & n0010O & n1Olll);
n1OOiO : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n1OOiO_data,
o => wire_n1OOiO_o,
sel => wire_n1OOiO_sel
);
wire_n1OOll_data <= ( "0" & wire_n01i0O_dataout & wire_n010iO_dataout);
wire_n1OOll_sel <= ( n11llO & n001ii & n0010O);
n1OOll : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n1OOll_data,
o => wire_n1OOll_o,
sel => wire_n1OOll_sel
);
wire_n1OOOi_data <= ( "0" & wire_n01ilO_dataout & wire_n010li_dataout);
wire_n1OOOi_sel <= ( n11lOi & n001il & n0010i);
n1OOOi : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n1OOOi_data,
o => wire_n1OOOi_o,
sel => wire_n1OOOi_sel
);
wire_n1OOOO_data <= ( "0" & wire_n01l1l_dataout & wire_n01iOi_dataout & wire_n010li_dataout);
wire_n1OOOO_sel <= ( n11lOl & n001ll & n001il & n0010O);
n1OOOO : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n1OOOO_data,
o => wire_n1OOOO_o,
sel => wire_n1OOOO_sel
);
wire_ni010i_data <= ( "0" & niiO0i & wire_ni0i1i_dataout & niii0l & wire_ni000l_dataout);
wire_ni010i_sel <= ( n100Ol & n100ll & ni0l1i & n100li & ni1O1i);
ni010i : oper_selector
GENERIC MAP (
width_data => 5,
width_sel => 5
)
PORT MAP (
data => wire_ni010i_data,
o => wire_ni010i_o,
sel => wire_ni010i_sel
);
wire_ni010l_data <= ( "0" & niiO0l & wire_ni0i1l_dataout & niii0O & wire_ni000O_dataout);
wire_ni010l_sel <= ( n100Ol & n100ll & ni0l1i & n100li & ni1O1i);
ni010l : oper_selector
GENERIC MAP (
width_data => 5,
width_sel => 5
)
PORT MAP (
data => wire_ni010l_data,
o => wire_ni010l_o,
sel => wire_ni010l_sel
);
wire_ni010O_data <= ( "0" & niiO0O & wire_ni0i1O_dataout & niiiii & wire_ni00ii_dataout);
wire_ni010O_sel <= ( n100Ol & n100ll & ni0l1i & n100li & ni1O1i);
ni010O : oper_selector
GENERIC MAP (
width_data => 5,
width_sel => 5
)
PORT MAP (
data => wire_ni010O_data,
o => wire_ni010O_o,
sel => wire_ni010O_sel
);
wire_ni011i_data <= ( "0" & niiOli & ni1lll & niiill);
wire_ni011i_sel <= ( n100Ol & n100ll & n100iO & n100li);
ni011i : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_ni011i_data,
o => wire_ni011i_o,
sel => wire_ni011i_sel
);
wire_ni011O_data <= ( "0" & niiO1O & wire_ni00OO_dataout & niii0i & wire_ni000i_dataout);
wire_ni011O_sel <= ( n100Ol & n100ll & ni0l1i & n100li & ni1O1i);
ni011O : oper_selector
GENERIC MAP (
width_data => 5,
width_sel => 5
)
PORT MAP (
data => wire_ni011O_data,
o => wire_ni011O_o,
sel => wire_ni011O_sel
);
wire_ni01iO_data <= ( "0" & wire_ni00il_dataout);
wire_ni01iO_sel <= ( n100lO & wire_w_lg_n100lO2238w);
ni01iO : oper_selector
GENERIC MAP (
width_data => 2,
width_sel => 2
)
PORT MAP (
data => wire_ni01iO_data,
o => wire_ni01iO_o,
sel => wire_ni01iO_sel
);
wire_ni01ll_data <= ( "0" & wire_ni0i0l_dataout & wire_ni0i0l_dataout & wire_ni0i0l_dataout & wire_ni00iO_dataout & wire_ni00iO_dataout & wire_ni00iO_dataout);
wire_ni01ll_sel <= ( n100Ol & ni0l1O & ni0l1l & ni0l1i & ni0iOO & ni0iOl & ni1O1i);
ni01ll : oper_selector
GENERIC MAP (
width_data => 7,
width_sel => 7
)
PORT MAP (
data => wire_ni01ll_data,
o => wire_ni01ll_o,
sel => wire_ni01ll_sel
);
wire_ni01Oi_data <= ( "0" & wire_ni0i0O_dataout);
wire_ni01Oi_sel <= ( n100Oi & wire_w_lg_n100Oi2210w);
ni01Oi : oper_selector
GENERIC MAP (
width_data => 2,
width_sel => 2
)
PORT MAP (
data => wire_ni01Oi_data,
o => wire_ni01Oi_o,
sel => wire_ni01Oi_sel
);
wire_ni01OO_data <= ( "0" & wire_ni0iii_dataout & wire_ni0iii_dataout & wire_ni0iii_dataout & wire_ni00li_dataout & wire_ni00li_dataout & wire_ni00li_dataout);
wire_ni01OO_sel <= ( n100Ol & ni0l1O & ni0l1l & ni0l1i & ni0iOO & ni0iOl & ni1O1i);
ni01OO : oper_selector
GENERIC MAP (
width_data => 7,
width_sel => 7
)
PORT MAP (
data => wire_ni01OO_data,
o => wire_ni01OO_o,
sel => wire_ni01OO_sel
);
wire_ni1OOi_data <= ( "0" & niiOii & ni1Oli & niiiil);
wire_ni1OOi_sel <= ( n100Ol & n100ll & n100iO & n100li);
ni1OOi : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_ni1OOi_data,
o => wire_ni1OOi_o,
sel => wire_ni1OOi_sel
);
wire_ni1OOl_data <= ( "0" & niiOil & ni1liO & niiiiO);
wire_ni1OOl_sel <= ( n100Ol & n100ll & n100iO & n100li);
ni1OOl : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_ni1OOl_data,
o => wire_ni1OOl_o,
sel => wire_ni1OOl_sel
);
wire_ni1OOO_data <= ( "0" & niiOiO & ni1lli & niiili);
wire_ni1OOO_sel <= ( n100Ol & n100ll & n100iO & n100li);
ni1OOO : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_ni1OOO_data,
o => wire_ni1OOO_o,
sel => wire_ni1OOO_sel
);
wire_nlili_data <= ( wire_nll1l_dataout & wire_nliOl_dataout & "0");
wire_nlili_sel <= ( nlllO & nllli & nllil);
nlili : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlili_data,
o => wire_nlili_o,
sel => wire_nlili_sel
);
wire_nlill_data <= ( wire_n1O01i24_w_lg_w_lg_q99w100w & wire_n1O01l22_w_lg_w_lg_q96w97w & n0000l);
wire_nlill_sel <= ( nlllO & nllli & wire_n1O01O20_w_lg_w_lg_q88w89w);
nlill : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlill_data,
o => wire_nlill_o,
sel => wire_nlill_sel
);
wire_nlilO_data <= ( n1O0OO & wire_nliOO_dataout & "0");
wire_nlilO_sel <= ( nlllO & wire_n1O00i18_w_lg_w_lg_q79w80w & nllil);
nlilO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlilO_data,
o => wire_nlilO_o,
sel => wire_nlilO_sel
);
wire_nliOi_data <= ( wire_nll0i_dataout & wire_nll1i_dataout & wire_nlliO_w_lg_n0000l72w);
wire_nliOi_sel <= ( nlllO & wire_n1O00l16_w_lg_w_lg_q68w69w & nllil);
nliOi : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nliOi_data,
o => wire_nliOi_o,
sel => wire_nliOi_sel
);
wire_nlOOil_data <= ( SYNC_COMP_PAT(8) & SYNC_COMP_PAT(0) & nlO01i);
wire_nlOOil_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOil : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOil_data,
o => wire_nlOOil_o,
sel => wire_nlOOil_sel
);
wire_nlOOiO_data <= ( SYNC_COMP_PAT(9) & SYNC_COMP_PAT(1) & nlO01l);
wire_nlOOiO_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOiO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOiO_data,
o => wire_nlOOiO_o,
sel => wire_nlOOiO_sel
);
wire_nlOOli_data <= ( SYNC_COMP_PAT(10) & SYNC_COMP_PAT(2) & nlO01O);
wire_nlOOli_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOli : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOli_data,
o => wire_nlOOli_o,
sel => wire_nlOOli_sel
);
wire_nlOOll_data <= ( SYNC_COMP_PAT(11) & SYNC_COMP_PAT(3) & nlO00i);
wire_nlOOll_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOll : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOll_data,
o => wire_nlOOll_o,
sel => wire_nlOOll_sel
);
wire_nlOOlO_data <= ( SYNC_COMP_PAT(12) & SYNC_COMP_PAT(4) & nlO00l);
wire_nlOOlO_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOlO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOlO_data,
o => wire_nlOOlO_o,
sel => wire_nlOOlO_sel
);
wire_nlOOOi_data <= ( SYNC_COMP_PAT(13) & SYNC_COMP_PAT(5) & nlO00O);
wire_nlOOOi_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOOi : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOOi_data,
o => wire_nlOOOi_o,
sel => wire_nlOOOi_sel
);
wire_nlOOOl_data <= ( SYNC_COMP_PAT(14) & SYNC_COMP_PAT(6) & nlO0ii);
wire_nlOOOl_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOOl : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOOl_data,
o => wire_nlOOOl_o,
sel => wire_nlOOOl_sel
);
wire_nlOOOO_data <= ( SYNC_COMP_PAT(15) & SYNC_COMP_PAT(7) & nlO0il);
wire_nlOOOO_sel <= ( n1l0Ol & n1l0Oi & wire_w_lg_n1l0lO774w);
nlOOOO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOOOO_data,
o => wire_nlOOOO_o,
sel => wire_nlOOOO_sel
);
END RTL; --stratixgx_hssi_rx_wal_rtl
--synopsys translate_on
--VALID FILE
--
-- STRATIXGX_HSSI_WORD_ALIGNER
--
library IEEE, stratixgx_gxb;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_hssi_word_aligner IS
generic (
channel_width : integer := 10;
align_pattern_length: integer := 10;
infiniband_invalid_code: integer := 0;
align_pattern : string := "0000000101111100";
synchronization_mode: string := "XAUI";
use_8b_10b_mode : string := "true";
use_auto_bit_slip : string := "true");
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
clk : IN std_logic;
softreset : IN std_logic;
enacdet : IN std_logic;
bitslip : IN std_logic;
a1a2size : IN std_logic;
aligneddata : OUT std_logic_vector(9 DOWNTO 0);
aligneddatapre : OUT std_logic_vector(9 DOWNTO 0);
invalidcode : OUT std_logic;
invalidcodepre : OUT std_logic;
syncstatus : OUT std_logic;
syncstatusdeskew : OUT std_logic;
disperr : OUT std_logic;
disperrpre : OUT std_logic;
patterndetectpre : OUT std_logic;
patterndetect : OUT std_logic);
END stratixgx_hssi_word_aligner;
ARCHITECTURE auto_translated OF stratixgx_hssi_word_aligner IS
COMPONENT stratixgx_hssi_rx_wal_rtl
PORT (
rcvd_clk : IN std_logic;
soft_reset : IN std_logic;
LP10BEN : IN std_logic;
RLV_EN : IN std_logic;
RUNDISP_SEL : IN std_logic_vector(4 DOWNTO 0);
PMADATAWIDTH : IN std_logic;
SYNC_COMP_PAT : IN std_logic_vector(15 DOWNTO 0);
SYNC_COMP_SIZE : IN std_logic_vector(1 DOWNTO 0);
IB_INVALID_CODE : IN std_logic_vector(1 DOWNTO 0);
AUTOBYTEALIGN_DIS : IN std_logic;
BITSLIP : IN std_logic;
DISABLE_RX_DISP : IN std_logic;
ENCDT : IN std_logic;
SYNC_SM_DIS : IN std_logic;
prbs_en : IN std_logic;
encdet_prbs : IN std_logic;
GE_XAUI_SEL : IN std_logic;
signal_detect : IN std_logic;
PUDI : IN std_logic_vector(9 DOWNTO 0);
PUDR : IN std_logic_vector(9 DOWNTO 0);
A1A2_SIZE : IN std_logic;
DWIDTH : IN std_logic;
cg_comma : OUT std_logic;
sync_status : OUT std_logic;
signal_detect_sync : OUT std_logic;
SUDI : OUT std_logic_vector(12 DOWNTO 0);
SUDI_pre : OUT std_logic_vector(9 DOWNTO 0);
RLV : OUT std_logic;
RLV_lt : OUT std_logic;
sync_curr_st : OUT std_logic_vector(3 DOWNTO 0));
END COMPONENT;
-- input interface
SIGNAL rcvd_clk : std_logic;
SIGNAL soft_reset : std_logic;
SIGNAL LP10BEN : std_logic;
SIGNAL RLV_EN : std_logic;
SIGNAL RUNDISP_SEL : std_logic_vector(4 DOWNTO 0);
SIGNAL PMADATAWIDTH : std_logic;
SIGNAL SYNC_COMP_PAT : std_logic_vector(15 DOWNTO 0);
SIGNAL SYNC_COMP_SIZE : std_logic_vector(1 DOWNTO 0);
SIGNAL IB_INVALID_CODE : std_logic_vector(1 DOWNTO 0);
SIGNAL AUTOBYTEALIGN_DIS : std_logic;
SIGNAL SYNC_SM_DIS : std_logic;
SIGNAL GE_XAUI_SEL : std_logic;
SIGNAL encdet_prbs : std_logic;
SIGNAL BITSLIP_xhdl11 : std_logic;
SIGNAL ENCDT : std_logic;
SIGNAL prbs_en : std_logic;
SIGNAL DISABLE_RX_DISP : std_logic;
SIGNAL signal_detect : std_logic;
SIGNAL PUDI : std_logic_vector(9 DOWNTO 0);
SIGNAL PUDR : std_logic_vector(9 DOWNTO 0);
SIGNAL A1A2_SIZE : std_logic;
-- A1A2 and A1A1A2A2 pattern detection
SIGNAL DWIDTH : std_logic;
-- output interface
SIGNAL cg_comma : std_logic;
SIGNAL sync_status : std_logic;
SIGNAL signal_detect_sync : std_logic;
SIGNAL SUDI : std_logic_vector(12 DOWNTO 0);
SIGNAL SUDI_pre : std_logic_vector(9 DOWNTO 0);
SIGNAL RLV : std_logic;
SIGNAL RLV_lt : std_logic;
SIGNAL sync_curr_st : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl13 : std_logic_vector(1 DOWNTO 0);
SIGNAL temp_xhdl14 : std_logic_vector(1 DOWNTO 0);
SIGNAL temp_xhdl15 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl17 : std_logic;
SIGNAL temp_xhdl18 : std_logic_vector(1 DOWNTO 0);
SIGNAL temp_xhdl19 : std_logic_vector(1 DOWNTO 0);
SIGNAL temp_xhdl20 : std_logic_vector(1 DOWNTO 0);
SIGNAL aligneddata_xhdl1 : std_logic_vector(9 DOWNTO 0);
SIGNAL aligneddatapre_xhdl2 : std_logic_vector(9 DOWNTO 0);
SIGNAL invalidcode_xhdl3 : std_logic;
SIGNAL invalidcodepre_xhdl4 : std_logic;
SIGNAL syncstatus_xhdl5 : std_logic;
SIGNAL syncstatusdeskew_xhdl6 : std_logic;
SIGNAL disperr_xhdl7 : std_logic;
SIGNAL disperrpre_xhdl8 : std_logic;
SIGNAL patterndetect_xhdl9 : std_logic;
SIGNAL patterndetectpre_xhdl10 : std_logic;
BEGIN
aligneddata <= aligneddata_xhdl1;
aligneddatapre <= aligneddatapre_xhdl2;
invalidcode <= invalidcode_xhdl3;
invalidcodepre <= invalidcodepre_xhdl4;
syncstatus <= syncstatus_xhdl5;
syncstatusdeskew <= syncstatusdeskew_xhdl6;
disperr <= disperr_xhdl7;
disperrpre <= disperrpre_xhdl8;
patterndetect <= patterndetect_xhdl9;
patterndetectpre <= patterndetectpre_xhdl10;
RLV_EN <= '0' ;
RUNDISP_SEL <= "01000" ;
DWIDTH <= '0' ;
LP10BEN <= '0' ;
DISABLE_RX_DISP <= '0' ;
temp_xhdl12 <= '1' WHEN (align_pattern_length = 16 OR align_pattern_length = 8) ELSE '0';
PMADATAWIDTH <= temp_xhdl12 ;
SYNC_COMP_PAT <= pattern_conversion(align_pattern) ;
temp_xhdl13 <= "01" WHEN (align_pattern_length = 16 OR align_pattern_length = 8) ELSE "10";
temp_xhdl14 <= "00" WHEN (align_pattern_length = 7) ELSE temp_xhdl13;
SYNC_COMP_SIZE <= temp_xhdl14 ;
temp_xhdl15 <= '1' WHEN (synchronization_mode = "none" OR synchronization_mode = "NONE") ELSE '0';
SYNC_SM_DIS <= temp_xhdl15 ;
temp_xhdl16 <= '1' WHEN (synchronization_mode = "gige" OR synchronization_mode = "GIGE") ELSE '0';
GE_XAUI_SEL <= temp_xhdl16 ;
temp_xhdl17 <= '0' WHEN (use_auto_bit_slip = "true" OR use_auto_bit_slip = "ON") ELSE '1';
AUTOBYTEALIGN_DIS <= temp_xhdl17 ;
temp_xhdl18 <= "10" WHEN (infiniband_invalid_code = 2) ELSE "11";
temp_xhdl19 <= "01" WHEN (infiniband_invalid_code = 1) ELSE temp_xhdl18;
temp_xhdl20 <= "00" WHEN (infiniband_invalid_code = 0) ELSE temp_xhdl19;
IB_INVALID_CODE <= temp_xhdl20 ;
prbs_en <= '0' ;
encdet_prbs <= '0' ;
signal_detect <= '1' ;
rcvd_clk <= clk ;
soft_reset <= softreset ;
BITSLIP_xhdl11 <= bitslip ;
ENCDT <= enacdet ;
-- filtering X valus
PUDI(0) <= datain(0) WHEN (datain(0) = '0' OR datain(0) = '1') ELSE '0';
PUDI(1) <= datain(1) WHEN (datain(1) = '0' OR datain(1) = '1') ELSE '0';
PUDI(2) <= datain(2) WHEN (datain(2) = '0' OR datain(2) = '1') ELSE '0';
PUDI(3) <= datain(3) WHEN (datain(3) = '0' OR datain(3) = '1') ELSE '0';
PUDI(4) <= datain(4) WHEN (datain(4) = '0' OR datain(4) = '1') ELSE '0';
PUDI(5) <= datain(5) WHEN (datain(5) = '0' OR datain(5) = '1') ELSE '0';
PUDI(6) <= datain(6) WHEN (datain(6) = '0' OR datain(6) = '1') ELSE '0';
PUDI(7) <= datain(7) WHEN (datain(7) = '0' OR datain(7) = '1') ELSE '0';
PUDI(8) <= datain(8) WHEN (datain(8) = '0' OR datain(8) = '1') ELSE '0';
PUDI(9) <= datain(9) WHEN (datain(9) = '0' OR datain(9) = '1') ELSE '0';
A1A2_SIZE <= a1a2size ;
PUDR <= "XXXXXXXXXX" ;
aligneddata_xhdl1 <= SUDI(9 DOWNTO 0) ;
invalidcode_xhdl3 <= SUDI(10) ;
syncstatus_xhdl5 <= SUDI(11) ;
disperr_xhdl7 <= SUDI(12) ;
syncstatusdeskew_xhdl6 <= sync_status ;
patterndetect_xhdl9 <= cg_comma ;
aligneddatapre_xhdl2 <= SUDI_pre ;
invalidcodepre_xhdl4 <= '0' ;
disperrpre_xhdl8 <= '0' ;
patterndetectpre_xhdl10 <= '0' ;
m_wal_rtl : stratixgx_hssi_rx_wal_rtl
PORT MAP (
rcvd_clk => rcvd_clk,
soft_reset => soft_reset,
LP10BEN => LP10BEN,
RLV_EN => RLV_EN,
RUNDISP_SEL => RUNDISP_SEL,
PMADATAWIDTH => PMADATAWIDTH,
SYNC_COMP_PAT => SYNC_COMP_PAT,
SYNC_COMP_SIZE => SYNC_COMP_SIZE,
IB_INVALID_CODE => IB_INVALID_CODE,
AUTOBYTEALIGN_DIS => AUTOBYTEALIGN_DIS,
BITSLIP => BITSLIP_xhdl11,
DISABLE_RX_DISP => DISABLE_RX_DISP,
ENCDT => ENCDT,
SYNC_SM_DIS => SYNC_SM_DIS,
prbs_en => prbs_en,
encdet_prbs => encdet_prbs,
GE_XAUI_SEL => GE_XAUI_SEL,
signal_detect => signal_detect,
PUDI => PUDI,
PUDR => PUDR,
cg_comma => cg_comma,
sync_status => sync_status,
signal_detect_sync => signal_detect_sync,
SUDI => SUDI,
SUDI_pre => SUDI_pre,
RLV => RLV,
RLV_lt => RLV_lt,
sync_curr_st => sync_curr_st,
A1A2_SIZE => A1A2_SIZE,
DWIDTH => DWIDTH);
END auto_translated;
--
-- STRATIXGX_HSSI_RX_SERDES
--
library IEEE, stratixgx_gxb,std;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
use std.textio.all;
entity stratixgx_hssi_rx_serdes is
generic (
channel_width : integer := 10;
rlv_length : integer := 1;
run_length_enable : String := "false";
cruclk_period : integer :=5000;
cruclk_multiplier : integer :=4;
use_cruclk_divider : String := "false";
use_double_data_mode : string := "false"
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
areset : in std_logic := '0';
feedback : in std_logic := '0';
fbkcntl : in std_logic := '0';
ltr : in std_logic := '0'; -- q3.0ll
ltd : in std_logic := '0'; -- q3.0ll
dataout : out std_logic_vector(9 downto 0);
clkout : out std_logic;
rlv : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
signaldetect: out std_logic
);
end stratixgx_hssi_rx_serdes;
architecture vital_rx_serdes_atom of stratixgx_hssi_rx_serdes is
constant channel_width_max : integer := 10;
constant init_lock_latency : integer := 9; -- q3.0ll
signal ltr_ipd : std_logic;
signal ltd_ipd : std_logic;
signal lock_tmp : std_logic;
signal freqlock_tmp : std_logic;
signal freqlock_tmp_dly : std_logic;
signal freqlock_tmp_dly1 : std_logic;
signal freqlock_tmp_dly2 : std_logic;
signal freqlock_tmp_dly3 : std_logic;
signal freqlock_tmp_dly4 : std_logic;
signal databuf_ipd : std_logic;
signal cruclk_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal fbena_ipd : std_logic;
-- add 2 deltas to balance new fastclk_gen - always read prev data
-- The 1st fastclk has: in_delta + 1(ipd) + 1 (fastclk <= after 0)
-- remaining fastclk has 0 delta
-- in summary: fastclk_delta = x(from top) + 1(ipd) + 1 or 0 (no delta)
-- data = x(from top) + 1(ipd) + 2 (new)
signal databuf_tmp1, databuf_tmp2 : std_logic;
signal areset_tmp1, areset_tmp2 : std_logic;
signal fbin_tmp1, fbin_tmp2 : std_logic;
signal fbena_tmp1, fbena_tmp2 : std_logic;
signal ltr_tmp1, ltr_tmp2 : std_logic;
signal ltd_tmp1, ltd_tmp2 : std_logic;
-- clock gen
signal fastclk : std_logic;
signal cruclk_ipd_last_value : std_logic := 'X';
signal rlv_flag : std_logic := '0';
signal rlv_flag_tmp : std_logic := '0';
signal rlv_set : std_logic := '0';
signal clkout_int : std_logic := '0';
signal deser_data_arr : std_logic_vector(channel_width_max-1 downto 0);
signal deser_data_arr_int : std_logic_vector(channel_width_max-1 downto 0);
signal deser_data_arr_tmp : std_logic_vector(channel_width_max-1 downto 0);
signal min_length : integer := 0;
signal rlv_tmp1 : std_logic := '0';
signal rlv_tmp2 : std_logic := '0';
signal rlv_tmp3 : std_logic := '0';
signal dataout_tmp : std_logic_vector(channel_width_max-1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
-- for now assuming all delays on top level
WireDelay : block
begin
cruclk_ipd <= cruclk;
databuf_tmp1 <= datain;
fbin_tmp1 <= feedback;
fbena_tmp1 <= fbkcntl;
areset_tmp1 <= areset;
ltr_tmp1 <= ltr;
ltd_tmp1 <= ltd;
databuf_tmp2 <= databuf_tmp1;
fbin_tmp2 <= fbin_tmp1;
fbena_tmp2 <= fbena_tmp1;
areset_tmp2 <= areset_tmp1;
ltr_tmp2 <= ltr_tmp1;
ltd_tmp2 <= ltd_tmp1;
databuf_ipd <= databuf_tmp2;
fbin_ipd <= fbin_tmp2;
fbena_ipd <= fbena_tmp2;
areset_ipd <= areset_tmp2;
ltr_ipd <= ltr_tmp2;
ltd_ipd <= ltd_tmp2;
end block;
min_length <= 4 WHEN (channel_width = 8) ELSE 5;
process (cruclk_ipd)
variable init : boolean := true;
variable n_fastclk : integer := 5;
variable fastclk_period : integer := 320;
variable cru_rem : integer := 0;
variable my_rem : integer := 0;
variable tmp_fastclk_period : integer := 320;
variable cycle_to_adjust : integer := 0;
variable k : integer := 1;
variable high_time : integer := 160;
variable low_time : integer := 160;
variable sched_time : time := 0 ps;
variable sched_val : std_logic := '0';
begin
if (init) then
if (use_cruclk_divider = "false") then
n_fastclk := cruclk_multiplier;
else
n_fastclk := cruclk_multiplier / 2;
end if;
fastclk_period := cruclk_period / n_fastclk;
cru_rem := cruclk_period rem n_fastclk;
init := false;
end if;
if ((cruclk_ipd = '1') and (cruclk_ipd_last_value = '0')) then
-- schedule n_fastclk of clk with period fastclk_period
sched_time := 0 ps;
sched_val := '1'; -- start with rising to match cruclk
k := 1; -- used to distribute rem ps to n_fastclk internals
for i in 1 to n_fastclk loop
fastclk <= transport sched_val after sched_time; -- rising
-- wether it needs to add extra ps to the period
tmp_fastclk_period := fastclk_period;
if (cru_rem /= 0 and k <= cru_rem) then
cycle_to_adjust := (n_fastclk * k) / cru_rem;
my_rem := (n_fastclk * k) rem cru_rem;
if (my_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
if (cycle_to_adjust = i) then
tmp_fastclk_period := tmp_fastclk_period + 1;
k := k + 1;
end if;
end if;
high_time := tmp_fastclk_period / 2;
low_time := tmp_fastclk_period - high_time;
sched_val := not sched_val;
sched_time := sched_time + (high_time * 1 ps);
fastclk <= transport sched_val after sched_time; -- falling
sched_time := sched_time + (low_time * 1 ps);
sched_val := not sched_val;
end loop;
end if; -- rising cruclk
cruclk_ipd_last_value <= cruclk_ipd;
end process;
process (fastclk, areset_ipd, fbena_ipd)
variable clk_count : integer := channel_width; --follow the 1st edge
variable signaldetect_tmp : std_logic := '0';
variable clkout_last_value : std_logic;
variable clkout_tmp : std_logic;
variable datain_ipd : std_logic;
variable last_datain : std_logic;
variable rlv_count : integer := 0;
variable data_changed : std_logic := '0';
begin
if (now = 0 ns) then
data_changed := '0';
clk_count := channel_width;
clkout_tmp := '0';
signaldetect_tmp := '1';
for i in channel_width_max-1 downto 0 loop
deser_data_arr(i) <= '0';
deser_data_arr_int(i) <= '0';
end loop;
last_datain := 'X';
end if;
------------------------
-- Timing Check Section
------------------------
-- for now assuming all delays on top level module
if (areset_ipd = '1') then
clkout_tmp := '0';
clkout_last_value := fastclk;
clk_count := channel_width;
signaldetect_tmp := '1';
for i in channel_width_max-1 downto 0 loop
deser_data_arr(i) <= '0';
deser_data_arr_int(i) <= '0';
end loop;
rlv_count := 0;
rlv_flag <= '0';
rlv_set <= '0';
last_datain := 'X';
data_changed := '0';
else
if (fbena_ipd = '1') then
datain_ipd := fbin_ipd;
else
datain_ipd := databuf_ipd;
end if;
if (fastclk'event and fastclk /= 'X' and fastclk /= 'U') then
if (clkout_last_value = 'U') then
clkout_last_value := fastclk;
clkout_tmp := fastclk;
elsif (clk_count = channel_width) then
clkout_tmp := NOT (clkout_last_value);
elsif (clk_count = channel_width/2) then
clkout_tmp := NOT (clkout_last_value);
elsif (clk_count < channel_width) then
clkout_tmp := clkout_last_value;
end if;
if (clk_count = channel_width) then
clk_count := 0;
end if;
clk_count := clk_count + 1;
if (run_length_enable = "true") then
if (last_datain /= datain_ipd) then
data_changed := '1';
last_datain := datain_ipd;
rlv_count := 1;
rlv_set <= '0';
else
rlv_count := rlv_count + 1;
data_changed := '0';
end if;
if (rlv_count > rlv_length AND rlv_count > min_length) then
rlv_set <= '1';
rlv_flag <= '1';
else
rlv_flag <= rlv_flag_tmp;
end if;
end if;
end if;
if (fastclk'event and fastclk /= 'X'and fastclk /= 'U') then
for i in 1 to channel_width_max-1 loop
deser_data_arr(i - 1) <= deser_data_arr(i);
end loop;
deser_data_arr(channel_width_max - 1) <= datain_ipd;
deser_data_arr_int <= deser_data_arr;
end if;
if (clkout_tmp /= 'U') then
clkout_last_value := clkout_tmp;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
-- for now assuming all delays on top level module
clkout_int <= clkout_tmp;
signaldetect <= signaldetect_tmp;
end process;
process (clkout_int, areset_ipd)
begin
if (now = 0 ns) then
dataout_tmp <= (OTHERS => '0');
for i in channel_width_max-1 downto 0 loop
deser_data_arr_tmp(i) <= '0';
end loop;
rlv_tmp1 <= '0';
rlv_tmp2 <= '0';
rlv_tmp3 <= '0';
rlv_flag_tmp <= '0';
end if;
if (areset_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
for i in channel_width_max-1 downto 0 loop
deser_data_arr_tmp(i) <= '0';
end loop;
rlv_tmp1 <= '0';
rlv_tmp2 <= '0';
rlv_tmp3 <= '0';
elsif (clkout_int'event and clkout_int = '1') then
deser_data_arr_tmp <= deser_data_arr_int;
dataout_tmp(channel_width_max-1 downto 0) <= deser_data_arr_tmp;
if (run_length_enable = "true") then
rlv_tmp2 <= rlv_tmp1;
rlv_tmp3 <= rlv_tmp2;
if (rlv_flag = '1') then
if (rlv_set = '0') then
rlv_flag_tmp <= '0';
rlv_tmp1 <= '0';
else
rlv_tmp1 <= '1';
rlv_flag_tmp <= '1';
end if;
else
rlv_tmp1 <= '0';
rlv_flag_tmp <= '0';
end if;
end if;
end if;
end process;
-- q3.0ll lock and freqlock based on LTR and LTD
process (cruclk_ipd, areset_ipd)
variable cruclk_cnt : integer := 0;
begin
if (now = 0 ns) then
cruclk_cnt := 0;
lock_tmp <= '1';
freqlock_tmp <= '0';
freqlock_tmp_dly <= '0';
freqlock_tmp_dly1 <= '0';
freqlock_tmp_dly2 <= '0';
freqlock_tmp_dly3 <= '0';
freqlock_tmp_dly4 <= '0';
end if;
if (areset_ipd = '1') then
cruclk_cnt := 0;
lock_tmp <= '1';
freqlock_tmp <= '0';
freqlock_tmp_dly <= '0';
freqlock_tmp_dly1 <= '0';
freqlock_tmp_dly2 <= '0';
freqlock_tmp_dly3 <= '0';
freqlock_tmp_dly4 <= '0';
elsif (cruclk_ipd'event and cruclk_ipd = '1' and cruclk_ipd_last_value = '0') then
freqlock_tmp_dly <= freqlock_tmp_dly4;
freqlock_tmp_dly4 <= freqlock_tmp_dly3;
freqlock_tmp_dly3 <= freqlock_tmp_dly2;
freqlock_tmp_dly2 <= freqlock_tmp_dly1;
freqlock_tmp_dly1 <= freqlock_tmp;
if (cruclk_cnt = init_lock_latency) then
if (ltd_ipd = '1') then
freqlock_tmp <= '1';
elsif (ltr_ipd = '1') then
lock_tmp <= '0';
freqlock_tmp <= '0';
else -- auto switch
lock_tmp <= '0';
freqlock_tmp <= '1';
end if;
end if;
-- initial latency
if (cruclk_cnt < init_lock_latency) then
cruclk_cnt := cruclk_cnt + 1;
end if;
end if;
end process;
rlv <= '0' WHEN (run_length_enable = "false") ELSE (rlv_tmp1 OR rlv_tmp2) WHEN (use_double_data_mode = "false") ELSE (rlv_tmp1 OR rlv_tmp2 OR rlv_tmp3);
lock <= lock_tmp;
freqlock <= freqlock_tmp_dly;
clkout <= clkout_int;
dataout <= dataout_tmp;
end vital_rx_serdes_atom;
--
-- stratixgx_hssi_tx_serdes
--
library IEEE, stratixgx_gxb;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
entity stratixgx_hssi_tx_serdes is
generic (
channel_width : integer := 10
);
port (
clk : in std_logic := '0';
clk1 : in std_logic := '0';
datain : in std_logic_vector(9 downto 0) := "0000000000";
serialdatain : in std_logic := '0';
srlpbk : in std_logic := '0';
areset : in std_logic := '0';
dataout : out std_logic
);
end stratixgx_hssi_tx_serdes;
architecture vital_tx_serdes_atom of stratixgx_hssi_tx_serdes is
constant shift_edge : integer := channel_width / 2;
signal indata : std_logic_vector(channel_width-1 downto 0);
signal regdata : std_logic_vector(9 downto 0);
signal clk_dly : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
-- for now assuming all timing done at top level
VITAL_clk0_dly: process (clk)
begin
clk_dly <= clk;
end process;
VITAL_clk0: process (clk_dly, clk1, areset)
variable i : integer := 0;
variable dataout_tmp : std_logic;
variable pclk_count : integer := 0;
variable shiftdata : std_logic_vector(9 downto 0);
begin
if (now = 0 ns) then
dataout_tmp := '0';
for i in 9 downto 0 loop --reset register
regdata(i) <= '0';
shiftdata(i) := '0';
end loop;
end if;
------------------------
-- Timing Check Section
------------------------
-- for now assuming all timing done at top level
if (areset = '1') then
dataout_tmp := 'Z';
for i in 9 downto 0 loop --reset register
regdata(i) <= 'Z';
shiftdata(i) := 'Z';
end loop;
else
if (clk_dly'event and clk_dly = '1') then
pclk_count := pclk_count + 1;
if (pclk_count = shift_edge) then
shiftdata := regdata;
end if;
end if;
if (clk_dly'event) then
-- loading parallel data
if (pclk_count = 1) then
for i in 9 downto 0 loop
regdata(i) <= datain(9 - i);
end loop;
end if;
if (srlpbk = '1') then
dataout_tmp := serialdatain;
else
dataout_tmp := shiftdata(9);
end if;
for i in 9 downto (10 - channel_width + 1) loop
shiftdata(i) := shiftdata(i-1);
end loop;
end if;
if (clk1'event and clk1 = '1') then -- rising edge
pclk_count := 0;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
-- for now assuming all delays on top level module
dataout <= dataout_tmp;
end process;
end vital_tx_serdes_atom;
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
--synthesis_resources = lut 123 mux21 348
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_xgm_rx_sm IS
PORT
(
resetall : IN STD_LOGIC;
rxclk : IN STD_LOGIC;
rxctrl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rxdatain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rxdatavalid : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rxrunningdisp : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END stratixgx_xgm_rx_sm;
ARCHITECTURE RTL OF stratixgx_xgm_rx_sm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL nl000l45 : STD_LOGIC := '0';
SIGNAL nl000l46 : STD_LOGIC := '0';
SIGNAL nl00iO43 : STD_LOGIC := '0';
SIGNAL nl00iO44 : STD_LOGIC := '0';
SIGNAL nl00OO41 : STD_LOGIC := '0';
SIGNAL nl00OO42 : STD_LOGIC := '0';
SIGNAL nl0i0O37 : STD_LOGIC := '0';
SIGNAL nl0i0O38 : STD_LOGIC := '0';
SIGNAL nl0i1l39 : STD_LOGIC := '0';
SIGNAL nl0i1l40 : STD_LOGIC := '0';
SIGNAL wire_nl0i1l40_w_lg_q180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl0iil35 : STD_LOGIC := '0';
SIGNAL nl0iil36 : STD_LOGIC := '0';
SIGNAL nl0ill33 : STD_LOGIC := '0';
SIGNAL nl0ill34 : STD_LOGIC := '0';
SIGNAL nl0iOO31 : STD_LOGIC := '0';
SIGNAL nl0iOO32 : STD_LOGIC := '0';
SIGNAL nl0l0l27 : STD_LOGIC := '0';
SIGNAL nl0l0l28 : STD_LOGIC := '0';
SIGNAL nl0l1O29 : STD_LOGIC := '0';
SIGNAL nl0l1O30 : STD_LOGIC := '0';
SIGNAL nl0lil25 : STD_LOGIC := '0';
SIGNAL nl0lil26 : STD_LOGIC := '0';
SIGNAL nl0lll23 : STD_LOGIC := '0';
SIGNAL nl0lll24 : STD_LOGIC := '0';
SIGNAL nl0llO21 : STD_LOGIC := '0';
SIGNAL nl0llO22 : STD_LOGIC := '0';
SIGNAL nl0O0O17 : STD_LOGIC := '0';
SIGNAL nl0O0O18 : STD_LOGIC := '0';
SIGNAL nl0O1l19 : STD_LOGIC := '0';
SIGNAL nl0O1l20 : STD_LOGIC := '0';
SIGNAL nl0Oli15 : STD_LOGIC := '0';
SIGNAL nl0Oli16 : STD_LOGIC := '0';
SIGNAL nl0OOO13 : STD_LOGIC := '0';
SIGNAL nl0OOO14 : STD_LOGIC := '0';
SIGNAL nli00O3 : STD_LOGIC := '0';
SIGNAL nli00O4 : STD_LOGIC := '0';
SIGNAL nli0lO1 : STD_LOGIC := '0';
SIGNAL nli0lO2 : STD_LOGIC := '0';
SIGNAL nli10l10 : STD_LOGIC := '0';
SIGNAL nli10l9 : STD_LOGIC := '0';
SIGNAL nli11O11 : STD_LOGIC := '0';
SIGNAL nli11O12 : STD_LOGIC := '0';
SIGNAL nli1ii7 : STD_LOGIC := '0';
SIGNAL nli1ii8 : STD_LOGIC := '0';
SIGNAL nli1OO5 : STD_LOGIC := '0';
SIGNAL nli1OO6 : STD_LOGIC := '0';
SIGNAL n11iO : STD_LOGIC := '0';
SIGNAL n1O1i : STD_LOGIC := '0';
SIGNAL n1O1l : STD_LOGIC := '0';
SIGNAL n1O1O : STD_LOGIC := '0';
SIGNAL n1Oii : STD_LOGIC := '0';
SIGNAL nlllli : STD_LOGIC := '0';
SIGNAL wire_n1O0O_PRN : STD_LOGIC;
SIGNAL n00ll : STD_LOGIC := '0';
SIGNAL n00lO : STD_LOGIC := '0';
SIGNAL n00Oi : STD_LOGIC := '0';
SIGNAL n00Ol : STD_LOGIC := '0';
SIGNAL n00OO : STD_LOGIC := '0';
SIGNAL n0i1i : STD_LOGIC := '0';
SIGNAL n0i1l : STD_LOGIC := '0';
SIGNAL n0i1O : STD_LOGIC := '0';
SIGNAL n110i : STD_LOGIC := '0';
SIGNAL n110l : STD_LOGIC := '0';
SIGNAL n110O : STD_LOGIC := '0';
SIGNAL n111i : STD_LOGIC := '0';
SIGNAL n111l : STD_LOGIC := '0';
SIGNAL n111O : STD_LOGIC := '0';
SIGNAL n11ii : STD_LOGIC := '0';
SIGNAL n11il : STD_LOGIC := '0';
SIGNAL n1lOl : STD_LOGIC := '0';
SIGNAL n1lOO : STD_LOGIC := '0';
SIGNAL n1O0i : STD_LOGIC := '0';
SIGNAL n1O0l : STD_LOGIC := '0';
SIGNAL n1Oil : STD_LOGIC := '0';
SIGNAL ni00i : STD_LOGIC := '0';
SIGNAL ni00l : STD_LOGIC := '0';
SIGNAL ni00O : STD_LOGIC := '0';
SIGNAL ni01i : STD_LOGIC := '0';
SIGNAL ni01l : STD_LOGIC := '0';
SIGNAL ni01O : STD_LOGIC := '0';
SIGNAL ni0ii : STD_LOGIC := '0';
SIGNAL ni1Ol : STD_LOGIC := '0';
SIGNAL ni1OO : STD_LOGIC := '0';
SIGNAL niii : STD_LOGIC := '0';
SIGNAL niil : STD_LOGIC := '0';
SIGNAL niiO : STD_LOGIC := '0';
SIGNAL niOl : STD_LOGIC := '0';
SIGNAL nl10i : STD_LOGIC := '0';
SIGNAL nl10l : STD_LOGIC := '0';
SIGNAL nl10O : STD_LOGIC := '0';
SIGNAL nl11O : STD_LOGIC := '0';
SIGNAL nl1ii : STD_LOGIC := '0';
SIGNAL nl1il : STD_LOGIC := '0';
SIGNAL nl1iO : STD_LOGIC := '0';
SIGNAL nl1li : STD_LOGIC := '0';
SIGNAL nlllll : STD_LOGIC := '0';
SIGNAL nllllO : STD_LOGIC := '0';
SIGNAL nlllOi : STD_LOGIC := '0';
SIGNAL nlllOl : STD_LOGIC := '0';
SIGNAL nlllOO : STD_LOGIC := '0';
SIGNAL nllO1i : STD_LOGIC := '0';
SIGNAL nllO1l : STD_LOGIC := '0';
SIGNAL nllO1O : STD_LOGIC := '0';
SIGNAL nlO00i : STD_LOGIC := '0';
SIGNAL nlO00l : STD_LOGIC := '0';
SIGNAL nlO00O : STD_LOGIC := '0';
SIGNAL nlO0ii : STD_LOGIC := '0';
SIGNAL nlO0il : STD_LOGIC := '0';
SIGNAL nlO0iO : STD_LOGIC := '0';
SIGNAL nlO0li : STD_LOGIC := '0';
SIGNAL nlO0ll : STD_LOGIC := '0';
SIGNAL nlO0lO : STD_LOGIC := '0';
SIGNAL nlOii : STD_LOGIC := '0';
SIGNAL nlOil : STD_LOGIC := '0';
SIGNAL nlOlO : STD_LOGIC := '0';
SIGNAL nlOOi : STD_LOGIC := '0';
SIGNAL nlOOO : STD_LOGIC := '0';
SIGNAL n00li : STD_LOGIC := '0';
SIGNAL nl1i : STD_LOGIC := '0';
SIGNAL nl1ll : STD_LOGIC := '0';
SIGNAL nlOiO : STD_LOGIC := '0';
SIGNAL nlOli : STD_LOGIC := '0';
SIGNAL nlOll : STD_LOGIC := '0';
SIGNAL nlOOl : STD_LOGIC := '0';
SIGNAL wire_niOO_CLRN : STD_LOGIC;
SIGNAL wire_niOO_PRN : STD_LOGIC;
SIGNAL wire_n000i_dataout : STD_LOGIC;
SIGNAL wire_n000l_dataout : STD_LOGIC;
SIGNAL wire_n001i_dataout : STD_LOGIC;
SIGNAL wire_n001l_dataout : STD_LOGIC;
SIGNAL wire_n001O_dataout : STD_LOGIC;
SIGNAL wire_n00i_dataout : STD_LOGIC;
SIGNAL wire_n00l_dataout : STD_LOGIC;
SIGNAL wire_n00O_dataout : STD_LOGIC;
SIGNAL wire_n010i_dataout : STD_LOGIC;
SIGNAL wire_n010l_dataout : STD_LOGIC;
SIGNAL wire_n010O_dataout : STD_LOGIC;
SIGNAL wire_n011i_dataout : STD_LOGIC;
SIGNAL wire_n011l_dataout : STD_LOGIC;
SIGNAL wire_n011O_dataout : STD_LOGIC;
SIGNAL wire_n01i_dataout : STD_LOGIC;
SIGNAL wire_n01ii_dataout : STD_LOGIC;
SIGNAL wire_n01il_dataout : STD_LOGIC;
SIGNAL wire_n01iO_dataout : STD_LOGIC;
SIGNAL wire_n01l_dataout : STD_LOGIC;
SIGNAL wire_n01li_dataout : STD_LOGIC;
SIGNAL wire_n01ll_dataout : STD_LOGIC;
SIGNAL wire_n01lO_dataout : STD_LOGIC;
SIGNAL wire_n01O_dataout : STD_LOGIC;
SIGNAL wire_n01Oi_dataout : STD_LOGIC;
SIGNAL wire_n01Ol_dataout : STD_LOGIC;
SIGNAL wire_n01OO_dataout : STD_LOGIC;
SIGNAL wire_n0i0i_dataout : STD_LOGIC;
SIGNAL wire_n0i0l_dataout : STD_LOGIC;
SIGNAL wire_n0i0O_dataout : STD_LOGIC;
SIGNAL wire_n0ii_dataout : STD_LOGIC;
SIGNAL wire_n0iii_dataout : STD_LOGIC;
SIGNAL wire_n0iil_dataout : STD_LOGIC;
SIGNAL wire_n0iiO_dataout : STD_LOGIC;
SIGNAL wire_n0il_dataout : STD_LOGIC;
SIGNAL wire_n0ili_dataout : STD_LOGIC;
SIGNAL wire_n0ill_dataout : STD_LOGIC;
SIGNAL wire_n0ilO_dataout : STD_LOGIC;
SIGNAL wire_n0iO_dataout : STD_LOGIC;
SIGNAL wire_n0iOi_dataout : STD_LOGIC;
SIGNAL wire_n0iOl_dataout : STD_LOGIC;
SIGNAL wire_n0iOO_dataout : STD_LOGIC;
SIGNAL wire_n0l0i_dataout : STD_LOGIC;
SIGNAL wire_n0l0l_dataout : STD_LOGIC;
SIGNAL wire_n0l0O_dataout : STD_LOGIC;
SIGNAL wire_n0l1i_dataout : STD_LOGIC;
SIGNAL wire_n0l1l_dataout : STD_LOGIC;
SIGNAL wire_n0l1O_dataout : STD_LOGIC;
SIGNAL wire_n0li_dataout : STD_LOGIC;
SIGNAL wire_n0lii_dataout : STD_LOGIC;
SIGNAL wire_n0lil_dataout : STD_LOGIC;
SIGNAL wire_n0liO_dataout : STD_LOGIC;
SIGNAL wire_n0ll_dataout : STD_LOGIC;
SIGNAL wire_n0lli_dataout : STD_LOGIC;
SIGNAL wire_n0lll_dataout : STD_LOGIC;
SIGNAL wire_n0llO_dataout : STD_LOGIC;
SIGNAL wire_n0lO_dataout : STD_LOGIC;
SIGNAL wire_n0lOi_dataout : STD_LOGIC;
SIGNAL wire_n0lOl_dataout : STD_LOGIC;
SIGNAL wire_n0lOO_dataout : STD_LOGIC;
SIGNAL wire_n0O0i_dataout : STD_LOGIC;
SIGNAL wire_n0O0l_dataout : STD_LOGIC;
SIGNAL wire_n0O0O_dataout : STD_LOGIC;
SIGNAL wire_n0O1i_dataout : STD_LOGIC;
SIGNAL wire_n0O1l_dataout : STD_LOGIC;
SIGNAL wire_n0O1O_dataout : STD_LOGIC;
SIGNAL wire_n0Oi_dataout : STD_LOGIC;
SIGNAL wire_n0Oii_dataout : STD_LOGIC;
SIGNAL wire_n0Oil_dataout : STD_LOGIC;
SIGNAL wire_n0OiO_dataout : STD_LOGIC;
SIGNAL wire_n0Ol_dataout : STD_LOGIC;
SIGNAL wire_n0Oli_dataout : STD_LOGIC;
SIGNAL wire_n0Oll_dataout : STD_LOGIC;
SIGNAL wire_n0OlO_dataout : STD_LOGIC;
SIGNAL wire_n0OO_dataout : STD_LOGIC;
SIGNAL wire_n0OOi_dataout : STD_LOGIC;
SIGNAL wire_n0OOl_dataout : STD_LOGIC;
SIGNAL wire_n0OOO_dataout : STD_LOGIC;
SIGNAL wire_n100i_dataout : STD_LOGIC;
SIGNAL wire_n100l_dataout : STD_LOGIC;
SIGNAL wire_n100O_dataout : STD_LOGIC;
SIGNAL wire_n101i_dataout : STD_LOGIC;
SIGNAL wire_n101l_dataout : STD_LOGIC;
SIGNAL wire_n101O_dataout : STD_LOGIC;
SIGNAL wire_n10i_dataout : STD_LOGIC;
SIGNAL wire_n10ii_dataout : STD_LOGIC;
SIGNAL wire_n10il_dataout : STD_LOGIC;
SIGNAL wire_n10iO_dataout : STD_LOGIC;
SIGNAL wire_n10l_dataout : STD_LOGIC;
SIGNAL wire_n10li_dataout : STD_LOGIC;
SIGNAL wire_n10ll_dataout : STD_LOGIC;
SIGNAL wire_n10lO_dataout : STD_LOGIC;
SIGNAL wire_n10O_dataout : STD_LOGIC;
SIGNAL wire_n10Oi_dataout : STD_LOGIC;
SIGNAL wire_n10Ol_dataout : STD_LOGIC;
SIGNAL wire_n10OO_dataout : STD_LOGIC;
SIGNAL wire_n11i_dataout : STD_LOGIC;
SIGNAL wire_n11l_dataout : STD_LOGIC;
SIGNAL wire_n11li_dataout : STD_LOGIC;
SIGNAL wire_n11ll_dataout : STD_LOGIC;
SIGNAL wire_n11lO_dataout : STD_LOGIC;
SIGNAL wire_n11O_dataout : STD_LOGIC;
SIGNAL wire_n11Oi_dataout : STD_LOGIC;
SIGNAL wire_n11Ol_dataout : STD_LOGIC;
SIGNAL wire_n11OO_dataout : STD_LOGIC;
SIGNAL wire_n1i0i_dataout : STD_LOGIC;
SIGNAL wire_n1i0l_dataout : STD_LOGIC;
SIGNAL wire_n1i0O_dataout : STD_LOGIC;
SIGNAL wire_n1i1i_dataout : STD_LOGIC;
SIGNAL wire_n1i1l_dataout : STD_LOGIC;
SIGNAL wire_n1i1O_dataout : STD_LOGIC;
SIGNAL wire_n1ii_dataout : STD_LOGIC;
SIGNAL wire_n1iii_dataout : STD_LOGIC;
SIGNAL wire_n1iil_dataout : STD_LOGIC;
SIGNAL wire_n1iiO_dataout : STD_LOGIC;
SIGNAL wire_n1il_dataout : STD_LOGIC;
SIGNAL wire_n1ili_dataout : STD_LOGIC;
SIGNAL wire_n1ill_dataout : STD_LOGIC;
SIGNAL wire_n1ilO_dataout : STD_LOGIC;
SIGNAL wire_n1iO_dataout : STD_LOGIC;
SIGNAL wire_n1iOi_dataout : STD_LOGIC;
SIGNAL wire_n1iOl_dataout : STD_LOGIC;
SIGNAL wire_n1iOO_dataout : STD_LOGIC;
SIGNAL wire_n1l0i_dataout : STD_LOGIC;
SIGNAL wire_n1l0l_dataout : STD_LOGIC;
SIGNAL wire_n1l0O_dataout : STD_LOGIC;
SIGNAL wire_n1li_dataout : STD_LOGIC;
SIGNAL wire_n1lii_dataout : STD_LOGIC;
SIGNAL wire_n1lil_dataout : STD_LOGIC;
SIGNAL wire_n1liO_dataout : STD_LOGIC;
SIGNAL wire_n1ll_dataout : STD_LOGIC;
SIGNAL wire_n1lli_dataout : STD_LOGIC;
SIGNAL wire_n1lll_dataout : STD_LOGIC;
SIGNAL wire_n1llO_dataout : STD_LOGIC;
SIGNAL wire_n1lO_dataout : STD_LOGIC;
SIGNAL wire_n1Oi_dataout : STD_LOGIC;
SIGNAL wire_n1OiO_dataout : STD_LOGIC;
SIGNAL wire_n1Ol_dataout : STD_LOGIC;
SIGNAL wire_n1Oli_dataout : STD_LOGIC;
SIGNAL wire_n1Oll_dataout : STD_LOGIC;
SIGNAL wire_n1OlO_dataout : STD_LOGIC;
SIGNAL wire_n1OO_dataout : STD_LOGIC;
SIGNAL wire_n1OOi_dataout : STD_LOGIC;
SIGNAL wire_n1OOl_dataout : STD_LOGIC;
SIGNAL wire_n1OOO_dataout : STD_LOGIC;
SIGNAL wire_ni0i_dataout : STD_LOGIC;
SIGNAL wire_ni0il_dataout : STD_LOGIC;
SIGNAL wire_ni0iO_dataout : STD_LOGIC;
SIGNAL wire_ni0l_dataout : STD_LOGIC;
SIGNAL wire_ni0li_dataout : STD_LOGIC;
SIGNAL wire_ni0ll_dataout : STD_LOGIC;
SIGNAL wire_ni0lO_dataout : STD_LOGIC;
SIGNAL wire_ni0O_dataout : STD_LOGIC;
SIGNAL wire_ni0Oi_dataout : STD_LOGIC;
SIGNAL wire_ni0Ol_dataout : STD_LOGIC;
SIGNAL wire_ni0OO_dataout : STD_LOGIC;
SIGNAL wire_ni10i_dataout : STD_LOGIC;
SIGNAL wire_ni10l_dataout : STD_LOGIC;
SIGNAL wire_ni10O_dataout : STD_LOGIC;
SIGNAL wire_ni11i_dataout : STD_LOGIC;
SIGNAL wire_ni11l_dataout : STD_LOGIC;
SIGNAL wire_ni11O_dataout : STD_LOGIC;
SIGNAL wire_ni1i_dataout : STD_LOGIC;
SIGNAL wire_ni1ii_dataout : STD_LOGIC;
SIGNAL wire_ni1il_dataout : STD_LOGIC;
SIGNAL wire_ni1iO_dataout : STD_LOGIC;
SIGNAL wire_ni1l_dataout : STD_LOGIC;
SIGNAL wire_ni1li_dataout : STD_LOGIC;
SIGNAL wire_ni1ll_dataout : STD_LOGIC;
SIGNAL wire_ni1lO_dataout : STD_LOGIC;
SIGNAL wire_ni1O_dataout : STD_LOGIC;
SIGNAL wire_nii0i_dataout : STD_LOGIC;
SIGNAL wire_nii0l_dataout : STD_LOGIC;
SIGNAL wire_nii0O_dataout : STD_LOGIC;
SIGNAL wire_nii1i_dataout : STD_LOGIC;
SIGNAL wire_nii1l_dataout : STD_LOGIC;
SIGNAL wire_nii1O_dataout : STD_LOGIC;
SIGNAL wire_niiii_dataout : STD_LOGIC;
SIGNAL wire_niiil_dataout : STD_LOGIC;
SIGNAL wire_niiiO_dataout : STD_LOGIC;
SIGNAL wire_niili_dataout : STD_LOGIC;
SIGNAL wire_niill_dataout : STD_LOGIC;
SIGNAL wire_niilO_dataout : STD_LOGIC;
SIGNAL wire_niiOi_dataout : STD_LOGIC;
SIGNAL wire_niiOl_dataout : STD_LOGIC;
SIGNAL wire_niiOO_dataout : STD_LOGIC;
SIGNAL wire_nil0i_dataout : STD_LOGIC;
SIGNAL wire_nil0l_dataout : STD_LOGIC;
SIGNAL wire_nil0O_dataout : STD_LOGIC;
SIGNAL wire_nil1i_dataout : STD_LOGIC;
SIGNAL wire_nil1l_dataout : STD_LOGIC;
SIGNAL wire_nil1O_dataout : STD_LOGIC;
SIGNAL wire_nili_dataout : STD_LOGIC;
SIGNAL wire_nilii_dataout : STD_LOGIC;
SIGNAL wire_nilil_dataout : STD_LOGIC;
SIGNAL wire_niliO_dataout : STD_LOGIC;
SIGNAL wire_nill_dataout : STD_LOGIC;
SIGNAL wire_nilli_dataout : STD_LOGIC;
SIGNAL wire_nilll_dataout : STD_LOGIC;
SIGNAL wire_nillO_dataout : STD_LOGIC;
SIGNAL wire_nilOi_dataout : STD_LOGIC;
SIGNAL wire_nilOl_dataout : STD_LOGIC;
SIGNAL wire_nilOO_dataout : STD_LOGIC;
SIGNAL wire_niO0i_dataout : STD_LOGIC;
SIGNAL wire_niO0l_dataout : STD_LOGIC;
SIGNAL wire_niO0O_dataout : STD_LOGIC;
SIGNAL wire_niO1i_dataout : STD_LOGIC;
SIGNAL wire_niO1l_dataout : STD_LOGIC;
SIGNAL wire_niO1O_dataout : STD_LOGIC;
SIGNAL wire_niOii_dataout : STD_LOGIC;
SIGNAL wire_niOil_dataout : STD_LOGIC;
SIGNAL wire_niOiO_dataout : STD_LOGIC;
SIGNAL wire_niOli_dataout : STD_LOGIC;
SIGNAL wire_niOll_dataout : STD_LOGIC;
SIGNAL wire_niOlO_dataout : STD_LOGIC;
SIGNAL wire_niOOi_dataout : STD_LOGIC;
SIGNAL wire_niOOl_dataout : STD_LOGIC;
SIGNAL wire_niOOO_dataout : STD_LOGIC;
SIGNAL wire_nl00i_dataout : STD_LOGIC;
SIGNAL wire_nl00l_dataout : STD_LOGIC;
SIGNAL wire_nl00O_dataout : STD_LOGIC;
SIGNAL wire_nl01i_dataout : STD_LOGIC;
SIGNAL wire_nl01l_dataout : STD_LOGIC;
SIGNAL wire_nl01O_dataout : STD_LOGIC;
SIGNAL wire_nl0i_dataout : STD_LOGIC;
SIGNAL wire_nl0i_w_lg_dataout92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl0ii_dataout : STD_LOGIC;
SIGNAL wire_nl0il_dataout : STD_LOGIC;
SIGNAL wire_nl0iO_dataout : STD_LOGIC;
SIGNAL wire_nl0l_dataout : STD_LOGIC;
SIGNAL wire_nl0l_w_lg_dataout123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl0li_dataout : STD_LOGIC;
SIGNAL wire_nl0ll_dataout : STD_LOGIC;
SIGNAL wire_nl0lO_dataout : STD_LOGIC;
SIGNAL wire_nl0Oi_dataout : STD_LOGIC;
SIGNAL wire_nl0Ol_dataout : STD_LOGIC;
SIGNAL wire_nl0OO_dataout : STD_LOGIC;
SIGNAL wire_nl11i_dataout : STD_LOGIC;
SIGNAL wire_nl1l_dataout : STD_LOGIC;
SIGNAL wire_nl1l_w_lg_dataout80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl1lO_dataout : STD_LOGIC;
SIGNAL wire_nl1O_dataout : STD_LOGIC;
SIGNAL wire_nl1O_w_lg_dataout89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl1O_w_lg_dataout182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl1Oi_dataout : STD_LOGIC;
SIGNAL wire_nl1Ol_dataout : STD_LOGIC;
SIGNAL wire_nl1OO_dataout : STD_LOGIC;
SIGNAL wire_nli0i_dataout : STD_LOGIC;
SIGNAL wire_nli0l_dataout : STD_LOGIC;
SIGNAL wire_nli0O_dataout : STD_LOGIC;
SIGNAL wire_nli1i_dataout : STD_LOGIC;
SIGNAL wire_nli1l_dataout : STD_LOGIC;
SIGNAL wire_nli1O_dataout : STD_LOGIC;
SIGNAL wire_nliii_dataout : STD_LOGIC;
SIGNAL wire_nliil_dataout : STD_LOGIC;
SIGNAL wire_nliiO_dataout : STD_LOGIC;
SIGNAL wire_nlili_dataout : STD_LOGIC;
SIGNAL wire_nlill_dataout : STD_LOGIC;
SIGNAL wire_nlilO_dataout : STD_LOGIC;
SIGNAL wire_nliOi_dataout : STD_LOGIC;
SIGNAL wire_nliOl_dataout : STD_LOGIC;
SIGNAL wire_nliOO_dataout : STD_LOGIC;
SIGNAL wire_nll0i_dataout : STD_LOGIC;
SIGNAL wire_nll0l_dataout : STD_LOGIC;
SIGNAL wire_nll0O_dataout : STD_LOGIC;
SIGNAL wire_nll1i_dataout : STD_LOGIC;
SIGNAL wire_nll1l_dataout : STD_LOGIC;
SIGNAL wire_nll1O_dataout : STD_LOGIC;
SIGNAL wire_nllii_dataout : STD_LOGIC;
SIGNAL wire_nllil_dataout : STD_LOGIC;
SIGNAL wire_nlliO_dataout : STD_LOGIC;
SIGNAL wire_nllli_dataout : STD_LOGIC;
SIGNAL wire_nllll_dataout : STD_LOGIC;
SIGNAL wire_nlllO_dataout : STD_LOGIC;
SIGNAL wire_nllO0i_dataout : STD_LOGIC;
SIGNAL wire_nllO0l_dataout : STD_LOGIC;
SIGNAL wire_nllO0O_dataout : STD_LOGIC;
SIGNAL wire_nllOi_dataout : STD_LOGIC;
SIGNAL wire_nllOii_dataout : STD_LOGIC;
SIGNAL wire_nllOil_dataout : STD_LOGIC;
SIGNAL wire_nllOiO_dataout : STD_LOGIC;
SIGNAL wire_nllOl_dataout : STD_LOGIC;
SIGNAL wire_nllOli_dataout : STD_LOGIC;
SIGNAL wire_nllOll_dataout : STD_LOGIC;
SIGNAL wire_nllOlO_dataout : STD_LOGIC;
SIGNAL wire_nllOO_dataout : STD_LOGIC;
SIGNAL wire_nllOOi_dataout : STD_LOGIC;
SIGNAL wire_nllOOl_dataout : STD_LOGIC;
SIGNAL wire_nllOOO_dataout : STD_LOGIC;
SIGNAL wire_nlO0i_dataout : STD_LOGIC;
SIGNAL wire_nlO0l_dataout : STD_LOGIC;
SIGNAL wire_nlO0Oi_dataout : STD_LOGIC;
SIGNAL wire_nlO0Ol_dataout : STD_LOGIC;
SIGNAL wire_nlO0OO_dataout : STD_LOGIC;
SIGNAL wire_nlO10i_dataout : STD_LOGIC;
SIGNAL wire_nlO10l_dataout : STD_LOGIC;
SIGNAL wire_nlO10O_dataout : STD_LOGIC;
SIGNAL wire_nlO11i_dataout : STD_LOGIC;
SIGNAL wire_nlO11l_dataout : STD_LOGIC;
SIGNAL wire_nlO11O_dataout : STD_LOGIC;
SIGNAL wire_nlO1i_dataout : STD_LOGIC;
SIGNAL wire_nlO1ii_dataout : STD_LOGIC;
SIGNAL wire_nlO1il_dataout : STD_LOGIC;
SIGNAL wire_nlO1iO_dataout : STD_LOGIC;
SIGNAL wire_nlO1l_dataout : STD_LOGIC;
SIGNAL wire_nlO1li_dataout : STD_LOGIC;
SIGNAL wire_nlO1ll_dataout : STD_LOGIC;
SIGNAL wire_nlO1lO_dataout : STD_LOGIC;
SIGNAL wire_nlO1O_dataout : STD_LOGIC;
SIGNAL wire_nlO1Oi_dataout : STD_LOGIC;
SIGNAL wire_nlO1Ol_dataout : STD_LOGIC;
SIGNAL wire_nlO1OO_dataout : STD_LOGIC;
SIGNAL wire_nlOi0i_dataout : STD_LOGIC;
SIGNAL wire_nlOi0l_dataout : STD_LOGIC;
SIGNAL wire_nlOi0O_dataout : STD_LOGIC;
SIGNAL wire_nlOi1i_dataout : STD_LOGIC;
SIGNAL wire_nlOi1l_dataout : STD_LOGIC;
SIGNAL wire_nlOi1O_dataout : STD_LOGIC;
SIGNAL wire_nlOiii_dataout : STD_LOGIC;
SIGNAL wire_nlOiil_dataout : STD_LOGIC;
SIGNAL wire_nlOiiO_dataout : STD_LOGIC;
SIGNAL wire_nlOili_dataout : STD_LOGIC;
SIGNAL wire_nlOill_dataout : STD_LOGIC;
SIGNAL wire_nlOilO_dataout : STD_LOGIC;
SIGNAL wire_nlOiOi_dataout : STD_LOGIC;
SIGNAL wire_nlOiOl_dataout : STD_LOGIC;
SIGNAL wire_nlOiOO_dataout : STD_LOGIC;
SIGNAL wire_nlOl0i_dataout : STD_LOGIC;
SIGNAL wire_nlOl0l_dataout : STD_LOGIC;
SIGNAL wire_nlOl0O_dataout : STD_LOGIC;
SIGNAL wire_nlOl1i_dataout : STD_LOGIC;
SIGNAL wire_nlOl1l_dataout : STD_LOGIC;
SIGNAL wire_nlOl1O_dataout : STD_LOGIC;
SIGNAL wire_nlOlii_dataout : STD_LOGIC;
SIGNAL wire_nlOlil_dataout : STD_LOGIC;
SIGNAL wire_nlOliO_dataout : STD_LOGIC;
SIGNAL wire_nlOlli_dataout : STD_LOGIC;
SIGNAL wire_nlOlll_dataout : STD_LOGIC;
SIGNAL wire_nlOllO_dataout : STD_LOGIC;
SIGNAL wire_nlOlOi_dataout : STD_LOGIC;
SIGNAL wire_nlOlOl_dataout : STD_LOGIC;
SIGNAL wire_nlOlOO_dataout : STD_LOGIC;
SIGNAL wire_nlOO0O_dataout : STD_LOGIC;
SIGNAL wire_nlOO1i_dataout : STD_LOGIC;
SIGNAL wire_nlOO1l_dataout : STD_LOGIC;
SIGNAL wire_nlOO1O_dataout : STD_LOGIC;
SIGNAL wire_nlOOii_dataout : STD_LOGIC;
SIGNAL wire_nlOOil_dataout : STD_LOGIC;
SIGNAL wire_nlOOiO_dataout : STD_LOGIC;
SIGNAL wire_nlOOli_dataout : STD_LOGIC;
SIGNAL wire_nlOOll_dataout : STD_LOGIC;
SIGNAL wire_nlOOlO_dataout : STD_LOGIC;
SIGNAL wire_nlOOOi_dataout : STD_LOGIC;
SIGNAL wire_nlOOOl_dataout : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_nli0iO178w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli0iO178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxctrl_range1w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxctrl_range9w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxctrl_range13w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxctrl_range21w122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range121w306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range153w320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range162w327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range140w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0lOi98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0OiO113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0OlO70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0OOi67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0OOl64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli00i23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli01l25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli0il15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli0li11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli11l58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli1iO37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli1ll33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli1Oi31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlii1i3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_resetall101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range152w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range120w236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range161w269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rxdatain_range139w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_nli0ll49w50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nli0ll49w50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nli1Ol35w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli0ll49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nli1Ol35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl00ii : STD_LOGIC;
SIGNAL nl00il : STD_LOGIC;
SIGNAL nl00ll : STD_LOGIC;
SIGNAL nl00lO : STD_LOGIC;
SIGNAL nl00Oi : STD_LOGIC;
SIGNAL nl00Ol : STD_LOGIC;
SIGNAL nl0i0i : STD_LOGIC;
SIGNAL nl0i0l : STD_LOGIC;
SIGNAL nl0iii : STD_LOGIC;
SIGNAL nl0ili : STD_LOGIC;
SIGNAL nl0iOi : STD_LOGIC;
SIGNAL nl0iOl : STD_LOGIC;
SIGNAL nl0l1l : STD_LOGIC;
SIGNAL nl0lii : STD_LOGIC;
SIGNAL nl0lli : STD_LOGIC;
SIGNAL nl0lOi : STD_LOGIC;
SIGNAL nl0lOl : STD_LOGIC;
SIGNAL nl0lOO : STD_LOGIC;
SIGNAL nl0O0i : STD_LOGIC;
SIGNAL nl0O0l : STD_LOGIC;
SIGNAL nl0O1i : STD_LOGIC;
SIGNAL nl0Oil : STD_LOGIC;
SIGNAL nl0OiO : STD_LOGIC;
SIGNAL nl0OlO : STD_LOGIC;
SIGNAL nl0OOi : STD_LOGIC;
SIGNAL nl0OOl : STD_LOGIC;
SIGNAL nli00i : STD_LOGIC;
SIGNAL nli00l : STD_LOGIC;
SIGNAL nli01l : STD_LOGIC;
SIGNAL nli01O : STD_LOGIC;
SIGNAL nli0il : STD_LOGIC;
SIGNAL nli0iO : STD_LOGIC;
SIGNAL nli0li : STD_LOGIC;
SIGNAL nli0ll : STD_LOGIC;
SIGNAL nli11l : STD_LOGIC;
SIGNAL nli1iO : STD_LOGIC;
SIGNAL nli1li : STD_LOGIC;
SIGNAL nli1ll : STD_LOGIC;
SIGNAL nli1lO : STD_LOGIC;
SIGNAL nli1Oi : STD_LOGIC;
SIGNAL nli1Ol : STD_LOGIC;
SIGNAL nlii1i : STD_LOGIC;
SIGNAL wire_w_rxctrl_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxctrl_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxctrl_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxctrl_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rxdatain_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_w_lg_w_lg_nli0iO178w181w(0) <= wire_w_lg_nli0iO178w(0) AND wire_nl0i1l40_w_lg_q180w(0);
wire_w_lg_nli0iO178w(0) <= nli0iO AND nli1lO;
wire_w_lg_w_rxctrl_range1w79w(0) <= wire_w_rxctrl_range1w(0) AND nl0Oil;
wire_w_lg_w_rxctrl_range9w85w(0) <= wire_w_rxctrl_range9w(0) AND nl0O0i;
wire_w_lg_w_rxctrl_range13w91w(0) <= wire_w_rxctrl_range13w(0) AND nl0lOO;
wire_w_lg_w_rxctrl_range21w122w(0) <= wire_w_rxctrl_range21w(0) AND nl0lii;
wire_w_lg_w_rxdatain_range121w306w(0) <= wire_w_rxdatain_range121w(0) AND wire_w_lg_w_rxdatain_range120w236w(0);
wire_w_lg_w_rxdatain_range153w320w(0) <= wire_w_rxdatain_range153w(0) AND wire_w_lg_w_rxdatain_range152w259w(0);
wire_w_lg_w_rxdatain_range162w327w(0) <= wire_w_rxdatain_range162w(0) AND wire_w_lg_w_rxdatain_range161w269w(0);
wire_w_lg_w_rxdatain_range140w313w(0) <= wire_w_rxdatain_range140w(0) AND wire_w_lg_w_rxdatain_range139w249w(0);
wire_w_lg_nl0lOi98w(0) <= NOT nl0lOi;
wire_w_lg_nl0OiO113w(0) <= NOT nl0OiO;
wire_w_lg_nl0OlO70w(0) <= NOT nl0OlO;
wire_w_lg_nl0OOi67w(0) <= NOT nl0OOi;
wire_w_lg_nl0OOl64w(0) <= NOT nl0OOl;
wire_w_lg_nli00i23w(0) <= NOT nli00i;
wire_w_lg_nli01l25w(0) <= NOT nli01l;
wire_w_lg_nli0il15w(0) <= NOT nli0il;
wire_w_lg_nli0li11w(0) <= NOT nli0li;
wire_w_lg_nli11l58w(0) <= NOT nli11l;
wire_w_lg_nli1iO37w(0) <= NOT nli1iO;
wire_w_lg_nli1ll33w(0) <= NOT nli1ll;
wire_w_lg_nli1Oi31w(0) <= NOT nli1Oi;
wire_w_lg_nlii1i3w(0) <= NOT nlii1i;
wire_w_lg_resetall101w(0) <= NOT resetall;
wire_w_lg_w_rxdatain_range152w259w(0) <= NOT wire_w_rxdatain_range152w(0);
wire_w_lg_w_rxdatain_range120w236w(0) <= NOT wire_w_rxdatain_range120w(0);
wire_w_lg_w_rxdatain_range161w269w(0) <= NOT wire_w_rxdatain_range161w(0);
wire_w_lg_w_rxdatain_range139w249w(0) <= NOT wire_w_rxdatain_range139w(0);
wire_w_lg_w_lg_w_lg_nli0ll49w50w51w(0) <= wire_w_lg_w_lg_nli0ll49w50w(0) OR nli01O;
wire_w_lg_w_lg_nli0ll49w50w(0) <= wire_w_lg_nli0ll49w(0) OR nli00l;
wire_w_lg_w_lg_nli1Ol35w36w(0) <= wire_w_lg_nli1Ol35w(0) OR nli1li;
wire_w_lg_nli0ll49w(0) <= nli0ll OR nli0iO;
wire_w_lg_nli1Ol35w(0) <= nli1Ol OR nli1lO;
nl00ii <= (nli01O OR wire_nl0l_dataout);
nl00il <= ((nl0lOl OR nl00ll) OR (NOT (nl00iO44 XOR nl00iO43)));
nl00ll <= (nl0O0l OR nl0O1i);
nl00lO <= (wire_nl0i_dataout OR (nli00l AND nli1li));
nl00Oi <= (nli00l OR wire_nl0i_dataout);
nl00Ol <= (wire_nl1O_w_lg_dataout182w(0) OR (NOT (nl00OO42 XOR nl00OO41)));
nl0i0i <= (niii OR nlOOO);
nl0i0l <= (nli0iO OR wire_nl1O_dataout);
nl0iii <= (wire_nl1l_dataout OR ((nli0ll AND nli1Ol) AND (nl0iil36 XOR nl0iil35)));
nl0ili <= (nlOOO OR ((niil OR niii) OR (NOT (nl0ill34 XOR nl0ill33))));
nl0iOi <= (nl0lOl OR nl0iOl);
nl0iOl <= ((nl0O1i OR nl0l1l) OR (NOT (nl0iOO32 XOR nl0iOO31)));
nl0l1l <= ((nl0OiO OR nl0O0l) OR (NOT (nl0l1O30 XOR nl0l1O29)));
nl0lii <= ((((((wire_w_lg_w_rxdatain_range162w327w(0) AND rxdatain(26)) AND rxdatain(27)) AND rxdatain(28)) AND rxdatain(29)) AND rxdatain(30)) AND rxdatain(31));
nl0lli <= '1';
nl0lOi <= ((((rxdatavalid(0) AND rxdatavalid(1)) AND rxdatavalid(2)) AND rxdatavalid(3)) AND (nl0lil26 XOR nl0lil25));
nl0lOl <= (wire_w_lg_w_rxctrl_range13w91w(0) AND wire_nl0i_w_lg_dataout92w(0));
nl0lOO <= ((((((wire_w_lg_w_rxdatain_range153w320w(0) AND rxdatain(18)) AND rxdatain(19)) AND rxdatain(20)) AND rxdatain(21)) AND rxdatain(22)) AND rxdatain(23));
nl0O0i <= ((((((wire_w_lg_w_rxdatain_range140w313w(0) AND rxdatain(10)) AND rxdatain(11)) AND rxdatain(12)) AND rxdatain(13)) AND rxdatain(14)) AND rxdatain(15));
nl0O0l <= ((wire_w_lg_w_rxctrl_range1w79w(0) AND wire_nl1l_w_lg_dataout80w(0)) AND (nl0O0O18 XOR nl0O0O17));
nl0O1i <= ((wire_w_lg_w_rxctrl_range9w85w(0) AND (nl0O1l20 XOR nl0O1l19)) AND wire_nl1O_w_lg_dataout89w(0));
nl0Oil <= ((((((wire_w_lg_w_rxdatain_range121w306w(0) AND rxdatain(2)) AND rxdatain(3)) AND rxdatain(4)) AND rxdatain(5)) AND rxdatain(6)) AND rxdatain(7));
nl0OiO <= (((NOT ((wire_w_lg_w_lg_nli1Ol35w36w(0) OR (((NOT rxctrl(3)) OR wire_w_lg_nli1iO37w(0)) OR (NOT (nli1ii8 XOR nli1ii7)))) OR (NOT (nli10l10 XOR nli10l9)))) OR (NOT (wire_w_lg_w_lg_w_lg_nli0ll49w50w51w(0) OR (NOT (nli11O12 XOR nli11O11))))) OR (NOT (((((((NOT rxctrl(0)) OR wire_w_lg_nli11l58w(0)) OR (NOT (nl0OOO14 XOR nl0OOO13))) OR ((NOT rxctrl(1)) OR wire_w_lg_nl0OOl64w(0))) OR ((NOT rxctrl(2)) OR wire_w_lg_nl0OOi67w(0))) OR ((NOT rxctrl(3)) OR wire_w_lg_nl0OlO70w(0))) OR (NOT (nl0Oli16 XOR nl0Oli15)))));
nl0OlO <= ((((((((NOT rxdatain(24)) AND wire_w_lg_w_rxdatain_range161w269w(0)) AND rxdatain(26)) AND rxdatain(27)) AND rxdatain(28)) AND (NOT rxdatain(29))) AND (NOT rxdatain(30))) AND (NOT rxdatain(31)));
nl0OOi <= ((((((((NOT rxdatain(16)) AND wire_w_lg_w_rxdatain_range152w259w(0)) AND rxdatain(18)) AND rxdatain(19)) AND rxdatain(20)) AND (NOT rxdatain(21))) AND (NOT rxdatain(22))) AND (NOT rxdatain(23)));
nl0OOl <= ((((((((NOT rxdatain(8)) AND wire_w_lg_w_rxdatain_range139w249w(0)) AND rxdatain(10)) AND rxdatain(11)) AND rxdatain(12)) AND (NOT rxdatain(13))) AND (NOT rxdatain(14))) AND (NOT rxdatain(15)));
nli00i <= ((((((((NOT rxdatain(24)) AND wire_w_lg_w_rxdatain_range161w269w(0)) AND rxdatain(26)) AND rxdatain(27)) AND rxdatain(28)) AND rxdatain(29)) AND (NOT rxdatain(30))) AND rxdatain(31));
nli00l <= (((NOT rxctrl(2)) OR wire_w_lg_nli0il15w(0)) OR (NOT (nli00O4 XOR nli00O3)));
nli01l <= ((((((((NOT rxdatain(0)) AND wire_w_lg_w_rxdatain_range120w236w(0)) AND rxdatain(2)) AND rxdatain(3)) AND rxdatain(4)) AND rxdatain(5)) AND rxdatain(6)) AND (NOT rxdatain(7)));
nli01O <= ((NOT rxctrl(3)) OR wire_w_lg_nli00i23w(0));
nli0il <= ((((((((NOT rxdatain(16)) AND wire_w_lg_w_rxdatain_range152w259w(0)) AND rxdatain(18)) AND rxdatain(19)) AND rxdatain(20)) AND rxdatain(21)) AND (NOT rxdatain(22))) AND rxdatain(23));
nli0iO <= ((NOT rxctrl(1)) OR wire_w_lg_nli0li11w(0));
nli0li <= ((((((((NOT rxdatain(8)) AND wire_w_lg_w_rxdatain_range139w249w(0)) AND rxdatain(10)) AND rxdatain(11)) AND rxdatain(12)) AND rxdatain(13)) AND (NOT rxdatain(14))) AND rxdatain(15));
nli0ll <= (((NOT rxctrl(0)) OR wire_w_lg_nlii1i3w(0)) OR (NOT (nli0lO2 XOR nli0lO1)));
nli11l <= ((((((((NOT rxdatain(0)) AND wire_w_lg_w_rxdatain_range120w236w(0)) AND rxdatain(2)) AND rxdatain(3)) AND rxdatain(4)) AND (NOT rxdatain(5))) AND (NOT rxdatain(6))) AND (NOT rxdatain(7)));
nli1iO <= ((((((((NOT rxdatain(24)) AND wire_w_lg_w_rxdatain_range161w269w(0)) AND rxdatain(26)) AND rxdatain(27)) AND rxdatain(28)) AND rxdatain(29)) AND rxdatain(30)) AND (NOT rxdatain(31)));
nli1li <= ((NOT rxctrl(2)) OR wire_w_lg_nli1ll33w(0));
nli1ll <= ((((((((NOT rxdatain(16)) AND wire_w_lg_w_rxdatain_range152w259w(0)) AND rxdatain(18)) AND rxdatain(19)) AND rxdatain(20)) AND rxdatain(21)) AND rxdatain(22)) AND (NOT rxdatain(23)));
nli1lO <= ((NOT rxctrl(1)) OR wire_w_lg_nli1Oi31w(0));
nli1Oi <= ((((((((NOT rxdatain(8)) AND wire_w_lg_w_rxdatain_range139w249w(0)) AND rxdatain(10)) AND rxdatain(11)) AND rxdatain(12)) AND rxdatain(13)) AND rxdatain(14)) AND (NOT rxdatain(15)));
nli1Ol <= (((NOT rxctrl(0)) OR wire_w_lg_nli01l25w(0)) OR (NOT (nli1OO6 XOR nli1OO5)));
nlii1i <= (((((((((NOT rxdatain(0)) AND wire_w_lg_w_rxdatain_range120w236w(0)) AND rxdatain(2)) AND rxdatain(3)) AND rxdatain(4)) AND rxdatain(5)) AND (NOT rxdatain(6))) AND rxdatain(7)) AND (nl000l46 XOR nl000l45));
rxctrlout <= ( niOl & nllO1O & nlO0lO & n11iO);
rxdataout <= ( nllO1l & nllO1i & nlllOO & nlllOl & nlllOi & nllllO & nlllll & nlllli & nlO0ll & nlO0li & nlO0iO & nlO0il & nlO0ii & nlO00O & nlO00l & nlO00i & n11il & n11ii & n110O & n110l & n110i & n111O & n111l & n111i & n1Oii & n1O0l & n1O0i & n1O1O & n1O1l & n1O1i & n1lOO & n1lOl);
wire_w_rxctrl_range1w(0) <= rxctrl(0);
wire_w_rxctrl_range9w(0) <= rxctrl(1);
wire_w_rxctrl_range13w(0) <= rxctrl(2);
wire_w_rxctrl_range21w(0) <= rxctrl(3);
wire_w_rxdatain_range121w(0) <= rxdatain(0);
wire_w_rxdatain_range153w(0) <= rxdatain(16);
wire_w_rxdatain_range152w(0) <= rxdatain(17);
wire_w_rxdatain_range120w(0) <= rxdatain(1);
wire_w_rxdatain_range162w(0) <= rxdatain(24);
wire_w_rxdatain_range161w(0) <= rxdatain(25);
wire_w_rxdatain_range140w(0) <= rxdatain(8);
wire_w_rxdatain_range139w(0) <= rxdatain(9);
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl000l45 <= nl000l46;
END IF;
if (now = 0 ns) then
nl000l45 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl000l46 <= nl000l45;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl00iO43 <= nl00iO44;
END IF;
if (now = 0 ns) then
nl00iO43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl00iO44 <= nl00iO43;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl00OO41 <= nl00OO42;
END IF;
if (now = 0 ns) then
nl00OO41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl00OO42 <= nl00OO41;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0i0O37 <= nl0i0O38;
END IF;
if (now = 0 ns) then
nl0i0O37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0i0O38 <= nl0i0O37;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0i1l39 <= nl0i1l40;
END IF;
if (now = 0 ns) then
nl0i1l39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0i1l40 <= nl0i1l39;
END IF;
END PROCESS;
wire_nl0i1l40_w_lg_q180w(0) <= nl0i1l40 XOR nl0i1l39;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0iil35 <= nl0iil36;
END IF;
if (now = 0 ns) then
nl0iil35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0iil36 <= nl0iil35;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0ill33 <= nl0ill34;
END IF;
if (now = 0 ns) then
nl0ill33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0ill34 <= nl0ill33;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0iOO31 <= nl0iOO32;
END IF;
if (now = 0 ns) then
nl0iOO31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0iOO32 <= nl0iOO31;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0l0l27 <= nl0l0l28;
END IF;
if (now = 0 ns) then
nl0l0l27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0l0l28 <= nl0l0l27;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0l1O29 <= nl0l1O30;
END IF;
if (now = 0 ns) then
nl0l1O29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0l1O30 <= nl0l1O29;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0lil25 <= nl0lil26;
END IF;
if (now = 0 ns) then
nl0lil25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0lil26 <= nl0lil25;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0lll23 <= nl0lll24;
END IF;
if (now = 0 ns) then
nl0lll23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0lll24 <= nl0lll23;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0llO21 <= nl0llO22;
END IF;
if (now = 0 ns) then
nl0llO21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0llO22 <= nl0llO21;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0O0O17 <= nl0O0O18;
END IF;
if (now = 0 ns) then
nl0O0O17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0O0O18 <= nl0O0O17;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0O1l19 <= nl0O1l20;
END IF;
if (now = 0 ns) then
nl0O1l19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0O1l20 <= nl0O1l19;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0Oli15 <= nl0Oli16;
END IF;
if (now = 0 ns) then
nl0Oli15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0Oli16 <= nl0Oli15;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0OOO13 <= nl0OOO14;
END IF;
if (now = 0 ns) then
nl0OOO13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nl0OOO14 <= nl0OOO13;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli00O3 <= nli00O4;
END IF;
if (now = 0 ns) then
nli00O3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli00O4 <= nli00O3;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli0lO1 <= nli0lO2;
END IF;
if (now = 0 ns) then
nli0lO1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli0lO2 <= nli0lO1;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli10l10 <= nli10l9;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli10l9 <= nli10l10;
END IF;
if (now = 0 ns) then
nli10l9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli11O11 <= nli11O12;
END IF;
if (now = 0 ns) then
nli11O11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli11O12 <= nli11O11;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli1ii7 <= nli1ii8;
END IF;
if (now = 0 ns) then
nli1ii7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli1ii8 <= nli1ii7;
END IF;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli1OO5 <= nli1OO6;
END IF;
if (now = 0 ns) then
nli1OO5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (rxclk)
BEGIN
IF (rxclk = '1' AND rxclk'event) THEN nli1OO6 <= nli1OO5;
END IF;
END PROCESS;
PROCESS (rxclk, wire_n1O0O_PRN)
BEGIN
IF (wire_n1O0O_PRN = '0') THEN
n11iO <= '1';
n1O1i <= '1';
n1O1l <= '1';
n1O1O <= '1';
n1Oii <= '1';
nlllli <= '1';
ELSIF (rxclk = '1' AND rxclk'event) THEN
n11iO <= wire_n1OiO_dataout;
n1O1i <= wire_n1OlO_dataout;
n1O1l <= wire_n1OOi_dataout;
n1O1O <= wire_n1OOl_dataout;
n1Oii <= wire_n011l_dataout;
nlllli <= wire_nllO0l_dataout;
END IF;
END PROCESS;
wire_n1O0O_PRN <= ((nl0i0O38 XOR nl0i0O37) AND wire_w_lg_resetall101w(0));
PROCESS (rxclk, resetall)
BEGIN
IF (resetall = '1') THEN
n00ll <= '0';
n00lO <= '0';
n00Oi <= '0';
n00Ol <= '0';
n00OO <= '0';
n0i1i <= '0';
n0i1l <= '0';
n0i1O <= '0';
n110i <= '0';
n110l <= '0';
n110O <= '0';
n111i <= '0';
n111l <= '0';
n111O <= '0';
n11ii <= '0';
n11il <= '0';
n1lOl <= '0';
n1lOO <= '0';
n1O0i <= '0';
n1O0l <= '0';
n1Oil <= '0';
ni00i <= '0';
ni00l <= '0';
ni00O <= '0';
ni01i <= '0';
ni01l <= '0';
ni01O <= '0';
ni0ii <= '0';
ni1Ol <= '0';
ni1OO <= '0';
niii <= '0';
niil <= '0';
niiO <= '0';
niOl <= '0';
nl10i <= '0';
nl10l <= '0';
nl10O <= '0';
nl11O <= '0';
nl1ii <= '0';
nl1il <= '0';
nl1iO <= '0';
nl1li <= '0';
nlllll <= '0';
nllllO <= '0';
nlllOi <= '0';
nlllOl <= '0';
nlllOO <= '0';
nllO1i <= '0';
nllO1l <= '0';
nllO1O <= '0';
nlO00i <= '0';
nlO00l <= '0';
nlO00O <= '0';
nlO0ii <= '0';
nlO0il <= '0';
nlO0iO <= '0';
nlO0li <= '0';
nlO0ll <= '0';
nlO0lO <= '0';
nlOii <= '0';
nlOil <= '0';
nlOlO <= '0';
nlOOi <= '0';
nlOOO <= '0';
ELSIF (rxclk = '1' AND rxclk'event) THEN
n00ll <= wire_n0i0O_dataout;
n00lO <= wire_n0iii_dataout;
n00Oi <= wire_n0iil_dataout;
n00Ol <= wire_n0iiO_dataout;
n00OO <= wire_n0ili_dataout;
n0i1i <= wire_n0ill_dataout;
n0i1l <= wire_n0ilO_dataout;
n0i1O <= wire_ni0il_dataout;
n110i <= wire_n11Ol_dataout;
n110l <= wire_n11OO_dataout;
n110O <= wire_n101i_dataout;
n111i <= wire_n11ll_dataout;
n111l <= wire_n11lO_dataout;
n111O <= wire_n11Oi_dataout;
n11ii <= wire_n101l_dataout;
n11il <= wire_n101O_dataout;
n1lOl <= wire_n1Oli_dataout;
n1lOO <= wire_n1Oll_dataout;
n1O0i <= wire_n1OOO_dataout;
n1O0l <= wire_n011i_dataout;
n1Oil <= wire_n0i0i_dataout;
ni00i <= wire_ni0Ol_dataout;
ni00l <= wire_ni0OO_dataout;
ni00O <= wire_nii1i_dataout;
ni01i <= wire_ni0ll_dataout;
ni01l <= wire_ni0lO_dataout;
ni01O <= wire_ni0Oi_dataout;
ni0ii <= wire_nl1lO_dataout;
ni1Ol <= wire_ni0iO_dataout;
ni1OO <= wire_ni0li_dataout;
niii <= nl0lOl;
niil <= nl0O1i;
niiO <= wire_nili_dataout;
niOl <= wire_nllO0i_dataout;
nl10i <= wire_nl1Ol_dataout;
nl10l <= wire_nl1OO_dataout;
nl10O <= wire_nl01i_dataout;
nl11O <= wire_nl1Oi_dataout;
nl1ii <= wire_nl01l_dataout;
nl1il <= wire_nl01O_dataout;
nl1iO <= wire_nl00i_dataout;
nl1li <= wire_nl00l_dataout;
nlllll <= wire_nllO0O_dataout;
nllllO <= wire_nllOii_dataout;
nlllOi <= wire_nllOil_dataout;
nlllOl <= wire_nllOiO_dataout;
nlllOO <= wire_nllOli_dataout;
nllO1i <= wire_nllOll_dataout;
nllO1l <= wire_nllOlO_dataout;
nllO1O <= wire_nlO0Oi_dataout;
nlO00i <= wire_nlO0Ol_dataout;
nlO00l <= wire_nlO0OO_dataout;
nlO00O <= wire_nlOi1i_dataout;
nlO0ii <= wire_nlOi1l_dataout;
nlO0il <= wire_nlOi1O_dataout;
nlO0iO <= wire_nlOi0i_dataout;
nlO0li <= wire_nlOi0l_dataout;
nlO0ll <= wire_nlOi0O_dataout;
nlO0lO <= wire_n11li_dataout;
nlOii <= wire_n11l_dataout;
nlOil <= wire_n11O_dataout;
nlOlO <= wire_n1ii_dataout;
nlOOi <= wire_n1il_dataout;
nlOOO <= ((wire_w_lg_w_rxctrl_range21w122w(0) AND wire_nl0l_w_lg_dataout123w(0)) AND (nl0l0l28 XOR nl0l0l27));
END IF;
END PROCESS;
PROCESS (rxclk, wire_niOO_PRN, wire_niOO_CLRN)
BEGIN
IF (wire_niOO_PRN = '0') THEN
n00li <= '1';
nl1i <= '1';
nl1ll <= '1';
nlOiO <= '1';
nlOli <= '1';
nlOll <= '1';
nlOOl <= '1';
ELSIF (wire_niOO_CLRN = '0') THEN
n00li <= '0';
nl1i <= '0';
nl1ll <= '0';
nlOiO <= '0';
nlOli <= '0';
nlOll <= '0';
nlOOl <= '0';
ELSIF (rxclk = '1' AND rxclk'event) THEN
n00li <= wire_n0i0l_dataout;
nl1i <= wire_w_lg_nl0lOi98w(0);
nl1ll <= wire_n11i_dataout;
nlOiO <= wire_n10i_dataout;
nlOli <= wire_n10l_dataout;
nlOll <= wire_n10O_dataout;
nlOOl <= wire_n1iO_dataout;
END IF;
if (now = 0 ns) then
n00li <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nl1i <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nl1ll <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOiO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOli <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOll <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOOl <= '1' after 1 ps;
end if;
END PROCESS;
wire_niOO_CLRN <= (nl0llO22 XOR nl0llO21);
wire_niOO_PRN <= ((nl0lll24 XOR nl0lll23) AND wire_w_lg_resetall101w(0));
wire_n000i_dataout <= nlOOi OR nl0iii;
wire_n000l_dataout <= nlOOl OR nl0iii;
wire_n001i_dataout <= nlOli OR nl0iii;
wire_n001l_dataout <= nlOll OR nl0iii;
wire_n001O_dataout <= nlOlO OR nl0iii;
wire_n00i_dataout <= rxctrl(0) WHEN nl0O0l = '1' ELSE wire_n0Oi_dataout;
wire_n00l_dataout <= rxdatain(0) WHEN nl0O0l = '1' ELSE wire_n0Ol_dataout;
wire_n00O_dataout <= rxdatain(1) WHEN nl0O0l = '1' ELSE wire_n0OO_dataout;
wire_n010i_dataout <= wire_n01Oi_dataout WHEN nl0ili = '1' ELSE nlOii;
wire_n010l_dataout <= wire_n01Ol_dataout WHEN nl0ili = '1' ELSE nlOil;
wire_n010O_dataout <= wire_n01OO_dataout WHEN nl0ili = '1' ELSE nlOiO;
wire_n011i_dataout <= wire_n01li_dataout AND NOT(nl1i);
wire_n011l_dataout <= wire_n01ll_dataout OR nl1i;
wire_n011O_dataout <= wire_n01lO_dataout WHEN nl0ili = '1' ELSE nl1ll;
wire_n01i_dataout <= wire_n0li_dataout AND NOT(wire_nill_dataout);
wire_n01ii_dataout <= wire_n001i_dataout WHEN nl0ili = '1' ELSE nlOli;
wire_n01il_dataout <= wire_n001l_dataout WHEN nl0ili = '1' ELSE nlOll;
wire_n01iO_dataout <= wire_n001O_dataout WHEN nl0ili = '1' ELSE nlOlO;
wire_n01l_dataout <= wire_n0ll_dataout AND NOT(wire_nill_dataout);
wire_n01li_dataout <= wire_n000i_dataout WHEN nl0ili = '1' ELSE nlOOi;
wire_n01ll_dataout <= wire_n000l_dataout WHEN nl0ili = '1' ELSE nlOOl;
wire_n01lO_dataout <= nl1ll OR nl0iii;
wire_n01O_dataout <= wire_n0lO_dataout AND NOT(wire_nill_dataout);
wire_n01Oi_dataout <= nlOii AND NOT(nl0iii);
wire_n01Ol_dataout <= nlOil OR nl0iii;
wire_n01OO_dataout <= nlOiO OR nl0iii;
wire_n0i0i_dataout <= wire_n0Oli_dataout WHEN niiO = '1' ELSE wire_n0l0O_dataout;
wire_n0i0l_dataout <= wire_n0Oll_dataout WHEN niiO = '1' ELSE wire_n0iOi_dataout;
wire_n0i0O_dataout <= wire_n0OlO_dataout WHEN niiO = '1' ELSE wire_n0iOl_dataout;
wire_n0ii_dataout <= rxdatain(2) WHEN nl0O0l = '1' ELSE wire_ni1i_dataout;
wire_n0iii_dataout <= wire_n0OOi_dataout WHEN niiO = '1' ELSE wire_n0iOO_dataout;
wire_n0iil_dataout <= wire_n0OOl_dataout WHEN niiO = '1' ELSE wire_n0l1i_dataout;
wire_n0iiO_dataout <= wire_n0OOO_dataout WHEN niiO = '1' ELSE wire_n0l1l_dataout;
wire_n0il_dataout <= rxdatain(3) WHEN nl0O0l = '1' ELSE wire_ni1l_dataout;
wire_n0ili_dataout <= wire_ni11i_dataout WHEN niiO = '1' ELSE wire_n0l1O_dataout;
wire_n0ill_dataout <= wire_ni11l_dataout WHEN niiO = '1' ELSE wire_n0l0i_dataout;
wire_n0ilO_dataout <= wire_ni11O_dataout WHEN niiO = '1' ELSE wire_n0l0l_dataout;
wire_n0iO_dataout <= rxdatain(4) WHEN nl0O0l = '1' ELSE wire_ni1O_dataout;
wire_n0iOi_dataout <= wire_n0lil_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n0iOl_dataout <= wire_n0liO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0iOO_dataout <= wire_n0lli_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l0i_dataout <= wire_n0lOl_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l0l_dataout <= wire_n0lOO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l0O_dataout <= wire_n0lii_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l1i_dataout <= wire_n0lll_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l1l_dataout <= wire_n0llO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0l1O_dataout <= wire_n0lOi_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0li_dataout <= rxdatain(5) WHEN nl0O0l = '1' ELSE wire_ni0i_dataout;
wire_n0lii_dataout <= wire_n0O1i_dataout OR nl0OiO;
wire_n0lil_dataout <= wire_n0O1l_dataout OR nl0OiO;
wire_n0liO_dataout <= wire_n0O1O_dataout OR nl0OiO;
wire_n0ll_dataout <= rxdatain(6) WHEN nl0O0l = '1' ELSE wire_ni0l_dataout;
wire_n0lli_dataout <= wire_n0O0i_dataout OR nl0OiO;
wire_n0lll_dataout <= wire_n0O0l_dataout AND NOT(nl0OiO);
wire_n0llO_dataout <= wire_n0O0O_dataout AND NOT(nl0OiO);
wire_n0lO_dataout <= rxdatain(7) WHEN nl0O0l = '1' ELSE wire_ni0O_dataout;
wire_n0lOi_dataout <= wire_n0Oii_dataout AND NOT(nl0OiO);
wire_n0lOl_dataout <= wire_n0Oil_dataout AND NOT(nl0OiO);
wire_n0lOO_dataout <= wire_n0OiO_dataout AND NOT(nl0OiO);
wire_n0O0i_dataout <= rxdatain(26) OR wire_nl0l_dataout;
wire_n0O0l_dataout <= rxdatain(27) OR wire_nl0l_dataout;
wire_n0O0O_dataout <= rxdatain(28) OR wire_nl0l_dataout;
wire_n0O1i_dataout <= rxctrl(3) OR wire_nl0l_dataout;
wire_n0O1l_dataout <= rxdatain(24) AND NOT(wire_nl0l_dataout);
wire_n0O1O_dataout <= rxdatain(25) OR wire_nl0l_dataout;
wire_n0Oi_dataout <= rxctrl(0) OR wire_nl1l_dataout;
wire_n0Oii_dataout <= rxdatain(29) OR wire_nl0l_dataout;
wire_n0Oil_dataout <= rxdatain(30) OR wire_nl0l_dataout;
wire_n0OiO_dataout <= rxdatain(31) OR wire_nl0l_dataout;
wire_n0Ol_dataout <= rxdatain(0) AND NOT(wire_nl1l_dataout);
wire_n0Oli_dataout <= wire_ni10i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0Oll_dataout <= wire_ni10l_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n0OlO_dataout <= wire_ni10O_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0OO_dataout <= rxdatain(1) OR wire_nl1l_dataout;
wire_n0OOi_dataout <= wire_ni1ii_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0OOl_dataout <= wire_ni1il_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n0OOO_dataout <= wire_ni1iO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n100i_dataout <= wire_n1l0i_dataout WHEN nl0O0l = '1' ELSE wire_n10Oi_dataout;
wire_n100l_dataout <= wire_n1l0l_dataout WHEN nl0O0l = '1' ELSE wire_n10Ol_dataout;
wire_n100O_dataout <= wire_n1l0O_dataout WHEN nl0O0l = '1' ELSE wire_n10OO_dataout;
wire_n101i_dataout <= wire_n10li_dataout AND NOT(nl1i);
wire_n101l_dataout <= wire_n10ll_dataout AND NOT(nl1i);
wire_n101O_dataout <= wire_n10lO_dataout AND NOT(nl1i);
wire_n10i_dataout <= wire_n1Oi_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n10ii_dataout <= wire_n1lii_dataout WHEN nl0O0l = '1' ELSE wire_n1i1i_dataout;
wire_n10il_dataout <= wire_n1lil_dataout WHEN nl0O0l = '1' ELSE wire_n1i1l_dataout;
wire_n10iO_dataout <= wire_n1liO_dataout WHEN nl0O0l = '1' ELSE wire_n1i1O_dataout;
wire_n10l_dataout <= wire_n1Ol_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n10li_dataout <= wire_n1lli_dataout WHEN nl0O0l = '1' ELSE wire_n1i0i_dataout;
wire_n10ll_dataout <= wire_n1lll_dataout WHEN nl0O0l = '1' ELSE wire_n1i0l_dataout;
wire_n10lO_dataout <= wire_n1llO_dataout WHEN nl0O0l = '1' ELSE wire_n1i0O_dataout;
wire_n10O_dataout <= wire_n1OO_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n10Oi_dataout <= wire_n1iii_dataout WHEN nl0i0i = '1' ELSE ni0ii;
wire_n10Ol_dataout <= wire_n1iil_dataout WHEN nl0i0i = '1' ELSE nl11O;
wire_n10OO_dataout <= wire_n1iiO_dataout WHEN nl0i0i = '1' ELSE nl10i;
wire_n11i_dataout <= wire_n1li_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n11l_dataout <= wire_n1ll_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n11li_dataout <= wire_n100i_dataout AND NOT(nl1i);
wire_n11ll_dataout <= wire_n100l_dataout AND NOT(nl1i);
wire_n11lO_dataout <= wire_n100O_dataout AND NOT(nl1i);
wire_n11O_dataout <= wire_n1lO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n11Oi_dataout <= wire_n10ii_dataout AND NOT(nl1i);
wire_n11Ol_dataout <= wire_n10il_dataout AND NOT(nl1i);
wire_n11OO_dataout <= wire_n10iO_dataout AND NOT(nl1i);
wire_n1i0i_dataout <= wire_n1iOi_dataout WHEN nl0i0i = '1' ELSE nl1il;
wire_n1i0l_dataout <= wire_n1iOl_dataout WHEN nl0i0i = '1' ELSE nl1iO;
wire_n1i0O_dataout <= wire_n1iOO_dataout WHEN nl0i0i = '1' ELSE nl1li;
wire_n1i1i_dataout <= wire_n1ili_dataout WHEN nl0i0i = '1' ELSE nl10l;
wire_n1i1l_dataout <= wire_n1ill_dataout WHEN nl0i0i = '1' ELSE nl10O;
wire_n1i1O_dataout <= wire_n1ilO_dataout WHEN nl0i0i = '1' ELSE nl1ii;
wire_n1ii_dataout <= wire_n01i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n1iii_dataout <= ni0ii OR nl00Ol;
wire_n1iil_dataout <= nl11O AND NOT(nl00Ol);
wire_n1iiO_dataout <= nl10i OR nl00Ol;
wire_n1il_dataout <= wire_n01l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_n1ili_dataout <= nl10l OR nl00Ol;
wire_n1ill_dataout <= nl10O OR nl00Ol;
wire_n1ilO_dataout <= nl1ii OR nl00Ol;
wire_n1iO_dataout <= wire_n01O_dataout OR wire_w_lg_nl0lOi98w(0);
wire_n1iOi_dataout <= nl1il OR nl00Ol;
wire_n1iOl_dataout <= nl1iO OR nl00Ol;
wire_n1iOO_dataout <= nl1li OR nl00Ol;
wire_n1l0i_dataout <= ni0ii OR nl0i0l;
wire_n1l0l_dataout <= nl11O AND NOT(nl0i0l);
wire_n1l0O_dataout <= nl10i OR nl0i0l;
wire_n1li_dataout <= wire_n00i_dataout OR wire_nill_dataout;
wire_n1lii_dataout <= nl10l OR nl0i0l;
wire_n1lil_dataout <= nl10O OR nl0i0l;
wire_n1liO_dataout <= nl1ii OR nl0i0l;
wire_n1ll_dataout <= wire_n00l_dataout OR wire_nill_dataout;
wire_n1lli_dataout <= nl1il OR nl0i0l;
wire_n1lll_dataout <= nl1iO OR nl0i0l;
wire_n1llO_dataout <= nl1li OR nl0i0l;
wire_n1lO_dataout <= wire_n00O_dataout OR wire_nill_dataout;
wire_n1Oi_dataout <= wire_n0ii_dataout OR wire_nill_dataout;
wire_n1OiO_dataout <= wire_n011O_dataout OR nl1i;
wire_n1Ol_dataout <= wire_n0il_dataout AND NOT(wire_nill_dataout);
wire_n1Oli_dataout <= wire_n010i_dataout AND NOT(nl1i);
wire_n1Oll_dataout <= wire_n010l_dataout AND NOT(nl1i);
wire_n1OlO_dataout <= wire_n010O_dataout OR nl1i;
wire_n1OO_dataout <= wire_n0iO_dataout AND NOT(wire_nill_dataout);
wire_n1OOi_dataout <= wire_n01ii_dataout OR nl1i;
wire_n1OOl_dataout <= wire_n01il_dataout OR nl1i;
wire_n1OOO_dataout <= wire_n01iO_dataout AND NOT(nl1i);
wire_ni0i_dataout <= rxdatain(5) OR wire_nl1l_dataout;
wire_ni0il_dataout <= wire_nilOl_dataout WHEN niiO = '1' ELSE wire_nii1l_dataout;
wire_ni0iO_dataout <= wire_nilOO_dataout WHEN niiO = '1' ELSE wire_nii1O_dataout;
wire_ni0l_dataout <= rxdatain(6) OR wire_nl1l_dataout;
wire_ni0li_dataout <= wire_niO1i_dataout WHEN niiO = '1' ELSE wire_nii0i_dataout;
wire_ni0ll_dataout <= wire_niO1l_dataout WHEN niiO = '1' ELSE wire_nii0l_dataout;
wire_ni0lO_dataout <= wire_niO1O_dataout WHEN niiO = '1' ELSE wire_nii0O_dataout;
wire_ni0O_dataout <= rxdatain(7) OR wire_nl1l_dataout;
wire_ni0Oi_dataout <= wire_niO0i_dataout WHEN niiO = '1' ELSE wire_niiii_dataout;
wire_ni0Ol_dataout <= wire_niO0l_dataout WHEN niiO = '1' ELSE wire_niiil_dataout;
wire_ni0OO_dataout <= wire_niO0O_dataout WHEN niiO = '1' ELSE wire_niiiO_dataout;
wire_ni10i_dataout <= wire_n0O1i_dataout OR nl0iOi;
wire_ni10l_dataout <= wire_n0O1l_dataout OR nl0iOi;
wire_ni10O_dataout <= wire_n0O1O_dataout OR nl0iOi;
wire_ni11i_dataout <= wire_ni1li_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_ni11l_dataout <= wire_ni1ll_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_ni11O_dataout <= wire_ni1lO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_ni1i_dataout <= rxdatain(2) OR wire_nl1l_dataout;
wire_ni1ii_dataout <= wire_n0O0i_dataout OR nl0iOi;
wire_ni1il_dataout <= wire_n0O0l_dataout AND NOT(nl0iOi);
wire_ni1iO_dataout <= wire_n0O0O_dataout AND NOT(nl0iOi);
wire_ni1l_dataout <= rxdatain(3) OR wire_nl1l_dataout;
wire_ni1li_dataout <= wire_n0Oii_dataout AND NOT(nl0iOi);
wire_ni1ll_dataout <= wire_n0Oil_dataout AND NOT(nl0iOi);
wire_ni1lO_dataout <= wire_n0OiO_dataout AND NOT(nl0iOi);
wire_ni1O_dataout <= rxdatain(4) OR wire_nl1l_dataout;
wire_nii0i_dataout <= wire_niiOi_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nii0l_dataout <= wire_niiOl_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nii0O_dataout <= wire_niiOO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nii1i_dataout <= wire_niOii_dataout WHEN niiO = '1' ELSE wire_niili_dataout;
wire_nii1l_dataout <= wire_niill_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nii1O_dataout <= wire_niilO_dataout OR wire_w_lg_nl0lOi98w(0);
wire_niiii_dataout <= wire_nil1i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niiil_dataout <= wire_nil1l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niiiO_dataout <= wire_nil1O_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niili_dataout <= wire_nil0i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niill_dataout <= wire_nil0l_dataout OR nl0OiO;
wire_niilO_dataout <= wire_nil0O_dataout OR nl0OiO;
wire_niiOi_dataout <= wire_nilii_dataout OR nl0OiO;
wire_niiOl_dataout <= wire_nilil_dataout OR nl0OiO;
wire_niiOO_dataout <= wire_niliO_dataout AND NOT(nl0OiO);
wire_nil0i_dataout <= wire_nilOi_dataout AND NOT(nl0OiO);
wire_nil0l_dataout <= rxctrl(2) OR wire_nl0i_dataout;
wire_nil0O_dataout <= rxdatain(16) AND NOT(wire_nl0i_dataout);
wire_nil1i_dataout <= wire_nilli_dataout AND NOT(nl0OiO);
wire_nil1l_dataout <= wire_nilll_dataout AND NOT(nl0OiO);
wire_nil1O_dataout <= wire_nillO_dataout AND NOT(nl0OiO);
wire_nili_dataout <= wire_w_lg_nl0OiO113w(0) AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nilii_dataout <= rxdatain(17) OR wire_nl0i_dataout;
wire_nilil_dataout <= rxdatain(18) OR wire_nl0i_dataout;
wire_niliO_dataout <= rxdatain(19) OR wire_nl0i_dataout;
wire_nill_dataout <= nl0OiO AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nilli_dataout <= rxdatain(20) OR wire_nl0i_dataout;
wire_nilll_dataout <= rxdatain(21) OR wire_nl0i_dataout;
wire_nillO_dataout <= rxdatain(22) OR wire_nl0i_dataout;
wire_nilOi_dataout <= rxdatain(23) OR wire_nl0i_dataout;
wire_nilOl_dataout <= wire_niOil_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nilOO_dataout <= wire_niOiO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO0i_dataout <= wire_niOOi_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO0l_dataout <= wire_niOOl_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO0O_dataout <= wire_niOOO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO1i_dataout <= wire_niOli_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO1l_dataout <= wire_niOll_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niO1O_dataout <= wire_niOlO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niOii_dataout <= wire_nl11i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_niOil_dataout <= wire_nil0l_dataout OR nl0iOl;
wire_niOiO_dataout <= wire_nil0O_dataout OR nl0iOl;
wire_niOli_dataout <= wire_nilii_dataout OR nl0iOl;
wire_niOll_dataout <= wire_nilil_dataout OR nl0iOl;
wire_niOlO_dataout <= wire_niliO_dataout AND NOT(nl0iOl);
wire_niOOi_dataout <= wire_nilli_dataout AND NOT(nl0iOl);
wire_niOOl_dataout <= wire_nilll_dataout AND NOT(nl0iOl);
wire_niOOO_dataout <= wire_nillO_dataout AND NOT(nl0iOl);
wire_nl00i_dataout <= wire_nllli_dataout WHEN niiO = '1' ELSE wire_nl0Oi_dataout;
wire_nl00l_dataout <= wire_nllll_dataout WHEN niiO = '1' ELSE wire_nl0Ol_dataout;
wire_nl00O_dataout <= wire_nl0OO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl01i_dataout <= wire_nllii_dataout WHEN niiO = '1' ELSE wire_nl0li_dataout;
wire_nl01l_dataout <= wire_nllil_dataout WHEN niiO = '1' ELSE wire_nl0ll_dataout;
wire_nl01O_dataout <= wire_nlliO_dataout WHEN niiO = '1' ELSE wire_nl0lO_dataout;
wire_nl0i_dataout <= rxrunningdisp(2) AND NOT(nl1i);
wire_nl0i_w_lg_dataout92w(0) <= NOT wire_nl0i_dataout;
wire_nl0ii_dataout <= wire_nli1i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0il_dataout <= wire_nli1l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0iO_dataout <= wire_nli1O_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0l_dataout <= rxrunningdisp(3) AND NOT(nl1i);
wire_nl0l_w_lg_dataout123w(0) <= NOT wire_nl0l_dataout;
wire_nl0li_dataout <= wire_nli0i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0ll_dataout <= wire_nli0l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0lO_dataout <= wire_nli0O_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0Oi_dataout <= wire_nliii_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0Ol_dataout <= wire_nliil_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nl0OO_dataout <= wire_nliiO_dataout OR nl0OiO;
wire_nl11i_dataout <= wire_nilOi_dataout AND NOT(nl0iOl);
wire_nl1l_dataout <= rxrunningdisp(0) AND NOT(nl1i);
wire_nl1l_w_lg_dataout80w(0) <= NOT wire_nl1l_dataout;
wire_nl1lO_dataout <= wire_nll1O_dataout WHEN niiO = '1' ELSE wire_nl00O_dataout;
wire_nl1O_dataout <= rxrunningdisp(1) AND NOT(nl1i);
wire_nl1O_w_lg_dataout89w(0) <= NOT wire_nl1O_dataout;
wire_nl1O_w_lg_dataout182w(0) <= wire_nl1O_dataout OR wire_w_lg_w_lg_nli0iO178w181w(0);
wire_nl1Oi_dataout <= wire_nll0i_dataout WHEN niiO = '1' ELSE wire_nl0ii_dataout;
wire_nl1Ol_dataout <= wire_nll0l_dataout WHEN niiO = '1' ELSE wire_nl0il_dataout;
wire_nl1OO_dataout <= wire_nll0O_dataout WHEN niiO = '1' ELSE wire_nl0iO_dataout;
wire_nli0i_dataout <= wire_nliOi_dataout AND NOT(nl0OiO);
wire_nli0l_dataout <= wire_nliOl_dataout AND NOT(nl0OiO);
wire_nli0O_dataout <= wire_nliOO_dataout AND NOT(nl0OiO);
wire_nli1i_dataout <= wire_nlili_dataout OR nl0OiO;
wire_nli1l_dataout <= wire_nlill_dataout OR nl0OiO;
wire_nli1O_dataout <= wire_nlilO_dataout OR nl0OiO;
wire_nliii_dataout <= wire_nll1i_dataout AND NOT(nl0OiO);
wire_nliil_dataout <= wire_nll1l_dataout AND NOT(nl0OiO);
wire_nliiO_dataout <= rxctrl(1) OR wire_nl1O_dataout;
wire_nlili_dataout <= rxdatain(8) AND NOT(wire_nl1O_dataout);
wire_nlill_dataout <= rxdatain(9) OR wire_nl1O_dataout;
wire_nlilO_dataout <= rxdatain(10) OR wire_nl1O_dataout;
wire_nliOi_dataout <= rxdatain(11) OR wire_nl1O_dataout;
wire_nliOl_dataout <= rxdatain(12) OR wire_nl1O_dataout;
wire_nliOO_dataout <= rxdatain(13) OR wire_nl1O_dataout;
wire_nll0i_dataout <= wire_nllOi_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nll0l_dataout <= wire_nllOl_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nll0O_dataout <= wire_nllOO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nll1i_dataout <= rxdatain(14) OR wire_nl1O_dataout;
wire_nll1l_dataout <= rxdatain(15) OR wire_nl1O_dataout;
wire_nll1O_dataout <= wire_nlllO_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nllii_dataout <= wire_nlO1i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nllil_dataout <= wire_nlO1l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nlliO_dataout <= wire_nlO1O_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nllli_dataout <= wire_nlO0i_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nllll_dataout <= wire_nlO0l_dataout AND NOT(wire_w_lg_nl0lOi98w(0));
wire_nlllO_dataout <= wire_nliiO_dataout OR nl0l1l;
wire_nllO0i_dataout <= wire_nlO10O_dataout AND NOT(nl1i);
wire_nllO0l_dataout <= wire_nllOOi_dataout OR nl1i;
wire_nllO0O_dataout <= wire_nllOOl_dataout AND NOT(nl1i);
wire_nllOi_dataout <= wire_nlili_dataout OR nl0l1l;
wire_nllOii_dataout <= wire_nllOOO_dataout AND NOT(nl1i);
wire_nllOil_dataout <= wire_nlO11i_dataout AND NOT(nl1i);
wire_nllOiO_dataout <= wire_nlO11l_dataout AND NOT(nl1i);
wire_nllOl_dataout <= wire_nlill_dataout OR nl0l1l;
wire_nllOli_dataout <= wire_nlO11O_dataout AND NOT(nl1i);
wire_nllOll_dataout <= wire_nlO10i_dataout AND NOT(nl1i);
wire_nllOlO_dataout <= wire_nlO10l_dataout AND NOT(nl1i);
wire_nllOO_dataout <= wire_nlilO_dataout OR nl0l1l;
wire_nllOOi_dataout <= wire_nlO1ii_dataout WHEN nl00il = '1' ELSE n00li;
wire_nllOOl_dataout <= wire_nlO1il_dataout WHEN nl00il = '1' ELSE n00ll;
wire_nllOOO_dataout <= wire_nlO1iO_dataout WHEN nl00il = '1' ELSE n00lO;
wire_nlO0i_dataout <= wire_nll1i_dataout AND NOT(nl0l1l);
wire_nlO0l_dataout <= wire_nll1l_dataout AND NOT(nl0l1l);
wire_nlO0Oi_dataout <= wire_nlOiii_dataout AND NOT(nl1i);
wire_nlO0Ol_dataout <= wire_nlOiil_dataout AND NOT(nl1i);
wire_nlO0OO_dataout <= wire_nlOiiO_dataout AND NOT(nl1i);
wire_nlO10i_dataout <= wire_nlO1Oi_dataout WHEN nl00il = '1' ELSE n0i1i;
wire_nlO10l_dataout <= wire_nlO1Ol_dataout WHEN nl00il = '1' ELSE n0i1l;
wire_nlO10O_dataout <= wire_nlO1OO_dataout WHEN nl00il = '1' ELSE n1Oil;
wire_nlO11i_dataout <= wire_nlO1li_dataout WHEN nl00il = '1' ELSE n00Oi;
wire_nlO11l_dataout <= wire_nlO1ll_dataout WHEN nl00il = '1' ELSE n00Ol;
wire_nlO11O_dataout <= wire_nlO1lO_dataout WHEN nl00il = '1' ELSE n00OO;
wire_nlO1i_dataout <= wire_nliOi_dataout AND NOT(nl0l1l);
wire_nlO1ii_dataout <= n00li AND NOT(nl00ii);
wire_nlO1il_dataout <= n00ll OR nl00ii;
wire_nlO1iO_dataout <= n00lO OR nl00ii;
wire_nlO1l_dataout <= wire_nliOl_dataout AND NOT(nl0l1l);
wire_nlO1li_dataout <= n00Oi OR nl00ii;
wire_nlO1ll_dataout <= n00Ol OR nl00ii;
wire_nlO1lO_dataout <= n00OO OR nl00ii;
wire_nlO1O_dataout <= wire_nliOO_dataout AND NOT(nl0l1l);
wire_nlO1Oi_dataout <= n0i1i OR nl00ii;
wire_nlO1Ol_dataout <= n0i1l OR nl00ii;
wire_nlO1OO_dataout <= n1Oil OR nl00ii;
wire_nlOi0i_dataout <= wire_nlOiOi_dataout AND NOT(nl1i);
wire_nlOi0l_dataout <= wire_nlOiOl_dataout AND NOT(nl1i);
wire_nlOi0O_dataout <= wire_nlOiOO_dataout AND NOT(nl1i);
wire_nlOi1i_dataout <= wire_nlOili_dataout AND NOT(nl1i);
wire_nlOi1l_dataout <= wire_nlOill_dataout AND NOT(nl1i);
wire_nlOi1O_dataout <= wire_nlOilO_dataout AND NOT(nl1i);
wire_nlOiii_dataout <= wire_nlOO0O_dataout WHEN nl00ll = '1' ELSE wire_nlOl1i_dataout;
wire_nlOiil_dataout <= wire_nlOOii_dataout WHEN nl00ll = '1' ELSE wire_nlOl1l_dataout;
wire_nlOiiO_dataout <= wire_nlOOil_dataout WHEN nl00ll = '1' ELSE wire_nlOl1O_dataout;
wire_nlOili_dataout <= wire_nlOOiO_dataout WHEN nl00ll = '1' ELSE wire_nlOl0i_dataout;
wire_nlOill_dataout <= wire_nlOOli_dataout WHEN nl00ll = '1' ELSE wire_nlOl0l_dataout;
wire_nlOilO_dataout <= wire_nlOOll_dataout WHEN nl00ll = '1' ELSE wire_nlOl0O_dataout;
wire_nlOiOi_dataout <= wire_nlOOlO_dataout WHEN nl00ll = '1' ELSE wire_nlOlii_dataout;
wire_nlOiOl_dataout <= wire_nlOOOi_dataout WHEN nl00ll = '1' ELSE wire_nlOlil_dataout;
wire_nlOiOO_dataout <= wire_nlOOOl_dataout WHEN nl00ll = '1' ELSE wire_nlOliO_dataout;
wire_nlOl0i_dataout <= wire_nlOlOi_dataout WHEN nlOOO = '1' ELSE ni01i;
wire_nlOl0l_dataout <= wire_nlOlOl_dataout WHEN nlOOO = '1' ELSE ni01l;
wire_nlOl0O_dataout <= wire_nlOlOO_dataout WHEN nlOOO = '1' ELSE ni01O;
wire_nlOl1i_dataout <= wire_nlOlli_dataout WHEN nlOOO = '1' ELSE n0i1O;
wire_nlOl1l_dataout <= wire_nlOlll_dataout WHEN nlOOO = '1' ELSE ni1Ol;
wire_nlOl1O_dataout <= wire_nlOllO_dataout WHEN nlOOO = '1' ELSE ni1OO;
wire_nlOlii_dataout <= wire_nlOO1i_dataout WHEN nlOOO = '1' ELSE ni00i;
wire_nlOlil_dataout <= wire_nlOO1l_dataout WHEN nlOOO = '1' ELSE ni00l;
wire_nlOliO_dataout <= wire_nlOO1O_dataout WHEN nlOOO = '1' ELSE ni00O;
wire_nlOlli_dataout <= n0i1O OR nl00lO;
wire_nlOlll_dataout <= ni1Ol AND NOT(nl00lO);
wire_nlOllO_dataout <= ni1OO OR nl00lO;
wire_nlOlOi_dataout <= ni01i OR nl00lO;
wire_nlOlOl_dataout <= ni01l OR nl00lO;
wire_nlOlOO_dataout <= ni01O OR nl00lO;
wire_nlOO0O_dataout <= n0i1O OR nl00Oi;
wire_nlOO1i_dataout <= ni00i OR nl00lO;
wire_nlOO1l_dataout <= ni00l OR nl00lO;
wire_nlOO1O_dataout <= ni00O OR nl00lO;
wire_nlOOii_dataout <= ni1Ol AND NOT(nl00Oi);
wire_nlOOil_dataout <= ni1OO OR nl00Oi;
wire_nlOOiO_dataout <= ni01i OR nl00Oi;
wire_nlOOli_dataout <= ni01l OR nl00Oi;
wire_nlOOll_dataout <= ni01O OR nl00Oi;
wire_nlOOlO_dataout <= ni00i OR nl00Oi;
wire_nlOOOi_dataout <= ni00l OR nl00Oi;
wire_nlOOOl_dataout <= ni00O OR nl00Oi;
END RTL; --stratixgx_xgm_rx_sm
--synopsys translate_on
--VALID FILE
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY sgate;
USE sgate.sgate_pack.all;
--synthesis_resources = lut 140 mux21 317 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 39
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_xgm_tx_sm IS
PORT
(
rdenablesync : IN STD_LOGIC;
resetall : IN STD_LOGIC;
txclk : IN STD_LOGIC;
txctrl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
txdatain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END stratixgx_xgm_tx_sm;
ARCHITECTURE RTL OF stratixgx_xgm_tx_sm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL niOOOO53 : STD_LOGIC := '0';
SIGNAL niOOOO54 : STD_LOGIC := '0';
SIGNAL nl000l5 : STD_LOGIC := '0';
SIGNAL nl000l6 : STD_LOGIC := '0';
SIGNAL nl00iO3 : STD_LOGIC := '0';
SIGNAL nl00iO4 : STD_LOGIC := '0';
SIGNAL nl00Oi1 : STD_LOGIC := '0';
SIGNAL nl00Oi2 : STD_LOGIC := '0';
SIGNAL nl010i13 : STD_LOGIC := '0';
SIGNAL nl010i14 : STD_LOGIC := '0';
SIGNAL nl01il11 : STD_LOGIC := '0';
SIGNAL nl01il12 : STD_LOGIC := '0';
SIGNAL nl01lO10 : STD_LOGIC := '0';
SIGNAL nl01lO9 : STD_LOGIC := '0';
SIGNAL nl01OO7 : STD_LOGIC := '0';
SIGNAL nl01OO8 : STD_LOGIC := '0';
SIGNAL nl100O39 : STD_LOGIC := '0';
SIGNAL nl100O40 : STD_LOGIC := '0';
SIGNAL nl10ll37 : STD_LOGIC := '0';
SIGNAL nl10ll38 : STD_LOGIC := '0';
SIGNAL nl111i51 : STD_LOGIC := '0';
SIGNAL nl111i52 : STD_LOGIC := '0';
SIGNAL nl11iO49 : STD_LOGIC := '0';
SIGNAL nl11iO50 : STD_LOGIC := '0';
SIGNAL nl11li47 : STD_LOGIC := '0';
SIGNAL nl11li48 : STD_LOGIC := '0';
SIGNAL nl11lO45 : STD_LOGIC := '0';
SIGNAL nl11lO46 : STD_LOGIC := '0';
SIGNAL nl11Oi43 : STD_LOGIC := '0';
SIGNAL nl11Oi44 : STD_LOGIC := '0';
SIGNAL nl11OO41 : STD_LOGIC := '0';
SIGNAL nl11OO42 : STD_LOGIC := '0';
SIGNAL nl1i0l33 : STD_LOGIC := '0';
SIGNAL nl1i0l34 : STD_LOGIC := '0';
SIGNAL nl1i1i35 : STD_LOGIC := '0';
SIGNAL nl1i1i36 : STD_LOGIC := '0';
SIGNAL nl1iiO31 : STD_LOGIC := '0';
SIGNAL nl1iiO32 : STD_LOGIC := '0';
SIGNAL nl1ilO29 : STD_LOGIC := '0';
SIGNAL nl1ilO30 : STD_LOGIC := '0';
SIGNAL nl1iOO27 : STD_LOGIC := '0';
SIGNAL nl1iOO28 : STD_LOGIC := '0';
SIGNAL nl1l0i25 : STD_LOGIC := '0';
SIGNAL nl1l0i26 : STD_LOGIC := '0';
SIGNAL nl1lli23 : STD_LOGIC := '0';
SIGNAL nl1lli24 : STD_LOGIC := '0';
SIGNAL nl1lOi21 : STD_LOGIC := '0';
SIGNAL nl1lOi22 : STD_LOGIC := '0';
SIGNAL nl1O0i19 : STD_LOGIC := '0';
SIGNAL nl1O0i20 : STD_LOGIC := '0';
SIGNAL nl1Oii17 : STD_LOGIC := '0';
SIGNAL nl1Oii18 : STD_LOGIC := '0';
SIGNAL nl1OOi15 : STD_LOGIC := '0';
SIGNAL nl1OOi16 : STD_LOGIC := '0';
SIGNAL n00i : STD_LOGIC := '0';
SIGNAL n01i : STD_LOGIC := '0';
SIGNAL n01l : STD_LOGIC := '0';
SIGNAL n10i : STD_LOGIC := '0';
SIGNAL n10l : STD_LOGIC := '0';
SIGNAL n10O : STD_LOGIC := '0';
SIGNAL n11i : STD_LOGIC := '0';
SIGNAL n11l : STD_LOGIC := '0';
SIGNAL n11O : STD_LOGIC := '0';
SIGNAL n1ii : STD_LOGIC := '0';
SIGNAL n1il : STD_LOGIC := '0';
SIGNAL n1iO : STD_LOGIC := '0';
SIGNAL n1li : STD_LOGIC := '0';
SIGNAL n1Oi : STD_LOGIC := '0';
SIGNAL n1Ol : STD_LOGIC := '0';
SIGNAL n1OO : STD_LOGIC := '0';
SIGNAL nllOO : STD_LOGIC := '0';
SIGNAL nlO0O : STD_LOGIC := '0';
SIGNAL nlO1l : STD_LOGIC := '0';
SIGNAL nlOii : STD_LOGIC := '0';
SIGNAL nlOiO : STD_LOGIC := '0';
SIGNAL nlOli : STD_LOGIC := '0';
SIGNAL nlOll : STD_LOGIC := '0';
SIGNAL nlOlO : STD_LOGIC := '0';
SIGNAL nlOOi : STD_LOGIC := '0';
SIGNAL nlOOl : STD_LOGIC := '0';
SIGNAL nlOOO : STD_LOGIC := '0';
SIGNAL n00O : STD_LOGIC := '0';
SIGNAL n0Ol : STD_LOGIC := '0';
SIGNAL n0OOO : STD_LOGIC := '0';
SIGNAL nli0O : STD_LOGIC := '0';
SIGNAL nliii : STD_LOGIC := '0';
SIGNAL nlliO : STD_LOGIC := '0';
SIGNAL nllli : STD_LOGIC := '0';
SIGNAL nllll : STD_LOGIC := '0';
SIGNAL nlllO : STD_LOGIC := '0';
SIGNAL nllOi : STD_LOGIC := '0';
SIGNAL nllOl : STD_LOGIC := '0';
SIGNAL wire_n0Oi_CLRN : STD_LOGIC;
SIGNAL wire_n0Oi_PRN : STD_LOGIC;
SIGNAL wire_n0Oi_w_lg_n00O166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0Oi_w_lg_n0Ol212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0Oi_w_lg_n0OOO272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0Oi_w_lg_nliii279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0Oil : STD_LOGIC := '0';
SIGNAL n0OiO : STD_LOGIC := '0';
SIGNAL n0Oli : STD_LOGIC := '0';
SIGNAL n0Oll : STD_LOGIC := '0';
SIGNAL n0OOl : STD_LOGIC := '0';
SIGNAL n1l0l : STD_LOGIC := '0';
SIGNAL n1l0O : STD_LOGIC := '0';
SIGNAL n1lii : STD_LOGIC := '0';
SIGNAL n1lil : STD_LOGIC := '0';
SIGNAL n1lli : STD_LOGIC := '0';
SIGNAL n1lll : STD_LOGIC := '0';
SIGNAL n1OOO : STD_LOGIC := '0';
SIGNAL nll01i : STD_LOGIC := '0';
SIGNAL nll1li : STD_LOGIC := '0';
SIGNAL nll1ll : STD_LOGIC := '0';
SIGNAL nll1lO : STD_LOGIC := '0';
SIGNAL nll1Oi : STD_LOGIC := '0';
SIGNAL nll1OO : STD_LOGIC := '0';
SIGNAL nlOi0i : STD_LOGIC := '0';
SIGNAL nlOi0l : STD_LOGIC := '0';
SIGNAL nlOi0O : STD_LOGIC := '0';
SIGNAL nlOi1O : STD_LOGIC := '0';
SIGNAL nlOiil : STD_LOGIC := '0';
SIGNAL nlOiiO : STD_LOGIC := '0';
SIGNAL wire_n0OOi_CLRN : STD_LOGIC;
SIGNAL wire_n0OOi_PRN : STD_LOGIC;
SIGNAL n1lO : STD_LOGIC := '0';
SIGNAL nlO0i : STD_LOGIC := '0';
SIGNAL nlO0l : STD_LOGIC := '0';
SIGNAL nlO1O : STD_LOGIC := '0';
SIGNAL nlOil : STD_LOGIC := '0';
SIGNAL wire_n1ll_CLRN : STD_LOGIC;
SIGNAL wire_n1ll_PRN : STD_LOGIC;
SIGNAL n00l : STD_LOGIC := '0';
SIGNAL n0O0O : STD_LOGIC := '0';
SIGNAL n0Oii : STD_LOGIC := '0';
SIGNAL n0OlO : STD_LOGIC := '0';
SIGNAL n0OO : STD_LOGIC := '0';
SIGNAL n1l0i : STD_LOGIC := '0';
SIGNAL n1l1O : STD_LOGIC := '0';
SIGNAL n1liO : STD_LOGIC := '0';
SIGNAL ni1l : STD_LOGIC := '0';
SIGNAL nl01O : STD_LOGIC := '0';
SIGNAL nli0i : STD_LOGIC := '0';
SIGNAL nli0l : STD_LOGIC := '0';
SIGNAL nli1O : STD_LOGIC := '0';
SIGNAL nll1il : STD_LOGIC := '0';
SIGNAL nll1iO : STD_LOGIC := '0';
SIGNAL nll1Ol : STD_LOGIC := '0';
SIGNAL nlOi1i : STD_LOGIC := '0';
SIGNAL nlOi1l : STD_LOGIC := '0';
SIGNAL nlOiii : STD_LOGIC := '0';
SIGNAL wire_ni1i_CLRN : STD_LOGIC;
SIGNAL wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w169w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_w_lg_ni1l162w164w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_ni1l162w164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_w_lg_ni1l162w168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_n00l278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_n0OO163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_w_lg_ni1l162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n000i_dataout : STD_LOGIC;
SIGNAL wire_n000l_dataout : STD_LOGIC;
SIGNAL wire_n000O_dataout : STD_LOGIC;
SIGNAL wire_n001i_dataout : STD_LOGIC;
SIGNAL wire_n001l_dataout : STD_LOGIC;
SIGNAL wire_n001O_dataout : STD_LOGIC;
SIGNAL wire_n00ii_dataout : STD_LOGIC;
SIGNAL wire_n00il_dataout : STD_LOGIC;
SIGNAL wire_n00iO_dataout : STD_LOGIC;
SIGNAL wire_n00li_dataout : STD_LOGIC;
SIGNAL wire_n00ll_dataout : STD_LOGIC;
SIGNAL wire_n00lO_dataout : STD_LOGIC;
SIGNAL wire_n00Oi_dataout : STD_LOGIC;
SIGNAL wire_n00Ol_dataout : STD_LOGIC;
SIGNAL wire_n00OO_dataout : STD_LOGIC;
SIGNAL wire_n010i_dataout : STD_LOGIC;
SIGNAL wire_n010l_dataout : STD_LOGIC;
SIGNAL wire_n010O_dataout : STD_LOGIC;
SIGNAL wire_n011i_dataout : STD_LOGIC;
SIGNAL wire_n011l_dataout : STD_LOGIC;
SIGNAL wire_n011O_dataout : STD_LOGIC;
SIGNAL wire_n01ii_dataout : STD_LOGIC;
SIGNAL wire_n01il_dataout : STD_LOGIC;
SIGNAL wire_n01iO_dataout : STD_LOGIC;
SIGNAL wire_n01li_dataout : STD_LOGIC;
SIGNAL wire_n01ll_dataout : STD_LOGIC;
SIGNAL wire_n01lO_dataout : STD_LOGIC;
SIGNAL wire_n01Oi_dataout : STD_LOGIC;
SIGNAL wire_n01Ol_dataout : STD_LOGIC;
SIGNAL wire_n01OO_dataout : STD_LOGIC;
SIGNAL wire_n0i0i_dataout : STD_LOGIC;
SIGNAL wire_n0i0l_dataout : STD_LOGIC;
SIGNAL wire_n0i0O_dataout : STD_LOGIC;
SIGNAL wire_n0i1i_dataout : STD_LOGIC;
SIGNAL wire_n0i1l_dataout : STD_LOGIC;
SIGNAL wire_n0i1O_dataout : STD_LOGIC;
SIGNAL wire_n0ii_dataout : STD_LOGIC;
SIGNAL wire_n0iii_dataout : STD_LOGIC;
SIGNAL wire_n0iil_dataout : STD_LOGIC;
SIGNAL wire_n0iiO_dataout : STD_LOGIC;
SIGNAL wire_n0il_dataout : STD_LOGIC;
SIGNAL wire_n0ili_dataout : STD_LOGIC;
SIGNAL wire_n0ill_dataout : STD_LOGIC;
SIGNAL wire_n0ilO_dataout : STD_LOGIC;
SIGNAL wire_n0iOi_dataout : STD_LOGIC;
SIGNAL wire_n0iOl_dataout : STD_LOGIC;
SIGNAL wire_n0iOO_dataout : STD_LOGIC;
SIGNAL wire_n0l0i_dataout : STD_LOGIC;
SIGNAL wire_n0l0l_dataout : STD_LOGIC;
SIGNAL wire_n0l0O_dataout : STD_LOGIC;
SIGNAL wire_n0l1i_dataout : STD_LOGIC;
SIGNAL wire_n0l1l_dataout : STD_LOGIC;
SIGNAL wire_n0l1O_dataout : STD_LOGIC;
SIGNAL wire_n0lii_dataout : STD_LOGIC;
SIGNAL wire_n0lil_dataout : STD_LOGIC;
SIGNAL wire_n0liO_dataout : STD_LOGIC;
SIGNAL wire_n0lli_dataout : STD_LOGIC;
SIGNAL wire_n0lll_dataout : STD_LOGIC;
SIGNAL wire_n0llO_dataout : STD_LOGIC;
SIGNAL wire_n0lOi_dataout : STD_LOGIC;
SIGNAL wire_n0lOl_dataout : STD_LOGIC;
SIGNAL wire_n0lOO_dataout : STD_LOGIC;
SIGNAL wire_n0O0i_dataout : STD_LOGIC;
SIGNAL wire_n0O0l_dataout : STD_LOGIC;
SIGNAL wire_n0O1i_dataout : STD_LOGIC;
SIGNAL wire_n0O1l_dataout : STD_LOGIC;
SIGNAL wire_n0O1O_dataout : STD_LOGIC;
SIGNAL wire_n100i_dataout : STD_LOGIC;
SIGNAL wire_n100l_dataout : STD_LOGIC;
SIGNAL wire_n100O_dataout : STD_LOGIC;
SIGNAL wire_n101i_dataout : STD_LOGIC;
SIGNAL wire_n101l_dataout : STD_LOGIC;
SIGNAL wire_n101O_dataout : STD_LOGIC;
SIGNAL wire_n10ii_dataout : STD_LOGIC;
SIGNAL wire_n10il_dataout : STD_LOGIC;
SIGNAL wire_n10iO_dataout : STD_LOGIC;
SIGNAL wire_n10li_dataout : STD_LOGIC;
SIGNAL wire_n10ll_dataout : STD_LOGIC;
SIGNAL wire_n10lO_dataout : STD_LOGIC;
SIGNAL wire_n10Oi_dataout : STD_LOGIC;
SIGNAL wire_n10Ol_dataout : STD_LOGIC;
SIGNAL wire_n10OO_dataout : STD_LOGIC;
SIGNAL wire_n110i_dataout : STD_LOGIC;
SIGNAL wire_n110l_dataout : STD_LOGIC;
SIGNAL wire_n110O_dataout : STD_LOGIC;
SIGNAL wire_n111i_dataout : STD_LOGIC;
SIGNAL wire_n111l_dataout : STD_LOGIC;
SIGNAL wire_n111O_dataout : STD_LOGIC;
SIGNAL wire_n11ii_dataout : STD_LOGIC;
SIGNAL wire_n11il_dataout : STD_LOGIC;
SIGNAL wire_n11iO_dataout : STD_LOGIC;
SIGNAL wire_n11li_dataout : STD_LOGIC;
SIGNAL wire_n11ll_dataout : STD_LOGIC;
SIGNAL wire_n11lO_dataout : STD_LOGIC;
SIGNAL wire_n11Oi_dataout : STD_LOGIC;
SIGNAL wire_n11Ol_dataout : STD_LOGIC;
SIGNAL wire_n11OO_dataout : STD_LOGIC;
SIGNAL wire_n1i0i_dataout : STD_LOGIC;
SIGNAL wire_n1i0l_dataout : STD_LOGIC;
SIGNAL wire_n1i0O_dataout : STD_LOGIC;
SIGNAL wire_n1i1i_dataout : STD_LOGIC;
SIGNAL wire_n1i1l_dataout : STD_LOGIC;
SIGNAL wire_n1i1O_dataout : STD_LOGIC;
SIGNAL wire_n1iii_dataout : STD_LOGIC;
SIGNAL wire_n1iil_dataout : STD_LOGIC;
SIGNAL wire_n1iiO_dataout : STD_LOGIC;
SIGNAL wire_n1ili_dataout : STD_LOGIC;
SIGNAL wire_n1ill_dataout : STD_LOGIC;
SIGNAL wire_n1ilO_dataout : STD_LOGIC;
SIGNAL wire_n1iOi_dataout : STD_LOGIC;
SIGNAL wire_n1iOl_dataout : STD_LOGIC;
SIGNAL wire_n1iOO_dataout : STD_LOGIC;
SIGNAL wire_n1l1i_dataout : STD_LOGIC;
SIGNAL wire_n1l1l_dataout : STD_LOGIC;
SIGNAL wire_n1llO_dataout : STD_LOGIC;
SIGNAL wire_n1lOi_dataout : STD_LOGIC;
SIGNAL wire_n1lOl_dataout : STD_LOGIC;
SIGNAL wire_n1lOO_dataout : STD_LOGIC;
SIGNAL wire_n1O0i_dataout : STD_LOGIC;
SIGNAL wire_n1O0l_dataout : STD_LOGIC;
SIGNAL wire_n1O1i_dataout : STD_LOGIC;
SIGNAL wire_n1O1l_dataout : STD_LOGIC;
SIGNAL wire_n1O1O_dataout : STD_LOGIC;
SIGNAL wire_ni00i_dataout : STD_LOGIC;
SIGNAL wire_ni00l_dataout : STD_LOGIC;
SIGNAL wire_ni00O_dataout : STD_LOGIC;
SIGNAL wire_ni0ii_dataout : STD_LOGIC;
SIGNAL wire_ni0il_dataout : STD_LOGIC;
SIGNAL wire_ni0iO_dataout : STD_LOGIC;
SIGNAL wire_ni0li_dataout : STD_LOGIC;
SIGNAL wire_ni0ll_dataout : STD_LOGIC;
SIGNAL wire_ni0lO_dataout : STD_LOGIC;
SIGNAL wire_ni0Oi_dataout : STD_LOGIC;
SIGNAL wire_ni0Ol_dataout : STD_LOGIC;
SIGNAL wire_ni0OO_dataout : STD_LOGIC;
SIGNAL wire_ni10i_dataout : STD_LOGIC;
SIGNAL wire_ni10l_dataout : STD_LOGIC;
SIGNAL wire_ni10O_dataout : STD_LOGIC;
SIGNAL wire_ni11i_dataout : STD_LOGIC;
SIGNAL wire_ni11l_dataout : STD_LOGIC;
SIGNAL wire_ni11O_dataout : STD_LOGIC;
SIGNAL wire_ni1ii_dataout : STD_LOGIC;
SIGNAL wire_ni1il_dataout : STD_LOGIC;
SIGNAL wire_ni1iO_dataout : STD_LOGIC;
SIGNAL wire_nii0i_dataout : STD_LOGIC;
SIGNAL wire_nii0l_dataout : STD_LOGIC;
SIGNAL wire_nii0O_dataout : STD_LOGIC;
SIGNAL wire_nii1i_dataout : STD_LOGIC;
SIGNAL wire_nii1l_dataout : STD_LOGIC;
SIGNAL wire_nii1O_dataout : STD_LOGIC;
SIGNAL wire_niiii_dataout : STD_LOGIC;
SIGNAL wire_niiil_dataout : STD_LOGIC;
SIGNAL wire_niiiO_dataout : STD_LOGIC;
SIGNAL wire_niili_dataout : STD_LOGIC;
SIGNAL wire_niill_dataout : STD_LOGIC;
SIGNAL wire_niilO_dataout : STD_LOGIC;
SIGNAL wire_niiOi_dataout : STD_LOGIC;
SIGNAL wire_niiOl_dataout : STD_LOGIC;
SIGNAL wire_niiOO_dataout : STD_LOGIC;
SIGNAL wire_nil0i_dataout : STD_LOGIC;
SIGNAL wire_nil0l_dataout : STD_LOGIC;
SIGNAL wire_nil0O_dataout : STD_LOGIC;
SIGNAL wire_nil1i_dataout : STD_LOGIC;
SIGNAL wire_nil1l_dataout : STD_LOGIC;
SIGNAL wire_nil1O_dataout : STD_LOGIC;
SIGNAL wire_nilii_dataout : STD_LOGIC;
SIGNAL wire_nilil_dataout : STD_LOGIC;
SIGNAL wire_niliO_dataout : STD_LOGIC;
SIGNAL wire_nilli_dataout : STD_LOGIC;
SIGNAL wire_nilll_dataout : STD_LOGIC;
SIGNAL wire_nillO_dataout : STD_LOGIC;
SIGNAL wire_nilOi_dataout : STD_LOGIC;
SIGNAL wire_nilOl_dataout : STD_LOGIC;
SIGNAL wire_nilOO_dataout : STD_LOGIC;
SIGNAL wire_niO0i_dataout : STD_LOGIC;
SIGNAL wire_niO0l_dataout : STD_LOGIC;
SIGNAL wire_niO0O_dataout : STD_LOGIC;
SIGNAL wire_niO1i_dataout : STD_LOGIC;
SIGNAL wire_niO1l_dataout : STD_LOGIC;
SIGNAL wire_niO1O_dataout : STD_LOGIC;
SIGNAL wire_niOii_dataout : STD_LOGIC;
SIGNAL wire_niOil_dataout : STD_LOGIC;
SIGNAL wire_niOiO_dataout : STD_LOGIC;
SIGNAL wire_niOli_dataout : STD_LOGIC;
SIGNAL wire_niOll_dataout : STD_LOGIC;
SIGNAL wire_niOlO_dataout : STD_LOGIC;
SIGNAL wire_niOOi_dataout : STD_LOGIC;
SIGNAL wire_nl00i_dataout : STD_LOGIC;
SIGNAL wire_nl00l_dataout : STD_LOGIC;
SIGNAL wire_nl01i_dataout : STD_LOGIC;
SIGNAL wire_nl01l_dataout : STD_LOGIC;
SIGNAL wire_nl10i_dataout : STD_LOGIC;
SIGNAL wire_nl10l_dataout : STD_LOGIC;
SIGNAL wire_nl10O_dataout : STD_LOGIC;
SIGNAL wire_nl11l_dataout : STD_LOGIC;
SIGNAL wire_nl1ii_dataout : STD_LOGIC;
SIGNAL wire_nl1il_dataout : STD_LOGIC;
SIGNAL wire_nl1iO_dataout : STD_LOGIC;
SIGNAL wire_nl1li_dataout : STD_LOGIC;
SIGNAL wire_nl1ll_dataout : STD_LOGIC;
SIGNAL wire_nl1lO_dataout : STD_LOGIC;
SIGNAL wire_nl1Oi_dataout : STD_LOGIC;
SIGNAL wire_nl1Ol_dataout : STD_LOGIC;
SIGNAL wire_nl1OO_dataout : STD_LOGIC;
SIGNAL wire_nliil_dataout : STD_LOGIC;
SIGNAL wire_nliiO_dataout : STD_LOGIC;
SIGNAL wire_nlili_dataout : STD_LOGIC;
SIGNAL wire_nlill_dataout : STD_LOGIC;
SIGNAL wire_nlilO_dataout : STD_LOGIC;
SIGNAL wire_nliOi_dataout : STD_LOGIC;
SIGNAL wire_nliOl_dataout : STD_LOGIC;
SIGNAL wire_nliOO_dataout : STD_LOGIC;
SIGNAL wire_nll00i_dataout : STD_LOGIC;
SIGNAL wire_nll00l_dataout : STD_LOGIC;
SIGNAL wire_nll00O_dataout : STD_LOGIC;
SIGNAL wire_nll01l_dataout : STD_LOGIC;
SIGNAL wire_nll01O_dataout : STD_LOGIC;
SIGNAL wire_nll0ii_dataout : STD_LOGIC;
SIGNAL wire_nll0il_dataout : STD_LOGIC;
SIGNAL wire_nll0iO_dataout : STD_LOGIC;
SIGNAL wire_nll0li_dataout : STD_LOGIC;
SIGNAL wire_nll1i_dataout : STD_LOGIC;
SIGNAL wire_nll1l_dataout : STD_LOGIC;
SIGNAL wire_nlli0l_dataout : STD_LOGIC;
SIGNAL wire_nlli0O_dataout : STD_LOGIC;
SIGNAL wire_nlliii_dataout : STD_LOGIC;
SIGNAL wire_nlliil_dataout : STD_LOGIC;
SIGNAL wire_nlliiO_dataout : STD_LOGIC;
SIGNAL wire_nllili_dataout : STD_LOGIC;
SIGNAL wire_nllill_dataout : STD_LOGIC;
SIGNAL wire_nllilO_dataout : STD_LOGIC;
SIGNAL wire_nlliOi_dataout : STD_LOGIC;
SIGNAL wire_nlliOl_dataout : STD_LOGIC;
SIGNAL wire_nlliOO_dataout : STD_LOGIC;
SIGNAL wire_nlll0i_dataout : STD_LOGIC;
SIGNAL wire_nlll0l_dataout : STD_LOGIC;
SIGNAL wire_nlll0O_dataout : STD_LOGIC;
SIGNAL wire_nlll1i_dataout : STD_LOGIC;
SIGNAL wire_nlll1l_dataout : STD_LOGIC;
SIGNAL wire_nlll1O_dataout : STD_LOGIC;
SIGNAL wire_nlllii_dataout : STD_LOGIC;
SIGNAL wire_nlllil_dataout : STD_LOGIC;
SIGNAL wire_nllliO_dataout : STD_LOGIC;
SIGNAL wire_nlllli_dataout : STD_LOGIC;
SIGNAL wire_nlllll_dataout : STD_LOGIC;
SIGNAL wire_nllllO_dataout : STD_LOGIC;
SIGNAL wire_nlllOi_dataout : STD_LOGIC;
SIGNAL wire_nlllOl_dataout : STD_LOGIC;
SIGNAL wire_nlllOO_dataout : STD_LOGIC;
SIGNAL wire_nllO0l_dataout : STD_LOGIC;
SIGNAL wire_nllO0O_dataout : STD_LOGIC;
SIGNAL wire_nllO1i_dataout : STD_LOGIC;
SIGNAL wire_nllOii_dataout : STD_LOGIC;
SIGNAL wire_nllOil_dataout : STD_LOGIC;
SIGNAL wire_nllOiO_dataout : STD_LOGIC;
SIGNAL wire_nllOli_dataout : STD_LOGIC;
SIGNAL wire_nllOll_dataout : STD_LOGIC;
SIGNAL wire_nllOlO_dataout : STD_LOGIC;
SIGNAL wire_nllOOi_dataout : STD_LOGIC;
SIGNAL wire_nllOOl_dataout : STD_LOGIC;
SIGNAL wire_nllOOO_dataout : STD_LOGIC;
SIGNAL wire_nlO00i_dataout : STD_LOGIC;
SIGNAL wire_nlO00l_dataout : STD_LOGIC;
SIGNAL wire_nlO01i_dataout : STD_LOGIC;
SIGNAL wire_nlO01l_dataout : STD_LOGIC;
SIGNAL wire_nlO01O_dataout : STD_LOGIC;
SIGNAL wire_nlO0ii_dataout : STD_LOGIC;
SIGNAL wire_nlO0il_dataout : STD_LOGIC;
SIGNAL wire_nlO0iO_dataout : STD_LOGIC;
SIGNAL wire_nlO0li_dataout : STD_LOGIC;
SIGNAL wire_nlO0ll_dataout : STD_LOGIC;
SIGNAL wire_nlO0lO_dataout : STD_LOGIC;
SIGNAL wire_nlO0Oi_dataout : STD_LOGIC;
SIGNAL wire_nlO0Ol_dataout : STD_LOGIC;
SIGNAL wire_nlO0OO_dataout : STD_LOGIC;
SIGNAL wire_nlO10i_dataout : STD_LOGIC;
SIGNAL wire_nlO10l_dataout : STD_LOGIC;
SIGNAL wire_nlO10O_dataout : STD_LOGIC;
SIGNAL wire_nlO11i_dataout : STD_LOGIC;
SIGNAL wire_nlO11l_dataout : STD_LOGIC;
SIGNAL wire_nlO11O_dataout : STD_LOGIC;
SIGNAL wire_nlO1ii_dataout : STD_LOGIC;
SIGNAL wire_nlO1il_dataout : STD_LOGIC;
SIGNAL wire_nlO1iO_dataout : STD_LOGIC;
SIGNAL wire_nlO1li_dataout : STD_LOGIC;
SIGNAL wire_nlO1ll_dataout : STD_LOGIC;
SIGNAL wire_nlO1lO_dataout : STD_LOGIC;
SIGNAL wire_nlO1Oi_dataout : STD_LOGIC;
SIGNAL wire_nlO1Ol_dataout : STD_LOGIC;
SIGNAL wire_nlO1OO_dataout : STD_LOGIC;
SIGNAL wire_nlOili_dataout : STD_LOGIC;
SIGNAL wire_nlOill_dataout : STD_LOGIC;
SIGNAL wire_nlOilO_dataout : STD_LOGIC;
SIGNAL wire_nlOiOi_dataout : STD_LOGIC;
SIGNAL wire_nlOiOl_dataout : STD_LOGIC;
SIGNAL wire_nlOiOO_dataout : STD_LOGIC;
SIGNAL wire_nlOl1i_dataout : STD_LOGIC;
SIGNAL wire_nlOl1l_dataout : STD_LOGIC;
SIGNAL wire_nlOl1O_dataout : STD_LOGIC;
SIGNAL wire_nlOlOi_dataout : STD_LOGIC;
SIGNAL wire_nlOlOl_dataout : STD_LOGIC;
SIGNAL wire_nlOlOO_dataout : STD_LOGIC;
SIGNAL wire_nlOO0i_dataout : STD_LOGIC;
SIGNAL wire_nlOO0l_dataout : STD_LOGIC;
SIGNAL wire_nlOO0O_dataout : STD_LOGIC;
SIGNAL wire_nlOO1i_dataout : STD_LOGIC;
SIGNAL wire_nlOO1l_dataout : STD_LOGIC;
SIGNAL wire_nlOO1O_dataout : STD_LOGIC;
SIGNAL wire_nlOOii_dataout : STD_LOGIC;
SIGNAL wire_nlOOil_dataout : STD_LOGIC;
SIGNAL wire_nlOOiO_dataout : STD_LOGIC;
SIGNAL wire_nlOOli_dataout : STD_LOGIC;
SIGNAL wire_nlOOll_dataout : STD_LOGIC;
SIGNAL wire_nlOOlO_dataout : STD_LOGIC;
SIGNAL wire_nlOOOi_dataout : STD_LOGIC;
SIGNAL wire_nlOOOl_dataout : STD_LOGIC;
SIGNAL wire_nlOOOO_dataout : STD_LOGIC;
SIGNAL wire_nll1O_a : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_nll1O_b : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_nll1O_o : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_nl11O_i : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl11O_o : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nl0OO_a : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl0OO_b : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl0OO_o : STD_LOGIC;
SIGNAL wire_n1O0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1O0O_o : STD_LOGIC;
SIGNAL wire_n1O0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1Oii_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1Oii_o : STD_LOGIC;
SIGNAL wire_n1Oii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1Oil_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1Oil_o : STD_LOGIC;
SIGNAL wire_n1Oil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1OiO_o : STD_LOGIC;
SIGNAL wire_n1OiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1Oli_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1Oli_o : STD_LOGIC;
SIGNAL wire_n1Oli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1Oll_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1Oll_o : STD_LOGIC;
SIGNAL wire_n1Oll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1OlO_o : STD_LOGIC;
SIGNAL wire_n1OlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1OOi_o : STD_LOGIC;
SIGNAL wire_n1OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n1OOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_n1OOl_o : STD_LOGIC;
SIGNAL wire_n1OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni01i_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni01i_o : STD_LOGIC;
SIGNAL wire_ni01i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni01l_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni01l_o : STD_LOGIC;
SIGNAL wire_ni01l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni01O_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni01O_o : STD_LOGIC;
SIGNAL wire_ni01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1li_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1li_o : STD_LOGIC;
SIGNAL wire_ni1li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1ll_o : STD_LOGIC;
SIGNAL wire_ni1ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1lO_o : STD_LOGIC;
SIGNAL wire_ni1lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1Oi_o : STD_LOGIC;
SIGNAL wire_ni1Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1Ol_o : STD_LOGIC;
SIGNAL wire_ni1Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ni1OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_ni1OO_o : STD_LOGIC;
SIGNAL wire_ni1OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_niOOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_niOOl_o : STD_LOGIC;
SIGNAL wire_niOOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_niOOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_niOOO_o : STD_LOGIC;
SIGNAL wire_niOOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nl11i_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nl11i_o : STD_LOGIC;
SIGNAL wire_nl11i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nll0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nll0ll_o : STD_LOGIC;
SIGNAL wire_nll0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nll0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nll0lO_o : STD_LOGIC;
SIGNAL wire_nll0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nll0Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nll0Oi_o : STD_LOGIC;
SIGNAL wire_nll0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nll0Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nll0Ol_o : STD_LOGIC;
SIGNAL wire_nll0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nll0OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nll0OO_o : STD_LOGIC;
SIGNAL wire_nll0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlli0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlli0i_o : STD_LOGIC;
SIGNAL wire_nlli0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlli1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlli1i_o : STD_LOGIC;
SIGNAL wire_nlli1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlli1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlli1l_o : STD_LOGIC;
SIGNAL wire_nlli1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlli1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlli1O_o : STD_LOGIC;
SIGNAL wire_nlli1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOl0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOl0i_o : STD_LOGIC;
SIGNAL wire_nlOl0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOl0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOl0l_o : STD_LOGIC;
SIGNAL wire_nlOl0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOl0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOl0O_o : STD_LOGIC;
SIGNAL wire_nlOl0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOlii_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOlii_o : STD_LOGIC;
SIGNAL wire_nlOlii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOlil_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOlil_o : STD_LOGIC;
SIGNAL wire_nlOlil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOliO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOliO_o : STD_LOGIC;
SIGNAL wire_nlOliO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOlli_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOlli_o : STD_LOGIC;
SIGNAL wire_nlOlli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOlll_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOlll_o : STD_LOGIC;
SIGNAL wire_nlOlll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_nlOllO_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_nlOllO_o : STD_LOGIC;
SIGNAL wire_nlOllO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_txctrl_range35w139w140w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_txctrl_range35w139w140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rdenablesync266w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nl11il273w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl11ll270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl11ll210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rdenablesync269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range1w149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range35w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range35w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range63w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range94w96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range208w1612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range192w1626w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range184w1759w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range200w1619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl000i21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl001l25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl001O23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl00ii16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl00il14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl00ll9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl00lO7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl010O43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl011i52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl011l50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl011O48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl01ii41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl01li36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl01Ol30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl0i1l2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl101i1196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl10Oi1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl110i277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl111l276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl11il209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1i0i124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1i1O126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1iii119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1iil117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1ill112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1iOl107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1l0O95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1l1l102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1l1O100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1lil92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1liO90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1llO85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1lOO80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1O0O69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1O1i78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1O1l76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1O1O74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1OiO64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1Oll61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1OlO59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl1OOO54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rdenablesync266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_resetall156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txctrl_range35w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range191w1566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range207w1611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range180w1575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_txdatain_range199w1557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_rdenablesync266w267w268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nl11il273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL niOOOi : STD_LOGIC;
SIGNAL niOOOl : STD_LOGIC;
SIGNAL nl000i : STD_LOGIC;
SIGNAL nl001l : STD_LOGIC;
SIGNAL nl001O : STD_LOGIC;
SIGNAL nl00ii : STD_LOGIC;
SIGNAL nl00il : STD_LOGIC;
SIGNAL nl00ll : STD_LOGIC;
SIGNAL nl00lO : STD_LOGIC;
SIGNAL nl010O : STD_LOGIC;
SIGNAL nl011i : STD_LOGIC;
SIGNAL nl011l : STD_LOGIC;
SIGNAL nl011O : STD_LOGIC;
SIGNAL nl01ii : STD_LOGIC;
SIGNAL nl01li : STD_LOGIC;
SIGNAL nl01ll : STD_LOGIC;
SIGNAL nl01Ol : STD_LOGIC;
SIGNAL nl0i1l : STD_LOGIC;
SIGNAL nl100i : STD_LOGIC;
SIGNAL nl100l : STD_LOGIC;
SIGNAL nl101i : STD_LOGIC;
SIGNAL nl101l : STD_LOGIC;
SIGNAL nl101O : STD_LOGIC;
SIGNAL nl10il : STD_LOGIC;
SIGNAL nl10iO : STD_LOGIC;
SIGNAL nl10li : STD_LOGIC;
SIGNAL nl10Oi : STD_LOGIC;
SIGNAL nl10Ol : STD_LOGIC;
SIGNAL nl10OO : STD_LOGIC;
SIGNAL nl110i : STD_LOGIC;
SIGNAL nl110l : STD_LOGIC;
SIGNAL nl110O : STD_LOGIC;
SIGNAL nl111l : STD_LOGIC;
SIGNAL nl111O : STD_LOGIC;
SIGNAL nl11ii : STD_LOGIC;
SIGNAL nl11il : STD_LOGIC;
SIGNAL nl11ll : STD_LOGIC;
SIGNAL nl11Ol : STD_LOGIC;
SIGNAL nl1i0i : STD_LOGIC;
SIGNAL nl1i1O : STD_LOGIC;
SIGNAL nl1iii : STD_LOGIC;
SIGNAL nl1iil : STD_LOGIC;
SIGNAL nl1ill : STD_LOGIC;
SIGNAL nl1iOl : STD_LOGIC;
SIGNAL nl1l0O : STD_LOGIC;
SIGNAL nl1l1l : STD_LOGIC;
SIGNAL nl1l1O : STD_LOGIC;
SIGNAL nl1lii : STD_LOGIC;
SIGNAL nl1lil : STD_LOGIC;
SIGNAL nl1liO : STD_LOGIC;
SIGNAL nl1llO : STD_LOGIC;
SIGNAL nl1lOO : STD_LOGIC;
SIGNAL nl1O0O : STD_LOGIC;
SIGNAL nl1O1i : STD_LOGIC;
SIGNAL nl1O1l : STD_LOGIC;
SIGNAL nl1O1O : STD_LOGIC;
SIGNAL nl1OiO : STD_LOGIC;
SIGNAL nl1Oli : STD_LOGIC;
SIGNAL nl1Oll : STD_LOGIC;
SIGNAL nl1OlO : STD_LOGIC;
SIGNAL nl1OOO : STD_LOGIC;
SIGNAL wire_w_txctrl_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txctrl_range35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txctrl_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txctrl_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_txdatain_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_gnd <= '0';
wire_w_lg_w_lg_w_lg_w_txctrl_range35w139w140w141w(0) <= wire_w_lg_w_lg_w_txctrl_range35w139w140w(0) AND nl10il;
wire_w_lg_w_lg_w_txctrl_range35w139w140w(0) <= wire_w_lg_w_txctrl_range35w139w(0) AND wire_w_txctrl_range94w(0);
wire_w_lg_w_lg_rdenablesync266w267w(0) <= wire_w_lg_rdenablesync266w(0) AND nl111O;
wire_w_lg_w_lg_nl11il273w274w(0) <= wire_w_lg_nl11il273w(0) AND nl110l;
wire_w_lg_nl11ll270w(0) <= nl11ll AND wire_w_lg_rdenablesync269w(0);
wire_w_lg_nl11ll210w(0) <= nl11ll AND wire_w_lg_nl11il209w(0);
wire_w_lg_rdenablesync269w(0) <= rdenablesync AND nl111O;
wire_w_lg_w_txctrl_range1w3w(0) <= wire_w_txctrl_range1w(0) AND wire_w_lg_nl0i1l2w(0);
wire_w_lg_w_txctrl_range1w149w(0) <= wire_w_txctrl_range1w(0) AND wire_w_lg_w_txctrl_range35w148w(0);
wire_w_lg_w_txctrl_range35w37w(0) <= wire_w_txctrl_range35w(0) AND wire_w_lg_nl01li36w(0);
wire_w_lg_w_txctrl_range35w139w(0) <= wire_w_txctrl_range35w(0) AND wire_w_txctrl_range63w(0);
wire_w_lg_w_txctrl_range63w65w(0) <= wire_w_txctrl_range63w(0) AND wire_w_lg_nl1OiO64w(0);
wire_w_lg_w_txctrl_range94w96w(0) <= wire_w_txctrl_range94w(0) AND wire_w_lg_nl1l0O95w(0);
wire_w_lg_w_txdatain_range208w1612w(0) <= wire_w_txdatain_range208w(0) AND wire_w_lg_w_txdatain_range207w1611w(0);
wire_w_lg_w_txdatain_range192w1626w(0) <= wire_w_txdatain_range192w(0) AND wire_w_lg_w_txdatain_range191w1566w(0);
wire_w_lg_w_txdatain_range184w1759w(0) <= wire_w_txdatain_range184w(0) AND wire_w_lg_w_txdatain_range180w1575w(0);
wire_w_lg_w_txdatain_range200w1619w(0) <= wire_w_txdatain_range200w(0) AND wire_w_lg_w_txdatain_range199w1557w(0);
wire_w_lg_nl000i21w(0) <= NOT nl000i;
wire_w_lg_nl001l25w(0) <= NOT nl001l;
wire_w_lg_nl001O23w(0) <= NOT nl001O;
wire_w_lg_nl00ii16w(0) <= NOT nl00ii;
wire_w_lg_nl00il14w(0) <= NOT nl00il;
wire_w_lg_nl00ll9w(0) <= NOT nl00ll;
wire_w_lg_nl00lO7w(0) <= NOT nl00lO;
wire_w_lg_nl010O43w(0) <= NOT nl010O;
wire_w_lg_nl011i52w(0) <= NOT nl011i;
wire_w_lg_nl011l50w(0) <= NOT nl011l;
wire_w_lg_nl011O48w(0) <= NOT nl011O;
wire_w_lg_nl01ii41w(0) <= NOT nl01ii;
wire_w_lg_nl01li36w(0) <= NOT nl01li;
wire_w_lg_nl01Ol30w(0) <= NOT nl01Ol;
wire_w_lg_nl0i1l2w(0) <= NOT nl0i1l;
wire_w_lg_nl101i1196w(0) <= NOT nl101i;
wire_w_lg_nl10Oi1195w(0) <= NOT nl10Oi;
wire_w_lg_nl110i277w(0) <= NOT nl110i;
wire_w_lg_nl111l276w(0) <= NOT nl111l;
wire_w_lg_nl11il209w(0) <= NOT nl11il;
wire_w_lg_nl1i0i124w(0) <= NOT nl1i0i;
wire_w_lg_nl1i1O126w(0) <= NOT nl1i1O;
wire_w_lg_nl1iii119w(0) <= NOT nl1iii;
wire_w_lg_nl1iil117w(0) <= NOT nl1iil;
wire_w_lg_nl1ill112w(0) <= NOT nl1ill;
wire_w_lg_nl1iOl107w(0) <= NOT nl1iOl;
wire_w_lg_nl1l0O95w(0) <= NOT nl1l0O;
wire_w_lg_nl1l1l102w(0) <= NOT nl1l1l;
wire_w_lg_nl1l1O100w(0) <= NOT nl1l1O;
wire_w_lg_nl1lil92w(0) <= NOT nl1lil;
wire_w_lg_nl1liO90w(0) <= NOT nl1liO;
wire_w_lg_nl1llO85w(0) <= NOT nl1llO;
wire_w_lg_nl1lOO80w(0) <= NOT nl1lOO;
wire_w_lg_nl1O0O69w(0) <= NOT nl1O0O;
wire_w_lg_nl1O1i78w(0) <= NOT nl1O1i;
wire_w_lg_nl1O1l76w(0) <= NOT nl1O1l;
wire_w_lg_nl1O1O74w(0) <= NOT nl1O1O;
wire_w_lg_nl1OiO64w(0) <= NOT nl1OiO;
wire_w_lg_nl1Oll61w(0) <= NOT nl1Oll;
wire_w_lg_nl1OlO59w(0) <= NOT nl1OlO;
wire_w_lg_nl1OOO54w(0) <= NOT nl1OOO;
wire_w_lg_rdenablesync266w(0) <= NOT rdenablesync;
wire_w_lg_resetall156w(0) <= NOT resetall;
wire_w_lg_w_txctrl_range35w148w(0) <= NOT wire_w_txctrl_range35w(0);
wire_w_lg_w_txdatain_range191w1566w(0) <= NOT wire_w_txdatain_range191w(0);
wire_w_lg_w_txdatain_range207w1611w(0) <= NOT wire_w_txdatain_range207w(0);
wire_w_lg_w_txdatain_range180w1575w(0) <= NOT wire_w_txdatain_range180w(0);
wire_w_lg_w_txdatain_range199w1557w(0) <= NOT wire_w_txdatain_range199w(0);
wire_w_lg_w_lg_w_lg_rdenablesync266w267w268w(0) <= wire_w_lg_w_lg_rdenablesync266w267w(0) OR wire_nl0OO_o;
wire_w_lg_nl11il273w(0) <= nl11il OR wire_n0Oi_w_lg_n0OOO272w(0);
niOOOi <= (nl101O OR niOOOl);
niOOOl <= (nl10iO OR nl100l);
nl000i <= ((((((((NOT txdatain(0)) AND wire_w_lg_w_txdatain_range207w1611w(0)) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND (NOT txdatain(5))) AND txdatain(6)) AND (NOT txdatain(7)));
nl001l <= ((((((((NOT txdatain(0)) AND wire_w_lg_w_txdatain_range207w1611w(0)) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND txdatain(5)) AND txdatain(6)) AND txdatain(7));
nl001O <= ((((((((NOT txdatain(0)) AND wire_w_lg_w_txdatain_range207w1611w(0)) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND (NOT txdatain(5))) AND txdatain(6)) AND txdatain(7));
nl00ii <= ((((((((NOT txdatain(0)) AND wire_w_lg_w_txdatain_range207w1611w(0)) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND txdatain(5)) AND (NOT txdatain(6))) AND (NOT txdatain(7)));
nl00il <= ((((((wire_w_lg_w_txdatain_range208w1612w(0) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND txdatain(5)) AND txdatain(6)) AND txdatain(7));
nl00ll <= (((((((txdatain(0) AND txdatain(1)) AND (NOT txdatain(2))) AND txdatain(3)) AND txdatain(4)) AND txdatain(5)) AND txdatain(6)) AND txdatain(7));
nl00lO <= ((((((((NOT txdatain(0)) AND wire_w_lg_w_txdatain_range207w1611w(0)) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND (NOT txdatain(5))) AND (NOT txdatain(6))) AND txdatain(7));
nl010O <= (((((((txdatain(8) AND txdatain(9)) AND (NOT txdatain(10))) AND txdatain(11)) AND txdatain(12)) AND txdatain(13)) AND txdatain(14)) AND txdatain(15));
nl011i <= ((((((((NOT txdatain(8)) AND wire_w_lg_w_txdatain_range199w1557w(0)) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND (NOT txdatain(13))) AND txdatain(14)) AND (NOT txdatain(15)));
nl011l <= ((((((((NOT txdatain(8)) AND wire_w_lg_w_txdatain_range199w1557w(0)) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND txdatain(13)) AND (NOT txdatain(14))) AND (NOT txdatain(15)));
nl011O <= ((((((wire_w_lg_w_txdatain_range200w1619w(0) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND txdatain(13)) AND txdatain(14)) AND txdatain(15));
nl01ii <= ((((((((NOT txdatain(8)) AND wire_w_lg_w_txdatain_range199w1557w(0)) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND (NOT txdatain(13))) AND (NOT txdatain(14))) AND txdatain(15));
nl01li <= (((((((txdatain(8) AND txdatain(9)) AND txdatain(10)) AND (NOT txdatain(11))) AND (NOT txdatain(12))) AND (NOT txdatain(13))) AND (NOT txdatain(14))) AND (NOT txdatain(15)));
nl01ll <= (((((((((((((wire_w_lg_w_txctrl_range1w3w(0) AND (nl00Oi2 XOR nl00Oi1)) AND wire_w_lg_nl00lO7w(0)) AND wire_w_lg_nl00ll9w(0)) AND (nl00iO4 XOR nl00iO3)) AND wire_w_lg_nl00il14w(0)) AND wire_w_lg_nl00ii16w(0)) AND (nl000l6 XOR nl000l5)) AND wire_w_lg_nl000i21w(0)) AND wire_w_lg_nl001O23w(0)) AND wire_w_lg_nl001l25w(0)) AND (nl01OO8 XOR nl01OO7)) AND wire_w_lg_nl01Ol30w(0)) AND (nl01lO10 XOR nl01lO9));
nl01Ol <= (((((((txdatain(0) AND txdatain(1)) AND txdatain(2)) AND (NOT txdatain(3))) AND txdatain(4)) AND txdatain(5)) AND txdatain(6)) AND txdatain(7));
nl0i1l <= (((((((txdatain(0) AND txdatain(1)) AND txdatain(2)) AND (NOT txdatain(3))) AND (NOT txdatain(4))) AND (NOT txdatain(5))) AND (NOT txdatain(6))) AND (NOT txdatain(7)));
nl100i <= ((((((((((((((wire_w_lg_w_txdatain_range192w1626w(0) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND txdatain(21)) AND txdatain(22)) AND txdatain(23)) AND txdatain(24)) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND (NOT txdatain(28))) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl100l <= (wire_w_lg_w_lg_w_lg_w_txctrl_range35w139w140w141w(0) AND (nl100O40 XOR nl100O39));
nl101i <= (((wire_w_lg_w_txctrl_range1w149w(0) AND (NOT txctrl(2))) AND (NOT txctrl(3))) AND nl00lO);
nl101l <= (txctrl(3) AND nl1iOl);
nl101O <= ((txctrl(2) AND txctrl(3)) AND nl100i);
nl10il <= ((((((((((((((((((((((wire_w_lg_w_txdatain_range200w1619w(0) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND txdatain(13)) AND txdatain(14)) AND txdatain(15)) AND txdatain(16)) AND txdatain(17)) AND txdatain(18)) AND (NOT txdatain(19))) AND (NOT txdatain(20))) AND (NOT txdatain(21))) AND (NOT txdatain(22))) AND (NOT txdatain(23))) AND txdatain(24)) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND (NOT txdatain(28))) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl10iO <= (((((txctrl(0) AND txctrl(1)) AND txctrl(2)) AND txctrl(3)) AND (nl10ll38 XOR nl10ll37)) AND nl10li);
nl10li <= ((((((((((((((((((((((((((((((wire_w_lg_w_txdatain_range208w1612w(0) AND txdatain(2)) AND txdatain(3)) AND txdatain(4)) AND txdatain(5)) AND txdatain(6)) AND txdatain(7)) AND txdatain(8)) AND txdatain(9)) AND txdatain(10)) AND (NOT txdatain(11))) AND (NOT txdatain(12))) AND (NOT txdatain(13))) AND (NOT txdatain(14))) AND (NOT txdatain(15))) AND txdatain(16)) AND txdatain(17)) AND txdatain(18)) AND (NOT txdatain(19))) AND (NOT txdatain(20))) AND (NOT txdatain(21))) AND (NOT txdatain(22))) AND (NOT txdatain(23))) AND txdatain(24)) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND (NOT txdatain(28))) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl10Oi <= ((((txctrl(0) AND txctrl(1)) AND txctrl(2)) AND txctrl(3)) AND nl10Ol);
nl10Ol <= (((((((((((((((((((((((((((((((txdatain(0) AND txdatain(1)) AND txdatain(2)) AND (NOT txdatain(3))) AND (NOT txdatain(4))) AND (NOT txdatain(5))) AND (NOT txdatain(6))) AND (NOT txdatain(7))) AND txdatain(8)) AND txdatain(9)) AND txdatain(10)) AND (NOT txdatain(11))) AND (NOT txdatain(12))) AND (NOT txdatain(13))) AND (NOT txdatain(14))) AND (NOT txdatain(15))) AND txdatain(16)) AND txdatain(17)) AND txdatain(18)) AND (NOT txdatain(19))) AND (NOT txdatain(20))) AND (NOT txdatain(21))) AND (NOT txdatain(22))) AND (NOT txdatain(23))) AND txdatain(24)) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND (NOT txdatain(28))) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl10OO <= ((((((((((((((wire_w_lg_w_txctrl_range94w96w(0) AND (nl1l0i26 XOR nl1l0i25)) AND wire_w_lg_nl1l1O100w(0)) AND wire_w_lg_nl1l1l102w(0)) AND (nl1iOO28 XOR nl1iOO27)) AND wire_w_lg_nl1iOl107w(0)) AND (nl1ilO30 XOR nl1ilO29)) AND wire_w_lg_nl1ill112w(0)) AND (nl1iiO32 XOR nl1iiO31)) AND wire_w_lg_nl1iil117w(0)) AND wire_w_lg_nl1iii119w(0)) AND (nl1i0l34 XOR nl1i0l33)) AND wire_w_lg_nl1i0i124w(0)) AND wire_w_lg_nl1i1O126w(0)) AND (nl1i1i36 XOR nl1i1i35));
nl110i <= (wire_w_lg_nl11il209w(0) AND n0OOO);
nl110l <= (nl11ll AND nl11ii);
nl110O <= (wire_w_lg_nl11ll210w(0) AND (((wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w169w(0) AND wire_n0Oi_w_lg_n00O166w(0)) OR wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w213w214w(0)) OR (n0OOO AND nl11ii)));
nl111l <= (wire_w_lg_nl10Oi1195w(0) AND wire_w_lg_nl101i1196w(0));
nl111O <= (wire_ni1i_w_lg_w_lg_w_lg_ni1l162w164w165w(0) AND n00O);
nl11ii <= ((wire_ni1i_w_lg_w_lg_ni1l162w164w(0) AND wire_n0Oi_w_lg_n0Ol212w(0)) AND n00O);
nl11il <= ((((nli0O OR nli0l) OR nli0i) OR nli1O) OR nl01O);
nl11ll <= (nl10Oi OR nl101i);
nl11Ol <= '1';
nl1i0i <= ((((((((NOT txdatain(24)) AND wire_w_lg_w_txdatain_range180w1575w(0)) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND txdatain(29)) AND txdatain(30)) AND txdatain(31));
nl1i1O <= (((((((txdatain(24) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND txdatain(28)) AND txdatain(29)) AND txdatain(30)) AND txdatain(31));
nl1iii <= ((((((((NOT txdatain(24)) AND wire_w_lg_w_txdatain_range180w1575w(0)) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND (NOT txdatain(29))) AND txdatain(30)) AND txdatain(31));
nl1iil <= ((((((((NOT txdatain(24)) AND wire_w_lg_w_txdatain_range180w1575w(0)) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND (NOT txdatain(29))) AND txdatain(30)) AND (NOT txdatain(31)));
nl1ill <= ((((((((NOT txdatain(24)) AND wire_w_lg_w_txdatain_range180w1575w(0)) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND txdatain(29)) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl1iOl <= ((((((wire_w_lg_w_txdatain_range184w1759w(0) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND txdatain(29)) AND txdatain(30)) AND txdatain(31));
nl1l0O <= (((((((txdatain(24) AND txdatain(25)) AND txdatain(26)) AND (NOT txdatain(27))) AND (NOT txdatain(28))) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND (NOT txdatain(31)));
nl1l1l <= (((((((txdatain(24) AND txdatain(25)) AND (NOT txdatain(26))) AND txdatain(27)) AND txdatain(28)) AND txdatain(29)) AND txdatain(30)) AND txdatain(31));
nl1l1O <= ((((((((NOT txdatain(24)) AND wire_w_lg_w_txdatain_range180w1575w(0)) AND txdatain(26)) AND txdatain(27)) AND txdatain(28)) AND (NOT txdatain(29))) AND (NOT txdatain(30))) AND txdatain(31));
nl1lii <= ((((((((((((wire_w_lg_w_txctrl_range63w65w(0) AND (nl1Oii18 XOR nl1Oii17)) AND wire_w_lg_nl1O0O69w(0)) AND (nl1O0i20 XOR nl1O0i19)) AND wire_w_lg_nl1O1O74w(0)) AND wire_w_lg_nl1O1l76w(0)) AND wire_w_lg_nl1O1i78w(0)) AND wire_w_lg_nl1lOO80w(0)) AND (nl1lOi22 XOR nl1lOi21)) AND wire_w_lg_nl1llO85w(0)) AND (nl1lli24 XOR nl1lli23)) AND wire_w_lg_nl1liO90w(0)) AND wire_w_lg_nl1lil92w(0));
nl1lil <= (((((((txdatain(16) AND txdatain(17)) AND txdatain(18)) AND (NOT txdatain(19))) AND txdatain(20)) AND txdatain(21)) AND txdatain(22)) AND txdatain(23));
nl1liO <= ((((((((NOT txdatain(16)) AND wire_w_lg_w_txdatain_range191w1566w(0)) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND txdatain(21)) AND txdatain(22)) AND txdatain(23));
nl1llO <= ((((((((NOT txdatain(16)) AND wire_w_lg_w_txdatain_range191w1566w(0)) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND (NOT txdatain(21))) AND txdatain(22)) AND txdatain(23));
nl1lOO <= ((((((((NOT txdatain(16)) AND wire_w_lg_w_txdatain_range191w1566w(0)) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND (NOT txdatain(21))) AND txdatain(22)) AND (NOT txdatain(23)));
nl1O0O <= ((((((((NOT txdatain(16)) AND wire_w_lg_w_txdatain_range191w1566w(0)) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND (NOT txdatain(21))) AND (NOT txdatain(22))) AND txdatain(23));
nl1O1i <= ((((((((NOT txdatain(16)) AND wire_w_lg_w_txdatain_range191w1566w(0)) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND txdatain(21)) AND (NOT txdatain(22))) AND (NOT txdatain(23)));
nl1O1l <= ((((((wire_w_lg_w_txdatain_range192w1626w(0) AND txdatain(18)) AND txdatain(19)) AND txdatain(20)) AND txdatain(21)) AND txdatain(22)) AND txdatain(23));
nl1O1O <= (((((((txdatain(16) AND txdatain(17)) AND (NOT txdatain(18))) AND txdatain(19)) AND txdatain(20)) AND txdatain(21)) AND txdatain(22)) AND txdatain(23));
nl1OiO <= (((((((txdatain(16) AND txdatain(17)) AND txdatain(18)) AND (NOT txdatain(19))) AND (NOT txdatain(20))) AND (NOT txdatain(21))) AND (NOT txdatain(22))) AND (NOT txdatain(23)));
nl1Oli <= (((((((((((wire_w_lg_w_txctrl_range35w37w(0) AND (nl01il12 XOR nl01il11)) AND wire_w_lg_nl01ii41w(0)) AND wire_w_lg_nl010O43w(0)) AND (nl010i14 XOR nl010i13)) AND wire_w_lg_nl011O48w(0)) AND wire_w_lg_nl011l50w(0)) AND wire_w_lg_nl011i52w(0)) AND wire_w_lg_nl1OOO54w(0)) AND (nl1OOi16 XOR nl1OOi15)) AND wire_w_lg_nl1OlO59w(0)) AND wire_w_lg_nl1Oll61w(0));
nl1Oll <= (((((((txdatain(8) AND txdatain(9)) AND txdatain(10)) AND (NOT txdatain(11))) AND txdatain(12)) AND txdatain(13)) AND txdatain(14)) AND txdatain(15));
nl1OlO <= ((((((((NOT txdatain(8)) AND wire_w_lg_w_txdatain_range199w1557w(0)) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND txdatain(13)) AND txdatain(14)) AND txdatain(15));
nl1OOO <= ((((((((NOT txdatain(8)) AND wire_w_lg_w_txdatain_range199w1557w(0)) AND txdatain(10)) AND txdatain(11)) AND txdatain(12)) AND (NOT txdatain(13))) AND txdatain(14)) AND txdatain(15));
txctrlout <= ( n1OOO & nll01i & nlOiiO & n1lll);
txdataout <= ( nll1OO & nll1Ol & nll1Oi & nll1lO & nll1ll & nll1li & nll1iO & nll1il & nlOiil & nlOiii & nlOi0O & nlOi0l & nlOi0i & nlOi1O & nlOi1l & nlOi1i & n1lli & n1liO & n1lil & n1lii & n1l0O & n1l0l & n1l0i & n1l1O & n0OOl & n0OlO & n0Oll & n0Oli & n0OiO & n0Oil & n0Oii & n0O0O);
wire_w_txctrl_range1w(0) <= txctrl(0);
wire_w_txctrl_range35w(0) <= txctrl(1);
wire_w_txctrl_range63w(0) <= txctrl(2);
wire_w_txctrl_range94w(0) <= txctrl(3);
wire_w_txdatain_range208w(0) <= txdatain(0);
wire_w_txdatain_range192w(0) <= txdatain(16);
wire_w_txdatain_range191w(0) <= txdatain(17);
wire_w_txdatain_range207w(0) <= txdatain(1);
wire_w_txdatain_range184w(0) <= txdatain(24);
wire_w_txdatain_range180w(0) <= txdatain(25);
wire_w_txdatain_range200w(0) <= txdatain(8);
wire_w_txdatain_range199w(0) <= txdatain(9);
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN niOOOO53 <= niOOOO54;
END IF;
if (now = 0 ns) then
niOOOO53 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN niOOOO54 <= niOOOO53;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl000l5 <= nl000l6;
END IF;
if (now = 0 ns) then
nl000l5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl000l6 <= nl000l5;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl00iO3 <= nl00iO4;
END IF;
if (now = 0 ns) then
nl00iO3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl00iO4 <= nl00iO3;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl00Oi1 <= nl00Oi2;
END IF;
if (now = 0 ns) then
nl00Oi1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl00Oi2 <= nl00Oi1;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl010i13 <= nl010i14;
END IF;
if (now = 0 ns) then
nl010i13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl010i14 <= nl010i13;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01il11 <= nl01il12;
END IF;
if (now = 0 ns) then
nl01il11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01il12 <= nl01il11;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01lO10 <= nl01lO9;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01lO9 <= nl01lO10;
END IF;
if (now = 0 ns) then
nl01lO9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01OO7 <= nl01OO8;
END IF;
if (now = 0 ns) then
nl01OO7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl01OO8 <= nl01OO7;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl100O39 <= nl100O40;
END IF;
if (now = 0 ns) then
nl100O39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl100O40 <= nl100O39;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl10ll37 <= nl10ll38;
END IF;
if (now = 0 ns) then
nl10ll37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl10ll38 <= nl10ll37;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl111i51 <= nl111i52;
END IF;
if (now = 0 ns) then
nl111i51 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl111i52 <= nl111i51;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11iO49 <= nl11iO50;
END IF;
if (now = 0 ns) then
nl11iO49 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11iO50 <= nl11iO49;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11li47 <= nl11li48;
END IF;
if (now = 0 ns) then
nl11li47 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11li48 <= nl11li47;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11lO45 <= nl11lO46;
END IF;
if (now = 0 ns) then
nl11lO45 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11lO46 <= nl11lO45;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11Oi43 <= nl11Oi44;
END IF;
if (now = 0 ns) then
nl11Oi43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11Oi44 <= nl11Oi43;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11OO41 <= nl11OO42;
END IF;
if (now = 0 ns) then
nl11OO41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl11OO42 <= nl11OO41;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1i0l33 <= nl1i0l34;
END IF;
if (now = 0 ns) then
nl1i0l33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1i0l34 <= nl1i0l33;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1i1i35 <= nl1i1i36;
END IF;
if (now = 0 ns) then
nl1i1i35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1i1i36 <= nl1i1i35;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1iiO31 <= nl1iiO32;
END IF;
if (now = 0 ns) then
nl1iiO31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1iiO32 <= nl1iiO31;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1ilO29 <= nl1ilO30;
END IF;
if (now = 0 ns) then
nl1ilO29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1ilO30 <= nl1ilO29;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1iOO27 <= nl1iOO28;
END IF;
if (now = 0 ns) then
nl1iOO27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1iOO28 <= nl1iOO27;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1l0i25 <= nl1l0i26;
END IF;
if (now = 0 ns) then
nl1l0i25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1l0i26 <= nl1l0i25;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1lli23 <= nl1lli24;
END IF;
if (now = 0 ns) then
nl1lli23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1lli24 <= nl1lli23;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1lOi21 <= nl1lOi22;
END IF;
if (now = 0 ns) then
nl1lOi21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1lOi22 <= nl1lOi21;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1O0i19 <= nl1O0i20;
END IF;
if (now = 0 ns) then
nl1O0i19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1O0i20 <= nl1O0i19;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1Oii17 <= nl1Oii18;
END IF;
if (now = 0 ns) then
nl1Oii17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1Oii18 <= nl1Oii17;
END IF;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1OOi15 <= nl1OOi16;
END IF;
if (now = 0 ns) then
nl1OOi15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (txclk)
BEGIN
IF (txclk = '1' AND txclk'event) THEN nl1OOi16 <= nl1OOi15;
END IF;
END PROCESS;
PROCESS (txclk, resetall)
BEGIN
IF (resetall = '1') THEN
n00i <= '0';
n01i <= '0';
n01l <= '0';
n10i <= '0';
n10l <= '0';
n10O <= '0';
n11i <= '0';
n11l <= '0';
n11O <= '0';
n1ii <= '0';
n1il <= '0';
n1iO <= '0';
n1li <= '0';
n1Oi <= '0';
n1Ol <= '0';
n1OO <= '0';
nllOO <= '0';
nlO0O <= '0';
nlO1l <= '0';
nlOii <= '0';
nlOiO <= '0';
nlOli <= '0';
nlOll <= '0';
nlOlO <= '0';
nlOOi <= '0';
nlOOl <= '0';
nlOOO <= '0';
ELSIF (txclk = '1' AND txclk'event) THEN
IF (nl101i = '1') THEN
n00i <= txdatain(31);
n01i <= txdatain(29);
n01l <= txdatain(30);
n10i <= txdatain(18);
n10l <= txdatain(19);
n10O <= txdatain(20);
n11i <= txdatain(15);
n11l <= txdatain(16);
n11O <= txdatain(17);
n1ii <= txdatain(21);
n1il <= txdatain(22);
n1iO <= txdatain(23);
n1li <= txdatain(24);
n1Oi <= txdatain(26);
n1Ol <= txdatain(27);
n1OO <= txdatain(28);
nllOO <= txdatain(0);
nlO0O <= txdatain(5);
nlO1l <= txdatain(1);
nlOii <= txdatain(6);
nlOiO <= txdatain(8);
nlOli <= txdatain(9);
nlOll <= txdatain(10);
nlOlO <= txdatain(11);
nlOOi <= txdatain(12);
nlOOl <= txdatain(13);
nlOOO <= txdatain(14);
END IF;
END IF;
END PROCESS;
PROCESS (txclk, wire_n0Oi_PRN, wire_n0Oi_CLRN)
BEGIN
IF (wire_n0Oi_PRN = '0') THEN
n00O <= '1';
n0Ol <= '1';
n0OOO <= '1';
nli0O <= '1';
nliii <= '1';
nlliO <= '1';
nllli <= '1';
nllll <= '1';
nlllO <= '1';
nllOi <= '1';
nllOl <= '1';
ELSIF (wire_n0Oi_CLRN = '0') THEN
n00O <= '0';
n0Ol <= '0';
n0OOO <= '0';
nli0O <= '0';
nliii <= '0';
nlliO <= '0';
nllli <= '0';
nllll <= '0';
nlllO <= '0';
nllOi <= '0';
nllOl <= '0';
ELSIF (txclk = '1' AND txclk'event) THEN
n00O <= wire_niOOl_o;
n0Ol <= wire_niOOO_o;
n0OOO <= wire_nl00i_dataout;
nli0O <= wire_nlilO_dataout;
nliii <= (nllOl XOR nllOi);
nlliO <= nliii;
nllli <= nlliO;
nllll <= nllli;
nlllO <= nllll;
nllOi <= nlllO;
nllOl <= nllOi;
END IF;
if (now = 0 ns) then
n00O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n0Ol <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n0OOO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nli0O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nliii <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlliO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nllli <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nllll <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlllO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nllOi <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nllOl <= '1' after 1 ps;
end if;
END PROCESS;
wire_n0Oi_CLRN <= (nl11Oi44 XOR nl11Oi43);
wire_n0Oi_PRN <= ((nl11lO46 XOR nl11lO45) AND wire_w_lg_resetall156w(0));
wire_n0Oi_w_lg_n00O166w(0) <= NOT n00O;
wire_n0Oi_w_lg_n0Ol212w(0) <= NOT n0Ol;
wire_n0Oi_w_lg_n0OOO272w(0) <= NOT n0OOO;
wire_n0Oi_w_lg_nliii279w(0) <= NOT nliii;
PROCESS (txclk, wire_n0OOi_PRN, wire_n0OOi_CLRN)
BEGIN
IF (wire_n0OOi_PRN = '0') THEN
n0Oil <= '1';
n0OiO <= '1';
n0Oli <= '1';
n0Oll <= '1';
n0OOl <= '1';
n1l0l <= '1';
n1l0O <= '1';
n1lii <= '1';
n1lil <= '1';
n1lli <= '1';
n1lll <= '1';
n1OOO <= '1';
nll01i <= '1';
nll1li <= '1';
nll1ll <= '1';
nll1lO <= '1';
nll1Oi <= '1';
nll1OO <= '1';
nlOi0i <= '1';
nlOi0l <= '1';
nlOi0O <= '1';
nlOi1O <= '1';
nlOiil <= '1';
nlOiiO <= '1';
ELSIF (wire_n0OOi_CLRN = '0') THEN
n0Oil <= '0';
n0OiO <= '0';
n0Oli <= '0';
n0Oll <= '0';
n0OOl <= '0';
n1l0l <= '0';
n1l0O <= '0';
n1lii <= '0';
n1lil <= '0';
n1lli <= '0';
n1lll <= '0';
n1OOO <= '0';
nll01i <= '0';
nll1li <= '0';
nll1ll <= '0';
nll1lO <= '0';
nll1Oi <= '0';
nll1OO <= '0';
nlOi0i <= '0';
nlOi0l <= '0';
nlOi0O <= '0';
nlOi1O <= '0';
nlOiil <= '0';
nlOiiO <= '0';
ELSIF (txclk = '1' AND txclk'event) THEN
n0Oil <= wire_ni10i_dataout;
n0OiO <= wire_ni10l_dataout;
n0Oli <= wire_ni10O_dataout;
n0Oll <= wire_ni1ii_dataout;
n0OOl <= wire_ni1iO_dataout;
n1l0l <= wire_n1lOO_dataout;
n1l0O <= wire_n1O1i_dataout;
n1lii <= wire_n1O1l_dataout;
n1lil <= wire_n1O1O_dataout;
n1lli <= wire_n1O0l_dataout;
n1lll <= wire_ni11i_dataout;
n1OOO <= wire_nll01l_dataout;
nll01i <= wire_nlOili_dataout;
nll1li <= wire_nll00l_dataout;
nll1ll <= wire_nll00O_dataout;
nll1lO <= wire_nll0ii_dataout;
nll1Oi <= wire_nll0il_dataout;
nll1OO <= wire_nll0li_dataout;
nlOi0i <= wire_nlOiOl_dataout;
nlOi0l <= wire_nlOiOO_dataout;
nlOi0O <= wire_nlOl1i_dataout;
nlOi1O <= wire_nlOiOi_dataout;
nlOiil <= wire_nlOl1O_dataout;
nlOiiO <= wire_n1llO_dataout;
END IF;
END PROCESS;
wire_n0OOi_CLRN <= (nl111i52 XOR nl111i51);
wire_n0OOi_PRN <= ((niOOOO54 XOR niOOOO53) AND wire_w_lg_resetall156w(0));
PROCESS (txclk, wire_n1ll_PRN, wire_n1ll_CLRN)
BEGIN
IF (wire_n1ll_PRN = '0') THEN
n1lO <= '1';
nlO0i <= '1';
nlO0l <= '1';
nlO1O <= '1';
nlOil <= '1';
ELSIF (wire_n1ll_CLRN = '0') THEN
n1lO <= '0';
nlO0i <= '0';
nlO0l <= '0';
nlO1O <= '0';
nlOil <= '0';
ELSIF (txclk = '1' AND txclk'event) THEN
IF (nl101i = '1') THEN
n1lO <= txdatain(25);
nlO0i <= txdatain(3);
nlO0l <= txdatain(4);
nlO1O <= txdatain(2);
nlOil <= txdatain(7);
END IF;
END IF;
if (now = 0 ns) then
n1lO <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlO0i <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlO0l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlO1O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOil <= '1' after 1 ps;
end if;
END PROCESS;
wire_n1ll_CLRN <= (nl11li48 XOR nl11li47);
wire_n1ll_PRN <= ((nl11iO50 XOR nl11iO49) AND wire_w_lg_resetall156w(0));
PROCESS (txclk, wire_ni1i_CLRN)
BEGIN
IF (wire_ni1i_CLRN = '0') THEN
n00l <= '0';
n0O0O <= '0';
n0Oii <= '0';
n0OlO <= '0';
n0OO <= '0';
n1l0i <= '0';
n1l1O <= '0';
n1liO <= '0';
ni1l <= '0';
nl01O <= '0';
nli0i <= '0';
nli0l <= '0';
nli1O <= '0';
nll1il <= '0';
nll1iO <= '0';
nll1Ol <= '0';
nlOi1i <= '0';
nlOi1l <= '0';
nlOiii <= '0';
ELSIF (txclk = '1' AND txclk'event) THEN
n00l <= wire_n0ii_dataout;
n0O0O <= wire_ni11l_dataout;
n0Oii <= wire_ni11O_dataout;
n0OlO <= wire_ni1il_dataout;
n0OO <= wire_nl11i_o;
n1l0i <= wire_n1lOl_dataout;
n1l1O <= wire_n1lOi_dataout;
n1liO <= wire_n1O0i_dataout;
ni1l <= wire_nl11l_dataout;
nl01O <= wire_nliil_dataout;
nli0i <= wire_nlili_dataout;
nli0l <= wire_nlill_dataout;
nli1O <= wire_nliiO_dataout;
nll1il <= wire_nll01O_dataout;
nll1iO <= wire_nll00i_dataout;
nll1Ol <= wire_nll0iO_dataout;
nlOi1i <= wire_nlOill_dataout;
nlOi1l <= wire_nlOilO_dataout;
nlOiii <= wire_nlOl1l_dataout;
END IF;
END PROCESS;
wire_ni1i_CLRN <= ((nl11OO42 XOR nl11OO41) AND wire_w_lg_resetall156w(0));
wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w213w214w(0) <= wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w213w(0) AND n00O;
wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w169w170w(0) <= wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w169w(0) AND n00O;
wire_ni1i_w_lg_w_lg_w_lg_ni1l162w164w165w(0) <= wire_ni1i_w_lg_w_lg_ni1l162w164w(0) AND n0Ol;
wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w213w(0) <= wire_ni1i_w_lg_w_lg_ni1l162w168w(0) AND wire_n0Oi_w_lg_n0Ol212w(0);
wire_ni1i_w_lg_w_lg_w_lg_ni1l162w168w169w(0) <= wire_ni1i_w_lg_w_lg_ni1l162w168w(0) AND n0Ol;
wire_ni1i_w_lg_w_lg_ni1l162w164w(0) <= wire_ni1i_w_lg_ni1l162w(0) AND wire_ni1i_w_lg_n0OO163w(0);
wire_ni1i_w_lg_w_lg_ni1l162w168w(0) <= wire_ni1i_w_lg_ni1l162w(0) AND n0OO;
wire_ni1i_w_lg_n00l278w(0) <= NOT n00l;
wire_ni1i_w_lg_n0OO163w(0) <= NOT n0OO;
wire_ni1i_w_lg_ni1l162w(0) <= NOT ni1l;
wire_n000i_dataout <= txctrl(1) OR nl100l;
wire_n000l_dataout <= txdatain(8) OR nl100l;
wire_n000O_dataout <= txdatain(9) AND NOT(nl100l);
wire_n001i_dataout <= wire_n00li_dataout OR nl10iO;
wire_n001l_dataout <= wire_n00ll_dataout AND NOT(nl10iO);
wire_n001O_dataout <= wire_n00lO_dataout OR nl10iO;
wire_n00ii_dataout <= txdatain(10) OR nl100l;
wire_n00il_dataout <= txdatain(11) OR nl100l;
wire_n00iO_dataout <= txdatain(12) OR nl100l;
wire_n00li_dataout <= txdatain(13) OR nl100l;
wire_n00ll_dataout <= txdatain(14) OR nl100l;
wire_n00lO_dataout <= txdatain(15) OR nl100l;
wire_n00Oi_dataout <= wire_n01li_dataout WHEN nl111l = '1' ELSE wire_ni1i_w_lg_n00l278w(0);
wire_n00Ol_dataout <= wire_n01ll_dataout WHEN nl111l = '1' ELSE wire_n0iii_dataout;
wire_n00OO_dataout <= wire_n01lO_dataout WHEN nl111l = '1' ELSE wire_n0iil_dataout;
wire_n010i_dataout <= wire_n01Oi_dataout OR NOT(nl111l);
wire_n010l_dataout <= wire_n01Ol_dataout OR NOT(nl111l);
wire_n010O_dataout <= wire_n01OO_dataout OR NOT(nl111l);
wire_n011i_dataout <= wire_n01li_dataout OR NOT(nl111l);
wire_n011l_dataout <= wire_n01ll_dataout AND nl111l;
wire_n011O_dataout <= wire_n01lO_dataout AND nl111l;
wire_n01ii_dataout <= wire_n001i_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n01il_dataout <= wire_n001l_dataout AND nl111l;
wire_n01iO_dataout <= wire_n001O_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n01li_dataout <= wire_n000i_dataout OR nl10iO;
wire_n01ll_dataout <= wire_n000l_dataout AND NOT(nl10iO);
wire_n01lO_dataout <= wire_n000O_dataout AND NOT(nl10iO);
wire_n01Oi_dataout <= wire_n00ii_dataout OR nl10iO;
wire_n01Ol_dataout <= wire_n00il_dataout OR nl10iO;
wire_n01OO_dataout <= wire_n00iO_dataout OR nl10iO;
wire_n0i0i_dataout <= wire_n001i_dataout WHEN nl111l = '1' ELSE wire_n0ilO_dataout;
wire_n0i0l_dataout <= wire_n001l_dataout WHEN nl111l = '1' ELSE wire_n0iOi_dataout;
wire_n0i0O_dataout <= wire_n001O_dataout WHEN nl111l = '1' ELSE wire_n0iOl_dataout;
wire_n0i1i_dataout <= wire_n01Oi_dataout WHEN nl111l = '1' ELSE wire_n0iiO_dataout;
wire_n0i1l_dataout <= wire_n01Ol_dataout WHEN nl111l = '1' ELSE wire_n0ili_dataout;
wire_n0i1O_dataout <= wire_n01OO_dataout WHEN nl111l = '1' ELSE wire_n0ill_dataout;
wire_n0ii_dataout <= wire_n0il_dataout OR nl101i;
wire_n0iii_dataout <= nlOiO AND n00l;
wire_n0iil_dataout <= nlOli AND n00l;
wire_n0iiO_dataout <= nlOll OR NOT(n00l);
wire_n0il_dataout <= n00l AND NOT(((((wire_ni1i_w_lg_w_lg_w_lg_ni1l162w164w165w(0) AND wire_n0Oi_w_lg_n00O166w(0)) OR wire_ni1i_w_lg_w_lg_w_lg_w_lg_ni1l162w168w169w170w(0)) AND nl11ll) AND n00l));
wire_n0ili_dataout <= nlOlO OR NOT(n00l);
wire_n0ill_dataout <= nlOOi OR NOT(n00l);
wire_n0ilO_dataout <= nlOOl WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n0iOi_dataout <= nlOOO AND n00l;
wire_n0iOl_dataout <= n11i WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n0iOO_dataout <= wire_n001i_dataout WHEN nl111l = '1' ELSE wire_nlO1li_dataout;
wire_n0l0i_dataout <= wire_n001O_dataout AND nl111l;
wire_n0l0l_dataout <= wire_n001i_dataout WHEN nl111l = '1' ELSE wire_n0lii_dataout;
wire_n0l0O_dataout <= wire_n001O_dataout WHEN nl111l = '1' ELSE wire_n0lil_dataout;
wire_n0l1i_dataout <= wire_n001l_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl11il209w(0);
wire_n0l1l_dataout <= wire_n001O_dataout WHEN nl111l = '1' ELSE wire_nlO1ll_dataout;
wire_n0l1O_dataout <= wire_n001i_dataout AND nl111l;
wire_n0lii_dataout <= nlOOl AND n00l;
wire_n0lil_dataout <= n11i AND n00l;
wire_n0liO_dataout <= wire_n001i_dataout OR NOT(nl111l);
wire_n0lli_dataout <= wire_n001l_dataout WHEN nl111l = '1' ELSE nl110i;
wire_n0lll_dataout <= wire_n001O_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl110i277w(0);
wire_n0llO_dataout <= wire_n011i_dataout OR NOT(rdenablesync);
wire_n0lOi_dataout <= wire_n011l_dataout AND rdenablesync;
wire_n0lOl_dataout <= wire_n011O_dataout AND rdenablesync;
wire_n0lOO_dataout <= wire_n010i_dataout OR NOT(rdenablesync);
wire_n0O0i_dataout <= wire_n01il_dataout AND rdenablesync;
wire_n0O0l_dataout <= wire_n0l0i_dataout OR NOT(rdenablesync);
wire_n0O1i_dataout <= wire_n010l_dataout OR NOT(rdenablesync);
wire_n0O1l_dataout <= wire_n010O_dataout OR NOT(rdenablesync);
wire_n0O1O_dataout <= wire_n0l1O_dataout OR NOT(rdenablesync);
wire_n100i_dataout <= n11l AND n00l;
wire_n100l_dataout <= n11O AND n00l;
wire_n100O_dataout <= n10i OR NOT(n00l);
wire_n101i_dataout <= wire_nlOOOi_dataout WHEN nl111l = '1' ELSE wire_n10iO_dataout;
wire_n101l_dataout <= wire_nlOOOl_dataout WHEN nl111l = '1' ELSE wire_n10li_dataout;
wire_n101O_dataout <= wire_nlOOOO_dataout WHEN nl111l = '1' ELSE wire_n10ll_dataout;
wire_n10ii_dataout <= n10l OR NOT(n00l);
wire_n10il_dataout <= n10O OR NOT(n00l);
wire_n10iO_dataout <= n1ii WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n10li_dataout <= n1il AND n00l;
wire_n10ll_dataout <= n1iO WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_n10lO_dataout <= wire_nlOOOi_dataout WHEN nl111l = '1' ELSE wire_nlO1li_dataout;
wire_n10Oi_dataout <= wire_nlOOOl_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl11il209w(0);
wire_n10Ol_dataout <= wire_nlOOOO_dataout WHEN nl111l = '1' ELSE wire_nlO1ll_dataout;
wire_n10OO_dataout <= wire_nlOOOi_dataout AND nl111l;
wire_n110i_dataout <= txdatain(18) OR nl101O;
wire_n110l_dataout <= txdatain(19) OR nl101O;
wire_n110O_dataout <= txdatain(20) OR nl101O;
wire_n111i_dataout <= txctrl(2) OR nl101O;
wire_n111l_dataout <= txdatain(16) OR nl101O;
wire_n111O_dataout <= txdatain(17) AND NOT(nl101O);
wire_n11ii_dataout <= txdatain(21) OR nl101O;
wire_n11il_dataout <= txdatain(22) OR nl101O;
wire_n11iO_dataout <= txdatain(23) OR nl101O;
wire_n11li_dataout <= wire_nlOOii_dataout WHEN nl111l = '1' ELSE wire_ni1i_w_lg_n00l278w(0);
wire_n11ll_dataout <= wire_nlOOil_dataout WHEN nl111l = '1' ELSE wire_n100i_dataout;
wire_n11lO_dataout <= wire_nlOOiO_dataout WHEN nl111l = '1' ELSE wire_n100l_dataout;
wire_n11Oi_dataout <= wire_nlOOli_dataout WHEN nl111l = '1' ELSE wire_n100O_dataout;
wire_n11Ol_dataout <= wire_nlOOll_dataout WHEN nl111l = '1' ELSE wire_n10ii_dataout;
wire_n11OO_dataout <= wire_nlOOlO_dataout WHEN nl111l = '1' ELSE wire_n10il_dataout;
wire_n1i0i_dataout <= n1ii AND n00l;
wire_n1i0l_dataout <= n1iO AND n00l;
wire_n1i0O_dataout <= wire_nlOOOi_dataout OR NOT(nl111l);
wire_n1i1i_dataout <= wire_nlOOOO_dataout AND nl111l;
wire_n1i1l_dataout <= wire_nlOOOi_dataout WHEN nl111l = '1' ELSE wire_n1i0i_dataout;
wire_n1i1O_dataout <= wire_nlOOOO_dataout WHEN nl111l = '1' ELSE wire_n1i0l_dataout;
wire_n1iii_dataout <= wire_nlOOOl_dataout WHEN nl111l = '1' ELSE nl110i;
wire_n1iil_dataout <= wire_nlOOOO_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl110i277w(0);
wire_n1iiO_dataout <= wire_nlOlOi_dataout OR NOT(rdenablesync);
wire_n1ili_dataout <= wire_nlOlOl_dataout AND rdenablesync;
wire_n1ill_dataout <= wire_nlOlOO_dataout AND rdenablesync;
wire_n1ilO_dataout <= wire_nlOO1i_dataout OR NOT(rdenablesync);
wire_n1iOi_dataout <= wire_nlOO1l_dataout OR NOT(rdenablesync);
wire_n1iOl_dataout <= wire_nlOO1O_dataout OR NOT(rdenablesync);
wire_n1iOO_dataout <= wire_n10OO_dataout OR NOT(rdenablesync);
wire_n1l1i_dataout <= wire_nlOO0l_dataout AND rdenablesync;
wire_n1l1l_dataout <= wire_n1i1i_dataout OR NOT(rdenablesync);
wire_n1llO_dataout <= wire_n1O0O_o OR nl1Oli;
wire_n1lOi_dataout <= wire_n1Oii_o AND NOT(nl1Oli);
wire_n1lOl_dataout <= wire_n1Oil_o OR nl1Oli;
wire_n1lOO_dataout <= wire_n1OiO_o OR nl1Oli;
wire_n1O0i_dataout <= wire_n1OOi_o OR nl1Oli;
wire_n1O0l_dataout <= wire_n1OOl_o OR nl1Oli;
wire_n1O1i_dataout <= wire_n1Oli_o OR nl1Oli;
wire_n1O1l_dataout <= wire_n1Oll_o OR nl1Oli;
wire_n1O1O_dataout <= wire_n1OlO_o OR nl1Oli;
wire_ni00i_dataout <= wire_ni0Oi_dataout OR NOT(nl111l);
wire_ni00l_dataout <= wire_ni0Ol_dataout AND nl111l;
wire_ni00O_dataout <= wire_ni0OO_dataout AND nl111l;
wire_ni0ii_dataout <= wire_nii1i_dataout OR NOT(nl111l);
wire_ni0il_dataout <= wire_nii1l_dataout OR NOT(nl111l);
wire_ni0iO_dataout <= wire_nii1O_dataout OR NOT(nl111l);
wire_ni0li_dataout <= wire_nii0i_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_ni0ll_dataout <= wire_nii0l_dataout AND nl111l;
wire_ni0lO_dataout <= wire_nii0O_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_ni0Oi_dataout <= txctrl(0) OR nl10iO;
wire_ni0Ol_dataout <= txdatain(0) OR nl10iO;
wire_ni0OO_dataout <= txdatain(1) AND NOT(nl10iO);
wire_ni10i_dataout <= wire_ni1Oi_o OR nl01ll;
wire_ni10l_dataout <= wire_ni1Ol_o OR nl01ll;
wire_ni10O_dataout <= wire_ni1OO_o OR nl01ll;
wire_ni11i_dataout <= wire_ni1li_o OR nl01ll;
wire_ni11l_dataout <= wire_ni1ll_o AND NOT(nl01ll);
wire_ni11O_dataout <= wire_ni1lO_o OR nl01ll;
wire_ni1ii_dataout <= wire_ni01i_o OR nl01ll;
wire_ni1il_dataout <= wire_ni01l_o OR nl01ll;
wire_ni1iO_dataout <= wire_ni01O_o OR nl01ll;
wire_nii0i_dataout <= txdatain(5) OR nl10iO;
wire_nii0l_dataout <= txdatain(6) OR nl10iO;
wire_nii0O_dataout <= txdatain(7) OR nl10iO;
wire_nii1i_dataout <= txdatain(2) OR nl10iO;
wire_nii1l_dataout <= txdatain(3) OR nl10iO;
wire_nii1O_dataout <= txdatain(4) OR nl10iO;
wire_niiii_dataout <= wire_ni0Ol_dataout WHEN nl111l = '1' ELSE wire_niiOO_dataout;
wire_niiil_dataout <= wire_ni0OO_dataout WHEN nl111l = '1' ELSE wire_nil1i_dataout;
wire_niiiO_dataout <= wire_nii1i_dataout WHEN nl111l = '1' ELSE wire_nil1l_dataout;
wire_niili_dataout <= wire_nii1l_dataout WHEN nl111l = '1' ELSE wire_nil1O_dataout;
wire_niill_dataout <= wire_nii1O_dataout WHEN nl111l = '1' ELSE wire_nil0i_dataout;
wire_niilO_dataout <= wire_nii0i_dataout WHEN nl111l = '1' ELSE wire_nil0l_dataout;
wire_niiOi_dataout <= wire_nii0l_dataout WHEN nl111l = '1' ELSE wire_nil0O_dataout;
wire_niiOl_dataout <= wire_nii0O_dataout WHEN nl111l = '1' ELSE wire_nilii_dataout;
wire_niiOO_dataout <= nllOO AND n00l;
wire_nil0i_dataout <= nlO0l OR NOT(n00l);
wire_nil0l_dataout <= nlO0O WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nil0O_dataout <= nlOii AND n00l;
wire_nil1i_dataout <= nlO1l AND n00l;
wire_nil1l_dataout <= nlO1O OR NOT(n00l);
wire_nil1O_dataout <= nlO0i OR NOT(n00l);
wire_nilii_dataout <= nlOil WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nilil_dataout <= wire_nii0i_dataout WHEN nl111l = '1' ELSE wire_nlO1li_dataout;
wire_niliO_dataout <= wire_nii0l_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl11il209w(0);
wire_nilli_dataout <= wire_nii0O_dataout WHEN nl111l = '1' ELSE wire_nlO1ll_dataout;
wire_nilll_dataout <= wire_nii0i_dataout AND nl111l;
wire_nillO_dataout <= wire_nii0O_dataout AND nl111l;
wire_nilOi_dataout <= wire_nii0i_dataout WHEN nl111l = '1' ELSE wire_nilOO_dataout;
wire_nilOl_dataout <= wire_nii0O_dataout WHEN nl111l = '1' ELSE wire_niO1i_dataout;
wire_nilOO_dataout <= nlO0O AND n00l;
wire_niO0i_dataout <= wire_nii0O_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl110i277w(0);
wire_niO0l_dataout <= wire_ni00i_dataout OR NOT(rdenablesync);
wire_niO0O_dataout <= wire_ni00l_dataout AND rdenablesync;
wire_niO1i_dataout <= nlOil AND n00l;
wire_niO1l_dataout <= wire_nii0i_dataout OR NOT(nl111l);
wire_niO1O_dataout <= wire_nii0l_dataout WHEN nl111l = '1' ELSE nl110i;
wire_niOii_dataout <= wire_ni00O_dataout AND rdenablesync;
wire_niOil_dataout <= wire_ni0ii_dataout OR NOT(rdenablesync);
wire_niOiO_dataout <= wire_ni0il_dataout OR NOT(rdenablesync);
wire_niOli_dataout <= wire_ni0iO_dataout OR NOT(rdenablesync);
wire_niOll_dataout <= wire_nilll_dataout OR NOT(rdenablesync);
wire_niOlO_dataout <= wire_ni0ll_dataout AND rdenablesync;
wire_niOOi_dataout <= wire_nillO_dataout OR NOT(rdenablesync);
wire_nl00i_dataout <= wire_nl00l_dataout OR ((wire_w_lg_w_lg_w_lg_rdenablesync266w267w268w(0) OR wire_w_lg_nl11ll270w(0)) OR wire_w_lg_w_lg_nl11il273w274w(0));
wire_nl00l_dataout <= n0OOO AND NOT((nl110l AND nl110i));
wire_nl01i_dataout <= wire_w_lg_nl110i277w(0) OR nl111l;
wire_nl01l_dataout <= wire_w_lg_nl111l276w(0) AND rdenablesync;
wire_nl10i_dataout <= nliii OR nl111l;
wire_nl10l_dataout <= wire_n0Oi_w_lg_nliii279w(0) AND NOT(nl111l);
wire_nl10O_dataout <= wire_nl1li_dataout OR nl111l;
wire_nl11l_dataout <= wire_nl1iO_dataout AND wire_nl11O_o(7);
wire_nl1ii_dataout <= wire_nl1ll_dataout AND NOT(nl111l);
wire_nl1il_dataout <= wire_ni1i_w_lg_n00l278w(0) AND NOT(nl111l);
wire_nl1iO_dataout <= n00l AND NOT(nl111l);
wire_nl1li_dataout <= nliii AND NOT(n00l);
wire_nl1ll_dataout <= wire_n0Oi_w_lg_nliii279w(0) AND NOT(n00l);
wire_nl1lO_dataout <= wire_nl1Ol_dataout OR nl111l;
wire_nl1Oi_dataout <= wire_nlO1li_dataout AND NOT(nl111l);
wire_nl1Ol_dataout <= nliii OR wire_w_lg_nl11il209w(0);
wire_nl1OO_dataout <= wire_ni1i_w_lg_n00l278w(0) OR nl111l;
wire_nliil_dataout <= nliii WHEN nl110O = '1' ELSE wire_nliOi_dataout;
wire_nliiO_dataout <= nlliO WHEN nl110O = '1' ELSE wire_nliOl_dataout;
wire_nlili_dataout <= nllli WHEN nl110O = '1' ELSE wire_nliOO_dataout;
wire_nlill_dataout <= nllll WHEN nl110O = '1' ELSE wire_nll1i_dataout;
wire_nlilO_dataout <= wire_nll1l_dataout OR nl110O;
wire_nliOi_dataout <= wire_nll1O_o(1) WHEN nl11il = '1' ELSE nl01O;
wire_nliOl_dataout <= wire_nll1O_o(2) WHEN nl11il = '1' ELSE nli1O;
wire_nliOO_dataout <= wire_nll1O_o(3) WHEN nl11il = '1' ELSE nli0i;
wire_nll00i_dataout <= wire_nll0Oi_o OR nl10OO;
wire_nll00l_dataout <= wire_nll0Ol_o OR nl10OO;
wire_nll00O_dataout <= wire_nll0OO_o OR nl10OO;
wire_nll01l_dataout <= wire_nll0ll_o OR nl10OO;
wire_nll01O_dataout <= wire_nll0lO_o AND NOT(nl10OO);
wire_nll0ii_dataout <= wire_nlli1i_o OR nl10OO;
wire_nll0il_dataout <= wire_nlli1l_o OR nl10OO;
wire_nll0iO_dataout <= wire_nlli1O_o OR nl10OO;
wire_nll0li_dataout <= wire_nlli0i_o OR nl10OO;
wire_nll1i_dataout <= wire_nll1O_o(4) WHEN nl11il = '1' ELSE nli0l;
wire_nll1l_dataout <= wire_nll1O_o(5) WHEN nl11il = '1' ELSE nli0O;
wire_nlli0l_dataout <= wire_nlliOl_dataout OR NOT(nl111l);
wire_nlli0O_dataout <= wire_nlliOO_dataout AND nl111l;
wire_nlliii_dataout <= wire_nlll1i_dataout AND nl111l;
wire_nlliil_dataout <= wire_nlll1l_dataout OR NOT(nl111l);
wire_nlliiO_dataout <= wire_nlll1O_dataout OR NOT(nl111l);
wire_nllili_dataout <= wire_nlll0i_dataout OR NOT(nl111l);
wire_nllill_dataout <= wire_nlll0l_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nllilO_dataout <= wire_nlll0O_dataout AND nl111l;
wire_nlliOi_dataout <= wire_nlllii_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nlliOl_dataout <= wire_nlllil_dataout OR niOOOi;
wire_nlliOO_dataout <= wire_nllliO_dataout AND NOT(niOOOi);
wire_nlll0i_dataout <= wire_nlllOi_dataout OR niOOOi;
wire_nlll0l_dataout <= wire_nlllOl_dataout OR niOOOi;
wire_nlll0O_dataout <= wire_nlllOO_dataout AND NOT(niOOOi);
wire_nlll1i_dataout <= wire_nlllli_dataout AND NOT(niOOOi);
wire_nlll1l_dataout <= wire_nlllll_dataout OR niOOOi;
wire_nlll1O_dataout <= wire_nllllO_dataout OR niOOOi;
wire_nlllii_dataout <= wire_nllO1i_dataout OR niOOOi;
wire_nlllil_dataout <= txctrl(3) OR nl101l;
wire_nllliO_dataout <= txdatain(24) OR nl101l;
wire_nlllli_dataout <= txdatain(25) AND NOT(nl101l);
wire_nlllll_dataout <= txdatain(26) OR nl101l;
wire_nllllO_dataout <= txdatain(27) OR nl101l;
wire_nlllOi_dataout <= txdatain(28) OR nl101l;
wire_nlllOl_dataout <= txdatain(29) OR nl101l;
wire_nlllOO_dataout <= txdatain(30) OR nl101l;
wire_nllO0l_dataout <= wire_nlliOl_dataout WHEN nl111l = '1' ELSE wire_ni1i_w_lg_n00l278w(0);
wire_nllO0O_dataout <= wire_nlliOO_dataout WHEN nl111l = '1' ELSE wire_nllOOl_dataout;
wire_nllO1i_dataout <= txdatain(31) OR nl101l;
wire_nllOii_dataout <= wire_nlll1i_dataout WHEN nl111l = '1' ELSE wire_nllOOO_dataout;
wire_nllOil_dataout <= wire_nlll1l_dataout WHEN nl111l = '1' ELSE wire_nlO11i_dataout;
wire_nllOiO_dataout <= wire_nlll1O_dataout WHEN nl111l = '1' ELSE wire_nlO11l_dataout;
wire_nllOli_dataout <= wire_nlll0i_dataout WHEN nl111l = '1' ELSE wire_nlO11O_dataout;
wire_nllOll_dataout <= wire_nlll0l_dataout WHEN nl111l = '1' ELSE wire_nlO10i_dataout;
wire_nllOlO_dataout <= wire_nlll0O_dataout WHEN nl111l = '1' ELSE wire_nlO10l_dataout;
wire_nllOOi_dataout <= wire_nlllii_dataout WHEN nl111l = '1' ELSE wire_nlO10O_dataout;
wire_nllOOl_dataout <= n1li AND n00l;
wire_nllOOO_dataout <= n1lO AND n00l;
wire_nlO00i_dataout <= wire_nlll0O_dataout WHEN nl111l = '1' ELSE nl110i;
wire_nlO00l_dataout <= wire_nlllii_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl110i277w(0);
wire_nlO01i_dataout <= n01i AND n00l;
wire_nlO01l_dataout <= n00i AND n00l;
wire_nlO01O_dataout <= wire_nlll0l_dataout OR NOT(nl111l);
wire_nlO0ii_dataout <= wire_nlli0l_dataout OR NOT(rdenablesync);
wire_nlO0il_dataout <= wire_nlli0O_dataout AND rdenablesync;
wire_nlO0iO_dataout <= wire_nlliii_dataout AND rdenablesync;
wire_nlO0li_dataout <= wire_nlliil_dataout OR NOT(rdenablesync);
wire_nlO0ll_dataout <= wire_nlliiO_dataout OR NOT(rdenablesync);
wire_nlO0lO_dataout <= wire_nllili_dataout OR NOT(rdenablesync);
wire_nlO0Oi_dataout <= wire_nlO1lO_dataout OR NOT(rdenablesync);
wire_nlO0Ol_dataout <= wire_nllilO_dataout AND rdenablesync;
wire_nlO0OO_dataout <= wire_nlO1Oi_dataout OR NOT(rdenablesync);
wire_nlO10i_dataout <= n01i WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nlO10l_dataout <= n01l AND n00l;
wire_nlO10O_dataout <= n00i WHEN n00l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nlO11i_dataout <= n1Oi OR NOT(n00l);
wire_nlO11l_dataout <= n1Ol OR NOT(n00l);
wire_nlO11O_dataout <= n1OO OR NOT(n00l);
wire_nlO1ii_dataout <= wire_nlll0l_dataout WHEN nl111l = '1' ELSE wire_nlO1li_dataout;
wire_nlO1il_dataout <= wire_nlll0O_dataout WHEN nl111l = '1' ELSE wire_w_lg_nl11il209w(0);
wire_nlO1iO_dataout <= wire_nlllii_dataout WHEN nl111l = '1' ELSE wire_nlO1ll_dataout;
wire_nlO1li_dataout <= wire_n0Oi_w_lg_nliii279w(0) OR wire_w_lg_nl11il209w(0);
wire_nlO1ll_dataout <= wire_n0Oi_w_lg_nliii279w(0) AND NOT(wire_w_lg_nl11il209w(0));
wire_nlO1lO_dataout <= wire_nlll0l_dataout AND nl111l;
wire_nlO1Oi_dataout <= wire_nlllii_dataout AND nl111l;
wire_nlO1Ol_dataout <= wire_nlll0l_dataout WHEN nl111l = '1' ELSE wire_nlO01i_dataout;
wire_nlO1OO_dataout <= wire_nlllii_dataout WHEN nl111l = '1' ELSE wire_nlO01l_dataout;
wire_nlOili_dataout <= wire_nlOl0i_o OR nl1lii;
wire_nlOill_dataout <= wire_nlOl0l_o AND NOT(nl1lii);
wire_nlOilO_dataout <= wire_nlOl0O_o OR nl1lii;
wire_nlOiOi_dataout <= wire_nlOlii_o OR nl1lii;
wire_nlOiOl_dataout <= wire_nlOlil_o OR nl1lii;
wire_nlOiOO_dataout <= wire_nlOliO_o OR nl1lii;
wire_nlOl1i_dataout <= wire_nlOlli_o OR nl1lii;
wire_nlOl1l_dataout <= wire_nlOlll_o OR nl1lii;
wire_nlOl1O_dataout <= wire_nlOllO_o OR nl1lii;
wire_nlOlOi_dataout <= wire_nlOOii_dataout OR NOT(nl111l);
wire_nlOlOl_dataout <= wire_nlOOil_dataout AND nl111l;
wire_nlOlOO_dataout <= wire_nlOOiO_dataout AND nl111l;
wire_nlOO0i_dataout <= wire_nlOOOi_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nlOO0l_dataout <= wire_nlOOOl_dataout AND nl111l;
wire_nlOO0O_dataout <= wire_nlOOOO_dataout WHEN nl111l = '1' ELSE wire_n0Oi_w_lg_nliii279w(0);
wire_nlOO1i_dataout <= wire_nlOOli_dataout OR NOT(nl111l);
wire_nlOO1l_dataout <= wire_nlOOll_dataout OR NOT(nl111l);
wire_nlOO1O_dataout <= wire_nlOOlO_dataout OR NOT(nl111l);
wire_nlOOii_dataout <= wire_n111i_dataout OR niOOOl;
wire_nlOOil_dataout <= wire_n111l_dataout AND NOT(niOOOl);
wire_nlOOiO_dataout <= wire_n111O_dataout AND NOT(niOOOl);
wire_nlOOli_dataout <= wire_n110i_dataout OR niOOOl;
wire_nlOOll_dataout <= wire_n110l_dataout OR niOOOl;
wire_nlOOlO_dataout <= wire_n110O_dataout OR niOOOl;
wire_nlOOOi_dataout <= wire_n11ii_dataout OR niOOOl;
wire_nlOOOl_dataout <= wire_n11il_dataout AND NOT(niOOOl);
wire_nlOOOO_dataout <= wire_n11iO_dataout OR niOOOl;
wire_nll1O_a <= ( nli0O & nli0l & nli0i & nli1O & nl01O & "1");
wire_nll1O_b <= ( "1" & "1" & "1" & "1" & "0" & "1");
nll1O : oper_add
GENERIC MAP (
sgate_representation => 0,
width_a => 6,
width_b => 6,
width_o => 6
)
PORT MAP (
a => wire_nll1O_a,
b => wire_nll1O_b,
cin => wire_gnd,
o => wire_nll1O_o
);
wire_nl11O_i <= ( ni1l & n0OO & n0Ol & n00O);
nl11O : oper_decoder
GENERIC MAP (
width_i => 4,
width_o => 16
)
PORT MAP (
i => wire_nl11O_i,
o => wire_nl11O_o
);
wire_nl0OO_a <= ( "1" & "0" & "0" & "0");
wire_nl0OO_b <= ( ni1l & n0OO & n0Ol & n00O);
nl0OO : oper_less_than
GENERIC MAP (
sgate_representation => 0,
width_a => 4,
width_b => 4
)
PORT MAP (
a => wire_nl0OO_a,
b => wire_nl0OO_b,
cin => wire_gnd,
o => wire_nl0OO_o
);
wire_n1O0O_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n011i_dataout & wire_n00Oi_dataout & wire_n011i_dataout & wire_n011i_dataout & wire_n011i_dataout & wire_n0llO_dataout & wire_n00Oi_dataout & wire_n011i_dataout & "1");
wire_n1O0O_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1O0O : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1O0O_data,
o => wire_n1O0O_o,
sel => wire_n1O0O_sel
);
wire_n1Oii_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n011l_dataout & wire_n00Ol_dataout & wire_n011l_dataout & wire_n011l_dataout & wire_n011l_dataout & wire_n0lOi_dataout & wire_n00Ol_dataout & wire_n011l_dataout & "0");
wire_n1Oii_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1Oii : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1Oii_data,
o => wire_n1Oii_o,
sel => wire_n1Oii_sel
);
wire_n1Oil_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n011O_dataout & wire_n00OO_dataout & wire_n011O_dataout & wire_n011O_dataout & wire_n011O_dataout & wire_n0lOl_dataout & wire_n00OO_dataout & wire_n011O_dataout & "0");
wire_n1Oil_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1Oil : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1Oil_data,
o => wire_n1Oil_o,
sel => wire_n1Oil_sel
);
wire_n1OiO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n010i_dataout & wire_n0i1i_dataout & wire_n010i_dataout & wire_n010i_dataout & wire_n010i_dataout & wire_n0lOO_dataout & wire_n0i1i_dataout & wire_n010i_dataout & "1");
wire_n1OiO_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1OiO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1OiO_data,
o => wire_n1OiO_o,
sel => wire_n1OiO_sel
);
wire_n1Oli_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n010l_dataout & wire_n0i1l_dataout & wire_n010l_dataout & wire_n010l_dataout & wire_n010l_dataout & wire_n0O1i_dataout & wire_n0i1l_dataout & wire_n010l_dataout & "1");
wire_n1Oli_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1Oli : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1Oli_data,
o => wire_n1Oli_o,
sel => wire_n1Oli_sel
);
wire_n1Oll_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n010O_dataout & wire_n0i1O_dataout & wire_n010O_dataout & wire_n010O_dataout & wire_n010O_dataout & wire_n0O1l_dataout & wire_n0i1O_dataout & wire_n010O_dataout & "1");
wire_n1Oll_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1Oll : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1Oll_data,
o => wire_n1Oll_o,
sel => wire_n1Oll_sel
);
wire_n1OlO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n01ii_dataout & wire_n0i0i_dataout & wire_n0iOO_dataout & wire_n0iOO_dataout & wire_n0l1O_dataout & wire_n0O1O_dataout & wire_n0l0l_dataout & wire_n0liO_dataout & "1");
wire_n1OlO_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1OlO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1OlO_data,
o => wire_n1OlO_o,
sel => wire_n1OlO_sel
);
wire_n1OOi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n01il_dataout & wire_n0i0l_dataout & wire_n0l1i_dataout & wire_n0l1i_dataout & wire_n01il_dataout & wire_n0O0i_dataout & wire_n0i0l_dataout & wire_n0lli_dataout & "0");
wire_n1OOi_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1OOi : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1OOi_data,
o => wire_n1OOi_o,
sel => wire_n1OOi_sel
);
wire_n1OOl_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n01iO_dataout & wire_n0i0O_dataout & wire_n0l1l_dataout & wire_n0l1l_dataout & wire_n0l0i_dataout & wire_n0O0l_dataout & wire_n0l0O_dataout & wire_n0lll_dataout & "1");
wire_n1OOl_sel <= ( ni1l & n0OO & n0Ol & n00O);
n1OOl : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_n1OOl_data,
o => wire_n1OOl_o,
sel => wire_n1OOl_sel
);
wire_ni01i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni0li_dataout & wire_niilO_dataout & wire_nilil_dataout & wire_nilil_dataout & wire_nilll_dataout & wire_niOll_dataout & wire_nilOi_dataout & wire_niO1l_dataout & "1");
wire_ni01i_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni01i : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni01i_data,
o => wire_ni01i_o,
sel => wire_ni01i_sel
);
wire_ni01l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni0ll_dataout & wire_niiOi_dataout & wire_niliO_dataout & wire_niliO_dataout & wire_ni0ll_dataout & wire_niOlO_dataout & wire_niiOi_dataout & wire_niO1O_dataout & "0");
wire_ni01l_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni01l : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni01l_data,
o => wire_ni01l_o,
sel => wire_ni01l_sel
);
wire_ni01O_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni0lO_dataout & wire_niiOl_dataout & wire_nilli_dataout & wire_nilli_dataout & wire_nillO_dataout & wire_niOOi_dataout & wire_nilOl_dataout & wire_niO0i_dataout & "1");
wire_ni01O_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni01O : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni01O_data,
o => wire_ni01O_o,
sel => wire_ni01O_sel
);
wire_ni1li_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni00i_dataout & wire_ni00i_dataout & wire_ni00i_dataout & wire_ni00i_dataout & wire_ni00i_dataout & wire_niO0l_dataout & wire_ni00i_dataout & wire_ni00i_dataout & "1");
wire_ni1li_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1li : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1li_data,
o => wire_ni1li_o,
sel => wire_ni1li_sel
);
wire_ni1ll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni00l_dataout & wire_niiii_dataout & wire_ni00l_dataout & wire_ni00l_dataout & wire_ni00l_dataout & wire_niO0O_dataout & wire_niiii_dataout & wire_ni00l_dataout & "0");
wire_ni1ll_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1ll : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1ll_data,
o => wire_ni1ll_o,
sel => wire_ni1ll_sel
);
wire_ni1lO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni00O_dataout & wire_niiil_dataout & wire_ni00O_dataout & wire_ni00O_dataout & wire_ni00O_dataout & wire_niOii_dataout & wire_niiil_dataout & wire_ni00O_dataout & "0");
wire_ni1lO_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1lO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1lO_data,
o => wire_ni1lO_o,
sel => wire_ni1lO_sel
);
wire_ni1Oi_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni0ii_dataout & wire_niiiO_dataout & wire_ni0ii_dataout & wire_ni0ii_dataout & wire_ni0ii_dataout & wire_niOil_dataout & wire_niiiO_dataout & wire_ni0ii_dataout & "1");
wire_ni1Oi_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1Oi : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1Oi_data,
o => wire_ni1Oi_o,
sel => wire_ni1Oi_sel
);
wire_ni1Ol_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni0il_dataout & wire_niili_dataout & wire_ni0il_dataout & wire_ni0il_dataout & wire_ni0il_dataout & wire_niOiO_dataout & wire_niili_dataout & wire_ni0il_dataout & "1");
wire_ni1Ol_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1Ol : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1Ol_data,
o => wire_ni1Ol_o,
sel => wire_ni1Ol_sel
);
wire_ni1OO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni0iO_dataout & wire_niill_dataout & wire_ni0iO_dataout & wire_ni0iO_dataout & wire_ni0iO_dataout & wire_niOli_dataout & wire_niill_dataout & wire_ni0iO_dataout & "1");
wire_ni1OO_sel <= ( ni1l & n0OO & n0Ol & n00O);
ni1OO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_ni1OO_data,
o => wire_ni1OO_o,
sel => wire_ni1OO_sel
);
wire_niOOl_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl10i_dataout & wire_nl10O_dataout & wire_nl1lO_dataout & wire_nl1lO_dataout & "1" & "1" & wire_nl1OO_dataout & wire_nl01i_dataout & "1");
wire_niOOl_sel <= ( ni1l & n0OO & n0Ol & n00O);
niOOl : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_niOOl_data,
o => wire_niOOl_o,
sel => wire_niOOl_sel
);
wire_niOOO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl10l_dataout & wire_nl1ii_dataout & wire_nl1Oi_dataout & wire_nl1Oi_dataout & "0" & wire_w_lg_rdenablesync266w & "0" & wire_w_lg_nl111l276w & "1");
wire_niOOO_sel <= ( ni1l & n0OO & n0Ol & n00O);
niOOO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_niOOO_data,
o => wire_niOOO_o,
sel => wire_niOOO_sel
);
wire_nl11i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_nl111l276w & wire_nl1il_dataout & wire_w_lg_nl111l276w & wire_w_lg_nl111l276w & wire_w_lg_nl111l276w & wire_nl01l_dataout & wire_w_lg_nl111l276w & "0" & "0");
wire_nl11i_sel <= ( ni1l & n0OO & n0Ol & n00O);
nl11i : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nl11i_data,
o => wire_nl11i_o,
sel => wire_nl11i_sel
);
wire_nll0ll_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlli0l_dataout & wire_nllO0l_dataout & wire_nlli0l_dataout & wire_nlli0l_dataout & wire_nlli0l_dataout & wire_nlO0ii_dataout & wire_nllO0l_dataout & wire_nlli0l_dataout & "1");
wire_nll0ll_sel <= ( ni1l & n0OO & n0Ol & n00O);
nll0ll : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nll0ll_data,
o => wire_nll0ll_o,
sel => wire_nll0ll_sel
);
wire_nll0lO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlli0O_dataout & wire_nllO0O_dataout & wire_nlli0O_dataout & wire_nlli0O_dataout & wire_nlli0O_dataout & wire_nlO0il_dataout & wire_nllO0O_dataout & wire_nlli0O_dataout & "0");
wire_nll0lO_sel <= ( ni1l & n0OO & n0Ol & n00O);
nll0lO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nll0lO_data,
o => wire_nll0lO_o,
sel => wire_nll0lO_sel
);
wire_nll0Oi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlliii_dataout & wire_nllOii_dataout & wire_nlliii_dataout & wire_nlliii_dataout & wire_nlliii_dataout & wire_nlO0iO_dataout & wire_nllOii_dataout & wire_nlliii_dataout & "0");
wire_nll0Oi_sel <= ( ni1l & n0OO & n0Ol & n00O);
nll0Oi : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nll0Oi_data,
o => wire_nll0Oi_o,
sel => wire_nll0Oi_sel
);
wire_nll0Ol_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlliil_dataout & wire_nllOil_dataout & wire_nlliil_dataout & wire_nlliil_dataout & wire_nlliil_dataout & wire_nlO0li_dataout & wire_nllOil_dataout & wire_nlliil_dataout & "1");
wire_nll0Ol_sel <= ( ni1l & n0OO & n0Ol & n00O);
nll0Ol : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nll0Ol_data,
o => wire_nll0Ol_o,
sel => wire_nll0Ol_sel
);
wire_nll0OO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlliiO_dataout & wire_nllOiO_dataout & wire_nlliiO_dataout & wire_nlliiO_dataout & wire_nlliiO_dataout & wire_nlO0ll_dataout & wire_nllOiO_dataout & wire_nlliiO_dataout & "1");
wire_nll0OO_sel <= ( ni1l & n0OO & n0Ol & n00O);
nll0OO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nll0OO_data,
o => wire_nll0OO_o,
sel => wire_nll0OO_sel
);
wire_nlli0i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlliOi_dataout & wire_nllOOi_dataout & wire_nlO1iO_dataout & wire_nlO1iO_dataout & wire_nlO1Oi_dataout & wire_nlO0OO_dataout & wire_nlO1OO_dataout & wire_nlO00l_dataout & "1");
wire_nlli0i_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlli0i : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlli0i_data,
o => wire_nlli0i_o,
sel => wire_nlli0i_sel
);
wire_nlli1i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nllili_dataout & wire_nllOli_dataout & wire_nllili_dataout & wire_nllili_dataout & wire_nllili_dataout & wire_nlO0lO_dataout & wire_nllOli_dataout & wire_nllili_dataout & "1");
wire_nlli1i_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlli1i : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlli1i_data,
o => wire_nlli1i_o,
sel => wire_nlli1i_sel
);
wire_nlli1l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nllill_dataout & wire_nllOll_dataout & wire_nlO1ii_dataout & wire_nlO1ii_dataout & wire_nlO1lO_dataout & wire_nlO0Oi_dataout & wire_nlO1Ol_dataout & wire_nlO01O_dataout & "1");
wire_nlli1l_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlli1l : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlli1l_data,
o => wire_nlli1l_o,
sel => wire_nlli1l_sel
);
wire_nlli1O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nllilO_dataout & wire_nllOlO_dataout & wire_nlO1il_dataout & wire_nlO1il_dataout & wire_nllilO_dataout & wire_nlO0Ol_dataout & wire_nllOlO_dataout & wire_nlO00i_dataout & "0");
wire_nlli1O_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlli1O : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlli1O_data,
o => wire_nlli1O_o,
sel => wire_nlli1O_sel
);
wire_nlOl0i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOlOi_dataout & wire_n11li_dataout & wire_nlOlOi_dataout & wire_nlOlOi_dataout & wire_nlOlOi_dataout & wire_n1iiO_dataout & wire_n11li_dataout & wire_nlOlOi_dataout & "1");
wire_nlOl0i_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOl0i : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOl0i_data,
o => wire_nlOl0i_o,
sel => wire_nlOl0i_sel
);
wire_nlOl0l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOlOl_dataout & wire_n11ll_dataout & wire_nlOlOl_dataout & wire_nlOlOl_dataout & wire_nlOlOl_dataout & wire_n1ili_dataout & wire_n11ll_dataout & wire_nlOlOl_dataout & "0");
wire_nlOl0l_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOl0l : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOl0l_data,
o => wire_nlOl0l_o,
sel => wire_nlOl0l_sel
);
wire_nlOl0O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOlOO_dataout & wire_n11lO_dataout & wire_nlOlOO_dataout & wire_nlOlOO_dataout & wire_nlOlOO_dataout & wire_n1ill_dataout & wire_n11lO_dataout & wire_nlOlOO_dataout & "0");
wire_nlOl0O_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOl0O : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOl0O_data,
o => wire_nlOl0O_o,
sel => wire_nlOl0O_sel
);
wire_nlOlii_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOO1i_dataout & wire_n11Oi_dataout & wire_nlOO1i_dataout & wire_nlOO1i_dataout & wire_nlOO1i_dataout & wire_n1ilO_dataout & wire_n11Oi_dataout & wire_nlOO1i_dataout & "1");
wire_nlOlii_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOlii : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOlii_data,
o => wire_nlOlii_o,
sel => wire_nlOlii_sel
);
wire_nlOlil_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOO1l_dataout & wire_n11Ol_dataout & wire_nlOO1l_dataout & wire_nlOO1l_dataout & wire_nlOO1l_dataout & wire_n1iOi_dataout & wire_n11Ol_dataout & wire_nlOO1l_dataout & "1");
wire_nlOlil_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOlil : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOlil_data,
o => wire_nlOlil_o,
sel => wire_nlOlil_sel
);
wire_nlOliO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOO1O_dataout & wire_n11OO_dataout & wire_nlOO1O_dataout & wire_nlOO1O_dataout & wire_nlOO1O_dataout & wire_n1iOl_dataout & wire_n11OO_dataout & wire_nlOO1O_dataout & "1");
wire_nlOliO_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOliO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOliO_data,
o => wire_nlOliO_o,
sel => wire_nlOliO_sel
);
wire_nlOlli_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOO0i_dataout & wire_n101i_dataout & wire_n10lO_dataout & wire_n10lO_dataout & wire_n10OO_dataout & wire_n1iOO_dataout & wire_n1i1l_dataout & wire_n1i0O_dataout & "1");
wire_nlOlli_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOlli : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOlli_data,
o => wire_nlOlli_o,
sel => wire_nlOlli_sel
);
wire_nlOlll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOO0l_dataout & wire_n101l_dataout & wire_n10Oi_dataout & wire_n10Oi_dataout & wire_nlOO0l_dataout & wire_n1l1i_dataout & wire_n101l_dataout & wire_n1iii_dataout & "0");
wire_nlOlll_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOlll : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOlll_data,
o => wire_nlOlll_o,
sel => wire_nlOlll_sel
);
wire_nlOllO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOO0O_dataout & wire_n101O_dataout & wire_n10Ol_dataout & wire_n10Ol_dataout & wire_n1i1i_dataout & wire_n1l1l_dataout & wire_n1i1O_dataout & wire_n1iil_dataout & "1");
wire_nlOllO_sel <= ( ni1l & n0OO & n0Ol & n00O);
nlOllO : oper_mux
GENERIC MAP (
width_data => 16,
width_sel => 4
)
PORT MAP (
data => wire_nlOllO_data,
o => wire_nlOllO_o,
sel => wire_nlOllO_sel
);
END RTL; --stratixgx_xgm_tx_sm
--synopsys translate_on
--VALID FILE
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY sgate;
USE sgate.sgate_pack.all;
--synthesis_resources = lut 59 mux21 20 oper_selector 10
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_xgm_dskw_sm IS
PORT
(
adet : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
alignstatus : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
rdalign : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
recovclk : IN STD_LOGIC;
resetall : IN STD_LOGIC;
syncstatus : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END stratixgx_xgm_dskw_sm;
ARCHITECTURE RTL OF stratixgx_xgm_dskw_sm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL nl00O43 : STD_LOGIC := '0';
SIGNAL nl00O44 : STD_LOGIC := '0';
SIGNAL wire_nl00O44_w_lg_w_lg_q210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl00O44_w_lg_q210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl0il41 : STD_LOGIC := '0';
SIGNAL nl0il42 : STD_LOGIC := '0';
SIGNAL nl0li39 : STD_LOGIC := '0';
SIGNAL nl0li40 : STD_LOGIC := '0';
SIGNAL wire_nl0li40_w_lg_w_lg_q178w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl0li40_w_lg_q178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl0Oi37 : STD_LOGIC := '0';
SIGNAL nl0Oi38 : STD_LOGIC := '0';
SIGNAL wire_nl0Oi38_w_lg_w_lg_q153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl0Oi38_w_lg_q153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl0Ol35 : STD_LOGIC := '0';
SIGNAL nl0Ol36 : STD_LOGIC := '0';
SIGNAL wire_nl0Ol36_w_lg_w_lg_q148w149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl0Ol36_w_lg_q148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nli0l29 : STD_LOGIC := '0';
SIGNAL nli0l30 : STD_LOGIC := '0';
SIGNAL nli1i33 : STD_LOGIC := '0';
SIGNAL nli1i34 : STD_LOGIC := '0';
SIGNAL nli1O31 : STD_LOGIC := '0';
SIGNAL nli1O32 : STD_LOGIC := '0';
SIGNAL wire_nli1O32_w_lg_w_lg_q128w129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nli1O32_w_lg_q128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nliil27 : STD_LOGIC := '0';
SIGNAL nliil28 : STD_LOGIC := '0';
SIGNAL nlili25 : STD_LOGIC := '0';
SIGNAL nlili26 : STD_LOGIC := '0';
SIGNAL wire_nlili26_w_lg_w_lg_q97w98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nlili26_w_lg_q97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nlilO23 : STD_LOGIC := '0';
SIGNAL nlilO24 : STD_LOGIC := '0';
SIGNAL nliOl21 : STD_LOGIC := '0';
SIGNAL nliOl22 : STD_LOGIC := '0';
SIGNAL wire_nliOl22_w_lg_w_lg_q75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nliOl22_w_lg_q75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nliOO19 : STD_LOGIC := '0';
SIGNAL nliOO20 : STD_LOGIC := '0';
SIGNAL wire_nliOO20_w_lg_w_lg_q72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nliOO20_w_lg_q72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nll0l13 : STD_LOGIC := '0';
SIGNAL nll0l14 : STD_LOGIC := '0';
SIGNAL nll1i17 : STD_LOGIC := '0';
SIGNAL nll1i18 : STD_LOGIC := '0';
SIGNAL wire_nll1i18_w_lg_w_lg_q65w66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nll1i18_w_lg_q65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nll1l15 : STD_LOGIC := '0';
SIGNAL nll1l16 : STD_LOGIC := '0';
SIGNAL wire_nll1l16_w_lg_w_lg_q59w60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nll1l16_w_lg_q59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nlliO11 : STD_LOGIC := '0';
SIGNAL nlliO12 : STD_LOGIC := '0';
SIGNAL nllll10 : STD_LOGIC := '0';
SIGNAL wire_nllll10_w_lg_q39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nllll9 : STD_LOGIC := '0';
SIGNAL nllOi7 : STD_LOGIC := '0';
SIGNAL nllOi8 : STD_LOGIC := '0';
SIGNAL nllOO5 : STD_LOGIC := '0';
SIGNAL nllOO6 : STD_LOGIC := '0';
SIGNAL nlO0l1 : STD_LOGIC := '0';
SIGNAL nlO0l2 : STD_LOGIC := '0';
SIGNAL nlO1l3 : STD_LOGIC := '0';
SIGNAL nlO1l4 : STD_LOGIC := '0';
SIGNAL n0i : STD_LOGIC := '0';
SIGNAL n1i : STD_LOGIC := '0';
SIGNAL n1l : STD_LOGIC := '0';
SIGNAL nlOO : STD_LOGIC := '0';
SIGNAL wire_n1O_PRN : STD_LOGIC;
SIGNAL wire_n1O_w_lg_n1i47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_n1l236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w140w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_nlOO101w102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_nlOO119w120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_nlOO101w102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_nlOO119w120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_w_lg_nlOO119w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_nlOO101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_w_lg_nlOO119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n0l : STD_LOGIC := '0';
SIGNAL nii : STD_LOGIC := '0';
SIGNAL nil : STD_LOGIC := '0';
SIGNAL nli : STD_LOGIC := '0';
SIGNAL nlil : STD_LOGIC := '0';
SIGNAL nliO : STD_LOGIC := '0';
SIGNAL nlli : STD_LOGIC := '0';
SIGNAL nlll : STD_LOGIC := '0';
SIGNAL nllO : STD_LOGIC := '0';
SIGNAL nlOi : STD_LOGIC := '0';
SIGNAL nlOl : STD_LOGIC := '0';
SIGNAL wire_niO_CLRN : STD_LOGIC;
SIGNAL wire_niO_w_lg_nil45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO_w_lg_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO_w_lg_w_lg_w_lg_nlOi81w82w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO_w_lg_w_lg_nlOi81w82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO_w_lg_nlOi81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0Ol_dataout : STD_LOGIC;
SIGNAL wire_n0OO_dataout : STD_LOGIC;
SIGNAL wire_ni0i_dataout : STD_LOGIC;
SIGNAL wire_ni0l_dataout : STD_LOGIC;
SIGNAL wire_ni0O_dataout : STD_LOGIC;
SIGNAL wire_ni1i_dataout : STD_LOGIC;
SIGNAL wire_ni1l_dataout : STD_LOGIC;
SIGNAL wire_niii_dataout : STD_LOGIC;
SIGNAL wire_niil_dataout : STD_LOGIC;
SIGNAL wire_niiO_dataout : STD_LOGIC;
SIGNAL wire_nili_dataout : STD_LOGIC;
SIGNAL wire_nill_dataout : STD_LOGIC;
SIGNAL wire_nilO_dataout : STD_LOGIC;
SIGNAL wire_niOi_dataout : STD_LOGIC;
SIGNAL wire_niOl_dataout : STD_LOGIC;
SIGNAL wire_niOO_dataout : STD_LOGIC;
SIGNAL wire_nl0O_dataout : STD_LOGIC;
SIGNAL wire_nl1i_dataout : STD_LOGIC;
SIGNAL wire_nl1l_dataout : STD_LOGIC;
SIGNAL wire_nl1O_dataout : STD_LOGIC;
SIGNAL wire_n00l_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n00l_o : STD_LOGIC;
SIGNAL wire_n00l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n01i_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n01i_o : STD_LOGIC;
SIGNAL wire_n01i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n01O_data : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n01O_o : STD_LOGIC;
SIGNAL wire_n01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_n0ii_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0ii_o : STD_LOGIC;
SIGNAL wire_n0ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0iO_o : STD_LOGIC;
SIGNAL wire_n0iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0ll_o : STD_LOGIC;
SIGNAL wire_n0ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n0Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_n0Oi_o : STD_LOGIC;
SIGNAL wire_n0Oi_sel : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_n1ll_data : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_n1ll_o : STD_LOGIC;
SIGNAL wire_n1ll_sel : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_n1Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_n1Oi_o : STD_LOGIC;
SIGNAL wire_n1Oi_sel : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_n1Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_n1Ol_o : STD_LOGIC;
SIGNAL wire_n1Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_adet_range31w33w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlO0i48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_adet_range31w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nll0i52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nllil79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlO0i11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlO1i53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_resetall27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nl0ii : STD_LOGIC;
SIGNAL nl0ll : STD_LOGIC;
SIGNAL nl0lO : STD_LOGIC;
SIGNAL nl0OO : STD_LOGIC;
SIGNAL nli0i : STD_LOGIC;
SIGNAL nliii : STD_LOGIC;
SIGNAL nlill : STD_LOGIC;
SIGNAL nll0i : STD_LOGIC;
SIGNAL nll1O : STD_LOGIC;
SIGNAL nllii : STD_LOGIC;
SIGNAL nllil : STD_LOGIC;
SIGNAL nllOl : STD_LOGIC;
SIGNAL nlO0i : STD_LOGIC;
SIGNAL nlO1i : STD_LOGIC;
SIGNAL wire_w_adet_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_adet_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_adet_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_adet_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_w41w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w40w(0) AND nil;
wire_w_lg_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w40w(0) <= wire_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w(0) AND wire_nllll10_w_lg_q39w(0);
wire_w_lg_w_lg_w_lg_w_adet_range31w33w35w37w(0) <= wire_w_lg_w_lg_w_adet_range31w33w35w(0) AND wire_w_adet_range36w(0);
wire_w_lg_w_lg_w_adet_range31w33w35w(0) <= wire_w_lg_w_adet_range31w33w(0) AND wire_w_adet_range34w(0);
wire_w_lg_nlO0i48w(0) <= nlO0i AND wire_n1O_w_lg_n1i47w(0);
wire_w_lg_w_adet_range31w33w(0) <= wire_w_adet_range31w(0) AND wire_w_adet_range32w(0);
wire_w_lg_nll0i52w(0) <= NOT nll0i;
wire_w_lg_nllil79w(0) <= NOT nllil;
wire_w_lg_nlO0i11w(0) <= NOT nlO0i;
wire_w_lg_nlO1i53w(0) <= NOT nlO1i;
wire_w_lg_resetall27w(0) <= NOT resetall;
alignstatus <= n0l;
enabledeskew <= n0i;
fiforesetrd <= (n0i AND wire_n1O_w_lg_n1l236w(0));
nl0ii <= (wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w188w(0) OR (NOT (nl0il42 XOR nl0il41)));
nl0ll <= wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w(0);
nl0lO <= (wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w161w(0) OR nlil);
nl0OO <= (wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w140w141w(0) OR (NOT (nli1i34 XOR nli1i33)));
nli0i <= (wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w123w(0) OR (NOT (nli0l30 XOR nli0l29)));
nliii <= (wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w105w(0) OR (NOT (nliil28 XOR nliil27)));
nlill <= (wire_niO_w_lg_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w85w(0) OR (NOT (nlilO24 XOR nlilO23)));
nll0i <= (wire_w_lg_nlO0i48w(0) AND (nll0l14 XOR nll0l13));
nll1O <= (nlO1i OR wire_niO_w_lg_nil45w(0));
nllii <= (nlO1i OR wire_niO_w_lg_nil45w(0));
nllil <= (wire_w41w(0) AND (nlliO12 XOR nlliO11));
nllOl <= '1';
nlO0i <= ((((rdalign(0) AND rdalign(1)) AND rdalign(2)) AND rdalign(3)) AND (nlO0l2 XOR nlO0l1));
nlO1i <= ((wire_w_lg_nlO0i11w(0) AND (((rdalign(0) OR rdalign(1)) OR rdalign(2)) OR rdalign(3))) AND (nlO1l4 XOR nlO1l3));
wire_w_adet_range31w(0) <= adet(0);
wire_w_adet_range32w(0) <= adet(1);
wire_w_adet_range34w(0) <= adet(2);
wire_w_adet_range36w(0) <= adet(3);
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl00O43 <= nl00O44;
END IF;
if (now = 0 ns) then
nl00O43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl00O44 <= nl00O43;
END IF;
END PROCESS;
wire_nl00O44_w_lg_w_lg_q210w211w(0) <= wire_nl00O44_w_lg_q210w(0) AND nlOO;
wire_nl00O44_w_lg_q210w(0) <= nl00O44 XOR nl00O43;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0il41 <= nl0il42;
END IF;
if (now = 0 ns) then
nl0il41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0il42 <= nl0il41;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0li39 <= nl0li40;
END IF;
if (now = 0 ns) then
nl0li39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0li40 <= nl0li39;
END IF;
END PROCESS;
wire_nl0li40_w_lg_w_lg_q178w179w(0) <= wire_nl0li40_w_lg_q178w(0) AND nlli;
wire_nl0li40_w_lg_q178w(0) <= nl0li40 XOR nl0li39;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0Oi37 <= nl0Oi38;
END IF;
if (now = 0 ns) then
nl0Oi37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0Oi38 <= nl0Oi37;
END IF;
END PROCESS;
wire_nl0Oi38_w_lg_w_lg_q153w154w(0) <= wire_nl0Oi38_w_lg_q153w(0) AND wire_ni0l_dataout;
wire_nl0Oi38_w_lg_q153w(0) <= nl0Oi38 XOR nl0Oi37;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0Ol35 <= nl0Ol36;
END IF;
if (now = 0 ns) then
nl0Ol35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nl0Ol36 <= nl0Ol35;
END IF;
END PROCESS;
wire_nl0Ol36_w_lg_w_lg_q148w149w(0) <= wire_nl0Ol36_w_lg_q148w(0) AND nlll;
wire_nl0Ol36_w_lg_q148w(0) <= nl0Ol36 XOR nl0Ol35;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli0l29 <= nli0l30;
END IF;
if (now = 0 ns) then
nli0l29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli0l30 <= nli0l29;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli1i33 <= nli1i34;
END IF;
if (now = 0 ns) then
nli1i33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli1i34 <= nli1i33;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli1O31 <= nli1O32;
END IF;
if (now = 0 ns) then
nli1O31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nli1O32 <= nli1O31;
END IF;
END PROCESS;
wire_nli1O32_w_lg_w_lg_q128w129w(0) <= wire_nli1O32_w_lg_q128w(0) AND nllO;
wire_nli1O32_w_lg_q128w(0) <= nli1O32 XOR nli1O31;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliil27 <= nliil28;
END IF;
if (now = 0 ns) then
nliil27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliil28 <= nliil27;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlili25 <= nlili26;
END IF;
if (now = 0 ns) then
nlili25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlili26 <= nlili25;
END IF;
END PROCESS;
wire_nlili26_w_lg_w_lg_q97w98w(0) <= wire_nlili26_w_lg_q97w(0) AND wire_nl1O_dataout;
wire_nlili26_w_lg_q97w(0) <= nlili26 XOR nlili25;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlilO23 <= nlilO24;
END IF;
if (now = 0 ns) then
nlilO23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlilO24 <= nlilO23;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliOl21 <= nliOl22;
END IF;
if (now = 0 ns) then
nliOl21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliOl22 <= nliOl21;
END IF;
END PROCESS;
wire_nliOl22_w_lg_w_lg_q75w76w(0) <= wire_nliOl22_w_lg_q75w(0) AND nllii;
wire_nliOl22_w_lg_q75w(0) <= nliOl22 XOR nliOl21;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliOO19 <= nliOO20;
END IF;
if (now = 0 ns) then
nliOO19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nliOO20 <= nliOO19;
END IF;
END PROCESS;
wire_nliOO20_w_lg_w_lg_q72w73w(0) <= wire_nliOO20_w_lg_q72w(0) AND nllii;
wire_nliOO20_w_lg_q72w(0) <= nliOO20 XOR nliOO19;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll0l13 <= nll0l14;
END IF;
if (now = 0 ns) then
nll0l13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll0l14 <= nll0l13;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll1i17 <= nll1i18;
END IF;
if (now = 0 ns) then
nll1i17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll1i18 <= nll1i17;
END IF;
END PROCESS;
wire_nll1i18_w_lg_w_lg_q65w66w(0) <= wire_nll1i18_w_lg_q65w(0) AND nll1O;
wire_nll1i18_w_lg_q65w(0) <= nll1i18 XOR nll1i17;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll1l15 <= nll1l16;
END IF;
if (now = 0 ns) then
nll1l15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nll1l16 <= nll1l15;
END IF;
END PROCESS;
wire_nll1l16_w_lg_w_lg_q59w60w(0) <= wire_nll1l16_w_lg_q59w(0) AND nllO;
wire_nll1l16_w_lg_q59w(0) <= nll1l16 XOR nll1l15;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlliO11 <= nlliO12;
END IF;
if (now = 0 ns) then
nlliO11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlliO12 <= nlliO11;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllll10 <= nllll9;
END IF;
END PROCESS;
wire_nllll10_w_lg_q39w(0) <= nllll10 XOR nllll9;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllll9 <= nllll10;
END IF;
if (now = 0 ns) then
nllll9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllOi7 <= nllOi8;
END IF;
if (now = 0 ns) then
nllOi7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllOi8 <= nllOi7;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllOO5 <= nllOO6;
END IF;
if (now = 0 ns) then
nllOO5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nllOO6 <= nllOO5;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlO0l1 <= nlO0l2;
END IF;
if (now = 0 ns) then
nlO0l1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlO0l2 <= nlO0l1;
END IF;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlO1l3 <= nlO1l4;
END IF;
if (now = 0 ns) then
nlO1l3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (recovclk)
BEGIN
IF (recovclk = '1' AND recovclk'event) THEN nlO1l4 <= nlO1l3;
END IF;
END PROCESS;
PROCESS (recovclk, wire_n1O_PRN)
BEGIN
IF (wire_n1O_PRN = '0') THEN
n0i <= '1';
n1i <= '1';
n1l <= '1';
nlOO <= '1';
ELSIF (recovclk = '1' AND recovclk'event) THEN
n0i <= wire_n1Oi_o;
n1i <= n1l;
n1l <= n0i;
nlOO <= wire_n0Oi_o;
END IF;
if (now = 0 ns) then
n0i <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1i <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
nlOO <= '1' after 1 ps;
end if;
END PROCESS;
wire_n1O_PRN <= ((nllOi8 XOR nllOi7) AND wire_w_lg_resetall27w(0));
wire_n1O_w_lg_n1i47w(0) <= NOT n1i;
wire_n1O_w_lg_n1l236w(0) <= NOT n1l;
wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w105w(0) <= wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w(0) OR nlil;
wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w123w(0) <= wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w(0) OR nlil;
wire_n1O_w_lg_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w188w(0) <= wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w(0) OR nlli;
wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO101w102w103w104w(0) <= wire_n1O_w_lg_w_lg_w_lg_nlOO101w102w103w(0) OR nliO;
wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w120w121w122w(0) <= wire_n1O_w_lg_w_lg_w_lg_nlOO119w120w121w(0) OR nliO;
wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w140w141w(0) <= wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w140w(0) OR nlil;
wire_n1O_w_lg_w_lg_w_lg_w_lg_nlOO119w139w161w174w(0) <= wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w161w(0) OR nlll;
wire_n1O_w_lg_w_lg_w_lg_nlOO101w102w103w(0) <= wire_n1O_w_lg_w_lg_nlOO101w102w(0) OR nlli;
wire_n1O_w_lg_w_lg_w_lg_nlOO119w120w121w(0) <= wire_n1O_w_lg_w_lg_nlOO119w120w(0) OR nlli;
wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w140w(0) <= wire_n1O_w_lg_w_lg_nlOO119w139w(0) OR nliO;
wire_n1O_w_lg_w_lg_w_lg_nlOO119w139w161w(0) <= wire_n1O_w_lg_w_lg_nlOO119w139w(0) OR nllO;
wire_n1O_w_lg_w_lg_nlOO101w102w(0) <= wire_n1O_w_lg_nlOO101w(0) OR nlll;
wire_n1O_w_lg_w_lg_nlOO119w120w(0) <= wire_n1O_w_lg_nlOO119w(0) OR nlll;
wire_n1O_w_lg_w_lg_nlOO119w139w(0) <= wire_n1O_w_lg_nlOO119w(0) OR nlOi;
wire_n1O_w_lg_nlOO101w(0) <= nlOO OR nllO;
wire_n1O_w_lg_nlOO119w(0) <= nlOO OR nlOl;
PROCESS (recovclk, wire_niO_CLRN)
BEGIN
IF (wire_niO_CLRN = '0') THEN
n0l <= '0';
nii <= '0';
nil <= '0';
nli <= '0';
nlil <= '0';
nliO <= '0';
nlli <= '0';
nlll <= '0';
nllO <= '0';
nlOi <= '0';
nlOl <= '0';
ELSIF (recovclk = '1' AND recovclk'event) THEN
n0l <= nii;
nii <= wire_n1ll_o;
nil <= nli;
nli <= (((syncstatus(0) AND syncstatus(1)) AND syncstatus(2)) AND syncstatus(3));
nlil <= wire_n1Ol_o;
nliO <= wire_n01i_o;
nlli <= wire_n01O_o;
nlll <= wire_n00l_o;
nllO <= wire_n0ii_o;
nlOi <= wire_n0iO_o;
nlOl <= wire_n0ll_o;
END IF;
END PROCESS;
wire_niO_CLRN <= ((nllOO6 XOR nllOO5) AND wire_w_lg_resetall27w(0));
wire_niO_w_lg_nil45w(0) <= NOT nil;
wire_niO_w_lg_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w85w(0) <= wire_niO_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w(0) OR nlil;
wire_niO_w_lg_w_lg_w_lg_w_lg_nlOi81w82w83w84w(0) <= wire_niO_w_lg_w_lg_w_lg_nlOi81w82w83w(0) OR nliO;
wire_niO_w_lg_w_lg_w_lg_nlOi81w82w83w(0) <= wire_niO_w_lg_w_lg_nlOi81w82w(0) OR nlli;
wire_niO_w_lg_w_lg_nlOi81w82w(0) <= wire_niO_w_lg_nlOi81w(0) OR nlll;
wire_niO_w_lg_nlOi81w(0) <= nlOi OR nllO;
wire_n0Ol_dataout <= n0i OR nll1O;
wire_n0OO_dataout <= nii AND NOT(nll1O);
wire_ni0i_dataout <= wire_ni0O_dataout AND NOT(wire_niO_w_lg_nil45w(0));
wire_ni0l_dataout <= wire_niii_dataout AND NOT(wire_niO_w_lg_nil45w(0));
wire_ni0O_dataout <= wire_w_lg_nlO0i11w(0) AND NOT(nlO1i);
wire_ni1i_dataout <= wire_w_lg_nlO0i11w(0) AND NOT(nll1O);
wire_ni1l_dataout <= nlO0i AND NOT(nll1O);
wire_niii_dataout <= nlO0i AND NOT(nlO1i);
wire_niil_dataout <= n0i OR wire_niO_w_lg_nil45w(0);
wire_niiO_dataout <= nii AND NOT(wire_niO_w_lg_nil45w(0));
wire_nili_dataout <= nlO1i AND NOT(wire_niO_w_lg_nil45w(0));
wire_nill_dataout <= wire_w_lg_nlO1i53w(0) AND NOT(wire_niO_w_lg_nil45w(0));
wire_nilO_dataout <= nii WHEN nllii = '1' ELSE wire_niOi_dataout;
wire_niOi_dataout <= nii OR nlO0i;
wire_niOl_dataout <= nlO0i AND NOT(nllii);
wire_niOO_dataout <= wire_w_lg_nlO0i11w(0) AND NOT(nllii);
wire_nl0O_dataout <= n0i AND NOT(nllil);
wire_nl1i_dataout <= n0i OR nllii;
wire_nl1l_dataout <= nll0i AND NOT(nllii);
wire_nl1O_dataout <= wire_w_lg_nll0i52w(0) AND NOT(nllii);
wire_n00l_data <= ( "0" & wire_niOl_dataout & wire_nill_dataout & wire_nl0Oi38_w_lg_w_lg_q153w154w);
wire_n00l_sel <= ( nl0OO & nllO & wire_nl0Ol36_w_lg_w_lg_q148w149w & nlli);
n00l : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n00l_data,
o => wire_n00l_o,
sel => wire_n00l_sel
);
wire_n01i_data <= ( "0" & wire_nili_dataout & wire_ni0i_dataout & wire_ni1l_dataout);
wire_n01i_sel <= ( nl0ll & wire_nl0li40_w_lg_w_lg_q178w179w & nliO & nlil);
n01i : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n01i_data,
o => wire_n01i_o,
sel => wire_n01i_sel
);
wire_n01O_data <= ( "0" & wire_nili_dataout & wire_ni0i_dataout & wire_ni0l_dataout);
wire_n01O_sel <= ( nl0lO & nlll & nlli & nliO);
n01O : oper_selector
GENERIC MAP (
width_data => 4,
width_sel => 4
)
PORT MAP (
data => wire_n01O_data,
o => wire_n01O_o,
sel => wire_n01O_sel
);
wire_n0ii_data <= ( "0" & wire_niOl_dataout & wire_niOO_dataout);
wire_n0ii_sel <= ( nli0i & nlOi & wire_nli1O32_w_lg_w_lg_q128w129w);
n0ii : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n0ii_data,
o => wire_n0ii_o,
sel => wire_n0ii_sel
);
wire_n0iO_data <= ( "0" & wire_nl1l_dataout & wire_niOO_dataout);
wire_n0iO_sel <= ( nliii & nlOl & nlOi);
n0iO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n0iO_data,
o => wire_n0iO_o,
sel => wire_n0iO_sel
);
wire_n0ll_data <= ( nllil & wire_nlili26_w_lg_w_lg_q97w98w & "0");
wire_n0ll_sel <= ( nlOO & nlOl & nlill);
n0ll : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n0ll_data,
o => wire_n0ll_o,
sel => wire_n0ll_sel
);
wire_n0Oi_data <= ( wire_w_lg_nllil79w & nllii & wire_nliOl22_w_lg_w_lg_q75w76w & wire_nliOO20_w_lg_w_lg_q72w73w & wire_niO_w_lg_nil45w & wire_niO_w_lg_nil45w & wire_niO_w_lg_nil45w & wire_nll1i18_w_lg_w_lg_q65w66w);
wire_n0Oi_sel <= ( nlOO & nlOl & nlOi & wire_nll1l16_w_lg_w_lg_q59w60w & nlll & nlli & nliO & nlil);
n0Oi : oper_selector
GENERIC MAP (
width_data => 8,
width_sel => 8
)
PORT MAP (
data => wire_n0Oi_data,
o => wire_n0Oi_o,
sel => wire_n0Oi_sel
);
wire_n1ll_data <= ( nii & wire_nilO_dataout & wire_niiO_dataout & wire_niiO_dataout & wire_niiO_dataout & wire_n0OO_dataout);
wire_n1ll_sel <= ( wire_n1O_w_lg_w_lg_nlOO119w139w & nllO & nlll & nlli & nliO & nlil);
n1ll : oper_selector
GENERIC MAP (
width_data => 6,
width_sel => 6
)
PORT MAP (
data => wire_n1ll_data,
o => wire_n1ll_o,
sel => wire_n1ll_sel
);
wire_n1Oi_data <= ( wire_nl0O_dataout & wire_nl1i_dataout & wire_nl1i_dataout & wire_nl1i_dataout & wire_niil_dataout & wire_niil_dataout & wire_niil_dataout & wire_n0Ol_dataout);
wire_n1Oi_sel <= ( wire_nl00O44_w_lg_w_lg_q210w211w & nlOl & nlOi & nllO & nlll & nlli & nliO & nlil);
n1Oi : oper_selector
GENERIC MAP (
width_data => 8,
width_sel => 8
)
PORT MAP (
data => wire_n1Oi_data,
o => wire_n1Oi_o,
sel => wire_n1Oi_sel
);
wire_n1Ol_data <= ( "0" & wire_nili_dataout & wire_ni1i_dataout);
wire_n1Ol_sel <= ( nl0ii & nliO & nlil);
n1Ol : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_n1Ol_data,
o => wire_n1Ol_o,
sel => wire_n1Ol_sel
);
END RTL; --stratixgx_xgm_dskw_sm
--synopsys translate_on
--VALID FILE
--
-- stratixgx_reset_block
--
library IEEE, stratixgx_gxb;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_reset_block IS
PORT (
txdigitalreset : IN std_logic_vector(3 DOWNTO 0);
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0);
rxanalogreset : IN std_logic_vector(3 DOWNTO 0);
pllreset : IN std_logic;
pllenable : IN std_logic;
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
pllresetout : OUT std_logic);
END stratixgx_reset_block;
ARCHITECTURE stratixgx_reset_arch OF stratixgx_reset_block IS
-- WIREs:
signal HARD_RESET : std_logic;
signal txdigitalresetout_tmp : std_logic_vector(3 DOWNTO 0);
signal rxdigitalresetout_tmp : std_logic_vector(3 DOWNTO 0);
signal txanalogresetout_tmp : std_logic_vector(3 DOWNTO 0);
signal rxanalogresetout_tmp : std_logic_vector(3 DOWNTO 0);
signal pllresetout_tmp : std_logic;
BEGIN
txdigitalresetout <= txdigitalresetout_tmp;
rxdigitalresetout <= rxdigitalresetout_tmp;
txanalogresetout <= txanalogresetout_tmp;
rxanalogresetout <= rxanalogresetout_tmp;
pllresetout <= pllresetout_tmp;
HARD_RESET <= pllreset OR NOT pllenable ;
rxanalogresetout_tmp <= (HARD_RESET OR rxanalogreset(3)) &
(HARD_RESET OR rxanalogreset(2)) &
(HARD_RESET OR rxanalogreset(1)) &
(HARD_RESET OR rxanalogreset(0)) ;
txanalogresetout_tmp <= (HARD_RESET & HARD_RESET &
HARD_RESET & HARD_RESET);
pllresetout_tmp <= ((((((rxanalogresetout_tmp(0) AND rxanalogresetout_tmp(1)) AND
rxanalogresetout_tmp(2)) AND rxanalogresetout_tmp(3)) AND
txanalogresetout_tmp(0)) AND txanalogresetout_tmp(1)) AND
txanalogresetout_tmp(2)) AND txanalogresetout_tmp(3) ;
rxdigitalresetout_tmp <= (HARD_RESET OR rxdigitalreset(3)) &
(HARD_RESET OR rxdigitalreset(2)) &
(HARD_RESET OR rxdigitalreset(1)) &
(HARD_RESET OR rxdigitalreset(0)) ;
txdigitalresetout_tmp <= (HARD_RESET OR txdigitalreset(3)) &
(HARD_RESET OR txdigitalreset(2)) &
(HARD_RESET OR txdigitalreset(1)) &
(HARD_RESET OR txdigitalreset(0)) ;
END stratixgx_reset_arch;
--IP Functional Simulation Model
--VERSION_BEGIN 11.0 cbx_mgl 2011:04:27:21:10:09:SJ cbx_simgen 2011:04:27:21:09:05:SJ VERSION_END
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Altera disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY sgate;
USE sgate.sgate_pack.all;
--synthesis_resources = lut 67 mux21 46 oper_selector 10
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY stratixgx_hssi_tx_enc_rtl IS
PORT
(
ENDEC : IN STD_LOGIC;
GE_XAUI_SEL : IN STD_LOGIC;
IB_FORCE_DISPARITY : IN STD_LOGIC;
INDV : IN STD_LOGIC;
prbs_en : IN STD_LOGIC;
PUDR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
soft_reset : IN STD_LOGIC;
tx_clk : IN STD_LOGIC;
tx_ctl_tc : IN STD_LOGIC;
tx_ctl_ts : IN STD_LOGIC;
tx_data_9_tc : IN STD_LOGIC;
tx_data_pg : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
tx_data_tc : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_data_ts : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
TXLP10B : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END stratixgx_hssi_tx_enc_rtl;
ARCHITECTURE RTL OF stratixgx_hssi_tx_enc_rtl IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL n100l27 : STD_LOGIC := '0';
SIGNAL n100l28 : STD_LOGIC := '0';
SIGNAL n101O29 : STD_LOGIC := '0';
SIGNAL n101O30 : STD_LOGIC := '0';
SIGNAL n10ii25 : STD_LOGIC := '0';
SIGNAL n10ii26 : STD_LOGIC := '0';
SIGNAL n10li23 : STD_LOGIC := '0';
SIGNAL n10li24 : STD_LOGIC := '0';
SIGNAL n10lO21 : STD_LOGIC := '0';
SIGNAL n10lO22 : STD_LOGIC := '0';
SIGNAL wire_n10lO22_w_lg_q71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n10OO19 : STD_LOGIC := '0';
SIGNAL n10OO20 : STD_LOGIC := '0';
SIGNAL wire_n10OO20_w_lg_q47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11ii43 : STD_LOGIC := '0';
SIGNAL n11ii44 : STD_LOGIC := '0';
SIGNAL wire_n11ii44_w_lg_w_lg_q155w156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11ii44_w_lg_q155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11il41 : STD_LOGIC := '0';
SIGNAL n11il42 : STD_LOGIC := '0';
SIGNAL wire_n11il42_w_lg_w_lg_q131w132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11il42_w_lg_q131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11iO39 : STD_LOGIC := '0';
SIGNAL n11iO40 : STD_LOGIC := '0';
SIGNAL wire_n11iO40_w_lg_w_lg_q125w126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11iO40_w_lg_q125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11li37 : STD_LOGIC := '0';
SIGNAL n11li38 : STD_LOGIC := '0';
SIGNAL wire_n11li38_w_lg_w_lg_q113w114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11li38_w_lg_q113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11ll35 : STD_LOGIC := '0';
SIGNAL n11ll36 : STD_LOGIC := '0';
SIGNAL wire_n11ll36_w_lg_w_lg_q109w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11ll36_w_lg_q109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11lO33 : STD_LOGIC := '0';
SIGNAL n11lO34 : STD_LOGIC := '0';
SIGNAL wire_n11lO34_w_lg_w_lg_q95w96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n11lO34_w_lg_q95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n11Ol31 : STD_LOGIC := '0';
SIGNAL n11Ol32 : STD_LOGIC := '0';
SIGNAL n1i0l15 : STD_LOGIC := '0';
SIGNAL n1i0l16 : STD_LOGIC := '0';
SIGNAL n1i1l17 : STD_LOGIC := '0';
SIGNAL n1i1l18 : STD_LOGIC := '0';
SIGNAL wire_n1i1l18_w_lg_q43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1iii13 : STD_LOGIC := '0';
SIGNAL n1iii14 : STD_LOGIC := '0';
SIGNAL n1iiO11 : STD_LOGIC := '0';
SIGNAL n1iiO12 : STD_LOGIC := '0';
SIGNAL wire_n1iiO12_w_lg_q28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1ill10 : STD_LOGIC := '0';
SIGNAL wire_n1ill10_w_lg_q24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1ill9 : STD_LOGIC := '0';
SIGNAL n1iOi7 : STD_LOGIC := '0';
SIGNAL n1iOi8 : STD_LOGIC := '0';
SIGNAL wire_n1iOi8_w_lg_q20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1iOO5 : STD_LOGIC := '0';
SIGNAL n1iOO6 : STD_LOGIC := '0';
SIGNAL wire_n1iOO6_w_lg_q15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1l1l3 : STD_LOGIC := '0';
SIGNAL n1l1l4 : STD_LOGIC := '0';
SIGNAL wire_n1l1l4_w_lg_q9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n1liO1 : STD_LOGIC := '0';
SIGNAL n1liO2 : STD_LOGIC := '0';
SIGNAL n10i : STD_LOGIC := '0';
SIGNAL n10l : STD_LOGIC := '0';
SIGNAL n10O : STD_LOGIC := '0';
SIGNAL n11O : STD_LOGIC := '0';
SIGNAL n1ii : STD_LOGIC := '0';
SIGNAL n1li : STD_LOGIC := '0';
SIGNAL n00i : STD_LOGIC := '0';
SIGNAL n00l : STD_LOGIC := '0';
SIGNAL n00O : STD_LOGIC := '0';
SIGNAL n01i : STD_LOGIC := '0';
SIGNAL n01l : STD_LOGIC := '0';
SIGNAL n01O : STD_LOGIC := '0';
SIGNAL n0ii : STD_LOGIC := '0';
SIGNAL n0il : STD_LOGIC := '0';
SIGNAL n11i : STD_LOGIC := '0';
SIGNAL n11l : STD_LOGIC := '0';
SIGNAL n1il : STD_LOGIC := '0';
SIGNAL n1ll : STD_LOGIC := '0';
SIGNAL n1lO : STD_LOGIC := '0';
SIGNAL n1OO : STD_LOGIC := '0';
SIGNAL nlOOO : STD_LOGIC := '0';
SIGNAL nO : STD_LOGIC := '0';
SIGNAL wire_nl_CLRN : STD_LOGIC;
SIGNAL wire_nl_w_lg_nO31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl_w_lg_nO4w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nl_w_lg_nO73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nlOOl : STD_LOGIC := '0';
SIGNAL wire_nlOOi_CLRN : STD_LOGIC;
SIGNAL wire_nlOOi_ENA : STD_LOGIC;
SIGNAL wire_nlOOi_w_lg_nlOOl68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0i0l_dataout : STD_LOGIC;
SIGNAL wire_n0i0l_w_lg_w_lg_dataout253w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0i0l_w_lg_w_lg_dataout253w258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0i0l_w_lg_dataout300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0i0l_w_lg_dataout253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0i0l_w_lg_w_lg_w_lg_dataout253w256w257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n0l0l_dataout : STD_LOGIC;
SIGNAL wire_n0l0O_dataout : STD_LOGIC;
SIGNAL wire_n0lii_dataout : STD_LOGIC;
SIGNAL wire_n0lil_dataout : STD_LOGIC;
SIGNAL wire_n0liO_dataout : STD_LOGIC;
SIGNAL wire_n0lli_dataout : STD_LOGIC;
SIGNAL wire_n0lO_dataout : STD_LOGIC;
SIGNAL wire_n0Oi_dataout : STD_LOGIC;
SIGNAL wire_n0Ol_dataout : STD_LOGIC;
SIGNAL wire_n0OO_dataout : STD_LOGIC;
SIGNAL wire_n1i_dataout : STD_LOGIC;
SIGNAL wire_n1l_dataout : STD_LOGIC;
SIGNAL wire_n1l_w_lg_w_lg_dataout327w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1l_w_lg_dataout255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1l_w_lg_dataout302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1l_w_lg_dataout327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_n1O_dataout : STD_LOGIC;
SIGNAL wire_ni0i_dataout : STD_LOGIC;
SIGNAL wire_ni0l_dataout : STD_LOGIC;
SIGNAL wire_ni0l_w_lg_dataout273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_dataout : STD_LOGIC;
SIGNAL wire_ni0O_w_lg_w_lg_dataout269w315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_w_lg_w_lg_dataout269w270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_w_lg_dataout274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_w_lg_dataout316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_w_lg_dataout269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni0O_w_lg_dataout324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni10O_dataout : STD_LOGIC;
SIGNAL wire_ni10O_w_lg_dataout356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1i_dataout : STD_LOGIC;
SIGNAL wire_ni1ii_dataout : STD_LOGIC;
SIGNAL wire_ni1ii_w_lg_dataout357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ni1l_dataout : STD_LOGIC;
SIGNAL wire_ni1O_dataout : STD_LOGIC;
SIGNAL wire_ni1Oi_dataout : STD_LOGIC;
SIGNAL wire_ni1Oi_w_lg_dataout358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_dataout : STD_LOGIC;
SIGNAL wire_niii_w_lg_w_lg_dataout268w394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_w_lg_dataout268w389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_w_lg_dataout268w380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_w_lg_dataout268w377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_w_lg_dataout268w290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_w_lg_dataout268w281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niii_w_lg_dataout325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_dataout : STD_LOGIC;
SIGNAL wire_niil_w_lg_w_lg_dataout266w337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_dataout266w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_dataout266w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout384w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_dataout266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_w_lg_dataout266w337w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_w_lg_dataout266w289w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_w_lg_dataout266w346w347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w337w339w341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w289w292w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niil_w_lg_w343w344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_dataout : STD_LOGIC;
SIGNAL wire_niiO_w_lg_w_lg_w_lg_dataout286w287w299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_w_lg_dataout286w348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_w_lg_dataout286w287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niiO_w_lg_dataout286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nili_dataout : STD_LOGIC;
SIGNAL wire_nili_w_lg_dataout312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nill_dataout : STD_LOGIC;
SIGNAL wire_nill_w_lg_dataout303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nill_w_lg_dataout265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nilll_dataout : STD_LOGIC;
SIGNAL wire_nilO_dataout : STD_LOGIC;
SIGNAL wire_nilO_w_lg_dataout304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nilO_w_lg_dataout261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nilOl_dataout : STD_LOGIC;
SIGNAL wire_nilOl_w_lg_dataout260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_nilOO_dataout : STD_LOGIC;
SIGNAL wire_niO0i_dataout : STD_LOGIC;
SIGNAL wire_niO0i_w_lg_dataout262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niO0O_dataout : STD_LOGIC;
SIGNAL wire_niO0O_w_lg_dataout263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_niOi_dataout : STD_LOGIC;
SIGNAL wire_niOii_dataout : STD_LOGIC;
SIGNAL wire_niOil_dataout : STD_LOGIC;
SIGNAL wire_niOiO_dataout : STD_LOGIC;
SIGNAL wire_niOl_dataout : STD_LOGIC;
SIGNAL wire_niOli_dataout : STD_LOGIC;
SIGNAL wire_niOO_dataout : STD_LOGIC;
SIGNAL wire_nl0i_dataout : STD_LOGIC;
SIGNAL wire_nl0l_dataout : STD_LOGIC;
SIGNAL wire_nl1i_dataout : STD_LOGIC;
SIGNAL wire_nl1l_dataout : STD_LOGIC;
SIGNAL wire_nl1O_dataout : STD_LOGIC;
SIGNAL wire_nlO0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO0i_o : STD_LOGIC;
SIGNAL wire_nlO0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO0l_o : STD_LOGIC;
SIGNAL wire_nlO0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO0O_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO0O_o : STD_LOGIC;
SIGNAL wire_nlO0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO1l_o : STD_LOGIC;
SIGNAL wire_nlO1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlO1O_o : STD_LOGIC;
SIGNAL wire_nlO1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOii_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOii_o : STD_LOGIC;
SIGNAL wire_nlOii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOil_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOil_o : STD_LOGIC;
SIGNAL wire_nlOil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOiO_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOiO_o : STD_LOGIC;
SIGNAL wire_nlOiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOli_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOli_o : STD_LOGIC;
SIGNAL wire_nlOli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOll_data : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_nlOll_o : STD_LOGIC;
SIGNAL wire_nlOll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w26w29w30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w26w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w48w49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_IB_FORCE_DISPARITY67w69w72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_n1l0l5w7w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_n1l0l5w7w10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_n1l0l5w7w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_nlOO0l329w331w332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_IB_FORCE_DISPARITY67w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_n1l0l5w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nlOO0l329w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_IB_FORCE_DISPARITY67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_tx_ctl_tc241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_ENDEC251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n10iO345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n110O254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n11Oi92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0i6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_n1l0l5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOO0i354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOO0l329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOO0O330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOOii355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_prbs_en249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_soft_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_tx_ctl_tc12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_tx_data_tc_range66w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nlOOOi349w350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOO1O351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nlOOOi349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL n101i : STD_LOGIC;
SIGNAL n101l : STD_LOGIC;
SIGNAL n10il : STD_LOGIC;
SIGNAL n10iO : STD_LOGIC;
SIGNAL n10Ol : STD_LOGIC;
SIGNAL n110i : STD_LOGIC;
SIGNAL n110l : STD_LOGIC;
SIGNAL n110O : STD_LOGIC;
SIGNAL n111i : STD_LOGIC;
SIGNAL n111l : STD_LOGIC;
SIGNAL n111O : STD_LOGIC;
SIGNAL n11Oi : STD_LOGIC;
SIGNAL n1i0i : STD_LOGIC;
SIGNAL n1l0i : STD_LOGIC;
SIGNAL n1l0l : STD_LOGIC;
SIGNAL n1lii : STD_LOGIC;
SIGNAL nlOllO : STD_LOGIC;
SIGNAL nlOlOi : STD_LOGIC;
SIGNAL nlOlOl : STD_LOGIC;
SIGNAL nlOlOO : STD_LOGIC;
SIGNAL nlOO0i : STD_LOGIC;
SIGNAL nlOO0l : STD_LOGIC;
SIGNAL nlOO0O : STD_LOGIC;
SIGNAL nlOO1i : STD_LOGIC;
SIGNAL nlOO1l : STD_LOGIC;
SIGNAL nlOO1O : STD_LOGIC;
SIGNAL nlOOii : STD_LOGIC;
SIGNAL nlOOil : STD_LOGIC;
SIGNAL nlOOiO : STD_LOGIC;
SIGNAL nlOOli : STD_LOGIC;
SIGNAL nlOOll : STD_LOGIC;
SIGNAL nlOOlO : STD_LOGIC;
SIGNAL nlOOOi : STD_LOGIC;
SIGNAL nlOOOl : STD_LOGIC;
SIGNAL nlOOOO : STD_LOGIC;
SIGNAL wire_w_tx_data_pg_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_tx_data_tc_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_tx_data_tc_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_w_lg_w_lg_w26w29w30w(0) <= wire_w_lg_w26w29w(0) AND nlOOO;
wire_w_lg_w26w29w(0) <= wire_w26w(0) AND wire_n1iiO12_w_lg_q28w(0);
wire_w_lg_w16w17w(0) <= wire_w16w(0) AND nlOOO;
wire_w_lg_w48w49w(0) <= wire_w48w(0) AND nlOOO;
wire_w26w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w25w(0) AND wire_w_lg_tx_ctl_tc12w(0);
wire_w16w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w13w(0) AND wire_n1iOO6_w_lg_q15w(0);
wire_w48w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w45w(0) AND wire_n10OO20_w_lg_q47w(0);
wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w25w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w(0) AND wire_n1ill10_w_lg_q24w(0);
wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w13w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w(0) AND wire_w_lg_tx_ctl_tc12w(0);
wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w37w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w(0) AND nlOOO;
wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w45w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w(0) AND wire_w_lg_tx_ctl_tc12w(0);
wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w21w22w(0) <= wire_w_lg_w_lg_w_lg_n1l0l5w7w21w(0) AND GE_XAUI_SEL;
wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w10w11w(0) <= wire_w_lg_w_lg_w_lg_n1l0l5w7w10w(0) AND GE_XAUI_SEL;
wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w(0) <= wire_w_lg_w_lg_w_lg_n1l0l5w7w35w(0) AND wire_w_lg_tx_ctl_tc12w(0);
wire_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w44w(0) <= wire_w_lg_w_lg_w_lg_n1l0l5w7w35w(0) AND wire_n1i1l18_w_lg_q43w(0);
wire_w_lg_w_lg_w_lg_IB_FORCE_DISPARITY67w69w72w(0) <= wire_w_lg_w_lg_IB_FORCE_DISPARITY67w69w(0) AND wire_n10lO22_w_lg_q71w(0);
wire_w_lg_w_lg_w_lg_n1l0l5w7w21w(0) <= wire_w_lg_w_lg_n1l0l5w7w(0) AND wire_n1iOi8_w_lg_q20w(0);
wire_w_lg_w_lg_w_lg_n1l0l5w7w10w(0) <= wire_w_lg_w_lg_n1l0l5w7w(0) AND wire_n1l1l4_w_lg_q9w(0);
wire_w_lg_w_lg_w_lg_n1l0l5w7w35w(0) <= wire_w_lg_w_lg_n1l0l5w7w(0) AND GE_XAUI_SEL;
wire_w_lg_w_lg_w_lg_nlOO0l329w331w332w(0) <= wire_w_lg_w_lg_nlOO0l329w331w(0) AND nlOOil;
wire_w_lg_w_lg_IB_FORCE_DISPARITY67w69w(0) <= wire_w_lg_IB_FORCE_DISPARITY67w(0) AND wire_nlOOi_w_lg_nlOOl68w(0);
wire_w_lg_w_lg_n1l0l5w7w(0) <= wire_w_lg_n1l0l5w(0) AND wire_w_lg_n1l0i6w(0);
wire_w_lg_w_lg_nlOO0l329w331w(0) <= wire_w_lg_nlOO0l329w(0) AND wire_w_lg_nlOO0O330w(0);
wire_w_lg_IB_FORCE_DISPARITY67w(0) <= IB_FORCE_DISPARITY AND tx_data_9_tc;
wire_w_lg_tx_ctl_tc241w(0) <= tx_ctl_tc AND wire_w_lg_w_tx_data_tc_range66w228w(0);
wire_w_lg_ENDEC251w(0) <= NOT ENDEC;
wire_w_lg_n10iO345w(0) <= NOT n10iO;
wire_w_lg_n110O254w(0) <= NOT n110O;
wire_w_lg_n11Oi92w(0) <= NOT n11Oi;
wire_w_lg_n1l0i6w(0) <= NOT n1l0i;
wire_w_lg_n1l0l5w(0) <= NOT n1l0l;
wire_w_lg_nlOO0i354w(0) <= NOT nlOO0i;
wire_w_lg_nlOO0l329w(0) <= NOT nlOO0l;
wire_w_lg_nlOO0O330w(0) <= NOT nlOO0O;
wire_w_lg_nlOOii355w(0) <= NOT nlOOii;
wire_w_lg_prbs_en249w(0) <= NOT prbs_en;
wire_w_lg_soft_reset2w(0) <= NOT soft_reset;
wire_w_lg_tx_ctl_tc12w(0) <= NOT tx_ctl_tc;
wire_w_lg_w_tx_data_tc_range66w228w(0) <= NOT wire_w_tx_data_tc_range66w(0);
wire_w_lg_w_lg_nlOOOi349w350w(0) <= wire_w_lg_nlOOOi349w(0) OR nlOO1l;
wire_w_lg_nlOO1O351w(0) <= nlOO1O OR wire_w_lg_w_lg_nlOOOi349w350w(0);
wire_w_lg_nlOOOi349w(0) <= nlOOOi OR wire_niiO_w_lg_w_lg_dataout286w348w(0);
n101i <= (wire_w_lg_ENDEC251w(0) AND wire_w_lg_prbs_en249w(0));
n101l <= (ENDEC AND wire_w_lg_prbs_en249w(0));
n10il <= (((((((wire_w_lg_tx_ctl_tc241w(0) AND (NOT tx_data_tc(1))) AND tx_data_tc(2)) AND tx_data_tc(3)) AND tx_data_tc(4)) AND tx_data_tc(5)) AND (NOT tx_data_tc(6))) AND tx_data_tc(7));
n10iO <= (wire_nl_w_lg_nO73w(0) OR (NOT (n10li24 XOR n10li23)));
n10Ol <= (wire_nl_w_lg_nO4w(0) AND wire_w_lg_w48w49w(0));
n110i <= (wire_n0i0l_w_lg_w_lg_w_lg_dataout253w256w257w(0) XOR wire_n0i0l_w_lg_w_lg_dataout253w258w(0));
n110l <= (wire_nill_dataout AND wire_nili_dataout);
n110O <= (n110l OR n111l);
n111i <= (wire_nilO_w_lg_dataout261w(0) AND n111l);
n111l <= (wire_nill_w_lg_dataout265w(0) AND wire_nili_w_lg_dataout312w(0));
n111O <= (wire_nilO_dataout AND (wire_nill_dataout AND (wire_nili_dataout AND (((wire_n0i0l_w_lg_dataout253w(0) AND (wire_niiO_w_lg_dataout267w(0) AND ((((wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_w_lg_dataout269w270w(0))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_dataout274w(0)))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_dataout AND nlOOOO))) OR wire_niil_w_lg_dataout282w(0)))) OR wire_n0i0l_w_lg_dataout300w(0)) OR wire_nilO_w_lg_dataout304w(0)))));
n11Oi <= ((n101l OR n101i) OR (NOT (n11Ol32 XOR n11Ol31)));
n1i0i <= (nO AND (wire_w_lg_w_lg_w_lg_w_lg_w_lg_n1l0l5w7w35w36w37w(0) AND (n1i0l16 XOR n1i0l15)));
n1l0i <= ((((((((wire_w_lg_tx_ctl_tc12w(0) AND wire_w_lg_w_tx_data_tc_range66w228w(0)) AND tx_data_tc(1)) AND (NOT tx_data_tc(2))) AND (NOT tx_data_tc(3))) AND (NOT tx_data_tc(4))) AND (NOT tx_data_tc(5))) AND tx_data_tc(6)) AND (NOT tx_data_tc(7)));
n1l0l <= ((((((((wire_w_lg_tx_ctl_tc12w(0) AND tx_data_tc(0)) AND (NOT tx_data_tc(1))) AND tx_data_tc(2)) AND (NOT tx_data_tc(3))) AND tx_data_tc(4)) AND tx_data_tc(5)) AND (NOT tx_data_tc(6))) AND tx_data_tc(7));
n1lii <= '1';
nlOllO <= wire_ni0O_w_lg_dataout316w(0);
nlOlOi <= wire_ni0O_w_lg_w_lg_dataout269w315w(0);
nlOlOl <= wire_ni0O_w_lg_dataout274w(0);
nlOlOO <= wire_ni0O_w_lg_w_lg_dataout269w270w(0);
nlOO0i <= (wire_n1l_w_lg_w_lg_dataout327w328w(0) OR wire_niiO_w_lg_dataout333w(0));
nlOO0l <= ((((wire_niil_w_lg_dataout266w(0) AND (wire_niii_dataout AND nlOllO)) OR wire_niil_w_lg_dataout395w(0)) OR wire_niil_w_lg_dataout294w(0)) OR wire_niil_w_lg_dataout297w(0));
nlOO0O <= ((((((wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_dataout316w(0))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_dataout AND nlOlOO))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_dataout AND nlOlOl))) OR wire_niil_w_lg_dataout378w(0)) OR wire_niil_w_lg_dataout381w(0)) OR wire_niil_w_lg_dataout384w(0));
nlOO1i <= (wire_niil_w_lg_w343w344w(0) XOR (wire_w_lg_n10iO345w(0) AND wire_w_lg_nlOO1O351w(0)));
nlOO1l <= (wire_niiO_dataout AND ((wire_niil_dataout AND nlOOli) OR nlOO0l));
nlOO1O <= (wire_n1l_dataout AND nlOO0O);
nlOOii <= (nlOOiO OR (wire_niiO_dataout AND nlOOil));
nlOOil <= (wire_niil_w_lg_dataout266w(0) OR wire_niii_w_lg_dataout325w(0));
nlOOiO <= (wire_niiO_w_lg_dataout286w(0) AND nlOOli);
nlOOli <= ((((wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_w_lg_dataout269w270w(0))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_dataout274w(0)))) OR (wire_niil_w_lg_dataout266w(0) AND (wire_niii_dataout AND nlOlOi))) OR wire_niil_w_lg_dataout390w(0));
nlOOll <= (wire_niil_dataout AND wire_niii_w_lg_dataout336w(0));
nlOOlO <= (wire_niil_w_lg_dataout266w(0) AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_w_lg_dataout269w315w(0)));
nlOOOi <= (nlOOll OR nlOOlO);
nlOOOl <= wire_ni0O_w_lg_dataout316w(0);
nlOOOO <= wire_ni0O_w_lg_w_lg_dataout269w315w(0);
PUDR <= ( wire_nlOll_o & wire_nlOli_o & wire_nlOiO_o & wire_nlOil_o & wire_nlOii_o & wire_nlO0O_o & wire_nlO0l_o & wire_nlO0i_o & wire_nlO1O_o & wire_nlO1l_o);
TXLP10B <= ( n0il & n0ii & n00O & n00l & n00i & n01O & n01l & n01i & n1OO & n1lO);
wire_w_tx_data_pg_range108w(0) <= tx_data_pg(8);
wire_w_tx_data_tc_range66w(0) <= tx_data_tc(0);
wire_w_tx_data_tc_range58w(0) <= tx_data_tc(4);
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n100l27 <= n100l28;
END IF;
if (now = 0 ns) then
n100l27 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n100l28 <= n100l27;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n101O29 <= n101O30;
END IF;
if (now = 0 ns) then
n101O29 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n101O30 <= n101O29;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10ii25 <= n10ii26;
END IF;
if (now = 0 ns) then
n10ii25 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10ii26 <= n10ii25;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10li23 <= n10li24;
END IF;
if (now = 0 ns) then
n10li23 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10li24 <= n10li23;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10lO21 <= n10lO22;
END IF;
if (now = 0 ns) then
n10lO21 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10lO22 <= n10lO21;
END IF;
END PROCESS;
wire_n10lO22_w_lg_q71w(0) <= n10lO22 XOR n10lO21;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10OO19 <= n10OO20;
END IF;
if (now = 0 ns) then
n10OO19 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n10OO20 <= n10OO19;
END IF;
END PROCESS;
wire_n10OO20_w_lg_q47w(0) <= n10OO20 XOR n10OO19;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11ii43 <= n11ii44;
END IF;
if (now = 0 ns) then
n11ii43 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11ii44 <= n11ii43;
END IF;
END PROCESS;
wire_n11ii44_w_lg_w_lg_q155w156w(0) <= wire_n11ii44_w_lg_q155w(0) AND wire_w_tx_data_tc_range58w(0);
wire_n11ii44_w_lg_q155w(0) <= n11ii44 XOR n11ii43;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11il41 <= n11il42;
END IF;
if (now = 0 ns) then
n11il41 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11il42 <= n11il41;
END IF;
END PROCESS;
wire_n11il42_w_lg_w_lg_q131w132w(0) <= wire_n11il42_w_lg_q131w(0) AND n101l;
wire_n11il42_w_lg_q131w(0) <= n11il42 XOR n11il41;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11iO39 <= n11iO40;
END IF;
if (now = 0 ns) then
n11iO39 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11iO40 <= n11iO39;
END IF;
END PROCESS;
wire_n11iO40_w_lg_w_lg_q125w126w(0) <= wire_n11iO40_w_lg_q125w(0) AND n1il;
wire_n11iO40_w_lg_q125w(0) <= n11iO40 XOR n11iO39;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11li37 <= n11li38;
END IF;
if (now = 0 ns) then
n11li37 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11li38 <= n11li37;
END IF;
END PROCESS;
wire_n11li38_w_lg_w_lg_q113w114w(0) <= wire_n11li38_w_lg_q113w(0) AND tx_ctl_tc;
wire_n11li38_w_lg_q113w(0) <= n11li38 XOR n11li37;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11ll35 <= n11ll36;
END IF;
if (now = 0 ns) then
n11ll35 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11ll36 <= n11ll35;
END IF;
END PROCESS;
wire_n11ll36_w_lg_w_lg_q109w110w(0) <= wire_n11ll36_w_lg_q109w(0) AND wire_w_tx_data_pg_range108w(0);
wire_n11ll36_w_lg_q109w(0) <= n11ll36 XOR n11ll35;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11lO33 <= n11lO34;
END IF;
if (now = 0 ns) then
n11lO33 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11lO34 <= n11lO33;
END IF;
END PROCESS;
wire_n11lO34_w_lg_w_lg_q95w96w(0) <= wire_n11lO34_w_lg_q95w(0) AND n101i;
wire_n11lO34_w_lg_q95w(0) <= n11lO34 XOR n11lO33;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11Ol31 <= n11Ol32;
END IF;
if (now = 0 ns) then
n11Ol31 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n11Ol32 <= n11Ol31;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1i0l15 <= n1i0l16;
END IF;
if (now = 0 ns) then
n1i0l15 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1i0l16 <= n1i0l15;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1i1l17 <= n1i1l18;
END IF;
if (now = 0 ns) then
n1i1l17 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1i1l18 <= n1i1l17;
END IF;
END PROCESS;
wire_n1i1l18_w_lg_q43w(0) <= n1i1l18 XOR n1i1l17;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iii13 <= n1iii14;
END IF;
if (now = 0 ns) then
n1iii13 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iii14 <= n1iii13;
END IF;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iiO11 <= n1iiO12;
END IF;
if (now = 0 ns) then
n1iiO11 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iiO12 <= n1iiO11;
END IF;
END PROCESS;
wire_n1iiO12_w_lg_q28w(0) <= n1iiO12 XOR n1iiO11;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1ill10 <= n1ill9;
END IF;
END PROCESS;
wire_n1ill10_w_lg_q24w(0) <= n1ill10 XOR n1ill9;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1ill9 <= n1ill10;
END IF;
if (now = 0 ns) then
n1ill9 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iOi7 <= n1iOi8;
END IF;
if (now = 0 ns) then
n1iOi7 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iOi8 <= n1iOi7;
END IF;
END PROCESS;
wire_n1iOi8_w_lg_q20w(0) <= n1iOi8 XOR n1iOi7;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iOO5 <= n1iOO6;
END IF;
if (now = 0 ns) then
n1iOO5 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1iOO6 <= n1iOO5;
END IF;
END PROCESS;
wire_n1iOO6_w_lg_q15w(0) <= n1iOO6 XOR n1iOO5;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1l1l3 <= n1l1l4;
END IF;
if (now = 0 ns) then
n1l1l3 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1l1l4 <= n1l1l3;
END IF;
END PROCESS;
wire_n1l1l4_w_lg_q9w(0) <= n1l1l4 XOR n1l1l3;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1liO1 <= n1liO2;
END IF;
if (now = 0 ns) then
n1liO1 <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk)
BEGIN
IF (tx_clk = '1' AND tx_clk'event) THEN n1liO2 <= n1liO1;
END IF;
END PROCESS;
PROCESS (tx_clk, soft_reset)
BEGIN
IF (soft_reset = '1') THEN
n10i <= '1';
n10l <= '1';
n10O <= '1';
n11O <= '1';
n1ii <= '1';
n1li <= '1';
ELSIF (tx_clk = '1' AND tx_clk'event) THEN
n10i <= wire_n0lil_dataout;
n10l <= wire_n0liO_dataout;
n10O <= wire_n0lli_dataout;
n11O <= wire_n0lii_dataout;
n1ii <= wire_niOii_dataout;
n1li <= wire_niOiO_dataout;
END IF;
if (now = 0 ns) then
n10i <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n10l <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n10O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n11O <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1ii <= '1' after 1 ps;
end if;
if (now = 0 ns) then
n1li <= '1' after 1 ps;
end if;
END PROCESS;
PROCESS (tx_clk, wire_nl_CLRN)
BEGIN
IF (wire_nl_CLRN = '0') THEN
n00i <= '0';
n00l <= '0';
n00O <= '0';
n01i <= '0';
n01l <= '0';
n01O <= '0';
n0ii <= '0';
n0il <= '0';
n11i <= '0';
n11l <= '0';
n1il <= '0';
n1ll <= '0';
n1lO <= '0';
n1OO <= '0';
nlOOO <= '0';
nO <= '0';
ELSIF (tx_clk = '1' AND tx_clk'event) THEN
n00i <= wire_nlOii_o;
n00l <= wire_nlOil_o;
n00O <= wire_nlOiO_o;
n01i <= wire_nlO0i_o;
n01l <= wire_nlO0l_o;
n01O <= wire_nlO0O_o;
n0ii <= wire_nlOli_o;
n0il <= wire_nlOll_o;
n11i <= wire_n0l0l_dataout;
n11l <= wire_n0l0O_dataout;
n1il <= wire_niOil_dataout;
n1ll <= wire_niOli_dataout;
n1lO <= wire_nlO1l_o;
n1OO <= wire_nlO1O_o;
nlOOO <= n10il;
nO <= wire_nilll_dataout;
END IF;
END PROCESS;
wire_nl_CLRN <= ((n1liO2 XOR n1liO1) AND wire_w_lg_soft_reset2w(0));
wire_nl_w_lg_nO31w(0) <= nO AND wire_w_lg_w_lg_w26w29w30w(0);
wire_nl_w_lg_nO4w(0) <= NOT nO;
wire_nl_w_lg_nO73w(0) <= nO OR wire_w_lg_w_lg_w_lg_IB_FORCE_DISPARITY67w69w72w(0);
PROCESS (tx_clk, wire_nlOOi_CLRN)
BEGIN
IF (wire_nlOOi_CLRN = '0') THEN
nlOOl <= '0';
ELSIF (tx_clk = '1' AND tx_clk'event) THEN
IF (wire_nlOOi_ENA = '1') THEN
nlOOl <= n1lii;
END IF;
END IF;
END PROCESS;
wire_nlOOi_CLRN <= ((n10ii26 XOR n10ii25) AND wire_w_lg_soft_reset2w(0));
wire_nlOOi_ENA <= (((wire_w_lg_IB_FORCE_DISPARITY67w(0) AND (n100l28 XOR n100l27)) AND wire_nlOOi_w_lg_nlOOl68w(0)) AND (n101O30 XOR n101O29));
wire_nlOOi_w_lg_nlOOl68w(0) <= NOT nlOOl;
wire_n0i0l_dataout <= wire_w_lg_n10iO345w(0) WHEN ((nlOOiO OR ((wire_n1l_dataout OR nlOOlO) OR nlOOll)) OR nlOO1l) = '1' ELSE n10iO;
wire_n0i0l_w_lg_w_lg_dataout253w256w(0) <= wire_n0i0l_w_lg_dataout253w(0) AND wire_n1l_w_lg_dataout255w(0);
wire_n0i0l_w_lg_w_lg_dataout253w258w(0) <= wire_n0i0l_w_lg_dataout253w(0) AND n110O;
wire_n0i0l_w_lg_dataout300w(0) <= wire_n0i0l_dataout AND wire_niiO_w_lg_w_lg_w_lg_dataout286w287w299w(0);
wire_n0i0l_w_lg_dataout253w(0) <= NOT wire_n0i0l_dataout;
wire_n0i0l_w_lg_w_lg_w_lg_dataout253w256w257w(0) <= wire_n0i0l_w_lg_w_lg_dataout253w256w(0) OR n110l;
wire_n0l0l_dataout <= wire_ni0l_w_lg_dataout273w(0) WHEN nlOO1i = '1' ELSE wire_ni0l_dataout;
wire_n0l0O_dataout <= wire_ni1Oi_w_lg_dataout358w(0) WHEN nlOO1i = '1' ELSE wire_ni1Oi_dataout;
wire_n0lii_dataout <= wire_ni1ii_w_lg_dataout357w(0) WHEN nlOO1i = '1' ELSE wire_ni1ii_dataout;
wire_n0lil_dataout <= wire_ni10O_w_lg_dataout356w(0) WHEN nlOO1i = '1' ELSE wire_ni10O_dataout;
wire_n0liO_dataout <= wire_w_lg_nlOOii355w(0) WHEN nlOO1i = '1' ELSE nlOOii;
wire_n0lli_dataout <= wire_w_lg_nlOO0i354w(0) WHEN nlOO1i = '1' ELSE nlOO0i;
wire_n0lO_dataout <= tx_data_tc(0) WHEN INDV = '1' ELSE tx_data_ts(0);
wire_n0Oi_dataout <= tx_data_tc(1) WHEN INDV = '1' ELSE tx_data_ts(1);
wire_n0Ol_dataout <= tx_data_tc(2) WHEN INDV = '1' ELSE tx_data_ts(2);
wire_n0OO_dataout <= tx_data_tc(3) WHEN INDV = '1' ELSE tx_data_ts(3);
wire_n1i_dataout <= tx_ctl_tc WHEN INDV = '1' ELSE tx_ctl_ts;
wire_n1l_dataout <= wire_n1O_dataout AND NOT((wire_nl_w_lg_nO31w(0) AND (n1iii14 XOR n1iii13)));
wire_n1l_w_lg_w_lg_dataout327w328w(0) <= wire_n1l_w_lg_dataout327w(0) AND nlOO0O;
wire_n1l_w_lg_dataout255w(0) <= wire_n1l_dataout AND wire_w_lg_n110O254w(0);
wire_n1l_w_lg_dataout302w(0) <= wire_n1l_dataout AND wire_nili_dataout;
wire_n1l_w_lg_dataout327w(0) <= wire_n1l_dataout OR wire_niiO_w_lg_dataout286w(0);
wire_n1O_dataout <= wire_n1i_dataout AND NOT((wire_nl_w_lg_nO4w(0) AND wire_w_lg_w16w17w(0)));
wire_ni0i_dataout <= tx_data_tc(7) WHEN INDV = '1' ELSE tx_data_ts(7);
wire_ni0l_dataout <= wire_niOi_dataout AND NOT(n1i0i);
wire_ni0l_w_lg_dataout273w(0) <= NOT wire_ni0l_dataout;
wire_ni0O_dataout <= wire_niOl_dataout AND NOT(n1i0i);
wire_ni0O_w_lg_w_lg_dataout269w315w(0) <= wire_ni0O_w_lg_dataout269w(0) AND wire_ni0l_w_lg_dataout273w(0);
wire_ni0O_w_lg_w_lg_dataout269w270w(0) <= wire_ni0O_w_lg_dataout269w(0) AND wire_ni0l_dataout;
wire_ni0O_w_lg_dataout274w(0) <= wire_ni0O_dataout AND wire_ni0l_w_lg_dataout273w(0);
wire_ni0O_w_lg_dataout316w(0) <= wire_ni0O_dataout AND wire_ni0l_dataout;
wire_ni0O_w_lg_dataout269w(0) <= NOT wire_ni0O_dataout;
wire_ni0O_w_lg_dataout324w(0) <= wire_ni0O_dataout OR wire_ni0l_dataout;
wire_ni10O_dataout <= wire_niil_w_lg_dataout266w(0) WHEN nlOOll = '1' ELSE wire_niil_dataout;
wire_ni10O_w_lg_dataout356w(0) <= NOT wire_ni10O_dataout;
wire_ni1i_dataout <= tx_data_tc(4) WHEN INDV = '1' ELSE tx_data_ts(4);
wire_ni1ii_dataout <= wire_niii_w_lg_dataout268w(0) WHEN ((wire_niiO_dataout AND (wire_niil_dataout AND (wire_niii_w_lg_dataout268w(0) AND wire_ni0O_w_lg_w_lg_dataout269w315w(0)))) OR nlOOlO) = '1' ELSE wire_niii_dataout;
wire_ni1ii_w_lg_dataout357w(0) <= NOT wire_ni1ii_dataout;
wire_ni1l_dataout <= tx_data_tc(5) WHEN INDV = '1' ELSE tx_data_ts(5);
wire_ni1O_dataout <= tx_data_tc(6) WHEN INDV = '1' ELSE tx_data_ts(6);
wire_ni1Oi_dataout <= wire_ni0O_w_lg_dataout269w(0) WHEN nlOOOi = '1' ELSE wire_ni0O_dataout;
wire_ni1Oi_w_lg_dataout358w(0) <= NOT wire_ni1Oi_dataout;
wire_niii_dataout <= wire_niOO_dataout AND NOT(n1i0i);
wire_niii_w_lg_w_lg_dataout268w394w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOllO;
wire_niii_w_lg_w_lg_dataout268w389w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOlOi;
wire_niii_w_lg_w_lg_dataout268w380w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOlOl;
wire_niii_w_lg_w_lg_dataout268w377w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOlOO;
wire_niii_w_lg_w_lg_dataout268w290w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOOOl;
wire_niii_w_lg_w_lg_dataout268w281w(0) <= wire_niii_w_lg_dataout268w(0) AND nlOOOO;
wire_niii_w_lg_dataout383w(0) <= wire_niii_dataout AND wire_ni0O_w_lg_w_lg_dataout269w315w(0);
wire_niii_w_lg_dataout293w(0) <= wire_niii_dataout AND wire_ni0O_w_lg_w_lg_dataout269w270w(0);
wire_niii_w_lg_dataout296w(0) <= wire_niii_dataout AND wire_ni0O_w_lg_dataout274w(0);
wire_niii_w_lg_dataout336w(0) <= wire_niii_dataout AND wire_ni0O_w_lg_dataout316w(0);
wire_niii_w_lg_dataout288w(0) <= wire_niii_dataout AND nlOOOl;
wire_niii_w_lg_dataout268w(0) <= NOT wire_niii_dataout;
wire_niii_w_lg_dataout325w(0) <= wire_niii_dataout OR wire_ni0O_w_lg_dataout324w(0);
wire_niil_dataout <= wire_nl1i_dataout AND NOT(n1i0i);
wire_niil_w_lg_w_lg_dataout266w337w(0) <= wire_niil_w_lg_dataout266w(0) AND wire_niii_w_lg_dataout336w(0);
wire_niil_w_lg_w_lg_dataout266w289w(0) <= wire_niil_w_lg_dataout266w(0) AND wire_niii_w_lg_dataout288w(0);
wire_niil_w_lg_w_lg_dataout266w346w(0) <= wire_niil_w_lg_dataout266w(0) AND nlOO0l;
wire_niil_w_lg_dataout395w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w394w(0);
wire_niil_w_lg_dataout390w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w389w(0);
wire_niil_w_lg_dataout381w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w380w(0);
wire_niil_w_lg_dataout378w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w377w(0);
wire_niil_w_lg_dataout291w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w290w(0);
wire_niil_w_lg_dataout282w(0) <= wire_niil_dataout AND wire_niii_w_lg_w_lg_dataout268w281w(0);
wire_niil_w_lg_dataout384w(0) <= wire_niil_dataout AND wire_niii_w_lg_dataout383w(0);
wire_niil_w_lg_dataout294w(0) <= wire_niil_dataout AND wire_niii_w_lg_dataout293w(0);
wire_niil_w_lg_dataout297w(0) <= wire_niil_dataout AND wire_niii_w_lg_dataout296w(0);
wire_niil_w_lg_dataout266w(0) <= NOT wire_niil_dataout;
wire_niil_w_lg_w_lg_w_lg_dataout266w337w339w(0) <= wire_niil_w_lg_w_lg_dataout266w337w(0) OR wire_niiO_w_lg_dataout338w(0);
wire_niil_w_lg_w_lg_w_lg_dataout266w289w292w(0) <= wire_niil_w_lg_w_lg_dataout266w289w(0) OR wire_niil_w_lg_dataout291w(0);
wire_niil_w_lg_w_lg_w_lg_dataout266w346w347w(0) <= wire_niil_w_lg_w_lg_dataout266w346w(0) OR nlOOli;
wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w337w339w341w(0) <= wire_niil_w_lg_w_lg_w_lg_dataout266w337w339w(0) OR wire_niiO_w_lg_dataout340w(0);
wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w289w292w295w(0) <= wire_niil_w_lg_w_lg_w_lg_dataout266w289w292w(0) OR wire_niil_w_lg_dataout294w(0);
wire_niil_w343w(0) <= wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w337w339w341w(0) OR wire_niiO_w_lg_dataout342w(0);
wire_niil_w298w(0) <= wire_niil_w_lg_w_lg_w_lg_w_lg_dataout266w289w292w295w(0) OR wire_niil_w_lg_dataout297w(0);
wire_niil_w_lg_w343w344w(0) <= wire_niil_w343w(0) OR nlOO1O;
wire_niiO_dataout <= wire_nl1l_dataout OR n1i0i;
wire_niiO_w_lg_w_lg_w_lg_dataout286w287w299w(0) <= wire_niiO_w_lg_w_lg_dataout286w287w(0) AND wire_niil_w298w(0);
wire_niiO_w_lg_w_lg_dataout286w348w(0) <= wire_niiO_w_lg_dataout286w(0) AND wire_niil_w_lg_w_lg_w_lg_dataout266w346w347w(0);
wire_niiO_w_lg_w_lg_dataout286w287w(0) <= wire_niiO_w_lg_dataout286w(0) AND wire_niil_dataout;
wire_niiO_w_lg_dataout333w(0) <= wire_niiO_dataout AND wire_w_lg_w_lg_w_lg_nlOO0l329w331w332w(0);
wire_niiO_w_lg_dataout267w(0) <= wire_niiO_dataout AND wire_niil_w_lg_dataout266w(0);
wire_niiO_w_lg_dataout342w(0) <= wire_niiO_dataout AND nlOO0l;
wire_niiO_w_lg_dataout340w(0) <= wire_niiO_dataout AND nlOOll;
wire_niiO_w_lg_dataout338w(0) <= wire_niiO_dataout AND nlOOlO;
wire_niiO_w_lg_dataout286w(0) <= NOT wire_niiO_dataout;
wire_nili_dataout <= wire_nl1O_dataout AND NOT(n1i0i);
wire_nili_w_lg_dataout312w(0) <= NOT wire_nili_dataout;
wire_nill_dataout <= wire_nl0i_dataout OR n1i0i;
wire_nill_w_lg_dataout303w(0) <= wire_nill_dataout AND wire_n1l_w_lg_dataout302w(0);
wire_nill_w_lg_dataout265w(0) <= NOT wire_nill_dataout;
wire_nilll_dataout <= wire_n0i0l_w_lg_dataout253w(0) WHEN (n111i OR (wire_nilO_dataout AND n110O)) = '1' ELSE wire_n0i0l_dataout;
wire_nilO_dataout <= wire_nl0l_dataout AND NOT(n1i0i);
wire_nilO_w_lg_dataout304w(0) <= wire_nilO_dataout AND wire_nill_w_lg_dataout303w(0);
wire_nilO_w_lg_dataout261w(0) <= NOT wire_nilO_dataout;
wire_nilOl_dataout <= wire_nilOO_dataout OR n111O;
wire_nilOl_w_lg_dataout260w(0) <= NOT wire_nilOl_dataout;
wire_nilOO_dataout <= wire_w_lg_n110O254w(0) AND NOT(wire_nilO_dataout);
wire_niO0i_dataout <= wire_nill_w_lg_dataout265w(0) WHEN n111i = '1' ELSE wire_nill_dataout;
wire_niO0i_w_lg_dataout262w(0) <= NOT wire_niO0i_dataout;
wire_niO0O_dataout <= wire_nili_dataout AND NOT(n111O);
wire_niO0O_w_lg_dataout263w(0) <= NOT wire_niO0O_dataout;
wire_niOi_dataout <= wire_n0lO_dataout OR n10Ol;
wire_niOii_dataout <= wire_niO0O_w_lg_dataout263w(0) WHEN n110i = '1' ELSE wire_niO0O_dataout;
wire_niOil_dataout <= wire_niO0i_w_lg_dataout262w(0) WHEN n110i = '1' ELSE wire_niO0i_dataout;
wire_niOiO_dataout <= wire_nilO_w_lg_dataout261w(0) WHEN n110i = '1' ELSE wire_nilO_dataout;
wire_niOl_dataout <= wire_n0Oi_dataout AND NOT(n10Ol);
wire_niOli_dataout <= wire_nilOl_w_lg_dataout260w(0) WHEN n110i = '1' ELSE wire_nilOl_dataout;
wire_niOO_dataout <= wire_n0Ol_dataout OR n10Ol;
wire_nl0i_dataout <= wire_ni1O_dataout OR n10Ol;
wire_nl0l_dataout <= wire_ni0i_dataout OR n10Ol;
wire_nl1i_dataout <= wire_n0OO_dataout AND NOT(n10Ol);
wire_nl1l_dataout <= wire_ni1i_dataout AND NOT(n10Ol);
wire_nl1O_dataout <= wire_ni1l_dataout AND NOT(n10Ol);
wire_nlO0i_data <= ( n11O & tx_data_tc(2) & tx_data_pg(2));
wire_nlO0i_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlO0i : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlO0i_data,
o => wire_nlO0i_o,
sel => wire_nlO0i_sel
);
wire_nlO0l_data <= ( n10i & tx_data_tc(3) & tx_data_pg(3));
wire_nlO0l_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlO0l : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlO0l_data,
o => wire_nlO0l_o,
sel => wire_nlO0l_sel
);
wire_nlO0O_data <= ( n10l & wire_n11ii44_w_lg_w_lg_q155w156w & tx_data_pg(4));
wire_nlO0O_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlO0O : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlO0O_data,
o => wire_nlO0O_o,
sel => wire_nlO0O_sel
);
wire_nlO1l_data <= ( n11i & tx_data_tc(0) & tx_data_pg(0));
wire_nlO1l_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlO1l : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlO1l_data,
o => wire_nlO1l_o,
sel => wire_nlO1l_sel
);
wire_nlO1O_data <= ( n11l & tx_data_tc(1) & tx_data_pg(1));
wire_nlO1O_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlO1O : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlO1O_data,
o => wire_nlO1O_o,
sel => wire_nlO1O_sel
);
wire_nlOii_data <= ( n10O & tx_data_tc(5) & tx_data_pg(5));
wire_nlOii_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlOii : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOii_data,
o => wire_nlOii_o,
sel => wire_nlOii_sel
);
wire_nlOil_data <= ( n1ii & tx_data_tc(6) & tx_data_pg(6));
wire_nlOil_sel <= ( wire_n11il42_w_lg_w_lg_q131w132w & n101i & wire_w_lg_n11Oi92w);
nlOil : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOil_data,
o => wire_nlOil_o,
sel => wire_nlOil_sel
);
wire_nlOiO_data <= ( wire_n11iO40_w_lg_w_lg_q125w126w & tx_data_tc(7) & tx_data_pg(7));
wire_nlOiO_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlOiO : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOiO_data,
o => wire_nlOiO_o,
sel => wire_nlOiO_sel
);
wire_nlOli_data <= ( n1li & wire_n11li38_w_lg_w_lg_q113w114w & wire_n11ll36_w_lg_w_lg_q109w110w);
wire_nlOli_sel <= ( n101l & n101i & wire_w_lg_n11Oi92w);
nlOli : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOli_data,
o => wire_nlOli_o,
sel => wire_nlOli_sel
);
wire_nlOll_data <= ( n1ll & tx_data_9_tc & tx_data_pg(9));
wire_nlOll_sel <= ( n101l & wire_n11lO34_w_lg_w_lg_q95w96w & wire_w_lg_n11Oi92w);
nlOll : oper_selector
GENERIC MAP (
width_data => 3,
width_sel => 3
)
PORT MAP (
data => wire_nlOll_data,
o => wire_nlOll_o,
sel => wire_nlOll_sel
);
END RTL; --stratixgx_hssi_tx_enc_rtl
--synopsys translate_on
--VALID FILE
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_8b10b_ENCODER
--
--/////////////////////////////////////////////////////////////////////////////
library IEEE, stratixgx_gxb;
use IEEE.std_logic_1164.all;
ENTITY stratixgx_8b10b_encoder IS
GENERIC (
transmit_protocol : string := "none";
use_8b_10b_mode : string := "true";
force_disparity_mode : string := "false");
PORT (
clk : IN std_logic;
reset : IN std_logic;
xgmctrl : IN std_logic;
kin : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
datain : IN std_logic_vector(7 DOWNTO 0);
forcedisparity : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
parafbkdataout : OUT std_logic_vector(9 DOWNTO 0));
END stratixgx_8b10b_encoder;
ARCHITECTURE auto_translated OF stratixgx_8b10b_encoder IS
COMPONENT stratixgx_hssi_tx_enc_rtl
PORT (
tx_clk : IN std_logic;
soft_reset : IN std_logic;
INDV : IN std_logic;
ENDEC : IN std_logic;
GE_XAUI_SEL : IN std_logic;
IB_FORCE_DISPARITY : IN std_logic;
prbs_en : IN std_logic;
tx_ctl_ts : IN std_logic;
tx_ctl_tc : IN std_logic;
tx_data_ts : IN std_logic_vector(7 DOWNTO 0);
tx_data_tc : IN std_logic_vector(7 DOWNTO 0);
tx_data_9_tc : IN std_logic;
tx_data_pg : IN std_logic_vector(9 DOWNTO 0);
PUDR : OUT std_logic_vector(9 DOWNTO 0);
TXLP10B : OUT std_logic_vector(9 DOWNTO 0));
END COMPONENT;
-- CORE MODULE INPUTs
SIGNAL tx_clk : std_logic;
SIGNAL soft_reset : std_logic;
SIGNAL INDV : std_logic;
SIGNAL ENDEC : std_logic;
SIGNAL GE_XAUI_SEL : std_logic;
SIGNAL IB_FORCE_DISPARITY : std_logic;
SIGNAL prbs_en : std_logic;
SIGNAL tx_ctl_ts : std_logic;
SIGNAL tx_ctl_tc : std_logic;
SIGNAL tx_data_ts : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_tc : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_tc : std_logic;
SIGNAL tx_data_pg : std_logic_vector(9 DOWNTO 0);
-- CORE MODULE OUTPUTs
SIGNAL TXLP10B : std_logic_vector(9 DOWNTO 0);
SIGNAL PUDR : std_logic_vector(9 DOWNTO 0);
SIGNAL temp_xhdl3 : std_logic;
SIGNAL temp_xhdl4 : std_logic;
SIGNAL temp_xhdl5 : std_logic;
SIGNAL temp_xhdl6 : std_logic;
SIGNAL dataout_xhdl1 : std_logic_vector(9 DOWNTO 0);
SIGNAL parafbkdataout_xhdl2 : std_logic_vector(9 DOWNTO 0);
BEGIN
dataout <= dataout_xhdl1;
parafbkdataout <= parafbkdataout_xhdl2;
tx_clk <= clk ;
soft_reset <= reset ;
temp_xhdl3 <= '1' WHEN (transmit_protocol /= "xaui") ELSE '0';
INDV <= temp_xhdl3 ;
temp_xhdl4 <= '1' WHEN (use_8b_10b_mode = "true") ELSE '0';
ENDEC <= temp_xhdl4 ;
temp_xhdl5 <= '1' WHEN (transmit_protocol = "gige") ELSE '0';
GE_XAUI_SEL <= temp_xhdl5 ;
temp_xhdl6 <= '1' WHEN (force_disparity_mode = "true") ELSE '0';
IB_FORCE_DISPARITY <= temp_xhdl6 ;
prbs_en <= '0' ;
tx_ctl_ts <= xgmctrl ;
tx_ctl_tc <= kin ;
tx_data_ts <= xgmdatain ;
tx_data_tc <= datain ;
tx_data_9_tc <= forcedisparity ;
tx_data_pg <= "0000000000" ;
dataout_xhdl1 <= PUDR ;
parafbkdataout_xhdl2 <= TXLP10B ;
m_enc_core : stratixgx_hssi_tx_enc_rtl
PORT MAP (
tx_clk => tx_clk,
soft_reset => soft_reset,
INDV => INDV,
ENDEC => ENDEC,
GE_XAUI_SEL => GE_XAUI_SEL,
IB_FORCE_DISPARITY => IB_FORCE_DISPARITY,
prbs_en => prbs_en,
tx_ctl_ts => tx_ctl_ts,
tx_ctl_tc => tx_ctl_tc,
tx_data_ts => tx_data_ts,
tx_data_tc => tx_data_tc,
tx_data_9_tc => tx_data_9_tc,
tx_data_pg => tx_data_pg,
PUDR => PUDR,
TXLP10B => TXLP10B);
END auto_translated;
--/////////////////////////////////////////////////////////////////////////////
--
-- DESKEW FIFO RAM MODULE
--
--/////////////////////////////////////////////////////////////////////////////
library IEEE, stratixgx_gxb, std;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY deskew_ram_block IS
PORT (
clk : IN std_logic;
reset : IN std_logic;
addrwr : IN std_logic_vector(15 DOWNTO 0);
addrrd1 : IN std_logic_vector(15 DOWNTO 0);
addrrd2 : IN std_logic_vector(15 DOWNTO 0);
datain : IN std_logic_vector(13 DOWNTO 0);
we : IN std_logic;
re : IN std_logic;
dataout1 : OUT std_logic_vector(13 DOWNTO 0);
dataout2 : OUT std_logic_vector(13 DOWNTO 0));
END deskew_ram_block;
ARCHITECTURE arch_deskew_ram_block OF deskew_ram_block IS
CONSTANT read_access_time : integer := 0;
CONSTANT write_access_time : integer := 0;
CONSTANT ram_width : integer := 14;
SIGNAL dataout1_i : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL dataout2_i : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_0 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_1 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_2 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_3 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_4 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_5 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_6 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_7 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_8 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_9 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_10 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_11 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_12 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_13 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_14 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_d_15 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_0 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_1 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_2 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_3 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_4 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_5 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_6 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_7 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_8 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_9 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_10 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_11 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_12 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_13 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_14 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL ram_array_q_15 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_0 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_1 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_2 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_3 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_4 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_5 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_6 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_7 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_8 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_9 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_10 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_11 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_12 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_13 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_14 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL data_reg_15 : std_logic_vector(ram_width - 1 DOWNTO 0);
SIGNAL dataout1_tmp1 : std_logic_vector(13 DOWNTO 0);
SIGNAL dataout2_tmp2 : std_logic_vector(13 DOWNTO 0);
BEGIN
dataout1 <= dataout1_tmp1;
dataout2 <= dataout2_tmp2;
data_reg_0 <= datain WHEN (addrwr(0) = '1') ELSE ram_array_q_0 ;
data_reg_1 <= datain WHEN (addrwr(1) = '1') ELSE ram_array_q_1 ;
data_reg_2 <= datain WHEN (addrwr(2) = '1') ELSE ram_array_q_2 ;
data_reg_3 <= datain WHEN (addrwr(3) = '1') ELSE ram_array_q_3 ;
data_reg_4 <= datain WHEN (addrwr(4) = '1') ELSE ram_array_q_4 ;
data_reg_5 <= datain WHEN (addrwr(5) = '1') ELSE ram_array_q_5 ;
data_reg_6 <= datain WHEN (addrwr(6) = '1') ELSE ram_array_q_6 ;
data_reg_7 <= datain WHEN (addrwr(7) = '1') ELSE ram_array_q_7 ;
data_reg_8 <= datain WHEN (addrwr(8) = '1') ELSE ram_array_q_8 ;
data_reg_9 <= datain WHEN (addrwr(9) = '1') ELSE ram_array_q_9 ;
data_reg_10 <= datain WHEN (addrwr(10) = '1') ELSE ram_array_q_10 ;
data_reg_11 <= datain WHEN (addrwr(11) = '1') ELSE ram_array_q_11 ;
data_reg_12 <= datain WHEN (addrwr(12) = '1') ELSE ram_array_q_12 ;
data_reg_13 <= datain WHEN (addrwr(13) = '1') ELSE ram_array_q_13 ;
data_reg_14 <= datain WHEN (addrwr(14) = '1') ELSE ram_array_q_14 ;
data_reg_15 <= datain WHEN (addrwr(15) = '1') ELSE ram_array_q_15 ;
dataout1_tmp1 <= "00000000000000" WHEN re = '1' ELSE dataout1_i after 0 ns;
dataout2_tmp2 <= "00000000000000" WHEN re = '1' ELSE dataout2_i after 0 ns;
PROCESS (ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15, addrrd1, addrrd2)
VARIABLE dataout1_i_tmp3 : std_logic_vector(ram_width - 1 DOWNTO 0);
VARIABLE dataout2_i_tmp4 : std_logic_vector(ram_width - 1 DOWNTO 0);
BEGIN
CASE addrrd1 IS
WHEN "0000000000000001" =>
dataout1_i_tmp3 := ram_array_q_0;
WHEN "0000000000000010" =>
dataout1_i_tmp3 := ram_array_q_1;
WHEN "0000000000000100" =>
dataout1_i_tmp3 := ram_array_q_2;
WHEN "0000000000001000" =>
dataout1_i_tmp3 := ram_array_q_3;
WHEN "0000000000010000" =>
dataout1_i_tmp3 := ram_array_q_4;
WHEN "0000000000100000" =>
dataout1_i_tmp3 := ram_array_q_5;
WHEN "0000000001000000" =>
dataout1_i_tmp3 := ram_array_q_6;
WHEN "0000000010000000" =>
dataout1_i_tmp3 := ram_array_q_7;
WHEN "0000000100000000" =>
dataout1_i_tmp3 := ram_array_q_8;
WHEN "0000001000000000" =>
dataout1_i_tmp3 := ram_array_q_9;
WHEN "0000010000000000" =>
dataout1_i_tmp3 := ram_array_q_10;
WHEN "0000100000000000" =>
dataout1_i_tmp3 := ram_array_q_11;
WHEN "0001000000000000" =>
dataout1_i_tmp3 := ram_array_q_12;
WHEN "0010000000000000" =>
dataout1_i_tmp3 := ram_array_q_13;
WHEN "0100000000000000" =>
dataout1_i_tmp3 := ram_array_q_14;
WHEN "1000000000000000" =>
dataout1_i_tmp3 := ram_array_q_15;
WHEN OTHERS =>
NULL;
END CASE;
CASE addrrd2 IS
WHEN "0000000000000001" =>
dataout2_i_tmp4 := ram_array_q_0;
WHEN "0000000000000010" =>
dataout2_i_tmp4 := ram_array_q_1;
WHEN "0000000000000100" =>
dataout2_i_tmp4 := ram_array_q_2;
WHEN "0000000000001000" =>
dataout2_i_tmp4 := ram_array_q_3;
WHEN "0000000000010000" =>
dataout2_i_tmp4 := ram_array_q_4;
WHEN "0000000000100000" =>
dataout2_i_tmp4 := ram_array_q_5;
WHEN "0000000001000000" =>
dataout2_i_tmp4 := ram_array_q_6;
WHEN "0000000010000000" =>
dataout2_i_tmp4 := ram_array_q_7;
WHEN "0000000100000000" =>
dataout2_i_tmp4 := ram_array_q_8;
WHEN "0000001000000000" =>
dataout2_i_tmp4 := ram_array_q_9;
WHEN "0000010000000000" =>
dataout2_i_tmp4 := ram_array_q_10;
WHEN "0000100000000000" =>
dataout2_i_tmp4 := ram_array_q_11;
WHEN "0001000000000000" =>
dataout2_i_tmp4 := ram_array_q_12;
WHEN "0010000000000000" =>
dataout2_i_tmp4 := ram_array_q_13;
WHEN "0100000000000000" =>
dataout2_i_tmp4 := ram_array_q_14;
WHEN "1000000000000000" =>
dataout2_i_tmp4 := ram_array_q_15;
WHEN OTHERS =>
NULL;
END CASE;
dataout1_i <= dataout1_i_tmp3;
dataout2_i <= dataout2_i_tmp4;
END PROCESS;
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN
ram_array_q_0 <= "00000000000000" AFTER 0 ns;
ram_array_q_1 <= "00000000000000" AFTER 0 ns;
ram_array_q_2 <= "00000000000000" AFTER 0 ns;
ram_array_q_3 <= "00000000000000" AFTER 0 ns;
ram_array_q_4 <= "00000000000000" AFTER 0 ns;
ram_array_q_5 <= "00000000000000" AFTER 0 ns;
ram_array_q_6 <= "00000000000000" AFTER 0 ns;
ram_array_q_7 <= "00000000000000" AFTER 0 ns;
ram_array_q_8 <= "00000000000000" AFTER 0 ns;
ram_array_q_9 <= "00000000000000" AFTER 0 ns;
ram_array_q_10 <= "00000000000000" AFTER 0 ns;
ram_array_q_11 <= "00000000000000" AFTER 0 ns;
ram_array_q_12 <= "00000000000000" AFTER 0 ns;
ram_array_q_13 <= "00000000000000" AFTER 0 ns;
ram_array_q_14 <= "00000000000000" AFTER 0 ns;
ram_array_q_15 <= "00000000000000" AFTER 0 ns;
ELSIF (clk'EVENT AND clk = '1') THEN
ram_array_q_0 <= ram_array_d_0 AFTER 0 ns;
ram_array_q_1 <= ram_array_d_1 AFTER 0 ns;
ram_array_q_2 <= ram_array_d_2 AFTER 0 ns;
ram_array_q_3 <= ram_array_d_3 AFTER 0 ns;
ram_array_q_4 <= ram_array_d_4 AFTER 0 ns;
ram_array_q_5 <= ram_array_d_5 AFTER 0 ns;
ram_array_q_6 <= ram_array_d_6 AFTER 0 ns;
ram_array_q_7 <= ram_array_d_7 AFTER 0 ns;
ram_array_q_8 <= ram_array_d_8 AFTER 0 ns;
ram_array_q_9 <= ram_array_d_9 AFTER 0 ns;
ram_array_q_10 <= ram_array_d_10 AFTER 0 ns;
ram_array_q_11 <= ram_array_d_11 AFTER 0 ns;
ram_array_q_12 <= ram_array_d_12 AFTER 0 ns;
ram_array_q_13 <= ram_array_d_13 AFTER 0 ns;
ram_array_q_14 <= ram_array_d_14 AFTER 0 ns;
ram_array_q_15 <= ram_array_d_15 AFTER 0 ns;
END IF;
END PROCESS;
PROCESS (we, data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, data_reg_8, data_reg_9, data_reg_10, data_reg_11, data_reg_12, data_reg_13, data_reg_14, data_reg_15, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15)
BEGIN
IF (we = '1') THEN
ram_array_d_0 <= data_reg_0 AFTER 0 ns;
ram_array_d_1 <= data_reg_1 AFTER 0 ns;
ram_array_d_2 <= data_reg_2 AFTER 0 ns;
ram_array_d_3 <= data_reg_3 AFTER 0 ns;
ram_array_d_4 <= data_reg_4 AFTER 0 ns;
ram_array_d_5 <= data_reg_5 AFTER 0 ns;
ram_array_d_6 <= data_reg_6 AFTER 0 ns;
ram_array_d_7 <= data_reg_7 AFTER 0 ns;
ram_array_d_8 <= data_reg_8 AFTER 0 ns;
ram_array_d_9 <= data_reg_9 AFTER 0 ns;
ram_array_d_10 <= data_reg_10 AFTER 0 ns;
ram_array_d_11 <= data_reg_11 AFTER 0 ns;
ram_array_d_12 <= data_reg_12 AFTER 0 ns;
ram_array_d_13 <= data_reg_13 AFTER 0 ns;
ram_array_d_14 <= data_reg_14 AFTER 0 ns;
ram_array_d_15 <= data_reg_15 AFTER 0 ns;
ELSE
ram_array_d_0 <= ram_array_q_0 AFTER 0 ns;
ram_array_d_1 <= ram_array_q_1 AFTER 0 ns;
ram_array_d_2 <= ram_array_q_2 AFTER 0 ns;
ram_array_d_3 <= ram_array_q_3 AFTER 0 ns;
ram_array_d_4 <= ram_array_q_4 AFTER 0 ns;
ram_array_d_5 <= ram_array_q_5 AFTER 0 ns;
ram_array_d_6 <= ram_array_q_6 AFTER 0 ns;
ram_array_d_7 <= ram_array_q_7 AFTER 0 ns;
ram_array_d_8 <= ram_array_q_8 AFTER 0 ns;
ram_array_d_9 <= ram_array_q_9 AFTER 0 ns;
ram_array_d_10 <= ram_array_q_10 AFTER 0 ns;
ram_array_d_11 <= ram_array_q_11 AFTER 0 ns;
ram_array_d_12 <= ram_array_q_12 AFTER 0 ns;
ram_array_d_13 <= ram_array_q_13 AFTER 0 ns;
ram_array_d_14 <= ram_array_q_14 AFTER 0 ns;
ram_array_d_15 <= ram_array_q_15 AFTER 0 ns;
END IF;
END PROCESS;
END arch_deskew_ram_block;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_DESKEW_FIFO
--
--/////////////////////////////////////////////////////////////////////////////
library IEEE, stratixgx_gxb, std;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY stratixgx_deskew_fifo IS
PORT (
datain : IN std_logic_vector(9 DOWNTO 0);
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
writeclock : IN std_logic;
readclock : IN std_logic;
adetectdeskew : OUT std_logic;
fiforesetrd : IN std_logic;
enabledeskew : IN std_logic;
reset : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
dataoutpre : OUT std_logic_vector(9 DOWNTO 0);
errdetect : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
errdetectpre : OUT std_logic;
syncstatuspre : OUT std_logic;
disperrpre : OUT std_logic;
patterndetectpre : OUT std_logic;
rdalign : OUT std_logic);
END stratixgx_deskew_fifo;
ARCHITECTURE arch_stratixgx_deskew_fifo OF stratixgx_deskew_fifo IS
COMPONENT deskew_ram_block
PORT (
clk : IN std_logic;
reset : IN std_logic;
addrwr : IN std_logic_vector(15 DOWNTO 0);
addrrd1 : IN std_logic_vector(15 DOWNTO 0);
addrrd2 : IN std_logic_vector(15 DOWNTO 0);
datain : IN std_logic_vector(13 DOWNTO 0);
we : IN std_logic;
re : IN std_logic;
dataout1 : OUT std_logic_vector(13 DOWNTO 0);
dataout2 : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
CONSTANT a : std_logic_vector(9 DOWNTO 0) := "0011000011";
CONSTANT FIFO_DEPTH : integer := 16;
SIGNAL fifo : std_logic_vector(16 * 15 - 1 DOWNTO 0);
SIGNAL dataout_tmp : std_logic_vector(9 DOWNTO 0);
SIGNAL dataout_tmp_pre : std_logic_vector(9 DOWNTO 0);
SIGNAL dataout_fifo : std_logic_vector(13 DOWNTO 0);
SIGNAL adetectdeskew_tmp : std_logic;
SIGNAL errdetect_tmp : std_logic;
SIGNAL syncstatus_tmp : std_logic;
SIGNAL disperr_tmp : std_logic;
SIGNAL errdetect_tmp_pre : std_logic;
SIGNAL syncstatus_tmp_pre : std_logic;
SIGNAL disperr_tmp_pre : std_logic;
SIGNAL patterndetect_tmp : std_logic;
SIGNAL patterndetect_tmp_pre : std_logic;
SIGNAL align_count : std_logic_vector(3 DOWNTO 0);
SIGNAL adetect_deskew : std_logic;
SIGNAL adetect_deskew_dly : std_logic;
SIGNAL enabledeskew_dly0 : std_logic;
SIGNAL enabledeskew_dly1 : std_logic;
SIGNAL enabledeskew_dly2 : std_logic;
SIGNAL adetectdeskew_dly : std_logic;
SIGNAL write_enable : std_logic;
SIGNAL wr_enable : std_logic;
SIGNAL reset_fifo : std_logic;
SIGNAL reset_write : std_logic;
SIGNAL wr_align : std_logic;
SIGNAL AUDI_d : std_logic_vector(13 DOWNTO 0);
SIGNAL AUDI_pre_d : std_logic_vector(13 DOWNTO 0);
SIGNAL write_ptr : std_logic_vector(FIFO_DEPTH - 1 DOWNTO 0);
SIGNAL read_ptr1 : std_logic_vector(FIFO_DEPTH - 1 DOWNTO 0);
SIGNAL read_ptr2 : std_logic_vector(FIFO_DEPTH - 1 DOWNTO 0);
-- WRITE ENABLE LOGIC
SIGNAL tmp_23 : std_logic_vector(13 DOWNTO 0);
-- active low
-- active high
SIGNAL port_tmp24 : std_logic;
SIGNAL port_tmp25 : std_logic;
SIGNAL adetect_out : std_logic;
SIGNAL adetect_in : std_logic;
BEGIN
PROCESS (reset, writeclock)
BEGIN
IF (reset = '1') THEN
write_ptr <= "0000000000000001";
ELSIF (writeclock'EVENT AND writeclock = '1') THEN
IF ((reset_fifo OR reset_write) = '1') THEN
write_ptr <= "0000000000000001";
ELSE
IF ((wr_enable OR wr_align) = '1') THEN
write_ptr <= write_ptr(FIFO_DEPTH - 2 DOWNTO 0) & write_ptr(FIFO_DEPTH - 1);
ELSE
write_ptr <= write_ptr;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (reset, readclock)
BEGIN
IF (reset = '1') THEN
read_ptr1 <= "0000000000000001";
read_ptr2 <= "0000000000000010";
ELSIF (readclock'EVENT AND readclock = '1') THEN
IF (fiforesetrd = '1') THEN
read_ptr1 <= "0000000000000001";
read_ptr2 <= "0000000000000010";
ELSE
IF (NOT enabledeskew = '1') THEN
read_ptr1 <= read_ptr1(FIFO_DEPTH - 2 DOWNTO 0) & read_ptr1(FIFO_DEPTH - 1);
read_ptr2 <= read_ptr2(FIFO_DEPTH - 2 DOWNTO 0) & read_ptr2(FIFO_DEPTH - 1);
ELSE
read_ptr1 <= "0000000000000001";
read_ptr2 <= "0000000000000010";
END IF;
END IF;
END IF;
END PROCESS;
tmp_23 <= patterndetectin & disperrin & syncstatusin & errdetectin & datain(9 DOWNTO 0);
port_tmp24 <= '1';
port_tmp25 <= '0';
deskew_ram : deskew_ram_block
PORT MAP (
clk => writeclock,
reset => reset,
addrwr => write_ptr,
addrrd1 => read_ptr1,
addrrd2 => read_ptr2,
datain => tmp_23,
we => port_tmp24,
re => port_tmp25,
dataout1 => AUDI_d,
dataout2 => AUDI_pre_d);
PROCESS (reset, readclock)
VARIABLE dataout_tmp_tmp26 : std_logic_vector(9 DOWNTO 0);
VARIABLE errdetect_tmp_tmp27 : std_logic;
VARIABLE syncstatus_tmp_tmp28 : std_logic;
VARIABLE disperr_tmp_tmp29 : std_logic;
VARIABLE dataout_tmp_pre_tmp30 : std_logic_vector(9 DOWNTO 0);
VARIABLE errdetect_tmp_pre_tmp31 : std_logic;
VARIABLE syncstatus_tmp_pre_tmp32 : std_logic;
VARIABLE disperr_tmp_pre_tmp33 : std_logic;
VARIABLE patterndetect_tmp_tmp34 : std_logic;
VARIABLE patterndetect_tmp_pre_tmp35 : std_logic;
BEGIN
IF (reset = '1') THEN
dataout_tmp_tmp26 := "0000000000";
errdetect_tmp_tmp27 := '0';
syncstatus_tmp_tmp28 := '0';
disperr_tmp_tmp29 := '0';
dataout_tmp_pre_tmp30 := "0000000000";
errdetect_tmp_pre_tmp31 := '0';
syncstatus_tmp_pre_tmp32 := '0';
disperr_tmp_pre_tmp33 := '0';
patterndetect_tmp_tmp34 := '0';
patterndetect_tmp_pre_tmp35 := '0';
ELSIF (readclock'EVENT AND readclock = '1') THEN
dataout_tmp_tmp26 := AUDI_d(9 DOWNTO 0);
errdetect_tmp_tmp27 := AUDI_d(10);
syncstatus_tmp_tmp28 := AUDI_d(11);
disperr_tmp_tmp29 := AUDI_d(12);
patterndetect_tmp_tmp34 := AUDI_d(13);
dataout_tmp_pre_tmp30 := AUDI_pre_d(9 DOWNTO 0);
errdetect_tmp_pre_tmp31 := AUDI_pre_d(10);
syncstatus_tmp_pre_tmp32 := AUDI_pre_d(11);
disperr_tmp_pre_tmp33 := AUDI_pre_d(12);
patterndetect_tmp_pre_tmp35 := AUDI_pre_d(13);
END IF;
dataout_tmp <= dataout_tmp_tmp26;
errdetect_tmp <= errdetect_tmp_tmp27;
syncstatus_tmp <= syncstatus_tmp_tmp28;
disperr_tmp <= disperr_tmp_tmp29;
dataout_tmp_pre <= dataout_tmp_pre_tmp30;
errdetect_tmp_pre <= errdetect_tmp_pre_tmp31;
syncstatus_tmp_pre <= syncstatus_tmp_pre_tmp32;
disperr_tmp_pre <= disperr_tmp_pre_tmp33;
patterndetect_tmp <= patterndetect_tmp_tmp34;
patterndetect_tmp_pre <= patterndetect_tmp_pre_tmp35;
END PROCESS;
PROCESS (reset, writeclock)
BEGIN
IF (reset = '1') THEN
wr_enable <= '0';
ELSIF (writeclock'EVENT AND writeclock = '1') THEN
IF ((reset_fifo OR reset_write) = '1') THEN
wr_enable <= '0';
ELSE
IF (wr_align = '1') THEN
wr_enable <= '1';
ELSE
wr_enable <= wr_enable;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (writeclock, reset)
BEGIN
IF (reset = '1') THEN
adetect_deskew <= '0';
ELSIF (writeclock'EVENT AND writeclock = '1') THEN
IF (wr_align = '1') THEN
adetect_deskew <= '1';
ELSE
IF (align_count = 0) THEN
adetect_deskew <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclock)
BEGIN
IF (reset = '1') THEN
align_count <= "0000";
ELSIF (writeclock'EVENT AND writeclock = '1') THEN
IF (NOT enabledeskew_dly1 = '1') THEN
align_count <= "0000";
ELSE
IF (wr_align = '1') THEN
align_count <= "1001";
ELSE
IF (align_count /= 0) THEN
align_count <= align_count - "0001";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (writeclock, reset)
BEGIN
IF (reset = '1') THEN
enabledeskew_dly0 <= '1';
enabledeskew_dly1 <= '1';
enabledeskew_dly2 <= '1';
ELSIF (writeclock'EVENT AND writeclock = '1') THEN
enabledeskew_dly0 <= enabledeskew;
enabledeskew_dly1 <= enabledeskew_dly0;
enabledeskew_dly2 <= enabledeskew_dly1;
END IF;
END PROCESS;
adetect_deskew_dly <= adetect_deskew after 1 ps;
PROCESS (reset, readclock)
BEGIN
IF (reset = '1') THEN
adetectdeskew_dly <= '0';
adetectdeskew_tmp <= '0';
ELSIF (readclock'EVENT AND readclock = '1') THEN
adetectdeskew_dly <= adetect_deskew_dly;
adetectdeskew_tmp <= adetectdeskew_dly;
END IF;
END PROCESS;
adetect_out <= '1' when ((unsigned(dataout_tmp(9 DOWNTO 0)) = unsigned(a)) OR
(unsigned(dataout_tmp(9 DOWNTO 0)) = unsigned(NOT a))) else '0';
adetect_in <= '1' when ((unsigned(datain(9 DOWNTO 0)) = unsigned(a)) OR
(unsigned(datain(9 DOWNTO 0)) = unsigned(NOT a))) else '0';
rdalign <= '1' when ( (adetect_out = '1') AND (disperr_tmp = '0') AND (errdetect_tmp = '0') ) else '0' ;
wr_align <= '1' when ((adetect_in = '1') AND (enabledeskew_dly1 = '1') AND (disperrin = '0') AND (errdetectin = '0')) else '0';
reset_fifo <= (wr_enable AND write_ptr(FIFO_DEPTH - 1)) AND enabledeskew_dly1 ;
reset_write <= enabledeskew_dly1 AND NOT enabledeskew_dly2 ;
adetectdeskew <= adetectdeskew_tmp ;
dataout <= dataout_tmp ;
errdetect <= errdetect_tmp ;
syncstatus <= syncstatus_tmp ;
disperr <= disperr_tmp ;
dataoutpre <= dataout_tmp_pre ;
errdetectpre <= errdetect_tmp_pre ;
syncstatuspre <= syncstatus_tmp_pre ;
disperrpre <= disperr_tmp_pre ;
patterndetect <= patterndetect_tmp ;
patterndetectpre <= patterndetect_tmp_pre ;
END arch_stratixgx_deskew_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_RX_CORE
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY ieee, stratixgx_gxb;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_rx_core IS
GENERIC (
channel_width : integer := 10;
use_double_data_mode : string := "false";
use_channel_align : string := "false";
use_8b_10b_mode : string := "true";
align_pattern : string := "0000000000000000";
synchronization_mode : string := "none");
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
errdetectin : IN std_logic;
patterndetectin : IN std_logic;
decdatavalid : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
post8b10b : IN std_logic_vector(9 DOWNTO 0);
datain : IN std_logic_vector(9 DOWNTO 0);
xgmctrlin : IN std_logic;
ctrldetectin : IN std_logic;
syncstatusin : IN std_logic;
disparityerrin : IN std_logic;
syncstatus : OUT std_logic_vector(1 DOWNTO 0);
errdetect : OUT std_logic_vector(1 DOWNTO 0);
ctrldetect : OUT std_logic_vector(1 DOWNTO 0);
disparityerr : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(19 DOWNTO 0);
a1a2sizeout : OUT std_logic_vector(1 DOWNTO 0);
clkout : OUT std_logic);
END stratixgx_rx_core;
ARCHITECTURE arch_stratixgx_rx_core OF stratixgx_rx_core IS
SIGNAL detect : std_logic;
SIGNAL xgmxor : std_logic_vector(7 DOWNTO 0);
SIGNAL resync_d : std_logic;
SIGNAL disperr_d : std_logic;
SIGNAL patterndetect_d : std_logic;
SIGNAL syncstatusin_1 : std_logic;
SIGNAL syncstatusin_2 : std_logic;
SIGNAL disparityerrin_1 : std_logic;
SIGNAL disparityerrin_2 : std_logic;
SIGNAL patterndetectin_1 : std_logic;
SIGNAL patterndetectin_2 : std_logic;
SIGNAL writeclk_by2 : std_logic := '0';
SIGNAL data_low_sync : std_logic_vector(12 DOWNTO 0);
SIGNAL data_low : std_logic_vector(12 DOWNTO 0);
SIGNAL data_high : std_logic_vector(12 DOWNTO 0);
SIGNAL data_int : std_logic_vector(9 DOWNTO 0);
SIGNAL dataout_tmp : std_logic_vector(19 DOWNTO 0);
SIGNAL patterndetect_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL disparityerr_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL syncstatus_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL errdetect_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL ctrldetect_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL a1a2sizeout_tmp : std_logic_vector(1 DOWNTO 0);
SIGNAL dataout_sync1 : std_logic_vector(19 DOWNTO 0);
SIGNAL patterndetect_sync1 : std_logic_vector(1 DOWNTO 0);
SIGNAL disparityerr_sync1 : std_logic_vector(1 DOWNTO 0);
SIGNAL syncstatus_sync1 : std_logic_vector(1 DOWNTO 0);
SIGNAL errdetect_sync1 : std_logic_vector(1 DOWNTO 0);
SIGNAL ctrldetect_sync1 : std_logic_vector(1 DOWNTO 0);
SIGNAL a1a2sizeout_sync1 : std_logic_vector(1 DOWNTO 0) := "00";
SIGNAL dataout_sync2 : std_logic_vector(19 DOWNTO 0);
SIGNAL patterndetect_sync2 : std_logic_vector(1 DOWNTO 0);
SIGNAL disparityerr_sync2 : std_logic_vector(1 DOWNTO 0);
SIGNAL syncstatus_sync2 : std_logic_vector(1 DOWNTO 0);
SIGNAL errdetect_sync2 : std_logic_vector(1 DOWNTO 0);
SIGNAL ctrldetect_sync2 : std_logic_vector(1 DOWNTO 0);
SIGNAL a1a2sizeout_sync2 : std_logic_vector(1 DOWNTO 0) := "00";
SIGNAL doublewidth : std_logic;
SIGNAL individual : std_logic;
SIGNAL ena8b10b : std_logic;
SIGNAL smdisable : std_logic;
SIGNAL syncstatus_tmp1 : std_logic_vector(1 DOWNTO 0);
SIGNAL errdetect_tmp2 : std_logic_vector(1 DOWNTO 0);
SIGNAL ctrldetect_tmp3 : std_logic_vector(1 DOWNTO 0);
SIGNAL disparityerr_tmp4 : std_logic_vector(1 DOWNTO 0);
SIGNAL patterndetect_tmp5 : std_logic_vector(1 DOWNTO 0);
SIGNAL dataout_tmp6 : std_logic_vector(19 DOWNTO 0);
SIGNAL a1a2sizeout_tmp7 : std_logic_vector(1 downto 0);
SIGNAL clkout_tmp8 : std_logic;
SIGNAL running_disp : std_logic;
-- A1A2 patterndetect related signals
signal align_pattern_int : std_logic_vector(15 downto 0);
signal patterndetect_8b : std_logic;
signal patterndetect_1_latch : std_logic;
signal patterndetect_2_latch : std_logic;
signal patterndetect_3_latch : std_logic;
BEGIN
syncstatus <= syncstatus_tmp1;
errdetect <= errdetect_tmp2;
ctrldetect <= ctrldetect_tmp3;
disparityerr <= disparityerr_tmp4;
patterndetect <= patterndetect_tmp5;
dataout <= dataout_tmp6;
a1a2sizeout <= a1a2sizeout_tmp7;
clkout <= clkout_tmp8;
doublewidth <= '1' WHEN (use_double_data_mode = "true") ELSE '0' ;
individual <= '1' WHEN (use_channel_align /= "true") ELSE '0' ;
ena8b10b <= '1' WHEN (use_8b_10b_mode = "true") ELSE '0' ;
smdisable <= '1' WHEN (synchronization_mode = "none") ELSE '0' ;
running_disp <= disparityerrin OR errdetectin;
-- A1A2 pattern detection
align_pattern_int <= pattern_conversion(align_pattern);
-- A1A2 patterndetect block
PROCESS (datain, align_pattern_int, patterndetect_1_latch, patterndetect_3_latch)
VARIABLE patterndetect_8b_tmp10 : std_logic;
VARIABLE match_tmp : std_logic := '0';
BEGIN
IF (datain(8) = '1') THEN
if (UNSIGNED(datain(7 DOWNTO 0)) = UNSIGNED(align_pattern_int(15 DOWNTO 8))) then
match_tmp := '1';
else
match_tmp := '0';
end if;
patterndetect_8b_tmp10 := match_tmp AND patterndetect_3_latch;
ELSE
if (UNSIGNED(datain(7 DOWNTO 0)) = UNSIGNED(align_pattern_int(15 DOWNTO 8))) then
match_tmp := '1';
else
match_tmp := '0';
end if;
patterndetect_8b_tmp10 := match_tmp AND patterndetect_1_latch;
END IF;
patterndetect_8b <= patterndetect_8b_tmp10;
END PROCESS;
-- A1A2 patterndetect latch
PROCESS (reset, writeclk)
VARIABLE match_low : std_logic := '0';
VARIABLE match_high : std_logic := '0';
BEGIN
IF (reset = '1') THEN
patterndetect_1_latch <= '0';
patterndetect_2_latch <= '0';
patterndetect_3_latch <= '0';
ELSIF (writeclk'EVENT AND writeclk = '1') THEN
if (UNSIGNED(datain(7 DOWNTO 0)) = UNSIGNED(align_pattern_int(7 DOWNTO 0))) then
match_low := '1';
else
match_low := '0';
end if;
if (UNSIGNED(datain(7 DOWNTO 0)) = UNSIGNED(align_pattern_int(15 DOWNTO 8))) then
match_high := '1';
else
match_high := '0';
end if;
patterndetect_1_latch <= match_low;
patterndetect_2_latch <= (patterndetect_1_latch) AND match_low;
patterndetect_3_latch <= (patterndetect_2_latch) AND match_high;
END IF;
END PROCESS;
PROCESS (xgmdatain, datain, xgmctrlin, ctrldetectin, decdatavalid, data_int, syncstatusin, disparityerrin, patterndetectin, patterndetect_8b, syncstatusin_2, disparityerrin_2, patterndetectin_2, running_disp)
variable i_detect : std_logic;
BEGIN
IF (ena8b10b = '1') THEN
IF (individual = '1') THEN
resync_d <= syncstatusin;
disperr_d <= disparityerrin;
IF ((NOT decdatavalid AND NOT smdisable) = '1') THEN
data_int(8 DOWNTO 0) <= "110011100";
data_int(9) <= '0';
patterndetect_d <= '0';
ELSE
IF (channel_width = 10) THEN
patterndetect_d <= patterndetectin;
ELSE
patterndetect_d <= patterndetect_8b;
END IF;
IF (((decdatavalid AND NOT smdisable) AND running_disp) = '1') THEN
data_int(8 DOWNTO 0) <= "111111110";
data_int(9) <= running_disp;
ELSE
data_int(8 DOWNTO 0) <= ctrldetectin & datain(7 DOWNTO 0);
data_int(9) <= running_disp;
END IF;
END IF;
ELSE
resync_d <= syncstatusin_2;
disperr_d <= disparityerrin_2;
patterndetect_d <= patterndetectin_2;
data_int(8 DOWNTO 0) <= xgmctrlin & xgmdatain(7 DOWNTO 0);
i_detect := '0';
if (xgmxor /= 0) then
i_detect := '1';
end if;
data_int(9) <= xgmctrlin AND NOT i_detect;
END IF;
ELSE
resync_d <= syncstatusin;
disperr_d <= disparityerrin;
data_int <= datain;
IF ((NOT decdatavalid AND NOT smdisable) = '1') THEN
patterndetect_d <= '0';
ELSE
IF (channel_width = 10) THEN
patterndetect_d <= patterndetectin;
ELSE
patterndetect_d <= patterndetect_8b;
END IF;
END IF;
END IF;
END PROCESS;
xgmxor <= xgmdatain(7 DOWNTO 0) XOR "11111110" ;
PROCESS (reset, writeclk)
BEGIN
IF (reset = '1') THEN
writeclk_by2 <= '0';
data_high <= "0000000000000";
data_low <= "0000000000000";
data_low_sync <= "0000000000000";
syncstatusin_1 <= '0';
syncstatusin_2 <= '0';
disparityerrin_1 <= '0';
disparityerrin_2 <= '0';
patterndetectin_1 <= '0';
patterndetectin_2 <= '0';
ELSIF (writeclk'EVENT AND writeclk = '1') THEN
writeclk_by2 <= NOT ((writeclk_by2 AND individual) OR (writeclk_by2 AND NOT individual));
syncstatusin_1 <= syncstatusin;
syncstatusin_2 <= syncstatusin_1;
disparityerrin_1 <= disparityerrin;
disparityerrin_2 <= disparityerrin_1;
patterndetectin_1 <= patterndetectin;
patterndetectin_2 <= patterndetectin_1;
IF ((doublewidth AND NOT writeclk_by2) = '1') THEN
data_high(9 DOWNTO 0) <= data_int;
data_high(10) <= resync_d;
data_high(11) <= disperr_d;
data_high(12) <= patterndetect_d;
END IF;
IF ((doublewidth AND writeclk_by2) = '1') THEN
data_low(9 DOWNTO 0) <= data_int;
data_low(10) <= resync_d;
data_low(11) <= disperr_d;
data_low(12) <= patterndetect_d;
END IF;
IF (NOT doublewidth = '1') THEN
data_low_sync(9 DOWNTO 0) <= data_int;
data_low_sync(10) <= resync_d;
data_low_sync(11) <= disperr_d;
data_low_sync(12) <= patterndetect_d;
ELSE
data_low_sync <= data_low;
END IF;
END IF;
END PROCESS;
PROCESS (writeclk_by2, writeclk)
BEGIN
IF (doublewidth = '1') THEN
clkout_tmp8 <= NOT writeclk_by2;
ELSE
clkout_tmp8 <= NOT writeclk;
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
dataout_tmp <= "00000000000000000000";
patterndetect_tmp <= "00";
disparityerr_tmp <= "00";
syncstatus_tmp <= "00";
errdetect_tmp <= "00";
ctrldetect_tmp <= "00";
a1a2sizeout_tmp <= "00";
dataout_sync1 <= "00000000000000000000";
patterndetect_sync1 <= "00";
disparityerr_sync1 <= "00";
syncstatus_sync1 <= "00";
errdetect_sync1 <= "00";
ctrldetect_sync1 <= "00";
a1a2sizeout_sync1 <= "00";
dataout_sync2 <= "00000000000000000000";
patterndetect_sync2 <= "00";
disparityerr_sync2 <= "00";
syncstatus_sync2 <= "00";
errdetect_sync2 <= "00";
ctrldetect_sync2 <= "00";
a1a2sizeout_sync2 <= "00";
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF (ena8b10b = '1' OR channel_width = 8 OR channel_width = 16) THEN
dataout_sync1 <= "0000" & data_high(7 DOWNTO 0) & data_low_sync(7 DOWNTO 0);
ELSE
dataout_sync1 <= data_high(9 DOWNTO 0) & data_low_sync(9 DOWNTO 0);
END IF;
patterndetect_sync1 <= data_high(12) & data_low_sync(12);
disparityerr_sync1 <= data_high(11) & data_low_sync(11);
syncstatus_sync1 <= data_high(10) & data_low_sync(10);
errdetect_sync1 <= data_high(9) & data_low_sync(9);
ctrldetect_sync1 <= data_high(8) & data_low_sync(8);
IF (channel_width = 8) THEN
a1a2sizeout_sync1 <= data_high(8) & data_low_sync(8);
ELSE
a1a2sizeout_sync1 <= "00";
END IF;
dataout_sync2 <= dataout_sync1;
patterndetect_sync2 <= patterndetect_sync1;
disparityerr_sync2 <= disparityerr_sync1;
syncstatus_sync2 <= syncstatus_sync1;
errdetect_sync2 <= errdetect_sync1;
ctrldetect_sync2 <= ctrldetect_sync1;
a1a2sizeout_sync2 <= a1a2sizeout_sync1;
dataout_tmp <= dataout_sync2;
patterndetect_tmp <= patterndetect_sync2;
disparityerr_tmp <= disparityerr_sync2;
syncstatus_tmp <= syncstatus_sync2;
errdetect_tmp <= errdetect_sync2;
ctrldetect_tmp <= ctrldetect_sync2;
a1a2sizeout_tmp <= a1a2sizeout_sync2;
END IF;
END PROCESS;
dataout_tmp6 <= dataout_tmp ;
a1a2sizeout_tmp7 <= a1a2sizeout_tmp;
patterndetect_tmp5 <= patterndetect_tmp ;
disparityerr_tmp4 <= disparityerr_tmp ;
syncstatus_tmp1 <= syncstatus_tmp ;
errdetect_tmp2 <= errdetect_tmp ;
ctrldetect_tmp3 <= ctrldetect_tmp ;
END arch_stratixgx_rx_core;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXGX_TX_CORE
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixgx_tx_core IS
GENERIC (
use_double_data_mode : string := "false";
use_fifo_mode : string := "true";
transmit_protocol : string := "none";
channel_width : integer := 10;
KCHAR : std_logic := '0';
ECHAR : std_logic := '0');
PORT (
reset : IN std_logic;
datain : IN std_logic_vector(19 DOWNTO 0);
writeclk : IN std_logic;
readclk : IN std_logic;
ctrlena : IN std_logic_vector(1 DOWNTO 0);
forcedisp : IN std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(9 DOWNTO 0);
forcedispout : OUT std_logic;
ctrlenaout : OUT std_logic;
rdenasync : OUT std_logic;
xgmctrlena : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
pre8b10bdataout : OUT std_logic_vector(9 DOWNTO 0));
END stratixgx_tx_core;
ARCHITECTURE arch_stratixgx_tx_core OF stratixgx_tx_core IS
SIGNAL kchar_sync_1 : std_logic;
SIGNAL kchar_sync : std_logic;
SIGNAL echar_sync_1 : std_logic;
SIGNAL echar_sync : std_logic;
SIGNAL datain_high : std_logic_vector(11 DOWNTO 0);
SIGNAL datain_low : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_high_tmp : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_high_dly1 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_high_dly2 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_high_dly3 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_low_tmp : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_low_dly1 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_low_dly2 : std_logic_vector(11 DOWNTO 0);
SIGNAL fifo_low_dly3 : std_logic_vector(11 DOWNTO 0);
SIGNAL dataout_read : std_logic_vector(11 DOWNTO 0);
SIGNAL wr_enable : std_logic;
SIGNAL rd_enable_sync_1 : std_logic;
SIGNAL rd_enable_sync_2 : std_logic;
SIGNAL rd_enable_sync_out : std_logic;
SIGNAL fifo_select_out : std_logic;
SIGNAL rdenasync_tmp : std_logic;
SIGNAL out_ena1 : std_logic;
SIGNAL out_ena2 : std_logic;
SIGNAL out_ena3 : std_logic;
SIGNAL out_ena4 : std_logic;
SIGNAL out_ena5 : std_logic;
SIGNAL doublewidth : std_logic;
SIGNAL disablefifo : std_logic;
SIGNAL individual : std_logic;
SIGNAL writeclk_dly : std_logic;
BEGIN
doublewidth <= '1' WHEN (use_double_data_mode = "true") ELSE '0' ;
disablefifo <= '1' WHEN (use_fifo_mode = "false") ELSE '0' ;
individual <= '1' WHEN (transmit_protocol /= "xaui") ELSE '0' ;
PROCESS (writeclk)
BEGIN
writeclk_dly <= writeclk;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
kchar_sync_1 <= '0';
kchar_sync <= '0';
echar_sync_1 <= '0';
echar_sync <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
kchar_sync_1 <= KCHAR;
kchar_sync <= kchar_sync_1;
echar_sync_1 <= ECHAR;
echar_sync <= echar_sync_1;
END IF;
END PROCESS;
-- outputs
dataout <= dataout_read(9 DOWNTO 0);
xgmdataout <= dataout_read(7 DOWNTO 0);
pre8b10bdataout <= dataout_read(9 DOWNTO 0);
forcedispout <= dataout_read(10);
ctrlenaout <= dataout_read(11);
xgmctrlena <= dataout_read(11);
rdenasync <= rdenasync_tmp;
PROCESS (reset, writeclk_dly, datain, forcedisp, ctrlena)
BEGIN
IF (reset = '1') THEN
datain_high(11 DOWNTO 0) <= "000000000000";
datain_low(11 DOWNTO 0) <= "000000000000";
ELSE
IF (channel_width = 10 OR channel_width = 20) THEN
IF (doublewidth = '1') THEN
datain_high(11 DOWNTO 0) <= ctrlena(1) & forcedisp(1) & datain(19 DOWNTO 10);
ELSE
datain_high(11 DOWNTO 0) <= ctrlena(0) & forcedisp(0) & datain(9 DOWNTO 0);
END IF;
datain_low(11 DOWNTO 0) <= ctrlena(0) & forcedisp(0) & datain(9 DOWNTO 0);
ELSE
IF (doublewidth = '1') THEN
datain_high(11 DOWNTO 0) <= ctrlena(1) & forcedisp(1) & "00" & datain(15 DOWNTO 8);
ELSE
datain_high(11 DOWNTO 0) <= ctrlena(0) & forcedisp(0) & "00" & datain(7 DOWNTO 0);
END IF;
datain_low(11 DOWNTO 0) <= ctrlena(0) & forcedisp(0) & "00" & datain(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
fifo_high_dly1 <= "000000000000";
fifo_high_dly2 <= "000000000000";
fifo_high_dly3 <= "000000000000";
fifo_high_tmp <= "000000000000";
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
fifo_high_dly1 <= datain_high;
fifo_high_dly2 <= fifo_high_dly1;
fifo_high_dly3 <= fifo_high_dly2;
fifo_high_tmp <= fifo_high_dly3;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
fifo_low_dly1 <= "000000000000";
fifo_low_dly2 <= "000000000000";
fifo_low_dly3 <= "000000000000";
fifo_low_tmp <= "000000000000";
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
fifo_low_dly1 <= datain_low;
fifo_low_dly2 <= fifo_low_dly1;
fifo_low_dly3 <= fifo_low_dly2;
fifo_low_tmp <= fifo_low_dly3;
END IF;
END PROCESS;
-- DATAOUT ENALBE LOGIC
out_ena1 <= (((NOT disablefifo AND rdenasync_tmp) AND (NOT doublewidth OR fifo_select_out)) AND NOT kchar_sync) AND NOT echar_sync ;
out_ena2 <= (((NOT disablefifo AND rdenasync_tmp) AND (doublewidth AND NOT fifo_select_out)) AND NOT kchar_sync) AND NOT echar_sync ;
out_ena3 <= ((disablefifo AND (NOT doublewidth OR NOT fifo_select_out)) AND NOT kchar_sync) AND NOT echar_sync ;
out_ena4 <= NOT kchar_sync AND echar_sync ;
out_ena5 <= (((disablefifo AND doublewidth) AND fifo_select_out) AND NOT kchar_sync) AND NOT echar_sync ;
-- Dataout, CTRL, FORCE_DISP registered by read clock
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
dataout_read(11 DOWNTO 0) <= "000000000000";
ELSIF (readclk'EVENT AND readclk = '1') THEN
IF (out_ena1 = '1') THEN
dataout_read <= fifo_low_tmp;
ELSIF (out_ena2 = '1') THEN
dataout_read <= fifo_high_tmp;
ELSIF (out_ena3 = '1') THEN
dataout_read <= datain_low;
ELSIF (out_ena4 = '1') THEN
dataout_read(7 DOWNTO 0) <= "11111110";
dataout_read(10) <= '0';
dataout_read(11) <= '1';
ELSIF (out_ena5 = '1') THEN
dataout_read <= datain_high;
ELSE
dataout_read(10) <= '0';
dataout_read(11) <= '1'; -- fixed from 0 to 1 in 3.0 .
IF ((NOT individual) = '1') THEN
dataout_read(7 DOWNTO 0) <= "00000111";
ELSE
dataout_read(7 DOWNTO 0) <= "10111100";
END IF;
END IF;
END IF; -- end of not reset
END PROCESS;
-- fifo select
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1' OR writeclk_dly = '1') THEN
fifo_select_out <= '1';
ELSE
fifo_select_out <= '0';
END IF;
END PROCESS;
PROCESS (reset, readclk)
BEGIN
IF (reset = '1') THEN
rd_enable_sync_1 <= '0';
rd_enable_sync_2 <= '0';
rd_enable_sync_out <= '0';
ELSIF (readclk'EVENT AND readclk = '1') THEN
rd_enable_sync_1 <= wr_enable OR disablefifo;
rd_enable_sync_2 <= rd_enable_sync_1;
rd_enable_sync_out <= rd_enable_sync_2;
END IF;
END PROCESS;
PROCESS (reset, writeclk_dly)
BEGIN
IF (reset = '1') THEN
wr_enable <= '0';
ELSIF (writeclk_dly'EVENT AND writeclk_dly = '1') THEN
wr_enable <= '1';
END IF;
END PROCESS;
rdenasync_tmp <= rd_enable_sync_out WHEN (individual) = '1' ELSE rd_enable_sync_1 ;
END arch_stratixgx_tx_core;
--
-- 4 to 1 MULTIPLEXER
--
library IEEE, stratixgx_gxb,std;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_hssi_mux4 IS
PORT (
Y : OUT std_logic;
I0 : IN std_logic;
I1 : IN std_logic;
I2 : IN std_logic;
I3 : IN std_logic;
C0 : IN std_logic;
C1 : IN std_logic);
END stratixgx_hssi_mux4;
ARCHITECTURE stratixgx_hssi_mux4_arch OF stratixgx_hssi_mux4 IS
SIGNAL Y_tmp : std_logic;
BEGIN
Y <= Y_tmp;
PROCESS (I0, I1, I2, I3, C0, C1)
VARIABLE Y_tmp1 : std_logic;
VARIABLE ctrl : std_logic_vector(1 DOWNTO 0);
BEGIN
ctrl := C1 & C0;
CASE ctrl IS
WHEN "00" =>
Y_tmp1 := I0;
WHEN "01" =>
Y_tmp1 := I1;
WHEN "10" =>
Y_tmp1 := I2;
WHEN "11" =>
Y_tmp1 := I3;
WHEN OTHERS =>
NULL;
END CASE;
Y_tmp <= Y_tmp1;
END PROCESS;
END stratixgx_hssi_mux4_arch;
--
-- DIVIDE BY TWO LOGIC
--
library IEEE, stratixgx_gxb,std;
use IEEE.std_logic_1164.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_hssi_divide_by_two IS
GENERIC (
divide : string := "true");
PORT (
reset : IN std_logic := '0';
clkin : IN std_logic;
clkout : OUT std_logic);
END stratixgx_hssi_divide_by_two;
ARCHITECTURE stratixgx_hssi_divide_by_two_arch OF stratixgx_hssi_divide_by_two IS
SIGNAL clktmp : std_logic := '0';
BEGIN
PROCESS (clkin, reset)
BEGIN
IF (divide = "false") THEN
clktmp <= clkin;
ELSIF (reset'event and (reset = '1')) THEN
clktmp <= '0';
ELSE
IF (reset = '0' and clkin'event and (clkin = '1')) THEN
clktmp <= NOT clktmp;
END IF;
END IF;
END PROCESS;
clkout <= clktmp;
END stratixgx_hssi_divide_by_two_arch;
--
-- stratixgx_xgm_interface
--
library IEEE, stratixgx_gxb;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use stratixgx_gxb.hssi_pack.all;
ENTITY stratixgx_xgm_interface IS
generic (
use_continuous_calibration_mode : String := "false";
mode_is_xaui : String := "false";
rx_ppm_setting_0 : integer := 0;
rx_ppm_setting_1 : integer := 0;
digital_test_output_select : integer := 0;
analog_test_output_signal_select : integer := 0;
analog_test_output_channel_select : integer := 0;
use_rx_calibration_status : String := "false";
use_global_serial_loopback : String := "false";
rx_calibration_test_write_value : integer := 0;
enable_rx_calibration_test_write : String := "false";
tx_calibration_test_write_value : integer := 0;
enable_tx_calibration_test_write : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_txdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_txctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdatain : VitalDelayArrayType01(31 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxctrl : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_rxrunningdisp : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_resetall : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_syncstatus : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_rdalign : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01
);
PORT (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
devpor : IN std_logic := '0';
devclrn : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0);
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0);
resetout : OUT std_logic;
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic;
-- NEW MDIO/PE ONLY PORTS
mdioclk : IN std_logic := '0';
mdiodisable : IN std_logic := '0';
mdioin : IN std_logic := '0';
rxppmselect : IN std_logic := '0';
scanclk : IN std_logic := '0';
scanin : IN std_logic := '0';
scanmode : IN std_logic := '0';
scanshift : IN std_logic := '0';
-- NEW MDIO/PE ONLY PORTS
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
digitalsmtest : OUT std_logic_vector(3 DOWNTO 0);
mdiooe : OUT std_logic;
mdioout : OUT std_logic;
scanout : OUT std_logic;
test : OUT std_logic;
-- RESET PORTS
txdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxanalogreset : IN std_logic_vector(3 DOWNTO 0) := "0000";
pllreset : IN std_logic := '0';
pllenable : IN std_logic := '1';
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
pllresetout : OUT std_logic
);
END stratixgx_xgm_interface;
ARCHITECTURE vital_stratixgx_xgm_interface_atom OF stratixgx_xgm_interface IS
-- input buffers
signal txdatain_ipd : std_logic_vector(31 downto 0);
signal txctrl_ipd : std_logic_vector(3 downto 0);
signal rdenablesync_ipd : std_logic;
signal txclk_ipd : std_logic;
signal rxdatain_ipd : std_logic_vector(31 downto 0);
signal rxctrl_ipd : std_logic_vector(3 downto 0);
signal rxrunningdisp_ipd : std_logic_vector(3 downto 0);
signal rxdatavalid_ipd : std_logic_vector(3 downto 0);
signal rxclk_ipd : std_logic;
signal resetall_ipd : std_logic;
signal adet_ipd : std_logic_vector(3 downto 0);
signal syncstatus_ipd : std_logic_vector(3 downto 0);
signal rdalign_ipd : std_logic_vector(3 downto 0);
signal recovclk_ipd : std_logic;
-- internal input signals
SIGNAL reset_int : std_logic;
SIGNAL extended_pllreset : std_logic;
SIGNAL rxdigitalresetout_tmp : std_logic_vector(3 downto 0) := "0000";
SIGNAL txdigitalresetout_tmp : std_logic_vector(3 downto 0) := "0000";
-- internal output signals
SIGNAL resetout_tmp : std_logic;
SIGNAL txdataout_xtmp1 : std_logic_vector(31 DOWNTO 0);
SIGNAL txctrlout_xtmp2 : std_logic_vector(3 DOWNTO 0);
SIGNAL rxdataout_xtmp3 : std_logic_vector(31 DOWNTO 0);
SIGNAL rxctrlout_xtmp4 : std_logic_vector(3 DOWNTO 0);
SIGNAL resetout_xtmp5 : std_logic;
SIGNAL alignstatus_xtmp6 : std_logic;
SIGNAL enabledeskew_xtmp7 : std_logic;
SIGNAL fiforesetrd_xtmp8 : std_logic;
component stratixgx_reset_block
PORT (
txdigitalreset : IN std_logic_vector(3 DOWNTO 0);
rxdigitalreset : IN std_logic_vector(3 DOWNTO 0);
rxanalogreset : IN std_logic_vector(3 DOWNTO 0);
pllreset : IN std_logic;
pllenable : IN std_logic;
txdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
rxdigitalresetout : OUT std_logic_vector(3 DOWNTO 0);
txanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
rxanalogresetout : OUT std_logic_vector(3 DOWNTO 0);
pllresetout : OUT std_logic);
END component;
component stratixgx_xgm_rx_sm
port (
rxdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
rxctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxrunningdisp : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxdatavalid : IN std_logic_vector(3 DOWNTO 0) := "0000";
rxclk : IN std_logic := '0';
resetall : IN std_logic := '0';
rxdataout : OUT std_logic_vector(31 DOWNTO 0);
rxctrlout : OUT std_logic_vector(3 DOWNTO 0)
);
end component;
component stratixgx_xgm_tx_sm
port (
txdatain : IN std_logic_vector(31 DOWNTO 0) := "00000000000000000000000000000000";
txctrl : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdenablesync : IN std_logic := '0';
txclk : IN std_logic := '0';
resetall : IN std_logic := '0';
txdataout : OUT std_logic_vector(31 DOWNTO 0);
txctrlout : OUT std_logic_vector(3 DOWNTO 0));
end component;
component stratixgx_xgm_dskw_sm
port (
resetall : IN std_logic := '0';
adet : IN std_logic_vector(3 DOWNTO 0) := "0000";
syncstatus : IN std_logic_vector(3 DOWNTO 0) := "0000";
rdalign : IN std_logic_vector(3 DOWNTO 0) := "0000";
recovclk : IN std_logic := '0';
alignstatus : OUT std_logic;
enabledeskew : OUT std_logic;
fiforesetrd : OUT std_logic);
end component;
BEGIN
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (txdatain_ipd(0), txdatain(0), tipd_txdatain(0));
VitalWireDelay (txdatain_ipd(1), txdatain(1), tipd_txdatain(1));
VitalWireDelay (txdatain_ipd(2), txdatain(2), tipd_txdatain(2));
VitalWireDelay (txdatain_ipd(3), txdatain(3), tipd_txdatain(3));
VitalWireDelay (txdatain_ipd(4), txdatain(4), tipd_txdatain(4));
VitalWireDelay (txdatain_ipd(5), txdatain(5), tipd_txdatain(5));
VitalWireDelay (txdatain_ipd(6), txdatain(6), tipd_txdatain(6));
VitalWireDelay (txdatain_ipd(7), txdatain(7), tipd_txdatain(7));
VitalWireDelay (txdatain_ipd(8), txdatain(8), tipd_txdatain(8));
VitalWireDelay (txdatain_ipd(9), txdatain(9), tipd_txdatain(9));
VitalWireDelay (txdatain_ipd(10), txdatain(10), tipd_txdatain(10));
VitalWireDelay (txdatain_ipd(11), txdatain(11), tipd_txdatain(11));
VitalWireDelay (txdatain_ipd(12), txdatain(12), tipd_txdatain(12));
VitalWireDelay (txdatain_ipd(13), txdatain(13), tipd_txdatain(13));
VitalWireDelay (txdatain_ipd(14), txdatain(14), tipd_txdatain(14));
VitalWireDelay (txdatain_ipd(15), txdatain(15), tipd_txdatain(15));
VitalWireDelay (txdatain_ipd(16), txdatain(16), tipd_txdatain(16));
VitalWireDelay (txdatain_ipd(17), txdatain(17), tipd_txdatain(17));
VitalWireDelay (txdatain_ipd(18), txdatain(18), tipd_txdatain(18));
VitalWireDelay (txdatain_ipd(19), txdatain(19), tipd_txdatain(19));
VitalWireDelay (txdatain_ipd(20), txdatain(20), tipd_txdatain(20));
VitalWireDelay (txdatain_ipd(21), txdatain(21), tipd_txdatain(21));
VitalWireDelay (txdatain_ipd(22), txdatain(22), tipd_txdatain(22));
VitalWireDelay (txdatain_ipd(23), txdatain(23), tipd_txdatain(23));
VitalWireDelay (txdatain_ipd(24), txdatain(24), tipd_txdatain(24));
VitalWireDelay (txdatain_ipd(25), txdatain(25), tipd_txdatain(25));
VitalWireDelay (txdatain_ipd(26), txdatain(26), tipd_txdatain(26));
VitalWireDelay (txdatain_ipd(27), txdatain(27), tipd_txdatain(27));
VitalWireDelay (txdatain_ipd(28), txdatain(28), tipd_txdatain(28));
VitalWireDelay (txdatain_ipd(29), txdatain(29), tipd_txdatain(29));
VitalWireDelay (txdatain_ipd(30), txdatain(30), tipd_txdatain(30));
VitalWireDelay (txdatain_ipd(31), txdatain(31), tipd_txdatain(31));
VitalWireDelay (rxdatain_ipd(0), rxdatain(0), tipd_rxdatain(0));
VitalWireDelay (rxdatain_ipd(1), rxdatain(1), tipd_rxdatain(1));
VitalWireDelay (rxdatain_ipd(2), rxdatain(2), tipd_rxdatain(2));
VitalWireDelay (rxdatain_ipd(3), rxdatain(3), tipd_rxdatain(3));
VitalWireDelay (rxdatain_ipd(4), rxdatain(4), tipd_rxdatain(4));
VitalWireDelay (rxdatain_ipd(5), rxdatain(5), tipd_rxdatain(5));
VitalWireDelay (rxdatain_ipd(6), rxdatain(6), tipd_rxdatain(6));
VitalWireDelay (rxdatain_ipd(7), rxdatain(7), tipd_rxdatain(7));
VitalWireDelay (rxdatain_ipd(8), rxdatain(8), tipd_rxdatain(8));
VitalWireDelay (rxdatain_ipd(9), rxdatain(9), tipd_rxdatain(9));
VitalWireDelay (rxdatain_ipd(10), rxdatain(10), tipd_rxdatain(10));
VitalWireDelay (rxdatain_ipd(11), rxdatain(11), tipd_rxdatain(11));
VitalWireDelay (rxdatain_ipd(12), rxdatain(12), tipd_rxdatain(12));
VitalWireDelay (rxdatain_ipd(13), rxdatain(13), tipd_rxdatain(13));
VitalWireDelay (rxdatain_ipd(14), rxdatain(14), tipd_rxdatain(14));
VitalWireDelay (rxdatain_ipd(15), rxdatain(15), tipd_rxdatain(15));
VitalWireDelay (rxdatain_ipd(16), rxdatain(16), tipd_rxdatain(16));
VitalWireDelay (rxdatain_ipd(17), rxdatain(17), tipd_rxdatain(17));
VitalWireDelay (rxdatain_ipd(18), rxdatain(18), tipd_rxdatain(18));
VitalWireDelay (rxdatain_ipd(19), rxdatain(19), tipd_rxdatain(19));
VitalWireDelay (rxdatain_ipd(20), rxdatain(20), tipd_rxdatain(20));
VitalWireDelay (rxdatain_ipd(21), rxdatain(21), tipd_rxdatain(21));
VitalWireDelay (rxdatain_ipd(22), rxdatain(22), tipd_rxdatain(22));
VitalWireDelay (rxdatain_ipd(23), rxdatain(23), tipd_rxdatain(23));
VitalWireDelay (rxdatain_ipd(24), rxdatain(24), tipd_rxdatain(24));
VitalWireDelay (rxdatain_ipd(25), rxdatain(25), tipd_rxdatain(25));
VitalWireDelay (rxdatain_ipd(26), rxdatain(26), tipd_rxdatain(26));
VitalWireDelay (rxdatain_ipd(27), rxdatain(27), tipd_rxdatain(27));
VitalWireDelay (rxdatain_ipd(28), rxdatain(28), tipd_rxdatain(28));
VitalWireDelay (rxdatain_ipd(29), rxdatain(29), tipd_rxdatain(29));
VitalWireDelay (rxdatain_ipd(30), rxdatain(30), tipd_rxdatain(30));
VitalWireDelay (rxdatain_ipd(31), rxdatain(31), tipd_rxdatain(31));
VitalWireDelay (txctrl_ipd(0), txctrl(0), tipd_txctrl(0));
VitalWireDelay (txctrl_ipd(1), txctrl(1), tipd_txctrl(1));
VitalWireDelay (txctrl_ipd(2), txctrl(2), tipd_txctrl(2));
VitalWireDelay (txctrl_ipd(3), txctrl(3), tipd_txctrl(3));
VitalWireDelay (rxctrl_ipd(0), rxctrl(0), tipd_rxctrl(0));
VitalWireDelay (rxctrl_ipd(1), rxctrl(1), tipd_rxctrl(1));
VitalWireDelay (rxctrl_ipd(2), rxctrl(2), tipd_rxctrl(2));
VitalWireDelay (rxctrl_ipd(3), rxctrl(3), tipd_rxctrl(3));
VitalWireDelay (rxrunningdisp_ipd(0), rxrunningdisp(0), tipd_rxrunningdisp(0));
VitalWireDelay (rxrunningdisp_ipd(1), rxrunningdisp(1), tipd_rxrunningdisp(1));
VitalWireDelay (rxrunningdisp_ipd(2), rxrunningdisp(2), tipd_rxrunningdisp(2));
VitalWireDelay (rxrunningdisp_ipd(3), rxrunningdisp(3), tipd_rxrunningdisp(3));
VitalWireDelay (rxdatavalid_ipd(0), rxdatavalid(0), tipd_rxdatavalid(0));
VitalWireDelay (rxdatavalid_ipd(1), rxdatavalid(1), tipd_rxdatavalid(1));
VitalWireDelay (rxdatavalid_ipd(2), rxdatavalid(2), tipd_rxdatavalid(2));
VitalWireDelay (rxdatavalid_ipd(3), rxdatavalid(3), tipd_rxdatavalid(3));
VitalWireDelay (rdenablesync_ipd, rdenablesync, tipd_rdenablesync);
VitalWireDelay (txclk_ipd, txclk, tipd_txclk);
VitalWireDelay (rxclk_ipd, rxclk, tipd_rxclk);
VitalWireDelay (recovclk_ipd, recovclk, tipd_recovclk);
VitalWireDelay (resetall_ipd, resetall, tipd_resetall);
VitalWireDelay (adet_ipd(0), adet(0), tipd_adet(0));
VitalWireDelay (adet_ipd(1), adet(1), tipd_adet(1));
VitalWireDelay (adet_ipd(2), adet(2), tipd_adet(2));
VitalWireDelay (adet_ipd(3), adet(3), tipd_adet(3));
VitalWireDelay (syncstatus_ipd(0), syncstatus(0), tipd_syncstatus(0));
VitalWireDelay (syncstatus_ipd(1), syncstatus(1), tipd_syncstatus(1));
VitalWireDelay (syncstatus_ipd(2), syncstatus(2), tipd_syncstatus(2));
VitalWireDelay (syncstatus_ipd(3), syncstatus(3), tipd_syncstatus(3));
VitalWireDelay (rdalign_ipd(0), rdalign(0), tipd_rdalign(0));
VitalWireDelay (rdalign_ipd(1), rdalign(1), tipd_rdalign(1));
VitalWireDelay (rdalign_ipd(2), rdalign(2), tipd_rdalign(2));
VitalWireDelay (rdalign_ipd(3), rdalign(3), tipd_rdalign(3));
end block;
------------------------
-- Timing Check Section
------------------------
txdataout <= txdataout_xtmp1;
txctrlout <= txctrlout_xtmp2;
rxdataout <= rxdataout_xtmp3;
rxctrlout <= rxctrlout_xtmp4;
resetout <= resetout_xtmp5;
alignstatus <= alignstatus_xtmp6;
enabledeskew <= enabledeskew_xtmp7;
fiforesetrd <= fiforesetrd_xtmp8;
reset_int <= resetall_ipd ;
rxdigitalresetout <= rxdigitalresetout_tmp;
txdigitalresetout <= txdigitalresetout_tmp;
resetout_tmp <= resetall_ipd ;
extended_pllreset <= pllreset OR (NOT devpor) OR (NOT devclrn);
stratixgx_reset : stratixgx_reset_block
port map (
txdigitalreset => txdigitalreset,
rxdigitalreset => rxdigitalreset,
rxanalogreset => rxanalogreset,
pllreset => extended_pllreset,
pllenable => pllenable,
txdigitalresetout => txdigitalresetout_tmp,
rxdigitalresetout => rxdigitalresetout_tmp,
txanalogresetout => txanalogresetout,
rxanalogresetout => rxanalogresetout,
pllresetout => pllresetout);
s_xgm_rx_sm : stratixgx_xgm_rx_sm
PORT MAP (
rxdatain => rxdatain_ipd,
rxctrl => rxctrl_ipd,
rxrunningdisp => rxrunningdisp_ipd,
rxdatavalid => rxdatavalid_ipd,
rxclk => rxclk_ipd,
resetall => rxdigitalresetout_tmp(0),
rxdataout => rxdataout_xtmp3,
rxctrlout => rxctrlout_xtmp4);
s_xgm_tx_sm : stratixgx_xgm_tx_sm
PORT MAP (
txdatain => txdatain_ipd,
txctrl => txctrl_ipd,
rdenablesync => rdenablesync_ipd,
txclk => txclk_ipd,
resetall => txdigitalresetout_tmp(0),
txdataout => txdataout_xtmp1,
txctrlout => txctrlout_xtmp2);
s_xgm_dskw_sm : stratixgx_xgm_dskw_sm
PORT MAP (
resetall => rxdigitalresetout_tmp(0),
adet => adet_ipd,
syncstatus => syncstatus_ipd,
rdalign => rdalign_ipd,
recovclk => recovclk_ipd,
alignstatus => alignstatus_xtmp6,
enabledeskew => enabledeskew_xtmp7,
fiforesetrd => fiforesetrd_xtmp8);
resetout_xtmp5 <= resetout_tmp AND '1';
----------------------
-- Path Delay Section
----------------------
END vital_stratixgx_xgm_interface_atom;
--
-- STRATIXGX_HSSI_RECEIVER
--
library IEEE, stratixgx_gxb,std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use stratixgx_gxb.hssi_pack.all;
use std.textio.all;
entity stratixgx_hssi_receiver is
generic (
channel_num : integer := 1;
channel_width : integer := 20;
deserialization_factor : integer := 10;
run_length : integer := 4;
run_length_enable : String := "false";
use_8b_10b_mode : String := "false";
use_double_data_mode : String := "false";
use_rate_match_fifo : String := "false";
rate_matching_fifo_mode : String := "none";
use_channel_align : String := "false";
use_symbol_align : String := "true";
use_auto_bit_slip : String := "false";
use_parallel_feedback : String := "false";
use_post8b10b_feedback : String := "false";
send_reverse_parallel_feedback : String := "false";
synchronization_mode : String := "none";
align_pattern : String := "0000000000000000";
align_pattern_length : integer := 7;
infiniband_invalid_code : integer := 0;
disparity_mode : String := "false";
clk_out_mode_reference : String := "true";
cruclk_period : integer := 5000;
cruclk_multiplier : integer := 4;
use_cruclk_divider : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
use_equalizer_ctrl_signal : String := "false";
enable_dc_coupling : String := "false";
equalizer_ctrl_setting : integer := 20;
signal_threshold_select : integer := 2;
vco_bypass : String := "false";
force_signal_detect : String := "false";
bandwidth_type : String := "low";
for_engineering_sample_device : String := "true"; -- new in 3.0 SP2
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_cruclk : VitalDelayType01 := DefpropDelay01;
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_analogreset : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_equalizerctrl : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_post8b10b : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefPropDelay01);
tipd_slpbk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_enacdet : VitalDelayType01 := DefpropDelay01;
tipd_we : VitalDelayType01 := DefpropDelay01;
tipd_re : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tsetup_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_re_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_dataout_posedge : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_syncstatus_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_patterndetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_ctrldetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_errdetect_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_disperr_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_a1a2sizeout_posedge : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_fifofull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoempty_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostfull_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_fifoalmostempty_posedge : VitalDelayType01 := DefPropDelay01
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
pllclk : in std_logic := '0';
masterclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
serialfdbk : in std_logic := '0';
parallelfdbk : in std_logic_vector(9 downto 0) := "0000000000";
post8b10b : in std_logic_vector(9 downto 0) := "0000000000";
slpbk : in std_logic := '0';
bitslip : in std_logic := '0';
enacdet : in std_logic := '0';
we : in std_logic := '0';
re : in std_logic := '0';
alignstatus : in std_logic := '0';
disablefifordin : in std_logic := '0';
disablefifowrin : in std_logic := '0';
fifordin : in std_logic := '0';
enabledeskew : in std_logic := '0';
fiforesetrd : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrlin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
a1a2size : in std_logic := '0';
locktorefclk : in std_logic := '0';
locktodata : in std_logic := '0';
equalizerctrl : in std_logic_vector(2 downto 0) := "000";
syncstatus : out std_logic_vector(1 downto 0);
patterndetect : out std_logic_vector(1 downto 0);
ctrldetect : out std_logic_vector(1 downto 0);
errdetect : out std_logic_vector(1 downto 0);
disperr : out std_logic_vector(1 downto 0);
syncstatusdeskew : out std_logic;
adetectdeskew : out std_logic;
rdalign : out std_logic;
dataout : out std_logic_vector(19 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrldet : out std_logic;
xgmrunningdisp : out std_logic;
xgmdatavalid : out std_logic;
fifofull : out std_logic;
fifoalmostfull : out std_logic;
fifoempty : out std_logic;
fifoalmostempty : out std_logic;
disablefifordout : out std_logic;
disablefifowrout : out std_logic;
fifordout : out std_logic;
signaldetect : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
rlv : out std_logic;
clkout : out std_logic;
recovclkout : out std_logic;
bisterr : out std_logic := '0';
bistdone : out std_logic := '1';
a1a2sizeout : out std_logic_vector(1 downto 0)
);
end stratixgx_hssi_receiver;
architecture vital_receiver_atom of stratixgx_hssi_receiver is
signal datain_ipd : std_logic;
signal cruclk_ipd : std_logic;
signal pllclk_ipd : std_logic;
signal masterclk_ipd : std_logic;
signal coreclk_ipd : std_logic;
signal softreset_ipd : std_logic := '0';
signal serialfdbk_ipd : std_logic := '0';
signal analogreset_ipd : std_logic := '0';
signal locktorefclk_ipd : std_logic := '0';
signal locktodata_ipd : std_logic := '0';
signal equalizerctrl_ipd : std_logic_vector(2 downto 0);
signal parallelfdbk_ipd : std_logic_vector(9 downto 0);
signal post8b10b_ipd : std_logic_vector(9 downto 0);
signal slpbk_ipd : std_logic := '0';
signal bitslip_ipd : std_logic := '0';
signal a1a2size_ipd : std_logic := '0';
signal enacdet_ipd : std_logic := '0';
signal we_ipd: std_logic := '0';
signal re_ipd : std_logic := '0';
signal alignstatus_ipd : std_logic := '0';
signal disablefifordin_ipd : std_logic := '0';
signal disablefifowrin_ipd : std_logic := '0';
signal fifordin_ipd : std_logic := '0';
signal enabledeskew_ipd : std_logic := '0';
signal fiforesetrd_ipd : std_logic := '0';
signal xgmdatain_ipd : std_logic_vector(7 downto 0);
signal xgmctrlin_ipd : std_logic := '0';
signal clkout_tmp : std_logic;
signal dataout_tmp : std_logic_vector(19 downto 0);
--constant signals
signal vcc : std_logic := '1';
signal gnd : std_logic := '0';
signal idle_bus : std_logic_vector(9 downto 0) := "0000000000";
--lower lever softreset
signal reset_int : std_logic;
-- serdes output signals
signal serdes_clkout : std_logic; --receovered clock
signal serdes_rlv : std_logic;
signal serdes_signaldetect : std_logic;
signal serdes_lock : std_logic;
signal serdes_freqlock : std_logic;
signal serdes_dataout : std_logic_vector(9 downto 0);
-- word aligner input/output signals
signal wa_datain : std_logic_vector(9 downto 0);
signal wa_clk : std_logic;
signal wa_enacdet : std_logic;
signal wa_bitslip : std_logic;
signal wa_a1a2size : std_logic;
signal wa_aligneddata : std_logic_vector(9 downto 0);
signal wa_aligneddatapre : std_logic_vector(9 downto 0);
signal wa_invalidcode : std_logic;
signal wa_invalidcodepre : std_logic;
signal wa_disperr : std_logic;
signal wa_disperrpre : std_logic;
signal wa_patterndetect : std_logic;
signal wa_patterndetectpre : std_logic;
signal wa_syncstatus : std_logic;
signal wa_syncstatusdeskew : std_logic;
-- deskew FIFO input/output signals
signal dsfifo_datain : std_logic_vector(9 downto 0);
signal dsfifo_errdetectin : std_logic;
signal dsfifo_syncstatusin : std_logic;
signal dsfifo_disperrin : std_logic;
signal dsfifo_patterndetectin : std_logic;
signal dsfifo_writeclock : std_logic;
signal dsfifo_readclock : std_logic;
signal dsfifo_fiforesetrd : std_logic;
signal dsfifo_enabledeskew : std_logic;
signal dsfifo_dataout : std_logic_vector(9 downto 0);
signal dsfifo_dataoutpre : std_logic_vector(9 downto 0);
signal dsfifo_errdetect : std_logic;
signal dsfifo_syncstatus : std_logic;
signal dsfifo_disperr : std_logic;
signal dsfifo_patterndetect : std_logic;
signal dsfifo_errdetectpre : std_logic;
signal dsfifo_syncstatuspre : std_logic;
signal dsfifo_disperrpre : std_logic;
signal dsfifo_patterndetectpre : std_logic;
signal dsfifo_adetectdeskew : std_logic;
signal dsfifo_rdalign : std_logic;
-- comp FIFO input/output signals
signal cmfifo_datain : std_logic_vector(9 downto 0);
signal cmfifo_datainpre : std_logic_vector(9 downto 0);
signal cmfifo_invalidcodein : std_logic;
signal cmfifo_invalidcodeinpre : std_logic;
signal cmfifo_disperrin : std_logic;
signal cmfifo_disperrinpre : std_logic;
signal cmfifo_patterndetectin : std_logic;
signal cmfifo_patterndetectinpre : std_logic;
signal cmfifo_syncstatusin : std_logic;
signal cmfifo_syncstatusinpre : std_logic;
signal cmfifo_writeclk : std_logic;
signal cmfifo_readclk : std_logic;
signal cmfifo_alignstatus : std_logic;
signal cmfifo_re : std_logic;
signal cmfifo_we : std_logic;
signal cmfifo_fifordin : std_logic;
signal cmfifo_disablefifordin : std_logic;
signal cmfifo_disablefifowrin : std_logic;
signal cmfifo_dataout : std_logic_vector(9 downto 0);
signal cmfifo_invalidcode : std_logic;
signal cmfifo_syncstatus : std_logic;
signal cmfifo_disperr : std_logic;
signal cmfifo_patterndetect : std_logic;
signal cmfifo_datavalid : std_logic;
signal cmfifo_fifofull : std_logic;
signal cmfifo_fifoalmostfull : std_logic;
signal cmfifo_fifoempty : std_logic;
signal cmfifo_fifoalmostempty : std_logic;
signal cmfifo_disablefifordout : std_logic;
signal cmfifo_disablefifowrout : std_logic;
signal cmfifo_fifordout : std_logic;
-- 8B10B decode input/output signals
signal decoder_clk : std_logic;
signal decoder_datain : std_logic_vector(9 downto 0);
signal decoder_errdetectin : std_logic;
signal decoder_syncstatusin : std_logic;
signal decoder_disperrin : std_logic;
signal decoder_patterndetectin : std_logic;
signal decoder_indatavalid : std_logic;
signal decoder_dataout : std_logic_vector(7 downto 0);
signal decoder_tenBdata : std_logic_vector(9 downto 0);
signal decoder_valid : std_logic;
signal decoder_errdetect : std_logic;
signal decoder_syncstatus : std_logic;
signal decoder_disperr : std_logic;
signal decoder_patterndetect : std_logic;
signal decoder_rderr : std_logic;
signal decoder_decdatavalid : std_logic;
signal decoder_ctrldetect : std_logic;
signal decoder_xgmdatavalid : std_logic;
signal decoder_xgmrunningdisp : std_logic;
signal decoder_xgmctrldet : std_logic;
signal decoder_xgmdataout : std_logic_vector(7 downto 0);
-- rx_core input/output signals
signal core_datain : std_logic_vector(9 downto 0);
signal core_writeclk : std_logic;
signal core_readclk : std_logic;
signal core_decdatavalid : std_logic;
signal core_xgmdatain : std_logic_vector(7 downto 0);
signal core_xgmctrlin : std_logic;
signal core_post8b10b : std_logic_vector(9 downto 0);
signal core_syncstatusin : std_logic;
signal core_errdetectin: std_logic;
signal core_ctrldetectin: std_logic;
signal core_disparityerrin: std_logic;
signal core_patterndetectin: std_logic;
signal core_dataout : std_logic_vector(19 downto 0);
signal core_clkout : std_logic;
signal core_syncstatus : std_logic_vector(1 downto 0);
signal core_errdetect : std_logic_vector(1 downto 0);
signal core_ctrldetect : std_logic_vector(1 downto 0);
signal core_disparityerr : std_logic_vector(1 downto 0);
signal core_patterndetect : std_logic_vector(1 downto 0);
signal core_a1a2sizeout : std_logic_vector(1 downto 0);
-- clkout mux output
-- added gfifo
signal clkoutmux_clkout : std_logic;
signal clkoutmux_clkout_pre : std_logic;
-- MAIN CLOCKS
SIGNAL rxrdclk_mux1 : std_logic;
SIGNAL rxrdclk_mux1_by2 : std_logic;
SIGNAL rxrdclkmux1_c0 : std_logic;
SIGNAL rxrdclkmux1_c1 : std_logic;
SIGNAL rxrdclkmux2_c0 : std_logic;
SIGNAL rxrdclkmux2_c1 : std_logic;
SIGNAL clk2_mux1 : std_logic;
SIGNAL clk2mux1_c0 : std_logic;
SIGNAL clk2mux1_c1 : std_logic;
SIGNAL rcvd_clk : std_logic;
SIGNAL clk_1 : std_logic;
SIGNAL clk_2 : std_logic;
SIGNAL rx_rd_clk : std_logic;
SIGNAL rx_rd_clk_mux : std_logic;
-- sub module componet declaration
component stratixgx_hssi_rx_serdes
generic (
channel_width : integer := 10;
rlv_length : integer := 1;
run_length_enable : String := "false";
cruclk_period : integer :=5000;
cruclk_multiplier : integer :=4;
use_cruclk_divider : String := "false";
use_double_data_mode : string := "false"
);
port (
datain : in std_logic := '0';
cruclk : in std_logic := '0';
areset : in std_logic := '0';
feedback : in std_logic := '0';
fbkcntl : in std_logic := '0';
ltr : in std_logic := '0';
ltd : in std_logic := '0';
dataout : out std_logic_vector(9 downto 0);
clkout : out std_logic;
rlv : out std_logic;
lock : out std_logic;
freqlock : out std_logic;
signaldetect : out std_logic
);
end component;
component stratixgx_hssi_word_aligner
generic (
channel_width : integer := 10;
align_pattern_length: integer := 10;
infiniband_invalid_code : integer := 0;
align_pattern : string := "0000000101111100";
synchronization_mode: string := "XAUI";
use_8b_10b_mode : string := "true";
use_auto_bit_slip : string := "true"
);
port (
datain : in std_logic_vector(9 downto 0) := "0000000000";
clk : in std_logic := '0';
softreset : in std_logic := '0';
enacdet : in std_logic := '0';
bitslip : in std_logic := '0';
a1a2size : in std_logic := '0';
aligneddata : out std_logic_vector(9 downto 0);
aligneddatapre : out std_logic_vector(9 downto 0);
invalidcode : out std_logic;
invalidcodepre : out std_logic;
syncstatus : out std_logic;
syncstatusdeskew : out std_logic;
disperr : out std_logic;
disperrpre : out std_logic;
patterndetect : out std_logic;
patterndetectpre : out std_logic
);
end component;
component stratixgx_deskew_fifo
port
(
datain : IN std_logic_vector(9 DOWNTO 0) := "0000000000";
errdetectin : IN std_logic := '0';
syncstatusin : IN std_logic := '0';
disperrin : IN std_logic := '0';
patterndetectin : IN std_logic := '0';
writeclock : IN std_logic := '0';
readclock : IN std_logic := '0';
adetectdeskew : OUT std_logic := '0';
fiforesetrd : IN std_logic := '0';
enabledeskew : IN std_logic := '0';
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(9 DOWNTO 0) := "0000000000";
dataoutpre : OUT std_logic_vector(9 DOWNTO 0) := "0000000000";
errdetect : OUT std_logic := '0';
syncstatus : OUT std_logic := '0';
disperr : OUT std_logic := '0';
patterndetect : OUT std_logic := '0';
errdetectpre : OUT std_logic := '0';
syncstatuspre : OUT std_logic := '0';
disperrpre : OUT std_logic := '0';
patterndetectpre : OUT std_logic := '0';
rdalign : OUT std_logic := '0'
);
end component;
component stratixgx_comp_fifo
GENERIC (
use_rate_match_fifo : string := "true";
rate_matching_fifo_mode : string := "xaui";
use_channel_align : string := "true";
for_engineering_sample_device : String := "true"; -- new in 3.0 SP2
channel_num : integer := 0
);
port (
datain : IN std_logic_vector(9 DOWNTO 0);
datainpre : IN std_logic_vector(9 DOWNTO 0);
reset : IN std_logic;
errdetectin : IN std_logic;
syncstatusin : IN std_logic;
disperrin : IN std_logic;
patterndetectin : IN std_logic;
errdetectinpre : IN std_logic;
syncstatusinpre : IN std_logic;
disperrinpre : IN std_logic;
patterndetectinpre : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
re : IN std_logic;
we : IN std_logic;
fifordin : IN std_logic;
disablefifordin : IN std_logic;
disablefifowrin : IN std_logic;
alignstatus : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
errdetectout : OUT std_logic;
syncstatus : OUT std_logic;
disperr : OUT std_logic;
patterndetect : OUT std_logic;
codevalid : OUT std_logic;
fifofull : OUT std_logic;
fifoalmostful : OUT std_logic;
fifoempty : OUT std_logic;
fifoalmostempty : OUT std_logic;
disablefifordout : OUT std_logic;
disablefifowrout : OUT std_logic;
fifordout : OUT std_logic
);
end component;
component stratixgx_8b10b_decoder
port (
clk : in std_logic := '0';
reset : in std_logic := '0'; -- reset the decoder
errdetectin : in std_logic := '0';
syncstatusin: in std_logic := '0';
disperrin : in std_logic := '0';
patterndetectin : in std_logic := '0';
datainvalid : in std_logic := '0';
datain : in std_logic_vector(9 downto 0) := "0000000000";
valid : out std_logic := '1'; -- valid decode
dataout : out std_logic_vector(7 downto 0) := "00000000";
tenBdata : OUT std_logic_vector(9 DOWNTO 0) := "0000000000";
errdetect : out std_logic := '0';
syncstatus : out std_logic := '0';
disperr : out std_logic := '0';
patterndetect : out std_logic := '0';
kout : out std_logic := '0'; -- high if decode of control word
rderr : out std_logic := '0'; -- running disparity error
decdatavalid: out std_logic := '0';
xgmdatavalid: out std_logic := '0';
xgmrunningdisp : out std_logic := '0';
xgmctrldet : out std_logic := '0';
xgmdataout : out std_logic_vector(7 downto 0) := "00000000"
);
end component;
component stratixgx_rx_core
GENERIC (
channel_width : integer := 10;
use_double_data_mode : string := "false";
use_channel_align : string := "false";
use_8b_10b_mode : string := "true";
align_pattern : string := "0000000000000000";
synchronization_mode : string := "none");
PORT (
reset : IN std_logic;
writeclk : IN std_logic;
readclk : IN std_logic;
errdetectin : IN std_logic;
patterndetectin : IN std_logic;
decdatavalid : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
post8b10b : IN std_logic_vector(9 DOWNTO 0);
datain : IN std_logic_vector(9 DOWNTO 0);
xgmctrlin : IN std_logic;
ctrldetectin : IN std_logic;
syncstatusin : IN std_logic;
disparityerrin : IN std_logic;
syncstatus : OUT std_logic_vector(1 DOWNTO 0);
errdetect : OUT std_logic_vector(1 DOWNTO 0);
ctrldetect : OUT std_logic_vector(1 DOWNTO 0);
disparityerr : OUT std_logic_vector(1 DOWNTO 0);
patterndetect : OUT std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(19 DOWNTO 0);
a1a2sizeout : OUT std_logic_vector(1 DOWNTO 0);
clkout : OUT std_logic);
end component;
component stratixgx_hssi_mux4
PORT (
Y : OUT std_logic;
I0 : IN std_logic;
I1 : IN std_logic;
I2 : IN std_logic;
I3 : IN std_logic;
C0 : IN std_logic;
C1 : IN std_logic);
END component;
component stratixgx_hssi_divide_by_two
GENERIC (
divide : string := "true");
PORT (
reset : IN std_logic := '0';
clkin : IN std_logic;
clkout : OUT std_logic);
END component;
-- end of sub module componet declaration
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (cruclk_ipd, cruclk, tipd_cruclk);
VitalWireDelay (pllclk_ipd, pllclk, tipd_pllclk);
VitalWireDelay (masterclk_ipd, masterclk, tipd_masterclk);
VitalWireDelay (coreclk_ipd, coreclk, tipd_coreclk);
VitalWireDelay (softreset_ipd, softreset, tipd_softreset);
VitalWireDelay (serialfdbk_ipd, serialfdbk, tipd_serialfdbk);
VitalWireDelay (analogreset_ipd, analogreset, tipd_analogreset);
VitalWireDelay (locktorefclk_ipd, locktorefclk, tipd_locktorefclk);
VitalWireDelay (locktodata_ipd, locktodata, tipd_locktodata);
VitalWireDelay (equalizerctrl_ipd(0), equalizerctrl(0), tipd_equalizerctrl(0));
VitalWireDelay (equalizerctrl_ipd(1), equalizerctrl(1), tipd_equalizerctrl(1));
VitalWireDelay (equalizerctrl_ipd(2), equalizerctrl(2), tipd_equalizerctrl(2));
VitalWireDelay (parallelfdbk_ipd(0), parallelfdbk(0), tipd_parallelfdbk(0));
VitalWireDelay (parallelfdbk_ipd(1), parallelfdbk(1), tipd_parallelfdbk(1));
VitalWireDelay (parallelfdbk_ipd(2), parallelfdbk(2), tipd_parallelfdbk(2));
VitalWireDelay (parallelfdbk_ipd(3), parallelfdbk(3), tipd_parallelfdbk(3));
VitalWireDelay (parallelfdbk_ipd(4), parallelfdbk(4), tipd_parallelfdbk(4));
VitalWireDelay (parallelfdbk_ipd(5), parallelfdbk(5), tipd_parallelfdbk(5));
VitalWireDelay (parallelfdbk_ipd(6), parallelfdbk(6), tipd_parallelfdbk(6));
VitalWireDelay (parallelfdbk_ipd(7), parallelfdbk(7), tipd_parallelfdbk(7));
VitalWireDelay (parallelfdbk_ipd(8), parallelfdbk(8), tipd_parallelfdbk(8));
VitalWireDelay (parallelfdbk_ipd(9), parallelfdbk(9), tipd_parallelfdbk(9));
VitalWireDelay (post8b10b_ipd(0), post8b10b(0), tipd_post8b10b(0));
VitalWireDelay (post8b10b_ipd(1), post8b10b(1), tipd_post8b10b(1));
VitalWireDelay (post8b10b_ipd(2), post8b10b(2), tipd_post8b10b(2));
VitalWireDelay (post8b10b_ipd(3), post8b10b(3), tipd_post8b10b(3));
VitalWireDelay (post8b10b_ipd(4), post8b10b(4), tipd_post8b10b(4));
VitalWireDelay (post8b10b_ipd(5), post8b10b(5), tipd_post8b10b(5));
VitalWireDelay (post8b10b_ipd(6), post8b10b(6), tipd_post8b10b(6));
VitalWireDelay (post8b10b_ipd(7), post8b10b(7), tipd_post8b10b(7));
VitalWireDelay (post8b10b_ipd(8), post8b10b(8), tipd_post8b10b(8));
VitalWireDelay (post8b10b_ipd(9), post8b10b(9), tipd_post8b10b(9));
VitalWireDelay (slpbk_ipd, slpbk, tipd_slpbk);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (a1a2size_ipd, a1a2size, tipd_a1a2size);
VitalWireDelay (enacdet_ipd, enacdet, tipd_enacdet);
VitalWireDelay (we_ipd, we, tipd_we);
VitalWireDelay (re_ipd, re, tipd_re);
VitalWireDelay (alignstatus_ipd, alignstatus, tipd_alignstatus);
VitalWireDelay (disablefifordin_ipd, disablefifordin, tipd_disablefifordin);
VitalWireDelay (disablefifowrin_ipd, disablefifowrin, tipd_disablefifowrin);
VitalWireDelay (fifordin_ipd, fifordin, tipd_fifordin);
VitalWireDelay (enabledeskew_ipd, enabledeskew, tipd_enabledeskew);
VitalWireDelay (fiforesetrd_ipd, fiforesetrd, tipd_fiforesetrd);
VitalWireDelay (xgmdatain_ipd(0), xgmdatain(0), tipd_xgmdatain(0));
VitalWireDelay (xgmdatain_ipd(1), xgmdatain(1), tipd_xgmdatain(1));
VitalWireDelay (xgmdatain_ipd(2), xgmdatain(2), tipd_xgmdatain(2));
VitalWireDelay (xgmdatain_ipd(3), xgmdatain(3), tipd_xgmdatain(3));
VitalWireDelay (xgmdatain_ipd(4), xgmdatain(4), tipd_xgmdatain(4));
VitalWireDelay (xgmdatain_ipd(5), xgmdatain(5), tipd_xgmdatain(5));
VitalWireDelay (xgmdatain_ipd(6), xgmdatain(6), tipd_xgmdatain(6));
VitalWireDelay (xgmdatain_ipd(7), xgmdatain(7), tipd_xgmdatain(7));
VitalWireDelay (xgmctrlin_ipd, xgmctrlin, tipd_xgmctrlin);
end block;
-- generate internal inut signals
reset_int <= softreset_ipd;
-- word_align inputs
wa_datain <= parallelfdbk when (use_parallel_feedback = "true") else serdes_dataout;
wa_clk <= rcvd_clk;
wa_enacdet <= enacdet_ipd;
wa_bitslip <= bitslip_ipd;
wa_a1a2size <= a1a2size_ipd;
-- deskew FIFO inputs
dsfifo_datain <= wa_aligneddata WHEN (use_symbol_align = "true") ELSE idle_bus;
dsfifo_errdetectin <= wa_invalidcode WHEN (use_symbol_align = "true") ELSE '0';
dsfifo_syncstatusin <= wa_syncstatus WHEN (use_symbol_align = "true") ELSE '1';
dsfifo_disperrin <= wa_disperr WHEN (use_symbol_align = "true") ELSE '0';
dsfifo_patterndetectin <= wa_patterndetect WHEN (use_symbol_align = "true") ELSE '0';
dsfifo_writeclock <= rcvd_clk;
dsfifo_readclock <= clk_1;
dsfifo_fiforesetrd <= fiforesetrd_ipd;
dsfifo_enabledeskew <= enabledeskew_ipd;
-- comp FIFO inputs
cmfifo_datain <= dsfifo_dataout WHEN (use_channel_align = "true") ELSE wa_aligneddata WHEN (use_symbol_align = "true") ELSE serdes_dataout;
cmfifo_datainpre <= dsfifo_dataoutpre WHEN (use_channel_align = "true") ELSE wa_aligneddatapre WHEN (use_symbol_align = "true") ELSE idle_bus;
cmfifo_invalidcodein <= dsfifo_errdetect WHEN (use_channel_align = "true") ELSE wa_invalidcode WHEN (use_symbol_align = "true") ELSE '0';
cmfifo_syncstatusin <= dsfifo_syncstatus WHEN (use_channel_align = "true") ELSE wa_syncstatus WHEN (use_symbol_align = "true") ELSE '1';
cmfifo_disperrin <= dsfifo_disperr WHEN (use_channel_align = "true") ELSE wa_disperr WHEN (use_symbol_align = "true") ELSE '0';
cmfifo_patterndetectin <= dsfifo_patterndetect WHEN (use_channel_align = "true") ELSE wa_patterndetect WHEN (use_symbol_align = "true") ELSE '1';
cmfifo_invalidcodeinpre <= dsfifo_errdetectpre WHEN (use_channel_align = "true") ELSE wa_invalidcodepre WHEN (use_symbol_align = "true") ELSE '0';
cmfifo_syncstatusinpre <= dsfifo_syncstatuspre WHEN (use_channel_align = "true") ELSE wa_syncstatusdeskew WHEN (use_symbol_align = "true") ELSE '1';
cmfifo_disperrinpre <= dsfifo_disperrpre WHEN (use_channel_align = "true") ELSE wa_disperrpre WHEN (use_symbol_align = "true") ELSE '0';
cmfifo_patterndetectinpre <= dsfifo_patterndetectpre WHEN (use_channel_align = "true") ELSE wa_patterndetectpre WHEN (use_symbol_align = "true") ELSE '0';
cmfifo_writeclk <= clk_1;
cmfifo_readclk <= clk_2;
cmfifo_alignstatus <= alignstatus_ipd;
cmfifo_re <= re_ipd;
cmfifo_we <= we_ipd;
cmfifo_fifordin <= fifordin_ipd;
cmfifo_disablefifordin <= disablefifordin_ipd;
cmfifo_disablefifowrin <= disablefifowrin_ipd;
-- 8B10B decoder inputs
decoder_clk <= clk_2;
decoder_datain <= cmfifo_dataout WHEN (use_rate_match_fifo = "true") ELSE dsfifo_dataout WHEN (use_channel_align = "true") ELSE wa_aligneddata WHEN (use_symbol_align = "true") ELSE serdes_dataout;
decoder_errdetectin <= cmfifo_invalidcode WHEN (use_rate_match_fifo = "true") ELSE dsfifo_errdetect WHEN (use_channel_align = "true") ELSE wa_invalidcode WHEN (use_symbol_align = "true") ELSE '0';
decoder_syncstatusin <= cmfifo_syncstatus WHEN (use_rate_match_fifo = "true") ELSE dsfifo_syncstatus WHEN (use_channel_align = "true") ELSE wa_syncstatus WHEN (use_symbol_align = "true") ELSE '1';
decoder_disperrin <= cmfifo_disperr WHEN (use_rate_match_fifo = "true") ELSE dsfifo_disperr WHEN (use_channel_align = "true") ELSE wa_disperr WHEN (use_symbol_align = "true") ELSE '0';
decoder_patterndetectin <= cmfifo_patterndetect WHEN (use_rate_match_fifo = "true") ELSE dsfifo_patterndetect WHEN (use_channel_align = "true") ELSE wa_patterndetect WHEN (use_symbol_align = "true") ELSE '0';
decoder_indatavalid <= cmfifo_datavalid WHEN (use_rate_match_fifo = "true") ELSE '1';
-- rx_core inputs
core_datain <= post8b10b when (use_post8b10b_feedback = "true") else ("00" & decoder_dataout) WHEN (use_8b_10b_mode = "true") ELSE decoder_tenBdata;
core_writeclk <= clk_2;
core_readclk <= rx_rd_clk;
core_decdatavalid <= decoder_decdatavalid WHEN (use_8b_10b_mode = "true") ELSE '1';
core_xgmdatain <= xgmdatain_ipd;
core_xgmctrlin <= xgmctrlin_ipd;
core_post8b10b <= post8b10b_ipd;
core_syncstatusin <= decoder_syncstatus;
core_errdetectin <= decoder_errdetect;
core_ctrldetectin <= decoder_ctrldetect;
core_disparityerrin <= decoder_disperr;
core_patterndetectin <= decoder_patterndetect;
rcvd_clk <= pllclk_ipd WHEN (use_parallel_feedback = "true") ELSE serdes_clkout ;
clk_1 <= pllclk_ipd WHEN (use_parallel_feedback = "true") ELSE masterclk_ipd WHEN (use_channel_align = "true") ELSE serdes_clkout ;
-- added gfifo
clk_2 <= coreclk_ipd WHEN (clk_out_mode_reference = "false") ELSE clk2_mux1 ;
rx_rd_clk <= coreclk_ipd WHEN (clk_out_mode_reference = "false") ELSE rx_rd_clk_mux ;
clk2mux1 : stratixgx_hssi_mux4
PORT MAP (
Y => clk2_mux1,
I0 => serdes_clkout,
I1 => masterclk_ipd,
I2 => gnd,
I3 => pllclk_ipd,
C0 => clk2mux1_c0,
C1 => clk2mux1_c1);
clk2mux1_c0 <= '1' WHEN (use_parallel_feedback = "true") OR (use_channel_align = "true") OR (use_rate_match_fifo = "true") ELSE '0' ;
clk2mux1_c1 <= '1' WHEN (use_parallel_feedback = "true") OR (use_rate_match_fifo = "true") ELSE '0' ;
rxrdclkmux1 : stratixgx_hssi_mux4
PORT MAP (
Y => rxrdclk_mux1,
I0 => serdes_clkout,
I1 => masterclk_ipd,
I2 => gnd,
I3 => pllclk_ipd,
C0 => rxrdclkmux1_c0,
C1 => rxrdclkmux1_c1);
rxrdclkmux1_c1 <= '1' WHEN (use_parallel_feedback = "true") OR (use_rate_match_fifo = "true") ELSE '0' ;
rxrdclkmux1_c0 <= '1' WHEN (use_parallel_feedback = "true") OR (use_channel_align = "true") OR (use_rate_match_fifo = "true") ELSE '0' ;
rxrdclkmux2 : stratixgx_hssi_mux4
PORT MAP (
Y => rx_rd_clk_mux,
I0 => coreclk_ipd,
I1 => gnd,
I2 => rxrdclk_mux1_by2,
I3 => rxrdclk_mux1,
C0 => rxrdclkmux2_c0,
C1 => rxrdclkmux2_c1);
rxrdclkmux2_c1 <= '1' WHEN (send_reverse_parallel_feedback = "true") ELSE '0' ;
rxrdclkmux2_c0 <= '1' WHEN ((use_double_data_mode = "false") AND (send_reverse_parallel_feedback = "true")) ELSE '0' ;
rxrdclkmux_by2 : stratixgx_hssi_divide_by_two
GENERIC MAP (
divide => use_double_data_mode)
PORT MAP (
clkin => rxrdclk_mux1,
clkout => rxrdclk_mux1_by2);
-- sub modules
s_rx_serdes : stratixgx_hssi_rx_serdes
generic map (
channel_width => deserialization_factor,
rlv_length => run_length,
run_length_enable => run_length_enable,
cruclk_period => cruclk_period,
cruclk_multiplier => cruclk_multiplier,
use_cruclk_divider => use_cruclk_divider,
use_double_data_mode => use_double_data_mode
)
port map (
datain => datain,
cruclk => cruclk,
areset => analogreset_ipd,
feedback => serialfdbk,
fbkcntl => slpbk,
ltr => locktorefclk,
ltd => locktodata,
dataout => serdes_dataout,
clkout => serdes_clkout,
rlv => serdes_rlv,
lock => serdes_lock,
freqlock => serdes_freqlock,
signaldetect => serdes_signaldetect
);
s_word_align : stratixgx_hssi_word_aligner
generic map (
channel_width => deserialization_factor,
align_pattern_length => align_pattern_length,
infiniband_invalid_code => infiniband_invalid_code,
align_pattern => align_pattern,
synchronization_mode => synchronization_mode,
use_auto_bit_slip => use_auto_bit_slip
)
port map (
datain => wa_datain,
clk => wa_clk,
softreset => reset_int,
enacdet => wa_enacdet,
bitslip => wa_bitslip,
a1a2size => wa_a1a2size,
aligneddata => wa_aligneddata,
aligneddatapre => wa_aligneddatapre,
invalidcode => wa_invalidcode,
invalidcodepre => wa_invalidcodepre,
syncstatus => wa_syncstatus,
syncstatusdeskew => wa_syncstatusdeskew,
disperr => wa_disperr,
disperrpre => wa_disperrpre,
patterndetect => wa_patterndetect,
patterndetectpre => wa_patterndetectpre
);
s_dsfifo : stratixgx_deskew_fifo
port map (
datain => dsfifo_datain,
errdetectin => dsfifo_errdetectin,
syncstatusin => dsfifo_syncstatusin,
disperrin => dsfifo_disperrin,
patterndetectin => dsfifo_patterndetectin,
writeclock => dsfifo_writeclock,
readclock => dsfifo_readclock,
adetectdeskew => dsfifo_adetectdeskew,
fiforesetrd => dsfifo_fiforesetrd,
enabledeskew => dsfifo_enabledeskew,
reset => reset_int,
dataout => dsfifo_dataout,
dataoutpre => dsfifo_dataoutpre,
errdetect => dsfifo_errdetect,
syncstatus => dsfifo_syncstatus,
disperr => dsfifo_disperr,
patterndetect => dsfifo_patterndetect,
errdetectpre => dsfifo_errdetectpre,
syncstatuspre => dsfifo_syncstatuspre,
disperrpre => dsfifo_disperrpre,
patterndetectpre => dsfifo_patterndetectpre,
rdalign => dsfifo_rdalign
);
s_cmfifo : stratixgx_comp_fifo
generic map (
use_rate_match_fifo => use_rate_match_fifo,
rate_matching_fifo_mode => rate_matching_fifo_mode,
use_channel_align => use_channel_align,
for_engineering_sample_device => for_engineering_sample_device, -- new in 3.0 SP2
channel_num => channel_num
)
port map (
datain => cmfifo_datain,
datainpre => cmfifo_datainpre,
reset => reset_int,
errdetectin => cmfifo_invalidcodein,
syncstatusin => cmfifo_syncstatusin,
disperrin => cmfifo_disperrin,
patterndetectin => cmfifo_patterndetectin,
errdetectinpre => cmfifo_invalidcodeinpre,
syncstatusinpre => cmfifo_syncstatusinpre,
disperrinpre => cmfifo_disperrinpre,
patterndetectinpre => cmfifo_patterndetectinpre,
writeclk => cmfifo_writeclk,
readclk => cmfifo_readclk,
re => cmfifo_re,
we => cmfifo_we,
fifordin => cmfifo_fifordin,
disablefifordin => cmfifo_disablefifordin,
disablefifowrin => cmfifo_disablefifowrin,
alignstatus => cmfifo_alignstatus,
dataout => cmfifo_dataout,
errdetectout => cmfifo_invalidcode,
syncstatus => cmfifo_syncstatus,
disperr => cmfifo_disperr,
patterndetect => cmfifo_patterndetect,
codevalid => cmfifo_datavalid,
fifofull => cmfifo_fifofull,
fifoalmostful => cmfifo_fifoalmostfull,
fifoempty => cmfifo_fifoempty,
fifoalmostempty => cmfifo_fifoalmostempty,
disablefifordout => cmfifo_disablefifordout,
disablefifowrout => cmfifo_disablefifowrout,
fifordout => cmfifo_fifordout
);
s_decoder : stratixgx_8b10b_decoder
port map (
clk => decoder_clk,
reset => reset_int,
errdetectin => decoder_errdetectin,
syncstatusin => decoder_syncstatusin,
disperrin => decoder_disperrin,
patterndetectin => decoder_patterndetectin,
datainvalid => decoder_indatavalid,
datain => decoder_datain,
valid => decoder_valid,
dataout => decoder_dataout,
tenBdata => decoder_tenBdata,
errdetect => decoder_errdetect,
syncstatus => decoder_syncstatus,
disperr => decoder_disperr,
patterndetect => decoder_patterndetect,
kout => decoder_ctrldetect,
rderr => decoder_rderr,
decdatavalid => decoder_decdatavalid,
xgmdatavalid => decoder_xgmdatavalid,
xgmrunningdisp => decoder_xgmrunningdisp,
xgmctrldet => decoder_xgmctrldet,
xgmdataout => decoder_xgmdataout
);
s_rx_clkout_mux : stratixgx_hssi_divide_by_two
GENERIC MAP (
divide => use_double_data_mode)
PORT MAP (
reset => reset_int,
clkin => rxrdclk_mux1,
clkout => clkoutmux_clkout_pre
);
s_rx_core : stratixgx_rx_core
generic map (
channel_width => deserialization_factor,
use_double_data_mode => use_double_data_mode,
use_channel_align => use_channel_align,
use_8b_10b_mode => use_8b_10b_mode,
align_pattern => align_pattern,
synchronization_mode => synchronization_mode
)
port map
(
reset => reset_int,
datain => core_datain,
writeclk => core_writeclk,
readclk => core_readclk,
decdatavalid => core_decdatavalid,
xgmdatain => core_xgmdatain,
xgmctrlin => core_xgmctrlin,
post8b10b => core_post8b10b,
syncstatusin => core_syncstatusin,
errdetectin => core_errdetectin,
ctrldetectin => core_ctrldetectin,
disparityerrin => core_disparityerrin,
patterndetectin => core_patterndetectin,
dataout => core_dataout,
syncstatus => core_syncstatus,
errdetect => core_errdetect,
ctrldetect => core_ctrldetect,
disparityerr => core_disparityerr,
patterndetect => core_patterndetect,
a1a2sizeout => core_a1a2sizeout,
clkout => core_clkout
);
dataout_tmp <= core_dataout;
-- output from clkout mux
-- - added gfifo
clkoutmux_clkout <= serdes_clkout WHEN ((use_parallel_feedback = "false") AND (clk_out_mode_reference = "false")) ELSE clkoutmux_clkout_pre;
clkout <= clkoutmux_clkout;
VITAL: process (pllclk_ipd, coreclk_ipd, dataout_tmp, core_syncstatus, core_patterndetect,
cmfifo_fifofull, cmfifo_fifoempty, cmfifo_fifoalmostfull, cmfifo_fifoalmostempty, re_ipd,
core_a1a2sizeout,
core_ctrldetect, core_errdetect, core_disparityerr)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(19 downto 0);
variable syncstatus_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable patterndetect_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable ctrldetect_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable errdetect_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable disperr_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable a1a2sizeout_VitalGlitchDataArray : VitalGlitchDataArrayType(1 downto 0);
variable fifofull_VitalGlitchData: VitalGlitchDataType;
variable fifoempty_VitalGlitchData: VitalGlitchDataType;
variable fifoalmostfull_VitalGlitchData: VitalGlitchDataType;
variable fifoalmostempty_VitalGlitchData: VitalGlitchDataType;
variable Tviol_re_clk : std_ulogic := '0';
variable TimingData_re_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_re_clk,
TimingData => TimingData_re_clk,
TestSignal => re_ipd,
TestSignalName => "RE",
RefSignal => coreclk_ipd,
RefSignalName => "CORECLK",
SetupHigh => tsetup_re_coreclk_noedge_posedge,
SetupLow => tsetup_re_coreclk_noedge_posedge,
HoldHigh => thold_re_coreclk_noedge_posedge,
HoldLow => thold_re_coreclk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_HSSI_RECEIVER",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => fifofull,
OutSignalName => "FIFOFULL",
OutTemp => cmfifo_fifofull,
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_fifofull_posedge, TRUE)),
GlitchData => fifofull_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => fifoempty,
OutSignalName => "FIFOEMPTY",
OutTemp => cmfifo_fifoempty,
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_fifoempty_posedge, TRUE)),
GlitchData => fifoempty_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => fifoalmostfull,
OutSignalName => "FIFOALMOSTFULL",
OutTemp => cmfifo_fifoalmostfull,
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_fifoalmostfull_posedge, TRUE)),
GlitchData => fifoalmostfull_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => fifoalmostempty,
OutSignalName => "FIFOALMOSTEMPTY",
OutTemp => cmfifo_fifoalmostempty,
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_fifoalmostempty_posedge, TRUE)),
GlitchData => fifoalmostempty_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(0),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(0), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(1),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(1), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(2),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(2),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(2), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(3),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(3),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(3), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(4),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(4),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(4), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(5),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(5),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(5), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(6),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(6),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(6), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(6),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(7),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(7),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(7), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(7),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(8),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(8),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(8), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(8),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(9),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(9),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(9), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(9),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(10),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(10),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(10), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(10),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(11),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(11),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(11), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(11),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(12),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(12),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(12), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(12),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(13),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(13),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(13), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(13),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(14),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(14),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(14), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(14),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(15),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(15),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(15), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(15),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(16),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(16),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(16), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(16),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(17),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(17),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(17), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(17),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(18),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(18),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(18), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(18),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout(19),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(19),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge(19), TRUE)),
GlitchData => dataout_VitalGlitchDataArray(19),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
-- control signals
VitalPathDelay01 (
OutSignal => syncstatus(0),
OutSignalName => "SYNCSTATUS",
OutTemp => core_syncstatus(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_syncstatus_posedge(0), TRUE)),
GlitchData => syncstatus_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => syncstatus(1),
OutSignalName => "SYNCSTATUS",
OutTemp => core_syncstatus(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_syncstatus_posedge(1), TRUE)),
GlitchData => syncstatus_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => patterndetect(0),
OutSignalName => "patterndetect(0)",
OutTemp => core_patterndetect(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_patterndetect_posedge(0), TRUE)),
GlitchData => patterndetect_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => patterndetect(1),
OutSignalName => "patterndetect(1)",
OutTemp => core_patterndetect(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_patterndetect_posedge(1), TRUE)),
GlitchData => patterndetect_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ctrldetect(0),
OutSignalName => "ctrldetect(0)",
OutTemp => core_ctrldetect(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_ctrldetect_posedge(0), TRUE)),
GlitchData => ctrldetect_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ctrldetect(1),
OutSignalName => "ctrldetect(1)",
OutTemp => core_ctrldetect(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_ctrldetect_posedge(1), TRUE)),
GlitchData => ctrldetect_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => errdetect(0),
OutSignalName => "errdetect(0)",
OutTemp => core_errdetect(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_errdetect_posedge(0), TRUE)),
GlitchData => errdetect_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => errdetect(1),
OutSignalName => "errdetect(1)",
OutTemp => core_errdetect(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_errdetect_posedge(1), TRUE)),
GlitchData => errdetect_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => disperr(0),
OutSignalName => "disperr(0)",
OutTemp => core_disparityerr(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_disperr_posedge(0), TRUE)),
GlitchData => disperr_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => disperr(1),
OutSignalName => "disperr(1)",
OutTemp => core_disparityerr(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_disperr_posedge(1), TRUE)),
GlitchData => disperr_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => a1a2sizeout(0),
OutSignalName => "a1a2sizeout(0)",
OutTemp => core_a1a2sizeout(0),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_a1a2sizeout_posedge(0), TRUE)),
GlitchData => a1a2sizeout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => a1a2sizeout(1),
OutSignalName => "a1a2sizeout(1)",
OutTemp => core_a1a2sizeout(1),
Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_a1a2sizeout_posedge(1), TRUE)),
GlitchData => a1a2sizeout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- generate output signals
-- outputs from serdes
recovclkout <= serdes_clkout;
rlv <= serdes_rlv;
lock <= serdes_lock;
freqlock <= serdes_freqlock;
signaldetect <= serdes_signaldetect;
-- outputs from word_aligner
syncstatusdeskew <= wa_syncstatusdeskew;
-- outputs from deskew FIFO
adetectdeskew <= dsfifo_adetectdeskew;
rdalign <= dsfifo_rdalign;
-- outputs from comp FIFO
-- fifofull <= cmfifo_fifofull;
-- fifoalmostfull <= cmfifo_fifoalmostfull;
-- fifoempty <= cmfifo_fifoempty;
-- fifoalmostempty <= cmfifo_fifoalmostempty;
fifordout <= cmfifo_fifordout;
disablefifordout <= cmfifo_disablefifordout;
disablefifowrout <= cmfifo_disablefifowrout;
-- outputs from decoder
xgmctrldet <= decoder_xgmctrldet;
xgmrunningdisp <= decoder_xgmrunningdisp;
xgmdatavalid <= decoder_xgmdatavalid;
xgmdataout <= decoder_xgmdataout;
end vital_receiver_atom;
--
-- STRATIXGX_HSSI_TRANSMITTER
--
library IEEE, stratixgx_gxb,std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use stratixgx_gxb.hssi_pack.all;
use std.textio.all;
entity stratixgx_hssi_transmitter is
generic (
channel_num : integer := 1;
channel_width : integer := 20;
serialization_factor: integer := 10;
use_8b_10b_mode : String := "false";
use_double_data_mode: String := "false";
use_fifo_mode : String := "false";
use_reverse_parallel_feedback : String := "false";
force_disparity_mode: String := "false";
transmit_protocol : String := "none";
use_vod_ctrl_signal : String := "false";
use_preemphasis_ctrl_signal : String := "false";
use_self_test_mode : String := "false";
self_test_mode : integer := 0;
vod_ctrl_setting : integer := 4;
preemphasis_ctrl_setting : integer := 5;
termination : integer := 0;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_datain : VitalDelayArrayType01(19 downto 0) := (OTHERS => DefPropDelay01);
tipd_pllclk : VitalDelayType01 := DefpropDelay01;
tipd_fastpllclk : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_softreset : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_forcedisparity : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain : VitalDelayArrayType01(7 downto 0) := (OTHERS => DefPropDelay01);
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_srlpbk : VitalDelayType01 := DefpropDelay01;
tipd_analogreset : VitalDelayType01 := DefpropDelay01;
tipd_vodctrl : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tipd_preemphasisctrl: VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_coreclk_noedge_posedge : VitalDelayArrayType(19 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_forcedisparity_coreclk_noedge_posedge: VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_forcedisparity_coreclk_noedge_posedge : VitalDelayArrayType(1 downto 0) := (OTHERS => DefSetupHoldCnst)
);
port (
datain : in std_logic_vector(19 downto 0);
pllclk : in std_logic := '0';
fastpllclk : in std_logic := '0';
coreclk : in std_logic := '0';
softreset : in std_logic := '0';
ctrlenable : in std_logic_vector(1 downto 0) := "00";
forcedisparity : in std_logic_vector(1 downto 0) := "00";
serialdatain : in std_logic := '0';
xgmdatain : in std_logic_vector(7 downto 0) := "00000000";
xgmctrl : in std_logic := '0';
srlpbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
analogreset : in std_logic := '0';
vodctrl : in std_logic_vector(2 downto 0) := "000";
preemphasisctrl : in std_logic_vector(2 downto 0) := "000";
dataout : out std_logic;
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic;
rdenablesync : out std_logic;
parallelfdbkdata : out std_logic_vector(9 downto 0);
pre8b10bdata : out std_logic_vector(9 downto 0)
);
end stratixgx_hssi_transmitter;
architecture vital_transmitter_atom of stratixgx_hssi_transmitter is
signal datain_ipd : std_logic_vector(19 downto 0);
signal pllclk_ipd : std_logic;
signal fastpllclk_ipd : std_logic;
signal coreclk_ipd : std_logic;
signal softreset_ipd : std_logic;
signal ctrlenable_ipd : std_logic_vector(1 downto 0);
signal forcedisparity_ipd : std_logic_vector(1 downto 0);
signal analogreset_ipd : std_logic;
signal vodctrl_ipd : std_logic_vector(2 downto 0);
signal preemphasisctrl_ipd : std_logic_vector(2 downto 0);
signal serialdatain_ipd : std_logic;
signal xgmdatain_ipd : std_logic_vector(7 downto 0);
signal xgmctrl_ipd : std_logic;
signal srlpbk_ipd : std_logic;
--constant signals
signal vcc : std_logic := '1';
signal gnd : std_logic := '0';
signal idle_bus : std_logic_vector(9 downto 0) := "0000000000";
--lower lever softreset
signal reset_int : std_logic;
-- tx_core input/output signals
signal core_datain : std_logic_vector(19 downto 0);
signal core_writeclk : std_logic;
signal core_readclk : std_logic;
signal core_ctrlena : std_logic_vector(1 downto 0);
signal core_forcedisp : std_logic_vector(1 downto 0);
signal core_dataout : std_logic_vector(9 downto 0);
signal core_forcedispout : std_logic;
signal core_ctrlenaout : std_logic;
signal core_rdenasync : std_logic;
signal core_xgmctrlena : std_logic;
signal core_xgmdataout : std_logic_vector(7 downto 0);
signal core_pre8b10bdataout : std_logic_vector(9 downto 0);
-- serdes input/output signals
signal serdes_clk : std_logic;
signal serdes_clk1 : std_logic;
signal serdes_datain : std_logic_vector(9 downto 0);
signal serdes_serialdatain : std_logic;
signal serdes_srlpbk : std_logic;
signal serdes_dataout : std_logic;
-- encoder input/output signals
signal encoder_clk : std_logic := '0';
signal encoder_kin : std_logic := '0';
signal encoder_datain : std_logic_vector(7 downto 0) := "00000000";
signal encoder_para : std_logic_vector(9 downto 0) := "0000000000";
signal encoder_xgmdatain : std_logic_vector(7 downto 0) := "00000000";
signal encoder_xgmctrl : std_logic := '0';
signal encoder_dataout : std_logic_vector(9 downto 0) := "0000000000";
signal encoder_rdout : std_logic := '0';
-- internal signal for parallelfdbkdata
signal parallelfdbkdata_tmp : std_logic_vector(9 downto 0);
signal txclk : std_logic;
signal pllclk_int : std_logic;
-- sub module component declaration
component stratixgx_tx_core
GENERIC (
use_double_data_mode : string := "false";
use_fifo_mode : string := "true";
channel_width : integer := 10;
transmit_protocol : string := "none";
KCHAR : std_logic := '0';
ECHAR : std_logic := '0');
port (
reset : IN std_logic;
datain : IN std_logic_vector(19 DOWNTO 0);
writeclk : IN std_logic;
readclk : IN std_logic;
ctrlena : IN std_logic_vector(1 DOWNTO 0);
forcedisp : IN std_logic_vector(1 DOWNTO 0);
dataout : OUT std_logic_vector(9 DOWNTO 0);
forcedispout : OUT std_logic;
ctrlenaout : OUT std_logic;
rdenasync : OUT std_logic;
xgmctrlena : OUT std_logic;
xgmdataout : OUT std_logic_vector(7 DOWNTO 0);
pre8b10bdataout : OUT std_logic_vector(9 DOWNTO 0)
);
end component;
component stratixgx_hssi_tx_serdes
generic (
channel_width : integer := 10
);
port (
clk : in std_logic := '0';
clk1 : in std_logic := '0';
datain : in std_logic_vector(9 downto 0) := "0000000000";
serialdatain : in std_logic := '0';
srlpbk : in std_logic := '0';
areset : in std_logic := '0';
dataout : out std_logic
);
end component;
component stratixgx_8b10b_encoder
GENERIC (
transmit_protocol : string := "none";
use_8b_10b_mode : string := "true";
force_disparity_mode : string := "false");
PORT (
clk : IN std_logic;
reset : IN std_logic;
xgmctrl : IN std_logic;
kin : IN std_logic;
xgmdatain : IN std_logic_vector(7 DOWNTO 0);
datain : IN std_logic_vector(7 DOWNTO 0);
forcedisparity : IN std_logic;
dataout : OUT std_logic_vector(9 DOWNTO 0);
parafbkdataout : OUT std_logic_vector(9 DOWNTO 0));
END component;
component stratixgx_hssi_divide_by_two
GENERIC (
divide : string := "true");
PORT (
reset : IN std_logic := '0';
clkin : IN std_logic;
clkout : OUT std_logic);
END component;
-- end of sub module component declaration
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd(0), datain(0), tipd_datain(0));
VitalWireDelay (datain_ipd(1), datain(1), tipd_datain(1));
VitalWireDelay (datain_ipd(2), datain(2), tipd_datain(2));
VitalWireDelay (datain_ipd(3), datain(3), tipd_datain(3));
VitalWireDelay (datain_ipd(4), datain(4), tipd_datain(4));
VitalWireDelay (datain_ipd(5), datain(5), tipd_datain(5));
VitalWireDelay (datain_ipd(6), datain(6), tipd_datain(6));
VitalWireDelay (datain_ipd(7), datain(7), tipd_datain(7));
VitalWireDelay (datain_ipd(8), datain(8), tipd_datain(8));
VitalWireDelay (datain_ipd(9), datain(9), tipd_datain(9));
VitalWireDelay (datain_ipd(10), datain(10), tipd_datain(10));
VitalWireDelay (datain_ipd(11), datain(11), tipd_datain(11));
VitalWireDelay (datain_ipd(12), datain(12), tipd_datain(12));
VitalWireDelay (datain_ipd(13), datain(13), tipd_datain(13));
VitalWireDelay (datain_ipd(14), datain(14), tipd_datain(14));
VitalWireDelay (datain_ipd(15), datain(15), tipd_datain(15));
VitalWireDelay (datain_ipd(16), datain(16), tipd_datain(16));
VitalWireDelay (datain_ipd(17), datain(17), tipd_datain(17));
VitalWireDelay (datain_ipd(18), datain(18), tipd_datain(18));
VitalWireDelay (datain_ipd(19), datain(19), tipd_datain(19));
VitalWireDelay (pllclk_ipd, pllclk, tipd_pllclk);
VitalWireDelay (fastpllclk_ipd, fastpllclk, tipd_fastpllclk);
VitalWireDelay (coreclk_ipd, coreclk, tipd_coreclk);
VitalWireDelay (softreset_ipd, softreset, tipd_softreset);
VitalWireDelay (ctrlenable_ipd(0), ctrlenable(0), tipd_ctrlenable(0));
VitalWireDelay (ctrlenable_ipd(1), ctrlenable(1), tipd_ctrlenable(1));
VitalWireDelay (forcedisparity_ipd(0), forcedisparity(0), tipd_forcedisparity(0));
VitalWireDelay (forcedisparity_ipd(1), forcedisparity(1), tipd_forcedisparity(1));
VitalWireDelay (analogreset_ipd, analogreset, tipd_analogreset);
VitalWireDelay (vodctrl_ipd(0), vodctrl(0), tipd_vodctrl(0));
VitalWireDelay (vodctrl_ipd(1), vodctrl(1), tipd_vodctrl(1));
VitalWireDelay (vodctrl_ipd(2), vodctrl(2), tipd_vodctrl(2));
VitalWireDelay (preemphasisctrl_ipd(0), preemphasisctrl(0), tipd_preemphasisctrl(0));
VitalWireDelay (preemphasisctrl_ipd(1), preemphasisctrl(1), tipd_preemphasisctrl(1));
VitalWireDelay (preemphasisctrl_ipd(2), preemphasisctrl(2), tipd_preemphasisctrl(2));
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (xgmdatain_ipd(0), xgmdatain(0), tipd_xgmdatain(0));
VitalWireDelay (xgmdatain_ipd(1), xgmdatain(1), tipd_xgmdatain(1));
VitalWireDelay (xgmctrl_ipd, xgmctrl, tipd_xgmctrl);
VitalWireDelay (srlpbk_ipd, srlpbk, tipd_srlpbk);
end block;
-- generate internal inut signals
txclk_block : stratixgx_hssi_divide_by_two
GENERIC MAP (
divide => use_double_data_mode)
PORT MAP (
clkin => pllclk_ipd,
clkout => pllclk_int);
txclk <= pllclk_int when use_reverse_parallel_feedback = "true" else coreclk_ipd;
reset_int <= softreset_ipd;
-- core_interface inputs
core_datain <= datain_ipd;
core_writeclk <= txclk;
core_readclk <= pllclk_ipd;
core_ctrlena <= ctrlenable_ipd;
core_forcedisp <= forcedisparity_ipd;
-- encoder inputs
encoder_clk <= pllclk_ipd;
encoder_kin <= core_ctrlenaout;
encoder_datain <= core_dataout(7 downto 0);
encoder_xgmdatain <= xgmdatain(7 downto 0);
encoder_xgmctrl <= xgmctrl_ipd;
-- serdes inputs
serdes_clk <= fastpllclk_ipd;
serdes_clk1 <= pllclk_ipd;
serdes_datain <= encoder_dataout WHEN (use_8b_10b_mode = "true") ELSE core_dataout;
serdes_serialdatain <= serialdatain_ipd;
serdes_srlpbk <= srlpbk_ipd;
-- sub modules
s_tx_core : stratixgx_tx_core
generic map (
use_double_data_mode => use_double_data_mode,
use_fifo_mode => use_fifo_mode,
channel_width => channel_width,
transmit_protocol => transmit_protocol)
port map (
reset => reset_int,
datain => core_datain,
writeclk => core_writeclk,
readclk => core_readclk,
ctrlena => core_ctrlena,
forcedisp => core_forcedisp,
dataout => core_dataout,
forcedispout => core_forcedispout,
ctrlenaout => core_ctrlenaout,
rdenasync => core_rdenasync,
xgmctrlena => core_xgmctrlena,
xgmdataout => core_xgmdataout,
pre8b10bdataout => core_pre8b10bdataout
);
s_encoder : stratixgx_8b10b_encoder
generic map (
transmit_protocol => transmit_protocol,
use_8b_10b_mode => use_8b_10b_mode,
force_disparity_mode => force_disparity_mode
)
port map (
clk => encoder_clk,
reset => reset_int,
kin => encoder_kin,
datain => encoder_datain,
xgmdatain => encoder_xgmdatain,
xgmctrl => encoder_xgmctrl,
forcedisparity => core_forcedispout,
dataout => encoder_dataout,
parafbkdataout => encoder_para
);
s_tx_serdes : stratixgx_hssi_tx_serdes
generic map (
channel_width => serialization_factor
)
port map (
clk => serdes_clk,
clk1 => serdes_clk1,
datain => serdes_datain,
serialdatain => serdes_serialdatain,
srlpbk => serdes_srlpbk,
areset => analogreset_ipd,
dataout => serdes_dataout
);
-- end of sub modules
-- generate output signals
parallelfdbkdata_tmp <= encoder_dataout WHEN (use_8b_10b_mode = "true") ELSE core_dataout;
dataout <= serdes_dataout;
xgmctrlenable <= core_xgmctrlena;
rdenablesync <= core_rdenasync;
xgmdataout <= core_xgmdataout;
pre8b10bdata <= core_pre8b10bdataout;
parallelfdbkdata <= parallelfdbkdata_tmp;
VITAL: process (pllclk_ipd, fastpllclk_ipd, coreclk_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ctrlenable_clk : std_ulogic := '0';
variable TimingData_ctrlenable_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_forcedisparity_clk : std_ulogic := '0';
variable TimingData_forcedisparity_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(19 downto 0);
variable clkout_VitalGlitchData: VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => coreclk_ipd,
RefSignalName => "CORECLK",
SetupHigh => tsetup_datain_coreclk_noedge_posedge(0),
SetupLow => tsetup_datain_coreclk_noedge_posedge(0),
HoldHigh => thold_datain_coreclk_noedge_posedge(0),
HoldLow => thold_datain_coreclk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_HSSI_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ctrlenable_clk,
TimingData => TimingData_ctrlenable_clk,
TestSignal => ctrlenable_ipd,
TestSignalName => "CTRLENABLE",
RefSignal => coreclk_ipd,
RefSignalName => "CORECLK",
SetupHigh => tsetup_ctrlenable_coreclk_noedge_posedge(0),
SetupLow => tsetup_ctrlenable_coreclk_noedge_posedge(0),
HoldHigh => thold_ctrlenable_coreclk_noedge_posedge(0),
HoldLow => thold_ctrlenable_coreclk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_HSSI_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_forcedisparity_clk,
TimingData => TimingData_forcedisparity_clk,
TestSignal => forcedisparity_ipd,
TestSignalName => "FORCEDISPARITY",
RefSignal => coreclk_ipd,
RefSignalName => "CORECLK",
SetupHigh => tsetup_forcedisparity_coreclk_noedge_posedge(0),
SetupLow => tsetup_forcedisparity_coreclk_noedge_posedge(0),
HoldHigh => thold_forcedisparity_coreclk_noedge_posedge(0),
HoldLow => thold_forcedisparity_coreclk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_HSSI_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
end process;
end vital_transmitter_atom;
| gpl-3.0 | d4b45b9e794a3d8e92117ec033772a85 | 0.638481 | 2.488367 | false | false | false | false |
EPiCS/reconos | demos/reconf_sort_matrix/hw/hwt_sort_demo_v1_00_c/hdl/vhdl/hwt_sort_demo.vhd | 2 | 7,858 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_sort_demo is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end entity hwt_sort_demo;
architecture implementation of hwt_sort_demo is
-- just for simpler use
signal clk : std_logic;
signal rst : std_logic;
type STATE_TYPE is (
STATE_GET_ADDR,STATE_READ,STATE_SORTING,
STATE_WRITE,STATE_ACK,STATE_THREAD_EXIT);
component bubble_sorter is
generic (
G_LEN : integer := 512; -- number of words to sort
G_AWIDTH : integer := 9; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- The sorting application reads 'C_LOCAL_RAM_SIZE' 32-bit words into the local RAM,
-- from a given address (send in a message box), sorts them and writes them back into main memory.
-- IMPORTANT: define size of local RAM here!!!!
constant C_LOCAL_RAM_SIZE : integer := 2048;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal addr : std_logic_vector(31 downto 0);
signal len : std_logic_vector(23 downto 0);
signal state : STATE_TYPE;
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
signal o_RAMAddr_sorter : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_sorter : std_logic_vector(0 to 31);
signal o_RAMWE_sorter : std_logic;
signal i_RAMData_sorter : std_logic_vector(0 to 31);
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal ignore : std_logic_vector(31 downto 0);
signal sort_start : std_logic := '0';
signal sort_done : std_logic := '0';
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local dual-port RAM
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(conv_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(conv_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sorter = '1') then
local_ram(conv_integer(unsigned(o_RAMAddr_sorter))) := o_RAMData_sorter;
else
i_RAMData_sorter <= local_ram(conv_integer(unsigned(o_RAMAddr_sorter)));
end if;
end if;
end process;
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => C_LOCAL_RAM_SIZE,
G_AWIDTH => C_LOCAL_RAM_ADDRESS_WIDTH,
G_DWIDTH => 32
)
port map (
clk => clk,
reset => rst,
o_RAMAddr => o_RAMAddr_sorter,
o_RAMData => o_RAMData_sorter,
i_RAMData => i_RAMData_sorter,
o_RAMWE => o_RAMWE_sorter,
start => sort_start,
done => sort_done
);
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- os and memory synchronisation state machine
reconos_fsm: process (clk,rst,o_osif,o_memif,o_ram) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_GET_ADDR;
done := False;
addr <= (others => '0');
len <= (others => '0');
sort_start <= '0';
elsif rising_edge(clk) then
case state is
-- get address via mbox: the data will be copied from this address to the local ram in the next states
when STATE_GET_ADDR =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, addr, done);
if done then
if (addr = X"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
len <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES,24);
addr <= addr(31 downto 2) & "00";
state <= STATE_READ;
end if;
end if;
-- copy data from main memory to local memory
when STATE_READ =>
memif_read(i_ram,o_ram,i_memif,o_memif,addr,X"00000000",len,done);
if done then
sort_start <= '1';
state <= STATE_SORTING;
end if;
-- sort the words in local RAM
when STATE_SORTING =>
sort_start <= '0';
--o_ram.addr <= (others => '0');
if sort_done = '1' then
len <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES,24);
--state <= STATE_WRITE_REQ;
state <= STATE_WRITE;
end if;
-- copy data from local memory to main memory
when STATE_WRITE =>
memif_write(i_ram,o_ram,i_memif,o_memif,X"00000000",addr,len,done);
if done then
state <= STATE_ACK;
end if;
-- send mbox that signals that the sorting is finished
when STATE_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, addr, ignore, done);
if done then state <= STATE_GET_ADDR; end if;
-- thread exit
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end architecture;
| gpl-2.0 | 5f00dedba69897e4b079f04c08b5a586 | 0.63973 | 2.765927 | false | false | false | false |
EPiCS/reconos | pcores/reconos_osif_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 7,380 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A AXI slave which maps the FIFOs of the HWTs to
-- registers accessible from the AXI-Bus.
-- Reg0: Read data
-- Reg1: Write data
-- Reg2: Fill - number of elements in receive-FIFO
-- Reg3: Rem - free space in send-FIFO
--
-- REMARK: The FIFOs must have the same clock than the
-- AXI-Bus.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
C_NUM_FIFOS : integer := 1;
C_FIFO_WIDTH : integer := 32;
-- Bus protocol parameters
C_SLV_DWIDTH : integer := 32
);
port (
-- FIFO ports
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i# : in std_logic_vector(31 downto 0);
FIFO_S_Fill_#i# : in std_logic_vector(15 downto 0);
FIFO_S_Empty_#i# : in std_logic;
FIFO_S_RE_#i# : out std_logic;
FIFO_M_Data_#i# : out std_logic_vector(31 downto 0);
FIFO_M_Rem_#i# : in std_logic_vector(15 downto 0);
FIFO_M_Full_#i# : in std_logic;
FIFO_M_WE_#i# : out std_logic;
-- ## END GENERATE LOOP ##
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_Addr : in std_logic_vector(31 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_CS : in std_logic_vector(0 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
end entity user_logic;
architecture implementation of user_logic is
-- Signals for user logic slave model s/w accessible register
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_bus2ip_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_addr : std_logic_vector(31 downto 0);
signal slv_rnw : std_logic;
signal slv_cs : std_logic;
type fifo_bi_t is record
s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
s_fill : std_logic_vector(15 downto 0);
s_empty : std_logic;
s_re : std_logic;
m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
m_rem : std_logic_vector(15 downto 0);
m_full : std_logic;
m_we : std_logic;
end record;
signal s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : std_logic_vector(15 downto 0);
signal s_empty : std_logic;
signal s_re : std_logic;
signal m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_rem : std_logic_vector(15 downto 0);
signal m_full : std_logic;
signal m_we : std_logic;
-- Array which contains all connected FIFOs
type fifos_t is array(0 to C_NUM_FIFOS - 1) of fifo_bi_t;
signal fifos : fifos_t;
signal fifo_bi_select : integer range 0 to C_NUM_FIFOS - 1;
signal reg_select : integer range 0 to 3;
signal pad_31 : std_logic_vector(14 downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= Bus2Ip_Clk;
rst <= not Bus2IP_Resetn;
pad_31 <= (others => '0');
IP2Bus_Data <= slv_ip2bus_data;
slv_bus2ip_data <= Bus2IP_Data;
slv_addr <= Bus2IP_Addr;
slv_rnw <= Bus2IP_RNW;
slv_cs <= Bus2IP_CS(0);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
fifo_bi_select <= CONV_INTEGER(slv_addr(19 downto 4));
reg_select <= CONV_INTEGER(slv_addr(3 downto 2));
mux_proc : process(fifos,fifo_bi_select,pad_31,
-- ## BEGIN GENERATE LOOP ##
FIFO_S_Data_#i#,FIFO_S_Fill_#i#,FIFO_S_Empty_#i#,
FIFO_M_Rem_#i#,FIFO_M_Full_#i#,
-- ## END GENERATE LOOP ##
s_re,m_data,m_we) is
begin
-- Assign FIFOs to array
-- ## BEGIN GENERATE LOOP ##
fifos(#i#).s_data <= FIFO_S_Data_#i#;
fifos(#i#).s_fill <= FIFO_S_Fill_#i#;
fifos(#i#).s_empty <= FIFO_S_Empty_#i#;
FIFO_S_RE_#i# <= fifos(#i#).s_re;
FIFO_M_Data_#i# <= fifos(#i#).m_data;
fifos(#i#).m_rem <= FIFO_M_Rem_#i#;
fifos(#i#).m_full <= FIFO_M_Full_#i#;
FIFO_M_WE_#i# <= fifos(#i#).m_we;
-- ## END GENERATE LOOP ##
-- default values for not connected ports
-- later assignments will override this defaults
for i in 0 to C_NUM_FIFOS - 1 loop
fifos(i).s_re <= '0';
fifos(i).m_we <= '0';
fifos(i).m_data <= (others => '0');
end loop;
s_data <= fifos(fifo_bi_select).s_data;
s_fill <= fifos(fifo_bi_select).s_fill;
s_empty <= fifos(fifo_bi_select).s_empty;
fifos(fifo_bi_select).s_re <= s_re;
fifos(fifo_bi_select).m_data <= m_data;
m_rem <= fifos(fifo_bi_select).m_rem;
m_full <= fifos(fifo_bi_select).m_full;
fifos(fifo_bi_select).m_we <= m_we;
end process;
slv_read_ack <= '1' when slv_cs = '1' and slv_rnw = '1' else '0';
slv_write_ack <= '1' when slv_cs = '1' and slv_rnw = '0' else '0';
-- REMARK: This is not totally right. Normally we need to
-- set the RE of the FIFO and read the next cycle.
-- Since we do not read data in the next cycle this
-- is totally fine.
s_re <= '1' when slv_cs = '1' and (reg_select = 0 and slv_rnw = '1') else '0';
m_we <= '1' when slv_cs = '1' and (reg_select = 1 and slv_rnw = '0') else '0';
bus_reg_read_proc : process(reg_select,s_data,
s_empty,s_fill,
m_full,m_rem) is
begin
case reg_select is
when 0 => slv_ip2bus_data <= s_data;
when 1 => slv_ip2bus_data <= (others => '0');
when 2 => slv_ip2bus_data <= s_empty & pad_31 & s_fill;
when 3 => slv_ip2bus_data <= m_full & pad_31 & m_rem;
end case;
end process bus_reg_read_proc;
bus_reg_write_proc : process(reg_select,slv_bus2ip_data) is
begin
case reg_select is
when 1 => m_data <= slv_bus2ip_data;
when others => m_data <= (others => '0');
end case;
end process bus_reg_write_proc;
end implementation;
| gpl-2.0 | 9d441b4dc3e42c7632c55c6d545f454d | 0.544925 | 2.939841 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t420_notri.vhd | 1 | 8,779 | -------------------------------------------------------------------------------
--
-- T420/421 controller toplevel without tri-states.
--
-- $Id: t420_notri.vhd,v 1.4 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t420_notri is
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t420_notri;
use work.t400_core_comp_pack.t400_core;
use work.t400_tech_comp_pack.t400_por;
use work.t400_tech_comp_pack.generic_ram_ena;
architecture struct of t420_notri is
component t420_rom
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(9 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end component;
signal por_n_s : std_logic;
signal pm_addr_s : std_logic_vector(9 downto 0);
signal pm_data_s : std_logic_vector(7 downto 0);
signal dm_addr_s : std_logic_vector(5 downto 0);
signal dm_we_s : std_logic;
signal dm_data_to_core_s,
dm_data_from_core_s : std_logic_vector(3 downto 0);
begin
-----------------------------------------------------------------------------
-- T400 core
-----------------------------------------------------------------------------
core_b : t400_core
generic map (
opt_type_g => opt_type_g,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => opt_microbus_g,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
por_n_i => por_n_s,
reset_n_i => reset_n_i,
cko_i => cko_i,
pm_addr_o => pm_addr_s,
pm_data_i => pm_data_s,
dm_addr_o => dm_addr_s,
dm_we_o => dm_we_s,
dm_data_o => dm_data_from_core_s,
dm_data_i => dm_data_to_core_s,
io_l_i => io_l_i,
io_l_o => io_l_o,
io_l_en_o => io_l_en_o,
io_d_o => io_d_o,
io_d_en_o => io_d_en_o,
io_g_i => io_g_i,
io_g_o => io_g_o,
io_g_en_o => io_g_en_o,
io_in_i => io_in_i,
si_i => si_i,
so_o => so_o,
so_en_o => so_en_o,
sk_o => sk_o,
sk_en_o => sk_en_o
);
-----------------------------------------------------------------------------
-- Program memory
-----------------------------------------------------------------------------
pmem_b : t420_rom
port map (
ck_i => ck_i,
addr_i => pm_addr_s,
data_o => pm_data_s
);
-----------------------------------------------------------------------------
-- Data memory
-----------------------------------------------------------------------------
dmem_b : generic_ram_ena
generic map (
addr_width_g => 6,
data_width_g => 4
)
port map (
clk_i => ck_i,
a_i => dm_addr_s,
we_i => dm_we_s,
ena_i => ck_en_i,
d_i => dm_data_from_core_s,
d_o => dm_data_to_core_s
);
-----------------------------------------------------------------------------
-- Power-on reset circuit
-----------------------------------------------------------------------------
por_b : t400_por
generic map (
delay_g => 4,
cnt_width_g => 2
)
port map (
clk_i => ck_i,
por_n_o => por_n_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2006/06/11 13:48:43 arniml
-- hand generic opt_type_g down to t400_core
--
-- Revision 1.2 2006/06/05 20:03:52 arniml
-- connect microbus generic and include generic_ram_ena
--
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 39665c5bb686ca2081cf488b0257fd28 | 0.527281 | 3.004449 | false | false | false | false |
alvieboy/xtc-base | opdec.vhd | 1 | 14,595 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity opdec is
port (
opcode_high: in std_logic_vector(15 downto 0);
opcode_low: in std_logic_vector(15 downto 0);
priv: in std_logic;
dec: out opdec_type
);
end entity opdec;
architecture behave of opdec is
-- signal decoded_op: decoded_opcode_type;
-- signal mtype: memory_access_type;
--signal opcode: std_logic_vector(15 downto 0);
--signal is_extended_opcode: boolean;
function loadimm2str(i: in loadimmtype) return string is
variable r: string(1 to 2);
begin
case i is
when LOADNONE => r:= "N ";
when LOAD8 => r:= "8 ";
when LOAD16 => r:= "16";
when LOAD24 => r:= "24";
when LOAD0 => r:= "0 ";
when others => r:= "??";
end case;
return r;
end function;
begin
-- Insn opcode depends on whether we have an extention opcode or
-- not.
process(opcode_low, opcode_high)
-- synthesis translate_off
variable targetstr: string(1 to 2);
variable sourcestr: string(1 to 5);
variable opstr: string(1 to 7);
variable rnum: string(1 to 1);
-- synthesis translate_on
variable d: opdec_type;
variable subloadimm: loadimmtype;
--variable subloadimm2: loadimmtype;
variable op: decoded_opcode_type;
variable force_flags: boolean;
variable mtype: memory_access_type;
variable opcode: std_logic_vector(15 downto 0);
variable is_extended_opcode: boolean;
variable supervisor: std_logic;
begin
if opcode_high(15)='1' then
is_extended_opcode := true;
else
is_extended_opcode := false;
end if;
opcode := opcode_high;
supervisor := priv;
-- Decode memory access type, if applicable
case opcode(10 downto 8) is
when "000" => mtype := M_WORD;
when "001" => mtype := M_HWORD;
when "010" => mtype := M_BYTE;
when "011" => mtype := M_SPR;
when "100" => mtype := M_WORD_POSTINC;
when "101" => mtype := M_HWORD_POSTINC;
when "110" => mtype := M_BYTE_POSTINC;
when "111" => mtype := M_SPR_POSTINC;
when others =>
end case;
case opcode(14 downto 12) is
when "000" => -- ALU
op := O_ALU;
when "001" =>
-- Memory instructions.
case opcode(11) is
when '0' => op := O_ST;
when '1' => op := O_LD;
when others =>
end case;
when "010" =>
-- Cop instructions
case opcode(11) is
when '0' =>
case opcode(10) is
when '0' => op := O_COPR;
when '1' => op := O_COPW;
when others =>
end case;
when '1' =>
op := O_SWI;
when others =>
end case;
when "011" =>
-- Single R/NoR.
case opcode(11) is
when '0' =>
-- Single R
case opcode(10) is
when '0' => op := O_JMP;
when '1' => op := O_JMPE;
when others =>
end case;
when '1' =>
-- No/R
case opcode(10) is
when '0' =>
case opcode(9 downto 8) is
when "00" => op := O_SEXTB; -- 38
when "10" => op := O_SEXTS; -- 3a
when others => op := O_ABORT;
end case;
when '1' =>
case opcode(9 downto 8) is
when "00" => op := O_RSPR; -- 38
when "10" => op := O_WSPR; -- 3a
when "01" => op := O_RDUSR;
when "11" => op := O_WRUSR;
when others =>
end case;
when others =>
end case;
--op := O_ABORT;
when others =>
op := O_ABORT;
end case;
when "100" =>
op := O_BR;
when "101" =>
op := O_ADDI;
when "110" =>
op := O_CMPI;
when "111" =>
op := O_LIMR;
when others =>
end case;
-- Special case op.
if is_extended_opcode then
if opcode_low(14 downto 13)="11" then
op := O_IM;
end if;
end if;
--decoded_op := op;
d.opcode := opcode;
d.sreg1 := supervisor & opcode(3 downto 0);
d.sreg2 := supervisor & opcode(7 downto 4);
d.sr := opcode(6 downto 4);
d.dreg := d.sreg1;
d.memory_access := '0';
d.memory_write := 'X';
d.alu_source := alu_source_reg;
d.rd1 := '0';
d.rd2 := '0';
d.except_return := false;
subloadimm := LOADNONE;
force_flags:=false;
-- Default values
d.modify_gpr := false;
d.op := op;
d.macc := mtype;
d.reg_source := reg_source_alu;
d.modify_flags:= false;
d.loadimm := LOADNONE;
d.is_jump := false;
d.jump := (others => 'X');
d.modify_spr := false;
d.blocks := '0';
d.condition := CONDITION_UNCONDITIONAL;
d.imflag := '0';
d.enable_alu := '0';
d.use_carry := '0';
d.cop_en := '0';
d.cop_wr := 'X';
d.cop_id := opcode(9 downto 8);
d.cop_reg := opcode(7 downto 4);
d.priv := '0';
d.ismult := '0';
-- ALU operations are directly extracted from
-- the opcode.
case opcode(11 downto 8) is
when "0000" =>
d.alu_op := ALU_ADD;
when "0001" =>
d.alu_op := ALU_ADDC;
when "0010" =>
d.alu_op := ALU_SUB;
when "0011" =>
d.alu_op := ALU_SUBB;
when "0100" =>
d.alu_op := ALU_AND;
when "0101" =>
d.alu_op := ALU_OR;
when "0110" =>
d.alu_op := ALU_XOR;
when "0111" =>
d.alu_op := ALU_CMP;
when "1000" =>
d.alu_op := ALU_SHL;
when "1001" =>
d.alu_op := ALU_SRL;
when "1010" =>
d.alu_op := ALU_SRA;
when "1011" =>
d.alu_op := ALU_MUL;
when "1100" =>
d.alu_op := ALU_ADDRI;
when "1101" =>
d.alu_op := ALU_NOT;
when "1110" =>
d.alu_op := ALU_ADD;--ALU_SEXTB;
force_flags:= true;
when "1111" =>
d.alu_op := ALU_SUB;--ALU_SEXTS;
force_flags:=true;
when others => null;
end case;
case op is
when O_IM =>
subloadimm := LOAD24;
when O_NOP =>
when O_LIMR =>
subloadimm := LOAD8;
-- Load IMMediate into register target
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source := reg_source_alu;
d.alu_source := alu_source_immed;
d.sreg1 := (others => '0');
d.alu_op := ALU_ADD;
--if opcode(3 downto 0)="000" then
-- Target is IMMed.
-- TODO
-- d.imflag := '1';
--end if;
when O_ALU =>
d.modify_gpr:=true;
if d.alu_op=ALU_CMP then
d.modify_flags := true;
d.modify_gpr := false;
d.alu_op := ALU_SUB;
end if;
if force_flags then
d.modify_flags := true;
end if;
if d.alu_op=ALU_ADDRI then
d.alu_source := alu_source_immed;
d.sreg1 := supervisor & opcode(7 downto 4);
--d.sreg2 := opcode(3 downto 0);
d.alu_op := ALU_ADD;
end if;
d.use_carry := '0';
if d.alu_op=ALU_ADDC then
d.use_carry := '1';
d.alu_op := ALU_ADD;
end if;
if d.alu_op=ALU_SUBB then
d.use_carry := '1';
d.alu_op := ALU_SUB;
end if;
if d.alu_op=ALU_MUL then
d.ismult := '1';
end if;
d.rd1:='1'; d.rd2:='1';
d.reg_source:=reg_source_alu;
d.enable_alu := '1';
when O_ADDI =>
subloadimm := LOAD8;
d.alu_source := alu_source_immed;
d.alu_op := ALU_ADD;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.enable_alu := '1';
when O_ADDRI =>
--subloadimm := LOAD0;
-- Swap register...
--d.sreg1 := opcode(7 downto 4);
d.alu_op := ALU_ADD;
d.alu_source := alu_source_immed;
d.rd1:='1'; d.rd2:='1'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.enable_alu := '1';
when O_RDUSR =>
d.alu_op := ALU_ADD;
d.alu_source := alu_source_immed;
d.rd1:='1'; d.rd2:='1'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.sreg1(4) := '0'; -- Read user.
--d.dreg(4) := '1'; -- Force into supervisor
d.priv:='1'; -- Privileged instruction
d.enable_alu := '1';
when O_WRUSR =>
d.alu_op := ALU_ADD;
d.alu_source := alu_source_immed;
d.rd1:='1'; d.rd2:='1'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.dreg(4) := '0'; -- Write user.
d.priv:='1'; -- Privileged instruction
d.enable_alu := '1';
when O_CMPI =>
subloadimm := LOAD8;
d.modify_flags := true;
d.alu_source := alu_source_immed;
d.alu_op := ALU_SUB;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=false; d.reg_source:=reg_source_alu;
d.enable_alu := '1';
--d.alu2_imreg:='1';
--d.alu2_op := ALU2_CMPI;
--d.uses := uses_alu2;
--d.blocking := true;
when O_BR =>
subloadimm := LOAD8;
d.rd1:='0'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_pcnext;
d.is_jump := true;
d.jump := JUMP_I_PCREL;
when O_JMP =>
-- Swap register...
d.sreg1 := supervisor & opcode(7 downto 4);
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_pcnext;
d.is_jump := true;
d.jump := JUMP_RI_ABS;
when O_JMPE =>
-- Swap register...
d.sreg1 := supervisor & opcode(7 downto 4);
d.rd1:='0'; d.rd2:='0'; d.modify_gpr:=false;
d.is_jump := true;
d.jump := JUMP_RI_ABS;
d.except_return:=true;
when O_COPR =>
d.cop_en := '1';
d.cop_wr := '0';
d.priv := '1';
d.rd1:='0'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_cop;
when O_COPW =>
d.cop_en := '1';
d.priv := '1';
d.cop_wr := '1';
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_cop;
when O_ST =>
d.memory_access := '1';
d.memory_write := '1';
d.rd1:='1'; d.rd2:='1';
d.loadimm := LOAD0;
when O_LD =>
-- Swap register
--d.sreg1 := opcode(7 downto 4);
d.memory_access := '1';
d.memory_write := '0';
d.rd1:='1'; d.rd2:='1';
d.blocks := '1';
when O_SEXTB =>
d.alu_source := alu_source_reg;
d.alu_op := ALU_SEXTB;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.enable_alu := '1';
d.sreg1 := supervisor & opcode(7 downto 4);
when O_SEXTS =>
d.alu_source := alu_source_reg;
d.alu_op := ALU_SEXTS;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_alu;
d.enable_alu := '1';
d.sreg1 := supervisor & opcode(7 downto 4);
when O_RSPR =>
--d.alu_source := alu_source_;
--d.alu_op := ALU_SEXTB;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=true; d.reg_source:=reg_source_spr;
d.enable_alu := '1';
d.priv := '1';
when O_WSPR =>
--d.alu_source := alu_source_;
--d.alu_op := ALU_SEXTB;
d.modify_spr:=true;
d.rd1:='1'; d.rd2:='0'; d.modify_gpr:=false;
d.enable_alu := '1';
d.priv := '1';
when O_SWI =>
when others =>
end case;
--- HAAAAACK
-- if opcode=x"0000" then
-- op:= O_SWI;
-- end if;
-- This is current version, and works.
d.imm8l(7 downto 0) := opcode(11 downto 4);
d.imm8h(7 downto 0) := opcode_low(7 downto 0);
d.imm24 := opcode_low(12) & opcode_low(7 downto 0) & opcode_high(14 downto 0);
-- This is more optimized. Requires lots of compiler changes.
--d.imm8l(7 downto 0) := opcode_high(11 downto 4);
--d.imm8h(7 downto 0) := opcode_low(7 downto 0);
--d.imm24 := opcode_low(12) & opcode_high(14 downto 12) & opcode_high(3 downto 0) &
-- opcode_low(7 downto 0) & opcode_high(11 downto 4);
if is_extended_opcode then
case subloadimm is
when LOAD8 =>
case opcode_low(14 downto 13) is
when "10" =>
d.loadimm := LOAD16;
when others =>
d.loadimm := LOAD8;
end case;
when LOAD24 =>
d.loadimm := LOAD24;
d.imflag := '1';
when others =>
case opcode_low(14 downto 13) is
when "10" =>
-- 8L is from upper word.
d.imm8l := d.imm8h;
d.loadimm := LOAD8;
when others =>
d.loadimm := LOADNONE;
end case;
end case;
else
d.loadimm := subloadimm;
end if;
d.extended := is_extended_opcode;
-- Condition codes.
if (is_extended_opcode) then
case opcode_low(11 downto 8) is
when "0000" => d.condition := CONDITION_UNCONDITIONAL;
when "0001" => d.condition := CONDITION_NE;
when "0010" => d.condition := CONDITION_E;
when "0011" => d.condition := CONDITION_G;
when "0100" => d.condition := CONDITION_GE;
when "0101" => d.condition := CONDITION_L;
when "0110" => d.condition := CONDITION_LE;
when "0111" => d.condition := CONDITION_UG;
when "1000" => d.condition := CONDITION_UGE;
when "1001" => d.condition := CONDITION_UL;
when "1010" => d.condition := CONDITION_ULE;
when "1011" => d.condition := CONDITION_S;
when "1100" => d.condition := CONDITION_NS;
when others => d.condition := CONDITION_UNCONDITIONAL;
end case;
-- Check DREG
if opcode_low(14 downto 12)="010" then
-- DREG extended....
d.dreg := supervisor & opcode_low(3 downto 0);
end if;
if op=O_ALU and opcode_low(14 downto 12)="100" then
d.alu_source := alu_source_immed;
d.sreg1 := supervisor & opcode(7 downto 4);
end if;
end if;
d.targetzero:='0';
if d.dreg(3 downto 0)="0000" then
d.targetzero:='1';
end if;
dec <= d;
end process;
end behave;
| bsd-3-clause | 7da2c0680fb951034df9c7381d22c8a1 | 0.487427 | 3.233991 | false | false | false | false |
Shadytel/Computer | Emulator/FPGA/Seg7Driver.vhd | 1 | 2,876 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:10:20 09/24/2011
-- Design Name:
-- Module Name: Seg7Driver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Seg7Driver is
Port(
clk: in std_logic;
data: in std_logic_vector(11 downto 0);
nibble: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0); -- segment outputs
an : out std_logic_vector(3 downto 0) -- anode select signals
);
end Seg7Driver;
architecture Behavioral of Seg7Driver is
signal HEX : std_logic_vector(4 downto 0); -- a digit for 7 seg display
signal cnt : std_logic_vector(10 downto 0):="00000000000";-- divider for 7SD
alias cntr is cnt(10 downto 9);
begin
process (clk, cnt)
begin
if rising_edge(clk) then
cnt <= cnt + "00000000000000001";
end if;
end process;
process(cnt, data, nibble)
begin
if(cntr = "00") then
HEX(3 downto 0) <= data(3 downto 0);
HEX(4) <= '0';
elsif(cntr= "01") then
HEX(3 downto 0) <= data(7 downto 4);
HEX(4) <= '0';
elsif(cntr = "10") then
HEX(3 downto 0) <= data(11 downto 8);
HEX(4) <= '0';
elsif(cntr = "11") then
HEX(3 downto 0) <= nibble;
HEX(4) <= '0';
end if;
end process;
with cntr select
an <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
--HEX-to-seven-segment decoder
--
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
with HEX select
seg<= "1000000" when "00000", --0
"1111001" when "00001", --1
"0100100" when "00010", --2
"0110000" when "00011", --3
"0011001" when "00100", --4
"0010010" when "00101", --5
"0000010" when "00110", --6
"1111000" when "00111", --7
"0000000" when "01000", --8
"0010000" when "01001", --9
"0001000" when "01010", --A
"0000011" when "01011", --B
"1000110" when "01100", --C
"0100001" when "01101", --D
"0000110" when "01110", --E
"0001110" when "01111", --F
"0111111" when "10000", -- minus sign
"1111111" when others; -- nothing, for plus sign
end Behavioral;
| bsd-3-clause | 39b02d0c5cfdd6d3faa4460ad64bf6b1 | 0.55146 | 3.290618 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaiigz_components.vhd | 1 | 103,356 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaiigz_atom_pack.all;
package arriaiigz_components is
--
-- arriaiigz_jtag
--
COMPONENT arriaiigz_jtag
generic (
lpm_type : string := "arriaiigz_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriaiigz_crcblock
--
COMPONENT arriaiigz_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaiigz_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaiigz_lcell_comb
--
COMPONENT arriaiigz_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaiigz_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriaiigz_routing_wire
--
COMPONENT arriaiigz_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- arriaiigz_lvds_transmitter
--
COMPONENT arriaiigz_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- ARRIAIIGZ
tx_output_path_delay_engineering_bits : Integer := -1; -- ARRIAIIGZ
enable_dpaclk_to_lvdsout : string := "off"; -- ARRIAIIGZ
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaiigz_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- ARRIAIIGZ
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- ARRIAIIGZ
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- ARRIAIIGZ
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriaiigz_rublock
--
COMPONENT arriaiigz_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriaiigz_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaiigz_ram_block
--
COMPONENT arriaiigz_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaiigz_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_ff
--
COMPONENT arriaiigz_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaiigz_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- arriaiigz_clkselect
--
COMPONENT arriaiigz_clkselect
generic (
lpm_type : STRING := "arriaiigz_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- arriaiigz_clkena
--
COMPONENT arriaiigz_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaiigz_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- arriaiigz_mlab_cell
--
COMPONENT arriaiigz_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaiigz_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_io_ibuf
--
COMPONENT arriaiigz_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaiigz_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_io_obuf
--
COMPONENT arriaiigz_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaiigz_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_ddio_in
--
COMPONENT arriaiigz_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaiigz_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_ddio_oe
--
COMPONENT arriaiigz_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaiigz_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_ddio_out
--
COMPONENT arriaiigz_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaiigz_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_termination
--
COMPONENT arriaiigz_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "arriaiigz_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- arriaiigz_termination_logic
--
COMPONENT arriaiigz_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "arriaiigz_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- arriaiigz_dll
--
COMPONENT arriaiigz_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaiigz_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_dll_offset_ctrl
--
COMPONENT arriaiigz_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaiigz_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_dqs_delay_chain
--
COMPONENT arriaiigz_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_dqs_enable
--
COMPONENT arriaiigz_dqs_enable
GENERIC (
lpm_type : string := "arriaiigz_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_dqs_enable_ctrl
--
COMPONENT arriaiigz_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_delay_chain
--
COMPONENT arriaiigz_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "arriaiigz_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_io_clock_divider
--
COMPONENT arriaiigz_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_output_phase_alignment
--
COMPONENT arriaiigz_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "arriaiigz_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_input_phase_alignment
--
COMPONENT arriaiigz_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "arriaiigz_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_half_rate_input
--
COMPONENT arriaiigz_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "arriaiigz_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_io_config
--
COMPONENT arriaiigz_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "arriaiigz_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_dqs_config
--
COMPONENT arriaiigz_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "arriaiigz_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_mac_mult
--
COMPONENT arriaiigz_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaiigz_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_mac_out
--
COMPONENT arriaiigz_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaiigz_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_io_pad
--
COMPONENT arriaiigz_io_pad
GENERIC (
lpm_type : string := "arriaiigz_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- arriaiigz_pll
--
COMPONENT arriaiigz_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaiigz_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "ARRIAIIGZ";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- arriaiigz_asmiblock
--
COMPONENT arriaiigz_asmiblock
generic (
lpm_type : string := "arriaiigz_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- arriaiigz_lvds_receiver
--
COMPONENT arriaiigz_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaiigz_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaiigz_pseudo_diff_out
--
COMPONENT arriaiigz_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaiigz_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaiigz_bias_block
--
COMPONENT arriaiigz_bias_block
GENERIC (
lpm_type : string := "arriaiigz_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
end arriaiigz_components;
| gpl-3.0 | b273298e74ebb1815d37d180a392f176 | 0.47945 | 4.345245 | false | false | false | false |
alvieboy/xtc-base | writeback.vhd | 1 | 2,344 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity writeback is
port (
clk: in std_logic;
rst: in std_logic;
-- Register 0 access writeback
r0_en: out std_logic;
r0_we: out std_logic;
r0_addr: out regaddress_type;
r0_write: out word_type_std;
-- Register 1 access writeback
r1_en: out std_logic;
r1_we: out std_logic;
r1_addr: out regaddress_type;
r1_write: out word_type_std;
busy: out std_logic;
-- Input for previous stages
mui: in memory_output_type;
eui: in execute_output_type -- For fast register write
);
end entity writeback;
architecture behave of writeback is
constant FAST_WRITEBACK: boolean := true;
begin
process(mui.mregwe,
eui.reg_source,
eui.regwe,
eui.dreg,
mui.mdata,
mui.mreg,
eui.alur,
eui.imreg,
eui.sprval,
eui.r,
eui.cop
)
variable wdata0: unsigned(31 downto 0);
variable wdata1: unsigned(31 downto 0);
variable wec: std_logic_vector(1 downto 0);
begin
wdata0 := (others => DontCareValue);
--wdata1 := (others => DontCareValue);
r0_we <= '0';
r0_en <= '0';
r0_addr <= (others => DontCareValue);
--r1_en <= '0';
--r1_we <= '0';
--r1_addr <= (others => DontCareValue);
busy <= '0';
if mui.mregwe='1' then
busy <= eui.r.regwe;
wdata0 := unsigned(mui.mdata);
r0_we <= '1';
r0_en <= '1';
r0_addr <= mui.mreg;
else
case eui.r.reg_source is
when reg_source_alu =>
wdata0 := eui.r.alur;
when reg_source_spr =>
wdata0 := eui.r.sprval;
when reg_source_pcnext=>
wdata0 := eui.r.npc;
when reg_source_cop=>
wdata0 := unsigned(eui.cop);
when others =>
wdata0 := (others => 'X');
end case;
r0_we <= eui.r.regwe;
r0_en <= eui.r.regwe;
r0_addr <= eui.r.dreg;
end if;
r0_write <= std_logic_vector(wdata0);
--r1_write <= std_logic_vector(wdata1);
end process;
end behave;
| bsd-3-clause | d731b7a52590c96645f20e75d16c59d5 | 0.537116 | 3.25104 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/elk_interface.vhd | 1 | 16,190 | -- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- This file contains code for the stuff that the Electron will actually see:
--
-- Sideways banks:
-- 0+1, 2+3, 4+5 = cartridges on the Minus One
-- 6 = "rom zero", implemented here
-- 7 = sideways RAM, implemented here
-- 8+9 = keyboard
-- 10+11 = BASIC ROM
-- 12, 13, 14, 15 = unused
entity elk_interface is
port (
debug_uart_txd : out std_logic; -- 2MHz trace uart transmitter
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic; -- 115k2 sideways ram input
ext_uart_txd : out std_logic; -- 115k2 debug output
fast_clock : in std_logic; -- 82MHz internal oscillator clock
elk_A : in std_logic_vector(15 downto 0);
elk_D : inout std_logic_vector(7 downto 0);
elk_PHI0 : in std_logic;
elk_16MHz : in std_logic;
elk_nEN : out std_logic; -- global enable
elk_nDBUF_OE : out std_logic; -- /OE for DBUF chip
elk_nSHADOW : out std_logic; -- '0' when shadowing memory
elk_nCPU_IS_EXTERNAL : out std_logic; -- '0' for external cpu
elk_RnW : in std_logic; -- input
elk_nRESET : in std_logic; -- input
elk_READY : in std_logic; -- input
elk_nNMI : in std_logic; -- input
elk_nIRQ : in std_logic; -- input
elk_CPU_DBUF : out std_logic -- '0' when we're driving the bus, '1' when the cpu is
);
end elk_interface;
architecture rtl of elk_interface is
-- '1' when elk_A is in sideways space
signal SIDEWAYS : std_logic;
-- '1' when elk_A = FCFx
signal DEBUG : std_logic;
signal debug_reg : std_logic_vector(7 downto 0) := "10101100"; -- &AC
-- currently selected memory bank, defaults to BASIC
signal bank : std_logic_vector(3 downto 0) := x"A";
-- '1' when we're selected
signal driving_bus : std_logic;
-- '1' when reading from the embedded ROM
signal reading_rom_zero : std_logic;
-- internal wiring for embedded ROM
signal rom_zero_D : std_logic_vector(7 downto 0);
-- '1' when reading/writing sideways ram
signal accessing_sideways_ram : std_logic;
signal sideways_ram_D : std_logic_vector(7 downto 0);
-- synchronous sideways ram signals
signal sideways_ram_data : std_logic_vector(7 downto 0) := (others => '0');
signal sideways_ram_address : std_logic_vector(13 downto 0) := (others => '0');
signal sideways_ram_rd : std_logic := '0';
signal sideways_ram_rd2 : std_logic := '0';
signal sideways_ram_we : std_logic := '0';
signal sideways_ram_q : std_logic_vector(7 downto 0);
component uart is
generic (
divide_count : integer
);
port (
clock : in std_logic; -- main clock
txd : out std_logic := '1';
tx_data : in std_logic_vector(23 downto 0);
tx_empty : out std_logic; -- '1' when tx_data can take a new byte
transmit : in std_logic -- pulse '1' when tx_data is valid
);
end component;
component uart_rx is
generic (
divide_count : integer
);
port (
clock : in std_logic; -- main clock
rxd : in std_logic := '1';
rx_data : out std_logic_vector(7 downto 0);
rx_full : out std_logic; -- '1' when rx_data is valid
ack : in std_logic -- pulse '1' when rx_data has been read
);
end component;
-- 2MHz debug uart
signal uart_txd : std_logic;
signal uart_tx_data : std_logic_vector(23 downto 0);
signal uart_tx_empty : std_logic;
signal uart_transmit : std_logic;
-- byte received from external uart to fill sideways ram
signal uart_rx_data : std_logic_vector(7 downto 0);
signal uart_rx_full : std_logic;
signal uart_rx_ack : std_logic := '1';
-- when loading ram via the uart, keep track of the address
signal uart_rx_address : unsigned(13 downto 0) := (others => '1');
-- 115k2 debug uart
signal ext_uart_tx_data : std_logic_vector(23 downto 0) := x"644266";
signal ext_uart_tx_empty : std_logic;
signal ext_uart_tx_transmit : std_logic := '0';
signal sync_PHI0 : std_logic_vector(2 downto 0) := "000";
type three_word_array is array(2 downto 0) of std_logic_vector(15 downto 0);
signal sync_A : three_word_array;
type three_byte_array is array(2 downto 0) of std_logic_vector(7 downto 0);
signal sync_D : three_byte_array;
signal sync_RESET : std_logic_vector(2 downto 0) := "000";
-- elk_A sampled on the rising PHI0 edge
signal sampled_A : std_logic_vector(15 downto 0) := x"0000";
-- FIFO so we can capture addr + data
component uart_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
end component;
signal uart_fifo_read_req : std_logic;
signal uart_fifo_write_req : std_logic;
signal uart_fifo_empty : std_logic;
signal uart_fifo_empty_sync : std_logic;
signal uart_fifo_full : std_logic;
signal uart_fifo_input : std_logic_vector(23 downto 0);
signal uart_fifo_output : std_logic_vector(23 downto 0);
signal uart_fifo_usedw : std_logic_vector(8 downto 0);
signal capturing : std_logic := '0';
-- count of the number of words we think we've sent to the uart.
-- this resets when we start a new transfer.
signal n_words_sent_to_uart : unsigned(31 downto 0) := x"00000000";
begin
-- global settings
elk_nEN <= '0';
elk_nSHADOW <= '1';
elk_nCPU_IS_EXTERNAL <= '1';
-- '0' to buffer from us to CPU, '1' to buffer from CPU to us
elk_CPU_DBUF <= not driving_bus;
-- only drive buffers during high clock period, when
-- either the cpu is writing, or we're selected and
-- the cpu is reading
elk_nDBUF_OE <= '0' when (
elk_PHI0 = '1' -- always buffer inward so we can track stuff
or elk_RnW = '0' -- extend out past the falling edge to give some hold time
) else '1';
-- sideways address space
SIDEWAYS <= '1' when elk_A(15 downto 14) = "10" else '0';
-- rom "zero" in bank 6 (the name comes from way back when I had it in bank 0)
--reading_rom_zero <= '1' when SIDEWAYS = '1' and bank = x"6" else '0';
--DEBUG: put it in &FDxx as well
reading_rom_zero <= '1' when
(SIDEWAYS = '1' and bank = x"6") or (elk_A(15 downto 8) = x"FD")
else '0';
-- sideways ram in bank 7 (or bank 0, depending)
accessing_sideways_ram <= '1' when SIDEWAYS = '1' and bank = x"7" else '0';
--DEBUG: put it in &FDxx as well
--accessing_sideways_ram <= '1' when
-- (SIDEWAYS = '1' and bank = x"7") or (elk_A(15 downto 8) = x"FD")
-- else '0';
-- debug register
DEBUG <= '1' when sampled_A(15 downto 4) = x"FCF" else '0';
-- data bus access
driving_bus <=
-- never during low clock period
'0' when elk_PHI0 = '0' else
-- never when cpu is writing
'0' when elk_RnW = '0' else
---- cases when we do drive the bus follow:
'1' when (
-- drive when reading embedded memory
(
accessing_sideways_ram = '1'
or reading_rom_zero = '1'
)
-- drive when reading registers
or (
DEBUG = '1'
)
) else
-- we're not selected
'0';
-- data bus
elk_D <=
"ZZZZZZZZ" when driving_bus = '0' else
-- -- reading from tube
-- tube_D when tube_access = '1' else
-- reading data from the embedded ROM
rom_zero_D when reading_rom_zero = '1' else
sideways_ram_D when accessing_sideways_ram = '1' else
-- reading debug register
debug_reg when DEBUG = '1' and elk_A(3 downto 0) = x"0" else
"0000" & bank when DEBUG = '1' and elk_A(3 downto 0) = x"1" else
elk_A(3 downto 0) & elk_A(3 downto 0) when DEBUG = '1' else
-- -- reading SPI status
-- MS_SD_MISO & "0000000" when EPP_STATUS = '1' else
-- -- reading serial RX
-- MS_SERIAL_RX & "11111" & MS_SERIAL_CTS & "1" when EUP_SERIAL = '1' else
-- default: this should never happen
"10101010";
-- Handle writes from Electron
process (elk_nRESET, elk_PHI0)
begin
if elk_nRESET = '0' then
-- default to BASIC ROM
bank <= x"A";
elsif falling_edge(elk_PHI0) then
-- set sideways bank
if (
elk_RnW = '0' and
elk_A(15 downto 8) & elk_A(3 downto 0) = x"FE5" and
elk_D(7 downto 4) = x"0"
) then
bank <= elk_D(3 downto 0);
end if;
-- debugging
if elk_RnW = '0' and DEBUG = '1' then
debug_reg <= elk_D;
end if;
end if;
end process;
-- Instantiate hardcoded ROM using 16k of block memory
rom_zero0: entity work.elk_user_flash port map (
slow_clock => elk_PHI0,
fast_clock => fast_clock,
reset_n => sync_RESET(2),
address => elk_A(13 downto 0), --debug_reg(5 downto 0) & elk_A(7 downto 0),
en => '1',
data_out => rom_zero_D
);
-- 16k synchronous block ram
ram0: entity work.sideways_ram port map (
clock => fast_clock,
data => sideways_ram_data,
address => sideways_ram_address,
we => sideways_ram_we,
q => sideways_ram_q
);
-- debug uart
uart0: component uart
generic map (
-- divide_count => 712 -- 115.2 kHz (= 82MHz / 712)
divide_count => 41 -- 2 MHz (= 82 MHz / 41)
-- divide_count => 20 -- ~2 MHz with 41MHz clock
)
port map (
clock => fast_clock,
txd => uart_txd,
tx_data => uart_tx_data,
tx_empty => uart_tx_empty,
transmit => uart_transmit
);
debug_uart_txd <= uart_txd;
ext_uart_rx0: component uart_rx
generic map (
divide_count => 178 -- 115200 bps or so
)
port map (
clock => fast_clock,
rxd => ext_uart_rxd,
rx_data => uart_rx_data,
rx_full => uart_rx_full,
ack => uart_rx_ack
);
ext_uart_tx0: component uart
generic map (
divide_count => 712 -- 115200 bps or so
)
port map (
clock => fast_clock,
txd => ext_uart_txd,
tx_data => ext_uart_tx_data,
tx_empty => ext_uart_tx_empty,
transmit => ext_uart_tx_transmit
);
uart_fifo_inst : uart_fifo PORT MAP (
clock => fast_clock,
empty => uart_fifo_empty,
full => uart_fifo_full,
data => uart_fifo_input,
wrreq => uart_fifo_write_req,
q => uart_fifo_output,
rdreq => uart_fifo_read_req,
usedw => uart_fifo_usedw
);
-- generic debug pins
-- debug_a <= uart_fifo_full;
debug_a <= '1' when sampled_A(15 downto 4) = x"FCF" else '0';
--debug_b <= capturing;
--debug_b <= '1' when sampled_A(15 downto 8) = x"FE" else '0';
debug_b <= '1' when elk_A(15 downto 4) = x"FCF" else '0';
process (fast_clock)
begin
if rising_edge(fast_clock) then
-- detect PHI0 rising and falling edge and capture data bus in time
sync_PHI0 <= sync_PHI0(1 downto 0) & elk_PHI0;
sync_A(2) <= sync_A(1);
sync_A(1) <= sync_A(0);
sync_A(0) <= elk_A;
sync_D(2) <= sync_D(1);
sync_D(1) <= sync_D(0);
sync_D(0) <= elk_D;
-- Sample 6502 address on rising PHI0 edge
if sync_PHI0(2) = '0' and sync_PHI0(1) = '1' then
sampled_A <= elk_A;
end if;
---------------------------------------------------
-- sideways ram, incl reading data from ext_uart --
---------------------------------------------------
sideways_ram_rd <= '0';
sideways_ram_rd2 <= '0';
sideways_ram_we <= '0';
uart_rx_ack <= '0';
ext_uart_tx_transmit <= '0';
-- latch byte from read started in previous clock cycle
if sideways_ram_rd = '1' then
sideways_ram_rd2 <= '1';
end if;
if sideways_ram_rd2 = '1' then
sideways_ram_D <= sideways_ram_q;
end if;
-- rising PHI0
if sync_PHI0(2) = '0' and sync_PHI0(1) = '1' then
-- trigger read
if accessing_sideways_ram = '1' then
sideways_ram_address <= elk_A(13 downto 0);
sideways_ram_rd <= '1';
end if;
-- falling PHI0
elsif sync_PHI0(2) = '1' and sync_PHI0(1) = '0' then
-- trigger write
if accessing_sideways_ram = '1' and elk_RnW = '0' then
sideways_ram_address <= sampled_A(13 downto 0);
sideways_ram_we <= '1';
sideways_ram_data <= elk_D;
end if;
-- reset RAM load address on writes to &FC90
if elk_RnW = '0' and elk_A = x"FC90" then
uart_rx_address <= (others => '0');
end if;
-- not on a clock edge: poll uart_rx_full
elsif uart_rx_full = '1' and uart_rx_ack = '0' then
-- write a byte from the uart into sideways ram
sideways_ram_address <= std_logic_vector(uart_rx_address);
uart_rx_address <= uart_rx_address + 1;
sideways_ram_we <= '1';
sideways_ram_data <= uart_rx_data;
uart_rx_ack <= '1';
-- send something out the debug uart too
ext_uart_tx_data <= "00" & std_logic_vector(uart_rx_address) & uart_rx_data;
ext_uart_tx_transmit <= '1';
end if;
-----------------------------------
-- fifo-filling and uart-feeding --
-----------------------------------
-- default: don't send a byte to the uart
uart_transmit <= '0';
-- default: don't read or write fifo
uart_fifo_read_req <= '0';
uart_fifo_write_req <= '0';
-- Capture data bus on falling PHI0 edge
if sync_PHI0(2) = '1' and sync_PHI0(1) = '0' then
-- start capture right after RESET
sync_RESET <= sync_RESET(1 downto 0) & elk_nRESET;
-- default: don't capture
capturing <= '0';
-- start capturing from an FExx access when the fifo is empty
if uart_fifo_full = '0' and -- stop when fifo fills up
(capturing = '1' -- continue if capturing
or (sync_RESET(2) = '0' and sync_RESET(1) = '1')
or (accessing_sideways_ram = '1' and uart_fifo_empty_sync = '1')
-- or DEBUG = '1' -- one shot capture after DEBUG access
-- or (sampled_A(15 downto 4) = x"FCF") -- capture any FCFx access
or (sampled_A(15 downto 4) = x"FCF" and uart_fifo_empty_sync = '1') -- start condition
-- or (sampled_A(15 downto 8) = x"FE" and uart_fifo_empty_sync = '1') -- start condition
)
then
-- continue capturing until the fifo is full
capturing <= '1'; -- comment this out to just capture accesses that match the start condition
-- pass in A and D from just before the falling clock edge
uart_fifo_input <= sync_A(2) & sync_D(2);
uart_fifo_write_req <= '1';
-- reset our counter and pass in a debug start word
if capturing = '0' then
n_words_sent_to_uart <= x"00000000";
--uart_fifo_input <= x"123456";
end if;
end if;
end if; -- falling PHI0 edge
-- feed from fifo into uart
uart_fifo_empty_sync <= uart_fifo_empty;
if uart_tx_empty = '1' and uart_fifo_empty_sync = '0' and uart_transmit = '0' then
if uart_fifo_read_req = '0' then
-- request a byte from the fifo
uart_fifo_read_req <= '1';
else
-- process byte from the fifo
uart_tx_data <= uart_fifo_output;
-- debug: output 16 bites from fifo and a counter word
-- uart_tx_data <= std_logic_vector(n_words_sent_to_uart(7 downto 0)) & uart_fifo_output(23 downto 8);
uart_transmit <= '1';
n_words_sent_to_uart <= n_words_sent_to_uart + 1;
end if;
end if;
end if; -- rising fast_clock edge
end process;
end rtl;
| apache-2.0 | ed362c44b46e77f33463fe10cc00373a | 0.587647 | 3.236705 | false | false | false | false |
google/myelin-acorn-electron-hardware | serial_sd_adapter/bbc_1mhz_bus_cpld/rom_fd00.vhd | 1 | 1,755 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- (Up to) 256 bytes of ROM
entity RomFD00 is
port (
A : in std_logic_vector(7 downto 0);
D : out std_logic_vector(7 downto 0)
);
end;
architecture Behavioural of RomFD00 is
begin
process(A)
begin
case A is
-- These are all dummy values for now; to be replaced with actual
-- data later
when x"00" => D <= x"12";
when x"01" => D <= x"d7";
when x"02" => D <= x"9f";
when x"03" => D <= x"6c";
when x"04" => D <= x"2a";
when x"05" => D <= x"42";
when x"06" => D <= x"ff";
when x"07" => D <= x"99";
when x"08" => D <= x"ca";
when x"09" => D <= x"d5";
when x"0a" => D <= x"a7";
when x"0b" => D <= x"46";
when x"0c" => D <= x"87";
when x"0d" => D <= x"a2";
when x"0e" => D <= x"b7";
when x"0f" => D <= x"dd";
when x"10" => D <= x"92";
when x"11" => D <= x"f7";
when x"12" => D <= x"44";
when x"13" => D <= x"c3";
when x"14" => D <= x"16";
when x"15" => D <= x"7a";
when x"16" => D <= x"ec";
when x"17" => D <= x"5d";
--when x"18" => D <= x"d9";
--when x"19" => D <= x"a2";
--when x"1a" => D <= x"f3";
--when x"1b" => D <= x"0a";
--when x"1c" => D <= x"2c";
--when x"1d" => D <= x"87";
--when x"1e" => D <= x"3e";
--when x"1f" => D <= x"44";
when x"fe" => D <= x"00";
when x"ff" => D <= x"fd";
when others => D <= "--------";
end case;
end process;
end Behavioural;
| apache-2.0 | 41dae6c09487e0df85609971c415b545 | 0.385755 | 2.826087 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_components.vhd | 1 | 86,165 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixv_atom_pack.all;
package stratixv_components is
--
-- stratixv_ff
--
COMPONENT stratixv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- stratixv_pseudo_diff_out
--
COMPONENT stratixv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tipd_oein : VitalDelayType01 := DefPropDelay01;
tpd_oein_oeout : VitalDelayType01 := DefPropDelay01;
tpd_oein_oebout : VitalDelayType01 := DefPropDelay01;
tipd_dtcin : VitalDelayType01 := DefPropDelay01;
tpd_dtcin_dtc : VitalDelayType01 := DefPropDelay01;
tpd_dtcin_dtcbar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratuxv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic;
dtcin : in std_logic := '0';
oein : in std_logic := '0';
dtc : OUT std_logic;
dtcbar : OUT std_logic;
oeout : OUT std_logic;
oebout : OUT std_logic
);
END COMPONENT;
--
-- stratixv_lcell_comb
--
COMPONENT stratixv_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixv_routing_wire
--
COMPONENT stratixv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixv_ram_block
--
COMPONENT stratixv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
ecc_pipeline_stage_enabled : STRING := "false";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 2;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
bist_ena : STRING := "false";
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : STRING := "";
mem_init1 : STRING := "";
mem_init2 : STRING := "";
mem_init3 : STRING := "";
mem_init4 : STRING := "";
mem_init5 : STRING := "";
mem_init6 : STRING := "";
mem_init7 : STRING := "";
mem_init8 : STRING := "";
mem_init9 : STRING := "";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
nerror : IN STD_LOGIC := '1';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixv_mlab_cell
--
COMPONENT stratixv_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "stratixv_mlab_cell";
lpm_hint : STRING := "true";
mem_init0 : STRING := "";
mixed_port_feed_through_mode : STRING := "new"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
clr : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixv_io_ibuf
--
COMPONENT stratixv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- stratixv_io_obuf
--
COMPONENT stratixv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tipd_parallelterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixv_ddio_in
--
COMPONENT stratixv_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixv_ddio_oe
--
COMPONENT stratixv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixv_ddio_out
--
COMPONENT stratixv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixv_io_pad
--
COMPONENT stratixv_io_pad
GENERIC (
lpm_type : string := "stratixv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- stratixv_bias_block
--
COMPONENT stratixv_bias_block
GENERIC (
lpm_type : string := "stratixv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- stratixv_mac
--
COMPONENT stratixv_mac
generic (
lpm_type : string := "stratixv_mac";
ax_width : integer := 16;
ay_scan_in_width : integer := 16;
az_width : integer := 1;
bx_width : integer := 16;
by_width : integer := 16;
scan_out_width : integer := 1;
result_a_width : integer := 33;
result_b_width : integer := 1;
operation_mode : string := "m18x18_sumof2";
mode_sub_location : integer := 0;
operand_source_max : string := "input";
operand_source_may : string := "input";
operand_source_mbx : string := "input";
operand_source_mby : string := "input";
preadder_subtract_a : string := "false";
preadder_subtract_b : string := "false";
signed_max : string := "false";
signed_may : string := "false";
signed_mbx : string := "false";
signed_mby : string := "false";
ay_use_scan_in : string := "false";
by_use_scan_in : string := "false";
delay_scan_out_ay : string := "false";
delay_scan_out_by : string := "false";
use_chainadder : string := "false";
load_const_value : integer := 0;
coef_a_0 : integer := 0;
coef_a_1 : integer := 0;
coef_a_2 : integer := 0;
coef_a_3 : integer := 0;
coef_a_4 : integer := 0;
coef_a_5 : integer := 0;
coef_a_6 : integer := 0;
coef_a_7 : integer := 0;
coef_b_0 : integer := 0;
coef_b_1 : integer := 0;
coef_b_2 : integer := 0;
coef_b_3 : integer := 0;
coef_b_4 : integer := 0;
coef_b_5 : integer := 0;
coef_b_6 : integer := 0;
coef_b_7 : integer := 0;
ax_clock : string := "none";
ay_scan_in_clock : string := "none";
az_clock : string := "none";
bx_clock : string := "none";
by_clock : string := "none";
coef_sel_a_clock : string := "none";
coef_sel_b_clock : string := "none";
sub_clock : string := "none";
negate_clock : string := "none";
accumulate_clock : string := "none";
load_const_clock : string := "none";
complex_clock : string := "none";
output_clock : string := "none"
);
port (
sub : in std_logic := '0';
negate : in std_logic := '0';
accumulate : in std_logic := '0';
loadconst : in std_logic := '0';
complex : in std_logic := '0';
cin : in std_logic := '0';
ax : in std_logic_vector(ax_width-1 downto 0) := (others => '0');
ay : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0');
scanin : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0');
az : in std_logic_vector(az_width-1 downto 0) := (others => '0');
bx : in std_logic_vector(bx_width-1 downto 0) := (others => '0');
by : in std_logic_vector(by_width-1 downto 0) := (others => '0');
coefsela : in std_logic_vector(2 downto 0) := (others => '0');
coefselb : in std_logic_vector(2 downto 0) := (others => '0');
clk : in std_logic_vector(2 downto 0) := (others => '0');
aclr : in std_logic_vector(1 downto 0) := (others => '0');
ena : in std_logic_vector(2 downto 0) := (others => '1');
chainin : in std_logic_vector(63 downto 0) := (others => '0');
cout : out std_logic;
dftout : out std_logic;
resulta : out std_logic_vector(result_a_width-1 downto 0);
resultb : out std_logic_vector(result_b_width-1 downto 0);
scanout : out std_logic_vector(scan_out_width-1 downto 0);
chainout : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--
-- stratixv_clk_phase_select
--
COMPONENT stratixv_clk_phase_select
generic (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
invert_phase : string := "false";
physical_clock_source : string := "auto"
);
port (
clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
phaseinvertctrl : in std_logic := '0';
powerdown : in std_logic := '0';
clkout : out std_logic
);
END COMPONENT;
--
-- stratixv_clkena
--
COMPONENT stratixv_clkena
generic (
clock_type : string := "auto";
ena_register_mode : string := "always enabled";
lpm_type : string := "stratixv_clkena";
ena_register_power_up : string := "high";
disable_mode : string := "low";
test_syn : string := "high"
);
port (
inclk : in std_logic := '1';
ena : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- stratixv_clkselect
--
COMPONENT stratixv_clkselect
generic (
lpm_type : string := "stratixv_clkselect";
test_cff : string := "low"
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- stratixv_delay_chain
--
COMPONENT stratixv_delay_chain
generic (
sim_intrinsic_rising_delay : integer := 200;
sim_intrinsic_falling_delay : integer := 200;
sim_rising_delay_increment : integer := 10;
sim_falling_delay_increment : integer := 10;
lpm_type : string := "stratixv_delay_chain"
);
port (
datain : in std_logic := '0';
delayctrlin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic
);
END COMPONENT;
--
-- stratixv_dll_offset_ctrl
--
COMPONENT stratixv_dll_offset_ctrl
generic (
use_offset : string := "false";
static_offset : integer := 0;
use_pvt_compensation : string := "false"
);
port (
clk : in std_logic := '0';
offsetdelayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offset : in std_logic_vector(6 downto 0) := (OTHERS => '0');
addnsub : in std_logic := '0';
aload : in std_logic := '0';
offsetctrlout : out std_logic_vector(6 downto 0);
offsettestout : out std_logic_vector(6 downto 0)
);
END COMPONENT;
--
-- stratixv_dll
--
COMPONENT stratixv_dll
generic (
input_frequency : string := "0 MHz";
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0;
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixv_dll";
delay_chain_length : integer := 8
);
port (
aload : in std_logic := '0';
clk : in std_logic := '0';
upndnin : in std_logic := '0';
upndninclkena : in std_logic := '0';
delayctrlout : out std_logic_vector(6 downto 0);
dqsupdate : out std_logic;
offsetdelayctrlout : out std_logic_vector(6 downto 0);
offsetdelayctrlclkout : out std_logic;
upndnout : out std_logic;
dffin : out std_logic;
locked : out std_logic
);
END COMPONENT;
--
-- stratixv_dqs_config
--
COMPONENT stratixv_dqs_config
generic (
lpm_type : string := "stratixv_dqs_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '0';
update : in std_logic := '0';
dqsbusoutdelaysetting : out std_logic_vector(5 downto 0);
dqsbusoutdelaysetting2 : out std_logic_vector(5 downto 0);
dqsinputphasesetting : out std_logic_vector(1 downto 0);
dqsoutputphasesetting : out std_logic_vector(1 downto 0);
dqoutputphasesetting : out std_logic_vector(1 downto 0);
resyncinputphasesetting : out std_logic_vector(1 downto 0);
enaoctcycledelaysetting : out std_logic_vector(2 downto 0);
enainputcycledelaysetting : out std_logic;
enaoutputcycledelaysetting : out std_logic_vector(2 downto 0);
dqsenabledelaysetting : out std_logic_vector(7 downto 0);
octdelaysetting1 : out std_logic_vector(4 downto 0);
octdelaysetting2 : out std_logic_vector(4 downto 0);
enadqsenablephasetransferreg : out std_logic;
enaoctphasetransferreg : out std_logic;
enaoutputphasetransferreg : out std_logic;
enainputphasetransferreg : out std_logic;
resyncinputphaseinvert : out std_logic;
dqoutputphaseinvert : out std_logic;
dqsoutputphaseinvert : out std_logic;
dataout : out std_logic;
resyncinputzerophaseinvert : out std_logic;
dqs2xoutputphasesetting : out std_logic_vector(1 downto 0);
dqs2xoutputphaseinvert : out std_logic;
ck2xoutputphasesetting : out std_logic_vector(1 downto 0);
ck2xoutputphaseinvert : out std_logic;
dq2xoutputphasesetting : out std_logic_vector(1 downto 0);
dq2xoutputphaseinvert : out std_logic;
postamblephasesetting : out std_logic_vector(1 downto 0);
postamblephaseinvert : out std_logic;
dividerphaseinvert : out std_logic;
addrphasesetting : out std_logic_vector(1 downto 0);
addrphaseinvert : out std_logic;
enadqscycledelaysetting : out std_logic_vector(2 downto 0);
enadqsphasetransferreg : out std_logic;
dqoutputzerophasesetting : out std_logic_vector(1 downto 0);
postamblezerophasesetting : out std_logic_vector(2 downto 0);
dividerioehratephaseinvert : out std_logic;
dqsdisablendelaysetting : out std_logic_vector(7 downto 0);
addrpowerdown : out std_logic;
dqsoutputpowerdown : out std_logic;
dqoutputpowerdown : out std_logic;
resyncinputpowerdown : out std_logic;
dqs2xoutputpowerdown : out std_logic;
ck2xoutputpowerdown : out std_logic;
dq2xoutputpowerdown : out std_logic;
postamblepowerdown : out std_logic
);
END COMPONENT;
--
-- stratixv_dqs_delay_chain
--
COMPONENT stratixv_dqs_delay_chain
generic (
dqs_input_frequency : string := "unused";
dqs_phase_shift : integer := 0;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
use_alternate_input_for_first_stage_delayctrl : string := "false";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
test_enable : string := "false"
);
port (
dqsin : in std_logic := '0';
dqsenable : in std_logic := '1';
dqsdisablen : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
dqsupdateen : in std_logic := '1';
phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0');
testin : in std_logic := '0';
dffin : out std_logic;
dqsbusout : out std_logic
);
END COMPONENT;
--
-- stratixv_dqs_enable_ctrl
--
COMPONENT stratixv_dqs_enable_ctrl
generic (
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
sim_dqsenablein_pre_delay : integer := 0;
bypass_output_register : string := "false";
ext_delay_chain_setting : integer := 0;
int_delay_chain_setting : integer := 0;
use_enable_tracking : string := "false";
use_on_die_variation_tracking : string := "false";
use_pvt_compensation : string := "false"
);
port (
dqsenablein : in std_logic := '1';
zerophaseclk : in std_logic := '1';
enaphasetransferreg : in std_logic := '0';
levelingclk : in std_logic := '1';
dffin : out std_logic;
dffphasetransfer : out std_logic;
dffextenddqsenable : out std_logic;
dqsenableout : out std_logic;
prevphasevalid : out std_logic;
enatrackingreset : in std_logic := '0';
enatrackingevent : out std_logic;
enatrackingupdwn : out std_logic;
nextphasealign : out std_logic;
prevphasealign : out std_logic;
prevphasedelaysetting : out std_logic_vector(5 downto 0)
);
END COMPONENT;
--
-- stratixv_duty_cycle_adjustment
--
COMPONENT stratixv_duty_cycle_adjustment
generic (
duty_cycle_delay_mode : string := "none";
lpm_type : string := "stratixv_duty_cycle_adjustment"
);
port (
clkin : in std_logic := '0';
delaymode : in std_logic := '0';
delayctrlin : in std_logic_vector(3 downto 0) := (OTHERS => '0');
clkout : out std_logic
);
END COMPONENT;
--
-- stratixv_fractional_pll
--
COMPONENT stratixv_fractional_pll
generic (
lpm_type : string := "stratixv_fractional_pll";
output_clock_frequency : string := "0 ps";
pll_chg_pump_crnt : integer := 10;
pll_clkin_cmp_path : string := "nrm";
pll_cmp_buf_dly : string := "0 ps";
pll_dnm_phsf_cnt_sel : string := "all_c";
pll_dsm_k : integer := 1;
pll_dsm_out_sel : string := "cram";
pll_enable : string := "true";
pll_fbclk_cmp_path : string := "nrm";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_lock_fltr_cfg : integer := 0;
pll_lock_fltr_test : string := "false";
pll_lock_win : string := "nrm";
pll_lp_fltr_cs : integer := 0;
pll_lp_fltr_rp : integer := 20;
pll_m_cnt_bypass_en : string := "false";
pll_m_cnt_coarse_dly : string := "0 ps";
pll_m_cnt_fine_dly : string := "0 ps";
pll_m_cnt_hi_div : integer := 0;
pll_m_cnt_in_src : string := "ph_mux_clk";
pll_m_cnt_lo_div : integer := 0;
pll_m_cnt_odd_div_duty_en : string := "false";
pll_m_cnt_ph_mux_prst : integer := 0;
pll_m_cnt_prst : integer := 0;
pll_mmd_div_sel : integer := 2;
pll_n_cnt_bypass_en : string := "false";
pll_n_cnt_coarse_dly : string := "0 ps";
pll_n_cnt_fine_dly : string := "0 ps";
pll_n_cnt_hi_div : integer := 1;
pll_n_cnt_lo_div : integer := 1;
pll_n_cnt_odd_div_duty_en : string := "false";
pll_p_cnt_set : integer := 1;
pll_pfd_pulse_width_min : string := "0 ps";
pll_ref_vco_over : integer := 1300;
pll_ref_vco_under : integer := 500;
pll_s_cnt_set : integer := 1;
pll_slf_rst : string := "true";
pll_tclk_mux_en : string := "false";
pll_unlock_fltr_cfg : integer := 0;
pll_vco_div : integer := 600;
pll_vco_ph0_en : string := "false";
pll_vco_ph1_en : string := "false";
pll_vco_ph2_en : string := "false";
pll_vco_ph3_en : string := "false";
pll_vco_ph4_en : string := "false";
pll_vco_ph5_en : string := "false";
pll_vco_ph6_en : string := "false";
pll_vco_ph7_en : string := "false";
pll_vco_rng_dt : string := "dis_en";
pll_vt_bp_reg_div : integer := 1700;
pll_vt_out : integer := 1650;
pll_vt_rg_mode : string := "nrm_mode";
pll_vt_test : string := "false";
reference_clock_frequency : string := "0 ps"
);
port (
analogtest : in std_logic;
cntnen : in std_logic;
coreclkfb : in std_logic;
crcm : in std_logic_vector(1 downto 0);
crcp : in std_logic_vector(2 downto 0);
crdltasgma : in std_logic_vector(23 downto 0);
crdsmen : in std_logic;
crfbclkdly : in std_logic_vector(2 downto 0);
crfbclksel : in std_logic_vector(1 downto 0);
crlckf : in std_logic_vector(11 downto 0);
crlcktest : in std_logic;
crlfc : in std_logic_vector(1 downto 0);
crlfr : in std_logic_vector(4 downto 0);
crlfrd : in std_logic_vector(5 downto 0);
crlock : in std_logic_vector(3 downto 0);
crmdirectfb : in std_logic;
crmhi : in std_logic_vector(8 downto 0);
crmlo : in std_logic_vector(8 downto 0);
crmmddiv : in std_logic_vector(1 downto 0);
crmprst : in std_logic_vector(10 downto 0);
crmrdly : in std_logic_vector(4 downto 0);
crmsel : in std_logic_vector(1 downto 0);
crnhi : in std_logic_vector(8 downto 0);
crnlckf : in std_logic_vector(2 downto 0);
crnlo : in std_logic_vector(8 downto 0);
crnrdly : in std_logic_vector(4 downto 0);
crpcnt : in std_logic_vector(3 downto 0);
crpfdpulsewidth : in std_logic;
crrefclkdly : in std_logic_vector(2 downto 0);
crrefclksel : in std_logic_vector(1 downto 0);
crscnt : in std_logic_vector(3 downto 0);
crselfrst : in std_logic_vector(1 downto 0);
crtclk : in std_logic_vector(1 downto 0);
crtest : in std_logic_vector(1 downto 0);
crvcop : in std_logic_vector(7 downto 0);
crvcophbyps : in std_logic;
crvr : in std_logic_vector(6 downto 0);
enpfd : in std_logic;
lfreset : in std_logic;
lvdsfbin : in std_logic;
niotricntr : in std_logic;
pdbvr : in std_logic;
pfden : in std_logic;
pllpd : in std_logic;
refclkin : in std_logic;
reset0 : in std_logic;
roc : in std_logic;
shift : in std_logic;
shiftdonein : in std_logic;
shiften : in std_logic;
up : in std_logic;
vcopen : in std_logic;
zdbinput : in std_logic;
fbclk : out std_logic;
fblvdsout : out std_logic;
lock : out std_logic;
mcntout : out std_logic;
selfrst : out std_logic;
shiftdoneout : out std_logic;
tclk : out std_logic;
vcoover : out std_logic;
vcoph : out std_logic_vector(7 downto 0);
vcounder : out std_logic
);
END COMPONENT;
--
-- stratixv_half_rate_input
--
COMPONENT stratixv_half_rate_input
generic (
power_up : string := "low";
async_mode : string := "no_reset";
use_dataoutbypass : string := "false"
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '1');
directin : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
dataoutbypass : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0);
dffin : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- stratixv_input_phase_alignment
--
COMPONENT stratixv_input_phase_alignment
generic (
power_up : string := "low";
async_mode : string := "no_reset";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
lpm_type : string := "stratixv_input_phase_alignment"
);
port (
datain : in std_logic := '1';
levelingclk : in std_logic := '0';
zerophaseclk : in std_logic := '0';
areset : in std_logic := '0';
enainputcycledelay : in std_logic := '0';
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dffphasetransfer : out std_logic
);
END COMPONENT;
--
-- stratixv_io_clock_divider
--
COMPONENT stratixv_io_clock_divider
generic (
power_up : string := "low";
invert_phase : string := "false";
use_masterin : string := "false";
lpm_type : string := "stratixv_io_clock_divider"
);
port (
clk : in std_logic := '0';
phaseinvertctrl : in std_logic := '0';
masterin : in std_logic := '0';
clkout : out std_logic;
slaveout : out std_logic
);
END COMPONENT;
--
-- stratixv_io_config
--
COMPONENT stratixv_io_config
generic (
lpm_type : string := "stratixv_io_config"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
update : in std_logic := '0';
outputdelaysetting1 : out std_logic_vector(5 downto 0);
outputdelaysetting2 : out std_logic_vector(5 downto 0);
padtoinputregisterdelaysetting : out std_logic_vector(5 downto 0);
padtoinputregisterrisefalldelaysetting : out std_logic_vector(5 downto 0);
inputclkdelaysetting : out std_logic_vector(1 downto 0);
inputclkndelaysetting : out std_logic_vector(1 downto 0);
dutycycledelaymode : out std_logic;
dutycycledelaysetting : out std_logic_vector(3 downto 0);
dataout : out std_logic
);
END COMPONENT;
--
-- stratixv_leveling_delay_chain
--
COMPONENT stratixv_leveling_delay_chain
generic (
physical_clock_source : string := "dqs";
sim_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10
);
port (
clkin : in std_logic := '0';
delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0');
clkout : out std_logic_vector(3 downto 0)
);
END COMPONENT;
--
-- stratixv_lvds_rx
--
COMPONENT stratixv_lvds_rx
generic (
data_align_rollover : integer := 2;
enable_dpa : string := "false";
lose_lock_on_one_change : string := "false";
reset_fifo_at_first_lock : string := "true";
align_to_rising_edge_only : string := "true";
use_serial_feedback_input : string := "off";
dpa_debug : string := "false";
x_on_bitslip : string := "true";
enable_soft_cdr : string := "false";
dpa_clock_output_phase_shift : integer := 0;
enable_dpa_initial_phase_selection : string := "false";
dpa_initial_phase_value : integer := 0;
enable_dpa_align_to_rising_edge_only : string := "false";
net_ppm_variation : integer := 0;
is_negative_ppm_drift : string := "false";
rx_input_path_delay_engineering_bits : integer := 2;
lpm_type : string := "stratixv_lvds_rx";
data_width : integer := 10
);
port (
clock0 : in std_logic := '0';
datain : in std_logic := '0';
enable0 : in std_logic := '0';
dpareset : in std_logic := '0';
dpahold : in std_logic := '0';
dpaswitch : in std_logic := '0';
fiforeset : in std_logic := '0';
bitslip : in std_logic := '0';
bitslipreset : in std_logic := '0';
serialfbk : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
dataout : out std_logic_vector(data_width-1 downto 0);
dpalock : out std_logic;
bitslipmax : out std_logic;
serialdataout : out std_logic;
postdpaserialdataout : out std_logic;
divfwdclk : out std_logic;
dpaclkout : out std_logic;
observableout : out std_logic_vector(3 downto 0)
);
END COMPONENT;
--
-- stratixv_lvds_tx
--
COMPONENT stratixv_lvds_tx
generic (
bypass_serializer : string := "false";
invert_clock : string := "false";
use_falling_clock_edge : string := "false";
use_serial_data_input : string := "false";
use_post_dpa_serial_data_input : string := "false";
is_used_as_outclk : string := "false";
tx_output_path_delay_engineering_bits : integer := -1;
enable_dpaclk_to_lvdsout : string := "false";
lpm_type : string := "stratixv_lvds_tx";
data_width : integer := 10
);
port (
datain : in std_logic_vector(data_width-1 downto 0) := (OTHERS => '0');
clock0 : in std_logic := '0';
enable0 : in std_logic := '0';
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dpaclkin : in std_logic := '0';
dataout : out std_logic;
serialfdbkout : out std_logic;
observableout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratixv_output_alignment
--
COMPONENT stratixv_output_alignment
generic (
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
add_phase_transfer_reg : string := "false"
);
port (
datain : in std_logic := '1';
clk : in std_logic := '0';
areset : in std_logic := '0';
sreset : in std_logic := '0';
enaoutputcycledelay : in std_logic_vector(2 downto 0) := (OTHERS => '0');
enaphasetransferreg : in std_logic := '0';
dataout : out std_logic;
dffin : out std_logic;
dff1t : out std_logic;
dff2t : out std_logic;
dffphasetransfer : out std_logic
);
END COMPONENT;
--
-- stratixv_pll_dll_output
--
COMPONENT stratixv_pll_dll_output
generic (
lpm_type : string := "stratixv_pll_dll_output";
pll_dll_src : string := "c_0_cnt"
);
port (
cclk : in std_logic_vector(17 downto 0);
clkin : in std_logic_vector(3 downto 0);
crsel : in std_logic_vector(4 downto 0);
mout : in std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- stratixv_pll_dpa_output
--
COMPONENT stratixv_pll_dpa_output
generic (
lpm_type : string := "stratixv_pll_dpa_output";
pll_vcoph_div_en : integer := 1
);
port (
crdpaen : in std_logic_vector(1 downto 0);
pd : in std_logic;
phin : in std_logic_vector(7 downto 0);
phout : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--
-- stratixv_pll_extclk_output
--
COMPONENT stratixv_pll_extclk_output
generic (
lpm_type : string := "stratixv_pll_extclk_output";
pll_extclk_cnt_src : string := "m0_cnt";
pll_extclk_enable : string := "true";
pll_extclk_invert : string := "false";
pll_extclken_invert : string := "false"
);
port (
cclk : in std_logic_vector(17 downto 0);
clken : in std_logic;
crenable : in std_logic;
crextclkeninv : in std_logic;
crinv : in std_logic;
crsel : in std_logic_vector(4 downto 0);
mcnt : in std_logic;
niotri : in std_logic;
extclk : out std_logic
);
END COMPONENT;
--
-- stratixv_pll_lvds_output
--
COMPONENT stratixv_pll_lvds_output
generic (
lpm_type : string := "stratixv_pll_lvds_output";
pll_loaden_coarse_dly : string := "0 ps";
pll_loaden_fine_dly : string := "0 ps";
pll_lvdsclk_coarse_dly : string := "0 ps";
pll_lvdsclk_fine_dly : string := "0 ps"
);
port (
ccout : in std_logic_vector(1 downto 0);
crdly : in std_logic_vector(9 downto 0);
loaden : out std_logic;
lvdsclk : out std_logic
);
END COMPONENT;
--
-- stratixv_pll_output_counter
--
COMPONENT stratixv_pll_output_counter
generic (
lpm_type : string := "stratixv_pll_output_counter";
duty_cycle : integer := 50;
output_clock_frequency : string := "0 ps";
phase_shift : string := "0 ps";
pll_c_cnt_bypass_en : string := "false";
pll_c_cnt_coarse_dly : string := "0 ps";
pll_c_cnt_fine_dly : string := "0 ps";
pll_c_cnt_hi_div : integer := 3;
pll_c_cnt_in_src : string := "ph_mux_clk";
pll_c_cnt_lo_div : integer := 3;
pll_c_cnt_odd_div_even_duty_en : string := "false";
pll_c_cnt_ph_mux_prst : integer := 0;
pll_c_cnt_prst : integer := 1
);
port (
cascadein : in std_logic;
crhi : in std_logic_vector(8 downto 0);
crlo : in std_logic_vector(8 downto 0);
nen : in std_logic;
shift : in std_logic;
shiftdonei : in std_logic;
shiften : in std_logic;
tclk : in std_logic;
up : in std_logic;
vcoph : in std_logic_vector(7 downto 0);
divclk : out std_logic;
shiftdoneo : out std_logic
);
END COMPONENT;
--
-- stratixv_pll_reconfig
--
COMPONENT stratixv_pll_reconfig
generic (
lpm_type : string := "stratixv_pll_reconfig"
);
port (
cntsel0 : in std_logic_vector(4 downto 0);
cr3lo : out std_logic_vector(10 downto 0);
cr3prst : out std_logic_vector(10 downto 0);
cr3sel : out std_logic_vector(1 downto 0);
cr4dly : out std_logic_vector(10 downto 0);
cr4hi : out std_logic_vector(10 downto 0);
cr4lo : out std_logic_vector(10 downto 0);
cr4prst : out std_logic_vector(10 downto 0);
cr4sel : out std_logic_vector(1 downto 0);
cr5dly : out std_logic_vector(10 downto 0);
cr5hi : out std_logic_vector(10 downto 0);
cntsel1 : in std_logic_vector(4 downto 0);
cr5lo : out std_logic_vector(10 downto 0);
cr5prst : out std_logic_vector(10 downto 0);
cr5sel : out std_logic_vector(1 downto 0);
cr6dly : out std_logic_vector(10 downto 0);
cr6hi : out std_logic_vector(10 downto 0);
cr6lo : out std_logic_vector(10 downto 0);
cr6prst : out std_logic_vector(10 downto 0);
cr6sel : out std_logic_vector(1 downto 0);
cr7dly : out std_logic_vector(10 downto 0);
cr7hi : out std_logic_vector(10 downto 0);
dprio0addr : in std_logic_vector(6 downto 0);
cr7lo : out std_logic_vector(10 downto 0);
cr7prst : out std_logic_vector(10 downto 0);
cr7sel : out std_logic_vector(1 downto 0);
cr8dly : out std_logic_vector(10 downto 0);
cr8hi : out std_logic_vector(10 downto 0);
cr8lo : out std_logic_vector(10 downto 0);
cr8prst : out std_logic_vector(10 downto 0);
cr8sel : out std_logic_vector(1 downto 0);
cr9dly : out std_logic_vector(10 downto 0);
cr9hi : out std_logic_vector(10 downto 0);
dprio0byteen : in std_logic_vector(1 downto 0);
cr9lo : out std_logic_vector(10 downto 0);
cr9prst : out std_logic_vector(10 downto 0);
cr9sel : out std_logic_vector(1 downto 0);
crclkenen : out std_logic_vector(3 downto 0);
crdll : out std_logic_vector(9 downto 0);
crext : out std_logic_vector(19 downto 0);
crextclkeninv : out std_logic_vector(3 downto 0);
crextclkinv : out std_logic_vector(10 downto 0);
crfpll0cp : out std_logic_vector(2 downto 0);
crfpll0dpadiv : out std_logic_vector(1 downto 0);
dprio0clk : in std_logic;
crfpll0lckbypass : out std_logic;
crfpll0lfc : out std_logic_vector(1 downto 0);
crfpll0lfr : out std_logic_vector(4 downto 0);
crfpll0lfrd : out std_logic_vector(5 downto 0);
crfpll0lockc : out std_logic_vector(3 downto 0);
crfpll0lockf : out std_logic_vector(11 downto 0);
crfpll0mdirectfb : out std_logic;
crfpll0mdly : out std_logic_vector(4 downto 0);
crfpll0mhi : out std_logic_vector(8 downto 0);
crfpll0mlo : out std_logic_vector(8 downto 0);
dprio0din : in std_logic_vector(15 downto 0);
crfpll0mprst : out std_logic_vector(10 downto 0);
crfpll0msel : out std_logic_vector(1 downto 0);
crfpll0ndly : out std_logic_vector(4 downto 0);
crfpll0nhi : out std_logic_vector(8 downto 0);
crfpll0nlo : out std_logic_vector(8 downto 0);
crfpll0pfdpulsewidth : out std_logic;
crfpll0selfrst : out std_logic_vector(1 downto 0);
crfpll0tclk : out std_logic_vector(1 downto 0);
crfpll0test : out std_logic_vector(1 downto 0);
crfpll0unlockf : out std_logic_vector(2 downto 0);
dprio0mdiodis : in std_logic;
crfpll0vcop : out std_logic_vector(7 downto 0);
crfpll0vcophbyps : out std_logic;
crfpll0vcorangeen : out std_logic;
crfpll0vr : out std_logic_vector(6 downto 0);
crfpll1cp : out std_logic_vector(2 downto 0);
crfpll1dpadiv : out std_logic_vector(1 downto 0);
crfpll1lckbypass : out std_logic;
crfpll1lfc : out std_logic_vector(1 downto 0);
crfpll1lfr : out std_logic_vector(4 downto 0);
crfpll1lfrd : out std_logic_vector(5 downto 0);
dprio0read : in std_logic;
crfpll1lockc : out std_logic_vector(3 downto 0);
crfpll1lockf : out std_logic_vector(11 downto 0);
crfpll1mdirectfb : out std_logic;
crfpll1mdly : out std_logic_vector(4 downto 0);
crfpll1mhi : out std_logic_vector(8 downto 0);
crfpll1mlo : out std_logic_vector(8 downto 0);
crfpll1mprst : out std_logic_vector(10 downto 0);
crfpll1msel : out std_logic_vector(1 downto 0);
crfpll1ndly : out std_logic_vector(4 downto 0);
crfpll1nhi : out std_logic_vector(8 downto 0);
dprio0rstn : in std_logic;
crfpll1nlo : out std_logic_vector(8 downto 0);
crfpll1pfdpulsewidth : out std_logic;
crfpll1selfrst : out std_logic_vector(1 downto 0);
crfpll1tclk : out std_logic_vector(1 downto 0);
crfpll1test : out std_logic_vector(1 downto 0);
crfpll1unlockf : out std_logic_vector(2 downto 0);
crfpll1vcop : out std_logic_vector(7 downto 0);
crfpll1vcophbyps : out std_logic;
crfpll1vcorangeen : out std_logic;
crfpll1vr : out std_logic_vector(6 downto 0);
dprio0sershiftload : in std_logic;
crinv : out std_logic_vector(85 downto 0);
crlvds : out std_logic_vector(39 downto 0);
crphaseshiftsel : out std_logic_vector(17 downto 0);
crvcosel : out std_logic_vector(17 downto 0);
crwrapback : out std_logic;
crwrapbackmux : out std_logic;
dprio0blockselect : out std_logic;
dprio0dout : out std_logic_vector(15 downto 0);
dprio1blockselect : out std_logic;
dprio1dout : out std_logic_vector(15 downto 0);
dprio0write : in std_logic;
fpll0cntnen : out std_logic;
fpll0enpfd : out std_logic;
fpll0lfreset : out std_logic;
fpll0niotricntr : out std_logic;
fpll0pdbvr : out std_logic;
fpll0pllpd : out std_logic;
fpll0reset0 : out std_logic;
fpll0vcopen : out std_logic;
fpll1cntnen : out std_logic;
fpll1enpfd : out std_logic;
dprio1addr : in std_logic_vector(6 downto 0);
fpll1lfreset : out std_logic;
fpll1niotricntr : out std_logic;
fpll1pdbvr : out std_logic;
fpll1pllpd : out std_logic;
fpll1reset0 : out std_logic;
fpll1vcopen : out std_logic;
iocsrdataout : out std_logic;
phasedone : out std_logic_vector(1 downto 0);
shift0 : out std_logic;
shift1 : out std_logic;
dprio1byteen : in std_logic_vector(1 downto 0);
shiftdone0o : out std_logic;
shiftdone1o : out std_logic;
shiften : out std_logic_vector(17 downto 0);
up0 : out std_logic;
up1 : out std_logic;
dprio1clk : in std_logic;
dprio1din : in std_logic_vector(15 downto 0);
dprio1mdiodis : in std_logic;
dprio1read : in std_logic;
dprio1rstn : in std_logic;
dprio1sershiftload : in std_logic;
dprio1write : in std_logic;
fpll0selfrst : in std_logic;
fpll1selfrst : in std_logic;
iocsrclkin : in std_logic;
iocsrdatain : in std_logic;
ioplniotri : in std_logic;
nfrzdrv : in std_logic;
nreset : in std_logic_vector(1 downto 0);
pfden : in std_logic;
phaseen0 : in std_logic;
phaseen1 : in std_logic;
pllbias : in std_logic;
updn0 : in std_logic;
updn1 : in std_logic;
cr0dly : out std_logic_vector(10 downto 0);
cr0hi : out std_logic_vector(10 downto 0);
cr0lo : out std_logic_vector(10 downto 0);
cr0prst : out std_logic_vector(10 downto 0);
cr0sel : out std_logic_vector(1 downto 0);
cr10dly : out std_logic_vector(10 downto 0);
cr10hi : out std_logic_vector(10 downto 0);
cr10lo : out std_logic_vector(10 downto 0);
cr10prst : out std_logic_vector(10 downto 0);
cr10sel : out std_logic_vector(1 downto 0);
cr11dly : out std_logic_vector(10 downto 0);
cr11hi : out std_logic_vector(10 downto 0);
cr11lo : out std_logic_vector(10 downto 0);
cr11prst : out std_logic_vector(10 downto 0);
cr11sel : out std_logic_vector(1 downto 0);
cr12dly : out std_logic_vector(10 downto 0);
cr12hi : out std_logic_vector(10 downto 0);
cr12lo : out std_logic_vector(10 downto 0);
cr12prst : out std_logic_vector(10 downto 0);
cr12sel : out std_logic_vector(1 downto 0);
cr13dly : out std_logic_vector(10 downto 0);
cr13hi : out std_logic_vector(10 downto 0);
cr13lo : out std_logic_vector(10 downto 0);
cr13prst : out std_logic_vector(10 downto 0);
cr13sel : out std_logic_vector(1 downto 0);
cr14dly : out std_logic_vector(10 downto 0);
cr14hi : out std_logic_vector(10 downto 0);
cr14lo : out std_logic_vector(10 downto 0);
cr14prst : out std_logic_vector(10 downto 0);
cr14sel : out std_logic_vector(1 downto 0);
cr15dly : out std_logic_vector(10 downto 0);
cr15hi : out std_logic_vector(10 downto 0);
cr15lo : out std_logic_vector(10 downto 0);
cr15prst : out std_logic_vector(10 downto 0);
cr15sel : out std_logic_vector(1 downto 0);
cr16dly : out std_logic_vector(10 downto 0);
cr16hi : out std_logic_vector(10 downto 0);
cr16lo : out std_logic_vector(10 downto 0);
cr16prst : out std_logic_vector(10 downto 0);
cr16sel : out std_logic_vector(1 downto 0);
cr17dly : out std_logic_vector(10 downto 0);
cr17hi : out std_logic_vector(10 downto 0);
cr17lo : out std_logic_vector(10 downto 0);
cr17prst : out std_logic_vector(10 downto 0);
cr17sel : out std_logic_vector(1 downto 0);
cr1dly : out std_logic_vector(10 downto 0);
cr1hi : out std_logic_vector(10 downto 0);
cr1lo : out std_logic_vector(10 downto 0);
cr1prst : out std_logic_vector(10 downto 0);
cr1sel : out std_logic_vector(1 downto 0);
cr2dly : out std_logic_vector(10 downto 0);
cr2hi : out std_logic_vector(10 downto 0);
cr2lo : out std_logic_vector(10 downto 0);
cr2prst : out std_logic_vector(10 downto 0);
cr2sel : out std_logic_vector(1 downto 0);
cr3dly : out std_logic_vector(10 downto 0);
cr3hi : out std_logic_vector(10 downto 0)
);
END COMPONENT;
--
-- stratixv_pll_refclk_select
--
COMPONENT stratixv_pll_refclk_select
generic (
lpm_type : string := "stratixv_pll_refclk_select";
pll_auto_clk_sw_en : string := "false";
pll_clk_loss_edge : string := "pll_clk_loss_both_edges";
pll_clk_loss_sw_en : string := "false";
pll_clk_sw_dly : string := "0 ps";
pll_manu_clk_sw_en : string := "false";
pll_sw_refclk_src : string := "clk_0";
reference_clock_frequency_0 : string := "0 ps";
reference_clock_frequency_1 : string := "0 ps"
);
port (
extswitch : in std_logic;
pllen : in std_logic;
refclk : in std_logic_vector(1 downto 0);
clk0bad : out std_logic;
clk1bad : out std_logic;
clkout : out std_logic;
pllclksel : out std_logic
);
END COMPONENT;
--
-- stratixv_termination_logic
--
COMPONENT stratixv_termination_logic
generic (
lpm_type : string := "stratixv_termination_logic";
a_iob_oct_test : string := "a_iob_oct_test_off"
);
port (
s2pload : in std_logic := '0';
serdata : in std_logic := '0';
scanenable : in std_logic := '0';
scanclk : in std_logic := '0';
enser : in std_logic := '0';
seriesterminationcontrol : out std_logic_vector(15 downto 0);
parallelterminationcontrol : out std_logic_vector(15 downto 0)
);
END COMPONENT;
--
-- stratixv_termination
--
COMPONENT stratixv_termination
generic (
lpm_type : string := "stratixv_termination";
a_oct_cal_mode : string := "a_oct_cal_mode_none";
a_oct_user_oct : string := "a_oct_user_oct_off";
a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off";
a_oct_pwrdn : string := "a_oct_pwrdn_on";
a_oct_intosc : string := "a_oct_intosc_none";
a_oct_test_0 : string := "a_oct_test_0_off";
a_oct_test_1 : string := "a_oct_test_1_off";
a_oct_test_4 : string := "a_oct_test_4_off";
a_oct_test_5 : string := "a_oct_test_5_off";
a_oct_pllbiasen : string := "a_oct_pllbiasen_dis";
a_oct_clkenusr_inv : string := "a_oct_clkenusr_inv_off";
a_oct_enserusr_inv : string := "a_oct_enserusr_inv_off";
a_oct_scanen_inv : string := "a_oct_scanen_inv_off";
a_oct_vrefl : string := "a_oct_vrefl_m";
a_oct_vrefh : string := "a_oct_vrefh_m";
a_oct_rsmult : string := "a_oct_rsmult_1";
a_oct_rsadjust : string := "a_oct_rsadjust_none";
a_oct_calclr : string := "a_oct_calclr_off";
a_oct_rshft_rup : string := "a_oct_rshft_rup_enable";
a_oct_rshft_rdn : string := "a_oct_rshft_rdn_enable";
a_oct_usermode : string := "false"
);
port (
rzqin : in std_logic := '0';
enserusr : in std_logic := '0';
nclrusr : in std_logic := '0';
clkenusr : in std_logic := '0';
clkusr : in std_logic := '0';
scanen : in std_logic := '0';
serdatafromcore : in std_logic := '0';
scanclk : in std_logic := '0';
otherenser : in std_logic_vector(9 downto 0) := (OTHERS => '0');
serdatain : in std_logic := '0';
serdataout : out std_logic;
enserout : out std_logic;
compoutrup : out std_logic;
compoutrdn : out std_logic;
serdatatocore : out std_logic;
scanin : in std_logic := '0';
scanout : out std_logic;
clkusrdftout : out std_logic
);
END COMPONENT;
--
-- stratixv_asmiblock
--
COMPONENT stratixv_asmiblock
generic (
lpm_type : string := "stratixv_asmiblock"
);
port (
dclk : in std_logic;
sce : in std_logic;
oe : in std_logic;
data0out : in std_logic;
data1out : in std_logic;
data2out : in std_logic;
data3out : in std_logic;
data0oe : in std_logic;
data1oe : in std_logic;
data2oe : in std_logic;
data3oe : in std_logic;
data0in : out std_logic;
data1in : out std_logic;
data2in : out std_logic;
data3in : out std_logic
);
END COMPONENT;
--
-- stratixv_chipidblock
--
COMPONENT stratixv_chipidblock
generic (
lpm_type : string := "stratixv_chipidblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixv_controller
--
COMPONENT stratixv_controller
generic (
lpm_type : string := "stratixv_controller"
);
port (
nceout : out std_logic
);
END COMPONENT;
--
-- stratixv_crcblock
--
COMPONENT stratixv_crcblock
generic (
oscillator_divider : integer := 256;
lpm_type : string := "stratixv_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixv_jtag
--
COMPONENT stratixv_jtag
generic (
lpm_type : string := "stratixv_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo : out std_logic;
tmsutap : out std_logic;
tckutap : out std_logic;
tdiutap : out std_logic;
shiftuser : out std_logic;
clkdruser : out std_logic;
updateuser : out std_logic;
runidleuser : out std_logic;
usr1user : out std_logic
);
END COMPONENT;
--
-- stratixv_prblock
--
COMPONENT stratixv_prblock
generic (
lpm_type : string := "stratixv_prblock"
);
port (
clk : in std_logic;
corectl : in std_logic;
prrequest : in std_logic;
data : in std_logic_vector(15 downto 0);
externalrequest : out std_logic;
error : out std_logic;
ready : out std_logic;
done : out std_logic
);
END COMPONENT;
--
-- stratixv_rublock
--
COMPONENT stratixv_rublock
generic (
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
sim_init_config_is_application : string := "false";
sim_init_watchdog_enabled : string := "false";
lpm_type : string := "stratixv_rublock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixv_tsdblock
--
COMPONENT stratixv_tsdblock
generic (
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
lpm_type : string := "stratixv_tsdblock"
);
port (
clk : in std_logic;
ce : in std_logic;
clr : in std_logic;
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic
);
END COMPONENT;
--
-- stratixv_read_fifo
--
COMPONENT stratixv_read_fifo
generic (
use_half_rate_read : string := "false";
sim_wclk_pre_delay : integer := 0
);
port (
datain : in std_logic_vector(1 downto 0) := (OTHERS => '0');
wclk : in std_logic := '0';
we : in std_logic := '0';
rclk : in std_logic := '0';
re : in std_logic := '0';
areset : in std_logic := '0';
plus2 : in std_logic := '0';
dataout : out std_logic_vector(3 downto 0)
);
END COMPONENT;
--
-- stratixv_read_fifo_read_enable
--
COMPONENT stratixv_read_fifo_read_enable
generic (
use_stalled_read_enable : string := "false"
);
port (
re : in std_logic := '1';
rclk : in std_logic := '0';
plus2 : in std_logic := '0';
areset : in std_logic := '0';
reout : out std_logic;
plus2out : out std_logic
);
END COMPONENT;
--
-- stratixv_phy_clkbuf
--
COMPONENT stratixv_phy_clkbuf
generic (
level1_mux : string := "VALUE_FAST";
level2_mux : string := "VALUE_FAST"
);
port (
inclk : in std_logic_vector(3 downto 0) := (OTHERS => '1');
outclk : out std_logic_vector(3 downto 0)
);
END COMPONENT;
end stratixv_components;
| gpl-3.0 | 683cd7a2c8345364b57b410a3d7fcd40 | 0.474984 | 3.678806 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratix_atoms.vhd | 1 | 448,717 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratix_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratix_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratix_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratix_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratix_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratix_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratix_pllpack;
package body stratix_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratix_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
entity stratix_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratix_dffe : entity is TRUE;
end stratix_dffe;
-- architecture body --
architecture behave of stratix_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratix_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratix_atom_pack.all;
entity stratix_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratix_mux21 : entity is TRUE;
end stratix_mux21;
architecture AltVITAL of stratix_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratix_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratix_atom_pack.all;
entity stratix_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratix_mux41 : entity is TRUE;
end stratix_mux41;
architecture AltVITAL of stratix_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratix_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratix_atom_pack.all;
-- entity declaration --
entity stratix_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratix_and1 : entity is TRUE;
end stratix_and1;
-- architecture body --
architecture AltVITAL of stratix_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for STRATIX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- Stratix Lcell.
--
-- Outputs : Asynchnous LUT function of Stratix Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratix_atom_pack.all;
ENTITY stratix_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of stratix_asynch_lcell : ENTITY is TRUE;
END stratix_asynch_lcell;
ARCHITECTURE vital_le of stratix_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- Stratix Lcell.
--
-- Outputs : Registered output of Stratix Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
ENTITY stratix_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of stratix_lcell_register : ENTITY is TRUE;
end stratix_lcell_register;
ARCHITECTURE vital_le_reg of stratix_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant stratix_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => stratix_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_lcell
--
-- Description : VHDL simulation model for Stratix Lcell.
--
-- Outputs : Output of Stratix Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use work.stratix_asynch_lcell;
use work.stratix_lcell_register;
ENTITY stratix_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratix_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end stratix_lcell;
ARCHITECTURE vital_le_atom of stratix_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT stratix_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT stratix_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: stratix_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: stratix_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_ASYNCH_IO
--
-- Description : Timing simulation model for the asynchronous submodule
-- of STRATIX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
ENTITY stratix_asynch_io is
GENERIC (
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
phase_shift_delay : time := 0 ps;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsundelayedout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout: out STD_LOGIC;
dqsundelayedout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of stratix_asynch_io : ENTITY is TRUE;
end stratix_asynch_io;
ARCHITECTURE behave of stratix_asynch_io is
attribute VITAL_LEVEL0 of behave : ARCHITECTURE is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_ipd, delayctrlin, tipd_delayctrlin);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, delayctrlin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable dqsundelayedout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable combout_tmp : std_logic;
variable dqs_delay : VitalDelayType01 := (0 ps, 0 ps);
variable warn_x : boolean := false;
variable combout_delay : VitalDelayType01;
variable dqs_delay_is_applied : boolean := false;
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (delayctrlin_ipd = '1') then
if (not dqs_delay_is_applied) then
for i in combout_delay'range loop
combout_delay(i) := combout_delay(i) + phase_shift_delay;
end loop;
dqs_delay_is_applied := true;
end if;
warn_x := false;
elsif (delayctrlin_ipd = '0') then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
warn_x := false;
elsif (delayctrlin_ipd'event) then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
if (not warn_x) then
assert false report "Illegal value detected on input DELAYCTRLIN" severity warning;
warn_x := true;
end if;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsundelayedout,
OutSignalName => "dqsundelayedout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dqsundelayedout, TRUE)),
GlitchData => dqsundelayedout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_IO_REGISTER
--
-- Description : Timing simulation model for the register submodule
-- of STRATIX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
ENTITY stratix_io_register is
GENERIC (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratix_io_register : ENTITY is TRUE;
end stratix_io_register;
ARCHITECTURE vital_io_reg of stratix_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : ARCHITECTURE is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd,
areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_IO
--
-- Description : Timing simulation model for STRATIX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use work.stratix_pllpack.all;
use work.stratix_asynch_io;
use work.stratix_io_register;
use work.stratix_mux21;
use work.stratix_and1;
ENTITY stratix_io is
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratix_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
end stratix_io;
ARCHITECTURE structure of stratix_io is
COMPONENT stratix_asynch_io
GENERIC
(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
phase_shift_delay : time := 0 ps);
PORT
(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC;
dqsundelayedout : out std_logic
);
end COMPONENT;
COMPONENT stratix_io_register
GENERIC
(
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01);
PORT
(
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end COMPONENT;
COMPONENT stratix_mux21
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
PORT
(
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end COMPONENT;
COMPONENT stratix_and1
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT
(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
constant phase_shift_delay : time := (dqs_str2int(sim_dll_phase_shift) * dqs_str2int(sim_dqs_input_frequency) * 1 ps) / 360;
begin
not_inclk <= not inclk;
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio0_reg
in_ddio0_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio1_reg
-- this register does not have sync_reset
in_ddio1_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => "none",
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn
);
-- out_reg
out_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up
)
PORT map
(
regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- out ddio reg
out_ddio_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
PORT map
(
regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe reg
oe_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe_pulse reg
oe_pulse_reg : stratix_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratix_and1
PORT map
(
Y => outclk_delayed,
IN1 => outclk
);
ddio_data_mux : stratix_mux21
PORT map
(
MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed
);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or
ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratix_asynch_io
GENERIC map
(
OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
PHASE_SHIFT_DELAY => phase_shift_delay
)
PORT map
(
datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
delayctrlin => delayctrlin,
padio => padio,
combout => combout,
regout => regout,
ddioregout => ddioregout,
dqsundelayedout => dqsundelayedout
);
end structure;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_BIT_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
entity stratix_mac_bit_register is
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end stratix_mac_bit_register;
architecture reg_arch OF stratix_mac_bit_register IS
signal data_ipd : STD_LOGIC := '0';
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC := '0';
begin
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC := '0';
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := '0';
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
end process;
-- Path Delay Selection
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
entity stratix_mac_register is
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end stratix_mac_register;
architecture reg_arch OF stratix_mac_register IS
signal data_ipd : STD_LOGIC_VECTOR (71 downto 0) := (others => '0');
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := (others => '0');
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
end process;
sh: block
begin
g0 : for i in data'range generate
process(data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "data(i)",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
END PROCESS;
end generate g0;
end block;
-- Path Delay Selection
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_MULT_INTERNAL
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
entity stratix_mac_mult_internal is
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
port
(
dataa : IN std_logic_vector (dataa_width - 1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width - 1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end stratix_mac_mult_internal;
architecture mult_internal_arch OF stratix_mac_mult_internal IS
signal dataa_ipd : std_logic_vector (dataa_width-1 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector (datab_width-1 downto 0) := (others => '0');
signal dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
process(dataa_ipd, datab_ipd, signa, signb)
begin
if((signa = '0') and (signb = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '1')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa = '0') and (signb = '0')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
PathDelay :block
begin
g1: for i in dataa_width + datab_width -1 downto 0 generate
p1: process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin -- process p1
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process p1;
a: if i < dataa_width generate
p2: PROCESS(dataa_ipd(i))
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p2;
end generate a;
b: if i < datab_width generate
p3: PROCESS(datab_ipd(i))
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p3;
end generate b;
end generate g1;
end block;
end mult_internal_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_OUT_INTERNAL
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
ENTITY stratix_mac_out_internal IS
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0) := (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
-- /////////////////////////////////////////////////////////////////////////////
-- //
-- // ADD_OR_SUB_ACCUM
-- //
-- /////////////////////////////////////////////////////////////////////////////
function add_or_sub_accum
(
sign_a : in std_logic := '0';
data_a : in std_logic_vector(dataout_width-1 downto 0)
:= (others => '0');
sign_b : in std_logic := '0';
data_b : in std_logic_vector(dataa_width-1 downto 0)
:= (others => '0');
operation : in string
) return std_logic_vector is
variable sign : std_logic := '0';
variable unsigned_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable unsigned_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
begin
-- signed or unsigned
sign := ((data_a(dataout_width-1) and (sign_a))
or (data_b(dataa_width-1) and (sign_b)));
if(sign = '1') then
signed_add(dataout_width downto 0) :=
sxt((signed(data_a) + signed(data_b)), dataout_width+1);
signed_sub(dataout_width downto 0) :=
sxt((signed(data_a) - signed(data_b)), dataout_width+1);
else
unsigned_add(dataout_width downto 0) :=
ext((unsigned('0' & data_a) + unsigned('0' & data_b)), dataout_width+1);
unsigned_sub(dataout_width downto 0) :=
sxt((unsigned('0' & data_a) - unsigned('0' & data_b)), dataout_width+1);
end if;
if (operation = "ADD") then
if (sign = '1') then
return signed_add(dataout_width downto 0);
else
return unsigned_add(dataout_width downto 0);
end if;
elsif (operation = "SUB") then
if (sign = '1') then
return signed_sub(dataout_width downto 0);
else
return unsigned_sub(dataout_width downto 0);
end if;
end if;
end add_or_sub_accum;
end stratix_mac_out_internal;
ARCHITECTURE mac_add OF stratix_mac_out_internal IS
signal dataa_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datac_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datad_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal dataa_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_s : std_logic_vector(71 downto 0) := (others => '0');
signal datac_u : std_logic_vector(71 downto 0) := (others => '0');
signal datac_s : std_logic_vector(71 downto 0) := (others => '0');
signal datad_u : std_logic_vector(71 downto 0) := (others => '0');
signal datad_s : std_logic_vector(71 downto 0) := (others => '0');
signal signx_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal signy_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub0_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub1_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal zeroacc_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal dataout_t : std_logic_vector(72 downto 0) := (others => '0');
signal next_dataout : std_logic_vector(72 downto 0) := (others => '0');
signal sll_36 : std_logic_vector(35 downto 0) := (others => '0');
signal sll_18 : std_logic_vector(17 downto 0) := (others => '0');
signal accoverflow_tmp: std_logic := '0';
signal sign_a_or_b : std_logic := '0';
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 : for i in datac'range generate
VitalWireDelay (datac_ipd(i), datac(i), tipd_datac(i));
end generate;
g4 : for i in datad'range generate
VitalWireDelay (datad_ipd(i), datad(i), tipd_datad(i));
end generate;
end block;
signx_tmp(0) <= signx;
signy_tmp(0) <= signy;
addnsub0_tmp(0) <= addnsub0;
addnsub1_tmp(0) <= addnsub1;
zeroacc_tmp(0) <= zeroacc;
sign_a_or_b <= '1' when ((signx_tmp(0) = '1') or (signy_tmp(0) = '1'))
else '0';
main : process (dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
signx_tmp, signy_tmp, addnsub0_tmp, addnsub1_tmp,
dataout_t, zeroacc_tmp, dataout_global,
sign_a_or_b, next_dataout, dataa_u, datab_u, datac_u,
datad_u, datab_s, datac_s, datad_s)
begin
if operation_mode = "output_only" then
dataout_tmp(dataa_width-1 downto 0) <= dataa_ipd(dataa_width-1 downto 0);
elsif operation_mode = "accumulator" then
if(zeroacc_tmp(0) = '0') then
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
else
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
end if;
dataout_tmp(dataout_width-1 downto 0) <=
next_dataout(dataout_width-1 downto 0);
if(sign_a_or_b = '1') then
accoverflow_tmp <=
next_dataout(dataa_width+16) xor next_dataout(dataa_width+15);
else
accoverflow_tmp <= next_dataout(dataa_width+16);
end if;
elsif operation_mode = "one_level_adder" then
if(addnsub0_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
end if;
elsif operation_mode = "two_level_adder" then
-- dataout = (dataa - datab) + (datac - datad);
if(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac - datad);
elsif(addnsub0_tmp(0) = '1' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa - datab) + (datac + datad);
elsif(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '1') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac + datad);
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
end if;
elsif operation_mode = "36_bit_multiply" then
dataa_u <= (others => '0');
datab_u <= (others => '0');
datac_u <= (others => '0');
datad_u <= (others => '0');
datab_s <= (others => '0');
datac_s <= (others => '0');
sll_36 <= (others => '0');
sll_18 <= (others => '0');
dataa_u(35 downto 0) <= dataa_ipd;
datab_u(71 downto 36) <= datab_ipd;
datab_s(71 downto 36) <= datab_ipd;
datac_u(53 downto 18) <= datac_ipd;
datac_s(71 downto 18) <= sxt(datac_ipd(datac_width-1 downto 0), 54);
datad_u(53 downto 18) <= datad_ipd;
datad_s(71 downto 18) <= sxt(datad_ipd(datad_width-1 downto 0), 54);
if((signx_tmp(0) = '0') and (signy_tmp(0) = '0')) then
dataout_tmp <= unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signx_tmp(0) = '0') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '0')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
end if;
end if;
end process;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx_tmp'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy_tmp'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0_tmp'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1_tmp'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc_tmp'last_event, tpd_zeroacc_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate g1;
g2 : for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx_tmp'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy_tmp'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0_tmp'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1_tmp'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc_tmp'last_event, tpd_zeroacc_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
end generate g2;
end block;
END mac_add;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_MULT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use work.stratix_mac_register;
use work.stratix_mac_mult_internal;
entity stratix_mac_mult IS
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
-- SELECT THE CLOCK, CLEAR, or ENABLE LINE FUNCTION
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratix_mac_mult;
architecture mult_arch OF stratix_mac_mult IS
component stratix_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratix_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratix_mac_mult_internal
GENERIC
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT
(
dataa : IN std_logic_vector (dataa_width-1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width-1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end component;
signal mult_output : std_logic_vector(71 downto 0) := (others => '0');
signal scanouta_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal scanoutb_tmp : std_logic_vector(71 downto 0) := (others => '0') ;
signal signa_out : std_logic := '1';
signal signb_out : std_logic := '1';
signal dataa_tmp : std_logic_vector(71 downto 0);
signal datab_tmp : std_logic_vector(71 downto 0);
signal dataout_tmp : std_logic_vector(71 downto 0);
signal dataa_async : std_logic := '0';
signal datab_async : std_logic := '0';
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal signa_internally : std_logic := '0';
signal signb_internally : std_logic := '0';
signal clk_dataa : std_logic;
signal aclr_dataa : std_logic;
signal ena_dataa : std_logic;
signal clk_datab : std_logic;
signal aclr_datab : std_logic;
signal ena_datab : std_logic;
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal dataa_if_clear : std_logic;
signal datab_if_clear : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
begin
signa_tmp <= signa;
signb_tmp <= signb;
dataa_async <= '1' when (dataa_clock = "none" or dataa_clear = "none") else '0';
datab_async <= '1' when (datab_clock = "none" or datab_clear = "none") else '0';
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
dataout_async <=
'1' when (output_clock = "none" or output_clear = "none") else '0';
signa_internally <= signa_out when (signa_internally_grounded = "false") else '0';
signb_internally <= signb_out when (signb_internally_grounded = "false") else '0';
--Assign the values for if_aclr ports
dataa_if_clear <= '1' when (dataa_clear /= "none") else '0';
datab_if_clear <= '1' when (datab_clear /= "none") else '0';
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
dataa_tmp(dataa_width-1 downto 0) <= dataa;
datab_tmp(datab_width-1 downto 0) <= datab;
dataout <= dataout_tmp((dataa_width+datab_width)-1 downto 0);
clk_dataa <= clk(select_the(dataa_clock));
aclr_dataa <= aclr(select_the(dataa_clear))or not(devclrn) or not(devpor);
ena_dataa <= ena(select_the(dataa_clock));
dataa_mac_reg : stratix_mac_register
generic map (data_width => dataa_width)
port map (data => dataa_tmp,
clk => clk_dataa,
aclr => aclr_dataa,
ena => ena_dataa,
if_aclr => dataa_if_clear,
dataout => scanouta_tmp,
async => dataa_async);
clk_datab <= clk(select_the(datab_clock));
aclr_datab <= aclr(select_the(datab_clear)) or not(devclrn) or not(devpor);
ena_datab <= ena(select_the(datab_clock));
datab_mac_reg : stratix_mac_register
generic map (data_width => datab_width)
port map (data => datab_tmp,
clk => clk_datab,
aclr => aclr_datab,
ena => ena_datab,
if_aclr => datab_if_clear,
dataout => scanoutb_tmp,
async => datab_async);
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear))or not(devclrn) or not(devpor);
ena_signa <= ena(select_the(signa_clock));
signa_mac_reg : stratix_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_out,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear))or not(devclrn) or not(devpor);
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratix_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_out,
async => signb_async);
mac_multiply : stratix_mac_mult_internal
generic map (dataa_width => dataa_width,
datab_width => datab_width)
port map(dataa => scanouta_tmp(dataa_width-1 downto 0),
datab => scanoutb_tmp(datab_width-1 downto 0),
signa => signa_internally,
signb => signb_internally,
scanouta => scanouta,
scanoutb => scanoutb,
dataout => mult_output(dataa_width+datab_width-1 downto 0)
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear))or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_mac_reg : stratix_mac_register
generic map (data_width => (dataa_width+datab_width))
port map (data => mult_output,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
END mult_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIX_MAC_OUT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use work.stratix_mac_register;
use work.stratix_mac_out_internal;
entity stratix_mac_out IS
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratix_mac_out;
ARCHITECTURE out_arch OF stratix_mac_out IS
component stratix_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratix_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr: IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratix_mac_out_internal
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0)
:= (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
end component;
signal signa_pipe : std_logic;
signal signb_pipe : std_logic;
signal zeroacc_pipe : std_logic;
signal addnsub0_pipe : std_logic;
signal addnsub1_pipe : std_logic;
signal signa_out : std_logic;
signal signb_out : std_logic;
signal zeroacc_out : std_logic;
signal addnsub0_out : std_logic;
signal addnsub1_out : std_logic;
signal dataout_sig : std_logic_vector (71 downto 0);
signal accoverflow_sig : std_logic;
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal zeroacc_async : std_logic := '0';
signal addnsub0_async : std_logic := '1';
signal addnsub1_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal accoverflow_async : std_logic := '0';
signal signa_pipeline_async : std_logic := '0';
signal signb_pipeline_async : std_logic := '0';
signal zeroacc_pipeline_async : std_logic := '0';
signal addnsub0_pipeline_async : std_logic := '1';
signal addnsub1_pipeline_async : std_logic := '1';
signal dataout_tmp : std_logic_vector(71 downto 0);
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_zeroacc : std_logic;
signal aclr_zeroacc : std_logic;
signal ena_zeroacc : std_logic;
signal clk_addnsub0 : std_logic;
signal aclr_addnsub0 : std_logic;
signal ena_addnsub0 : std_logic;
signal clk_addnsub1 : std_logic;
signal aclr_addnsub1 : std_logic;
signal ena_addnsub1 : std_logic;
signal clk_signa_pipeline : std_logic;
signal aclr_signa_pipeline : std_logic;
signal ena_signa_pipeline : std_logic;
signal clk_signb_pipeline : std_logic;
signal aclr_signb_pipeline : std_logic;
signal ena_signb_pipeline : std_logic;
signal clk_zeroacc_pipeline : std_logic;
signal aclr_zeroacc_pipeline : std_logic;
signal ena_zeroacc_pipeline : std_logic;
signal clk_addnsub0_pipeline : std_logic;
signal aclr_addnsub0_pipeline : std_logic;
signal ena_addnsub0_pipeline : std_logic;
signal clk_addnsub1_pipeline : std_logic;
signal aclr_addnsub1_pipeline : std_logic;
signal ena_addnsub1_pipeline : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal clk_accoverflow : std_logic;
signal aclr_accoverflow : std_logic;
signal ena_accoverflow : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal signa_pip_if_clear : std_logic;
signal signb_pip_if_clear : std_logic;
signal zeroacc_if_clear : std_logic;
signal zeroacc_pip_if_clear : std_logic;
signal addnsub0_if_clear : std_logic;
signal addnsub1_if_clear : std_logic;
signal addnsub0_pip_if_clear : std_logic;
signal addnsub1_pip_if_clear : std_logic;
signal accoverflow_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal accoverflow_tmp : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
signal addnsub0_tmp : std_logic;
signal addnsub1_tmp : std_logic;
signal zeroacc_tmp : std_logic;
BEGIN
signa_tmp <= signa ;
signb_tmp <= signb ;
addnsub0_tmp <= addnsub0 ;
addnsub1_tmp <= addnsub1 ;
zeroacc_tmp <= zeroacc ;
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
addnsub0_async <= '1' when
(addnsub0_clock = "none" or addnsub0_clear = "none") else '0';
addnsub1_async <= '1' when
(addnsub1_clock = "none" or addnsub1_clear = "none") else '0';
zeroacc_async <= '1' when
(zeroacc_clock = "none" or zeroacc_clear = "none") else '0';
signa_pipeline_async <= '1' when
(signa_pipeline_clock = "none" or signa_pipeline_clear = "none") else '0';
signb_pipeline_async <= '1' when
(signb_pipeline_clock = "none" or signb_pipeline_clear = "none") else '0';
addnsub0_pipeline_async <= '1' when
(addnsub0_pipeline_clock = "none" or addnsub0_pipeline_clear = "none") else '0';
addnsub1_pipeline_async <= '1' when
(addnsub1_pipeline_clock = "none" or addnsub1_pipeline_clear = "none") else '0';
zeroacc_pipeline_async <= '1' when
(zeroacc_pipeline_clock = "none" or zeroacc_pipeline_clear = "none") else '0';
dataout_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
accoverflow_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear));
ena_signa <= ena(select_the(signa_clock));
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
signa_pip_if_clear <= '1' when (signa_pipeline_clear /= "none") else '0';
signb_pip_if_clear <= '1' when (signb_pipeline_clear /= "none") else '0';
zeroacc_if_clear <= '1' when (zeroacc_clear /= "none") else '0';
zeroacc_pip_if_clear <= '1' when (zeroacc_pipeline_clear /= "none") else '0';
addnsub0_if_clear <= '1' when (addnsub0_clear /= "none") else '0';
addnsub0_pip_if_clear <= '1' when (addnsub0_pipeline_clear /= "none") else '0';
addnsub1_if_clear <= '1' when (addnsub1_clear /= "none") else '0';
addnsub1_pip_if_clear <= '1' when (addnsub1_pipeline_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
accoverflow_if_clear <='1' when (output_clear /= "none") else '0';
signa_mac_reg : stratix_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_pipe,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear)) or not(devclrn) or not(devpor) ;
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratix_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_pipe,
async => signb_async);
clk_zeroacc <= clk(select_the(zeroacc_clock));
aclr_zeroacc <= aclr(select_the(zeroacc_clear)) or not(devclrn) or not(devpor);
ena_zeroacc <= ena(select_the(zeroacc_clock));
zeroacc_mac_reg : stratix_mac_bit_register
port map (data => zeroacc_tmp,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
ena => ena_zeroacc,
if_aclr => zeroacc_if_clear,
dataout => zeroacc_pipe,
async => zeroacc_async);
clk_addnsub0 <= clk(select_the(addnsub0_clock));
aclr_addnsub0 <= aclr(select_the(addnsub0_clear)) or not(devclrn) or not(devpor);
ena_addnsub0 <= ena(select_the(addnsub0_clock));
addnsub0_mac_reg : stratix_mac_bit_register
port map (data => addnsub0_tmp,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
ena => ena_addnsub0,
if_aclr => addnsub0_if_clear,
dataout => addnsub0_pipe,
async => addnsub0_async);
clk_addnsub1 <= clk(select_the(addnsub1_clock));
aclr_addnsub1 <= aclr(select_the(addnsub1_clear)) or not(devclrn) or not(devpor);
ena_addnsub1 <= ena(select_the(addnsub1_clock));
addnsub1_mac_reg : stratix_mac_bit_register
port map (data => addnsub1_tmp,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
ena => ena_addnsub1,
if_aclr => addnsub1_if_clear,
dataout => addnsub1_pipe,
async => addnsub1_async);
clk_signa_pipeline <= clk(select_the(signa_pipeline_clock));
aclr_signa_pipeline <= aclr(select_the(signa_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signa_pipeline <= ena(select_the(signa_pipeline_clock));
signa_mac_pipeline_reg : stratix_mac_bit_register
port map (data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
ena => ena_signa_pipeline,
if_aclr => signa_pip_if_clear,
dataout => signa_out,
async => signa_pipeline_async);
clk_signb_pipeline <= clk(select_the(signb_pipeline_clock));
aclr_signb_pipeline <= aclr(select_the(signb_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signb_pipeline <= ena(select_the(signb_pipeline_clock));
signb_mac_pipeline_reg : stratix_mac_bit_register
port map (data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
ena => ena_signb_pipeline,
if_aclr => signb_pip_if_clear,
dataout => signb_out,
async => signb_pipeline_async);
clk_zeroacc_pipeline <= clk(select_the(zeroacc_pipeline_clock));
aclr_zeroacc_pipeline <= aclr(select_the(zeroacc_pipeline_clear)) or not(devclrn) or not(devpor);
ena_zeroacc_pipeline <= ena(select_the(zeroacc_pipeline_clock));
zeroacc_mac_pipeline_reg : stratix_mac_bit_register
port map (data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
if_aclr => zeroacc_pip_if_clear,
dataout => zeroacc_out,
async => zeroacc_pipeline_async);
clk_addnsub0_pipeline <= clk(select_the(addnsub0_pipeline_clock));
aclr_addnsub0_pipeline <= aclr(select_the(addnsub0_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub0_pipeline <= ena(select_the(addnsub0_pipeline_clock));
addnsub0_mac_pipeline_reg : stratix_mac_bit_register
port map (data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
if_aclr => addnsub0_pip_if_clear,
dataout => addnsub0_out,
async => addnsub0_pipeline_async);
clk_addnsub1_pipeline <= clk(select_the(addnsub1_pipeline_clock));
aclr_addnsub1_pipeline <= aclr(select_the(addnsub1_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub1_pipeline <= ena(select_the(addnsub1_pipeline_clock));
addnsub1_mac_pipeline_reg : stratix_mac_bit_register
port map (data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
if_aclr => addnsub1_pip_if_clear,
dataout => addnsub1_out,
async => addnsub1_pipeline_async);
mac_adder : stratix_mac_out_internal
generic map (operation_mode => operation_mode,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
signa_clock => signa_clock,
signb_clock => signb_clock,
signa_clear => signa_clear,
signb_clear => signb_clear,
output_clock => output_clock,
output_clear => output_clear)
port map (dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
dataout_global => dataout_tmp(dataout_width-1 downto 0),
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
zeroacc => zeroacc_out,
dataout => dataout_sig,
accoverflow => accoverflow_sig
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_out_reg : stratix_mac_register
generic map (data_width => 72)
port map (data => dataout_sig,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
clk_accoverflow <= clk(select_the(output_clock));
aclr_accoverflow <=aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_accoverflow <= ena(select_the(output_clock));
accoverflow_out_reg : stratix_mac_bit_register
port map (data => accoverflow_sig,
clk => clk_accoverflow,
aclr => aclr_accoverflow,
ena => ena_accoverflow,
if_aclr => accoverflow_if_clear,
dataout => accoverflow_tmp,
async => accoverflow_async);
dataout <= dataout_tmp(dataout'range) xor data_out_programmable_invert(dataout'range);
accoverflow <= accoverflow_tmp xor overflow_programmable_invert;
END out_arch;
----------------------------------------------------------------------------
-- Module Name : stratix_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratix_atom_pack.all;
ENTITY stratix_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratix_ram_register;
ARCHITECTURE reg_arch OF stratix_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratix_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratix_atom_pack.all;
ENTITY stratix_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratix_ram_pulse_generator:ENTITY IS TRUE;
END stratix_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratix_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratix_atom_pack.all;
USE work.stratix_ram_register;
USE work.stratix_ram_pulse_generator;
ENTITY stratix_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratix_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratix_ram_block;
ARCHITECTURE block_arch OF stratix_ram_block IS
COMPONENT stratix_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratix_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= ena0;
active_b_in <= ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratix_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratix_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratix_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratix_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratix_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratix_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratix_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratix_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratix_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratix_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratix_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratix_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratix_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratix_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratix_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratix_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratix_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratix_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_LVDS_TX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- of STRATIX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use std.textio.all;
ENTITY stratix_lvds_tx_parallel_register is
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratix_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratix_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIX_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_LVDS_TX_OUT_BLOCK
--
-- Description : Timing simulation model for output block submodule
-- of STRATIX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use std.textio.all;
use work.stratix_lvds_tx_parallel_register;
use work.stratix_dffe;
ENTITY stratix_lvds_tx_out_block is
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratix_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratix_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_LVDS_TRANSMITTER
--
-- Description : Timing simulation model for STRATIX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use std.textio.all;
use work.stratix_lvds_tx_out_block;
ENTITY stratix_lvds_transmitter is
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratix_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratix_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratix_lvds_transmitter is
signal clk0_ipd : std_logic;
signal not_clk0 : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal txload1 : std_logic;
signal txload2 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly5 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
COMPONENT stratix_lvds_tx_parallel_register
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratix_lvds_tx_out_block
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end COMPONENT;
COMPONENT stratix_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01
);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
end block;
txload0_reg: stratix_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly2,
Q => txload0);
txload1_reg: stratix_dffe
PORT map(D => txload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly1,
Q => txload1);
not_clk0 <= not clk0_dly0;
txload2_reg: stratix_dffe
PORT map(D => txload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => txload2);
input_reg: stratix_lvds_tx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor);
output_module: stratix_lvds_tx_out_block
GENERIC map(bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT map(clk => clk0_dly2,
datain => shift_out,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly5 <= datain_dly4;
end process;
data_delay2: process (datain_dly5)
begin
datain_dly <= datain_dly5;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable i : integer := 0;
variable dataout_tmp : std_logic;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload2 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
end vital_transmitter_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_LVDS_RX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- of STRATIX_LVDS_RX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use std.textio.all;
ENTITY stratix_lvds_rx_parallel_register is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratix_lvds_rx_parallel_register;
ARCHITECTURE vital_rx_reg of stratix_lvds_rx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
end block;
VITAL: process (clk_ipd, enable_ipd, devpor, devclrn)
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_rx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIX_LVDS_RECEIVER
--
-- Description : Timing simulation model for STRATIX_LVDS_RX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
use std.textio.all;
use work.stratix_lvds_rx_parallel_register;
use work.stratix_dffe;
use work.stratix_and1;
ENTITY stratix_lvds_receiver is
GENERIC (
channel_width : integer := 1;
use_enable1 : String := "false";
lpm_type : string := "stratix_lvds_receiver";
InstancePath : String := "*"
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratix_lvds_receiver;
ARCHITECTURE vital_receiver_atom of stratix_lvds_receiver is
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal not_clk0 : std_logic;
signal txload_in : std_logic;
signal rxload0 : std_logic;
signal rxload1 : std_logic;
signal rxload2 : std_logic;
signal shift_data : std_logic_vector(channel_width - 1 downto 0);
signal load_data : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
COMPONENT stratix_lvds_rx_parallel_register
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratix_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01
);
PORT (
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
COMPONENT stratix_and1
GENERIC (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
begin
clkdelaybuffer: stratix_and1
PORT map(IN1 => clk0,
Y => clk0_ipd);
dataindelaybuffer: stratix_and1
PORT map(IN1 => datain,
Y => datain_ipd);
rxload0_reg: stratix_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload0);
rxload1_reg: stratix_dffe
PORT map(D => rxload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload1);
not_clk0 <= not clk0;
rxload2_reg: stratix_dffe
PORT map(D => rxload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => rxload2);
txload_in <= enable1 when use_enable1 = "true" else
enable0;
load_reg: stratix_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => not_clk0,
enable => rxload2,
datain => shift_data,
dataout => load_data,
devclrn => devclrn,
devpor => devpor);
output_reg: stratix_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => clk0,
enable => txload_in,
datain => load_data,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
VITAL: process (clk0_ipd, devpor, devclrn)
variable i : integer := 0;
begin
if (now = 0 ns) then
shift_data <= (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
for i in channel_width-1 downto 0 loop
shift_data(i) <= '0';
end loop;
else
if (clk0_ipd'event and clk0_ipd = '0') then
for i in channel_width-1 downto 1 loop
shift_data(i) <= shift_data(i-1);
end loop;
shift_data(0) <= datain_ipd;
end if;
end if;
end process;
end vital_receiver_atom;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_m_cntr
--
-- Description : Timing simulation model for the M counter. This is a
-- model for the loop feedback counter of the Stratix PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratix_m_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0);
END stratix_m_cntr;
ARCHITECTURE behave of stratix_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_n_cntr
--
-- Description : Timing simulation model for the N counter. This is a
-- model for the input counter of the Stratix PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratix_n_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END stratix_n_cntr;
ARCHITECTURE behave of stratix_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on Stratix PLL input clk. This edge will be ignored" severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge and (clk_last_valid_value /= clk)) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the L0, L1, G0, G1, G2, G3, E0,
-- E1, E2 and E3 output counters of the Stratix PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratix_scale_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
initial : IN integer;
high : IN integer;
low : IN integer;
mode : IN string := "bypass";
time_delay : IN integer;
ph_tap : IN natural;
cout : OUT std_logic);
END stratix_scale_cntr;
ARCHITECTURE behave of stratix_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 0;
variable first_rising_edge : boolean := false;
variable high_reg : integer := 0;
variable low_reg : integer := 0;
variable init : boolean := true;
variable high_cnt_xfer_done : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 0;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (init) then
init := false;
high_reg := high;
low_reg := low;
end if;
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
elsif (not first_rising_edge) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high_reg*2) + 1)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (mode = " odd" and (count = high_reg*2)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (count = (high_reg + low_reg)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
if (high_reg /= high) then
high_cnt_xfer_done := true;
high_reg := high;
end if;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratix_pll_reg is
PORT ( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic);
end stratix_pll_reg;
ARCHITECTURE behave of stratix_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_pll
--
-- Description : Timing simulation model for the Stratix StratixGX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratix_atom_pack.all;
USE work.stratix_pllpack.all;
USE work.stratix_m_cntr;
USE work.stratix_n_cntr;
USE work.stratix_scale_cntr;
USE work.stratix_dffe;
USE work.stratix_pll_reg;
ENTITY stratix_pll is
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratix_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
-- LVDS mode parameters
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
-- Simulation only generics
family_name : string := "Stratix";
skip_vco : string := "off";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
-- lvds specific ports
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END stratix_pll;
ARCHITECTURE vital_pll of stratix_pll is
-- internal advanced parameter signals
signal i_vco_min : natural;
signal i_vco_max : natural;
signal i_vco_center : natural;
signal i_pfd_min : natural;
signal i_pfd_max : natural;
signal l0_ph_val : natural;
signal l1_ph_val : natural;
signal g0_ph_val : natural;
signal g1_ph_val : natural;
signal g2_ph_val : natural;
signal g3_ph_val : natural;
signal e0_ph_val : natural;
signal e1_ph_val : natural;
signal e2_ph_val : natural;
signal e3_ph_val : natural;
signal i_extclk3_counter : string(1 to 2) := "e3";
signal i_extclk2_counter : string(1 to 2) := "e2";
signal i_extclk1_counter : string(1 to 2) := "e1";
signal i_extclk0_counter : string(1 to 2) := "e0";
signal i_clk5_counter : string(1 to 2) := "l1";
signal i_clk4_counter : string(1 to 2) := "l0";
signal i_clk3_counter : string(1 to 2) := "g3";
signal i_clk2_counter : string(1 to 2) := "g2";
signal i_clk1_counter : string(1 to 2) := "g1";
signal i_clk0_counter : string(1 to 2) := "g0";
signal i_charge_pump_current : natural;
signal i_loop_filter_r : natural;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT EGPP_SCAN_CHAIN : integer := 289;
CONSTANT GPP_SCAN_CHAIN : integer := 193;
CONSTANT TRST : time := 5000 ps;
CONSTANT TRSTCLK : time := 5000 ps;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal l0_clk : std_logic;
signal l1_clk : std_logic;
signal g0_clk : std_logic;
signal g1_clk : std_logic;
signal g2_clk : std_logic;
signal g3_clk : std_logic;
signal e0_clk : std_logic;
signal e1_clk : std_logic;
signal e2_clk : std_logic;
signal e3_clk : std_logic;
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal m_val_tmp : integer := 1;
signal m2_val : integer := 1;
signal n_val : integer := 1;
signal n_val_tmp : integer := 1;
signal n2_val : integer := 1;
signal m_time_delay_val, n_time_delay_val : integer := 0;
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal l0_initial_val : integer := l0_initial;
signal l1_initial_val : integer := l1_initial;
signal l0_high_val : integer := l0_high;
signal l1_high_val : integer := l1_high;
signal l0_low_val : integer := l0_low;
signal l1_low_val : integer := l1_low;
signal l0_mode_val : string(1 to 6) := "bypass";
signal l1_mode_val : string(1 to 6) := "bypass";
signal l0_time_delay_val : integer := l0_time_delay;
signal l1_time_delay_val : integer := l1_time_delay;
signal g0_initial_val : integer := g0_initial;
signal g1_initial_val : integer := g1_initial;
signal g2_initial_val : integer := g2_initial;
signal g3_initial_val : integer := g3_initial;
signal g0_high_val : integer := g0_high;
signal g1_high_val : integer := g1_high;
signal g2_high_val : integer := g2_high;
signal g3_high_val : integer := g3_high;
signal g0_mode_val : string(1 to 6) := "bypass";
signal g1_mode_val : string(1 to 6) := "bypass";
signal g2_mode_val : string(1 to 6) := "bypass";
signal g3_mode_val : string(1 to 6) := "bypass";
signal g0_low_val : integer := g0_low;
signal g1_low_val : integer := g1_low;
signal g2_low_val : integer := g2_low;
signal g3_low_val : integer := g3_low;
signal g0_time_delay_val : integer := g0_time_delay;
signal g1_time_delay_val : integer := g1_time_delay;
signal g2_time_delay_val : integer := g2_time_delay;
signal g3_time_delay_val : integer := g3_time_delay;
signal e0_initial_val : integer := e0_initial;
signal e1_initial_val : integer := e1_initial;
signal e2_initial_val : integer := e2_initial;
signal e3_initial_val : integer := e3_initial;
signal e0_high_val : integer := e0_high;
signal e1_high_val : integer := e1_high;
signal e2_high_val : integer := e2_high;
signal e3_high_val : integer := e3_high;
signal e0_low_val : integer := e0_low;
signal e1_low_val : integer := e1_low;
signal e2_low_val : integer := e2_low;
signal e3_low_val : integer := e3_low;
signal e0_time_delay_val : integer := e0_time_delay;
signal e1_time_delay_val : integer := e1_time_delay;
signal e2_time_delay_val : integer := e2_time_delay;
signal e3_time_delay_val : integer := e3_time_delay;
signal e0_mode_val : string(1 to 6) := "bypass";
signal e1_mode_val : string(1 to 6) := "bypass";
signal e2_mode_val : string(1 to 6) := "bypass";
signal e3_mode_val : string(1 to 6) := "bypass";
signal m_mode_val : string(1 to 6) := " ";
signal m2_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal n2_mode_val : string(1 to 6) := " ";
signal cntr_e0_initial : integer := 1;
signal cntr_e1_initial : integer := 1;
signal cntr_e2_initial : integer := 1;
signal cntr_e3_initial : integer := 1;
signal ext_fbk_delay : integer := 0;
signal cntr_e0_delay : integer := 0;
signal cntr_e1_delay : integer := 0;
signal cntr_e2_delay : integer := 0;
signal cntr_e3_delay : integer := 0;
signal transfer : std_logic := '0';
signal scan_data : std_logic_vector(288 downto 0) := (OTHERS => '0');
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
signal ena4 : std_logic;
signal ena5 : std_logic;
signal extena0 : std_logic;
signal extena1 : std_logic;
signal extena2 : std_logic;
signal extena3 : std_logic;
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal extclk0_tmp : std_logic;
signal extclk1_tmp : std_logic;
signal extclk2_tmp : std_logic;
signal extclk3_tmp : std_logic;
signal not_clk0_tmp : std_logic;
signal not_clk1_tmp : std_logic;
signal not_clk2_tmp : std_logic;
signal not_clk3_tmp : std_logic;
signal not_clk4_tmp : std_logic;
signal not_clk5_tmp : std_logic;
signal not_extclk0_tmp : std_logic;
signal not_extclk1_tmp : std_logic;
signal not_extclk2_tmp : std_logic;
signal not_extclk3_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal quiet_period_violation : boolean := false;
signal reconfig_err : boolean := false;
signal scanclr_violation : boolean := false;
signal scanclr_clk_violation : boolean := false;
signal inclk_l0 : std_logic;
signal inclk_l1 : std_logic;
signal inclk_g0 : std_logic;
signal inclk_g1 : std_logic;
signal inclk_g2 : std_logic;
signal inclk_g3 : std_logic;
signal inclk_e0 : std_logic;
signal inclk_e1 : std_logic;
signal inclk_e2 : std_logic;
signal inclk_e3 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal comparator_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal clkena0_ipd : std_logic;
signal clkena1_ipd : std_logic;
signal clkena2_ipd : std_logic;
signal clkena3_ipd : std_logic;
signal clkena4_ipd : std_logic;
signal clkena5_ipd : std_logic;
signal extclkena0_ipd : std_logic;
signal extclkena1_ipd : std_logic;
signal extclkena2_ipd : std_logic;
signal extclkena3_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanaclr_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal lvds_dffa_clk : std_logic;
signal lvds_dffb_clk : std_logic;
signal lvds_dffc_clk : std_logic;
signal lvds_dffd_clk : std_logic;
signal dffa_out : std_logic := '0';
signal dffb_out : std_logic := '0';
signal dffc_out : std_logic := '0';
signal dffd_out : std_logic := '0';
signal nce_temp : std_logic := '0';
signal nce_l0 : std_logic := '0';
signal nce_l1 : std_logic := '0';
signal inclk_l0_dly1 : std_logic := '0';
signal inclk_l0_dly2 : std_logic := '0';
signal inclk_l0_dly3 : std_logic := '0';
signal inclk_l0_dly4 : std_logic := '0';
signal inclk_l0_dly5 : std_logic := '0';
signal inclk_l0_dly6 : std_logic := '0';
signal inclk_l1_dly1 : std_logic := '0';
signal inclk_l1_dly2 : std_logic := '0';
signal inclk_l1_dly3 : std_logic := '0';
signal inclk_l1_dly4 : std_logic := '0';
signal inclk_l1_dly5 : std_logic := '0';
signal inclk_l1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal sig_current_clock : string(1 to 6);
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal sig_curr_clock : string(1 to 6) := primary_clock;
signal scan_chain_length : integer := GPP_SCAN_CHAIN;
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_delay : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "e0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal sdataout_trig : std_logic := '0';
signal sdataout_rst_trig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal done_with_param_calc : boolean := false;
COMPONENT stratix_m_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0 );
END COMPONENT;
COMPONENT stratix_n_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END COMPONENT;
COMPONENT stratix_scale_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
time_delay : IN integer := 0;
ph_tap : IN natural );
END COMPONENT;
COMPONENT stratix_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratix_pll_reg
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (clkena0_ipd, clkena(0), tipd_clkena(0));
VitalWireDelay (clkena1_ipd, clkena(1), tipd_clkena(1));
VitalWireDelay (clkena2_ipd, clkena(2), tipd_clkena(2));
VitalWireDelay (clkena3_ipd, clkena(3), tipd_clkena(3));
VitalWireDelay (clkena4_ipd, clkena(4), tipd_clkena(4));
VitalWireDelay (clkena5_ipd, clkena(5), tipd_clkena(5));
VitalWireDelay (extclkena0_ipd, extclkena(0), tipd_extclkena(0));
VitalWireDelay (extclkena1_ipd, extclkena(1), tipd_extclkena(1));
VitalWireDelay (extclkena2_ipd, extclkena(2), tipd_extclkena(2));
VitalWireDelay (extclkena3_ipd, extclkena(3), tipd_extclkena(3));
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanaclr_ipd, scanaclr, tipd_scanaclr);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (comparator_ipd, comparator, tipd_comparator);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
-- User to Advanced parameter conversion
i_extclk3_counter <= "e3" when m=0 else extclk3_counter;
i_extclk2_counter <= "e2" when m=0 else extclk2_counter;
i_extclk1_counter <= "e1" when m=0 else extclk1_counter;
i_extclk0_counter <= "e0" when m=0 else extclk0_counter;
i_clk5_counter <= "l1" when m=0 else clk5_counter;
i_clk4_counter <= "l0" when m=0 else clk4_counter;
i_clk3_counter <= "g3" when m=0 else clk3_counter;
i_clk2_counter <= "g2" when m=0 else clk2_counter;
i_clk1_counter <= "g1" when m=0 else clk1_counter;
i_clk0_counter <= "l0" when m=0 and pll_type = "lvds" else
"g0" when m=0 else clk0_counter;
-- end parameter conversion
inclk_m <= extclk0_tmp when operation_mode = "external_feedback" and feedback_source = "extclk0" else
extclk1_tmp when operation_mode = "external_feedback" and feedback_source = "extclk1" else
extclk2_tmp when operation_mode = "external_feedback" and feedback_source = "extclk2" else
extclk3_tmp when operation_mode = "external_feedback" and feedback_source = "extclk3" else
vco_out(m_ph_val);
ext_fbk_cntr <= "e0" when (feedback_source = "extclk0" and extclk0_counter = "e0") or (feedback_source = "extclk1" and extclk1_counter = "e0") or (feedback_source = "extclk2" and extclk2_counter = "e0") or (feedback_source = "extclk3" and extclk3_counter = "e0") else
"e1" when (feedback_source = "extclk0" and extclk0_counter = "e1") or (feedback_source = "extclk1" and extclk1_counter = "e1") or (feedback_source = "extclk2" and extclk2_counter = "e1") or (feedback_source = "extclk3" and extclk3_counter = "e1") else
"e2" when (feedback_source = "extclk0" and extclk0_counter = "e2") or (feedback_source = "extclk1" and extclk1_counter = "e2") or (feedback_source = "extclk2" and extclk2_counter = "e2") or (feedback_source = "extclk3" and extclk3_counter = "e2") else
"e3" when (feedback_source = "extclk0" and extclk0_counter = "e3") or (feedback_source = "extclk1" and extclk1_counter = "e3") or (feedback_source = "extclk2" and extclk2_counter = "e3") or (feedback_source = "extclk3" and extclk3_counter = "e3") else
"e0";
ext_fbk_cntr_high <= e0_high_val when ext_fbk_cntr = "e0" else
e1_high_val when ext_fbk_cntr = "e1" else
e2_high_val when ext_fbk_cntr = "e2" else
e3_high_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_low <= e0_low_val when ext_fbk_cntr = "e0" else
e1_low_val when ext_fbk_cntr = "e1" else
e2_low_val when ext_fbk_cntr = "e2" else
e3_low_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_delay <= e0_time_delay_val when ext_fbk_cntr = "e0" else
e1_time_delay_val when ext_fbk_cntr = "e1" else
e2_time_delay_val when ext_fbk_cntr = "e2" else
e3_time_delay_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_ph <= e0_ph_val when ext_fbk_cntr = "e0" else
e1_ph_val when ext_fbk_cntr = "e1" else
e2_ph_val when ext_fbk_cntr = "e2" else
e3_ph_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_initial <= e0_initial_val when ext_fbk_cntr = "e0" else
e1_initial_val when ext_fbk_cntr = "e1" else
e2_initial_val when ext_fbk_cntr = "e2" else
e3_initial_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_mode <= e0_mode_val when ext_fbk_cntr = "e0" else
e1_mode_val when ext_fbk_cntr = "e1" else
e2_mode_val when ext_fbk_cntr = "e2" else
e3_mode_val when ext_fbk_cntr = "e3" else
e0_mode_val;
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
m1 : stratix_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay,
ph => m_ph_val );
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
n1 : stratix_n_cntr
port map ( clk => clkin,
reset => areset_ipd,
cout => refclk,
modulus => n_val,
time_delay => n_time_delay_val);
inclk_l0 <= vco_out(l0_ph_val);
l0 : stratix_scale_cntr
port map ( clk => inclk_l0,
reset => areset_ena_sig,
cout => l0_clk,
initial => l0_initial_val,
high => l0_high_val,
low => l0_low_val,
mode => l0_mode_val,
time_delay => l0_time_delay_val,
ph_tap => l0_ph_val);
inclk_l1 <= vco_out(l1_ph_val);
l1 : stratix_scale_cntr
port map ( clk => inclk_l1,
reset => areset_ena_sig,
cout => l1_clk,
initial => l1_initial_val,
high => l1_high_val,
low => l1_low_val,
mode => l1_mode_val,
time_delay => l1_time_delay_val,
ph_tap => l1_ph_val);
inclk_g0 <= vco_out(g0_ph_val);
g0 : stratix_scale_cntr
port map ( clk => inclk_g0,
reset => areset_ena_sig,
cout => g0_clk,
initial => g0_initial_val,
high => g0_high_val,
low => g0_low_val,
mode => g0_mode_val,
time_delay => g0_time_delay_val,
ph_tap => g0_ph_val);
process(g0_clk, l0_clk, l1_clk)
begin
if (g0_clk'event and g0_clk = '1') then
dffa_out <= comparator_ipd;
end if;
if (l0_clk'event and l0_clk = '1' and enable0_counter = "l0") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
if (l1_clk'event and l1_clk = '1' and enable0_counter = "l1") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
end process;
nce_temp <= (not dffc_out) and dffb_out;
nce_l0 <= dffd_out when enable0_counter = "l0" else '0';
nce_l1 <= dffd_out when enable0_counter = "l1" else '0';
inclk_g1 <= vco_out(g1_ph_val);
g1 : stratix_scale_cntr
port map ( clk => inclk_g1,
reset => areset_ena_sig,
cout => g1_clk,
initial => g1_initial_val,
high => g1_high_val,
low => g1_low_val,
mode => g1_mode_val,
time_delay => g1_time_delay_val,
ph_tap => g1_ph_val);
inclk_g2 <= vco_out(g2_ph_val);
g2 : stratix_scale_cntr
port map ( clk => inclk_g2,
reset => areset_ena_sig,
cout => g2_clk,
initial => g2_initial_val,
high => g2_high_val,
low => g2_low_val,
mode => g2_mode_val,
time_delay => g2_time_delay_val,
ph_tap => g2_ph_val);
inclk_g3 <= vco_out(g3_ph_val);
g3 : stratix_scale_cntr
port map ( clk => inclk_g3,
reset => areset_ena_sig,
cout => g3_clk,
initial => g3_initial_val,
high => g3_high_val,
low => g3_low_val,
mode => g3_mode_val,
time_delay => g3_time_delay_val,
ph_tap => g3_ph_val);
inclk_e0 <= vco_out(e0_ph_val);
cntr_e0_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else e0_initial_val;
cntr_e0_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else
e0_time_delay_val;
e0 : stratix_scale_cntr
port map ( clk => inclk_e0,
reset => areset_ena_sig,
cout => e0_clk,
initial => cntr_e0_initial,
high => e0_high_val,
low => e0_low_val,
mode => e0_mode_val,
time_delay => cntr_e0_delay,
ph_tap => e0_ph_val);
inclk_e1 <= vco_out(e1_ph_val);
cntr_e1_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else e1_initial_val;
cntr_e1_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else
e1_time_delay_val;
e1 : stratix_scale_cntr
port map ( clk => inclk_e1,
reset => areset_ena_sig,
cout => e1_clk,
initial => cntr_e1_initial,
high => e1_high_val,
low => e1_low_val,
mode => e1_mode_val,
time_delay => cntr_e1_delay,
ph_tap => e1_ph_val);
inclk_e2 <= vco_out(e2_ph_val);
cntr_e2_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else e2_initial_val;
cntr_e2_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else
e2_time_delay_val;
e2 : stratix_scale_cntr
port map ( clk => inclk_e2,
reset => areset_ena_sig,
cout => e2_clk,
initial => cntr_e2_initial,
high => e2_high_val,
low => e2_low_val,
mode => e2_mode_val,
time_delay => cntr_e2_delay,
ph_tap => e2_ph_val);
inclk_e3 <= vco_out(e3_ph_val);
cntr_e3_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else e3_initial_val;
cntr_e3_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else
e3_time_delay_val;
e3 : stratix_scale_cntr
port map ( clk => inclk_e3,
reset => areset_ena_sig,
cout => e3_clk,
initial => cntr_e3_initial,
high => e3_high_val,
low => e3_low_val,
mode => e3_mode_val,
time_delay => cntr_e3_delay,
ph_tap => e3_ph_val);
inclk_l0_dly1 <= inclk_l0;
inclk_l0_dly2 <= inclk_l0_dly1;
inclk_l0_dly3 <= inclk_l0_dly2;
inclk_l0_dly4 <= inclk_l0_dly3;
inclk_l0_dly5 <= inclk_l0_dly4;
inclk_l0_dly6 <= inclk_l0_dly5;
inclk_l1_dly1 <= inclk_l1;
inclk_l1_dly2 <= inclk_l1_dly1;
inclk_l1_dly3 <= inclk_l1_dly2;
inclk_l1_dly4 <= inclk_l1_dly3;
inclk_l1_dly5 <= inclk_l1_dly4;
inclk_l1_dly6 <= inclk_l1_dly5;
process(inclk_l0_dly6, inclk_l1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable l0_got_first_rising_edge : boolean := false;
variable l0_count : integer := 1;
variable l0_tmp, l1_tmp : std_logic := '0';
variable l1_got_first_rising_edge : boolean := false;
variable l1_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
l0_count := 1;
l1_count := 1;
l0_got_first_rising_edge := false;
l1_got_first_rising_edge := false;
else
if (nce_l0 = '0') then
if (not l0_got_first_rising_edge) then
if (inclk_l0_dly6'event and inclk_l0_dly6 = '1') then
l0_got_first_rising_edge := true;
end if;
elsif (inclk_l0_dly6'event) then
l0_count := l0_count + 1;
if (l0_count = (l0_high_val + l0_low_val) * 2) then
l0_count := 1;
end if;
end if;
end if;
if (inclk_l0_dly6'event and inclk_l0_dly6 = '0') then
if (l0_count = 1) then
l0_tmp := '1';
l0_got_first_rising_edge := false;
else
l0_tmp := '0';
end if;
end if;
if (nce_l1 = '0') then
if (not l1_got_first_rising_edge) then
if (inclk_l1_dly6'event and inclk_l1_dly6 = '1') then
l1_got_first_rising_edge := true;
end if;
elsif (inclk_l1_dly6'event) then
l1_count := l1_count + 1;
if (l1_count = (l1_high_val + l1_low_val) * 2) then
l1_count := 1;
end if;
end if;
end if;
if (inclk_l1_dly6'event and inclk_l1_dly6 = '0') then
if (l1_count = 1) then
l1_tmp := '1';
l1_got_first_rising_edge := false;
else
l1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "l0") then
enable0_tmp <= l0_tmp;
elsif (enable0_counter = "l1") then
enable0_tmp <= l1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "l0") then
enable1_tmp <= l0_tmp;
elsif (enable1_counter = "l1") then
enable1_tmp <= l1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (count = gate_lock_counter) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (transfer)
variable init : boolean := true;
variable low, high : std_logic_vector(8 downto 0);
variable delay_chain : std_logic_vector(3 downto 0);
variable mn_delay_chain : std_logic_vector(0 to 3);
variable mode : string(1 to 6) := "bypass";
variable delay_val : integer := 0;
variable is_error : boolean := false;
variable buf : line;
-- user to advanced variables
variable i_m_initial : natural;
variable i_m : integer := 1;
variable i_n : natural := 1;
variable i_m2 : natural;
variable i_n2 : natural;
variable i_ss : natural;
variable i_l0_high : natural;
variable i_l1_high : natural;
variable i_g0_high : natural;
variable i_g1_high : natural;
variable i_g2_high : natural;
variable i_g3_high : natural;
variable i_e0_high : natural;
variable i_e1_high : natural;
variable i_e2_high : natural;
variable i_e3_high : natural;
variable i_l0_low : natural;
variable i_l1_low : natural;
variable i_g0_low : natural;
variable i_g1_low : natural;
variable i_g2_low : natural;
variable i_g3_low : natural;
variable i_e0_low : natural;
variable i_e1_low : natural;
variable i_e2_low : natural;
variable i_e3_low : natural;
variable i_l0_initial : natural;
variable i_l1_initial : natural;
variable i_g0_initial : natural;
variable i_g1_initial : natural;
variable i_g2_initial : natural;
variable i_g3_initial : natural;
variable i_e0_initial : natural;
variable i_e1_initial : natural;
variable i_e2_initial : natural;
variable i_e3_initial : natural;
variable i_l0_mode : string(1 to 6);
variable i_l1_mode : string(1 to 6);
variable i_g0_mode : string(1 to 6);
variable i_g1_mode : string(1 to 6);
variable i_g2_mode : string(1 to 6);
variable i_g3_mode : string(1 to 6);
variable i_e0_mode : string(1 to 6);
variable i_e1_mode : string(1 to 6);
variable i_e2_mode : string(1 to 6);
variable i_e3_mode : string(1 to 6);
variable max_neg_abs : integer := 0;
variable i_l0_time_delay : natural;
variable i_l1_time_delay : natural;
variable i_g0_time_delay : natural;
variable i_g1_time_delay : natural;
variable i_g2_time_delay : natural;
variable i_g3_time_delay : natural;
variable i_e0_time_delay : natural;
variable i_e1_time_delay : natural;
variable i_e2_time_delay : natural;
variable i_e3_time_delay : natural;
variable i_m_time_delay : natural;
variable i_n_time_delay : natural;
variable i_l0_ph : natural;
variable i_l1_ph : natural;
variable i_g0_ph : natural;
variable i_g1_ph : natural;
variable i_g2_ph : natural;
variable i_g3_ph : natural;
variable i_e0_ph : natural;
variable i_e1_ph : natural;
variable i_e2_ph : natural;
variable i_e3_ph : natural;
variable i_m_ph : natural;
variable output_count : natural;
variable new_divisor : natural;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_extclk0_mult_by : integer := 1;
variable i_extclk0_div_by : integer := 1;
variable i_extclk1_mult_by : integer := 1;
variable i_extclk1_div_by : integer := 1;
variable i_extclk2_mult_by : integer := 1;
variable i_extclk2_div_by : integer := 1;
variable i_extclk3_mult_by : integer := 1;
variable i_extclk3_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
begin
if (init) then
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
i_n := 1;
if (pll_type = "lvds") then
i_m := clk0_multiply_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
end if;
i_m_time_delay := maxnegabs ( str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay := mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (pll_type = "lvds") then
i_g0_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
else
i_g0_time_delay := counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,i_n_time_delay);
end if;
i_g1_time_delay := counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_g2_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_g3_time_delay := counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "lvds") then
i_l0_time_delay := i_g0_time_delay;
i_l1_time_delay := i_g0_time_delay;
else
i_l0_time_delay := counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay, i_n_time_delay);
i_l1_time_delay := counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay, i_n_time_delay);
end if;
i_e0_time_delay := counter_time_delay ( str2int(extclk0_time_delay),
i_m_time_delay, i_n_time_delay);
i_e1_time_delay := counter_time_delay ( str2int(extclk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_e2_time_delay := counter_time_delay ( str2int(extclk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_e3_time_delay := counter_time_delay ( str2int(extclk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
else
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_g1_ph := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g2_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_ph := i_g0_ph;
i_l1_ph := i_g0_ph;
else
i_l0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_l1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_e0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e2_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high := counter_high ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_high := counter_high ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high := counter_high ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_high := i_g0_high;
i_l1_high := i_g0_high;
else
i_l0_high := counter_high ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high := counter_high ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_high := counter_high ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high := counter_high ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high := counter_high ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high := counter_high ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (pll_type = "lvds") then
i_g0_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low := counter_low ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_low := counter_low ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low := counter_low ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_low := i_g0_low;
i_l1_low := i_g0_low;
else
i_l0_low := counter_low ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low := counter_low ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_low := counter_low ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low := counter_low ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low := counter_low ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low := counter_low ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
if (pll_type = "lvds") then
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
else
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_g1_initial := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g2_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_initial := i_g0_initial;
i_l1_initial := i_g0_initial;
else
i_l0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_l1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_e0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e2_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
end if;
i_g1_mode := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (pll_type = "lvds") then
i_l0_mode := "bypass";
i_l1_mode := "bypass";
else
i_l0_mode := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end if;
i_e0_mode := counter_mode(extclk0_duty_cycle, output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode := counter_mode(extclk1_duty_cycle, output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode := counter_mode(extclk2_duty_cycle, output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode := counter_mode(extclk3_duty_cycle, output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (feedback_source = "extclk0") then
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
elsif (feedback_source = "extclk1") then
if (i_e1_mode = "bypass") then
output_count := 1;
else
output_count := i_e1_high + i_e1_low;
end if;
elsif (feedback_source = "extclk2") then
if (i_e2_mode = "bypass") then
output_count := 1;
else
output_count := i_e2_high + i_e2_low;
end if;
elsif (feedback_source = "extclk3") then
if (i_e3_mode = "bypass") then
output_count := 1;
else
output_count := i_e3_high + i_e3_low;
end if;
else -- default to e0
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_time_delay := m_time_delay;
i_n_time_delay := n_time_delay;
i_l0_time_delay := l0_time_delay;
i_l1_time_delay := l1_time_delay;
i_g0_time_delay := g0_time_delay;
i_g1_time_delay := g1_time_delay;
i_g2_time_delay := g2_time_delay;
i_g3_time_delay := g3_time_delay;
i_e0_time_delay := e0_time_delay;
i_e1_time_delay := e1_time_delay;
i_e2_time_delay := e2_time_delay;
i_e3_time_delay := e3_time_delay;
i_m_ph := m_ph;
i_l0_ph := l0_ph;
i_l1_ph := l1_ph;
i_g0_ph := g0_ph;
i_g1_ph := g1_ph;
i_g2_ph := g2_ph;
i_g3_ph := g3_ph;
i_e0_ph := e0_ph;
i_e1_ph := e1_ph;
i_e2_ph := e2_ph;
i_e3_ph := e3_ph;
i_l0_high := l0_high;
i_l1_high := l1_high;
i_g0_high := g0_high;
i_g1_high := g1_high;
i_g2_high := g2_high;
i_g3_high := g3_high;
i_e0_high := e0_high;
i_e1_high := e1_high;
i_e2_high := e2_high;
i_e3_high := e3_high;
i_l0_low := l0_low;
i_l1_low := l1_low;
i_g0_low := g0_low;
i_g1_low := g1_low;
i_g2_low := g2_low;
i_g3_low := g3_low;
i_e0_low := e0_low;
i_e1_low := e1_low;
i_e2_low := e2_low;
i_e3_low := e3_low;
i_l0_initial := l0_initial;
i_l1_initial := l1_initial;
i_g0_initial := g0_initial;
i_g1_initial := g1_initial;
i_g2_initial := g2_initial;
i_g3_initial := g3_initial;
i_e0_initial := e0_initial;
i_e1_initial := e1_initial;
i_e2_initial := e2_initial;
i_e3_initial := e3_initial;
i_l0_mode := translate_string(l0_mode);
i_l1_mode := translate_string(l1_mode);
i_g0_mode := translate_string(g0_mode);
i_g1_mode := translate_string(g1_mode);
i_g2_mode := translate_string(g2_mode);
i_g3_mode := translate_string(g3_mode);
i_e0_mode := translate_string(e0_mode);
i_e1_mode := translate_string(e1_mode);
i_e2_mode := translate_string(e2_mode);
i_e3_mode := translate_string(e3_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val_tmp <= i_n;
m_val_tmp <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
end if;
-- NOTE: m_time_delay (vco time delay) not supported for external
-- feedback mode
-- in feedback mode, m_time_delay = delay of feedback loop tap
m_time_delay_val <= i_m_time_delay;
n_time_delay_val <= i_n_time_delay;
m_ph_val <= i_m_ph;
m2_val <= m2;
n2_val <= n2;
if (m2 = 1) then
m2_mode_val <= "bypass";
end if;
if (n2 = 1) then
n2_mode_val <= "bypass";
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
m_initial_val <= 1;
m_time_delay_val <= 0;
m_ph_val <= 0;
end if;
l0_ph_val <= i_l0_ph;
l1_ph_val <= i_l1_ph;
g0_ph_val <= i_g0_ph;
g1_ph_val <= i_g1_ph;
g2_ph_val <= i_g2_ph;
g3_ph_val <= i_g3_ph;
e0_ph_val <= i_e0_ph;
e1_ph_val <= i_e1_ph;
e2_ph_val <= i_e2_ph;
e3_ph_val <= i_e3_ph;
l0_initial_val <= i_l0_initial;
l0_high_val <= i_l0_high;
l0_low_val <= i_l0_low;
l0_mode_val <= i_l0_mode;
l0_time_delay_val <= i_l0_time_delay;
l1_initial_val <= i_l1_initial;
l1_high_val <= i_l1_high;
l1_low_val <= i_l1_low;
l1_mode_val <= i_l1_mode;
l1_time_delay_val <= i_l1_time_delay;
g0_initial_val <= i_g0_initial;
g0_high_val <= i_g0_high;
g0_low_val <= i_g0_low;
g0_mode_val <= i_g0_mode;
g0_time_delay_val <= i_g0_time_delay;
g1_initial_val <= i_g1_initial;
g1_high_val <= i_g1_high;
g1_low_val <= i_g1_low;
g1_mode_val <= i_g1_mode;
g1_time_delay_val <= i_g1_time_delay;
g2_initial_val <= i_g2_initial;
g2_high_val <= i_g2_high;
g2_low_val <= i_g2_low;
g2_mode_val <= i_g2_mode;
g2_time_delay_val <= i_g2_time_delay;
g3_initial_val <= i_g3_initial;
g3_high_val <= i_g3_high;
g3_low_val <= i_g3_low;
g3_mode_val <= i_g3_mode;
g3_time_delay_val <= i_g3_time_delay;
if (scan_chain = "long") then
e0_initial_val <= i_e0_initial;
e0_high_val <= i_e0_high;
e0_low_val <= i_e0_low;
e0_mode_val <= i_e0_mode;
e0_time_delay_val <= i_e0_time_delay;
e1_initial_val <= i_e1_initial;
e1_high_val <= i_e1_high;
e1_low_val <= i_e1_low;
e1_mode_val <= i_e1_mode;
e1_time_delay_val <= i_e1_time_delay;
e2_initial_val <= i_e2_initial;
e2_high_val <= i_e2_high;
e2_low_val <= i_e2_low;
e2_mode_val <= i_e2_mode;
e2_time_delay_val <= i_e2_time_delay;
e3_initial_val <= i_e3_initial;
e3_high_val <= i_e3_high;
e3_low_val <= i_e3_low;
e3_mode_val <= i_e3_mode;
e3_time_delay_val <= i_e3_time_delay;
scan_chain_length <= EGPP_SCAN_CHAIN;
end if;
init := false;
done_with_param_calc <= true;
elsif (transfer'event and transfer = '1') then
reconfig_err <= false;
ASSERT false REPORT "Reconfiguring PLL" severity note;
if (scan_chain = "long") then
-- cntr e3
delay_chain := scan_data(287 downto 284);
if (scan_data(273) = '1') then
e3_mode_val <= "bypass";
if (scan_data(283) = '1') then
e3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(283) = '1') then
e3_mode_val <= " odd";
else
e3_mode_val <= " even";
end if;
high := scan_data(272 downto 264);
low := scan_data(282 downto 274);
e3_low_val <= alt_conv_integer(low);
e3_high_val <= alt_conv_integer(high);
-- count value of 0 is actually 512
if (alt_conv_integer(high) = 0) then
e3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e3_time_delay_val <= delay_val;
-- cntr e2
delay_chain := scan_data(263 downto 260);
if (scan_data(249) = '1') then
e2_mode_val <= "bypass";
if (scan_data(259) = '1') then
e2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(259) = '1') then
e2_mode_val <= " odd";
else
e2_mode_val <= " even";
end if;
high := scan_data(248 downto 240);
low := scan_data(258 downto 250);
e2_low_val <= alt_conv_integer(low);
e2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e2_time_delay_val <= delay_val;
-- cntr e1
delay_chain := scan_data(239 downto 236);
if (scan_data(225) = '1') then
e1_mode_val <= "bypass";
if (scan_data(235) = '1') then
e1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(235) = '1') then
e1_mode_val <= " odd";
else
e1_mode_val <= " even";
end if;
high := scan_data(224 downto 216);
low := scan_data(234 downto 226);
e1_low_val <= alt_conv_integer(low);
e1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e1_time_delay_val <= delay_val;
-- cntr e0
delay_chain := scan_data(215 downto 212);
if (scan_data(201) = '1') then
e0_mode_val <= "bypass";
if (scan_data(211) = '1') then
e0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(211) = '1') then
e0_mode_val <= " odd";
else
e0_mode_val <= " even";
end if;
high := scan_data(200 downto 192);
low := scan_data(210 downto 202);
e0_low_val <= alt_conv_integer(low);
e0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e0_time_delay_val <= delay_val;
end if;
-- cntr l1
delay_chain := scan_data(191 downto 188);
if (scan_data(177) = '1') then
l1_mode_val <= "bypass";
if (scan_data(187) = '1') then
l1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(187) = '1') then
l1_mode_val <= " odd";
else
l1_mode_val <= " even";
end if;
high := scan_data(176 downto 168);
low := scan_data(186 downto 178);
l1_low_val <= alt_conv_integer(low);
l1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l1_time_delay_val <= delay_val;
-- cntr l0
delay_chain := scan_data(167 downto 164);
if (scan_data(153) = '1') then
l0_mode_val <= "bypass";
if (scan_data(163) = '1') then
l0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(163) = '1') then
l0_mode_val <= " odd";
else
l0_mode_val <= " even";
end if;
high := scan_data(152 downto 144);
low := scan_data(162 downto 154);
l0_low_val <= alt_conv_integer(low);
l0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l0_time_delay_val <= delay_val;
-- cntr g3
delay_chain := scan_data(143 downto 140);
if (scan_data(129) = '1') then
g3_mode_val <= "bypass";
if (scan_data(139) = '1') then
g3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(139) = '1') then
g3_mode_val <= " odd";
else
g3_mode_val <= " even";
end if;
high := scan_data(128 downto 120);
low := scan_data(138 downto 130);
g3_low_val <= alt_conv_integer(low);
g3_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g3_time_delay_val <= delay_val;
-- cntr g2
delay_chain := scan_data(119 downto 116);
if (scan_data(105) = '1') then
g2_mode_val <= "bypass";
if (scan_data(115) = '1') then
g2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(115) = '1') then
g2_mode_val <= " odd";
else
g2_mode_val <= " even";
end if;
high := scan_data(104 downto 96);
low := scan_data(114 downto 106);
g2_low_val <= alt_conv_integer(low);
g2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g2_time_delay_val <= delay_val;
-- cntr g1
delay_chain := scan_data(95 downto 92);
if (scan_data(81) = '1') then
g1_mode_val <= "bypass";
if (scan_data(91) = '1') then
g1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(91) = '1') then
g1_mode_val <= " odd";
else
g1_mode_val <= " even";
end if;
high := scan_data(80 downto 72);
low := scan_data(90 downto 82);
g1_low_val <= alt_conv_integer(low);
g1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g1_time_delay_val <= delay_val;
-- cntr g0
delay_chain := scan_data(71 downto 68);
if (scan_data(57) = '1') then
g0_mode_val <= "bypass";
if (scan_data(67) = '1') then
g0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(67) = '1') then
g0_mode_val <= " odd";
else
g0_mode_val <= " even";
end if;
high := scan_data(56 downto 48);
low := scan_data(66 downto 58);
g0_low_val <= alt_conv_integer(low);
g0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g0_time_delay_val <= delay_val;
-- cntr M
is_error := false;
-- 'low' contains modulus for m_cntr(spread_spectrum disabled)
low := scan_data(32 downto 24);
m_val_tmp <= alt_conv_integer(low);
if (scan_data(33) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m_val_tmp <= 512;
end if;
if (not is_error) then
if (m_mode_val = "bypass") then
ASSERT false REPORT "M counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m_mode_val <= " ";
end if;
elsif (scan_data(33) = '1') then
if (scan_data(24) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val /= "bypass") then
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M modulus = "));
write (buf, 1);
writeline (output, buf);
m_val_tmp <= 1;
m_mode_val <= "bypass";
end if;
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
ASSERT FALSE REPORT "VCO is bypassed, setting M modulus = 1, M time delay = 0" severity note;
end if;
-- cntr M2
if (ss > 0) then
is_error := false;
low := scan_data(42 downto 34);
m2_val <= alt_conv_integer(low);
if (scan_data(43) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M2 counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m2_val <= 512;
end if;
if (not is_error) then
if (m2_mode_val = "bypass") then
ASSERT false REPORT "M2 counter switched from BYPASS mode to enabled (M2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m2_mode_val <= " ";
end if;
elsif (scan_data(43) = '1') then
if (scan_data(34) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m2_mode_val /= "bypass") then
ASSERT false REPORT "M2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M2 modulus = "));
write (buf, 1);
writeline (output, buf);
m2_val <= 1;
m2_mode_val <= "bypass";
end if;
end if;
if (m_mode_val /= m2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for M1/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(47 downto 44);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
m_time_delay_val <= delay_val;
if (skip_vco = "on") then
m_time_delay_val <= 0;
delay_val := 0;
end if;
write (buf, string'(" M time delay = "));
write (buf, delay_val);
writeline (output, buf);
-- cntr N
is_error := false;
-- 'low' contains modulus for n_cntr(spread_spectrum disabled)
low := scan_data(8 downto 0);
n_val_tmp <= alt_conv_integer(low);
if (scan_data(9) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n_val_tmp <= 512;
write (buf, string'(" N modulus = "));
write (buf, 512);
writeline (output, buf);
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
if (not is_error) then
if (n_mode_val = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n_mode_val <= " ";
end if;
elsif (scan_data(9) = '1') then
if (scan_data(0) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val /= "bypass") then
ASSERT false REPORT "N counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N modulus = "));
write (buf, 1);
writeline (output, buf);
n_val_tmp <= 1;
n_mode_val <= "bypass";
end if;
end if;
-- cntr N2
if (ss > 0) then
is_error := false;
low := scan_data(18 downto 10);
n2_val <= alt_conv_integer(low);
if (scan_data(19) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N2 counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n2_val <= 512;
end if;
if (not is_error) then
if (n2_mode_val = "bypass") then
ASSERT false REPORT "N2 counter switched from BYPASS mode to enabled (N2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n2_mode_val <= " ";
end if;
elsif (scan_data(19) = '1') then
if (scan_data(10) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n2_mode_val /= "bypass") then
ASSERT false REPORT "N2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N2 modulus = "));
write (buf, 1);
writeline (output, buf);
n2_val <= 1;
n2_mode_val <= "bypass";
end if;
end if;
if (n_mode_val /= n2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for N1/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(23 downto 20);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
n_time_delay_val <= delay_val;
write (buf, string'(" N time delay = "));
write (buf, delay_val);
writeline (output, buf);
else
if (scan_chain = "long") then
write (buf, string'(" E3 high = "));
write (buf, e3_high_val);
write (buf, string'(" , E3 low = "));
write (buf, e3_low_val);
write (buf, string'(" , E3 mode = "));
write (buf, e3_mode_val);
write (buf, string'(" , E3 time delay = "));
write (buf, e3_time_delay_val);
writeline(output, buf);
write (buf, string'(" E2 high = "));
write (buf, e2_high_val);
write (buf, string'(" , E2 low = "));
write (buf, e2_low_val);
write (buf, string'(" , E2 mode = "));
write (buf, e2_mode_val);
write (buf, string'(" , E2 time delay = "));
write (buf, e2_time_delay_val);
writeline(output, buf);
write (buf, string'(" E1 high = "));
write (buf, e1_high_val);
write (buf, string'(" , E1 low = "));
write (buf, e1_low_val);
write (buf, string'(" , E1 mode = "));
write (buf, e1_mode_val);
write (buf, string'(" , E1 time delay = "));
write (buf, e1_time_delay_val);
writeline(output, buf);
write (buf, string'(" E0 high = "));
write (buf, e0_high_val);
write (buf, string'(" , E0 low = "));
write (buf, e0_low_val);
write (buf, string'(" , E0 mode = "));
write (buf, e0_mode_val);
write (buf, string'(" , E0 time delay = "));
write (buf, e0_time_delay_val);
writeline(output, buf);
end if;
write (buf, string'(" L1 high = "));
write (buf, l1_high_val);
write (buf, string'(" , L1 low = "));
write (buf, l1_low_val);
write (buf, string'(" , L1 mode = "));
write (buf, l1_mode_val);
write (buf, string'(" , L1 time delay = "));
write (buf, l1_time_delay_val);
writeline(output, buf);
write (buf, string'(" L0 high = "));
write (buf, l0_high_val);
write (buf, string'(" , L0 low = "));
write (buf, l0_low_val);
write (buf, string'(" , L0 mode = "));
write (buf, l0_mode_val);
write (buf, string'(" , L0 time delay = "));
write (buf, l0_time_delay_val);
writeline(output, buf);
write (buf, string'(" G3 high = "));
write (buf, g3_high_val);
write (buf, string'(" , G3 low = "));
write (buf, g3_low_val);
write (buf, string'(" , G3 mode = "));
write (buf, g3_mode_val);
write (buf, string'(" , G3 time delay = "));
write (buf, g3_time_delay_val);
writeline(output, buf);
write (buf, string'(" G2 high = "));
write (buf, g2_high_val);
write (buf, string'(" , G2 low = "));
write (buf, g2_low_val);
write (buf, string'(" , G2 mode = "));
write (buf, g2_mode_val);
write (buf, string'(" , G2 time delay = "));
write (buf, g2_time_delay_val);
writeline(output, buf);
write (buf, string'(" G1 high = "));
write (buf, g1_high_val);
write (buf, string'(" , G1 low = "));
write (buf, g1_low_val);
write (buf, string'(" , G1 mode = "));
write (buf, g1_mode_val);
write (buf, string'(" , G1 time delay = "));
write (buf, g1_time_delay_val);
writeline(output, buf);
write (buf, string'(" G0 high = "));
write (buf, g0_high_val);
write (buf, string'(" , G0 low = "));
write (buf, g0_low_val);
write (buf, string'(" , G0 mode = "));
write (buf, g0_mode_val);
write (buf, string'(" , G0 time delay = "));
write (buf, g0_time_delay_val);
writeline(output, buf);
end if;
end process;
process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, inclk0_ipd, inclk1_ipd, clkswitch_ipd, done_with_param_calc)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable primary_clock_frequency : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable schedule_offset : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_ext_fbk_cntr : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable init_clks : boolean := true;
variable ext_fbk_cntr_modulus : integer := 1;
variable pll_is_in_reset : boolean := false;
-- clkswitch variables
variable other_clock_value : std_logic := '0';
variable other_clock_last_value : std_logic;
variable current_clock : string(1 to 6) := primary_clock;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (init and done_with_param_calc) then
if (pll_type = "fast") then
locked_tmp := '1';
end if;
m_val <= m_val_tmp;
n_val <= n_val_tmp;
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
-- merged from separate process
if (now = 0 ps) then
if (current_clock = "inclk1") then
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
external_switch := true;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
if (current_clock /= "inclk0") then
other_clock_value := inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event) then
if (current_clock /= "inclk1") then
other_clock_value := inclk1_ipd;
end if;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
if (current_clock = "inclk0") then
current_clk_is_bad := false;
end if;
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = "inclk1") then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_ipd'event and inclk1_ipd = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
if (current_clock = "inclk1") then
current_clk_is_bad := false;
end if;
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = "inclk0") then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if ((primary_clock = "inclk0" and clk0_is_bad = '1') or (primary_clock = "inclk1" and clk1_is_bad = '1')) then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = "inclk0") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event and current_clock = "inclk1") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_ipd;
end if;
else
clkin <= transport inclk1_ipd;
end if;
end if;
if (inclk0_ipd'event or inclk1_ipd'event) then
if ( (other_clock_value = '1') and
(other_clock_value /= other_clock_last_value) and
(switch_over_on_lossclk = "on") and
(enable_switch_over_counter = "on") and
(primary_clk_is_bad) ) then
switch_over_count := switch_over_count + 1;
end if;
if ((other_clock_value = '0') and (other_clock_value /= other_clock_last_value)) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = "inclk0") then
current_clock := "inclk1";
else
current_clock := "inclk0";
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
other_clock_last_value := other_clock_value;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
-- end -- clkswitch
if (schedule_vco'event) then
if (init_clks) then
if (primary_clock = "inclk0") then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk0_input_frequency * 1 ps;
elsif (primary_clock = "inclk1") then
refclk_period := inclk1_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk1_input_frequency * 1 ps;
end if;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
end if;
-- areset deasserted
if (areset_ipd'event and areset_ipd = '0') then
if (scandataout_tmp = '1') then
sdataout_rst_trig <= transport not sdataout_rst_trig;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
end if;
if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
schedule_offset := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and (now > 0 ps)) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
loop_time_delay := m_time_delay_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * (ext_fbk_cntr_modulus));
loop_time_delay := m_time_delay_val + ext_fbk_cntr_delay;
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_ext_fbk_cntr := ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier)/1 ps + fbk_phase;
while (pull_back_ext_fbk_cntr > refclk_period/1 ps) loop
pull_back_ext_fbk_cntr := pull_back_ext_fbk_cntr - refclk_period/ 1 ps;
end loop;
pull_back_M := m_time_delay_val + (m_initial_val - 1) * (ext_fbk_cntr_modulus) * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_ext_fbk_cntr := 0;
pull_back_M := initial_delay/1 ps + m_time_delay_val + fbk_phase;
end if;
total_pull_back := pull_back_M + pull_back_ext_fbk_cntr;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
ext_fbk_delay <= transport (pull_back_ext_fbk_cntr - fbk_phase) after 1 ps;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- add offset
if (schedule_offset) then
sched_time := sched_time + offset;
schedule_offset := false;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
if (sched_time > 0 ps) then
schedule_vco <= transport not schedule_vco after sched_time;
end if;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
n_val <= n_val_tmp;
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ((vco_max /= 0 and vco_min /= 0 and skip_vco = "off" and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
-- unlock
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert false report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= transport m_val_tmp after 1 ps;
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ((now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert (quiet_period_violation) report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
if (pll_type = "fast") then
locked_tmp := '0';
end if;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert (quiet_period_violation) report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped; do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
locked_tmp := 'X';
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (quiet_period_violation or reconfig_err or scanclr_violation or scanclr_clk_violation) then
lock <= '0';
if (pll_type = "fast") then
lock <= '1';
end if;
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
sig_current_clock <= current_clock;
-- signals for debugging
sig_offset <= offset;
sig_refclk_time <= refclk_time;
sig_fbclk_time <= fbclk_time;
sig_fbclk_period <= fbclk_period;
sig_vco_period_was_phase_adjusted <= vco_period_was_phase_adjusted;
sig_phase_adjust_was_scheduled <= phase_adjust_was_scheduled;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
sig_m_times_vco_period <= m_times_vco_period;
sig_new_m_times_vco_period <= new_m_times_vco_period;
sig_got_refclk_posedge <= got_refclk_posedge;
sig_got_fbclk_posedge <= got_fbclk_posedge;
sig_got_second_refclk <= got_second_refclk;
end process;
process (scanclk_ipd, scanaclr_ipd, scan_data, transfer, sdataout_trig, sdataout_rst_trig)
variable j : integer := 0;
variable pll_in_quiet_period : boolean := false;
variable start_quiet_time : time := 0 ps;
variable quiet_time : time := 0 ps;
variable scanclr_rising_time : time := 0 ps;
variable scanclr_falling_time : time := 0 ps;
variable got_first_scanclk_after_scanclr_inactive_edge : boolean := false;
variable scan_chain_being_reset : boolean := false;
function slowest_clk ( L0 : integer; L0_mode : string(1 to 6);
L1 : integer; L1_mode : string(1 to 6);
G0 : integer; G0_mode : string(1 to 6);
G1 : integer; G1_mode : string(1 to 6);
G2 : integer; G2_mode : string(1 to 6);
G3 : integer; G3_mode : string(1 to 6);
E0 : integer; E0_mode : string(1 to 6);
E1 : integer; E1_mode : string(1 to 6);
E2 : integer; E2_mode : string(1 to 6);
E3 : integer; E3_mode : string(1 to 6);
scan_chain : string;
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (L0_mode /= "bypass" and L0_mode /= " off") then
max_modulus := L0;
end if;
if (L1 > max_modulus and L1_mode /= "bypass" and L1_mode /= " off") then
max_modulus := L1;
end if;
if (G0 > max_modulus and G0_mode /= "bypass" and G0_mode /= " off") then
max_modulus := G0;
end if;
if (G1 > max_modulus and G1_mode /= "bypass" and G1_mode /= " off") then
max_modulus := G1;
end if;
if (G2 > max_modulus and G2_mode /= "bypass" and G2_mode /= " off") then
max_modulus := G2;
end if;
if (G3 > max_modulus and G3_mode /= "bypass" and G3_mode /= " off") then
max_modulus := G3;
end if;
if (scan_chain = "long") then
if (E0 > max_modulus and E0_mode /= "bypass" and E0_mode /= " off") then
max_modulus := E0;
end if;
if (E1 > max_modulus and E1_mode /= "bypass" and E1_mode /= " off") then
max_modulus := E1;
end if;
if (E2 > max_modulus and E2_mode /= "bypass" and E2_mode /= " off") then
max_modulus := E2;
end if;
if (E3 > max_modulus and E3_mode /= "bypass" and E3_mode /= " off") then
max_modulus := E3;
end if;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := ((refclk_int/m_mod) * max_modulus) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
begin
if (transfer'event) then
if (transfer = '0') then
-- clear the chain
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
elsif (scanaclr_ipd'event and scanaclr_ipd = '1') then
-- scanaclr rising
scanclr_rising_time := now;
scan_chain_being_reset := true;
elsif (scanaclr_ipd'event and scanaclr_ipd = '0') then
-- scanaclr falling
scanclr_falling_time := now;
if (scan_chain_being_reset and (now - scanclr_rising_time < TRST)) then
scanclr_violation <= true;
ASSERT false REPORT "Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is "& int2str((now - scanclr_rising_time) / 1 ps) &". The PLL may not function correctly." severity warning;
else
scanclr_violation <= false;
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
scan_chain_being_reset := false;
got_first_scanclk_after_scanclr_inactive_edge := false;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and not got_first_scanclk_after_scanclr_inactive_edge and (now - scanclr_falling_time < TRSTCLK)) then
scanclr_clk_violation <= true;
got_first_scanclk_after_scanclr_inactive_edge := true;
ASSERT false REPORT "Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is "& int2str((now - scanclr_falling_time) / 1 ps) &". Reconfiguration may not work." severity warning;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
else
pll_in_quiet_period := false;
for j in scan_chain_length-1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
if (not got_first_scanclk_after_scanclr_inactive_edge) then
got_first_scanclk_after_scanclr_inactive_edge := true;
scanclr_clk_violation <= false;
end if;
elsif (scanclk_ipd'event and scanclk_ipd = '0' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
elsif (scan_data(scan_chain_length-1) = '1') then
-- reset violation flag only after another reconfig seq.
quiet_period_violation <= false;
-- initiate transfer
transfer <= '1';
transfer <= transport '0' after 1 ps;
scandataout_tmp <= '1';
pll_in_quiet_period := true;
start_quiet_time := now;
quiet_time := slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
scan_chain, sig_refclk_period, m_val);
sdataout_trig <= transport not sdataout_trig after quiet_time;
end if;
elsif (sdataout_trig'event) then
if (areset_ipd = '0') then
scandataout_tmp <= transport '0';
end if;
elsif (sdataout_rst_trig'event) then
scandataout_tmp <= transport '0' after quiet_time;
end if;
end process;
clk0_tmp <= l0_clk when i_clk0_counter = "l0" else
l1_clk when i_clk0_counter = "l1" else
g0_clk when i_clk0_counter = "g0" else
g1_clk when i_clk0_counter = "g1" else
g2_clk when i_clk0_counter = "g2" else
g3_clk when i_clk0_counter = "g3" else
'0';
not_clk0_tmp <= not clk0_tmp;
ena0_reg : stratix_dffe
port map ( D => clkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0_tmp,
Q => ena0 );
clk(0) <= ena0 and clk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena0 and 'X';
clk1_tmp <= l0_clk when i_clk1_counter = "l0" else
l1_clk when i_clk1_counter = "l1" else
g0_clk when i_clk1_counter = "g0" else
g1_clk when i_clk1_counter = "g1" else
g2_clk when i_clk1_counter = "g2" else
g3_clk when i_clk1_counter = "g3" else
'0';
not_clk1_tmp <= not clk1_tmp;
ena1_reg : stratix_dffe
port map ( D => clkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk1_tmp,
Q => ena1 );
clk(1) <= ena1 and clk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena1 and 'X';
clk2_tmp <= l0_clk when i_clk2_counter = "l0" else
l1_clk when i_clk2_counter = "l1" else
g0_clk when i_clk2_counter = "g0" else
g1_clk when i_clk2_counter = "g1" else
g2_clk when i_clk2_counter = "g2" else
g3_clk when i_clk2_counter = "g3" else
'0';
not_clk2_tmp <= not clk2_tmp;
ena2_reg : stratix_dffe
port map ( D => clkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk2_tmp,
Q => ena2 );
clk(2) <= ena2 and clk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena2 and 'X';
clk3_tmp <= l0_clk when i_clk3_counter = "l0" else
l1_clk when i_clk3_counter = "l1" else
g0_clk when i_clk3_counter = "g0" else
g1_clk when i_clk3_counter = "g1" else
g2_clk when i_clk3_counter = "g2" else
g3_clk when i_clk3_counter = "g3" else
'0';
not_clk3_tmp <= not clk3_tmp;
ena3_reg : stratix_dffe
port map ( D => clkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk3_tmp,
Q => ena3 );
clk(3) <= ena3 and clk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena3 and 'X';
clk4_tmp <= l0_clk when i_clk4_counter = "l0" else
l1_clk when i_clk4_counter = "l1" else
g0_clk when i_clk4_counter = "g0" else
g1_clk when i_clk4_counter = "g1" else
g2_clk when i_clk4_counter = "g2" else
g3_clk when i_clk4_counter = "g3" else
'0';
not_clk4_tmp <= not clk4_tmp;
ena4_reg : stratix_dffe
port map ( D => clkena(4),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk4_tmp,
Q => ena4 );
clk(4) <= ena4 and clk4_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena4 and 'X';
clk5_tmp <= l0_clk when i_clk5_counter = "l0" else
l1_clk when i_clk5_counter = "l1" else
g0_clk when i_clk5_counter = "g0" else
g1_clk when i_clk5_counter = "g1" else
g2_clk when i_clk5_counter = "g2" else
g3_clk when i_clk5_counter = "g3" else
'0';
not_clk5_tmp <= not clk5_tmp;
ena5_reg : stratix_dffe
port map ( D => clkena(5),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk5_tmp,
Q => ena5 );
clk(5) <= ena5 and clk5_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena5 and 'X';
extclk0_tmp <= e0_clk when i_extclk0_counter = "e0" else
e1_clk when i_extclk0_counter = "e1" else
e2_clk when i_extclk0_counter = "e2" else
e3_clk when i_extclk0_counter = "e3" else
g0_clk when i_extclk0_counter = "g0" else
'0';
not_extclk0_tmp <= not extclk0_tmp;
extena0_reg : stratix_dffe
port map ( D => extclkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk0_tmp,
Q => extena0 );
extclk(0) <= extena0 and extclk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena0 and 'X';
extclk1_tmp <= e0_clk when i_extclk1_counter = "e0" else
e1_clk when i_extclk1_counter = "e1" else
e2_clk when i_extclk1_counter = "e2" else
e3_clk when i_extclk1_counter = "e3" else
g0_clk when i_extclk1_counter = "g0" else
'0';
not_extclk1_tmp <= not extclk1_tmp;
extena1_reg : stratix_dffe
port map ( D => extclkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk1_tmp,
Q => extena1 );
extclk(1) <= extena1 and extclk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena1 and 'X';
extclk2_tmp <= e0_clk when i_extclk2_counter = "e0" else
e1_clk when i_extclk2_counter = "e1" else
e2_clk when i_extclk2_counter = "e2" else
e3_clk when i_extclk2_counter = "e3" else
g0_clk when i_extclk2_counter = "g0" else
'0';
not_extclk2_tmp <= not extclk2_tmp;
extena2_reg : stratix_dffe
port map ( D => extclkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk2_tmp,
Q => extena2 );
extclk(2) <= extena2 and extclk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena2 and 'X';
extclk3_tmp <= e0_clk when i_extclk3_counter = "e0" else
e1_clk when i_extclk3_counter = "e1" else
e2_clk when i_extclk3_counter = "e2" else
e3_clk when i_extclk3_counter = "e3" else
g0_clk when i_extclk3_counter = "g0" else
'0';
not_extclk3_tmp <= not extclk3_tmp;
extena3_reg : stratix_dffe
port map ( D => extclkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk3_tmp,
Q => extena3 );
extclk(3) <= extena3 and extclk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena3 and 'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
scandataout <= scandataout_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratix_dll
--
-- Description : Simulation model for the Stratix DLL.
--
-- Outputs : Delayctrlout output (active high) indicates when the
-- DLL locks to the incoming clock
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratix_atom_pack.all;
USE work.stratix_pllpack.all;
ENTITY stratix_dll is
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratix_dll";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END stratix_dll;
ARCHITECTURE vital_dll of stratix_dll is
signal clk_detect : std_logic := '0';
signal clk_ipd : std_logic;
begin
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
process (clk_ipd, clk_detect)
variable got_first_rising_edge : boolean := false;
variable got_first_falling_edge : boolean := false;
variable clk_ipd_last_rising_edge : time := 0 ps;
variable clk_ipd_last_falling_edge : time := 0 ps;
variable inclk_ps : time := 0 ps;
variable duty_cycle : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable clk_detect_count : integer := 0;
variable start_clk_detect : boolean := false;
variable half_cycles_to_lock : integer := 0;
variable half_cycles_to_keep_lock : integer := 0;
variable violation : boolean := false;
variable dll_is_locked : std_logic := '0';
variable init : boolean := true;
variable input_freq_warn : boolean := true;
variable duty_cycle_warn : boolean := true;
begin
if (init) then
-- convert the frequency in string form to integer
inclk_ps := dqs_str2int(input_frequency) * 1 ps;
duty_cycle := inclk_ps/2;
clk_per_tolerance := inclk_ps * 0.1;
-- if sim_valid_lock = 0, dll starts out locked
if (sim_valid_lock = 0) then
dll_is_locked := '1';
end if;
init := false;
end if;
if (clk_ipd'event and clk_ipd = '1') then
if (not got_first_rising_edge) then
got_first_rising_edge := true;
half_cycles_to_lock := half_cycles_to_lock + 1;
if (sim_valid_lock > 0 and half_cycles_to_lock >= sim_valid_lock and not violation) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
-- start the internal clock that will monitor
-- the input clock
if (not start_clk_detect) then
start_clk_detect := true;
clk_detect <= '1';
end if;
else
-- reset clk_event counter
clk_detect_count := 0;
-- check for clk period violation
if ( ((now - clk_ipd_last_rising_edge) < (inclk_ps - clk_per_tolerance)) or ((now - clk_ipd_last_rising_edge) > (inclk_ps + clk_per_tolerance)) ) then
violation := true;
if (input_freq_warn) then
assert false report "Input frequency violation." severity warning;
input_freq_warn := false;
end if;
elsif ( ((now - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (violation and dll_is_locked = '1') then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (violation) then
half_cycles_to_lock := 0;
elsif (not violation and dll_is_locked = '0') then
-- increment lock counter
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
else
half_cycles_to_keep_lock := 0;
end if;
end if;
clk_ipd_last_rising_edge := now;
elsif (clk_ipd'event and clk_ipd = '0') then
-- reset clk_event counter
clk_detect_count := 0;
got_first_falling_edge := true;
if (got_first_rising_edge) then
-- check for duty cycle violation
if ( ((now - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (dll_is_locked = '1' and violation) then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (dll_is_locked = '1') then
half_cycles_to_keep_lock := 0;
elsif (dll_is_locked = '0' and violation) then
half_cycles_to_lock := 0;
else
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
else
-- first clk edge is falling edge, do nothing
end if;
clk_ipd_last_falling_edge := now;
else
if (clk_ipd'event) then
-- illegal value
if (got_first_rising_edge or got_first_falling_edge) then
if (dll_is_locked = '1') then
dll_is_locked := '0';
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
else
-- clock started up, then went to 'X'
-- this is to weed out the 'X' at start of simulation.
assert false report "Illegal value detected on input clock." severity error;
-- reset lock counter
half_cycles_to_lock := 0;
end if;
end if;
end if;
end if;
-- ********************************************************************
-- The following block generates the internal clock that is used to
-- track loss of input clock. A counter counts events on this internal
-- clock, and is reset to 0 on event on input clock. If input clock
-- flatlines, the counter will exceed the limit and DLL will lose lock.
-- Events on internal clock are scheduled at the max. allowable input
-- clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
-- ********************************************************************
if (start_clk_detect) then
if (clk_detect'event and clk_detect /= clk_detect'last_value) then
-- increment clock event counter
clk_detect_count := clk_detect_count + 1;
if (dll_is_locked = '1') then
if (clk_detect_count > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to loss of input clock" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
clk_detect_count := 0;
start_clk_detect := false;
clk_detect <= transport '0' after inclk_ps/2;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
elsif (clk_detect_count > 10) then
assert false report "No input clock : DLL will not lock" severity warning;
clk_detect_count := 0;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
end if;
end if;
delayctrlout <= dll_is_locked;
end process;
end vital_dll;
-------------------------------------------------------------------
--
-- Entity Name : stratix_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratix_atom_pack.all;
entity stratix_jtag is
generic (
lpm_type : string := "stratix_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratix_jtag;
architecture architecture_jtag of stratix_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratix_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratix_atom_pack.all;
entity stratix_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratix_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratix_crcblock;
architecture architecture_crcblock of stratix_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratix_rublock
--
-- Description : Stratix RUBLOCK VHDL Simulation model
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratix_atom_pack.all;
entity stratix_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratix_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratix_rublock;
architecture architecture_rublock of stratix_rublock is
signal update_reg : std_logic_vector(16 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(21 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is inverted output of shift-reg bit 0
regout <= not shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(16 downto 5) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(4) <= '1';
else
update_reg(4) <= '0';
end if;
-- PGM[] field
update_reg(3 downto 1) <= conv_std_logic_vector(sim_init_page_select, 3);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1]);
--report " -> Field User Watchdog is set to %s", update_reg[4] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 20 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(21) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and operation_mode = "remote") then
-- every bit in Update Reg gets updated
update_reg(16 downto 0) <= shift_reg(21 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[8:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[9] == 1) ? "Enableds" : (shift_reg[9] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[21:10];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
else
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1];
--report " -> Field User Watchdog is set to %s", (update_reg[4] == 1) ? "Enabled" : (update_reg[4] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
---------------------------------------------------------------------
--
-- Entity Name : stratix_routing_wire
--
-- Description : Stratix Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratix_atom_pack.all;
ENTITY stratix_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratix_routing_wire : entity is TRUE;
end stratix_routing_wire;
ARCHITECTURE behave of stratix_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | dc1e63eae38e8d6a94febf8d5f69c1dc | 0.502461 | 3.858006 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_core_comp_pack-p.vhd | 1 | 3,270 | -------------------------------------------------------------------------------
--
-- $Id: t400_core_comp_pack-p.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
package t400_core_comp_pack is
component t400_core
generic (
opt_type_g : integer := t400_opt_type_420_c;
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
por_n_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
pm_addr_o : out std_logic_vector(9 downto 0);
pm_data_i : in std_logic_vector(7 downto 0);
dm_addr_o : out std_logic_vector(5 downto 0);
dm_we_o : out std_logic;
dm_data_o : out std_logic_vector(3 downto 0);
dm_data_i : in std_logic_vector(3 downto 0);
io_l_i : in std_logic_vector(7 downto 0);
io_l_o : out std_logic_vector(7 downto 0);
io_l_en_o : out std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_d_en_o : out std_logic_vector(3 downto 0);
io_g_i : in std_logic_vector(3 downto 0);
io_g_o : out std_logic_vector(3 downto 0);
io_g_en_o : out std_logic_vector(3 downto 0);
io_in_i : in std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
end t400_core_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 546beeafce8057ed389a928488babc6a | 0.51682 | 2.759494 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/altera_europa_support_lib.vhd | 1 | 23,513 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
-----------------------------------------------------------------------------
-- --
-- Description: Declares utility package for Altera IP support --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
package altera_europa_support_lib is
attribute IS_SIGNED : BOOLEAN ;
attribute SYNTHESIS_RETURN : STRING ;
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION A_SRL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SRL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR) return Std_Logic;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC;
-- Result subtype: STD_LOGIC
-- Result: Converts a BOOLEAN to a STD_LOGIC..
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
function a_min(L, R: INTEGER) return INTEGER ;
function a_max(L, R: INTEGER) return INTEGER ;
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
-- All required padding is to the left of the value (right justified) to
-- a string that can hold the maximum value of the vector in that radix.
-- When displaying decimal values (e.g. %d), padding is spaces.
-- When displaying other radices (e.g. %h), padding is zeros.
-- There is no padding when a zero is placed after the % (e.g. %0d or %0h).
type pad_type is (pad_none, pad_spaces, pad_zeros);
function to_hex_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : integer;
pad : pad_type := pad_spaces) return string;
function to_decimal_string(val : std_logic_vector;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_hex_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : std_logic;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
end altera_europa_support_lib;
package body altera_europa_support_lib is
--
-- Reducing logical functions.
--
FUNCTION and_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION or_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result OR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NOR" ;
BEGIN
result := NOT or_reduce(arg);
RETURN result;
END;
FUNCTION xor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result XOR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION xnor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_XNOR" ;
BEGIN
result := NOT xor_reduce(arg);
RETURN result;
END;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC is
begin
if(arg = true) then
return('1');
else
return('0');
end if;
end;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SRL(arg,conv_integer(shift)));
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SLL(arg,conv_integer(shift)));
END;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT - shift DOWNTO 0) := arg(arg'LEFT DOWNTO shift);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT DOWNTO shift) := arg(arg'LEFT - shift DOWNTO 0);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector IS
BEGIN
IF a = '1' THEN
return "1";
ELSE
return "0";
END IF;
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector IS
BEGIN
return a;
END;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR)
return Std_Logic IS
BEGIN
return (vector(vector'right));
END;
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(repeat-1 DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result(i) := arg;
end LOOP;
RETURN(result);
END;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR(((repeat * (arg_copy'LEFT+1))-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result((((arg_copy'left + 1) * i) + arg_copy'left) downto ((arg_copy'left + 1) * i)) := arg_copy(arg_copy'LEFT DOWNTO 0);
end LOOP;
RETURN(result);
END;
-- a_min : return the minimum of two integers;
function a_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- a_max : return the minimum of two integers;
function a_max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
-- a_ext is the Altera version of the EXT function. It is used to both
-- zero-extend a signal to a new length, and to extract a signal of 'size'
-- length from a larger signal.
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
VARIABLE bits_to_copy : integer := 0;
VARIABLE arg_length : integer := arg'length ;
VARIABLE LSB_bit : integer := 0;
BEGIN
bits_to_copy := a_min(arg_length, size);
FOR i IN 0 TO (bits_to_copy - 1) LOOP
result(i) := arg_copy(i);
end LOOP;
RETURN(result);
END;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
subtype slv4 is std_logic_vector(1 to 4);
subtype slv3 is std_logic_vector(1 to 3);
-- Remove leading zeros. Also changes strings of all 'x' or 'z' to one char.
-- This handles the %0<radix> kind of Verilog syntax in the format string.
-- Examples:
-- input output
-- ----- -----------
-- 001f 1f
-- 0000 0
-- xxxx x
-- zzzz z
-- xxzz xxzz
function do_pad_none(
str_in : string) return string is
variable start : integer;
variable all_x : boolean := true;
variable all_z : boolean := true;
begin
-- Nothing to remove if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
case str_in(i) is
when 'X' | 'x' => all_z := false;
when 'Z' | 'z' => all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x or all_z) then
return str_in(str_in'left to str_in'left);
end if;
-- Find index of first non-zero character.
for i in str_in'range loop
start := i;
exit when (str_in(i) /= '0');
end loop;
return str_in(start to str_in'right);
end do_pad_none;
-- Replace leading zeros with spaces.
-- This handles the %d kind of Verilog syntax in the format string.
function replace_leading_zeros(
str_in : string;
c : character) return string is
variable str_out : string(str_in'range) := str_in;
begin
-- Nothing to replace if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
if (str_in(i) = '0') then
str_out(i) := c;
else
exit;
end if;
end loop;
return str_out;
end replace_leading_zeros;
function do_pad(
str : string;
pad : pad_type) return string is
begin
case pad is
when pad_none => return do_pad_none(str);
when pad_spaces => return replace_leading_zeros(str, ' ');
when pad_zeros => return str;
end case;
end do_pad;
function round_up_to_multiple(
val : integer;
size : integer) return integer is
begin
return ((val + size - 1) / size) * size;
end round_up_to_multiple;
function to_hex_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,4);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/4)+1 := 1;
variable str : string(1 to ext_len/4) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 4 /= 1;
case slv4(to_x01z(val_ext(i to i+3))) is
when "0000" => str(ptr) := '0';
when "0001" => str(ptr) := '1';
when "0010" => str(ptr) := '2';
when "0011" => str(ptr) := '3';
when "0100" => str(ptr) := '4';
when "0101" => str(ptr) := '5';
when "0110" => str(ptr) := '6';
when "0111" => str(ptr) := '7';
when "1000" => str(ptr) := '8';
when "1001" => str(ptr) := '9';
when "1010" => str(ptr) := 'a';
when "1011" => str(ptr) := 'b';
when "1100" => str(ptr) := 'c';
when "1101" => str(ptr) := 'd';
when "1110" => str(ptr) := 'e';
when "1111" => str(ptr) := 'f';
when "XXXX" => str(ptr) := 'x';
when "ZZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 3 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_hex_string;
function to_decimal_string(
val : integer;
pad : pad_type := pad_spaces) return string is
variable tmp : integer := val;
variable ptr : integer range 1 to 32 := 32;
variable str : string(1 to 32) := (others=>'0');
begin
if val=0 then
return do_pad("0", pad);
else
while tmp > 0 loop
case tmp rem 10 is
when 0 => str(ptr) := '0';
when 1 => str(ptr) := '1';
when 2 => str(ptr) := '2';
when 3 => str(ptr) := '3';
when 4 => str(ptr) := '4';
when 5 => str(ptr) := '5';
when 6 => str(ptr) := '6';
when 7 => str(ptr) := '7';
when 8 => str(ptr) := '8';
when 9 => str(ptr) := '9';
when others => null;
end case;
tmp := tmp / 10;
ptr := ptr - 1;
end loop;
return do_pad(str(ptr+1 to 32), pad);
end if;
end to_decimal_string;
function to_decimal_string(
val : std_logic_vector;
pad : pad_type := pad_spaces) return string is
variable all_x : boolean := true;
variable all_z : boolean := true;
variable some_x : boolean := false;
variable some_z : boolean := false;
variable fixed_str : string(1 to 1);
begin
for i in val'range loop
case to_x01z(val(i)) is
when 'X' => some_x := true; all_z := false;
when 'Z' => some_z := true; all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x) then
fixed_str(1) := 'x';
return fixed_str;
elsif (all_z) then
fixed_str(1) := 'z';
return fixed_str;
elsif (some_x) then
fixed_str(1) := 'X';
return fixed_str;
elsif (some_z) then
fixed_str(1) := 'Z';
return fixed_str;
else
return to_decimal_string(conv_integer(val), pad);
end if;
end to_decimal_string;
function to_octal_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,3);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/3)+1 := 1;
variable str : string(1 to ext_len/3) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 3 /= 1;
case slv3(to_x01z(val_ext(i to i+2))) is
when "000" => str(ptr) := '0';
when "001" => str(ptr) := '1';
when "010" => str(ptr) := '2';
when "011" => str(ptr) := '3';
when "100" => str(ptr) := '4';
when "101" => str(ptr) := '5';
when "110" => str(ptr) := '6';
when "111" => str(ptr) := '7';
when "XXX" => str(ptr) := 'x';
when "ZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 2 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_octal_string;
function to_hex_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_hex_string;
function to_decimal_string(
val : std_logic;
pad : pad_type := pad_spaces) return string is
begin
return to_binary_string(val, pad);
end to_decimal_string;
function to_octal_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_octal_string;
function to_binary_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to 1);
begin
case to_x01z(val) is
when '0' => str(1) := '0';
when '1' => str(1) := '1';
when 'X' => str(1) := 'x';
when 'Z' => str(1) := 'z';
when others => str(1) := 'x';
end case;
return do_pad(str, pad);
end to_binary_string;
function to_binary_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to val'length) := (others=>'0');
variable ptr : integer := str'left;
begin
for i in val'range loop
str(ptr to ptr) := to_binary_string(val(i));
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_binary_string;
end altera_europa_support_lib;
| gpl-3.0 | 954157b9bf0156d6e52d95e2f369c455 | 0.547272 | 3.726307 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaii_atoms.vhd | 1 | 765,843 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package arriaii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE arriaii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end arriaii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body arriaii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end arriaii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package arriaii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end arriaii_pllpack;
package body arriaii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end arriaii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
entity arriaii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaii_dffe : entity is TRUE;
end arriaii_dffe;
-- architecture body --
architecture behave of arriaii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- arriaii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
entity arriaii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of arriaii_mux21 : entity is TRUE;
end arriaii_mux21;
architecture AltVITAL of arriaii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriaii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
entity arriaii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_mux41 : entity is TRUE;
end arriaii_mux41;
architecture AltVITAL of arriaii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- arriaii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
-- entity declaration --
entity arriaii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaii_and1 : entity is TRUE;
end arriaii_and1;
-- architecture body --
architecture AltVITAL of arriaii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_lcell_comb
--
-- Description : Piranha LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
entity arriaii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_lcell_comb : entity is TRUE;
end arriaii_lcell_comb;
architecture vital_lcell_comb of arriaii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_routing_wire
--
-- Description : PiranhaII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_routing_wire : entity is TRUE;
end arriaii_routing_wire;
ARCHITECTURE behave of arriaii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of arriaii_lvds_tx_reg : ENTITY is TRUE;
END arriaii_lvds_tx_reg;
ARCHITECTURE vital_arriaii_lvds_tx_reg of arriaii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_arriaii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the Piranha
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE std.textio.all;
ENTITY arriaii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END arriaii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of arriaii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE std.textio.all;
ENTITY arriaii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END arriaii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of arriaii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : arriaii_lvds_transmitter
--
-- Description : Timing simulation model for the Piranha LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) Piranha_lvds_tx_parallel_register and
-- 3) Piranha_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE std.textio.all;
USE work.arriaii_lvds_tx_parallel_register;
USE work.arriaii_lvds_tx_out_block;
USE work.arriaii_lvds_tx_reg;
ENTITY arriaii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end arriaii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of arriaii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT arriaii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT arriaii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT arriaii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: arriaii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: arriaii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: arriaii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
dataout_tmp := dpaclkin_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- ARRIAII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.arriaii_atom_pack.all;
entity arriaii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriaii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end arriaii_rublock;
architecture architecture_rublock of arriaii_rublock is
begin
end architecture_rublock;
--
--
-- ARRIAII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
entity arriaii_oscillator is
generic
(
lpm_type: string := "arriaii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end arriaii_oscillator;
architecture architecture_oscillator of arriaii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
----------------------------------------------------------------------------
-- Module Name : arriaii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END arriaii_ram_register;
ARCHITECTURE reg_arch OF arriaii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : arriaii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF arriaii_ram_pulse_generator:ENTITY IS TRUE;
END arriaii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF arriaii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_ram_register;
USE work.arriaii_ram_pulse_generator;
ENTITY arriaii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END arriaii_ram_block;
ARCHITECTURE block_arch OF arriaii_ram_block IS
COMPONENT arriaii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriaii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : arriaii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : arriaii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : arriaii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : arriaii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : arriaii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : arriaii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : arriaii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : arriaii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : arriaii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : arriaii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : arriaii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : arriaii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : arriaii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : arriaii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_ff
--
-- Description : Piranha FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
use work.arriaii_and1;
entity arriaii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_ff : entity is TRUE;
end arriaii_ff;
architecture vital_lcell_ff of arriaii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component arriaii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: arriaii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: arriaii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: arriaii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Piranha CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- ARRIAII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
entity arriaii_clkselect is
generic (
lpm_type : STRING := "arriaii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_clkselect : entity is TRUE;
end arriaii_clkselect;
architecture vital_clkselect of arriaii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- arriaii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
-- entity declaration --
entity arriaii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of arriaii_and2 : entity is TRUE;
end arriaii_and2;
-- architecture body --
architecture AltVITAL of arriaii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_ena_reg : entity is TRUE;
end arriaii_ena_reg;
ARCHITECTURE behave of arriaii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Piranha CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- Piranha_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
use work.arriaii_ena_reg;
use work.arriaii_and2;
entity arriaii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_clkena : entity is TRUE;
end arriaii_clkena;
architecture vital_clkena of arriaii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component arriaii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component arriaii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : arriaii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : arriaii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : arriaii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : arriaii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : arriaii_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF arriaii_mlab_cell_pulse_generator:ENTITY IS TRUE;
END arriaii_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF arriaii_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_mlab_cell_pulse_generator;
ENTITY arriaii_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END arriaii_mlab_cell;
ARCHITECTURE block_arch OF arriaii_mlab_cell IS
COMPONENT arriaii_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : arriaii_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_io_ibuf
--
-- Description : Piranha IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END arriaii_io_ibuf;
ARCHITECTURE arch OF arriaii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_io_obuf
--
-- Description : Piranha IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END arriaii_io_obuf;
ARCHITECTURE arch OF arriaii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : arriaii_ddio_in
--
-- Description : Piranha DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_ddio_in;
ARCHITECTURE arch OF arriaii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_ddio_oe
--
-- Description : Piranha DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_ddio_oe;
ARCHITECTURE arch OF arriaii_ddio_oe IS
component arriaii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : arriaii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : arriaii_ddio_out
--
-- Description : Piranha DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_ddio_out;
ARCHITECTURE arch OF arriaii_ddio_out IS
component arriaii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : arriaii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package arriaii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end arriaii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body arriaii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end arriaii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY arriaii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END arriaii_dll_gray_encoder;
ARCHITECTURE arriaii_dll_gray_encoder_arch OF arriaii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END arriaii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY arriaii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END arriaii_dll_gray_decoder;
ARCHITECTURE arriaii_dll_gray_decoder_arch OF arriaii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END arriaii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: arriaii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.arriaii_atom_pack.all;
use work.arriaii_dll_gray_decoder;
ENTITY arriaii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END arriaii_ddr_delay_chain_s;
ARCHITECTURE arriaii_ddr_delay_chain_s_arch OF arriaii_ddr_delay_chain_s IS
COMPONENT arriaii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : arriaii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END arriaii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
entity arriaii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of arriaii_ddr_io_reg : entity is TRUE;
end arriaii_ddr_io_reg;
architecture vital_arriaii_ddr_io_reg of arriaii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_arriaii_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/arriaii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaii_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : Piranha_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
use work.arriaii_pllpack.all;
use work.arriaii_atom_ddr_pack.all;
use work.arriaii_dll_gray_encoder;
ENTITY arriaii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END arriaii_dll;
ARCHITECTURE vital_piranhadll of arriaii_dll is
COMPONENT arriaii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in arriaii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in arriaii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in arriaii
signal pc_comp_range : integer := 0; -- new in arriaii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : arriaii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in arriaii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_piranhadll;
-------------------------------------------------------------------------------
--
-- Entity Name : Piranha_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
USE work.arriaii_pllpack.all;
use work.arriaii_atom_ddr_pack.all;
use work.arriaii_dll_gray_encoder;
use work.arriaii_dll_gray_decoder;
ENTITY arriaii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END arriaii_dll_offset_ctrl;
ARCHITECTURE vital_piranhaoffset of arriaii_dll_offset_ctrl is
COMPONENT arriaii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : arriaii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : arriaii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : arriaii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : arriaii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_piranhaoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : arriaii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_dqs_enable IS
GENERIC (
lpm_type : string := "arriaii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE arriaii_dqs_enable_arch OF arriaii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaii_dqs_enable_arch;
-------------------------------------------------------------------------------
-- Module Name: arriaii_mac_bit_register --
-- Description: Piranha MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaii_mac_bit_register;
ARCHITECTURE arch OF arriaii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: arriaii_mac_register --
-- Description: Piranha MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END arriaii_mac_register;
ARCHITECTURE arch OF arriaii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: arriaii_mac_multiplier --
-- Description: Piranha MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END arriaii_mac_multiplier;
ARCHITECTURE arch OF arriaii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: arriaii_mac_mult_atom --
-- Description: Simulation model for arriaii mac mult atom. --
-- This model instantiates the following components. --
-- 1.arriaii_mac_bit_register. --
-- 2.arriaii_mac_register. --
-- 3.arriaii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_mac_mult;
ARCHITECTURE arch OF arriaii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT arriaii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : arriaii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : arriaii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : arriaii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : arriaii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : arriaii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : arriaii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_fsa_isse --
-- Description: Piranha first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END arriaii_fsa_isse;
ARCHITECTURE arch OF arriaii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_first_stage_add_sub --
-- Description: Piranha First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaii_first_stage_add_sub;
ARCHITECTURE arch OF arriaii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_second_stage_add_accum --
-- Description: Piranha Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END arriaii_second_stage_add_accum;
ARCHITECTURE arch OF arriaii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_round_block --
-- Description: Piranha round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaii_round_block;
ARCHITECTURE arch OF arriaii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_saturate_block --
-- Description: Piranha saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END arriaii_saturate_block;
ARCHITECTURE arch OF arriaii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_round_saturate_block --
-- Description: Piranha round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.arriaii_round_block. --
-- 2.arriaii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END arriaii_round_saturate_block;
ARCHITECTURE arch OF arriaii_round_saturate_block IS
COMPONENT arriaii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : arriaii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : arriaii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_rotate_shift_block --
-- Description: Piranha roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END arriaii_rotate_shift_block;
ARCHITECTURE arch OF arriaii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: arriaii_carry_chain_adder --
-- Description: Piranha carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END arriaii_carry_chain_adder;
ARCHITECTURE arch OF arriaii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: arriaii_mac_out_atom --
-- Description: Simulation model for arriaii mac out atom --
-- This model instantiates the following components --
-- 1.arriaii_mac_bit_register --
-- 2.arriaii_mac_register --
-- 3.arriaii_fsa_isse --
-- 4.arriaii_first_stage_add_sub --
-- 5.arriaii_second_stage_add_accum --
-- 6.arriaii_round_saturate_block --
-- 7.arriaii_rotate_shift_block --
-- 8.arriaii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY arriaii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END arriaii_mac_out;
ARCHITECTURE arch OF arriaii_mac_out IS
COMPONENT arriaii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT arriaii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : arriaii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : arriaii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : arriaii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : arriaii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : arriaii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : arriaii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : arriaii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : arriaii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : arriaii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : arriaii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : arriaii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : arriaii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : arriaii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : arriaii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : arriaii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : arriaii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : arriaii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : arriaii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : arriaii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : arriaii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : arriaii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : arriaii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : arriaii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : arriaii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : arriaii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : arriaii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : arriaii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : arriaii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : arriaii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : arriaii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : arriaii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : arriaii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : arriaii_io_pad
-- Description : Simulation model for arriaii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY arriaii_io_pad IS
GENERIC (
lpm_type : string := "arriaii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END arriaii_io_pad;
ARCHITECTURE arch OF arriaii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the PiranhaII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END arriaii_mn_cntr;
ARCHITECTURE behave of arriaii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the PiranhaII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END arriaii_scale_cntr;
ARCHITECTURE behave of arriaii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY arriaii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end arriaii_pll_reg;
ARCHITECTURE behave of arriaii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : arriaii_pll
--
-- Description : Timing simulation model for the PiranhaII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_pllpack.all;
USE work.arriaii_mn_cntr;
USE work.arriaii_scale_cntr;
USE work.arriaii_dffe;
USE work.arriaii_pll_reg;
-- New Features : The list below outlines key new features in ARRIAII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY arriaii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "PiranhaIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END arriaii_pll;
ARCHITECTURE vital_pll of arriaii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT arriaii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT arriaii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT arriaii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT arriaii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : arriaii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : arriaii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : arriaii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : arriaii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : arriaii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : arriaii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : arriaii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : arriaii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : arriaii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : arriaii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : arriaii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : arriaii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/arriaii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/arriaii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : arriaii_asmiblock
--
-- Description : Piranha ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaii_atom_pack.all;
entity arriaii_asmiblock is
generic (
lpm_type : string := "arriaii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end arriaii_asmiblock;
architecture architecture_asmiblock of arriaii_asmiblock is
begin
end architecture_asmiblock; -- end of arriaii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END arriaii_lvds_reg;
ARCHITECTURE vital_arriaii_lvds_reg of arriaii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_arriaii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF arriaii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_lvds_rx_fifo_sync_ram;
ENTITY arriaii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END arriaii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of arriaii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT arriaii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : arriaii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_lvds_reg;
ENTITY arriaii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END arriaii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF arriaii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT arriaii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : arriaii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : arriaii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_rx_deser
--
-- Description : Timing simulation model for the arriaii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF arriaii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the arriaii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
ENTITY arriaii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF arriaii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY arriaii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END arriaii_pclk_divider;
ARCHITECTURE arch OF arriaii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY arriaii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END arriaii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF arriaii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY arriaii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END arriaii_dpa_retime_block;
ARCHITECTURE trans OF arriaii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.arriaii_dpa_retime_block;
ENTITY arriaii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END arriaii_dpa_block;
ARCHITECTURE trans OF arriaii_dpa_block IS
COMPONENT arriaii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : arriaii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : arriaii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the arriaii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) arriaii_lvds_rx_fifo
-- 2) arriaii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) arriaii_lvds_rx_parallel_reg
-- 5) arriaii_pclk_divider
-- 6) arriaii_select_ini_phase_dpaclk
-- 7) arriaii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.arriaii_atom_pack.all;
USE work.arriaii_lvds_rx_bitslip;
USE work.arriaii_lvds_rx_fifo;
USE work.arriaii_lvds_rx_deser;
USE work.arriaii_lvds_rx_parallel_reg;
USE work.arriaii_lvds_reg;
USE work.arriaii_pclk_divider;
USE work.arriaii_select_ini_phase_dpaclk;
USE work.arriaii_dpa_block;
ENTITY arriaii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END arriaii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF arriaii_lvds_receiver IS
COMPONENT arriaii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT arriaii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT arriaii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT arriaii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT arriaii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal in_reg_data_dly : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
signal ini_dpa_clk_dly : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
process(in_reg_data)
begin
if(dpaswitch_ipd = '1') then
if(rx_input_path_delay_engineering_bits = 1) then
in_reg_data_dly <= TRANSPORT in_reg_data after 60 ps;
elsif(rx_input_path_delay_engineering_bits = 2) then
in_reg_data_dly <= TRANSPORT in_reg_data after 120 ps;
elsif(rx_input_path_delay_engineering_bits = 3) then
in_reg_data_dly <= TRANSPORT in_reg_data after 180 ps;
else
in_reg_data_dly <= in_reg_data;
end if;
else
in_reg_data_dly <= in_reg_data;
end if;
end process;
xhdl_12 <= devclrn OR devpor;
process(ini_dpa_clk)
begin
ini_dpa_clk_dly <= ini_dpa_clk;
end process;
-- input register in non-DPA mode for sampling incoming data
in_reg : arriaii_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : arriaii_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: arriaii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : arriaii_lvds_reg
PORT MAP (
d => in_reg_data_dly,
clk => ini_dpa_clk_dly,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : arriaii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: arriaii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: arriaii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : arriaii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : arriaii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" ) else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : arriaii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : arriaii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : arriaii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: arriaii_pseudo_diff_out --
--Description: Simulation model for Piranha Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END arriaii_pseudo_diff_out;
ARCHITECTURE arch OF arriaii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_dqs_delay_chain
--
-- Description : arriaii DQS Delay Chain (within DQS I/O)
-- VHDL simulation model
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_dqs_delay_chain IS
GENERIC (
lpm_type : STRING := "arriaii_dqs_delay_chain";
delay_buffer_mode : STRING := "low";
dqs_ctrl_latches_enable : STRING := "false";
dqs_input_frequency : string := "unused" ;
dqs_offsetctrl_enable : STRING := "false";
dqs_phase_shift : INTEGER := 0;
phase_setting : INTEGER := 0;
sim_buffer_delay_increment : INTEGER := 10;
sim_high_buffer_intrinsic_delay : INTEGER := 175;
sim_low_buffer_intrinsic_delay : INTEGER := 350;
test_enable : STRING := "false";
test_select : INTEGER := 0 ;
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
dqsin : IN STD_LOGIC := '0';
dqsupdateen : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT STD_LOGIC
);
END arriaii_dqs_delay_chain;
ARCHITECTURE arriaii_dqs_delay_chain_arch OF arriaii_dqs_delay_chain IS
-- component section
COMPONENT arriaii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT (
gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs for delayctrl and offsetctrl
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- mux outputs after registers
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
SIGNAL test_bus : std_logic_vector(14 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
BEGIN
--offsetctrlin mux select
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- delayctrlin and offsetctrlin registers
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1' AND dqsupdateen_in'event) THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
-- mux after registers
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
-- decode gray inputs to binary
mdelayctrlin_dec : arriaii_dll_gray_decoder
GENERIC MAP (
width => 6
)
PORT MAP (
gin => delayctrl_reg_mux,
bout => delayctrl_bin
);
moffsetctrlin_dec : arriaii_dll_gray_decoder
GENERIC MAP (
width => 6
)
PORT MAP (
gin => offsetctrl_reg_mux,
bout => offsetctrl_bin
);
PROCESS (delayctrl_bin, offsetctrl_bin)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(offsetctrl_bin)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
-- total delay
IF (phase_setting = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (phase_setting - 1)*acell_delay + aoffsetcell_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & 'X' & 'X' & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 14)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/ARRIAII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END arriaii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Module Name : arriaii_dqs_enable_ctrl
--
-- Description : arriaii DQS enable control (within DQS I/O)
-- VHDL simulation model
--
-------------------------------------------------------------------------------
library IEEE;
library altera;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.arriaii_atom_pack.all;
ENTITY arriaii_dqs_enable_ctrl IS
GENERIC (
lpm_type : STRING := "arriaii_dqs_enable_ctrl";
delay_dqs_enable_by_half_cycle : STRING := "false" ;
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN STD_LOGIC := '0';
dqsenablein : IN STD_LOGIC := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT STD_LOGIC
);
END arriaii_dqs_enable_ctrl;
ARCHITECTURE trans OF arriaii_dqs_enable_ctrl IS
signal devpor_ipd :STD_LOGIC;
signal dqsenablein_ipd :STD_LOGIC;
signal clk_ipd :STD_LOGIC;
signal devclrn_ipd :STD_LOGIC;
COMPONENT dffeas
GENERIC (
power_up : STRING := "DONT_CARE";
is_wysiwyg : STRING := "false";
x_on_violation : STRING := "on";
lpm_type : STRING := "dffeas"
);
PORT (
d : IN STD_LOGIC;
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
clrn : IN STD_LOGIC;
prn : IN STD_LOGIC;
aload : IN STD_LOGIC;
asdata : IN STD_LOGIC;
sclr : IN STD_LOGIC;
sload : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC
);
END COMPONENT;
--Internal signals
SIGNAL dqsenablein_regp : STD_LOGIC;
SIGNAL dqsenablein_regn : STD_LOGIC;
SIGNAL dqsenableout_tmp : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl0 : STD_LOGIC;
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
end block;
regp : dffeas
PORT MAP (
d => dqsenablein_in,
clk => clk_in,
clrn => '1',
aload => '0',
sclr => '0',
sload => '0',
asdata => '0',
ena => '1',
prn => '1',
q => dqsenablein_regp,
devpor => devpor,
devclrn => devclrn
);
xhdl0 <= NOT(clk);
regn : dffeas
PORT MAP (
d => dqsenablein_regp,
clk => xhdl0,
clrn => '1',
aload => '0',
sclr => '0',
sload => '0',
asdata => '0',
ena => '1',
prn => '1',
q => dqsenablein_regn,
devpor => devpor,
devclrn => devclrn
);
--output assignment
dqsenableout_tmp <= dqsenablein_regp WHEN (delay_dqs_enable_by_half_cycle = ("false")) ELSE
(dqsenablein_regn AND dqsenablein_regp);
dqsenableout <= dqsenableout_tmp;
END trans;
--arriaii_dqs_enable_ctrl
-------------------------------------------------------------------
--
-- Entity Name : arriaii_jtag
--
-- Description : arriaii JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaii_atom_pack.all;
entity arriaii_jtag is
generic (
lpm_type : string := "arriaii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end arriaii_jtag;
architecture architecture_jtag of arriaii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : arriaii_crcblock
--
-- Description : arriaii CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaii_atom_pack.all;
entity arriaii_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end arriaii_crcblock;
architecture architecture_crcblock of arriaii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : arriaii_controller
--
-- Description : arriaii CONTROLLER VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaii_atom_pack.all;
entity arriaii_controller is
generic (
lpm_type : string := "arriaii_controller"
);
port (
nceout : out std_logic
);
end arriaii_controller;
architecture architecture_controller of arriaii_controller is
begin
end architecture_controller;
-------------------------------------------------------------------
--
-- Entity Name : arriaii_spiblock
--
-- Description : arriaii SPIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.arriaii_atom_pack.all;
entity arriaii_spiblock is
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0in : in std_logic;
data0out : out std_logic;
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic
);
end arriaii_spiblock;
architecture architecture_spiblock of arriaii_spiblock is
begin
end architecture_spiblock;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY STD;
USE STD.textio.ALL;
USE work.arriaii_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaii_termination_logic IS
GENERIC (
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationselect : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
--INPUT PORTS
lpm_type : STRING := "arriaii_termination_logic"
);
PORT (
terminationclock : IN STD_LOGIC := '0';
terminationdata : IN STD_LOGIC := '0';
terminationselect : IN STD_LOGIC := '0';
--OUTPUT PORTS
terminationcontrol : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arriaii_termination_logic;
ARCHITECTURE trans OF arriaii_termination_logic IS
signal terminationclock_ipd :STD_LOGIC;
signal terminationselect_ipd :STD_LOGIC;
signal terminationdata_ipd :STD_LOGIC;
SIGNAL shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000" ;
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (terminationclock_ipd,terminationclock, tipd_terminationclock);
VitalWireDelay (terminationselect_ipd,terminationselect, tipd_terminationselect);
VitalWireDelay (terminationdata_ipd,terminationdata, tipd_terminationdata);
END BLOCK;
------------------------
-- Functionality Section --
------------------------
terminationcontrol <= shift_reg;
-- END PROCESS;
PROCESS (terminationclock_ipd)
VARIABLE txt : LINE;
BEGIN
IF (terminationclock_ipd'EVENT AND terminationclock_ipd = '1') THEN
IF (terminationselect_ipd = '1') THEN
shift_reg <= (shift_reg(14 DOWNTO 0) & terminationdata_ipd);
END IF;
END IF;
END PROCESS;
END trans;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY STD;
USE STD.textio.ALL;
USE work.arriaii_atom_pack.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY arriaii_termination IS
GENERIC (
-- generic control parameters --
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_scanshiftmux : VitalDelayType01 := DefpropDelay01;
tipd_scaninmux : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclock : VitalDelayType01 := DefpropDelay01;
tipd_scanclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclear : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_rup : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination";
runtime_control : STRING := "false"
);
PORT (
rdn : IN STD_LOGIC := '0';
rup : IN STD_LOGIC := '0';
scanclock : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC := '0';
scaninmux : IN STD_LOGIC := '0';
scanshiftmux : IN STD_LOGIC := '0';
terminationuserclear : IN STD_LOGIC := '0';
terminationuserclock : IN STD_LOGIC := '0';
comparatorprobe : OUT STD_LOGIC;
scanout : OUT STD_LOGIC;
terminationclockout : OUT STD_LOGIC;
terminationcontrolprobe : OUT STD_LOGIC;
terminationdataout : OUT STD_LOGIC;
terminationdone : OUT STD_LOGIC;
terminationselectout : OUT STD_LOGIC
);
END arriaii_termination;
ARCHITECTURE trans OF arriaii_termination IS
signal scanshiftmux_ipd :STD_LOGIC;
signal scaninmux_ipd :STD_LOGIC;
signal scanin_ipd :STD_LOGIC;
signal terminationuserclock_ipd :STD_LOGIC;
signal scanclock_ipd :STD_LOGIC;
signal terminationuserclear_ipd :STD_LOGIC;
signal rdn_ipd :STD_LOGIC;
signal rup_ipd :STD_LOGIC;
SIGNAL cal_shift_cycles : INTEGER := 0 ;
SIGNAL reset_oct_reg : STD_LOGIC;
SIGNAL terminationdone_tmp : STD_LOGIC := '0' ;
SIGNAL internal_enable_read : STD_LOGIC;
SIGNAL internal_clk_enable : STD_LOGIC;
SIGNAL terminationclockout_tmp : STD_LOGIC := '0' ;
SIGNAL terminationselectout_tmp : STD_LOGIC := '0' ;
SIGNAL terminationuserclear_prev : STD_LOGIC;
BEGIN
------------------------
-- Wire Delay Block --
------------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay (terminationuserclear_ipd,terminationuserclear, tipd_terminationuserclear);
VitalWireDelay (rdn_ipd,rdn, tipd_rdn);
VitalWireDelay (scanin_ipd,scanin, tipd_scanin);
VitalWireDelay (scaninmux_ipd,scaninmux, tipd_scaninmux);
VitalWireDelay (scanshiftmux_ipd,scanshiftmux, tipd_scanshiftmux);
VitalWireDelay (rup_ipd,rup, tipd_rup);
VitalWireDelay (scanclock_ipd,scanclock, tipd_scanclock);
VitalWireDelay (terminationuserclock_ipd,terminationuserclock, tipd_terminationuserclock);
END BLOCK;
------------------------
-- Functionality Section --
------------------------
-- END PROCESS;
PROCESS (terminationuserclock_ipd, terminationuserclear_ipd)
VARIABLE txt : LINE;
BEGIN
-- detect rising edge of terminationuserclear_ipd
IF (terminationuserclear_ipd = '1' AND terminationuserclear_prev = '0') THEN
reset_oct_reg <= '1';
terminationdone_tmp <= '1';
cal_shift_cycles <= 0;
terminationselectout_tmp <= '0';
terminationclockout_tmp <= '0';
END IF;
-- detect falling edge of terminationuserclear_ipd
IF (terminationuserclear_ipd = '0' AND reset_oct_reg = '1') THEN
reset_oct_reg <= '0';
internal_enable_read <= '1';
END IF;
-- set internal clock enable at the first negative edge of terminationuserclock_ipd after terminationuserclear_ipd is pulled low-high
IF (internal_enable_read = '1' AND terminationuserclock_ipd = '0') THEN
internal_clk_enable <= '1';
internal_enable_read <= '0';
END IF;
--Assign values for terminationclockout and terminationselectout
IF (terminationselectout_tmp = '1') THEN
--Start calibration at the positive edge of terminationuserclock_ipd when internal clock enable is asserted
terminationclockout_tmp <= terminationuserclock_ipd;
END IF;
IF (internal_clk_enable = '1' AND terminationuserclock_ipd = '1') THEN
IF (cal_shift_cycles = 27) THEN
terminationdone_tmp <= '0';
ELSE
IF (cal_shift_cycles = 10) THEN
terminationselectout_tmp <= '1';
END IF;
cal_shift_cycles <= cal_shift_cycles + 1;
END IF;
END IF;
-- if(cal_shift_cycles == 11 && terminationuserclock_ipd == 1'b1)
-- terminationselectout_tmp = 1'b1;
IF (cal_shift_cycles = 27 AND terminationuserclock_ipd = '0') THEN
-- Reset all the internal signals at the end of calibration+shift
terminationselectout_tmp <= '0';
END IF;
IF (terminationdone_tmp = '0') THEN
cal_shift_cycles <= 0;
internal_clk_enable <= '0';
END IF;
terminationuserclear_prev <= terminationuserclear_ipd;
END PROCESS;
terminationdone <= terminationdone_tmp;
terminationclockout <= terminationclockout_tmp;
terminationselectout <= terminationselectout_tmp;
END trans;
| gpl-3.0 | 40294c9b4010c8a0e03504b1ddac99e5 | 0.471927 | 4.126131 | false | false | false | false |
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