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alvieboy/xtc-base | tb.vhd | 1 | 2,499 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity tb is
end entity tb;
architecture sim of tb is
constant period: time := 10 ns;--9.615 ns;
signal w_clk: std_logic := '0';
signal w_clk_2x: std_logic := '1';
signal w_rst: std_logic := '0';
component uart is
generic (
bits: integer := 11
);
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
tx: out std_logic;
rx: in std_logic
);
end component;
component spi is
generic (
INTERNAL_SPI: boolean := false
);
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
cs: out std_logic;
enabled: out std_logic
);
end component spi;
signal txd, rxd: std_logic;
signal wbi: wb_mosi_type;
signal wbo: wb_miso_type;
signal syscon: wb_syscon_type;
signal swbi: slot_wbi;
signal swbo: slot_wbo;
signal sids: slot_ids;
begin
rxd <= '1';
w_clk <= not w_clk after period/2;
syscon.clk<=w_clk;
syscon.rst<=w_rst;
cpu: xtc_top_bram
port map (
wb_syscon => syscon,
-- Master wishbone interface
iowbi => wbo,
iowbo => wbi
);
ioctrl: xtc_ioctrl
port map (
syscon => syscon,
wbi => wbi,
wbo => wbo,
swbi => swbi,
swbo => swbo,
sids => sids
);
nodev0: nodev port map ( syscon => syscon, wbi => swbo(0), wbo => swbi(0) );
myuart: uart
port map (
syscon => syscon,
wbi => swbo(1),
wbo => swbi(1),
tx => txd,
rx => rxd
);
flashspi: spi
generic map (
INTERNAL_SPI => true
)
port map (
syscon => syscon,
wbi => swbo(2),
wbo => swbi(2),
mosi => open,
miso => '1',
sck => open,
cs => open
);
emptyslots: for N in 3 to 15 generate
eslot: nodev
port map (
syscon => syscon,
wbi => swbo(N),
wbo => swbi(N)
);
end generate;
-- Reset procedure
process
begin
w_rst<='0';
wait for period;
w_rst<='1';
wait for period;
w_rst<='0';
wait;
end process;
end sim;
| bsd-3-clause | fada173ee95de41b0eb6490e2edc9e5d | 0.507803 | 3.262402 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t411.vhd | 1 | 7,284 | -------------------------------------------------------------------------------
--
-- T411 system toplevel.
--
-- $Id: t411.vhd,v 1.2 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t411 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(1 downto 0);
io_g_b : inout std_logic_vector(2 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t411;
use work.t400_system_comp_pack.t410_notri;
architecture struct of t411 is
signal io_l_from_t410_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t410_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_to_t410_s,
io_g_from_t410_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal gnd_s : std_logic;
begin
gnd_s <= '0';
-----------------------------------------------------------------------------
-- T411 without tri-states
-----------------------------------------------------------------------------
t410_notri_b : t410_notri
generic map (
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => t400_opt_cko_crystal_c,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_d_out_type_3_g => t400_opt_out_type_std_c,
opt_d_out_type_2_g => t400_opt_out_type_std_c,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => t400_opt_out_type_std_c,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => gnd_s,
io_l_i => io_l_b,
io_l_o => io_l_from_t410_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t410_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_to_t410_s,
io_g_o => io_g_from_t410_s,
io_g_en_o => io_g_en_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t410_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 1 downto 0 generate
io_d_o(idx) <= io_d_from_t410_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 2 downto 0 generate
io_g_b(idx) <= io_g_from_t410_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
io_g_to_t410_s <= io_g_from_t410_s(3) & io_g_b;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 9ba865b40559c66e57e9914842d999b6 | 0.531713 | 2.992605 | false | false | false | false |
migueljiarr/RV32I | src/right_XLEN_barrel_shifter.vhd | 1 | 1,156 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_XLEN_barrel_shifter;
architecture structural of right_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= '0' & i(31 downto 1);
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= "00" & s1(31 downto 2);
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= "0000" & s2(31 downto 4);
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= "00000000" & s3(31 downto 8);
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= "0000000000000000" & s4(31 downto 16);
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
| mit | 1bc6c73160d02c0573067a5aa3120248 | 0.622837 | 2.603604 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_t410.vhd | 1 | 4,618 | -------------------------------------------------------------------------------
--
-- Testbench for the T410 system toplevel.
--
-- $Id: tb_t410.vhd,v 1.1 2006-06-11 22:19:32 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t410 is
end tb_t410;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t410;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t410 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t410_b : t410
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/05 18:50:45 arniml
-- remove obsolete en_clk_s
--
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | f1a2546892570b53d9bb712ce862b3bf | 0.553053 | 3.697358 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/enc_chan.vhd | 1 | 2,723 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ENC_CHAN is
port (
RESET: in std_logic;
CLK: in std_logic;
CAPTURE: in std_logic;
TIMESTAMP: in std_logic_vector(31 downto 0);
CNT_REG: out std_logic_vector(31 downto 0);
TS_REG: out std_logic_vector(31 downto 0);
IDX_REG: out std_logic_vector(31 downto 0);
ENC_A: in std_logic;
ENC_B: in std_logic;
ENC_I: in std_logic
);
end;
architecture rtl of ENC_CHAN is
signal enc_in: std_logic_vector(1 downto 0);
signal enc_q: std_logic_vector(1 downto 0);
signal enc_dly: std_logic;
signal enc_idx_in: std_logic_vector(2 downto 0);
signal enc_cnt: std_logic_vector(30 downto 0);
signal enc_cnt_flag: std_logic;
signal enc_ts: std_logic_vector(31 downto 0);
signal enc_idx: std_logic_vector(30 downto 0);
signal enc_idx_flag: std_logic;
begin
capture_proc: process(RESET, CLK)
begin
if RESET = '1' then
CNT_REG <= (others => '0');
TS_REG <= (others => '0');
IDX_REG <= (others => '0');
elsif rising_edge(CLK) then
if CAPTURE = '1' then
CNT_REG <= enc_cnt_flag & enc_cnt;
TS_REG <= enc_ts;
IDX_REG <= enc_idx_flag & enc_idx;
end if;
end if;
end process;
enc_filter_proc: process(RESET, CLK)
begin
if RESET = '1' then
enc_in <= (others => '0');
enc_q <= (others => '0');
enc_idx_in <= (others => '0');
elsif rising_edge(CLK) then
enc_in <= ENC_A & ENC_B;
case enc_in is
when "00" => enc_q <= enc_q(1) & '0';
when "01" => enc_q <= '0' & enc_q(0);
when "10" => enc_q <= '1' & enc_q(0);
when others => enc_q <= enc_q(1) & '1';
end case;
enc_idx_in <= enc_idx_in(1 downto 0) & ENC_I;
end if;
end process;
enc_cnt_proc: process(RESET, CLK)
begin
if RESET = '1' then
enc_cnt <= (others => '0');
enc_idx <= (others => '0');
enc_cnt_flag <= '0';
enc_idx_flag <= '0';
elsif rising_edge(CLK) then
if CAPTURE = '1' then
enc_cnt_flag <= '0';
enc_idx_flag <= '0';
end if;
enc_dly <= enc_q(0);
if enc_q(0) = '1' and enc_dly = '0' then
if enc_q(1) = '0' then
enc_cnt <= enc_cnt + 1;
enc_cnt_flag <= '1';
enc_ts <= TIMESTAMP;
else
enc_cnt <= enc_cnt - 1;
enc_cnt_flag <= '1';
enc_ts <= TIMESTAMP;
end if;
end if;
if enc_idx_in = "011" and enc_idx_flag = '0' then
enc_idx <= enc_cnt;
enc_idx_flag <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 | a3af6aa430f4c422a83dab7a3a1e7a93 | 0.536173 | 2.953362 | false | false | false | false |
shvorin/pcie-emu | hdllib/common/ast256.vhd | 1 | 3,078 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.types.all;
use work.util.all;
-- ast stands for Avalon-ST
package ast256 is
type ast256half_t is record
data : qqword;
sop, eop : std_logic;
empty : std_logic;
end record;
type half_idx is (lo, hi);
type ast256half_array is array (half_idx) of ast256half_t;
type ast256mp_t is record
half : ast256half_array;
valid : std_logic;
end record;
function nothing return ast256mp_t;
subtype ast_t is ast256mp_t;
type ast_bp_t is record
ready : std_logic;
end record;
type ast_array is array (integer range <>) of ast_t;
type ast_bp_array is array (integer range <>) of ast_bp_t;
---------------------------------------------------------------------------
constant ast_raw_width : natural := 256 + 6;
subtype ast_raw_t is std_logic_vector(ast_raw_width - 1 downto 0);
function combine(a : ast_t) return ast_raw_t;
function parse(r : ast_raw_t; valid : std_logic) return ast_t;
---------------------------------------------------------------------------
component ast_io
port (
ast_rx : in ast_t;
ast_tx : out ast_t;
ast_tx_bp : in ast_bp_t;
rx_st_bardec : in std_logic_vector(7 downto 0);
--
clk : in std_logic;
reset : in std_logic);
end component;
end ast256;
package body ast256 is
function nothing return ast256half_t is
begin
return (data => (others => 'X'),
others => '0');
end;
function nothing return ast256mp_t is
begin
return ((nothing, nothing), '0');
end;
subtype asthalf_raw_t is std_logic_vector(128 + 3 - 1 downto 0);
function combine(h : ast256half_t) return asthalf_raw_t is
begin
return h.data & h.sop& h.eop & h.empty;
end;
function parse(r : asthalf_raw_t) return ast256half_t is
begin
return (data => r(128 + 3 - 1 downto 3),
sop => r(2), eop => r(1), empty => r(0));
end;
function refine(h : ast256half_t; valid : std_logic) return ast256half_t is
begin
return (
data => h.data,
sop => h.sop and valid,
eop => h.eop and valid,
empty => h.empty);
end;
function combine(a : ast_t) return ast_raw_t is
begin
return combine(a.half(lo)) & combine(a.half(hi));
end;
function parse(r : ast_raw_t; valid : std_logic) return ast_t is
begin
return (
half => (refine(parse(r(ast_raw_width - 1 downto ast_raw_width/2)), valid),
refine(parse(r(ast_raw_width/2 - 1 downto 0)), valid)),
valid => valid);
end;
end ast256;
| bsd-3-clause | ac9ca6c61bbcfbe3973eeea75baa93ac | 0.538986 | 3.525773 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaii_pcie_hip_components.vhd | 1 | 71,773 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAII_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- arriaii_pciehip_pciexp_dcfiforam
--
COMPONENT arriaii_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_hssi_pcie_hip
--
COMPONENT arriaii_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "arriaii_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end arriaii_pcie_hip_components;
package body ARRIAII_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end ARRIAII_PCIE_HIP_COMPONENTS;
| gpl-3.0 | 446b80034b2947b3dd2a3f6589a07ae3 | 0.522662 | 4.296498 | false | false | false | false |
thoralt/KCVGA | FPGA/SRAM_INTERFACE.vhd | 1 | 14,369 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.std_logic_unsigned."+";
USE IEEE.std_logic_unsigned."-";
USE IEEE.std_logic_unsigned."=";
ENTITY SRAM_INTERFACE IS
PORT
(
VGA_ADDR : IN STD_LOGIC_VECTOR (16 DOWNTO 0); -- address requested from VGA module
VGA_DATA : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); -- pixel data out to VGA module
VGA_ADDR_WR : IN STD_LOGIC; -- VGA address write input
VGA_FIFO_WR : OUT STD_LOGIC; -- VGA FIFO write output
VGA_FIFO_RST : OUT STD_LOGIC; -- VGA FIFO reset output
VGA_FIFO_FULL : IN STD_LOGIC;
KCVIDEO_ADDR : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
KCVIDEO_ADDR_WR : IN STD_LOGIC;
KCVIDEO_DATA : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- KCVIDEO pixel data in
KCVIDEO_FIFO_RD : OUT STD_LOGIC;
KCVIDEO_FIFO_EMPTY : IN STD_LOGIC;
PIC32_DATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- PIC32 address and data input
PIC32_FIFO_RD : OUT STD_LOGIC; -- PIC32 FIFO read output
PIC32_FIFO_EMPTY : IN STD_LOGIC; -- PIC32 FIFO empty input
A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output
D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output
nOE : OUT STD_LOGIC; -- SRAM output enable
nWE : OUT STD_LOGIC; -- SRAM write enable
nCE : OUT STD_LOGIC; --
nBLE : OUT STD_LOGIC; --
nBHE : OUT STD_LOGIC; --
reset : IN STD_LOGIC; -- RESET input
CLK : IN STD_LOGIC; -- master clock input 108 MHz
DEBUG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END SRAM_INTERFACE;
ARCHITECTURE Behavioral OF SRAM_INTERFACE IS
-- possible states of the SRAM state machine
--type SRAM_INTERFACE_STATE is (
-- idle, -- the SRAM interface is idle
-- VGA_READ1, -- reading data from SRAM into VGA FIFO,
-- -- address has been set up, data lines are high-Z,
-- -- now waiting for one clock cycle (one wait state)
-- VGA_READ2, -- read data word from SRAM, write data word to VGA FIFO,
-- -- increment address, start next read cycle
-- KCVIDEO_WRITE1, -- request next data word from KCVIDEO FIFO
-- KCVIDEO_WRITE2, -- set up data and address for SRAM write
-- KCVIDEO_WRITE3, -- write to SRAM
-- PIC32_WRITE1, -- wait for next data word from PIC32 FIFO
-- PIC32_WRITE2, -- wait for next data word from PIC32 FIFO
-- PIC32_WRITE3, -- set up data and address for SRAM write
-- PIC32_WRITE4 -- write to SRAM
--);
--
--type PIXEL_COUNT is (PIXEL1, PIXEL2, PIXEL3);
--
---- current state of the SRAM state machine
--signal current_state : SRAM_INTERFACE_STATE := idle;
--
--signal previous_VGA_ADDR_WR: STD_LOGIC;
--signal previous_KCVIDEO_ADDR_WR: STD_LOGIC;
--
---- current address being read from SRAM
--signal CURRENT_VGA_ADDR: STD_LOGIC_VECTOR(16 downto 0);
--
---- counter for remaining data words of current SRAM->VGA FIFO transfer
--signal VGA_PIXEL_COUNTER: integer range 0 to 320;
--signal VGA_SUBPIXEL: PIXEL_COUNT;
--
--signal DEBUG_i: STD_LOGIC_VECTOR(31 downto 0);
--signal CURRENT_KC_ADDR: STD_LOGIC_VECTOR(16 downto 0);
--signal KC_PIXEL_INDEX: PIXEL_COUNT;
--signal KCVIDEO_DATA_PREV1, KCVIDEO_DATA_PREV2: STD_LOGIC_VECTOR (4 downto 0);
BEGIN
-- DEBUG <= DEBUG_i;
--
-- -- clock = 108 MHz, 9.26 ns
-- process (nRESET, CLK)
-- begin
-- --========================================================================
-- -- RESET
-- --========================================================================
-- if reset = '1' then
-- current_state <= idle;
--
-- -- SRAM OE/WE/address/data inactive
-- nOE <= '1';
-- nWE <= '1';
-- D <= (others => 'Z');
-- A <= (others => 'Z');
--
-- DEBUG_i <= (others => '0');
-- CURRENT_VGA_ADDR <= (others => '0');
-- VGA_PIXEL_COUNTER <= 0;
-- previous_VGA_ADDR_WR <= '0';
-- VGA_FIFO_RST <= '1';
-- VGA_FIFO_WR <= '0';
-- previous_KCVIDEO_ADDR_WR <= '0';
-- KCVIDEO_FIFO_RD <= '0';
-- PIC32_FIFO_RD <= '0';
--
-- --========================================================================
-- -- Master clock 108 MHz rising edge
-- --========================================================================
-- elsif rising_edge(CLK) then
--
-- -- reset FIFO flags every cycle
-- VGA_FIFO_RST <= '0';
-- VGA_FIFO_WR <= '0';
-- PIC32_FIFO_RD <= '0';
--
-- ----------------------------------------------------------------------
-- -- central state machine begin
-- ----------------------------------------------------------------------
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- idle
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- if current_state = idle then
--
-- if not(VGA_PIXEL_COUNTER = 0) and VGA_FIFO_FULL = '0' then
-- -- need to fill VGA FIFO?
-- -- start SRAM read cycle
-- A <= CURRENT_VGA_ADDR;
-- D <= (others => 'Z');
-- nOE <= '0';
-- nWE <= '1';
-- current_state <= VGA_READ1;
--
-- -- new video input data available?
-- elsif KCVIDEO_FIFO_EMPTY = '0' then
-- -- request next data word from FIFO
-- KCVIDEO_FIFO_RD <= '1';
-- current_state <= KCVIDEO_WRITE1;
--
-- -- new PIC32 input data available?
-- elsif PIC32_FIFO_EMPTY = '0' then
-- -- request next data word from FIFO
-- PIC32_FIFO_RD <= '1';
--
-- -- prepare SRAM write
-- nWE <= '1';
-- nOE <= '1';
-- current_state <= PIC32_WRITE1;
-- end if;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- KCVIDEO_WRITE1
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = KCVIDEO_WRITE1 then
-- -- one wait state to wait for FIFO to deliver next data word
-- KCVIDEO_FIFO_RD <= '0';
-- current_state <= KCVIDEO_WRITE2; -- TODO: really necessary?
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- KCVIDEO_WRITE2
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = KCVIDEO_WRITE2 then
--
-- -- data layout in SRAM:
-- --
-- -- unused|<-pxl 2>-|<-pxl 1>-|<-pxl 0>-|
-- -- first| | | |
-- -- bit| | | |
-- -- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
-- -- |x|2|2|2|2|2|1|1|1|1|1|0|0|0|0|0|
-- -- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
--
-- if KC_PIXEL_INDEX = PIXEL1 then
-- KCVIDEO_DATA_PREV2 <= KCVIDEO_DATA;
-- KC_PIXEL_INDEX <= PIXEL2;
-- -- exit to idle state, we need two more pixels from FIFO
-- -- before we can start writing to SRAM
-- current_state <= idle;
--
-- elsif KC_PIXEL_INDEX = PIXEL2 then
-- KCVIDEO_DATA_PREV1 <= KCVIDEO_DATA;
-- KC_PIXEL_INDEX <= PIXEL3;
-- -- exit to idle state, we need one more pixel from FIFO
-- -- before we can start writing to SRAM
-- current_state <= idle;
--
-- elsif KC_PIXEL_INDEX = PIXEL3 then
-- A <= CURRENT_KC_ADDR;
-- D <= '0' & KCVIDEO_DATA & KCVIDEO_DATA_PREV1 & KCVIDEO_DATA_PREV2;
-- nWE <= '1';
-- nOE <= '1';
--
-- CURRENT_KC_ADDR <= CURRENT_KC_ADDR + 1;
-- KC_PIXEL_INDEX <= PIXEL1;
--
-- -- do not set nWE <= '0' since address/data is not yet stable
-- -- write cycle is started in next state
-- current_state <= KCVIDEO_WRITE3;
-- end if;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- KCVIDEO_WRITE3
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = KCVIDEO_WRITE3 then
-- nWE <= '0';
--
-- -- always exit to state "idle" to allow VGA output to fetch data
-- -- -> no back-to-back write since this could potentially block VGA
-- current_state <= idle;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- PIC32_WRITE1
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = PIC32_WRITE1 then
-- -- one wait state to wait for FIFO to deliver next data word
-- current_state <= PIC32_WRITE2;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- PIC32_WRITE2
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = PIC32_WRITE2 then
-- -- fetch address and data from FIFO
-- A <= '0' & PIC32_DATA(31 downto 16);
-- D <= PIC32_DATA(15 downto 0);
-- DEBUG_i <= PIC32_DATA;
-- current_state <= PIC32_WRITE3;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- PIC32_WRITE3
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = PIC32_WRITE3 then
-- nWE <= '0';
--
-- -- always exit to state "idle" to allow VGA output to fetch data
-- -- -> no back-to-back write since this could potentially block VGA
-- current_state <= idle;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- VGA_READ1
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = VGA_READ1 then
-- -- one wait state
-- current_state <= VGA_READ2;
--
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- -- VGA_READ2
-- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- elsif current_state = VGA_READ2 then
--
-- if VGA_SUBPIXEL = PIXEL1 then
-- VGA_DATA <= D(4 downto 0);
-- VGA_SUBPIXEL <= PIXEL2;
-- elsif VGA_SUBPIXEL = PIXEL2 then
-- VGA_DATA <= D(9 downto 5);
-- VGA_SUBPIXEL <= PIXEL3;
-- elsif VGA_SUBPIXEL = PIXEL3 then
-- VGA_DATA <= D(14 downto 10);
-- VGA_SUBPIXEL <= PIXEL1;
-- CURRENT_VGA_ADDR <= CURRENT_VGA_ADDR + 1;
-- nOE <= '1';
-- end if;
--
-- VGA_FIFO_WR <= '1'; -- write to FIFO
-- VGA_PIXEL_COUNTER <= VGA_PIXEL_COUNTER - 1; -- decrement counter
--
-- current_state <= idle;
--
-- ----------------------------------------------------------------------
-- -- end of state machine
-- ----------------------------------------------------------------------
-- end if;
--
-- -- read new VGA address and start filling the FIFO with one line
-- -- of video data (107 data words)
-- if previous_VGA_ADDR_WR = '0' and VGA_ADDR_WR = '1' then
-- CURRENT_VGA_ADDR <= VGA_ADDR;
-- VGA_PIXEL_COUNTER <= 320;
-- VGA_SUBPIXEL <= PIXEL1;
-- VGA_FIFO_RST <= '1'; -- reset FIFO
-- end if;
-- previous_VGA_ADDR_WR <= VGA_ADDR_WR;
--
-- -- read new KC VIDEO address
-- if previous_KCVIDEO_ADDR_WR = '0' and KCVIDEO_ADDR_WR = '1' then
-- CURRENT_KC_ADDR <= KCVIDEO_ADDR;
-- KC_PIXEL_INDEX <= PIXEL1;
-- end if;
-- previous_KCVIDEO_ADDR_WR <= KCVIDEO_ADDR_WR;
--
-- end if;
-- end process;
END Behavioral;
| mit | 1a57573d2a6cee9b979b77db0b6e4b9e | 0.35841 | 3.915259 | false | false | false | false |
alvieboy/xtc-base | xtc_top_sdram.vhd | 1 | 6,319 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
entity xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
-- DMA
dmawbi: in wb_mosi_type;
dmawbo: out wb_miso_type;
-- SDRAM signals
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity;
architecture behave of xtc_top_sdram is
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_tago: std_logic_vector(31 downto 0);
signal wb_tagi: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_stall: std_logic;
--signal rstreq: std_logic;
component sdram_ctrl is
generic (
HIGH_BIT: integer := 24
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
dbg: out memory_debug_type;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component;
signal wbo,romwbo,bootwbo,sdramorbootwbo,ramwbo,piowbo,sdram_wbo,cpu_sdram_wbo: wb_mosi_type;
signal wbi,romwbi,bootwbi,sdramorbootwbi,ramwbi,piowbi,sdram_wbi,cpu_sdram_wbi: wb_miso_type;
signal edbg: memory_debug_type;
begin
sdram_wbi.err <= '0';
sdram_wbi.int <= '0';
cpu: entity work.xtc
port map (
wb_syscon => wb_syscon,
-- Master wishbone interface
wbo => ramwbo,
wbi => ramwbi,
-- ROM wb interface
romwbo => romwbo,
romwbi => romwbi,
nmi => nmi,
nmiack => nmiack,
rstreq => rstreq,
edbg => edbg
);
data_mux_io: entity work.xtc_wbmux2
generic map (
select_line => 31,
address_high => 31,
address_low => 2
)
port map (
wb_syscon => wb_syscon,
-- Master
m_wbi => ramwbo,
m_wbo => ramwbi,
-- Slave 0 signals
s0_wbi => wbi,
s0_wbo => wbo,
-- Slave 0 signals
s1_wbi => piowbi,
s1_wbo => piowbo
);
dma_arb: entity work.wbarb2_1
port map (
wb_syscon => wb_syscon,
-- Master 0 signals
m0_wbi => cpu_sdram_wbo,
m0_wbo => cpu_sdram_wbi,
-- Master 1 signals
m1_wbi => dmawbi,
m1_wbo => dmawbo,
-- Slave signals
s0_wbi => sdram_wbi,
s0_wbo => sdram_wbo
);
--ramwbi.int <= iowbi.int;
i_d_arb: entity work.wbarb2_1
port map (
wb_syscon => wb_syscon,
-- Master 0 signals
m0_wbi => wbo,
m0_wbo => wbi,
-- Master 1 signals
m1_wbi => romwbo,
m1_wbo => romwbi,
-- Slave signals
s0_wbi => sdramorbootwbi,
s0_wbo => sdramorbootwbo
);
boot_sdram_mux: entity work.xtc_wbmux2
generic map (
select_line => 30,
address_high => 31,
address_low => 2
)
port map (
wb_syscon => wb_syscon,
-- Master
m_wbi => sdramorbootwbo,
m_wbo => sdramorbootwbi,
-- Slave 0 signals
s0_wbi => cpu_sdram_wbi,
s0_wbo => cpu_sdram_wbo,
-- Slave 0 signals
s1_wbi => bootwbi,
s1_wbo => bootwbo
);
bootrom: entity work.bootrom
port map (
syscon => wb_syscon,
wbi => bootwbo,
wbo => bootwbi
);
ioadaptor: entity work.wb_master_p_to_slave_np
port map (
syscon => wb_syscon,
mwbo => piowbi,
mwbi => piowbo,
swbi => iowbi,
swbo => iowbo
);
sdramcrtl_inst: entity work.sdram_ctrl
generic map (
HIGH_BIT => 22
)
port map (
wb_clk_i => wb_syscon.clk,
wb_rst_i => wb_syscon.rst,
wb_dat_o => sdram_wbi.dat,
wb_dat_i => sdram_wbo.dat,
wb_adr_i => sdram_wbo.adr,
wb_we_i => sdram_wbo.we,
wb_cyc_i => sdram_wbo.cyc,
wb_stb_i => sdram_wbo.stb,
wb_sel_i => sdram_wbo.sel,
wb_tag_i => sdram_wbo.tag,
wb_ack_o => sdram_wbi.ack,
wb_stall_o => sdram_wbi.stall,
wb_tag_o => sdram_wbi.tag,
dbg => edbg,
-- extra clocking
clk_off_3ns => clk_off_3ns,
-- SDRAM signals
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
end behave;
| bsd-3-clause | 7fda879669e4c8aded86cb0d2da847e7 | 0.53537 | 3.011916 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/maxv_components.vhd | 1 | 9,555 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxv_atom_pack.all;
package maxv_components is
--
-- maxv_jtag
--
COMPONENT maxv_jtag
generic (
lpm_type : string := "maxv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- maxv_lcell
--
COMPONENT maxv_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "maxv_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- maxv_ufm
--
COMPONENT maxv_ufm
generic (
address_width : integer := 9;
init_file : string := "none";
lpm_type : string := "maxv_ufm";
mem1 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem2 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem3 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem4 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem5 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem6 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem7 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem8 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem9 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem10 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem11 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem12 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem13 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem14 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem15 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem16 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
osc_sim_setting : integer := 180000; -- default osc frequency to 5.56MHz
program_time : integer := 1600000; -- default program_time is 1600ns
erase_time : integer := 500000000; -- default erase time is 500us
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_program_busy_posedge: VitalDelayType01 := DefPropDelay01;
tpd_erase_busy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_drclk_drdout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_oscena_osc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sbdin_sbdout : VitalDelayType01 := DefPropDelay01;
tsetup_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_program_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_erase_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_program_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_erase_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_program_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_erase_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_program_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_erase_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tipd_program : VitalDelayType01 := DefPropDelay01;
tipd_erase : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01;
tipd_arclk : VitalDelayType01 := DefPropDelay01;
tipd_arshft : VitalDelayType01 := DefPropDelay01;
tipd_ardin : VitalDelayType01 := DefPropDelay01;
tipd_drclk : VitalDelayType01 := DefPropDelay01;
tipd_drshft : VitalDelayType01 := DefPropDelay01;
tipd_drdin : VitalDelayType01 := DefPropDelay01;
tipd_sbdin : VitalDelayType01 := DefPropDelay01
);
port (
program : in std_logic := '0';
erase : in std_logic := '0';
oscena : in std_logic;
arclk : in std_logic;
arshft : in std_logic;
ardin : in std_logic;
drclk : in std_logic;
drshft : in std_logic;
drdin : in std_logic := '0';
sbdin : in std_logic := '0';
devclrn : in std_logic := '1'; -- simulation only port
devpor : in std_logic := '1'; -- simulation only port
ctrl_bgpbusy : in std_logic := '0'; -- simulation only port, to control
busy : out std_logic;
osc : out std_logic := 'X';
drdout : out std_logic;
sbdout : out std_logic;
bgpbusy : out std_logic);
END COMPONENT;
--
-- maxv_io
--
COMPONENT maxv_io
generic(
lpm_type : STRING := "maxv_io";
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01
);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
padio : inout STD_LOGIC;
combout : out STD_LOGIC
);
END COMPONENT;
--
-- maxv_routing_wire
--
COMPONENT maxv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end maxv_components;
| gpl-3.0 | 5af0c6a74337b66b163f3e88a7416dce | 0.567138 | 3.924025 | false | false | false | false |
alvieboy/xtc-base | sinkdev.vhd | 1 | 701 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity sinkdev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end entity sinkdev;
architecture behave of sinkdev is
signal ack,err: std_logic;
begin
wbo.ack<=ack;
wbo.err<='0';
wbo.dat<=(others => 'X');
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
ack<='0';
else
ack<='0';
--err<='0';
if ack='0' and wbi.stb='1' and wbi.cyc='1' then
ack<='1';
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | b9a709b0a316c90de4984ab6e47af6eb | 0.570613 | 3.129464 | false | false | false | false |
keith-epidev/md2x | build/code/n_register.vhdl | 1 | 599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end n_register;
architecture arch of n_register is
signal data : std_logic_vector(width-1 downto 0);
begin
output <= data;
latch: process (clk,input,rst)
begin
if (rst = '1') then
data <= (others=>'0');
else if (clk'event and clk = '1') then
data <= input;
end if;
end if;
end process ;
end arch;
| gpl-2.0 | 82beb8e343b4ff90e4519c531852f861 | 0.659432 | 2.722727 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_io_d.vhd | 1 | 5,344 | -------------------------------------------------------------------------------
--
-- The D port controller.
--
-- $Id: t400_io_d.vhd,v 1.2 2006-05-07 02:24:16 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_d is
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_d_op_t;
bd_i : in bd_t;
-- Port D Interface -------------------------------------------------------
io_d_o : out dw_t;
io_d_en_o : out dw_t
);
end t400_io_d;
use work.t400_io_pack.all;
architecture rtl of t400_io_d is
signal d_q : dw_t;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process d_reg
--
-- Purpose:
-- Implements the D output register.
--
d_reg: process (ck_i, por_i)
begin
if por_i then
d_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
d_q <= (others => '0');
elsif ck_en_i then
if op_i = IOD_LOAD then
d_q <= bd_i;
end if;
end if;
end if;
end process d_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (d_q,
vdd_s)
begin
-- bit 3
io_d_o(3) <= io_out_f(dat => d_q(3),
opt => opt_out_type_3_g);
io_d_en_o(3) <= io_en_f (en => vdd_s, dat => d_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_d_o(2) <= io_out_f(dat => d_q(2),
opt => opt_out_type_2_g);
io_d_en_o(2) <= io_en_f (en => vdd_s, dat => d_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_d_o(1) <= io_out_f(dat => d_q(1),
opt => opt_out_type_1_g);
io_d_en_o(1) <= io_en_f (en => vdd_s, dat => d_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_d_o(0) <= io_out_f(dat => d_q(0),
opt => opt_out_type_0_g);
io_d_en_o(0) <= io_en_f (en => vdd_s, dat => d_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 9ad2bb3155c7070cdfe8f34b027525cd | 0.505988 | 3.752809 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/altera_primitives_components.vhd | 1 | 14,222 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
----------------------------------------------------------------------------
-- ALtera Primitives Component Declaration File
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package dffeas_pack is
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
end dffeas_pack;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.dffeas_pack.all;
package altera_primitives_components is
component carry
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component cascade
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component global
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component tri
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end component;
component carry_sum
port (
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic );
end component;
component exp
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component soft
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component opndrn
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component row_global
port (
a_in : in std_logic;
a_out : out std_logic );
end component;
component lut_input
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component lut_output
port(
a_in : in std_logic;
a_out : out std_logic);
end component;
component dlatch
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end component;
component latch
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end component;
component dff
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffe
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component dffea
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;
component tff
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component tffe
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkff
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component jkffe
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srff
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
component srffe
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end component;
component clklock
generic(
input_frequency : natural := 10000;
clockboost : natural := 1);
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component alt_inbuf
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_tri
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end component;
component alt_iobuf
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
component alt_inbuf_diff
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end component;
component alt_outbuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_outbuf_tri_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic );
end component;
component alt_iobuf_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic );
end component;
component alt_bidir_diff
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic );
end component;
component alt_bidir_buf
generic (
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic );
end component;
end altera_primitives_components;
| gpl-3.0 | 18d50930d54d060be6e0221529c23cfa | 0.52693 | 3.898575 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/simulation/bmg_stim_gen.vhd | 1 | 12,651 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (127 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"instructionMemory.mif",
DEFAULT_DATA,
32,
128);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>128 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(31 DOWNTO 0) <= READ_ADDR(31 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 128 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
ENA <= DO_READ ;
END ARCHITECTURE;
| gpl-3.0 | 227d5813a1c11a5d2f345cdd1f65e6ae | 0.54715 | 3.688338 | false | false | false | false |
SonicFrog/CPU | ALU.vhd | 1 | 3,436 | -- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Full Version"
-- CREATED "Thu Sep 30 08:49:10 2010"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY alu IS
PORT
(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
op : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END alu;
ARCHITECTURE bdf_type OF alu IS
COMPONENT add_sub
PORT(sub_mode : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
carry : OUT STD_LOGIC;
zero : OUT STD_LOGIC;
r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT comparator
PORT(carry : IN STD_LOGIC;
zero : IN STD_LOGIC;
a_31 : IN STD_LOGIC;
b_31 : IN STD_LOGIC;
diff_31 : IN STD_LOGIC;
op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
r : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT logic_unit
PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
op : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(i0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT shift_unit
PORT(a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
op : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
r : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL addsub : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL carry : STD_LOGIC;
SIGNAL comp_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL logic_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL shift_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL zero : STD_LOGIC;
BEGIN
b2v_add_sub_0 : add_sub
PORT MAP(sub_mode => op(3),
a => a,
b => b,
carry => carry,
zero => zero,
r => addsub);
b2v_comparator_0 : comparator
PORT MAP(carry => carry,
zero => zero,
a_31 => a(31),
b_31 => b(31),
diff_31 => addsub(31),
op => op(2 DOWNTO 0),
r => comp_r(0));
b2v_logic_unit_0 : logic_unit
PORT MAP(a => a,
b => b,
op => op(1 DOWNTO 0),
r => logic_r);
b2v_multiplexer_0 : multiplexer
PORT MAP(i0 => addsub,
i1 => comp_r,
i2 => logic_r,
i3 => shift_r,
sel => op(5 DOWNTO 4),
o => s);
b2v_shift_unit_0 : shift_unit
PORT MAP(a => a,
b => b(4 DOWNTO 0),
op => op(2 DOWNTO 0),
r => shift_r);
comp_r(31 DOWNTO 1) <= "0000000000000000000000000000000";
END bdf_type; | gpl-2.0 | e8bab4de160d0ff29ad7bd9bbe2cc78c | 0.663271 | 3.05151 | false | false | false | false |
SonicFrog/CPU | multiplexer.vhd | 1 | 734 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplexer is
port(
i0 : in std_logic_vector(31 downto 0);
i1 : in std_logic_vector(31 downto 0);
i2 : in std_logic_vector(31 downto 0);
i3 : in std_logic_vector(31 downto 0);
sel : in std_logic_vector( 1 downto 0);
o : out std_logic_vector(31 downto 0)
);
end multiplexer;
architecture synth of multiplexer is
begin
process(i0, i1, i2, i3, sel)
begin
case sel is
when "00" => o <= i0;
when "01" => o <= i1;
when "10" => o <= i2;
when "11" => o <= i3;
when others =>
end case;
end process;
end synth;
| gpl-2.0 | a4ee80e5ceedbffc9cc4a51d4dda8ad2 | 0.573569 | 2.98374 | false | false | false | false |
nikste/visualizationDemo | zeppelin-web/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 | 00803ec0ebb797b4ead2d048e6d70328 | 0.477108 | 4.08867 | false | false | false | false |
bluemurder/chaotic-rngs | rng08-vhdl/testCaosComb.vhd | 1 | 2,587 | --------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 16:27:59 10/06/2011
-- Design Name:
-- Module Name: testCaosComb.vhd
-- Project Name: Caos
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CaosComb
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testCaosComb IS
END testCaosComb;
ARCHITECTURE behavior OF testCaosComb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CaosComb
PORT(
res : IN std_logic;
out0 : OUT std_logic
);
END COMPONENT;
--Inputs
signal ck : std_logic := '0';
signal res : std_logic := '0';
--Outputs
signal out0 : std_logic;
constant ck_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CaosComb PORT MAP (
res => res,
out0 => out0
);
-- Clock process definitions
ck_process :process
begin
ck <= '0';
wait for ck_period/2;
ck <= '1';
wait for ck_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
res <= '1';
wait for 100 ns;
res<='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (ck) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(ck) then
if res = '0' then
write(my_output_line,out0);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit | 54888f80e6daf7209345a4020e0e6859 | 0.572864 | 4.017081 | false | true | false | false |
bluemurder/chaotic-rngs | rng08-vhdl/CaosComb.vhd | 1 | 2,285 | ----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosComb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosComb is
Port ( res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosComb;
architecture Behavioral of CaosComb is
-- Integer part is ALWAYS 2 bits
constant nbit : integer := 128; -- total bits num
signal reg_in : signed(nbit-1 downto 0);
signal reg_out : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := (others => '0');
constant one : signed(nbit-1 downto 0) := (nbit-2 => '1', others => '0');
constant minusone : signed(nbit-1 downto 0) := (nbit-1 => '1', nbit-2 => '1', others => '0');
-- x0 = 0.5
constant x0 : signed(nbit-1 downto 0) := (nbit-3 => '1', others => '0');
begin
-- only sign of register in output
out0 <= reg_out(nbit-1);
-- map
proc_map: process(reg_in)
begin
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg_in < zero) then
-- if reg<1, reg = 1.875 * reg + 1
reg_out <= (( reg_in(nbit-2 downto 0) & '0' ) - ( "111" & reg_in(nbit-1 downto 3) )) + one;
else
-- else, reg = 1.875 * reg - 1
reg_out <= (( reg_in(nbit-2 downto 0)&'0' ) - ( "000" & reg_in(nbit-1 downto 3) )) + minusone;
end if;
end process;
-- init condition and loop processing
proc_loop: process(reg_out,res)
begin
if res = '0' then
-- normal behavior (loop)
reg_in <= reg_out;
else
-- if reset, init with specified x0
reg_in <= x0;
end if;
end process;
end Behavioral; | mit | 5421da33fd7e685791d6281f688f27ca | 0.513786 | 3.472644 | false | false | false | false |
SonicFrog/CPU | controller.vhd | 1 | 7,643 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clk : in std_logic;
reset_n : in std_logic;
-- instruction opcode
op : in std_logic_vector(5 downto 0);
opx : in std_logic_vector(5 downto 0);
-- activates branch condition
branch_op : out std_logic;
-- immediate value sign extention
imm_signed : out std_logic;
-- instruction register enable
ir_en : out std_logic;
-- PC control signals
pc_add_imm : out std_logic;
pc_en : out std_logic;
pc_sel_a : out std_logic;
pc_sel_imm : out std_logic;
-- register file enable
rf_wren : out std_logic;
-- multiplexers selections
sel_addr : out std_logic;
sel_b : out std_logic;
sel_mem : out std_logic;
sel_pc : out std_logic;
sel_ra : out std_logic;
sel_rC : out std_logic;
-- write memory output
read : out std_logic;
write : out std_logic;
-- alu op
op_alu : out std_logic_vector(5 downto 0)
);
end controller;
architecture synth of controller is
type state is (fetch1, fetch2, decode, r_op, store, break, load1, load2, i_op, branch, call, jmp, ur_op, ui_op);
signal current_state, future_state : state;
begin
process(clk)
begin
if(reset_n = '0') then
current_state <= fetch1;
elsif(rising_edge(clk)) then
current_state <= future_state;
end if;
end process;
process(current_state, op, opx)
begin
future_state <= current_state;
read <= '0';
write <= '0';
branch_op <= '0';
imm_signed <= '0';
pc_sel_a <= '0';
pc_sel_imm <= '0';
pc_add_imm <= '0';
sel_pc <= '0';
sel_ra <= '0';
ir_en <= '0';
pc_en <= '0';
imm_signed <= '0';
sel_b <= '0';
sel_addr <= '0';
sel_rC <= '0';
sel_mem <= '0';
op_alu <= (others => '0');
rf_wren <= '0';
case current_state is
when fetch1 =>
read <= '1';
future_state <= fetch2;
when fetch2 =>
pc_en <= '1';
ir_en <= '1';
future_state <= decode;
when decode =>
case "00" & op is
when X"3A" => -- R_OP
case "00" & opx is
when X"34" =>
future_state <= break;
when X"0D" | X"05" =>
future_state <= jmp;
when others =>
case "00" & opx is
when X"12" | X"1A" | X"3A" =>
-- R_OP avec opérande non signée
future_state <= ur_op;
when others =>
future_state <= r_op;
end case;
end case;
when X"17" => -- Load word
future_state <= load1;
when X"15" => -- Store word
future_state <= store;
when X"04" => -- Operande imm avec signe
future_state <= i_op;
when X"0C" |
X"14" |
X"1C" => --Operande imm sans signe
future_state <= ui_op;
when X"06" |
X"0E" |
X"16" |
X"1E" |
X"26" |
X"2E" |
X"36" => -- Opération de branching
future_state <= branch;
when X"00" => -- Instruction call
future_state <= call ;
when others =>
future_state <= fetch1;
end case;
when r_op =>
rf_wren <= '1';
sel_mem <= '0';
sel_pc <= '0';
sel_b <= '1';
sel_rC <= '1';
case "00" & opx is
when X"1B" =>
-- srl
op_alu <= "110011";
when X"0E" =>
-- and
op_alu <= "100001";
when X"31" =>
--add
op_alu <= (others => '0');
when X"39" =>
--sub
op_alu <= "001000";
when X"08" =>
--cmpge
op_alu <= "011001";
when X"10" =>
--cmplt
op_alu <= "011010";
when X"06" =>
--nor
op_alu <= "100000";
when X"16" =>
--or
op_alu <= "100010";
when X"1E" =>
--xor
op_alu <= "100011";
when X"13" =>
--sll
op_alu <= "110010";
when X"3B" =>
--sra
op_alu <= "110111";
when others =>
end case;
-- Skip fetch1
read <= '1';
future_state <= fetch2;
when store =>
sel_b <= '0';
sel_addr <= '1';
write <= '1';
imm_signed <= '1';
future_state <= fetch1;
when break =>
future_state <= break;
when load1 =>
imm_signed <= '1';
sel_b <= '0';
op_alu <= (others => '0');
read <= '1';
sel_addr <= '1';
future_state <= load2;
when load2 =>
sel_rC <= '0';
sel_mem <= '1';
rf_wren <= '1';
-- Skip fetch1
read <= '1';
future_state <= fetch2;
when i_op =>
rf_wren <= '1';
future_state <= fetch1;
case "00" & op is
when X"04" => -- addi
op_alu <= (others => '0');
imm_signed <= '1';
when X"0C" | X"14" | X"1C" => --Opération non signée
future_state <= ur_op;
when others =>
rf_wren <= '0';
end case;
-- Skip fetch1
read <= '1';
future_state <= fetch2;
when ur_op =>
-- Execution des instructions r-type avec
-- opérande non signées
rf_wren <= '1';
sel_rC <= '1';
imm_signed <= '0';
case "00" & opx is
when X"12" => -- slli
op_alu <= "110010";
when X"1A" => -- srli
op_alu <= "110011";
when X"3A" => -- srai
op_alu <= "111111";
when others =>
end case;
-- Skip fetch1
read <= '1';
future_state <= fetch2;
when ui_op =>
--Execution des instructions i_type avec
-- opérande non signée
rf_wren <= '1';
sel_rc <= '0';
imm_signed <= '0';
future_state <= fetch1;
case "00" & op is
when X"0C" => -- andi
op_alu <= "100001";
when X"14" => -- ori
op_alu <= "100010";
when X"1C" => -- xori
op_alu <= "100011";
when others =>
end case;
-- Skip fetch1
read <= '1';
future_state <= fetch2;
when branch =>
future_state <= fetch1;
branch_op <= '1';
sel_b <= '1';
-- pc_en <= '1' ;
-- N'est pas activé sur le pdf
pc_add_imm <= '1';
-- L'instruction content IMM16, donc on
-- ajoute tout de suite l'adresse dans le pc
-- Géré dans un process à part
case "00" & op is
when X"06" =>
-- br
op_alu <= "011100";
when X"0E" =>
-- bge
-- A >= B
op_alu <= "011001" ;
when X"16" =>
-- blt
-- A < B
op_alu <= "011010" ;
when X"1E" =>
-- bne
-- A != B
op_alu <= "011011" ;
when X"26" =>
-- beq
-- A == B
op_alu <= "011100" ;
when X"2E" =>
-- bgeu
-- unsigned A >= unsigned B
op_alu <= "011101" ;
when X"36" =>
-- bltu
-- unsigned A < unsigned B
op_alu <= "011110" ;
when others =>
branch_op <= '0' ;
sel_b <= '0' ;
end case;
when call => --Store the current pc address in the ra register
pc_en <= '1';
sel_ra <= '1';
sel_rC <= '0';
rf_wren <= '1';
sel_mem <= '0';
sel_pc <= '1';
pc_sel_imm <= '1';
future_state <= fetch1;
when jmp => --Jumps at the address contained in the given register
pc_sel_a <= '1';
pc_en <= '1';
future_state <= fetch1;
when others =>
future_state <= fetch1;
end case;
end process;
end synth;
| gpl-2.0 | a45d247eff6fb2d57675ee887d82face | 0.453211 | 2.967717 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/example_design/instructionMemory_exdes.vhd | 1 | 4,503 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionMemory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionMemory_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END instructionMemory_exdes;
ARCHITECTURE xilinx OF instructionMemory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instructionMemory IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : instructionMemory
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | dbd747ff0527223e2262e19ffb501efd | 0.576505 | 4.878657 | false | false | false | false |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/raw2rgb/onchip_fifo.vhd | 2 | 6,420 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: test_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.2 Build 222 07/20/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY onchip_fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END onchip_fifo;
ARCHITECTURE SYN OF onchip_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone V",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 12,
lpm_widthu => 11,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "12"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "12"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | a064039e01d4482793f581166e759af1 | 0.667601 | 3.631222 | false | false | false | false |
bluemurder/chaotic-rngs | rng07-vhdl/chaoticMap.vhd | 2 | 1,546 | -- This block describes the chaotic map used for the random generator --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end chaoticMap;
architecture Behavioral of chaoticMap is
-- Supposing 2 integer bits and two's complement, the constants
-- correspond to zero, one and minus one values
constant zero : signed(N_BIT-1 downto 0) := (others => '0');
constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => '1', others => '0');
constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => '1', N_BIT-2 => '1', others => '0');
-- Stores the current state
signal reg : signed(N_BIT-1 downto 0);
begin
-- update map
proc_map: process(clk,reset)
begin
if reset = '0' then
if rising_edge(clk) then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(N_BIT-2 downto 0) & '0' ) - ( "111" & reg(N_BIT-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(N_BIT-2 downto 0)&'0' ) - ( "000" & reg(N_BIT-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= X0;
end if;
end process;
output <= reg(N_BIT-1);
end Behavioral;
| mit | 6504e7b8c488b560ed474d4c95cae59c | 0.516818 | 3.310493 | false | false | false | false |
bluemurder/chaotic-rngs | rng02-vhdl/CaosAlAl.vhd | 1 | 1,808 | ----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosAlAl is
generic (nbit : integer := 32);
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
signal reg : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := "00000000000000000000000000000000";
constant one : signed(nbit-1 downto 0) := "01000000000000000000000000000000";
constant minusone : signed(nbit-1 downto 0) := "11000000000000000000000000000000";
constant x0 : signed(nbit-1 downto 0) := "00100000000000000000000000000000";
begin
out0 <= reg(nbit-1);
main:process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
if (reg < zero) then
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
end Behavioral; | mit | 33860e56490dad097ac11a49728b882e | 0.552544 | 3.830508 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/dataMemory/simulation/dataMemory_tb.vhd | 1 | 4,334 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: dataMemory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dataMemory_tb IS
END ENTITY;
ARCHITECTURE dataMemory_tb_ARCH OF dataMemory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
dataMemory_synth_inst:ENTITY work.dataMemory_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | f23b5d1dba2d431a727e4b31c1a93df1 | 0.621597 | 4.690476 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/example_design/instructionMemory_prod.vhd | 1 | 10,048 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instructionMemory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 1
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instructionMemory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 128
-- C_READ_DEPTH_A : 128
-- C_ADDRA_WIDTH : 32
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 128
-- C_READ_DEPTH_B : 128
-- C_ADDRB_WIDTH : 32
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionMemory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instructionMemory_prod;
ARCHITECTURE xilinx OF instructionMemory_prod IS
COMPONENT instructionMemory_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instructionMemory_exdes
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 5887aaaec0413fe07a8ed6314fee74af | 0.497512 | 3.87057 | false | false | false | false |
DigitalBrains1/clash-lt24-quartus | lt24/brwrap.vhd | 1 | 3,830 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY blockramwrapper IS
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR;
data_b : IN STD_LOGIC_VECTOR;
q_a : OUT STD_LOGIC_VECTOR;
wren_b : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR;
data_a : IN STD_LOGIC_VECTOR;
q_b : OUT STD_LOGIC_VECTOR
);
END blockramwrapper;
ARCHITECTURE SYN OF blockramwrapper IS
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR;
data_b : IN STD_LOGIC_VECTOR;
q_a : OUT STD_LOGIC_VECTOR;
wren_b : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR;
data_a : IN STD_LOGIC_VECTOR;
q_b : OUT STD_LOGIC_VECTOR
);
END COMPONENT;
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => address_reg_b,
clock_enable_input_a => clock_enable_input_a,
clock_enable_input_b => clock_enable_input_b,
clock_enable_output_a => clock_enable_output_a,
clock_enable_output_b => clock_enable_output_b,
indata_reg_b => indata_reg_b,
intended_device_family => intended_device_family,
lpm_type => lpm_type,
numwords_a => numwords_a,
numwords_b => numwords_b,
operation_mode => operation_mode,
outdata_aclr_a => outdata_aclr_a,
outdata_aclr_b => outdata_aclr_b,
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => power_up_uninitialized,
ram_block_type => ram_block_type,
read_during_write_mode_mixed_ports => read_during_write_mode_mixed_ports,
read_during_write_mode_port_a => read_during_write_mode_port_a,
read_during_write_mode_port_b => read_during_write_mode_port_b,
widthad_a => widthad_a,
widthad_b => widthad_b,
width_a => width_a,
width_b => width_b,
width_byteena_a => width_byteena_a,
width_byteena_b => width_byteena_b,
wrcontrol_wraddress_reg_b => wrcontrol_wraddress_reg_b
)
PORT MAP (
clock0 => clock0,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => q_a,
q_b => q_b
);
END SYN; | bsd-2-clause | a1efb5cb8c891c04e1efa2718c6656bb | 0.665013 | 2.534745 | false | false | false | false |
SonicFrog/CPU | add_sub.vhd | 1 | 1,520 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add_sub is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
sub_mode : in std_logic;
carry : out std_logic;
zero : out std_logic;
r : out std_logic_vector(31 downto 0)
);
end add_sub;
architecture synth of add_sub is
signal b_s : std_logic_vector(31 downto 0);
signal result : std_logic_vector(32 downto 0);
begin
-- b_s is the output of the xor between b and sub_mode.
-- here a vector of 32 bits of sub_mode has been created
b_s <= b xor (31 downto 0 => sub_mode);
-- result of the adder will be on 33 bits to keep the carry.
-- Using the unsigned library, at least the left operand should have the same bitwidht
-- than the result. This is done for a and b by concatenating a 0 on the most significant bit.
-- sub_mode will be converted by the unsigned library to match
-- the others operand sizes.
result <= ('0' & a) + ('0' & b_s) + sub_mode;
-- The carry is extracted from the most significant bit of the result
carry <= result(32);
-- the r output is the 32 least significant bits of result
r <= result(31 downto 0);
-- zero is 1 when r=0. r is an output, it can't be read.
-- We have to compare the 32 least significant bits of result
zero <= '1' when result(31 downto 0)=0 else '0';
end synth;
| gpl-2.0 | d13577b2f3dd0522ac6e9e026be94315 | 0.631579 | 3.543124 | false | false | false | false |
bluemurder/chaotic-rngs | rng01-vhdl/newCaoticGen2.vhd | 1 | 1,601 | ----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 11:06:29 07/26/2011
-- Design Name:
-- Module Name: newCaoticGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
use work.variable_Caos.all ;
entity newCaoticGen2 is
Port ( Clk : in STD_LOGIC;
reset : IN std_logic;
X_out : out signed(numbit-1 downto 0));
end newCaoticGen2;
architecture Behavioral of newCaoticGen2 is
signal x : signed(numbit-1 downto 0):= signed(convtosigned(Val_init));
begin
process(Clk,reset)
variable k : signed(numbit-1 downto 0):= signed(convtosigned(Param));
variable temp: integer;
begin
X_out <= x;
if reset = '0' then
if (Clk'event and Clk ='1') then
if (x < conv_signed(0,numBit)) then
temp:=mult(k,x);
x <= conv_signed(2**(scalamento) + temp,numBit);
temp := 0;
else
temp:=mult(k,x);
x <= conv_signed(-2**(scalamento)+temp,numBit);
temp:=0;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | cb225b5910ab00ea323092d1ace4ca30 | 0.532792 | 3.573661 | false | false | false | false |
bluemurder/chaotic-rngs | rng05-vhdl/template.vhd | 1 | 3,148 | ----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CaosAlAl is
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
ready : out STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
-- Integer part is ALWAYS 2 bits
constant nbit : integer := 128; -- total bits num
constant skip : integer := 9;
signal reg : signed(nbit-1 downto 0);
signal counter : integer range 0 to skip := 0;
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := (others => '0');
constant one : signed(nbit-1 downto 0) := (nbit-2 => '1', others => '0');
constant minusone : signed(nbit-1 downto 0) := (nbit-1 => '1', nbit-2 => '1', others => '0');
-- x0 = 0.5
constant x0 : signed(nbit-1 downto 0) := (nbit-3 => '1', others => '0');
function minimum (a,b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
begin
-- 1 when positive, 0 otherwise
--out0 <= not(reg(nbit-1)) when rising_edge(ck) and counter = 0;
out0 <= not(reg(nbit-1)) when rising_edge(ck); --and counter = skip;
--ready <= '1' when counter = minimum(1,skip) else
ready <= '1' when counter = skip else
'0';
proc_map: process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
proc_counter: process(ck,res,counter)
begin
if res = '1' then
counter <= 0;
elsif rising_edge(ck) then
if counter = skip then
counter <= 0;
else
counter <= counter+1;
end if;
end if;
end process;
end Behavioral; | mit | cff1de048c77f1584b0daefe02694697 | 0.502224 | 3.752086 | false | false | false | false |
SonicFrog/CPU | comparator.vhd | 1 | 1,230 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port (
a_31 : in std_logic;
b_31 : in std_logic;
diff_31 : in std_logic;
carry : in std_logic;
zero : in std_logic;
op : in std_logic_vector( 2 downto 0);
r : out std_logic
);
end comparator;
architecture synth of comparator is
begin
process (op, zero, carry, a_31, b_31, diff_31)
begin
-- all bits to 0
r <= zero;
-- here we modify only the least significant bit.
case op is
-- >=
when "001" =>
-- take care to surround all logical operation with parenthesis:
-- there's no priority between them.
r <= (not a_31 and b_31) or ((not a_31 xor b_31) and not diff_31);
-- <
when "010" =>
r <= (a_31 and not b_31) or ((not a_31 xor b_31) and diff_31);
-- !=
when "011" => r <= not zero;
-- >= unsigned
when "101" => r <= carry;
-- < unsigned
when "110" => r <= not carry;
-- 0, 4, 7: =
when others => r <= zero;
end case;
end process;
end synth;
| gpl-2.0 | 4834abb4ff7d6bd6a65c18b28100627f | 0.511382 | 3.360656 | false | false | false | false |
bluemurder/chaotic-rngs | rng01-vhdl/variable_Caos.vhd | 1 | 2,024 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0';
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
return res;
end function;
end variable_Caos;
| mit | 1475f5b3c82f640293a73f031ef51775 | 0.583004 | 3.2384 | false | false | false | false |
SonicFrog/CPU | FPGA4U.vhd | 1 | 4,395 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
-- CREATED "Wed Oct 23 06:50:47 2013"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FPGA4U IS
PORT
(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
in_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
);
END FPGA4U;
ARCHITECTURE bdf_type OF FPGA4U IS
COMPONENT buttons
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
write : IN STD_LOGIC;
address : IN STD_LOGIC;
buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT decoder
PORT(address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
cs_RAM : OUT STD_LOGIC;
cs_ROM : OUT STD_LOGIC;
cs_Buttons : OUT STD_LOGIC;
cs_LEDs : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cpu
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT leds
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ram
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT rom
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL address : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL cs_Buttons : STD_LOGIC;
SIGNAL cs_LEDs : STD_LOGIC;
SIGNAL cs_RAM : STD_LOGIC;
SIGNAL cs_ROM : STD_LOGIC;
SIGNAL rddata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wrdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
BEGIN
b2v_buttons_0 : buttons
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_Buttons,
read => SYNTHESIZED_WIRE_7,
write => SYNTHESIZED_WIRE_8,
address => address(2),
buttons => in_buttons,
wrdata => wrdata,
rddata => rddata);
b2v_decoder_0 : decoder
PORT MAP(address => address,
cs_RAM => cs_RAM,
cs_ROM => cs_ROM,
cs_Buttons => cs_Buttons,
cs_LEDs => cs_LEDs);
b2v_inst : cpu
PORT MAP(clk => clk,
reset_n => reset_n,
rddata => rddata,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address,
wrdata => wrdata);
b2v_LEDs_0 : leds
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_LEDs,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(3 DOWNTO 2),
wrdata => wrdata,
LEDs => out_LEDs,
rddata => rddata);
b2v_RAM_0 : ram
PORT MAP(clk => clk,
cs => cs_RAM,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
wrdata => wrdata,
rddata => rddata);
b2v_ROM_0 : rom
PORT MAP(clk => clk,
cs => cs_ROM,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
rddata => rddata);
END bdf_type; | gpl-2.0 | d0f72f544cdf7b1af2907807e143e88e | 0.668487 | 3.189405 | false | false | false | false |
bluemurder/chaotic-rngs | rng07-vhdl/vonNeumannCorrector.vhd | 2 | 1,603 | -- This block performs a Von Neumann correction --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.randgen_package.all;
entity vonNeumannCorrector is
Port ( clk : in std_logic;
reset : in std_logic;
data_in : in std_logic;
ready_in : in std_logic;
data_out : out std_logic;
ready_out : out std_logic);
end vonNeumannCorrector;
architecture Behavioral of vonNeumannCorrector is
signal counter : integer range 0 to 1;
signal reg : std_logic_vector(1 downto 0);
signal reg_xor : std_logic;
begin
proc_load_register : process(clk,reset)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) and ready_in = '1' then
reg(counter) <= data_in;
end if;
end process;
proc_counter : process(clk,reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) and ready_in = '1' then
if counter = 0 then
counter <= 1;
else
counter <= 0;
end if;
end if;
end process;
-- Xor between the two bits of reg
reg_xor <= reg(0) xor reg(1);
-- If the block is disabled, data_out equals data_in else
-- it is the first bit of the sequence of two bits
data_out <= data_in when ENABLE_VON_NEUMANN = false else
reg(0);
ready_out <= ready_in when ENABLE_VON_NEUMANN = false else
'1' when (counter = 1 and reg_xor = '1') else
'0';
end Behavioral;
| mit | 4ad9171ea747bf1caaf31bf0e484e8f1 | 0.554585 | 3.762911 | false | false | false | false |
SonicFrog/CPU | register_file.vhd | 1 | 1,916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity register_file is
port(
clk : in std_logic;
aa : in std_logic_vector( 4 downto 0);
ab : in std_logic_vector( 4 downto 0);
aw : in std_logic_vector( 4 downto 0);
wren : in std_logic;
wrdata : in std_logic_vector(31 downto 0);
a : out std_logic_vector(31 downto 0);
b : out std_logic_vector(31 downto 0)
);
end register_file;
architecture synth of register_file is
type reg_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal reg_array : reg_type := (others=>(others=>'0'));
signal decoder : std_logic_vector(31 downto 0);
begin
-- asynchronous read (1396 LUT)
--a <= reg_array(conv_integer(aa)) when aa/=0 else (others=>'0');
--b <= reg_array(conv_integer(ab)) when ab/=0 else (others=>'0');
-- asynchronous read (1396 LUT)
a <= reg_array(conv_integer(aa));
b <= reg_array(conv_integer(ab));
-- synchronous write (1403 LUT)
-- process(clk)
-- begin
-- if(rising_edge(clk))then
-- if(wren='1')then
-- reg_array(conv_integer(aw)) <= wrdata;
-- end if;
-- -- fix register 0 to 0
-- reg_array(0) <= (others => '0');
-- end if;
-- end process;
-- synchronous write (1393 LUT)
process(clk)
begin
if(rising_edge(clk))then
if(wren='1' and aw /= 0)then
reg_array(conv_integer(aw)) <= wrdata;
end if;
-- fix register 0 to 0
--reg_array(0) <= (others => '0');
end if;
end process;
-- -- synchronous write (1392 LU)
-- process(clk)
-- begin
-- if(rising_edge(clk))then
-- if(wren='1')then
-- reg_array(conv_integer(aw)) <= wrdata;
-- end if;
-- end if;
-- end process;
end synth;
| gpl-2.0 | cc20fb1cb8865d551b4ee10bbabf8a75 | 0.539666 | 3.286449 | false | false | false | false |
bluemurder/chaotic-rngs | rng07-vhdl/randGen.vhd | 2 | 2,030 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.randgen_package.all;
entity randgen is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC);
end randgen;
architecture Behavioral of randgen is
-- Components
component chaoticMap is
Port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic);
end component;
component vonNeumannCorrector is
Port ( clk : in std_logic;
reset : in std_logic;
data_in : in std_logic;
ready_in : in std_logic;
data_out : out std_logic;
ready_out : out std_logic);
end component;
-- Signals
signal counter : integer range 0 to SKIP := 0;
signal signal_output : std_logic;
signal signal_ready_in : std_logic;
begin
-- Port maps
inst_chaoticMap : chaoticMap
port map ( clk => clk,
reset => reset,
output => signal_output);
inst_vonNeumannCorrector : vonNeumannCorrector
port map ( clk => clk,
reset => reset,
data_in => signal_output,
ready_in => signal_ready_in,
data_out => output,
ready_out => ready);
-- Processes
proc_ready : process(clk,counter,reset)
begin
if reset = '1' then
signal_ready_in <= '0';
elsif rising_edge(clk) then
if counter = SKIP then
signal_ready_in <= '1';
else
signal_ready_in <= '0';
end if;
end if;
end process;
proc_counter : process(clk,reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) then
if counter = SKIP then
counter <= 0;
else
counter <= counter+1;
end if;
end if;
end process;
end Behavioral;
| mit | 0ab42a530beca8a580a00a6615f0274c | 0.516256 | 4.076305 | false | false | false | false |
bluemurder/chaotic-rngs | rng06-vhdl/randgen_package.vhd | 1 | 711 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package randgen_package is
-- Declare constants
-- Number of bits used for internal register of the chaotic map
constant N_BIT : integer := 16;
-- Number of bits to skip in the output sequence
constant SKIP : integer := 3;
-- Initial condition for the chaotic map
constant X0 : signed(N_BIT-1 downto 0) := (N_BIT-3 => '1', others => '0'); -- 0.5
-- Enables the Von Neumann corrector
constant ENABLE_VON_NEUMANN : boolean := true;
-- Clock period for the simulation
constant CLK_PERIOD : time := 10 ns;
end randgen_package;
package body randgen_package is
end randgen_package;
| mit | e5ceb3fbeb23572ee0a32a0b410c0dd3 | 0.663854 | 3.646154 | false | false | false | false |
bluemurder/chaotic-rngs | rng05-vhdl/CaosAlAl.vhd | 1 | 3,123 | ----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CaosAlAl is
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
ready : out STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
-- Integer part is ALWAYS 2 bits
constant nbit : integer := 16;
constant skip : integer := 3;
signal reg : signed(nbit-1 downto 0);
signal counter : integer range 0 to skip := 0;
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := (others => '0');
constant one : signed(nbit-1 downto 0) := (nbit-2 => '1', others => '0');
constant minusone : signed(nbit-1 downto 0) := (nbit-1 => '1', nbit-2 => '1', others => '0');
-- x0 = 0.5
constant x0 : signed(nbit-1 downto 0) := (nbit-3 => '1', others => '0');
function minimum (a,b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
begin
-- 1 when positive, 0 otherwise
--out0 <= not(reg(nbit-1)) when rising_edge(ck) and counter = 0;
out0 <= not(reg(nbit-1)) when rising_edge(ck); --and counter = skip;
--ready <= '1' when counter = minimum(1,skip) else
ready <= '1' when counter = skip else
'0';
proc_map: process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg < zero) then
-- reg = 1.875 * reg + 1
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
-- reg = 1.875 * reg - 1
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
proc_counter: process(ck,res,counter)
begin
if res = '1' then
counter <= 0;
elsif rising_edge(ck) then
if counter = skip then
counter <= 0;
else
counter <= counter+1;
end if;
end if;
end process;
end Behavioral;
| mit | c49916dd047ec4cd3a06ff0cbef675b6 | 0.502402 | 3.735646 | false | false | false | false |
SonicFrog/CPU | shift_unit.vhd | 1 | 2,001 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift_unit is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector( 4 downto 0);
op : in std_logic_vector( 2 downto 0);
r : out std_logic_vector(31 downto 0)
);
end shift_unit;
architecture synth of shift_unit is
signal rotate, shift_left, shift_right : std_logic_vector(31 downto 0);
begin
-- selection between the operations
sel: process(op, rotate, shift_left, shift_right)
begin
case op(1 downto 0) is
when "00" | "01" => r <= rotate;
when "10" => r <= shift_left;
when "11" => r <= shift_right;
when others =>
end case;
end process;
-- rotate left or right
ror_rol: process(a, b, op)
variable b_s : std_logic_vector( 4 downto 0);
variable v : std_logic_vector(31 downto 0);
begin
-- we invert b if we want to rotate to the right:
-- (a rol b <=> a ror (-b))
-- When we rotate to the right op(0)='1'
b_s := (b xor (4 downto 0 => op(0))) + op(0);
v := a;
for i in 0 to 4 loop
if(b_s(i)='1')then
v := v(31-2**i downto 0) & v(31 downto 32-2**i);
end if;
end loop;
rotate <= v;
end process;
-- shift_right
srl_sra: process(a, b, op)
variable sign : std_logic;
variable v : std_logic_vector(31 downto 0);
begin
-- if op(2)='1' we have to replicate the sign of the operand a.
sign := op(2) and a(31);
v := a;
for i in 0 to 4 loop
if(b(i)='1')then
v := ((2**i)-1 downto 0 => sign) & v(31 downto 2**i);
end if;
end loop;
shift_right<= v;
end process;
-- shift_left
sh_left: process(a, b)
variable v : std_logic_vector(31 downto 0);
begin
v := a;
for i in 0 to 4 loop
if(b(i)='1')then
v := v(31-2**i downto 0) & ((2**i)-1 downto 0 => '0');
end if;
end loop;
shift_left<= v;
end process;
end synth;
| gpl-2.0 | 170f4aab7f5a07bceea7e820cd38101a | 0.55922 | 3 | false | false | false | false |
SonicFrog/CPU | RAM.vhd | 1 | 1,630 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port(
clk : in std_logic;
cs : in std_logic;
read : in std_logic;
write : in std_logic;
address : in std_logic_vector(9 downto 0);
wrdata : in std_logic_vector(31 downto 0);
rddata : out std_logic_vector(31 downto 0));
end RAM;
architecture synth of RAM is
type mem_type is array(0 to 1023) of std_logic_vector(31 downto 0);
signal mem : mem_type;
signal reg_address : std_logic_vector(9 downto 0);
signal reg_read : std_logic;
begin
-- address register
process (clk)
begin
if (rising_edge(clk)) then
reg_read <= cs and read;
-- The next statement is optional and ONLY compatible
-- with Quartus II 8.0 or higher:
-- Since we don't read during the next cycle, we can
-- save power consumption by keeping the address constant.
--if(read='1' and cs='1')then
reg_address <= address;
--end if;
end if;
end process;
-- read in memory
process (mem, reg_read, reg_address)
begin
rddata <= (others => 'Z');
if (reg_read ='1') then
rddata <= mem(conv_integer(reg_address));
end if;
end process;
-- write in memory
process (clk)
begin
if (rising_edge(clk)) then
if (cs = '1' and write = '1') then
mem(conv_integer(address)) <= wrdata;
end if;
end if;
end process;
end synth;
| gpl-2.0 | 9b35b8ca672af5796af57ad3f9d4393c | 0.544785 | 3.790698 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/simulation/instructionMemory_tb.vhd | 1 | 4,409 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: instructionMemory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY instructionMemory_tb IS
END ENTITY;
ARCHITECTURE instructionMemory_tb_ARCH OF instructionMemory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
instructionMemory_synth_inst:ENTITY work.instructionMemory_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | f8252e320444d700b74313d39824e57a | 0.625085 | 4.74086 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/dataMemory/simulation/bmg_stim_gen.vhd | 1 | 7,818 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(31 DOWNTO 0) <= WRITE_ADDR(31 DOWNTO 0);
READ_ADDR_INT(31 DOWNTO 0) <= READ_ADDR(31 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
ENA <= DO_READ OR DO_WRITE ;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
| gpl-3.0 | f36e10c83f5c5dffff43aa5f9926db56 | 0.556664 | 3.760462 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/dataMemory/example_design/dataMemory_exdes.vhd | 1 | 4,856 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dataMemory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dataMemory_exdes IS
PORT (
--Inputs - Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END dataMemory_exdes;
ARCHITECTURE xilinx OF dataMemory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT dataMemory IS
PORT (
--Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : dataMemory
PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 8d8f628bb3517dfef7f6616db4017449 | 0.562191 | 4.700871 | false | false | false | false |
SonicFrog/CPU | logic_unit.vhd | 1 | 573 | library ieee;
use ieee.std_logic_1164.all;
entity logic_unit is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
op : in std_logic_vector( 1 downto 0);
r : out std_logic_vector(31 downto 0)
);
end logic_unit;
architecture synth of logic_unit is
begin
process(a, b, op)
begin
case op is
when "00" => r <= a nor b;
when "01" => r <= a and b;
when "10" => r <= a or b;
when "11" => r <= a xor b;
when others =>
end case;
end process;
end synth;
| gpl-2.0 | e5b6a9b0d6da03fcddf19455a452c405 | 0.544503 | 3.047872 | false | false | false | false |
DigitalBrains1/clash-lt24-quartus | lt24/lt24.vhd | 1 | 1,895 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.types.all;
entity lt24 is
port
(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(1 downto 0);
GPIO_0 : inout std_logic_vector(33 downto 0);
LT24_LCD_ON : out std_logic;
LT24_CS_N : out std_logic;
LT24_RESET_N : out std_logic;
LT24_RS : out std_logic; -- D/CX
LT24_WR_N : out std_logic;
LT24_RD_N : out std_logic;
LT24_D : inout std_logic_vector(15 downto 0));
end lt24;
architecture rtl of lt24 is
component bidir16
port
(
bidir : inout std_logic_vector(15 downto 0);
oe : in std_logic;
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0));
end component;
component topEntity_0
port(eta_i1 : in std_logic_vector(17 downto 0);
clk1000 : in std_logic;
clk1000_rst : in std_logic;
topLet_o : out std_logic_vector(24 downto 0));
end component;
signal clashi : std_logic_vector(17 downto 0);
signal clasho : std_logic_vector(24 downto 0);
signal ltdin : std_logic_vector(15 downto 0);
signal ltdout : std_logic_vector(15 downto 0);
signal oe : std_logic;
signal rxd : std_logic;
signal txd : std_logic;
begin
clash : topEntity_0
port map(
eta_i1 => clashi,
clk1000 => CLOCK_50,
clk1000_rst => KEY(0),
topLet_o => clasho);
lt24d : bidir16
port map(
bidir => LT24_D,
oe => oe,
clk => CLOCK_50,
i => ltdout,
o => ltdin);
clashi(15 downto 0) <= ltdin;
clashi(16) <= rxd;
clashi(17) <= KEY(1);
rxd <= GPIO_0(2);
GPIO_0(1) <= clasho(24);
txd <= clasho(23);
GPIO_0(4) <= txd;
LT24_LCD_ON <= clasho(22);
LT24_CS_N <= clasho(21);
LT24_RESET_N <= clasho(20);
LT24_RS <= clasho(19); -- D/CX
LT24_WR_N <= clasho(18);
LT24_RD_N <= clasho(17);
ltdout <= clasho(16 downto 1);
oe <= clasho(0);
end rtl;
| bsd-2-clause | 4f8479cbb16da833c8194dc7786694a8 | 0.612137 | 2.536814 | false | false | false | false |
martinmiranda14/Digitales | Lab_6/clkdiv/clkdiv.cache/ip/1ba1617468e3eb91/clk_wiz_0_sim_netlist.vhdl | 1 | 7,297 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:41:12 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.250000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 12.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
reset => reset
);
end STRUCTURE;
| apache-2.0 | f0c8d9d47797365c175b8dfbe1a3b6e0 | 0.641359 | 3.354943 | false | false | false | false |
martinmiranda14/Digitales | Lab_6/clkdiv/clkdiv.cache/ip/cdfdc0ad26be34f0/clk_wiz_0_sim_netlist.vhdl | 1 | 7,297 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:22:32 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.250000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 12.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
reset => reset
);
end STRUCTURE;
| apache-2.0 | c4f7a39a6b978f92bb1baee300984609 | 0.641359 | 3.354943 | false | false | false | false |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/image_capture.vhd | 1 | 10,317 | ------------------------------------------------------------------
-- image_capture component
------------------------------------------------------------------
-- This component is used to save an image in memory. It uses two
-- buffers in memory with addresses buff0 and buff1 to do it.
-- When start_capture is asserted the component waits for the next
-- positive flank of frame valid to synchronize and start at the
-- beginning of a new image. Then, every time data_valid is
-- asserted the component packs the {R,G,B,Gray} components into a
-- 32-bit (when components are 8-bit) or 64-bit (when
-- components are 16-bit) word and writes it to the avalon bus.
-- It is supossed that the bus can react in a single
-- clock cycle to the writes because waitrequest signal of avalon
-- specification is not implemented. In case the slave bus cannot
-- react in a single cycle an Avalon FIFO should be implemented
-- in between the master of this component and the slave where
-- data is being written. The component starts writting in buff0.
-- When a line from the image is acquired buff0full signal is
-- asserted during 1 clock cycle. Next line is written into buff1.
-- When a line from the image is acquired again the bus asserts
-- buff1full line for 1 cycle. Next line is saved in buff0 again.
-- So the component goes writing odd lines in buff0 and even lines
-- in buff1 until all lines in one image (image_height) are acquired.
-- The processor (or whatever component processes acquired lines)
-- should empty one buffer before this component finishes
-- filling the other one so data is not lost.
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all; -- For using ceil and log2.
use IEEE.NUMERIC_STD.all; -- For using to_unsigned.
use ieee.std_logic_unsigned.all; -- Needed for the sum used in counter.
ENTITY image_capture IS
GENERIC (
-- Size of each color component (8 or 16).
COMPONENT_SIZE : integer := 8
);
PORT (
-- Clock and reset.
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
-- Signals from the video stream.
R : IN STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
G : IN STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
B : IN STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
Gray : IN STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
--Signals to control the component
-- When fram_valid is 1, the image from camera is being aquired.
frame_valid : IN STD_LOGIC;
data_valid : IN STD_LOGIC; -- Valid pixel in R,G,B,Gray inputs.
-- Signals to control this component (usually coming from avalon_camera)
-- When start_capture is 1, start getting a new image.
start_capture : IN STD_LOGIC;
-- Number of columns and rows in the input image array.
image_width : IN STD_LOGIC_VECTOR(15 downto 0);
image_height : IN STD_LOGIC_VECTOR(15 downto 0);
-- Odd lines buffer address.
buff0 : IN STD_LOGIC_VECTOR(31 downto 0);
-- Even lines buffer address.
buff1 : IN STD_LOGIC_VECTOR(31 downto 0);
-- Signals indicating that buffers are full (Active 1 clock cycle only).
buff0full : OUT STD_LOGIC;
buff1full : OUT STD_LOGIC;
-- Signal indicating standby state
--(outside of reset, waiting for flank in start_capture)
standby : OUT STD_LOGIC;
-- Avalon MM Master port to save data into a memory.
-- Byte adresses are multiples of 4 when accessing 32-bit data.
address : OUT STD_LOGIC_VECTOR(31 downto 0);
write : OUT STD_LOGIC;
byteenable :OUT STD_LOGIC_VECTOR((COMPONENT_SIZE/2-1) downto 0);
writedata : OUT STD_LOGIC_VECTOR((COMPONENT_SIZE*4-1) downto 0);
waitrequest : IN STD_LOGIC;
burstcount : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END image_capture;
ARCHITECTURE arch OF image_capture IS
constant NUMBER_OF_STATES : INTEGER := 6;
--signals for the evolution of the state machine
SIGNAL current_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
SIGNAL next_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
-- Conditions to change next state.
-- State_condition(x) condition to go from x to x+1.
SIGNAL state_condition : STD_LOGIC_VECTOR((NUMBER_OF_STATES - 2) downto 0);
SIGNAL condition_5_to_4 : STD_LOGIC;
SIGNAL condition_5_to_1 : STD_LOGIC;
--counters.
SIGNAL pix_counter : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL line_counter : STD_LOGIC_VECTOR(12 downto 0);
SIGNAL line_end_reached : STD_LOGIC;
SIGNAL image_end_reached: STD_LOGIC;
-- Write_buff: it saves the address where the next pixel will be saved.
SIGNAL write_buff : STD_LOGIC_VECTOR(31 downto 0);
-- 0 if writting in buff0, 1 if writting in buff1.
SIGNAL current_buff : STD_LOGIC;
-- captures a flank in start capture that comes from other clock region.
SIGNAL start_capture_reg: STD_LOGIC;
BEGIN
-- FSM (Finite State Machine) clocking and reset.
fsm_mem: PROCESS (clk,reset_n)
BEGIN
IF rising_edge(clk) THEN
IF reset_n='0' THEN current_state <= 0;
ELSE
current_state<=next_state;
END IF;
END IF;
END PROCESS fsm_mem;
-- Evolution of FSM.
comb_fsm: PROCESS (current_state, state_condition, condition_5_to_1,
condition_5_to_4)
BEGIN
CASE current_state IS
WHEN 0 =>
IF state_condition(0) = '1' THEN next_state <= 1;
ELSE next_state<=0; END IF;
WHEN 1 =>
IF state_condition(1) = '1' THEN next_state <= 2;
ELSE next_state<=1; END IF;
WHEN 2 =>
IF state_condition(2) = '1' THEN next_state <= 3;
ELSE next_state<=2; END IF;
WHEN 3 =>
IF state_condition(3) = '1' THEN next_state <= 4;
ELSE next_state<=3; END IF;
WHEN 4 =>
IF state_condition(4) = '1' THEN next_state <= 5;
ELSE next_state<=4; END IF;
WHEN 5 =>
IF condition_5_to_1 = '1' THEN next_state <= 1;
ELSIF condition_5_to_4 = '1' THEN next_state <= 4;
ELSE next_state<=5; END IF;
WHEN OTHERS =>
next_state <= 0;
END CASE;
END PROCESS comb_fsm;
-- Conditions of FSM.
state_condition(0) <= '1';
state_condition(1) <= start_capture_reg;
state_condition(2) <= not(frame_valid);
state_condition(3) <= frame_valid;
state_condition(4) <= line_end_reached;
condition_5_to_1 <= image_end_reached;
condition_5_to_4 <= not (image_end_reached);
-- Evaluation and update pix_counter.
pix_counter_proc:process (clk, current_state, data_valid)
begin
if rising_edge(clk) then
if (current_state = 1) or (current_state = 5) then
pix_counter <= (others => '0'); --reset ctr
elsif (current_state = 4) and (data_valid = '1') then -- ctr incremented
pix_counter <= pix_counter + 1;
end if;
end if;
if pix_counter = image_width(12 downto 0) then
line_end_reached <= '1';
else
line_end_reached <= '0';
end if;
end process;
-- Evaluation and update of line_counter.
line_counter_proc:process (clk, current_state, data_valid)
begin
if rising_edge(clk) then
if (current_state = 1) then
line_counter <= (others => '0'); -- reset ctr
elsif (current_state = 5) then -- ctr incremented
line_counter <= line_counter + 1;
end if;
end if;
if line_counter = image_height(12 downto 0) then
image_end_reached <= '1';
else
image_end_reached <= '0';
end if;
end process;
-- Generate standby signal
WITH current_state SELECT standby <=
'1' WHEN 1,
'0' WHEN OTHERS;
-- Generate Avalon bus signals
address <= write_buff;
writedata <= Gray & B & G & R;
byteenable <= (others => '1');
write_proc: process (current_state, data_valid)
begin
if (current_state = 4) and (data_valid = '1') then write <= '1';
else write <= '0'; end if;
end process;
burstcount <= "0000001"; --always single transactions (no burst)
-- Write_buff, current_buff, buff0full and buff1full generation
buff_proc:process (clk, current_state)
begin
if rising_edge(clk) then
if current_state = 1 then --reset signals to initial values
write_buff <= buff0;
current_buff <= '0';
buff0full <= '0';
buff1full <= '0';
elsif current_state = 5 and current_buff = '0'then
write_buff <= buff1;
current_buff <= '1';
buff0full <= '1';
buff1full <= '0';
elsif current_state = 5 and current_buff = '1'then
write_buff <= buff0;
current_buff <= '0';
buff0full <= '0';
buff1full <= '1';
elsif current_state = 4 then
buff0full <= '0';
buff1full <= '0';
if data_valid = '1' then
write_buff <= write_buff + (COMPONENT_SIZE/2);
end if;
end if;
end if;
end process;
-- Detection of a flank in start_capture. This signal is coming from the
-- processor and could have different clock. That's why flank is detected
-- instead of level.
start_capture_reg_proc:process(start_capture)
begin
if (current_state = 2 or current_state = 0) then
start_capture_reg <= '0';
elsif rising_edge(start_capture) then
start_capture_reg <= '1';
end if;
end process;
END arch;
| gpl-3.0 | c2fce6fd2634987cc86be777bb9a2b53 | 0.569545 | 4.053831 | false | false | false | false |
SonicFrog/CPU | ROM_Block.vhd | 1 | 6,218 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM_Block.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ROM_Block IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END ROM_Block;
ARCHITECTURE SYN OF rom_block IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../quartus/ROM.hex",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../quartus/ROM.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../quartus/ROM.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Block_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | ebb3e9c564ecf81c7adf10c28dfab047 | 0.669025 | 3.571511 | false | false | false | false |
SonicFrog/CPU | PC.vhd | 1 | 1,032 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port(
clk : in std_logic;
reset_n : in std_logic;
en : in std_logic;
sel_a : in std_logic;
sel_imm : in std_logic;
add_imm : in std_logic;
imm : in std_logic_vector(15 downto 0);
a : in std_logic_vector(15 downto 0);
addr : out std_logic_vector(31 downto 0)
);
end PC;
architecture synth of PC is
signal inst_addr : std_logic_vector(15 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset_n = '0') then
inst_addr <= (others => '0');
elsif(en = '1') then
if(add_imm = '1') then
inst_addr <= inst_addr + imm;
elsif(sel_imm = '1') then
inst_addr <= imm(13 downto 0) & "00";
elsif(sel_a = '1') then
inst_addr <= a(15 downto 2) & "00";
else
inst_addr <= inst_addr + 4;
end if;
end if;
end if;
end process;
addr <= X"0000" & inst_addr;
end synth;
| gpl-2.0 | d9e16cb9a1f06aecc3c4e2bd68f0a7b0 | 0.545543 | 2.804348 | false | false | false | false |
SonicFrog/CPU | CPU.vhd | 1 | 6,932 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY CPU IS
port
(
reset_n : IN STD_LOGIC;
clk : IN STD_LOGIC;
rddata : IN STD_LOGIC_VECTOR(31 downto 0);
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR(15 downto 0);
wrdata : OUT STD_LOGIC_VECTOR(31 downto 0)
);
END CPU;
ARCHITECTURE bdf_type OF CPU IS
component alu
PORT(a : IN STD_LOGIC_VECTOR(31 downto 0);
b : IN STD_LOGIC_VECTOR(31 downto 0);
op : IN STD_LOGIC_VECTOR(5 downto 0);
s : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component controller
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
op : IN STD_LOGIC_VECTOR(5 downto 0);
opx : IN STD_LOGIC_VECTOR(5 downto 0);
branch_op : OUT STD_LOGIC;
imm_signed : OUT STD_LOGIC;
ir_en : OUT STD_LOGIC;
pc_add_imm : OUT STD_LOGIC;
pc_en : OUT STD_LOGIC;
pc_sel_a : OUT STD_LOGIC;
pc_sel_imm : OUT STD_LOGIC;
rf_wren : OUT STD_LOGIC;
sel_addr : OUT STD_LOGIC;
sel_b : OUT STD_LOGIC;
sel_mem : OUT STD_LOGIC;
sel_pc : OUT STD_LOGIC;
sel_ra : OUT STD_LOGIC;
sel_rC : OUT STD_LOGIC;
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
op_alu : OUT STD_LOGIC_VECTOR(5 downto 0)
);
end component;
component extend
PORT(signed : IN STD_LOGIC;
imm16 : IN STD_LOGIC_VECTOR(15 downto 0);
imm32 : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component ir
PORT(clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(31 downto 0);
Q : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component mux2x16
PORT(sel : IN STD_LOGIC;
i0 : IN STD_LOGIC_VECTOR(15 downto 0);
i1 : IN STD_LOGIC_VECTOR(15 downto 0);
o : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component mux2x5
PORT(sel : IN STD_LOGIC;
i0 : IN STD_LOGIC_VECTOR(4 downto 0);
i1 : IN STD_LOGIC_VECTOR(4 downto 0);
o : OUT STD_LOGIC_VECTOR(4 downto 0)
);
end component;
component mux2x32
PORT(sel : IN STD_LOGIC;
i0 : IN STD_LOGIC_VECTOR(31 downto 0);
i1 : IN STD_LOGIC_VECTOR(31 downto 0);
o : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component pc
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
en : IN STD_LOGIC;
sel_a : IN STD_LOGIC;
sel_imm : IN STD_LOGIC;
add_imm : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 downto 0);
imm : IN STD_LOGIC_VECTOR(15 downto 0);
addr : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component register_file
PORT(clk : IN STD_LOGIC;
wren : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR(4 downto 0);
ab : IN STD_LOGIC_VECTOR(4 downto 0);
aw : IN STD_LOGIC_VECTOR(4 downto 0);
wrdata : IN STD_LOGIC_VECTOR(31 downto 0);
a : OUT STD_LOGIC_VECTOR(31 downto 0);
b : OUT STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal a : STD_LOGIC_VECTOR(31 downto 0);
signal alu_res : STD_LOGIC_VECTOR(31 downto 0);
signal aw : STD_LOGIC_VECTOR(4 downto 0);
signal b : STD_LOGIC_VECTOR(31 downto 0);
signal branch_op : STD_LOGIC;
signal branch_taken : STD_LOGIC;
signal imm : STD_LOGIC_VECTOR(31 downto 0);
signal imm_signed : STD_LOGIC;
signal instr : STD_LOGIC_VECTOR(31 downto 0);
signal ir_en : STD_LOGIC;
signal op_alu : STD_LOGIC_VECTOR(5 downto 0);
signal op_b : STD_LOGIC_VECTOR(31 downto 0);
signal pc_add_imm : STD_LOGIC;
signal pc_addr : STD_LOGIC_VECTOR(31 downto 0);
signal pc_en : STD_LOGIC;
signal pc_sel_a : STD_LOGIC;
signal pc_sel_imm : STD_LOGIC;
signal pc_wren : STD_LOGIC;
signal ra : STD_LOGIC_VECTOR(4 downto 0);
signal rf_wren : STD_LOGIC;
signal sel_addr : STD_LOGIC;
signal sel_b : STD_LOGIC;
signal sel_mem : STD_LOGIC;
signal sel_pc : STD_LOGIC;
signal sel_ra : STD_LOGIC;
signal sel_rC : STD_LOGIC;
signal SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(4 downto 0);
signal SYNTHESIZED_WIRE_1 : STD_LOGIC;
signal SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(31 downto 0);
signal SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
b2v_alu_0 : alu
PORT MAP(a => a,
b => op_b,
op => op_alu,
s => alu_res);
branch_taken <= branch_op AND alu_res(0);
b2v_controller_0 : controller
PORT MAP(clk => clk,
reset_n => reset_n,
op => instr(5 downto 0),
opx => instr(16 downto 11),
branch_op => branch_op,
imm_signed => imm_signed,
ir_en => ir_en,
pc_add_imm => pc_add_imm,
pc_en => pc_wren,
pc_sel_a => pc_sel_a,
pc_sel_imm => pc_sel_imm,
rf_wren => rf_wren,
sel_addr => sel_addr,
sel_b => sel_b,
sel_mem => sel_mem,
sel_pc => sel_pc,
sel_ra => sel_ra,
sel_rC => sel_rC,
write => write,
read => read,
op_alu => op_alu);
b2v_extend_0 : extend
PORT MAP(signed => imm_signed,
imm16 => instr(21 downto 6),
imm32 => imm);
b2v_IR_0 : ir
PORT MAP(clk => clk,
enable => ir_en,
D => rddata,
Q => instr);
b2v_mux_addr : mux2x16
PORT MAP(sel => sel_addr,
i0 => pc_addr(15 downto 0),
i1 => alu_res(15 downto 0),
o => address);
b2v_mux_aw : mux2x5
PORT MAP(sel => sel_rC,
i0 => SYNTHESIZED_WIRE_0,
i1 => instr(21 downto 17),
o => aw);
b2v_mux_b : mux2x32
PORT MAP(sel => sel_b,
i0 => imm,
i1 => b,
o => op_b);
b2v_mux_data : mux2x32
PORT MAP(sel => SYNTHESIZED_WIRE_1,
i0 => alu_res,
i1 => SYNTHESIZED_WIRE_2,
o => SYNTHESIZED_WIRE_3);
b2v_mux_mem : mux2x32
PORT MAP(sel => sel_mem,
i0 => pc_addr,
i1 => rddata,
o => SYNTHESIZED_WIRE_2);
b2v_mux_ra : mux2x5
PORT MAP(sel => sel_ra,
i0 => instr(26 downto 22),
i1 => ra,
o => SYNTHESIZED_WIRE_0);
pc_en <= pc_wren OR branch_taken;
b2v_PC_0 : pc
PORT MAP(clk => clk,
reset_n => reset_n,
en => pc_en,
sel_a => pc_sel_a,
sel_imm => pc_sel_imm,
add_imm => pc_add_imm,
a => a(15 downto 0),
imm => instr(21 downto 6),
addr => pc_addr);
SYNTHESIZED_WIRE_1 <= sel_pc OR sel_mem;
b2v_register_file_0 : register_file
PORT MAP(clk => clk,
wren => rf_wren,
aa => instr(31 downto 27),
ab => instr(26 downto 22),
aw => aw,
wrdata => SYNTHESIZED_WIRE_3,
a => a,
b => b);
wrdata <= b;
ra <= "11111";
END; | gpl-2.0 | a2612c5cc4e49353776847672255043c | 0.64599 | 2.806478 | false | false | false | false |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/avalon_write_bridge.vhd | 2 | 1,655 | ---Avalon Bridge
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all; -- For using ceil and log2.
use IEEE.NUMERIC_STD.all; -- For using to_unsigned.
use ieee.std_logic_unsigned.all; -- Needed for the sum used in counter.
ENTITY avalon_write_bridge IS
GENERIC (
DATA_SIZE : integer := 32;
ADDRESS_SIZE : integer := 32;
BURSCOUNT_SIZE : integer := 7
);
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
--avalon master
avm_write_address : OUT STD_LOGIC_VECTOR((ADDRESS_SIZE-1) downto 0);
avm_write_write : OUT STD_LOGIC;
avm_write_byteenable : OUT STD_LOGIC_VECTOR(((DATA_SIZE/8)-1) downto 0);
avm_write_writedata : OUT STD_LOGIC_VECTOR((DATA_SIZE-1) downto 0);
avm_write_waitrequest: IN STD_LOGIC;
avm_write_burstcount : OUT STD_LOGIC_VECTOR((BURSCOUNT_SIZE-1) downto 0);
--avalon slave
avs_write_address : IN STD_LOGIC_VECTOR((ADDRESS_SIZE-1) downto 0);
avs_write_write : IN STD_LOGIC;
avs_write_byteenable : IN STD_LOGIC_VECTOR(((DATA_SIZE/8)-1) downto 0);
avs_write_writedata : IN STD_LOGIC_VECTOR((DATA_SIZE-1) downto 0);
avs_write_waitrequest: OUT STD_LOGIC;
avs_write_burstcount : IN STD_LOGIC_VECTOR((BURSCOUNT_SIZE-1) downto 0)
);
END avalon_write_bridge;
ARCHITECTURE arch OF avalon_write_bridge IS
BEGIN
avm_write_address <= avs_write_address;
avm_write_write <= avs_write_write;
avm_write_byteenable <= avs_write_byteenable;
avm_write_writedata <= avs_write_writedata;
avs_write_waitrequest <= avm_write_waitrequest;
avm_write_burstcount <= avs_write_burstcount;
END arch; | gpl-3.0 | dea42721883789e06c79389fc9e19da7 | 0.670091 | 3.053506 | false | false | false | false |
SonicFrog/CPU | buttons.vhd | 1 | 1,986 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity buttons is
port(
-- bus interface
clk : in std_logic;
reset_n : in std_logic;
--irq : out std_logic;
cs : in std_logic;
read : in std_logic;
write : in std_logic;
address : in std_logic;
wrdata : in std_logic_vector(31 downto 0);
rddata : out std_logic_vector(31 downto 0);
buttons : in std_logic_vector(3 downto 0)
);
end buttons;
architecture synth of buttons is
constant REG_DATA : std_logic := '0';
constant REG_EDGE : std_logic := '1';
signal address_reg : std_logic;
signal read_reg : std_logic;
signal buttons_reg : std_logic_vector(3 downto 0);
signal edges : std_logic_vector(3 downto 0);
begin
--irq <= '0' when edges = 0 else '1';
-- address_reg & button_reg
process(clk, reset_n)
begin
if (reset_n='0') then
address_reg <= '0';
read_reg <= '0';
buttons_reg <= (others => '1');
elsif (rising_edge(clk)) then
address_reg <= address;
read_reg <= read and cs;
buttons_reg <= buttons;
end if;
end process;
-- read
process(read_reg, address_reg, edges, buttons)
begin
rddata <= (others => 'Z');
if (read_reg = '1') then
rddata <= (others => '0');
case address_reg is
when REG_DATA =>
rddata(3 downto 0) <= buttons;
when REG_EDGE =>
rddata(3 downto 0) <= edges;
when others =>
end case;
end if;
end process;
-- edges
process(clk, reset_n)
begin
if (reset_n='0') then
edges <= (others => '0');
elsif (rising_edge(clk)) then
-- edge detection
edges <= edges or (not buttons and buttons_reg);
-- clear edges
if (cs = '1' and write = '1') then
if (address = REG_EDGE) then
edges <= (others => '0');
end if;
end if;
end if;
end process;
end synth;
| gpl-2.0 | 56643236ba39d662e1df946c3f8db188 | 0.563444 | 3.315526 | false | false | false | false |
SonicFrog/CPU | LEDs.vhd | 1 | 2,676 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LEDs is
port(
-- bus interface
clk : in std_logic;
reset_n : in std_logic;
cs : in std_logic;
read : in std_logic;
write : in std_logic;
address : in std_logic_vector( 1 downto 0);
rddata : out std_logic_vector(31 downto 0);
wrdata : in std_logic_vector(31 downto 0);
-- external output
LEDs : out std_logic_vector(95 downto 0)
);
end LEDs;
architecture synth of LEDs is
constant REG_LED_0_31 : std_logic_vector(1 downto 0) := "00";
constant REG_LED_32_63 : std_logic_vector(1 downto 0) := "01";
constant REG_LED_64_95 : std_logic_vector(1 downto 0) := "10";
constant REG_DUTY_CYCLE : std_logic_vector(1 downto 0) := "11";
signal reg_read : std_logic;
signal reg_address : std_logic_vector( 1 downto 0);
signal counter : std_logic_vector( 7 downto 0);
signal LEDs_reg : std_logic_vector(95 downto 0);
signal duty_cycle : std_logic_vector( 7 downto 0);
begin
LEDs <= LEDs_reg when counter < duty_cycle
else (others => '0');
-- registers
process (clk, reset_n)
begin
if (reset_n='0') then
reg_read <= '0';
reg_address <= (others => '0');
counter <= (others => '0');
elsif (rising_edge(clk)) then
reg_read <= cs and read;
reg_address <= address;
counter <= counter + 1;
end if;
end process;
-- read
process (reg_read, reg_address, LEDs_reg, duty_cycle)
begin
rddata <= (others => 'Z');
if (reg_read = '1') then
rddata <= (others => '0');
case reg_address is
when REG_LED_0_31 =>
rddata <= LEDs_reg(31 downto 0);
when REG_LED_32_63 =>
rddata <= LEDs_reg(63 downto 32);
when REG_LED_64_95 =>
rddata <= LEDs_reg(95 downto 64);
when REG_DUTY_CYCLE =>
rddata(7 downto 0) <= duty_cycle;
when others =>
end case;
end if;
end process;
-- write
process (clk, reset_n)
begin
if (reset_n='0') then
LEDs_reg <= (others => '0');
duty_cycle <= X"0F";
elsif (rising_edge(clk)) then
if (cs = '1' and write = '1') then
case address is
when REG_LED_0_31 =>
LEDs_reg(31 downto 0) <= wrdata;
when REG_LED_32_63 =>
LEDs_reg(63 downto 32) <= wrdata;
when REG_LED_64_95 =>
LEDs_reg(95 downto 64) <= wrdata;
when REG_DUTY_CYCLE =>
duty_cycle <= wrdata(7 downto 0);
when others =>
end case;
end if;
end if;
end process;
end synth;
| gpl-2.0 | aca4e1737fff706a2f64b9311bea3c10 | 0.559043 | 3.279412 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/dataMemory/simulation/dataMemory_synth.vhd | 1 | 8,486 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dataMemory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY dataMemory_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE dataMemory_synth_ARCH OF dataMemory_synth IS
COMPONENT dataMemory_exdes
PORT (
--Inputs - Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
ADDRA_SHIFT(31 DOWNTO 2) <= ADDRA(29 DOWNTO 0) ;
ADDRA_SHIFT(1 DOWNTO 0) <= (OTHERS=> '0' );
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_SHIFT_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ADDRA_SHIFT_R <= ADDRA_SHIFT AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: dataMemory_exdes PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_SHIFT_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | 47f78f317a188074d8a048b77f046907 | 0.562574 | 3.746578 | false | false | false | false |
SonicFrog/CPU | decoder.vhd | 1 | 906 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
address : in std_logic_vector(15 downto 0);
cs_Buttons : out std_logic;
cs_LEDS : out std_logic;
cs_RAM : out std_logic;
cs_ROM : out std_logic
);
end decoder;
architecture synth of decoder is
begin
-- unit selection
process (address)
begin
cs_ROM <= '0';
cs_RAM <= '0';
cs_LEDS <= '0';
cs_Buttons <= '0';
if (address < X"1000") then
cs_ROM <= '1';
elsif (address < X"2000") then
cs_RAM <= '1';
elsif (address < X"2010") then
cs_LEDS <= '1';
elsif (address < X"2030") then
-- empty space
elsif (address < X"2038") then
cs_Buttons <= '1';
end if;
end process;
end synth;
| gpl-2.0 | 1cf597c7a74700f9f1be09e3bbb6a17c | 0.493377 | 3.581028 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/instructionMemory/simulation/instructionMemory_synth.vhd | 1 | 7,397 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionMemory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY instructionMemory_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE instructionMemory_synth_ARCH OF instructionMemory_synth IS
COMPONENT instructionMemory_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
ENA => ENA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
ADDRA_SHIFT(31 DOWNTO 2) <= ADDRA(29 DOWNTO 0) ;
ADDRA_SHIFT(1 DOWNTO 0) <= (OTHERS=> '0' );
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_SHIFT_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ADDRA_SHIFT_R <= ADDRA_SHIFT AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: instructionMemory_exdes PORT MAP (
--Port A
ENA => ENA_R,
ADDRA => ADDRA_SHIFT_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | 09c96a37a322d3ec2f669547d4c12674 | 0.58037 | 3.797228 | false | false | false | false |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/dataMemory/example_design/dataMemory_prod.vhd | 1 | 10,239 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: dataMemory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 1
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : dataMemory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 1
-- C_RST_PRIORITY_A : SR
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 4
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 64
-- C_READ_DEPTH_A : 64
-- C_ADDRA_WIDTH : 32
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 4
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 64
-- C_READ_DEPTH_B : 64
-- C_ADDRB_WIDTH : 32
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dataMemory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END dataMemory_prod;
ARCHITECTURE xilinx OF dataMemory_prod IS
COMPONENT dataMemory_exdes IS
PORT (
--Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : dataMemory_exdes
PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 0ca09099ad358158e478c7364d8c9305 | 0.492626 | 3.843468 | false | false | false | false |
SonicFrog/CPU | ROM.vhd | 1 | 1,179 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port(
clk : in std_logic;
cs : in std_logic;
read : in std_logic;
address : in std_logic_vector(9 downto 0);
rddata : out std_logic_vector(31 downto 0));
end ROM;
architecture synth of ROM is
component ROM_Block is
port(
address : in std_logic_vector(9 downto 0);
clock : in std_logic;
q : out std_logic_vector(31 downto 0)
);
end component;
-- internal signal for the ROM rddata
signal in_rddata : std_logic_vector(31 downto 0);
signal reg_read : std_logic;
begin
rom_block_0: ROM_Block port map(
address => address,
clock => clk,
q => in_rddata);
-- 1 cycle latency
process(clk)
begin
if(rising_edge(clk))then
reg_read <= read and cs;
end if;
end process;
-- read in memory
process(reg_read, in_rddata)
begin
rddata <= (others => 'Z');
if(reg_read='1')then
rddata <= in_rddata;
end if;
end process;
end synth;
| gpl-2.0 | 28e9c84dc9b580638802dee69e19b301 | 0.544529 | 3.616564 | false | false | false | false |
bluemurder/chaotic-rngs | rng08-vhdl/variable_Caos.vhd | 1 | 3,082 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0' ;
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
--if (k(scalamento)= '1') then
-- sott := conv_signed(2**((scalamento)+1),numBit)- k;
-- res := ((2**(scalamento+1)) * conv_integer(x))/(2**(scalamento));
--else
-- sott := conv_signed(2**((scalamento)),numBit)- k;
-- res := ((2**(scalamento)) * conv_integer(x))/(2**(scalamento));
--
--end if;
-- for i in 1 to scalamento loop
-- if(sott((scalamento)-i) = '1')then
-- res := res - ((2**(scalamento-i)) * conv_integer(x))/(2**(scalamento));
-- end if;
-- end loop;
--return res;
--res := (conv_integer(x)/(2**(numBit/2)))*(conv_integer(k)/(2**(numBit/2)));
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
--res := (((2**numBit-1)/(2**(numBit/2))) * (conv_integer(x)/(2**(numBit/2))))-(((conv_integer(1/8 * 2**(numBit-1))/(2**(numBit/2))))*(conv_integer(x)/(2**(numBit/2))));
--res := (2**Nint) * res;
--res := res/4;
--res :=(conv_integer(x)*conv_integer(k))/(2**(scalamento));
return res;
end function;
end variable_Caos;
| mit | a8c3024e2b951e78c336158318f9728e | 0.532446 | 3.17732 | false | false | false | false |
DigitalBrains1/clash-lt24-quartus | lt24/bidir16.vhd | 1 | 854 | -- Based on Altera provided design downloaded from:
-- http://wl.altera.com/support/examples/vhdl/v_bidir.html
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bidir16 is
port
(
bidir : inout std_logic_vector(15 downto 0);
oe : in std_logic;
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0));
end bidir16;
architecture behavioral of bidir16 is
signal iff : std_logic_vector(15 downto 0); -- DFF storing i
signal off : std_logic_vector(15 downto 0); -- DFF storing o
begin
process(clk)
begin
if rising_edge(clk) then
iff <= i;
o <= off;
end if;
end process;
process (oe, bidir, iff)
begin
if (oe = '0') then
bidir <= "ZZZZZZZZZZZZZZZZ";
off <= bidir;
else
bidir <= iff;
off <= bidir;
end if;
end process;
end behavioral;
| bsd-2-clause | 86d16a85f1784a17b1b94d4160287358 | 0.640515 | 3.007042 | false | false | false | false |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/vga_controller/vga_controller.vhd | 2 | 5,903 | -- Function: VGA Controller
-- Resolutions: 640x480 --- 1920x1080
-- INSTRUCTIONS: For changing the resolution, comment the generic mapping at
-- the entity level for the actual resolution,
-- and uncomment the generic mapping for the desired resolution.
-- NOTE: It is important to wire this component with the specified input clock,
-- when an instance is created on a higher level.
library IEEE;
use IEEE.std_logic_1164.all;
entity vga_controller is
---- Map for a 1920x1200 diplay -- Refresh rate: 60 Hz
-- Ideal pixel clock: 193.16 MHz
-- generic(
-- h_pulse : INTEGER := 208; --horiztonal sync pulse width in pixels
-- h_bp : INTEGER := 336; --horiztonal back porch width in pixels
-- h_pixels : INTEGER := 1920; --horiztonal display width in pixels
-- h_fp : INTEGER := 128; --horiztonal front porch width in pixels
-- h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity
-- v_pulse : INTEGER := 3; --vertical sync pulse width in rows
-- v_bp : INTEGER := 38; --vertical back porch width in rows
-- v_pixels : INTEGER := 1200; --vertical display width in rows
-- v_fp : INTEGER := 1; --vertical front porch width in rows
-- v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity
---- Map for a 640x480 diplay -- Refresh rate: 60 Hz
-- Ideal pixel clock: 25.175 MHz
generic(
h_pulse : INTEGER := 96; --horizontal sync pulse width in pixels
h_bp : INTEGER := 48; --horizontal back porch width in pixels
h_pixels : INTEGER := 640; --horizontal display width in pixels
h_fp : INTEGER := 16; --horizontal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity
v_pulse : INTEGER := 2; --vertical sync pulse width in rows
v_bp : INTEGER := 33; --vertical back porch width in rows
v_pixels : INTEGER := 480; --vertical display width in rows
v_fp : INTEGER := 10; --vertical front porch width in rows
v_pol : STD_LOGIC := '0'); --vertical sync pulse polarity
port(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horizontal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1'=display, '0'=blanking)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC; --sync-on-green output to DAC
data_req : OUT STD_LOGIC);
end vga_controller;
architecture behavior of vga_controller is
--total number of pixel clocks in a row and total number of rows in frame.
constant h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp;
constant v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp;
begin
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
-- The statements below will be evaluated any time there is a change in the
-- sensitivity list (pixel_clk or reset_n).
process(pixel_clk, reset_n)
--horizontal counter (columns) and vertical counter (rows).
variable h_count : INTEGER RANGE 0 TO h_period - 1 := 0;
variable v_count : INTEGER RANGE 0 TO v_period - 1 := 0;
begin
if(reset_n = '0') then --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
data_req <= '0'; --disable request
column <= 0; --reset column pixel coordinate
row <= 0; --reset row pixel coordinate
elsif(pixel_clk'event AND pixel_clk = '1') then
--counters
if(h_count < h_period - 1) then --horizontal counter (pixels)
h_count := h_count + 1;
else
h_count := 0;
if(v_count < v_period - 1) then --veritcal counter (rows)
v_count := v_count + 1;
else
v_count := 0;
end if;
end if;
--horizontal sync signal
if(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) then
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
else
h_sync <= h_pol; --assert horiztonal sync pulse
end if;
--vertical sync signal
if(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) then
v_sync <= NOT v_pol; --deassert vertical sync pulse
else
v_sync <= v_pol; --assert vertical sync pulse
end if;
--set pixel coordinates
if(h_count < h_pixels) then --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
end if;
if(v_count < v_pixels) then --vertical display time
row <= v_count; --set vertical pixel coordinate
end if;
--set display enable output
if(h_count < h_pixels AND v_count < v_pixels) then --display time
disp_ena <= '1'; --enable display
else --blanking time
disp_ena <= '0'; --disable display
end if;
--set data request value
if (h_count < h_pixels - 2) AND (h_count >= h_period - 3)
AND (v_count < v_pixels)
then
data_req <= '1';
else
data_req <= '0';
end if;
end if;
end process;
end behavior;
| gpl-3.0 | e6ddb49ade31fa01fb0029a7c198c3f7 | 0.570049 | 3.719597 | false | false | false | false |
bluemurder/chaotic-rngs | rng07-vhdl/test_randgen.vhd | 2 | 1,675 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
LIBRARY std;
use STD.textio.all;
use work.randgen_package.all;
ENTITY test_randgen IS
END test_randgen;
ARCHITECTURE behavior OF test_randgen IS
-- Component Declaration for the Unit Under Test (UUT)
component randgen is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
output : out STD_LOGIC);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic;
signal ready : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: randgen PORT MAP (
clk => clk,
reset => reset,
ready => ready,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <='0';
-- write a single line
wait;
end process;
-- Write bigregister process
write_file: process (clk) is
file my_output : TEXT open WRITE_MODE is "Test.out";
variable my_output_line : LINE;
begin
if rising_edge(clk) then
if ready = '1' and reset = '0' then
write(my_output_line,output);
writeline(my_output, my_output_line);
end if;
end if;
end process write_file;
END;
| mit | acd8055473c5aa7f0158a5bdda0ebe2e | 0.557612 | 3.86836 | false | true | false | false |
bluemurder/chaotic-rngs | rng08-vhdl/newCaoticGen2.vhd | 1 | 2,063 | ----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 11:06:29 07/26/2011
-- Design Name:
-- Module Name: newCaoticGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
--use ieee.Signed_to_Bit.all;
--use package Signed_to_Bit.all;
--Library YYY_math_lib ;
--use YYY_math_lib.ZZZ_fixed_pkg.all ;
use work.variable_Caos.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity newCaoticGen2 is
Port ( Clk : in STD_LOGIC;
reset : IN std_logic;
X_out : out signed(numbit-1 downto 0));
end newCaoticGen2;
architecture Behavioral of newCaoticGen2 is
signal x : signed(numbit-1 downto 0):= signed(convtosigned(Val_init));
begin
process(Clk,reset)
variable k : signed(numbit-1 downto 0):= signed(convtosigned(Param));
variable temp: integer;
begin
X_out <= x;
if reset = '0' then
if (Clk'event and Clk ='1') then
if (x < conv_signed(0,numBit)) then
temp:=mult(k,x);
x <= conv_signed(2**(scalamento) + temp,numBit);
temp := 0;
else
temp:=mult(k,x);
x <= conv_signed(-2**(scalamento)+temp,numBit);
temp:=0;
end if;
end if;
end if;
--X_out <=k;
end process;
end Behavioral;
| mit | daf779a4146100d99ffbb11b2c02de8c | 0.570528 | 3.600349 | false | false | false | false |
SonicFrog/CPU | extend.vhd | 1 | 598 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity extend is
port(
imm16 : in std_logic_vector(15 downto 0);
signed : in std_logic;
imm32 : out std_logic_vector(31 downto 0)
);
end extend;
architecture synth of extend is
begin
process(imm16, signed)
begin
if(signed = '1') then
imm32(31 downto 15) <= (others => imm16(15));
imm32(14 downto 0) <= imm16(14 downto 0);
else
imm32(31 downto 16) <= (others => '0');
imm32(15 downto 0) <= imm16;
end if;
end process;
end synth;
| gpl-2.0 | 5e67b18dc54caefa10875f86dbb168e4 | 0.632107 | 2.861244 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/mem_content.vhd | 1 | 26,582 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mem_content is
-- content of m_0_0
constant m_0_0_0 : BIT_VECTOR := X"E2BF124C93051303CFCCAC2652AEC692651B64AB6F4B926C081C0804080004D8";
constant m_0_0_1 : BIT_VECTOR := X"3FECF52100000231E7622B29268922F7931543E3664B3853387CEE7E65615B26";
constant m_0_0_2 : BIT_VECTOR := X"A3DF7793B9EFA732AAA25225224A0504A18029D278325DA4C200000709A03C38";
constant m_0_0_3 : BIT_VECTOR := X"16FB6E31C79C5674A32FF38CBCDDCC3AC9249D44A8BC952CC48B890935196A2A";
constant m_0_0_4 : BIT_VECTOR := X"9747FF77CA23FDFFD5BFFD5AA5FFEAD447FFAB5019BBED52FFDD5F2099A8D485";
constant m_0_0_5 : BIT_VECTOR := X"BEBDD5F1A999ABDED9BDB7E3C3C87F7FECF6FFECF7BDB97FF67BDED8BFFB3DEF";
constant m_0_0_6 : BIT_VECTOR := X"F5795E5795A769DE72DEF5AFDAA92E593BEBF001E1A9DD5E15659B6EFA4B6B57";
constant m_0_0_7 : BIT_VECTOR := X"C979FFA375642725E137AB37725E7FE8DD5909287E2725E7FECDD49094D55FD7";
constant m_0_0_8 : BIT_VECTOR := X"CC29BD98577B30A6F6615DECC5056F6418B3E6AF158EE4EE2725E7FE8DD49096";
constant m_0_0_9 : BIT_VECTOR := X"A9468AB07F9A8DD52A43627DAB64EFEB6142615DECC29BD98577B30A6F6615DE";
constant m_0_0_A : BIT_VECTOR := X"C37F407497FFC07C6F39FD9ABA7747C65D0AB43A1468556A56BA4AF04870D26E";
constant m_0_0_B : BIT_VECTOR := X"D5A1521A956A49666EFB555B43EA964B4EA54B4A2940E47252C115963FB6E0D3";
constant m_0_0_C : BIT_VECTOR := X"D914D4D3FF4DEE6A66D4D4B6A6A514D4AA6A5352B4F696CACD252979E92D4A92";
constant m_0_0_D : BIT_VECTOR := X"FB783C1E0F07825B7DA5A8B56DFEB66D412888104BF52A4192884BC2D115A6FD";
constant m_0_0_E : BIT_VECTOR := X"D949482400AE5242865241948065201242A2A48250A884F290DF6942A59554A6";
constant m_0_0_F : BIT_VECTOR := X"E37FFEB6A42ADBBBB776EDDCABFC921BF5B5247F1241E46A40934A52921525BE";
-- content of m_0_1
constant m_0_1_0 : BIT_VECTOR := X"80710228CA648A1C4AC88A359072F4E3512A2443C653894400000400080005F8";
constant m_0_1_1 : BIT_VECTOR := X"2CDA76114000020319D9E2815261D81190833D5B640CA648A1C4A25E44519435";
constant m_0_1_2 : BIT_VECTOR := X"584711D108232251871523DA353AE97B250035ADC4767BADF1000005A216E21B";
constant m_0_1_3 : BIT_VECTOR := X"227805D04096659DA10D7682C82A834F48844968961CC087A661488CA5A921C7";
constant m_0_1_4 : BIT_VECTOR := X"9050A52548A93452D3052D320429699010A5A64449CAD232525737A0D57AFD47";
constant m_0_1_5 : BIT_VECTOR := X"AF3C7AC2F0A8C7203045C2290F304D14A6AA14A6AB2A8B0A535594448529AACA";
constant m_0_1_6 : BIT_VECTOR := X"EF694EF694EF295EF2F7FDAFA41022C42AF0C8000EF6C7AD2F13A802BD1890E0";
constant m_0_1_7 : BIT_VECTOR := X"6156F7D6D11BD9855C9BA46D1855BDF1B446F6279219855BDF1B4C4E486CF694";
constant m_0_1_8 : BIT_VECTOR := X"633522C66E458CDC8B19A9163426C8B0464D9A22FF7BB0ABD9855BDF1B4C4E4A";
constant m_0_1_9 : BIT_VECTOR := X"A4EE4A88CA560B349EA159FA54B0ABB499BD99A91633522C66E458CDC8B19A91";
constant m_0_1_A : BIT_VECTOR := X"88093E5F9081BE5F9F2CA1A53F15F2360FDF1F9FBF3F1F3E7EEF2788D45AB659";
constant m_0_1_B : BIT_VECTOR := X"0F9B3A81D327503B7334ADACDE1FC8E55E10E44B0CAE7331395EC7A39F805D7E";
constant m_0_1_C : BIT_VECTOR := X"6BAC675508C62DA3AACC670263384C676633B79DCE03B9D45321990CBD7C99D6";
constant m_0_1_D : BIT_VECTOR := X"26F47A3D1E8F472B1372BDCC034A00E323915631F0E65688A40DF5FF3BCE6466";
constant m_0_1_E : BIT_VECTOR := X"A944E733BE62199C6A39D88E746399D9984833392E4E6BE9CEC4DCAAB2230E56";
constant m_0_1_F : BIT_VECTOR := X"F49B5E4973A800AD5564D56C292E39D350019D254333583B3249792C4E1F9989";
-- content of m_0_2
constant m_0_2_0 : BIT_VECTOR := X"094339A22811E831226222911943600815C01222E322D910000000040FFFFAD8";
constant m_0_2_1 : BIT_VECTOR := X"8021119540000264311108A4D1D45A49D84AB11170E2851E8712291311144691";
constant m_0_2_2 : BIT_VECTOR := X"3D374DDCCE9BB99CF4C89A01A01246517C0028D20D0300221940000404400681";
constant m_0_2_3 : BIT_VECTOR := X"810CD0934E45111006D2F323B23B637CA7D346F226C3D1A0516CA6A28BC21314";
constant m_0_2_4 : BIT_VECTOR := X"0B8A117245658508C3508C357284618A8A1186AA2C85C8D8882CD34A228540D4";
constant m_0_2_5 : BIT_VECTOR := X"5943E85C8A2008F70B2E687C38E7E1422E41422E41905CA11720C92F508B9064";
constant m_0_2_6 : BIT_VECTOR := X"4212908421480090004B1283B5B966C925DE97FFF9D83E8540F220416447DC3C";
constant m_0_2_7 : BIT_VECTOR := X"49BDDA54D2B72126FB52A54D126F769534ADC8973A9126F769134BFDA8488400";
constant m_0_2_8 : BIT_VECTOR := X"309790612B20C2564184AC830C52E418E1E3061C321924972126F769134BFDAA";
constant m_0_2_9 : BIT_VECTOR := X"2216631A98006004406B91BB5124972684B204AC8309590612F20C25E4184BC8";
constant m_0_2_A : BIT_VECTOR := X"4A211611561106100323C842E00B1C5E1C78C138718250A30EB8101A0D440300";
constant m_0_2_B : BIT_VECTOR := X"19B762E317AC5477A1F22570D9185A2D04342D13D5AE2699AB1EEC0149842C44";
constant m_0_2_C : BIT_VECTOR := X"E95497EE4949856BF25497E524BF1497EA4BD61A5CFE0BD8A6A5B53D914DFB17";
constant m_0_2_D : BIT_VECTOR := X"F60D068341A0D168FB16349044226A2428B156294B113F4AD29C4BB17B62F753";
constant m_0_2_E : BIT_VECTOR := X"A54C2D563E732B5A730B5EC2C770B12B1A5A56396D4562385A3EC58AD6ABA2C1";
constant m_0_2_F : BIT_VECTOR := X"C36DEC041630105D0BAD42EE59AC8B5B4022B535156365F16B6D129184F0B07D";
-- content of m_0_3
constant m_0_3_0 : BIT_VECTOR := X"0006843D0F080F409E1D1E5F1004CFC4F5074E20000011F80C0C0C0C000000C9";
constant m_0_3_1 : BIT_VECTOR := X"0CD2700740000109524077C210821021C00020405E10F080F40BE4F0E8F23C5F";
constant m_0_3_2 : BIT_VECTOR := X"28A7A1C00043800020044044044B6099BF800892559008B04060000106602AD8";
constant m_0_3_3 : BIT_VECTOR := X"10204088A13C8F26D0807802802A03721D084001040001020840909080000200";
constant m_0_3_4 : BIT_VECTOR := X"6121110490004488BB088BB000445DA10111768402088800884442241140C459";
constant m_0_3_5 : BIT_VECTOR := X"88054C008C465A2200603120BA379122209C22209C270A11104E128008882709";
constant m_0_3_6 : BIT_VECTOR := X"31CC731CE67B8EF399A5215935B92A5BC88137FFF96054C00111404232488000";
constant m_0_3_7 : BIT_VECTOR := X"9ED7DB6CD5166A7B5112AECD67B5F6DB35459A569D0A7B5F6DB35559AD99B9CF";
constant m_0_3_8 : BIT_VECTOR := X"9654272CA84E59509CB2A13965CA89CB2DF9F2E990C84F226A7B5F6DF35559AD";
constant m_0_3_9 : BIT_VECTOR := X"B4E7828B938683369A2EF4934B4F2246B2A6B2B139656272CA84E59509CB2A13";
constant m_0_3_A : BIT_VECTOR := X"DA1165E7451175E613AC8806CE11212710C91321932642644FC4A6AB45983619";
constant m_0_3_B : BIT_VECTOR := X"4C1833C98346713183A231309912AD57EC2057C00AD8443015F089D098044A1D";
constant m_0_3_C : BIT_VECTOR := X"7D86076808605923B246072030398607230396D8EFFC9DB80231919C39E0819C";
constant m_0_3_D : BIT_VECTOR := X"BF75BA5D6EB74AB55FABCC984223222E0D5F7475424B76C8F74D4663BF076C07";
constant m_0_3_E : BIT_VECTOR := X"E0A856ABE24015F06015B0056C015B15F0606B65887252C8AF57EAFD2BEF357A";
constant m_0_3_F : BIT_VECTOR := X"64891C042B60108F9124647C0C8C95E840215B9192B645CEBE498A5292E55EAF";
-- content of m_0_4
constant m_0_4_0 : BIT_VECTOR := X"00848018060306401898780C00840DC0C0461C20800010CC180C080C07FFF811";
constant m_0_4_1 : BIT_VECTOR := X"4C814146000001000211460000800600E08000014C006430600180C4C3C0F00C";
constant m_0_4_2 : BIT_VECTOR := X"200380E09001C120298C92C92C9B24480300000001B2990284600000064000D8";
constant m_0_4_3 : BIT_VECTOR := X"10014208A0303C2200A07A48A08A5800B9000500618231604018800014010200";
constant m_0_4_4 : BIT_VECTOR := X"210050F1B09000282082820A2814105100504145000028448C00406132050118";
constant m_0_4_5 : BIT_VECTOR := X"04202449CC440810612531088000000A1E340A1E358D00050F1AC68002878D63";
constant m_0_4_6 : BIT_VECTOR := X"6B58C6B5AD210A42918D695B74CB6ECBC0419000000802449809414010404994";
constant m_0_4_7 : BIT_VECTOR := X"5E00493A0C40E97805060BA05780124E83103A12B409780124E83103A50A158C";
constant m_0_4_8 : BIT_VECTOR := X"82018D04031A080634100C682F406341048B568CB65B2F00E9780124A83103A7";
constant m_0_4_9 : BIT_VECTOR := X"2297422300865324508C8437492F0127900E900C682018D04031A080634100C6";
constant m_0_4_A : BIT_VECTOR := X"530050C04050D0C003A20C20020010971C48913811227160C722142311843099";
constant m_0_4_B : BIT_VECTOR := X"0D983381B3467A19018A30320D402513802C13A80270241004A0001003142001";
constant m_0_4_C : BIT_VECTOR := X"1D86076828601003B246073030394607230396DC470008B21231918419ECC19C";
constant m_0_4_D : BIT_VECTOR := X"19008040603018940489C60060A0A00A8C4A224CB18000080111B03117022E43";
constant m_0_4_E : BIT_VECTOR := X"44A81289C00404A60404A90128404E84A60609C0002000002501225509492128";
constant m_0_4_F : BIT_VECTOR := X"2008011409545002000400100A8084EE08A04E50909C040094009294A6004A06";
-- content of m_0_5
constant m_0_5_0 : BIT_VECTOR := X"528E81485241520A28282814528C94914452148AA94A42540400000407FFF855";
constant m_0_5_1 : BIT_VECTOR := X"220104224000010146514A28A2A8A28ACA944A531405201520A2814141405114";
constant m_0_5_2 : BIT_VECTOR := X"8A2B8ACA8515950A28AA90A90A9344953900089251A055269260000141092840";
constant m_0_5_3 : BIT_VECTOR := X"04A32A28A050146680A93A4225200232A822955428A29428428A8505155148A8";
constant m_0_5_4 : BIT_VECTOR := X"64344AF1D2AA082504225040A5128204144A08145028250425414244AA0D1419";
constant m_0_5_5 : BIT_VECTOR := X"82151128A1112288108484AA728F82095E34895E358D2944AF1AC791A2578D63";
constant m_0_5_6 : BIT_VECTOR := X"635AC6B1AD6B58C6B18C63084A201800282247FFF52151120504532A0A082042";
constant m_0_5_7 : BIT_VECTOR := X"014124892D04940506E11892C05049224B41250A4D2405049224B4125108B18D";
constant m_0_5_8 : BIT_VECTOR := X"880B8D10171A202E34405C68830163441020C1AA010080A09405049264B41251";
constant m_0_5_9 : BIT_VECTOR := X"020748A13210088042065284A000A0894049405C6880B8D10171A202E34405C6";
constant m_0_5_A : BIT_VECTOR := X"3142D144544A41442B0A250AC85042864552A51A840A3448970210A140908044";
constant m_0_5_B : BIT_VECTOR := X"D5A1530AB56A6B480A89415095128141808541AAA832A15250651944A0328295";
constant m_0_5_C : BIT_VECTOR := X"3410910A6509024890109114848810910848828481FC902A8524493229A55A9A";
constant m_0_5_D : BIT_VECTOR := X"9951A8D46A151A054CA04A212894952A4D0223450400101C01FF00520D141A15";
constant m_0_5_E : BIT_VECTOR := X"456140A0CAA15062815068541A1502102282A0CA52829482835328332040040A";
constant m_0_5_F : BIT_VECTOR := X"204110B2A042CA8610468435A2501062A595064A820CA1CA0492108424E502A6";
-- content of m_0_6
constant m_0_6_0 : BIT_VECTOR := X"516CAA4E935593534C4EADA6516C66DA641B46AA4E4A9A600000000407FFF859";
constant m_0_6_1 : BIT_VECTOR := X"0CEB6412000001484604134D284D2AD2D21B521366A935593534DA62756D59A6";
constant m_0_6_2 : BIT_VECTOR := X"B34BD2D289A5A51296ACC0CC0CDB709981800A52109A0892512000001660085C";
constant m_0_6_3 : BIT_VECTOR := X"16AA4A2AAA9B5662240D7A10800A00800DB49466AAA8D5AA54AA296941946B36";
constant m_0_6_4 : BIT_VECTOR := X"742692719A82AB496434964281A4B2140692C85412A049402901093011A49008";
constant m_0_6_5 : BIT_VECTOR := X"021015A82DDDA88A14B0B68340882AD24E36D24E378DA869271BC7D534938DE3";
constant m_0_6_6 : BIT_VECTOR := X"214A5210A5294A5231AC6B1D92ADAB61A02040000109015A84441A4808622042";
constant m_0_6_7 : BIT_VECTOR := X"0D012499244524340921499243404926491149A95514340492649114930A94A4";
constant m_0_6_8 : BIT_VECTOR := X"E8A98DD1531BA2A637454C6E8515637450A142A2110886812434049264911493";
constant m_0_6_9 : BIT_VECTOR := X"B6C74A2120974336D8040299200680824552454C6E8A98DD1531BA2A637454C6";
constant m_0_6_A : BIT_VECTOR := X"126A52611692D261232029A8004042065D52A52AA54A550A1700B6010080B819";
constant m_0_6_B : BIT_VECTOR := X"90A2431215086840A81250400000211184B511A32234A6514469501722A48484";
constant m_0_6_C : BIT_VECTOR := X"1016D423496DB24A1356D426B6A156D42B6A1A1023000468D5254922018D1218";
constant m_0_6_D : BIT_VECTOR := X"0B0080402010088C058842A14D25241A24426644FBFC0F03C1DCF8108D111810";
constant m_0_6_E : BIT_VECTOR := X"D16D1088D4A2446AA2446091182446046A8A885294ACA4022101623308CC3118";
constant m_0_6_F : BIT_VECTOR := X"2248842488C092028054A0102C94C42AA12442929884A60084921AD6B7004202";
-- content of m_0_7
constant m_0_7_0 : BIT_VECTOR := X"0080010842414248282829141080148141020400210040400000000400000241";
constant m_0_7_1 : BIT_VECTOR := X"0A8340020000000800150A208A208208C8840800140420142082914141485014";
constant m_0_7_2 : BIT_VECTOR := X"082388C804119008888210210203148401000240008804020020000015400054";
constant m_0_7_3 : BIT_VECTOR := X"0021220000521400008038400402400088020010208010200208044440400088";
constant m_0_7_4 : BIT_VECTOR := X"6020484010800224000240002012000100480000000024000400091008040108";
constant m_0_7_5 : BIT_VECTOR := X"0000000800000082041400200080008908040908040100048402008002420100";
constant m_0_7_6 : BIT_VECTOR := X"214A52948421084210A521084804892800081000040000000000012000200000";
constant m_0_7_7 : BIT_VECTOR := X"4010000804409100448048805004000201102400040100400020100241421084";
constant m_0_7_8 : BIT_VECTOR := X"8202010404020808041010082140004104085080804020009100400020100241";
constant m_0_7_9 : BIT_VECTOR := X"06874021008542A0D08410048920002910091010082020104040208080410100";
constant m_0_7_A : BIT_VECTOR := X"11005141004851410B0000020200109604000008000010000700342110802815";
constant m_0_7_B : BIT_VECTOR := X"04881340900260000009000000000300A0040080801201000024000080120204";
constant m_0_7_C : BIT_VECTOR := X"1480010024000000810001000008000100008A00030000680120090009A4409A";
constant m_0_7_D : BIT_VECTOR := X"090080402010080C0480C208209091100406664C00000000000000100D001A00";
constant m_0_7_E : BIT_VECTOR := X"406001804A210022210028400A10028022220048420210000101203300C82018";
constant m_0_7_F : BIT_VECTOR := X"2248801200D04802801020140244406200900648080C22000C00000001000602";
-- content of m_1_0
constant m_1_0_0 : BIT_VECTOR := X"E5E0924F05AD3BEC52829CFDAFFF7EFFAF2B5FD201E0900D20B7B41DE0924832";
constant m_1_0_1 : BIT_VECTOR := X"04A24A04964929EFCFD28E74A2E9673A5934F4A39D2CABA4B16D65E03F249241";
constant m_1_0_2 : BIT_VECTOR := X"8A412056D752A9E02F7BD752A9E02F73D09E0F04824124920C0E9E0944555535";
constant m_1_0_3 : BIT_VECTOR := X"000001E3C3777EAB7773F56EEC7BADDDCA9078241EA78249549176D5B5AA48A4";
constant m_1_0_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_8 : BIT_VECTOR := X"880140807C6807C6803A2C000000000000000000000000000000000000000000";
constant m_1_0_9 : BIT_VECTOR := X"801CE4B9C536A49F2B8E0029E91F562502C2982B550056AA53E19B235C46394F";
constant m_1_0_A : BIT_VECTOR := X"4895717C7129B6C4810133C1085B924C90C9A388000A2E3310AE4EA0AE239675";
constant m_1_0_B : BIT_VECTOR := X"5F47CD474F6ABF32B73D539E882248FB762D558A32E44D0BC944CC72B4B9571C";
constant m_1_0_C : BIT_VECTOR := X"E31C831C849DC891DC85115F2D5048D56322B9195BD5AB46ADECC8F355D5C2EE";
constant m_1_0_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000724AC77C";
constant m_1_0_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_1
constant m_1_1_0 : BIT_VECTOR := X"931179D88A1ECA9082DEDFAD29DAD2BDE73BDB351F10CCEB5038631311CCD440";
constant m_1_1_1 : BIT_VECTOR := X"8E75677ACCF79C1D7439D3AE751CEDD732FB0E74EB98965E76CA305BF95E76A3";
constant m_1_1_2 : BIT_VECTOR := X"B6A351492202815BFC9F2AA6D35BFC972F31188E46A04135100EF11CCB2AAA84";
constant m_1_1_3 : BIT_VECTOR := X"0000017E215953EA557A7D4AAD4AA955A9A8C46A22DC432A0654255320A32A32";
constant m_1_1_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000100000";
constant m_1_1_8 : BIT_VECTOR := X"A8012080330804A680330E000000000000000000000000000000000000000000";
constant m_1_1_9 : BIT_VECTOR := X"4002C943DB0B492E3096001832E8624B8480A04C660098CC30608537586EB0C1";
constant m_1_1_A : BIT_VECTOR := X"1C296235629D20280E24574421100489948022940017300000309420C2110A65";
constant m_1_1_B : BIT_VECTOR := X"281B8D0AC168C81056346B1A310501494C08881022608086110808A034380628";
constant m_1_1_C : BIT_VECTOR := X"C12009200829420294112FA852B801220084980466090502130081034601826C";
constant m_1_1_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000601988A0";
constant m_1_1_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_2
constant m_1_2_0 : BIT_VECTOR := X"78348B01A5C785C90F250000520425210042148348355AE034FD8E38345A0D3F";
constant m_1_2_1 : BIT_VECTOR := X"A2C2AD5558A8B4611C4B48E2D2258471691E12C238B1CBAAD4E48139EF22C068";
constant m_1_2_2 : BIT_VECTOR := X"B06834A086360939E3B0E6360939E3B0E08341A2E06B64834FFC8345A5575508";
constant m_1_2_3 : BIT_VECTOR := X"0000011068B0B9220B0204416040882C481A0D069F20D57ACAF4720392157357";
constant m_1_2_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_2_8 : BIT_VECTOR := X"88016000664807C6001F28000000000000000000000000000000000000000000";
constant m_1_2_9 : BIT_VECTOR := X"001A14B8F744A490B4BC0028C9FA6B2F864E18707800E0F051ABA26E02DC0546";
constant m_1_2_A : BIT_VECTOR := X"0DCC09C009E81544850F2E8F7BC35245A859C118001F167733964B40D2B69009";
constant m_1_2_B : BIT_VECTOR := X"53442C5546623A5A208110408863F0A6376165CA01424E83C8E42256899DF194";
constant m_1_2_C : BIT_VECTOR := X"159D859D871619E1618B9F9329D988D9752A50A913CBAAECA9E22AEB117C6141";
constant m_1_2_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000000B8DDF4C";
constant m_1_2_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_3
constant m_1_3_0 : BIT_VECTOR := X"155615EA90AC88E810208563085694842148C6112952AF9D12B0BB5152AD44CF";
constant m_1_3_1 : BIT_VECTOR := X"357856D0ADA15F117515ABA5788AF5D2B432456AE95EA2056C89515CA9057A2D";
constant m_1_3_2 : BIT_VECTOR := X"E22516808E995E5CA8922E995E5CA89220956A956A252D9133F2152AD1061028";
constant m_1_3_3 : BIT_VECTOR := X"00000052A51D1C621102AC42225188444A8955A2E5A54AB7456C44EA2542B62B";
constant m_1_3_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_8 : BIT_VECTOR := X"D00141002E3800D3806552000000000000000000000000000000000000000000";
constant m_1_3_9 : BIT_VECTOR := X"800A8DE26151EDB41A14000C9BE3336B86001201800403001930A86610CC2064";
constant m_1_3_A : BIT_VECTOR := X"0848432C4388860C94346614A50986C198404010001704004004D80068500C41";
constant m_1_3_B : BIT_VECTOR := X"014D064C6432631AE42D3216995715940004011D1484C20B582CA4C098388834";
constant m_1_3_C : BIT_VECTOR := X"81B009B00AB2822B28193EC17C14AB80402721013B55AE209DAA49B193A21488";
constant m_1_3_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000414BCA04";
constant m_1_3_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_4
constant m_1_4_0 : BIT_VECTOR := X"044304E218A00029326DEE399EF398C73BDE72047046251847B8885046251180";
constant m_1_4_1 : BIT_VECTOR := X"312C128827104A801084A8813C4270409E00213A204AB1412863C18208412884";
constant m_1_4_2 : BIT_VECTOR := X"408C438287188C82000007188C82000008842231288D2484200104627820823A";
constant m_1_4_3 : BIT_VECTOR := X"000000308C0407620022EC40045988008E23108840611895413871918D209409";
constant m_1_4_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_5 : BIT_VECTOR := X"0000000000000000000000000000000040000000000000000000000000000000";
constant m_1_4_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000180000";
constant m_1_4_8 : BIT_VECTOR := X"F0016180757807C5005F56000000000000000000000000000000000000000000";
constant m_1_4_9 : BIT_VECTOR := X"600050138A0A000A84A80012200000002484E301FF8603FF247B05184A309491";
constant m_1_4_A : BIT_VECTOR := X"D0012801281122201A3A105AD69070080082278C000038226138076012C18A0C";
constant m_1_4_B : BIT_VECTOR := X"3802A9129148800012804940218020684808EA45A168048C01009830A0044209";
constant m_1_4_C : BIT_VECTOR := X"50000800080882408812803802A1003A90885A044C10010A0609800A40108165";
constant m_1_4_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000281410E0";
constant m_1_4_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_5
constant m_1_5_0 : BIT_VECTOR := X"0D46902A346828214480842958C6B18C6B1A525069468129063221C54681418F";
constant m_1_5_1 : BIT_VECTOR := X"340A419481290282409022041A4835020D20A4188106682409635490A1241A0D";
constant m_1_5_2 : BIT_VECTOR := X"CA0D06B652422190A81202422190A81204146A341A0C001063F2146814924929";
constant m_1_5_3 : BIT_VECTOR := X"000000428D0505495041812A0A112541068351A0C4A51A0CD40931858F0A04A0";
constant m_1_5_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_5_8 : BIT_VECTOR := X"6804000029280090802228000000000000000000000000000000000000000000";
constant m_1_5_9 : BIT_VECTOR := X"DFFFE01FFEFC000FFF7DFFFFC0FFFE0FAFDFFB7FFF8203FF7FDBFF7FFEFFFDFF";
constant m_1_5_A : BIT_VECTOR := X"FFFFF0FFF0FFF001CFAF1FEF7BFFE01FC1FC0821FFFF7EFFBFFE07DFFFEF7DFB";
constant m_1_5_B : BIT_VECTOR := X"FFF3FFE3FFFF1FFF1FFFCFFFE7E1F87EFFFFFF83FFF01F5F8301FC3FE3FFFF8F";
constant m_1_5_C : BIT_VECTOR := X"EF0FFF8FFF8FFFF8FFFF8FFE07FE1C7FFFF9FC7FCFFFF91FE7FFFE7FFCFFFFFF";
constant m_1_5_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000779F9FF9";
constant m_1_5_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_6
constant m_1_6_0 : BIT_VECTOR := X"4C02046010E2202954818C6B5AC6B5AC694843402002234C02B289D4022300A0";
constant m_1_6_1 : BIT_VECTOR := X"910811802300462A02046811080210088408810A0442E0010963650208811804";
constant m_1_6_2 : BIT_VECTOR := X"480402A4965AAD020248965AAD02024894C020110805B6C02800002210000828";
constant m_1_6_3 : BIT_VECTOR := X"000000100404044A40538948087029010A0100805000088DD11971958FA88C88";
constant m_1_6_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_8 : BIT_VECTOR := X"E80000802820008000020A000000000000000000000000000000000000000000";
constant m_1_6_9 : BIT_VECTOR := X"E01EF011FF7E000FBFBE003FE01F7F078088827E0004FC007FFBBF7F1EFE3DFF";
constant m_1_6_A : BIT_VECTOR := X"1DFC78FC787DA3E010101FD0841BF009BCD3E79C000F2044422007E0FEF79E7D";
constant m_1_6_B : BIT_VECTOR := X"7F13EF13FF789F7887BC03DE00F0FC7F7F4DFFC537EE0F8FC1E0FE343D3DFF8C";
constant m_1_6_C : BIT_VECTOR := X"F7810781078FD1F8FD0F81FF03F9E27FF789FBBC4FDF89EE27EFE27BC47FE7EF";
constant m_1_6_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000007BDFDFFC";
constant m_1_6_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
-- content of m_1_7
constant m_1_7_0 : BIT_VECTOR := X"4442006210200021100084294A521084294A52042042032842300940420310A0";
constant m_1_7_1 : BIT_VECTOR := X"1018008001000280128020900840104804002008240220000800500008801884";
constant m_1_7_2 : BIT_VECTOR := X"C084420242000000024892000000024894442210188492442800042030020008";
constant m_1_7_3 : BIT_VECTOR := X"00000000840405010010A02002140400422110885001080C4018000001000C00";
constant m_1_7_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_8 : BIT_VECTOR := X"0805808008080000802228000000000000000000000000000000000000000000";
constant m_1_7_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
end mem_content;
package body mem_content is
end mem_content;
| mit | 051a84f8a08bb73362433b78ba13a1c3 | 0.839252 | 2.617627 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/midi_decoder.vhd | 1 | 7,564 | -- entity that contains an FSM to decode midi type 1 files such that the FPGA can
-- play them
--
-- Determines if a file that has been sent to midi_ram is actually a midi file.
--
-- Reads the following data:
-- * number of tracks
-- * address and length of each track
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.midi_pkg.all;
entity midi_decoder is
generic(
max_read_bytes : integer
);
port(
ctrl : in ctrl_t;
buttons : in button_arr;
-- ram read interface
read_start_addr : out unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0) := (others => '0');
read_num_bytes : out integer range 0 to max_read_bytes;
read_en : out std_logic;
read_busy : in std_logic;
midi_ram_out : in std_logic_vector((max_read_bytes * 8) - 1 downto 0);
contents_count : in natural range 0 to midi_file_rx_bram_depth;
chunk_data : out chunk_data_t_arr;
num_chunks : out integer range 0 to max_num_tracks - 1;
enable_decoder : out std_logic;
errors : out errors_t;
playing_en : out std_logic
);
end;
architecture rtl of midi_decoder is
signal read_start_addr_int : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal enable_decoder_int : std_logic;
signal read_num_bytes_int : integer range 0 to max_read_bytes;
type midi_decoder_state_t is (
initial_wait,
read_chunk_header_1,
read_chunk_header_2,
read_mthd_1,
read_mthd_2,
update_track_details,
done
);
signal state : midi_decoder_state_t;
type header_data_t is record
num_tracks : unsigned(15 downto 0);
division_ticks : unsigned(15 downto 0);
end record;
signal first_chunk : std_logic;
signal errors_int : errors_t;
signal errors_noreg : errors_t;
signal header_data : header_data_t;
signal header_data_noreg : header_data_t;
signal chunk_data_int : chunk_data_t_arr;
signal chunk_no : integer range 0 to max_num_tracks;
signal chunk_is_mtrk : std_logic;
signal chunk_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal chunk_length : unsigned(31 downto 0);
-- ram related signals
signal read_busy_d1 : std_logic;
begin
read_start_addr <= read_start_addr_int;
enable_decoder <= enable_decoder_int;
errors <= errors_int;
chunk_data <= chunk_data_int;
-- Once the user is sure that the RAM is full of midi data, they will press q
-- to start the player.
wait_enable : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
enable_decoder_int <= '0';
else
if buttons(q).pressed = '1' then
enable_decoder_int <= '1';
end if;
end if;
end if;
end process;
delay_read_busy : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_busy_d1 <= read_busy;
end if;
end process;
midi_decoder_fsm : process(ctrl.clk) is
impure function ram_read_finished return boolean is
begin
return read_busy = '0' and read_busy_d1 = '1';
end;
-- Make setting literal addresses slightly easier
impure function format_addr(addr : std_logic_vector) return unsigned is
begin
return resize(unsigned(addr), read_start_addr_int'length);
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
read_start_addr_int <= (others => '0');
state <= initial_wait;
errors_int <= (others => '0');
header_data <= (others => (others => '0'));
chunk_no <= 0;
chunk_data_int <= (others => (others => (others => '0')));
chunk_addr <= to_unsigned(0, chunk_addr'length);
chunk_length <= to_unsigned(0, chunk_length'length);
playing_en <= '0';
read_en <= '0';
first_chunk <= '1';
else
case state is
when initial_wait =>
if enable_decoder_int = '1' then
state <= read_chunk_header_1;
end if;
-- Reads the first 8 fixed bytes of a chunk.
when read_chunk_header_1 =>
-- Preset the errors. Hopefully we will clear them very soon.
-- Find the start of the chunk we are about to read by examining
-- summing the addr and length of the previous chunk
if first_chunk = '0' then
chunk_addr <= resize(8 + chunk_addr + chunk_length, chunk_addr'length);
read_start_addr_int <= resize(8 + chunk_addr + chunk_length, chunk_addr'length);
end if;
read_num_bytes_int <= 8;
-- Check if we are done by seeing if there is
-- room for another chunk before the end of the midi file.
if chunk_addr + chunk_length + 8 >= contents_count then
state <= done;
else
state <= read_chunk_header_2;
read_en <= '1';
end if;
when read_chunk_header_2 =>
read_en <= '0';
if ram_read_finished then
chunk_length <= unsigned(midi_ram_out(31 downto 0));
case midi_ram_out(63 downto 32) is
when mthd => state <= read_mthd_1;
when mtrk => state <= update_track_details;
when others => report "unknown chunk type found" severity note;
end case;
end if;
-- Check that the midi header exists in the received data. This is a
-- sanity check to make sure we actually have a midi file.
--
-- Also check that this midi file is format 1. This midi decoder
-- can only play format 1 tracks.
when read_mthd_1 =>
first_chunk <= '0';
errors_int.no_mthd <= '0';
read_start_addr_int <= chunk_addr + 8;
read_en <= '1';
read_num_bytes_int <= 6;
state <= read_mthd_2;
when read_mthd_2 =>
read_en <= '0';
if ram_read_finished then
if to_integer(unsigned(midi_ram_out(47 downto 32))) = 1 then
errors_int.not_format_1 <= '0';
else
errors_int.not_format_1 <= '1';
end if;
header_data.num_tracks <= unsigned(midi_ram_out(31 downto 16));
header_data.division_ticks <= unsigned(midi_ram_out(15 downto 0));
state <= read_chunk_header_1;
end if;
-- If we have correctly read a track chunk then store it.
when update_track_details =>
chunk_data_int(chunk_no).length <= chunk_length;
chunk_data_int(chunk_no).base_addr <= chunk_addr;
chunk_no <= chunk_no + 1;
state <= read_chunk_header_1;
when done =>
if errors_int.no_mthd = '0' and errors_int.not_format_1 = '0' and chunk_no > 1 then
playing_en <= '1';
num_chunks <= chunk_no - 1;
end if;
end case;
end if;
end if;
end process;
read_num_bytes <= read_num_bytes_int;
end;
| bsd-2-clause | 91d2c771a7ba687f3345fe3f6eb7fa94 | 0.562797 | 3.670063 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_2/diviseur.vhdl | 1 | 4,100 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity diviseur is
port (
ck: in std_logic;
go: in std_logic;
n: in std_logic_vector(7 downto 0);
p: in std_logic_vector(7 downto 0);
q: out std_logic_vector(7 downto 0);
ok: out std_logic
);
end entity;
architecture rtl of diviseur is
-- a type declaration to make the following easier to read
subtype state is std_logic_vector(1 downto 0);
-- State encoding:
constant waiting: state := "00"; -- rem: wait is a reserved word...
constant increment: state := "01";
constant done1: state := "10";
constant done2: state := "11";
signal current_state, next_state: state;
signal rN, rX, rP, rQ, newX, newQ: unsigned(7 downto 0);
-- unsigned/signed is a std_logic_vector interpreted as an integer:
-- we can use +, - and * on it. Defined in numeric_std
signal diff: signed(8 downto 0); -- one bit more for the sign bit
signal loadX, loadQ, loadN, loadP, resetX, resetQ, pp: std_logic;
begin -- Reminder: all that follows are parallel statements
------- Combinatorial parts of the datapath --------
newX <= rX + rP; -- this + is defined in the numeric_std library
q <= std_logic_vector(rQ - 1);
newQ <= rQ + 1;
-- comparison by subtracting, then observing the sign bit
-- we first cast each (unsigned) input into a signed,
-- with sign bit 0 (the & is a concatenation)
-- then perform the subtraction.
diff <= signed('0' & rN) - signed('0' & newX);
pp <= not diff(8);
-------- datapath registers --------
-- the register for N
process (ck)
begin
if (rising_edge(ck)) then
if (loadN='1') then
rN <= unsigned(N);
end if;
end if;
end process;
-- the register for X, it has a reset
process (ck)
begin
if (rising_edge(ck)) then
if (resetX = '1') then
rX <= "00000000"; -- written like this, it is a synchronous reset
elsif (loadX = '1') then
rX <= newX;
end if;
end if;
end process;
-- the register for P
process (ck)
begin
if (rising_edge(ck)) then
if (loadP='1') then
rP <= unsigned(P);
end if;
end if;
end process;
-- the register for Q, it has a reset
process (ck)
begin
if (rising_edge(ck)) then
if (resetQ = '1') then
rQ <= "00000000";
elsif (loadQ = '1') then
rQ <= newQ;
end if;
end if;
end process;
------------------ Now the automaton ------------------
-- transition function --
next_state <=
waiting when go = '0' else
increment when current_state = waiting and go = '1' else
increment when current_state = increment and pp = '1' else
done1 when current_state = increment and pp = '0' else
done2 when current_state = done1;
-- output function --
loadN <= '1' when current_state = waiting else '0';
loadP <= '1' when current_state = waiting else '0';
resetX <= '1' when current_state = waiting else '0';
resetQ <= '1' when current_state = waiting else '0';
loadX <= '1' when current_state = increment else '0';
loadQ <= '1' when current_state = increment else '0';
ok <= '1' when current_state = done1 or current_state = done2 else '0';
-- the state register --
-- Since we use go as a reset, we do not strictly follow the specification of the
-- TD, where go is allowed to go back to 0 during the computation.
-- But then the TD misses the reset signal...
process (ck)
begin
if (rising_edge(ck)) then
if (go = '0') then -- here we use go as a reset, active low
current_state <= waiting;
else
current_state <= next_state;
end if;
end if;
end process;
end architecture;
| unlicense | d63c59ebe3e00a0fa2a9125a46d3abaf | 0.55561 | 3.882576 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/midi_top.vhd | 1 | 6,362 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.midi_pkg.all;
entity midi_top is
port(
ctrl : in ctrl_t;
buttons : in button_arr;
enqueue : in std_logic;
write_in_data : in std_logic_vector(7 downto 0);
midi_nos : out midi_note_arr_t;
empty : out std_logic;
full : out std_logic;
enable_decoder : out std_logic;
errors : out errors_t;
contents_count : out natural range 0 to midi_file_rx_bram_depth
);
end;
architecture rtl of midi_top is
signal contents_count_int : natural range 0 to midi_file_rx_bram_depth;
signal midi_nos_int : midi_note_arr_t;
signal read_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_addr_track_dec : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_addr_midi_dec : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal midi_ram_data : std_logic_vector(7 downto 0);
signal chunk_data : chunk_data_t_arr;
signal num_chunks : integer range 0 to max_num_tracks - 1;
signal playing_en : std_logic;
--constant midi_pulse_time : time := 1 us;
constant midi_pulse_time : time := 5 ms;
constant midi_pulse_clocks : integer := midi_pulse_time / clk_period;
constant midi_pulse_time_faster : time := 3 ms;
constant midi_pulse_faster_clocks : integer := midi_pulse_time / clk_period;
constant midi_pulse_time_fastest : time := 1 ms;
constant midi_pulse_fastest_clocks : integer := midi_pulse_time / clk_period;
signal midi_pulse_counter : integer range 0 to midi_pulse_clocks - 1;
signal midi_pulse_limit : integer range 0 to midi_pulse_clocks - 1;
signal midi_pulses : midi_pulse_arr;
signal midi_pulse_acks : midi_pulse_arr;
-- midi ram signals
constant max_read_bytes : integer := 10;
signal read_start_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_num_bytes : integer range 0 to max_read_bytes;
signal read_en : std_logic;
signal read_busy : std_logic;
signal midi_ram_out : std_logic_vector((max_read_bytes * 8) - 1 downto 0);
-- midi ram signals from midi decoder
signal read_start_addr_midi_dec : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_num_bytes_midi_dec : integer range 0 to max_read_bytes;
signal read_en_midi_dec : std_logic;
-- midi ram signals from track decoder
signal read_start_addr_track_dec : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal read_num_bytes_track_dec : integer range 0 to max_read_bytes;
signal read_en_track_dec : std_logic;
begin
contents_count <= contents_count_int;
midi_nos <= midi_nos_int;
midi_ram_top_1 : entity work.midi_ram_top
generic map (
max_read_bytes => max_read_bytes,
queue_width => 8)
port map (
ctrl => ctrl,
enqueue => enqueue,
write_in_data => write_in_data,
empty => empty,
full => full,
contents_count => contents_count_int,
read_start_addr => read_start_addr,
read_num_bytes => read_num_bytes,
read_en => read_en,
read_busy => read_busy,
midi_ram_out => midi_ram_out);
midi_decoder_1 : entity work.midi_decoder
generic map(
max_read_bytes => max_read_bytes
)
port map (
ctrl => ctrl,
buttons => buttons,
-- ram read interface
read_start_addr => read_start_addr_midi_dec,
read_num_bytes => read_num_bytes_midi_dec,
read_en => read_en_midi_dec,
read_busy => read_busy,
midi_ram_out => midi_ram_out,
contents_count => contents_count_int,
chunk_data => chunk_data,
num_chunks => num_chunks,
enable_decoder => enable_decoder,
errors => errors,
playing_en => playing_en
);
track_decoder_1 : entity work.track_decoder
generic map (
max_read_bytes => 10
)
port map (
ctrl => ctrl,
midi_pulses => midi_pulses,
midi_pulse_acks => midi_pulse_acks,
playing_en => playing_en,
chunk_data => chunk_data,
num_chunks => num_chunks,
-- ram read interface
read_start_addr => read_start_addr_track_dec,
read_num_bytes => read_num_bytes_track_dec,
read_en => read_en_track_dec,
read_busy => read_busy,
midi_ram_out => midi_ram_out,
midi_nos => midi_nos_int
);
read_start_addr <= read_start_addr_midi_dec when playing_en = '0'
else read_start_addr_track_dec;
read_num_bytes <= read_num_bytes_midi_dec when playing_en = '0'
else read_num_bytes_track_dec;
read_en <= read_en_midi_dec when playing_en = '0' else
read_en_track_dec;
gen_midi_pulse_strobe : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
midi_pulse_limit <= midi_pulse_clocks - 1;
for i in 1 to max_num_tracks - 1 loop
midi_pulses(i) <= '0';
end loop;
else
if buttons(z).pressed = '1' then
midi_pulse_limit <= midi_pulse_clocks - 1;
elsif buttons(x).pressed = '1' then
midi_pulse_limit <= midi_pulse_faster_clocks - 1;
elsif buttons(c).pressed = '1' then
midi_pulse_limit <= midi_pulse_faster_clocks - 1;
end if;
for i in 1 to max_num_tracks - 1 loop
if midi_pulse_acks(i) = '1' then
midi_pulses(i) <= '0';
end if;
end loop;
if midi_pulse_counter = midi_pulse_clocks - 1 then
midi_pulse_counter <= 0;
for i in 1 to max_num_tracks - 1 loop
midi_pulses(i) <= '1';
end loop;
else
midi_pulse_counter <= midi_pulse_counter + 1;
end if;
end if;
end if;
end process;
end;
| bsd-2-clause | 39e7cb32d359a7d1788c5152b6761f3a | 0.593838 | 3.329147 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/Original 512 Fifos/fifo_generator_64_512.vhd | 1 | 134,346 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_512.vhd
-- /___/ /\ Timestamp: Thu Jul 25 19:22:26 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_512;
architecture STRUCTURE of fifo_generator_64_512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"F3A2F300FFA2FF00"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 97a97b3a0bd34b7b8217682df45d320c | 0.689258 | 2.640915 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/opcode_decoder.vhd | 1 | 33,501 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle; -- current cycle (M1, M2, ...)
INT : IN std_logic; -- interrupt
RRZ : IN std_logic; -- RR is zero
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal INT_M1 : std_logic;
signal INT_M2 : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED; -- show when CPU is halted
-- HLT <= '1' when DISABLE_CNT = 0 else '0'; -- show when ints enabled
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_M2 <= '0';
HALTED <= '0';
elsif (CE = '1' and T2 = '1') then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_M2 <= INT_M1;
end if;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_M2, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_SP <= SP_NOP;
D_WE_O <= '0';
D_RD_O <= '0';
D_LOCK <= '0';
D_IO <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
INT_M1 <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_M2 = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
INT_M1 <= IS_M1;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_INT);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= IS_M1;
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M2, PC_JMP);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_JPRR);
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= IS_M1;
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
D_RD_O <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_WE_SP <= SP_LOAD;
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= '1';
D_LOCK <= IS_M1;
D_WE_SP <= SP_LOAD;
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_O <= IS_M1;
D_WE_SP <= SP_LOAD;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_IO;
D_RD_O <= IS_M1;
D_IO <= IS_M1;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
D_WE_O <= IS_M1;
D_IO <= IS_M1;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_O <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_O <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_cI16_L;
D_WE_O <= IS_M2;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_WE_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_SMQ <= IS_M3;
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_WE_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_SMQ <= IS_M2;
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
D_WE_O <= IS_M2;
D_OP <= ALU_X_OR_Y;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
D_WE_O <= IS_M1;
D_OP <= ALU_X_OR_Y;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_SA <= hadr(IS_M3, ADR_16SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_RR <= IS_M3_M4;
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_RR <= IS_M2_M3;
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_8SP_H);
D_RD_O <= IS_M2_M3;
D_LOCK <= IS_M2;
D_WE_LL <= IS_M3_M4;
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_8SP_H);
D_RD_O <= IS_M1_M2;
D_LOCK <= IS_M1;
D_WE_LL <= IS_M2_M3;
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_RD_O <= IS_M2;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_RD_O <= IS_M1;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_RD_O <= IS_M1;
D_WE_O <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= IS_M1;
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= IS_M1;
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
| mit | 61942dfe475b62a15be3c210f83f7531 | 0.422495 | 2.218756 | false | false | false | false |
RafaelCatrou/docker_ghdl | src/ghdl_check1/b.vhd | 1 | 882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity b is
port(
clk : in std_logic;
din_enable : in std_logic;
din_value : in unsigned(15 downto 0);
dout_enable : out std_logic;
dout_value : out unsigned(15 downto 0)
);
end b;
architecture b_archi1 of b is
begin
proc_add : process(clk)
begin
if rising_edge(clk) then
dout_enable <= din_enable;
if din_enable = '1' then
dout_value <= resize(din_value * 2,dout_value'length);
end if;
end if;
end process proc_add;
end b_archi1;
architecture b_archi2 of b is
begin
proc_add : process(clk)
begin
if rising_edge(clk) then
dout_enable <= din_enable;
if din_enable = '1' then
dout_value <= resize(din_value * 3,dout_value'length);
end if;
end if;
end process proc_add;
end b_archi2;
| apache-2.0 | 7ee2b2f1cce9f86be3d8b5afea340687 | 0.613379 | 3.094737 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/constants.vhd | 1 | 2,564 | -- Tweakable constants
library ieee;
use ieee.std_logic_1164.all;
use work.utils.all;
package constants is
constant clk_period : time := 1 sec / 50_000_000;
-- todo this constant is useless. Remove it.
constant spi_word_length : integer := 8;
-----------------------------------------------------------------------------
--sine wave generator configuration
-- The higher this number, the more concurrent midi notes can be played
constant num_sines : integer := 10;
-----------------------------------------------------------------------------
-- Always ensure that the maximum number of brams is used.
--each The lx9 FPGA has 64 brams.
constant device_brams : integer := 50;
-- The number of brams used for the SPI tx buffer. The higher this number,
-- the more protection against the pi hiccoughing and failing to read data
-- from the FPGA.
constant spi_tx_ram_brams : integer := 4;
-- brams for holding sine lookup data. The higher this number, the more
-- accurate the sine lookup process is
constant sine_lut_brams : integer := 2;
-- Allocate all remaining block rams to the receive buffer from the pi. The
-- higher this number, the more music can be played.
constant midi_file_rx_brams : integer := device_brams - spi_tx_ram_brams - sine_lut_brams;
-- each spartan 6 RAMB8BWER is 1024 bits long
constant device_bram_depth : integer := 1024;
constant spi_tx_ram_depth : integer := spi_tx_ram_brams * device_bram_depth;
constant sine_lut_bram_depth : integer := sine_lut_brams * device_bram_depth;
constant midi_file_rx_bram_depth : integer := midi_file_rx_brams * device_bram_depth;
-------------------------------------------------------------------------------
-- The max number of words (each word is currently 2 bytes) that SPI transmitter will send
-- in a frame. Must be less than (256/word size)
constant spi_tx_max_block_size : integer := 100;
-----------------------------------------------------------------------------
-- midi constants
-- The maximum number of tracks in a midi file that may be simulataneously decoded.
constant max_num_tracks : integer := 5;
-----------------------------------------------------------------------------
-- Midi track constants.
-- Record some constant data as defined in the midi format.
-- The midi spec expects MThd to be the first four bytes of a midi file.
constant mthd : std_logic_vector(31 downto 0) := to_slv("MThd");
constant mtrk : std_logic_vector(31 downto 0) := to_slv("MTrk");
end;
| bsd-2-clause | 6532ca9a1041f640841d8f8530d9ec7c | 0.593214 | 4.231023 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/ws2812/ws2812_data.vhd | 1 | 1,706 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.math_real.all;
library virtual_button_lib;
package ws2812_data is
type ws2812_t is
record
r : integer range 0 to 255;
g : integer range 0 to 255;
b : integer range 0 to 255;
end record;
type ws2812_array_t is array (integer range <>) of ws2812_t;
procedure set_ws2812(
signal w : inout ws2812_t;
r : in integer range 0 to 255;
g : in integer range 0 to 255;
b : in integer range 0 to 255
);
function lighten_ws2812 (
input : ws2812_t;
lightness : real)
return ws2812_t;
procedure clear_ws2812(signal w : inout ws2812_t);
end ws2812_data;
package body ws2812_data is
function lighten_ws2812(input : ws2812_t;
lightness : real)
return ws2812_t is
variable ret : ws2812_t;
begin
ret.r := integer(real(input.r) * lightness);
ret.g := integer(real(input.g) * lightness);
ret.b := integer(real(input.b) * lightness);
return ret;
end;
procedure set_ws2812(
signal w : inout ws2812_t;
r : in integer range 0 to 255;
g : in integer range 0 to 255;
b : in integer range 0 to 255
) is
begin
w.r <= r;
w.g <= g;
w.b <= b;
end set_ws2812;
procedure clear_ws2812(signal w : inout ws2812_t) is
begin
w.r <= 0;
w.g <= 0;
w.b <= 0;
end clear_ws2812;
end ws2812_data;
| bsd-2-clause | c07c8465bb99313600c094ef8fa4fdb9 | 0.593787 | 3.312621 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/master.vhd | 1 | 19,956 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Control workflow
-- Requests Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic;
done : out std_logic;
started : out std_logic;
-- kernels communication signals
current_level : in unsigned(31 downto 0); -- Current Level
kernel_rx_vld : in std_logic;
wr_offset : in unsigned(31 downto 0);
wr_reserved_space : in unsigned(31 downto 0);
wr_used_space : out unsigned(31 downto 0);
-- Queue pointers
nq_address : in std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
-- Process 2 signals
p2_req_q_rd_enb : out std_logic;
p2_req_q_dout : in std_logic_vector(63 downto 0);
p2_req_q_valid : in std_logic;
p2_req_q_empty : in std_logic;
-- Process 3 signals
p3_req_q_rd_enb : out std_logic;
p3_req_q_dout : in std_logic_vector(63 downto 0);
p3_req_q_valid : in std_logic;
p3_req_q_empty : in std_logic;
-- Process 4 signals
p4_done : in std_logic;
p4_addr_q_rd_enb : out std_logic;
p4_addr_q_dout : in std_logic_vector(63 downto 0);
p4_addr_q_valid : in std_logic;
p4_addr_q_empty : in std_logic;
p4_info_q_rd_enb : out std_logic;
p4_info_q_dout : in std_logic_vector(63 downto 0);
p4_info_q_valid : in std_logic;
p4_info_q_empty : in std_logic
);
end entity; -- Master process
architecture arch of master is
type state_type is (st_idle, st_busy, st_done);
signal state : state_type;
type muxstatetype is (mx_start, mx_stall, mx_p1, mx_p2, mx_p3, mx_p4, mx_p5);
signal mux_state : muxstatetype;
signal mux_green_light : std_logic;
signal saved_state : std_logic_vector(7 downto 0);
signal saved_addr : std_logic_vector(63 downto 0);
signal saved_data : std_logic_vector(63 downto 0);
signal used_space : unsigned(31 downto 0); -- What I consumed from the reserved space
signal local_offset : unsigned(31 downto 0);
signal pause_p4 : std_logic;
signal done_count : integer range 0 to 3;
-- debug signals
signal p2_req_count_debug : unsigned(31 downto 0);
begin
started <= '1' when state = st_busy else '0';
wr_used_space <= used_space;
mux_green_light <= '1' when ((mux_state = mx_start)
or (mux_state = mx_stall and saved_state /= x"04")
or (mux_state = mx_stall and saved_state = x"04" and used_space < wr_reserved_space and wr_reserved_space > 0)
or (mux_state = mx_p1 and p1_req_q_valid = '1')
or (mux_state = mx_p2 and p2_req_q_valid = '1')
or (mux_state = mx_p3 and p3_req_q_valid = '1')
or (mux_state = mx_p4 and p4_info_q_valid = '1' and used_space < wr_reserved_space and wr_reserved_space > 0)
or (mux_state = mx_p5 and p4_addr_q_valid = '1'))
else '0';
-- Requests Multiplexer
-- Read from the processes' request queues with the specific tag
Master : process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
state <= st_idle;
busy <= '0';
done <= '0';
done_count <= 0;
-- reset master process control signals
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p4_info_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
else
-- Kernel go idle
--- Reset signals
--- Wait for enable signal
if (state = st_idle) then
busy <= '0';
done_count <= 0;
-- reset master process control signals
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
-- If got enable signal, go busy
if (enable = '1') then
busy <= '1';
done <= '0';
done_count <= 0;
state <= st_busy;
else
busy <= '0';
state <= st_idle;
end if ;
-- Go Busy:
--- MULTIPLEX requests to memory controller
--- Set done signal if everything is done
elsif (state = st_busy) then
-- is memory controller asserting rd/wr stall?
if (mc_rd_rq_stall = '1' or mc_wr_rq_stall = '1') then
-- save addr/data
if (p1_req_q_valid = '1') then
saved_state <= x"01";
saved_addr <= p1_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_req_q_valid = '1') then
saved_state <= x"02";
saved_addr <= p2_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_req_q_valid = '1') then
saved_state <= x"03";
saved_addr <= p3_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p4_info_q_valid = '1') then
-- Push CSR to NQ
saved_state <= x"04";
saved_addr <= (others => '0');
saved_data <= p4_info_q_dout;
mux_state <= mx_stall;
elsif (p4_addr_q_valid = '1') then
-- Vist node by setting CSR to current level
saved_state <= x"05";
saved_addr <= p4_addr_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
else
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mux_state;
end if;
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- If not a memory controller rd/wr stall
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0') then
if (mux_state = mx_stall) then
-- Issue a request, if comming from a stall
if (saved_state = x"01") then
-- Request from current queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"02") then
-- Request neighbors (IDs of 32-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "10";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"03") then
-- Request neighbors informations (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"04") then
-- Push CSR to Next Queue
if (used_space < wr_reserved_space and wr_reserved_space > 0) then
-- Write node CSR to next queue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(nq_address) + (wr_offset + local_offset) * 8, 48));
mc_req_wrd_rdctl <= saved_data;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- Reset MC
mc_req_ld <= '0';
mc_req_st <= '0';
-- keep state
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
end if;
elsif (saved_state = x"05") then
-- Visit node by setting CSR (current_level & 1)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl <= x"00000000" & std_logic_vector(current_level(30 downto 0)) & '1';
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if;
elsif (mux_state = mx_p1 and p1_req_q_valid = '1') then
-- TODO: fix that to replace the whole code of process 1
-- Request from current queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p1_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"01";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p2 and p2_req_q_valid = '1') then
-- Request neighbors (IDs of 32-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "10";
mc_req_vaddr <= p2_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"02";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p3 and p3_req_q_valid = '1') then
-- Request neighbors informations (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p3_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"03";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p4 and p4_info_q_valid = '1') then
if (used_space < wr_reserved_space and wr_reserved_space > 0) then
-- Write node CSR to next queue
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= std_logic_vector(resize(unsigned(nq_address) + (wr_offset + local_offset) * 8, 48));
mc_req_wrd_rdctl <= p4_info_q_dout;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- Reset MC
mc_req_ld <= '0';
mc_req_st <= '0';
-- keep state
saved_state <= x"04";
saved_addr <= (others => '0');
saved_data <= p4_info_q_dout;
end if;
elsif (mux_state = mx_p5 and p4_addr_q_valid = '1') then
-- Write new CSR (current_level & 1)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= p4_addr_q_dout(47 downto 0);
mc_req_wrd_rdctl <= x"00000000" & std_logic_vector(current_level(30 downto 0)) & '1';
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if; -- End mux states execution
-- Pop from queue if mux is ready
if ((mux_state = mx_start)
or (mux_state = mx_stall and saved_state /= x"04")
or (mux_state = mx_stall and saved_state = x"04" and used_space < wr_reserved_space and wr_reserved_space > 0)
or (mux_state = mx_p1 and p1_req_q_valid = '1')
or (mux_state = mx_p2 and p2_req_q_valid = '1')
or (mux_state = mx_p3 and p3_req_q_valid = '1')
or (mux_state = mx_p4 and p4_info_q_valid = '1' and used_space < wr_reserved_space and wr_reserved_space > 0)
or (mux_state = mx_p5 and p4_addr_q_valid = '1')) then
-- if (mux_green_light = '1') then
if (p4_addr_q_empty = '0') then
-- If process 4 addr queue is not empty, make a write request
p4_addr_q_rd_enb <= '1';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p5;
elsif (p4_info_q_empty = '0' and wr_reserved_space > 0 and used_space < wr_reserved_space) then
-- If process 4 info queue is not empty, make a write request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '1';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p4;
elsif (p3_req_q_empty = '0') then
-- If process 3 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '1';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p3;
elsif (p2_req_q_empty = '0') then
-- If process 2 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '1';
p1_req_q_rd_enb <= '0';
mux_state <= mx_p2;
elsif (p1_req_q_empty = '0') then -- TODO: fix that to replace the whole code of process 1
-- If process 1 queue isn't empty, make a read request
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '1';
mux_state <= mx_p1;
else
-- reset
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
mux_state <= mx_start;
end if;
else
if (mux_state = mx_p4 and (used_space >= wr_reserved_space or wr_reserved_space = 0)) then
mux_state <= mx_stall;
else
mux_state <= mux_state;
end if;
-- reset
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
end if; -- end if mux green light!
else
-- weird case, memory controller not ready yet
mux_state <= mux_state;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p4_info_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
end if; -- end check for rd/wr stall
-- Update the used space count ---------------------------------------- CHECK THIS LOGIC HERE
if (used_space >= wr_reserved_space and kernel_rx_vld = '1') then
local_offset <= (others => '0');
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0' and used_space < wr_reserved_space and wr_reserved_space > 0
and ((mux_state = mx_stall and saved_state = x"04") or (mux_state = mx_p4 and p4_info_q_valid = '1'))) then
used_space <= used_space + 1;
local_offset <= local_offset + 1;
end if;
----- TODO #####
-- if all processes are done and queues ar eempty go done
if (p4_done = '1' and p4_addr_q_empty = '1' and p4_info_q_empty = '1' and p1_req_q_empty = '1'
and p2_req_q_empty = '1' and p3_req_q_empty = '1' and done_count < 3) then
state <= st_busy;
done_count <= done_count + 1;
elsif (p4_done = '1' and p4_addr_q_empty = '1' and p4_info_q_empty = '1' and p1_req_q_empty = '1'
and p2_req_q_empty = '1' and p3_req_q_empty = '1' and done_count = 3) then
state <= st_done;
done_count <= 0;
else
state <= st_busy;
done_count <= 0;
end if;
if (p2_req_q_valid = '1') then
p2_req_count_debug <= p2_req_count_debug + 1;
end if;
-- Kernel is done with its part of the level
elsif (state = st_done) then
-- set done signal one and go idle
state <= st_idle;
busy <= '0';
done <= '1';
done_count <= 0;
-- reset saved state
pause_p4 <= '0';
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
used_space <= (others => '0');
local_offset <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p4_info_q_rd_enb <= '0';
p4_addr_q_rd_enb <= '0';
p3_req_q_rd_enb <= '0';
p2_req_q_rd_enb <= '0';
p1_req_q_rd_enb <= '0';
-- reset debug signals
p2_req_count_debug <= (others => '0');
else
state <= st_idle;
end if; -- end if state
end if; -- end if rst
end if; -- end if clk
end process; -- Master
end architecture ; -- arch | apache-2.0 | 7c752c178e9fc9fbd62b50173c811f91 | 0.509721 | 2.653371 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/ws2812/ws2812_drv.vhd | 1 | 7,571 | library IEEE;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.ws2812_data.all;
entity ws2812_drv is
generic(
num_leds : positive
);
port(
ctrl : in ctrl_t;
data_in : in ws2812_t;
current_led : out integer range 0 to num_leds;
data_out : out std_logic
);
end ws2812_drv;
architecture rtl of ws2812_drv is
---------------------------------------------------------------------------------------------------
-- Timing constants
-- These constants are pullsed directly from the datasheet for the
-- LEDs (http://www.adafruit.com/datasheets/WS2812.pdf)
---------------------------------------------------------------------------------------------------
constant t0h : time := 350 ns;
constant t1h : time := 700 ns;
constant t0l : time := 800 ns;
constant t1l : time := 600 ns;
constant res : time := 51 us;
-- clockified constants
-- To make the firmware wait for the times specified by these times, we will count the number of
-- FPGA clock cycles
-- in each one (Note that the FPGA is clocked at 50 MHz).
constant t0h_clocks : positive := calc_delay_clocks(clk_period, t0h);
constant t1h_clocks : positive := calc_delay_clocks(clk_period, t1h);
constant t0l_clocks : positive := calc_delay_clocks(clk_period, t0l);
constant t1l_clocks : positive := calc_delay_clocks(clk_period, t1l);
constant res_clocks : positive := calc_delay_clocks(clk_period, res);
-- timer. These are the signals we need to implement the counter that makes the firmware
-- wait for these times.
signal timer : natural range 0 to res_clocks;
signal timer_limit : natural range 0 to res_clocks;
signal timer_done : std_logic;
---------------------------------------------------------------------------------------------------
-- These signals index the data.
---------------------------------------------------------------------------------------------------
-- The index in data_in of the bit that is currently being sent to the LEDs.
signal bit_index : integer range 0 to 23;
-- The value of the bit that is being sent to the LEDs. This signal exists solely to decrease logic depth.
signal current_bit : std_logic;
signal current_led_int : integer range 0 to num_leds;
---------------------------------------------------------------------------------------------------
-- statey things.
---------------------------------------------------------------------------------------------------
type driver_state is (high, low, wait_res);
signal state : driver_state;
---------------------------------------------------------------------------------------------------
--provide useful symbolic names for some things
impure function current_bit_is_last return boolean is
begin
return bit_index = 0;
end current_bit_is_last;
impure function current_led_is_last return boolean is
begin
return current_led_int = num_leds - 1;
end current_led_is_last;
begin
current_led <= current_led_int;
-- Place the bit that is currently being to the LEDs in its own register. This helps us decrease
-- logic depth, which is good for high speed operation.
--
-- Additionally, output blank if the FPGA is in reset.
select_current_bit : process (ctrl.clk) is
variable data_in_as_slv : std_logic_vector(23 downto 0);
begin
if rising_edge(ctrl.clk) then
data_in_as_slv := (
std_logic_vector(to_unsigned(data_in.g, 8)) &
std_logic_vector(to_unsigned(data_in.r, 8)) &
std_logic_vector(to_unsigned(data_in.b, 8)));
if ctrl.reset_n = '0' then
current_bit <= '0';
else
current_bit <= data_in_as_slv(bit_index);
end if;
end if;
end process select_current_bit;
-- Here is the driver's main logic. Its derivation, planning and rationalisation is as follows:
--
-- * Observe that the way the LEDs differentiate between a '1' and a '0' is by timing not by bit pattern;
-- to send a single bit, we send a '1' followed by an '0'.
--
-- * Because of this, sequencing is very easy.. To send a bitpattern to the LEDs, we send an
-- alternating series of '1's and '0's followed by a stop (which is just a very long '0').
--
-- * It is easy to separate out timing and sequencing, so we will choose to do that.
-- The FSM will handle sequencing, and the limit_select process will handle timing.
--
-- * This means that the FSM will just sequence through '1' and '0' states, checking for when
-- it has reached the last bit. When it reaches the last bit, it should output a stop bit.
fsm_nextstate : process (ctrl.clk) is
-- We are finishing outputting a bit of data, so choose whether the next thing is to output
-- the next bit or output a stop bit.
procedure dispatch_next is
begin
if current_bit_is_last then
if current_led_is_last then
state <= wait_res;
else
current_led_int <= current_led_int + 1;
bit_index <= 23;
state <= high;
end if;
else
bit_index <= bit_index - 1;
state <= high;
end if;
end dispatch_next;
begin
if rising_edge(ctrl.clk) then
case state is
when wait_res =>
bit_index <= 23;
current_led_int <= 0;
if timer_done = '1' then
state <= high;
end if;
when high =>
if timer_done = '1' then
state <= low;
end if;
when low =>
if timer_done = '1' then
dispatch_next;
end if;
end case;
end if;
end process fsm_nextstate;
-- This counter lets us implement the timings of the output serial stream.
counter_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if timer >= timer_limit then
timer <= 0;
timer_done <= '1';
else
timer <= timer + 1;
timer_done <= '0';
end if;
end if;
end process counter_proc;
-- Select out counter limit here so that we can do timing.
-- We need two pieces of information here. Whether the value of the current bit is a '1' or a '0',
-- and whether we are outputting the high part or the low part of that bit. The current_bit signal
-- tells us the value of the current bit. The FSM state tells us the whether we are currently in a
-- high or a low.
limit_select : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if state = wait_res then
timer_limit <= res_clocks;
elsif state = high and current_bit = '1' then
timer_limit <= t1h_clocks;
elsif state = high and current_bit = '0' then
timer_limit <= t0h_clocks;
elsif state = low and current_bit = '1' then
timer_limit <= t1l_clocks;
else
-- By elimination, state = low and current_bit = '0'
timer_limit <= t0l_clocks;
end if;
end if;
end process limit_select;
-- Here is where we actually set out output.
-- We just dispatch based off the current state of the FSM.
output_select : process (ctrl.clk) is
begin
--register output to prevent glitching.
if rising_edge(ctrl.clk) then
case state is
when wait_res | low =>
data_out <= '0';
when high =>
data_out <= '1';
end case;
end if;
end process output_select;
end rtl;
| bsd-2-clause | 9a29ef41506c5bfbbf7566169d19a36e | 0.5739 | 4.035714 | false | false | false | false |
willtmwu/vhdlExamples | Project/top_controller.vhd | 1 | 18,437 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: top_controller.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Controls memory access and full message sending in 6 packets
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
LIBRARY work;
use work.project_nrf_subprogV2.all;
entity top_controller is
Port (
clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
-- Buttons and display for direct memory view
bSend : in STD_LOGIC; -- Right Button
bModeChange : in STD_LOGIC; -- Up Button
bEnterData : in STD_LOGIC; -- Bottom Button
bCount : in STD_LOGIC; -- Left Button
-- Switch send/receive address, base1, base 2, base 3, base 4, partner
sTransmission : in STD_LOGIC_VECTOR(2 downto 0);
-- switch High Speed Transmission
sHighSpeed : in STD_LOGIC;
displayLower : out STD_LOGIC_VECTOR(15 downto 0); -- RECV(1,0) | SEND(1,0)
displayUpper : out STD_LOGIC_VECTOR(15 downto 0); -- MODE(0-A) | COUNT(0-31)
data_nib : in std_logic_vector(3 downto 0);
-- NRF CTRL Lines fed down to SPI_CTRL
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : in std_logic;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
end top_controller;
architecture Behavioral of top_controller is
COMPONENT SPI_ctrlr
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
m_en : IN std_logic;
m_ready : OUT std_logic;
sTransmissionLines : in STD_LOGIC_VECTOR(2 downto 0);
send_now : IN std_logic;
send_message : IN std_logic_vector(55 downto 0);
send_active : OUT std_logic;
recv_dtr : OUT std_logic;
recv_message : OUT std_logic_vector(55 downto 0);
recv_active : OUT std_logic;
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : in std_logic;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
component RAM_BLOCK -- Array of 64 nibbles
port(
clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
d_i : in std_logic_vector(3 downto 0);
d_o : out std_logic_vector(3 downto 0)
);
end COMPONENT;
signal SEND_CACHE : std_logic_vector(55 downto 0) := (others => '0');
signal SEND_STRING_WEN : std_logic := '0';
signal SEND_STRING_EN : std_logic := '0';
signal SEND_STRING_ADDR : std_logic_vector(5 downto 0) := (others => '0');
signal SEND_STRING_Di : std_logic_vector(3 downto 0) := (others => '0');
signal SEND_STRING_Do : std_logic_vector(3 downto 0);
signal SEND_STRING_OFFSET : integer range 13 downto 0 := 0;
signal DATA_ENTER_L : std_logic := '0';
signal RECV_CACHE : std_logic_vector(55 downto 0) := (others => '0');
signal RECV_STRING_WEN : std_logic := '0';
signal RECV_STRING_EN : std_logic := '0';
signal RECV_STRING_ADDR : std_logic_vector(5 downto 0) := (others => '0');
signal RECV_STRING_Di : std_logic_vector(3 downto 0) := (others => '0');
signal RECV_STRING_Do : std_logic_vector(3 downto 0);
signal RECV_PACKET_Num : integer range 15 downto 0 := 6;
signal RECV_STRING_OFFSET : integer range 13 downto 0 := 0;
-- 2 FSM, 1 main controller, 1 change state
type DISPLAY_MODE_FSM is (DISPLAY_PAUSED, DISPLAY_SPEED_1, DISPLAY_SPEED_2, DISPLAY_SPEED_3);
signal DATA_Counter : integer range 31 downto 0 := 0;
signal DISPLAY_STATE : DISPLAY_MODE_FSM := DISPLAY_PAUSED;
signal DISPLAY_L_BYTE : std_logic := '0';
signal DISPLAY_SEND_BYTE : std_logic_vector(7 downto 0) := (others => '0');
signal DISPLAY_RECV_BYTE : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Generation for Display
signal clockScalers : std_logic_vector(26 downto 0) := (others => '0');
signal COUNT_T_SIG : std_logic := '0';
type COUNT_FSM is (COUNT_IDLE, COUNT_HIGH);
signal COUNT_STATE : COUNT_FSM := COUNT_IDLE;
-- Delay Counter
constant SPEED_Low : integer := 500_000_000;
constant SPEED_High : integer := 930_000;
signal TRANS_SPEED : integer range SPEED_LOW downto 0 := 0;
signal COUNTER_MSG_DELAY : integer range SPEED_LOW downto 0 := 0;
-- Initialisation Counter
constant INIT_DELAY : integer := 1000_000;
signal COUNTER_INIT : integer range INIT_DELAY downto 0 := 0;
-- Message Counter
constant TOTAL_PACKETS : integer := 6;
signal MSG_SENT : integer range TOTAL_PACKETS downto 0 := 0; -- 32 Bytes, 6/Packet = 6 packets total. Header is 0-5
-- Main FSM
type TOP_CTRL_FSM is (TOP_CTRL_INIT, TOP_CTRL_IDLE, TOP_CTRL_RECV_CACHE, TOP_CTRL_SEND_CACHE, TOP_CTRL_SEND, TOP_CTRL_SEND_WAIT, TOP_CTRL_DELAY);
signal TOP_CTRL_STATE : TOP_CTRL_FSM := TOP_CTRL_INIT;
-- SPI Submodule
signal SPI_MC_en : std_logic := '0';
signal SPI_MC_ready : std_logic;
signal SPI_C_send_now : std_logic := '0';
signal SPI_C_send_active : std_logic;
signal SPI_C_send_message : std_logic_vector(55 downto 0) := (others => '0');
signal SPI_C_recv_dtr : std_logic;
signal SPI_C_recv_active : std_logic;
signal SPI_C_recv_message : std_logic_vector(55 downto 0);
begin
TRANS_SPEED <= SPEED_LOW when sHighSpeed = '0' else SPEED_HIGH;
displayLower(7 downto 0) <= DISPLAY_SEND_BYTE;
displayLower(15 downto 8) <= DISPLAY_RECV_BYTE;
displayUpper(7 downto 0) <= to_BCD(std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter, 5))); --Display BCD of Count
-- with DISPLAY_STATE select
-- displayUpper(15 downto 8) <= x"0A" when DISPLAY_PAUSED,
-- x"01" when DISPLAY_SPEED_1,
-- x"02" when DISPLAY_SPEED_2,
-- x"03" when DISPLAY_SPEED_3;
with DISPLAY_STATE select
displayUpper(11 downto 8) <= x"A" when DISPLAY_PAUSED,
x"1" when DISPLAY_SPEED_1,
x"2" when DISPLAY_SPEED_2,
x"3" when DISPLAY_SPEED_3;
displayUpper(15 downto 12) <= std_logic_vector(IEEE.numeric_std.to_unsigned(RECV_Packet_num, 4));
-- Main FSM Loop
process (masterReset, clk)
variable upper_vect : integer range 55 downto 0 := 0;
variable lower_vect : integer range 55 downto 0 := 0;
variable packet_number : integer range 5 downto 0 := 0;
begin
if (masterReset = '1') then
MSG_SENT <= 0;
COUNTER_MSG_DELAY <= 0;
COUNTER_INIT <= 0;
TOP_CTRL_STATE <= TOP_CTRL_INIT;
elsif rising_edge(clk) then
case TOP_CTRL_STATE is
when TOP_CTRL_INIT =>
if (COUNTER_INIT = INIT_DELAY) then
if (SPI_MC_Ready = '1') then
SEND_STRING_EN <= '1'; -- Enable both RAM Modules
RECV_STRING_EN <= '1';
TOP_CTRL_STATE <= TOP_CTRL_IDLE; -- NRF Chip initialised
end if;
else
COUNTER_INIT <= COUNTER_INIT + 1;
SPI_MC_EN <= '1';
end if;
when TOP_CTRL_IDLE =>
if (bSend = '1') then
MSG_SENT <= 0;
SEND_STRING_WEN <= '0';
SEND_STRING_ADDR <= (others => '0');
SEND_STRING_OFFSET <= 1;
TOP_CTRL_STATE <= TOP_CTRL_SEND_CACHE;
elsif (SPI_C_recv_dtr = '1') then
-- Filter and store in the data
RECV_CACHE <= SPI_C_recv_message;
RECV_STRING_OFFSET <= 0;
RECV_STRING_WEN <= '0';
RECV_STRING_ADDR <= (others => '0');
if ( SPI_C_recv_message(51 downto 48) = "1111" ) then
RECV_PACKET_Num <= conv_integer( IEEE.std_logic_arith.unsigned(SPI_C_recv_message(55 downto 52)) );
else
RECV_PACKET_Num <= 6;
end if;
TOP_CTRL_STATE <= TOP_CTRL_RECV_CACHE;
elsif(bEnterData = '1') then
SEND_STRING_WEN <= '1';
SEND_STRING_Di <= data_nib;
if (Data_Enter_L = '0') then
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2, 6));
DATA_Enter_L <= '1';
else
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2+1, 6));
DATA_Enter_L <= '0';
end if;
elsif((COUNT_T_SIG = '1') or (bCount = '1')) then
if (Data_counter < 31) then
DATA_Counter <= DATA_Counter + 1;
else
DATA_Counter <= 0;
end if;
else
SEND_STRING_WEN <= '0';
RECV_STRING_WEN <= '0';
if (DISPLAY_L_Byte = '0') then
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2+1, 6));
RECV_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2+1, 6));
DISPLAY_SEND_BYTE(7 downto 4) <= SEND_STRING_Do;
DISPLAY_RECV_BYTE(7 downto 4) <= RECV_STRING_Do;
DISPLAY_L_Byte <= '1';
else
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2, 6)); -- Reverse offset, and multiples due to clock delay
RECV_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(Data_counter*2, 6)); -- Reverse offset, and multiples due to clock delay
DISPLAY_SEND_BYTE(3 downto 0) <= SEND_STRING_Do;
DISPLAY_RECV_BYTE(3 downto 0) <= RECV_STRING_Do;
DISPLAY_L_Byte <= '0';
end if;
end if;
when TOP_CTRL_RECV_CACHE =>
if( RECV_PACKET_Num <= 5 ) then
if (RECV_PACKET_NUM = 5) then
if (RECV_STRING_OFFSET <= 3) then
RECV_STRING_WEN <= '1';
lower_vect := RECV_STRING_OFFSET*4;
upper_vect := ((RECV_STRING_OFFSET+1)*4)-1;
RECV_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(RECV_PACKET_Num*12 + RECV_STRING_OFFSET, 6));
RECV_STRING_Di <= RECV_CACHE(upper_vect downto lower_vect);
RECV_STRING_OFFSET <= RECV_STRING_OFFSET + 1;
else
RECV_STRING_WEN <= '0';
RECV_STRING_OFFSET <= 0;
-- RECV_STRING_ADDR <= (others => '0');
TOP_CTRL_STATE <= TOP_CTRL_IDLE;
end if;
else
if (RECV_STRING_OFFSET <= 11) then
RECV_STRING_WEN <= '1';
lower_vect := RECV_STRING_OFFSET*4;
upper_vect := ((RECV_STRING_OFFSET+1)*4)-1;
RECV_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(RECV_PACKET_Num*12 + RECV_STRING_OFFSET, 6));
RECV_STRING_Di <= RECV_CACHE(upper_vect downto lower_vect);
RECV_STRING_OFFSET <= RECV_STRING_OFFSET + 1;
else
RECV_STRING_WEN <= '0';
RECV_STRING_OFFSET <= 0;
TOP_CTRL_STATE <= TOP_CTRL_IDLE;
end if;
end if;
else
if (RECV_STRING_OFFSET <= 13) then
RECV_STRING_WEN <= '1';
lower_vect := RECV_STRING_OFFSET*4;
upper_vect := ((RECV_STRING_OFFSET+1)*4)-1;
RECV_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(RECV_STRING_OFFSET, 6));
RECV_STRING_Di <= RECV_CACHE(upper_vect downto lower_vect);
RECV_STRING_OFFSET <= RECV_STRING_OFFSET + 1;
else
RECV_STRING_WEN <= '0';
RECV_STRING_OFFSET <= 0;
TOP_CTRL_STATE <= TOP_CTRL_IDLE;
end if;
end if;
when TOP_CTRL_SEND_CACHE =>
if ( MSG_SENT = (TOTAL_PACKETS-1) ) then
if (SEND_STRING_OFFSET<=4) then -- Unload from RAM and cache
if (SEND_STRING_OFFSET>=2) then
upper_vect := ((SEND_STRING_OFFSET-1)*4)-1;
lower_vect := (SEND_STRING_OFFSET-2)*4;
SEND_CACHE(upper_vect downto lower_vect) <= SEND_STRING_Do;
end if;
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(MSG_SENT*12 + SEND_STRING_OFFSET, 6));
SEND_STRING_OFFSET <= SEND_STRING_OFFSET + 1;
else
SEND_STRING_OFFSET <= 1;
SEND_CACHE(47 downto 16) <= (others => '0');
SEND_CACHE(51 downto 48) <= (others => '1'); -- Byte 6
SEND_CACHE(55 downto 52) <= std_logic_vector(IEEE.numeric_std.to_unsigned(MSG_SENT, 4));
TOP_CTRL_STATE <= TOP_CTRL_SEND;
end if;
elsif (MSG_SENT <= (TOTAL_PACKETS-2)) then
if (SEND_STRING_OFFSET <= 12) then -- Unload from RAM and cache
if (SEND_STRING_OFFSET>=2) then
upper_vect := ((SEND_STRING_OFFSET-1)*4)-1;
lower_vect := (SEND_STRING_OFFSET-2)*4;
SEND_CACHE(upper_vect downto lower_vect) <= SEND_STRING_Do;
end if;
SEND_STRING_ADDR <= std_logic_vector(IEEE.numeric_std.to_unsigned(MSG_SENT*12 + SEND_STRING_OFFSET, 6));
SEND_STRING_OFFSET <= SEND_STRING_OFFSET + 1;
else
SEND_STRING_OFFSET <= 1;
SEND_CACHE(51 downto 48) <= (others => '1'); -- Byte 6
SEND_CACHE(55 downto 52) <= std_logic_vector(IEEE.numeric_std.to_unsigned(MSG_SENT, 4));
TOP_CTRL_STATE <= TOP_CTRL_SEND;
end if;
end if;
when TOP_CTRL_SEND =>
SPI_C_send_now <= '1';
SPI_C_send_message <= SEND_CACHE;
TOP_CTRL_STATE <= TOP_CTRL_SEND_WAIT;
when TOP_CTRL_SEND_WAIT =>
SPI_C_send_now <= '0';
if (SPI_C_send_active = '0') then
TOP_CTRL_STATE <= TOP_CTRL_DELAY;
end if;
when TOP_CTRL_DELAY => -- Delay after each packet send
if (COUNTER_MSG_DELAY = TRANS_SPEED) then
COUNTER_MSG_DELAY <= 0;
if (MSG_SENT = TOTAL_PACKETS-1) then
TOP_CTRL_STATE <= TOP_CTRL_IDLE;
MSG_SENT <= 0;
else
TOP_CTRL_STATE <= TOP_CTRL_SEND_CACHE;
MSG_SENT <= MSG_SENT + 1;
end if;
else
COUNTER_MSG_DELAY <= COUNTER_MSG_DELAY + 1;
end if;
end case;
end if;
end process;
-- Counting Signal Generation
process (masterReset, clk) begin
if (masterReset = '1') then
COUNT_T_SIG <= '0';
COUNT_STATE <= COUNT_IDLE;
elsif rising_edge(clk) then
case COUNT_STATE is
when COUNT_IDLE =>
if (DISPLAY_STATE = DISPLAY_PAUSED) then
COUNT_T_SIG <= '0';
elsif (DISPLAY_STATE = DISPLAY_SPEED_1) then
if (clockScalers(26) = '1') then
COUNT_T_SIG <= '1';
COUNT_STATE <= COUNT_HIGH;
end if;
elsif (DISPLAY_STATE = DISPLAY_SPEED_2) then
if (clockScalers(25) = '1') then
COUNT_T_SIG <= '1';
COUNT_STATE <= COUNT_HIGH;
end if;
elsif (DISPLAY_STATE = DISPLAY_SPEED_3) then
if (clockScalers(24) = '1') then
COUNT_T_SIG <= '1';
COUNT_STATE <= COUNT_HIGH;
end if;
end if;
when COUNT_HIGH =>
COUNT_T_SIG <= '0';
if (DISPLAY_STATE = DISPLAY_SPEED_1) then
if (clockScalers(26) = '0') then
COUNT_STATE <= COUNT_IDLE;
end if;
elsif (DISPLAY_STATE = DISPLAY_SPEED_2) then
if (clockScalers(25) = '0') then
COUNT_STATE <= COUNT_IDLE;
end if;
elsif (DISPLAY_STATE = DISPLAY_SPEED_3) then
if (clockScalers(24) = '0') then
COUNT_STATE <= COUNT_IDLE;
end if;
end if;
end case;
end if;
end process;
-- DISPLAY_STATE switching
process (masterReset, clk) begin
if (masterReset = '1') then
DISPLAY_STATE <= DISPLAY_PAUSED;
elsif rising_edge(clk) then
case DISPLAY_STATE is
when DISPLAY_PAUSED =>
if (bModeChange = '1') then
DISPLAY_STATE <= DISPLAY_SPEED_1;
end if;
when DISPLAY_SPEED_1 =>
if (bModeChange = '1') then
DISPLAY_STATE <= DISPLAY_SPEED_2;
end if;
when DISPLAY_SPEED_2 =>
if (bModeChange = '1') then
DISPLAY_STATE <= DISPLAY_SPEED_3;
end if;
when DISPLAY_SPEED_3 =>
if (bModeChange = '1') then
DISPLAY_STATE <= DISPLAY_PAUSED;
end if;
end case;
end if;
end process;
process (clk, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif rising_edge(clk) then
clockScalers <= clockScalers + '1';
end if;
end process;
SPI_C: SPI_ctrlr PORT MAP (
clk,
masterReset,
SPI_MC_en,
SPI_MC_ready,
sTransmission,
SPI_C_send_now,
SPI_C_send_message,
SPI_C_send_active,
SPI_C_recv_dtr,
SPI_C_recv_message,
SPI_C_recv_active,
hamming_err,
-- NRF Control Lines
IRQ,
CE,
CS,
SCLK,
MOSI,
MISO,
LED_SPI
);
SEND_RAM: RAM_BLOCK PORT MAP (
clk,
SEND_STRING_WEN,
SEND_STRING_EN,
SEND_STRING_ADDR,
SEND_STRING_Di,
SEND_STRING_Do
);
RECV_RAM: RAM_BLOCK PORT MAP (
clk,
RECV_STRING_WEN,
RECV_STRING_EN,
RECV_STRING_ADDR,
RECV_STRING_Di,
RECV_STRING_Do
);
end Behavioral;
| apache-2.0 | ca58aaa9448c4cc4f2b98cb2d0c81097 | 0.53973 | 3.32318 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/FA/FA_tb.vhd | 1 | 1,780 |
library ieee;
use ieee.std_logic_1164.all;
entity FA_tb is
end FA_tb;
architecture tb of FA_tb is
component FA is
port( A, B, Cin : in std_logic;
Sout, Cout : out std_logic);
end component;
signal A, B, Cin, Sout, Cout : std_logic;
begin
mapping: FA port map(A, B, Cin, Sout, Cout);
--concurrent processes
process
begin
Cin <= '0'; wait for 5 ns;
Cin <= '1'; wait for 5 ns;
end process;
process
variable errCnt : integer := 0;
begin
--TEST 1
A <= '0';
B <= '1';
wait for 10 ns;
assert(Sout = '0') report "Sout error 1" severity error;
assert(Cout = '1') report "Cout error 1" severity error;
if(Sout /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;
--TEST 2
A <= '1';
B <= '1';
wait for 10 ns;
assert(Sout = '1') report "Sout error 2" severity error;
assert(Cout = '1') report "Cout error 2" severity error;
if(Sout /= '0' or Cout /= '1') then
errCnt := errCnt + 1;
end if;
--TEST 3
A <= '1';
B <= '0';
wait for 10 ns;
assert(Sout = '0') report "Sout error 3" severity error;
assert(Cout = '1') report "Cout error 3" severity error;
if(Sout /= '1' or Cout /= '0') then
errCnt := errCnt + 1;
end if;
---- SoutMARY ----
if(errCnt = 0) then
assert false report "Success!" severity note;
else
assert false report "Faillure!" severity note;
end if;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of FA_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END | mit | 019d30884b6e4d02f4739d5d01f91d64 | 0.493258 | 3.59596 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/opcode_fetch.vhd | 1 | 1,483 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then LPC <= X"0000";
elsif (CE = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 06336ffb22c4ee0b70dd4b0a7da324e2 | 0.601483 | 2.782364 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/cygraph.vhd | 1 | 52,640 | library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
-- use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity cygraph is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- ae-to-ae signals
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
nxtae_rx_data : in std_logic_vector(31 downto 0);
nxtae_rx_vld : in std_logic;
prvae_rx_data : in std_logic_vector(31 downto 0);
prvae_rx_vld : in std_logic;
nxtae_tx_data : out std_logic_vector(31 downto 0);
nxtae_tx_vld : out std_logic;
prvae_tx_data : out std_logic_vector(31 downto 0);
prvae_tx_vld : out std_logic;
-- Graph Parameters
n_in : in std_logic_vector(63 downto 0); -- Number of nodes in graph
non_zeros_in : in std_logic_vector(63 downto 0); -- Number of non-zero edges
current_level_in : in std_logic_vector(63 downto 0); -- Current level of traversal
cq_count_in : in std_logic_vector(63 downto 0); -- How many nodes to traverse in the current level
nq_count_out : out std_logic_vector(63 downto 0); -- How many nodes to traverse in the next level
-- Input Graph Pointers (Represented in Custom CSR)
graphData_in : in std_logic_vector(63 downto 0);
graphInfo_in : in std_logic_vector(63 downto 0);
-- Queue pointers
queue1_address_in : in std_logic_vector(63 downto 0);
queue2_address_in : in std_logic_vector(63 downto 0);
reach_queue_in : in std_logic_vector(63 downto 0);
-- MC0 port signals
mc0_req_ld : out std_logic;
mc0_req_st : out std_logic;
mc0_req_size : out std_logic_vector(1 downto 0);
mc0_req_vaddr : out std_logic_vector(47 downto 0);
mc0_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc0_req_flush : out std_logic;
mc0_rd_rq_stall : in std_logic;
mc0_wr_rq_stall : in std_logic;
mc0_rsp_push : in std_logic;
mc0_rsp_stall : out std_logic;
mc0_rsp_data : in std_logic_vector(63 downto 0);
mc0_rsp_rdctl : in std_logic_vector(31 downto 0);
mc0_rsp_flush_cmplt : in std_logic;
-- MC1 port signals
mc1_req_ld : out std_logic;
mc1_req_st : out std_logic;
mc1_req_size : out std_logic_vector(1 downto 0);
mc1_req_vaddr : out std_logic_vector(47 downto 0);
mc1_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc1_req_flush : out std_logic;
mc1_rd_rq_stall : in std_logic;
mc1_wr_rq_stall : in std_logic;
mc1_rsp_push : in std_logic;
mc1_rsp_stall : out std_logic;
mc1_rsp_data : in std_logic_vector(63 downto 0);
mc1_rsp_rdctl : in std_logic_vector(31 downto 0);
mc1_rsp_flush_cmplt : in std_logic;
-- MC2 port signals
mc2_req_ld : out std_logic;
mc2_req_st : out std_logic;
mc2_req_size : out std_logic_vector(1 downto 0);
mc2_req_vaddr : out std_logic_vector(47 downto 0);
mc2_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc2_req_flush : out std_logic;
mc2_rd_rq_stall : in std_logic;
mc2_wr_rq_stall : in std_logic;
mc2_rsp_push : in std_logic;
mc2_rsp_stall : out std_logic;
mc2_rsp_data : in std_logic_vector(63 downto 0);
mc2_rsp_rdctl : in std_logic_vector(31 downto 0);
mc2_rsp_flush_cmplt : in std_logic;
-- MC3 port signals
mc3_req_ld : out std_logic;
mc3_req_st : out std_logic;
mc3_req_size : out std_logic_vector(1 downto 0);
mc3_req_vaddr : out std_logic_vector(47 downto 0);
mc3_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc3_req_flush : out std_logic;
mc3_rd_rq_stall : in std_logic;
mc3_wr_rq_stall : in std_logic;
mc3_rsp_push : in std_logic;
mc3_rsp_stall : out std_logic;
mc3_rsp_data : in std_logic_vector(63 downto 0);
mc3_rsp_rdctl : in std_logic_vector(31 downto 0);
mc3_rsp_flush_cmplt : in std_logic;
-- MC4 port signals
mc4_req_ld : out std_logic;
mc4_req_st : out std_logic;
mc4_req_size : out std_logic_vector(1 downto 0);
mc4_req_vaddr : out std_logic_vector(47 downto 0);
mc4_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc4_req_flush : out std_logic;
mc4_rd_rq_stall : in std_logic;
mc4_wr_rq_stall : in std_logic;
mc4_rsp_push : in std_logic;
mc4_rsp_stall : out std_logic;
mc4_rsp_data : in std_logic_vector(63 downto 0);
mc4_rsp_rdctl : in std_logic_vector(31 downto 0);
mc4_rsp_flush_cmplt : in std_logic;
-- MC5 port signals
mc5_req_ld : out std_logic;
mc5_req_st : out std_logic;
mc5_req_size : out std_logic_vector(1 downto 0);
mc5_req_vaddr : out std_logic_vector(47 downto 0);
mc5_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc5_req_flush : out std_logic;
mc5_rd_rq_stall : in std_logic;
mc5_wr_rq_stall : in std_logic;
mc5_rsp_push : in std_logic;
mc5_rsp_stall : out std_logic;
mc5_rsp_data : in std_logic_vector(63 downto 0);
mc5_rsp_rdctl : in std_logic_vector(31 downto 0);
mc5_rsp_flush_cmplt : in std_logic;
-- MC6 port signals
mc6_req_ld : out std_logic;
mc6_req_st : out std_logic;
mc6_req_size : out std_logic_vector(1 downto 0);
mc6_req_vaddr : out std_logic_vector(47 downto 0);
mc6_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc6_req_flush : out std_logic;
mc6_rd_rq_stall : in std_logic;
mc6_wr_rq_stall : in std_logic;
mc6_rsp_push : in std_logic;
mc6_rsp_stall : out std_logic;
mc6_rsp_data : in std_logic_vector(63 downto 0);
mc6_rsp_rdctl : in std_logic_vector(31 downto 0);
mc6_rsp_flush_cmplt : in std_logic;
-- MC7 port signals
mc7_req_ld : out std_logic;
mc7_req_st : out std_logic;
mc7_req_size : out std_logic_vector(1 downto 0);
mc7_req_vaddr : out std_logic_vector(47 downto 0);
mc7_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc7_req_flush : out std_logic;
mc7_rd_rq_stall : in std_logic;
mc7_wr_rq_stall : in std_logic;
mc7_rsp_push : in std_logic;
mc7_rsp_stall : out std_logic;
mc7_rsp_data : in std_logic_vector(63 downto 0);
mc7_rsp_rdctl : in std_logic_vector(31 downto 0);
mc7_rsp_flush_cmplt : in std_logic;
-- MC8 port signals
mc8_req_ld : out std_logic;
mc8_req_st : out std_logic;
mc8_req_size : out std_logic_vector(1 downto 0);
mc8_req_vaddr : out std_logic_vector(47 downto 0);
mc8_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc8_req_flush : out std_logic;
mc8_rd_rq_stall : in std_logic;
mc8_wr_rq_stall : in std_logic;
mc8_rsp_push : in std_logic;
mc8_rsp_stall : out std_logic;
mc8_rsp_data : in std_logic_vector(63 downto 0);
mc8_rsp_rdctl : in std_logic_vector(31 downto 0);
mc8_rsp_flush_cmplt : in std_logic;
-- MC9 port signals
mc9_req_ld : out std_logic;
mc9_req_st : out std_logic;
mc9_req_size : out std_logic_vector(1 downto 0);
mc9_req_vaddr : out std_logic_vector(47 downto 0);
mc9_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc9_req_flush : out std_logic;
mc9_rd_rq_stall : in std_logic;
mc9_wr_rq_stall : in std_logic;
mc9_rsp_push : in std_logic;
mc9_rsp_stall : out std_logic;
mc9_rsp_data : in std_logic_vector(63 downto 0);
mc9_rsp_rdctl : in std_logic_vector(31 downto 0);
mc9_rsp_flush_cmplt : in std_logic;
-- MC10 port signals
mc10_req_ld : out std_logic;
mc10_req_st : out std_logic;
mc10_req_size : out std_logic_vector(1 downto 0);
mc10_req_vaddr : out std_logic_vector(47 downto 0);
mc10_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc10_req_flush : out std_logic;
mc10_rd_rq_stall : in std_logic;
mc10_wr_rq_stall : in std_logic;
mc10_rsp_push : in std_logic;
mc10_rsp_stall : out std_logic;
mc10_rsp_data : in std_logic_vector(63 downto 0);
mc10_rsp_rdctl : in std_logic_vector(31 downto 0);
mc10_rsp_flush_cmplt: in std_logic;
-- MC11 port signals
mc11_req_ld : out std_logic;
mc11_req_st : out std_logic;
mc11_req_size : out std_logic_vector(1 downto 0);
mc11_req_vaddr : out std_logic_vector(47 downto 0);
mc11_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc11_req_flush : out std_logic;
mc11_rd_rq_stall : in std_logic;
mc11_wr_rq_stall : in std_logic;
mc11_rsp_push : in std_logic;
mc11_rsp_stall : out std_logic;
mc11_rsp_data : in std_logic_vector(63 downto 0);
mc11_rsp_rdctl : in std_logic_vector(31 downto 0);
mc11_rsp_flush_cmplt: in std_logic;
-- MC12 port signals
mc12_req_ld : out std_logic;
mc12_req_st : out std_logic;
mc12_req_size : out std_logic_vector(1 downto 0);
mc12_req_vaddr : out std_logic_vector(47 downto 0);
mc12_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc12_req_flush : out std_logic;
mc12_rd_rq_stall : in std_logic;
mc12_wr_rq_stall : in std_logic;
mc12_rsp_push : in std_logic;
mc12_rsp_stall : out std_logic;
mc12_rsp_data : in std_logic_vector(63 downto 0);
mc12_rsp_rdctl : in std_logic_vector(31 downto 0);
mc12_rsp_flush_cmplt: in std_logic;
-- MC13 port signals
mc13_req_ld : out std_logic;
mc13_req_st : out std_logic;
mc13_req_size : out std_logic_vector(1 downto 0);
mc13_req_vaddr : out std_logic_vector(47 downto 0);
mc13_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc13_req_flush : out std_logic;
mc13_rd_rq_stall : in std_logic;
mc13_wr_rq_stall : in std_logic;
mc13_rsp_push : in std_logic;
mc13_rsp_stall : out std_logic;
mc13_rsp_data : in std_logic_vector(63 downto 0);
mc13_rsp_rdctl : in std_logic_vector(31 downto 0);
mc13_rsp_flush_cmplt: in std_logic;
-- MC14 port signals
mc14_req_ld : out std_logic;
mc14_req_st : out std_logic;
mc14_req_size : out std_logic_vector(1 downto 0);
mc14_req_vaddr : out std_logic_vector(47 downto 0);
mc14_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc14_req_flush : out std_logic;
mc14_rd_rq_stall : in std_logic;
mc14_wr_rq_stall : in std_logic;
mc14_rsp_push : in std_logic;
mc14_rsp_stall : out std_logic;
mc14_rsp_data : in std_logic_vector(63 downto 0);
mc14_rsp_rdctl : in std_logic_vector(31 downto 0);
mc14_rsp_flush_cmplt: in std_logic;
-- MC15 port signals
mc15_req_ld : out std_logic;
mc15_req_st : out std_logic;
mc15_req_size : out std_logic_vector(1 downto 0);
mc15_req_vaddr : out std_logic_vector(47 downto 0);
mc15_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc15_req_flush : out std_logic;
mc15_rd_rq_stall : in std_logic;
mc15_wr_rq_stall : in std_logic;
mc15_rsp_push : in std_logic;
mc15_rsp_stall : out std_logic;
mc15_rsp_data : in std_logic_vector(63 downto 0);
mc15_rsp_rdctl : in std_logic_vector(31 downto 0);
mc15_rsp_flush_cmplt: in std_logic
);
end entity;
architecture arch of cygraph is
component cygraph_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
current_level : in unsigned(31 downto 0); -- Current Level
cq_count : in unsigned(31 downto 0); -- Number of nodes to visit in the current level
-- kernels communication signals
kernel_tx_done : out std_logic; -- 0 kernel done, 1 kernel working
kernel_tx_vld : out std_logic;
kernel_tx_count : out unsigned(31 downto 0);
kernel_rx_done : in std_logic; -- 0 previous kernel done, 1 previous kernel working
kernel_rx_vld : in std_logic;
kernel_rx_count : in unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
graphInfo : in std_logic_vector(63 downto 0);
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
nq_address : in std_logic_vector(63 downto 0);
reach_queue : in std_logic_vector(63 downto 0);
-- Parameters for next kernel
nxtk_rst : out std_logic;
nxtk_enable : out std_logic;
nextk_busy : in std_logic;
nxtk_current_lvl : out unsigned(31 downto 0);
nxtk_cq_count : out unsigned(31 downto 0);
nxtk_graphData : out std_logic_vector(63 downto 0);
nxtk_graphInfo : out std_logic_vector(63 downto 0);
nxtk_cq_address : out std_logic_vector(63 downto 0);
nxtk_nq_address : out std_logic_vector(63 downto 0);
nxtk_reach_queue : out std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0);
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic
);
end component;
-- Input signals
signal n : std_logic_vector(63 downto 0); -- Number of nodes in graph
signal non_zeros : std_logic_vector(63 downto 0); -- Number of non-zero edges
signal graphData : std_logic_vector(63 downto 0);
signal graphInfo : std_logic_vector(63 downto 0);
signal queue1_address : std_logic_vector(63 downto 0);
signal queue2_address : std_logic_vector(63 downto 0);
signal reach_queue : std_logic_vector(63 downto 0);
-- Master Process Signals
signal kernels_count : unsigned(7 downto 0) := x"40"; -- 64 kernels
signal current_level : unsigned(31 downto 0);
signal cq_count : unsigned(31 downto 0);
type state is (st_idle, st_start, st_wait, st_busy, st_done);
signal cygraph_state : state;
-- Kernels control signals
signal kernels_enable : std_logic;
signal kernels_busy : std_logic;
signal kernel_done : std_logic_vector(15 downto 0);
signal cq_address : std_logic_vector(63 downto 0);
signal nq_address : std_logic_vector(63 downto 0);
type unsigned32 is array (0 to 15) of unsigned(31 downto 0);
type array_of_slv64 is array (0 to 15) of std_logic_vector(63 downto 0);
signal nxtk_rst : std_logic_vector(15 downto 0);
signal nxtk_enable : std_logic_vector(15 downto 0);
signal nextk_busy : std_logic_vector(15 downto 0);
signal nxtk_current_lvl : unsigned32;
signal nxtk_cq_count : unsigned32;
signal nxtk_graphData : array_of_slv64;
signal nxtk_graphInfo : array_of_slv64;
signal nxtk_cq_address : array_of_slv64;
signal nxtk_nq_address : array_of_slv64;
signal nxtk_reach_queue : array_of_slv64;
-- Kernel-to-kernel communication signals
signal kernel_tx_done : std_logic_vector(15 downto 0);
signal kernel_tx_vld : std_logic_vector(15 downto 0);
signal kernel_tx_count : unsigned32;
signal master_tx_done : std_logic;
signal master_tx_vld : std_logic;
signal master_tx_count : unsigned(31 downto 0);
signal k2k_start : std_logic;
signal k0_rx_vld : std_logic;
signal nxtae_done : std_logic;
signal nxtae_count : std_logic_vector(31 downto 0);
signal done_sent_bw : std_logic;
signal done_sent_fw : std_logic;
begin
-- CyGraph Kernel 0
k0 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => rst,
enable => kernels_enable,
busy => kernels_busy,
done => kernel_done(0),
-- Kernel Parameters
kernel_id => x"00",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => current_level,
cq_count => cq_count,
-- kernels communication signals
kernel_tx_done => kernel_tx_done(0),
kernel_tx_vld => kernel_tx_vld(0),
kernel_tx_count => kernel_tx_count(0),
kernel_rx_done => master_tx_done,
kernel_rx_vld => k0_rx_vld, -- was master_tx_vld
kernel_rx_count => master_tx_count,
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => graphData,
graphInfo => graphInfo,
cq_address => cq_address,
nq_address => nq_address,
reach_queue => reach_queue,
-- Parameters for next kernel
nxtk_rst => nxtk_rst(0),
nxtk_enable => nxtk_enable(0),
nextk_busy => nextk_busy(0),
nxtk_current_lvl => nxtk_current_lvl(0),
nxtk_cq_count => nxtk_cq_count(0),
nxtk_graphData => nxtk_graphData(0),
nxtk_graphInfo => nxtk_graphInfo(0),
nxtk_cq_address => nxtk_cq_address(0),
nxtk_nq_address => nxtk_nq_address(0),
nxtk_reach_queue => nxtk_reach_queue(0),
-- MC0 request port signals
mc_req_ld => mc0_req_ld,
mc_req_st => mc0_req_st,
mc_req_size => mc0_req_size,
mc_req_vaddr => mc0_req_vaddr,
mc_req_wrd_rdctl => mc0_req_wrd_rdctl,
mc_rd_rq_stall => mc0_rd_rq_stall,
mc_wr_rq_stall => mc0_wr_rq_stall,
-- MC0 response port signals
mc_rsp_push => mc0_rsp_push,
mc_rsp_stall => mc0_rsp_stall,
mc_rsp_data => mc0_rsp_data,
mc_rsp_rdctl => mc0_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc0_req_flush,
mc_rsp_flush_cmplt => mc0_rsp_flush_cmplt
);
-- CyGraph Kernel 1
k1 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(0),
enable => nxtk_enable(0),
busy => nextk_busy(0),
done => kernel_done(1),
-- Kernel Parameters
kernel_id => x"01",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(0),
cq_count => nxtk_cq_count(0),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(1),
kernel_tx_vld => kernel_tx_vld(1),
kernel_tx_count => kernel_tx_count(1),
kernel_rx_done => kernel_tx_done(0),
kernel_rx_vld => kernel_tx_vld(0),
kernel_rx_count => kernel_tx_count(0),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(0),
graphInfo => nxtk_graphInfo(0),
cq_address => nxtk_cq_address(0),
nq_address => nxtk_nq_address(0),
reach_queue => nxtk_reach_queue(0),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(1),
nxtk_enable => nxtk_enable(1),
nextk_busy => nextk_busy(1),
nxtk_current_lvl => nxtk_current_lvl(1),
nxtk_cq_count => nxtk_cq_count(1),
nxtk_graphData => nxtk_graphData(1),
nxtk_graphInfo => nxtk_graphInfo(1),
nxtk_cq_address => nxtk_cq_address(1),
nxtk_nq_address => nxtk_nq_address(1),
nxtk_reach_queue => nxtk_reach_queue(1),
-- MC1 request port signals
mc_req_ld => mc1_req_ld,
mc_req_st => mc1_req_st,
mc_req_size => mc1_req_size,
mc_req_vaddr => mc1_req_vaddr,
mc_req_wrd_rdctl => mc1_req_wrd_rdctl,
mc_rd_rq_stall => mc1_rd_rq_stall,
mc_wr_rq_stall => mc1_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc1_rsp_push,
mc_rsp_stall => mc1_rsp_stall,
mc_rsp_data => mc1_rsp_data,
mc_rsp_rdctl => mc1_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc1_req_flush,
mc_rsp_flush_cmplt => mc1_rsp_flush_cmplt
);
-- CyGraph Kernel 2
k2 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(1),
enable => nxtk_enable(1),
busy => nextk_busy(1),
done => kernel_done(2),
-- Kernel Parameters
kernel_id => x"02",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(1),
cq_count => nxtk_cq_count(1),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(2),
kernel_tx_vld => kernel_tx_vld(2),
kernel_tx_count => kernel_tx_count(2),
kernel_rx_done => kernel_tx_done(1),
kernel_rx_vld => kernel_tx_vld(1),
kernel_rx_count => kernel_tx_count(1),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(1),
graphInfo => nxtk_graphInfo(1),
cq_address => nxtk_cq_address(1),
nq_address => nxtk_nq_address(1),
reach_queue => nxtk_reach_queue(1),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(2),
nxtk_enable => nxtk_enable(2),
nextk_busy => nextk_busy(2),
nxtk_current_lvl => nxtk_current_lvl(2),
nxtk_cq_count => nxtk_cq_count(2),
nxtk_graphData => nxtk_graphData(2),
nxtk_graphInfo => nxtk_graphInfo(2),
nxtk_cq_address => nxtk_cq_address(2),
nxtk_nq_address => nxtk_nq_address(2),
nxtk_reach_queue => nxtk_reach_queue(2),
-- MC2 request port signals
mc_req_ld => mc2_req_ld,
mc_req_st => mc2_req_st,
mc_req_size => mc2_req_size,
mc_req_vaddr => mc2_req_vaddr,
mc_req_wrd_rdctl => mc2_req_wrd_rdctl,
mc_rd_rq_stall => mc2_rd_rq_stall,
mc_wr_rq_stall => mc2_wr_rq_stall,
-- MC2 response port signals
mc_rsp_push => mc2_rsp_push,
mc_rsp_stall => mc2_rsp_stall,
mc_rsp_data => mc2_rsp_data,
mc_rsp_rdctl => mc2_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc2_req_flush,
mc_rsp_flush_cmplt => mc2_rsp_flush_cmplt
);
-- CyGraph Kernel 3
k3 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(2),
enable => nxtk_enable(2),
busy => nextk_busy(2),
done => kernel_done(3),
-- Kernel Parameters
kernel_id => x"03",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(2),
cq_count => nxtk_cq_count(2),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(3),
kernel_tx_vld => kernel_tx_vld(3),
kernel_tx_count => kernel_tx_count(3),
kernel_rx_done => kernel_tx_done(2),
kernel_rx_vld => kernel_tx_vld(2),
kernel_rx_count => kernel_tx_count(2),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(2),
graphInfo => nxtk_graphInfo(2),
cq_address => nxtk_cq_address(2),
nq_address => nxtk_nq_address(2),
reach_queue => nxtk_reach_queue(2),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(3),
nxtk_enable => nxtk_enable(3),
nextk_busy => nextk_busy(3),
nxtk_current_lvl => nxtk_current_lvl(3),
nxtk_cq_count => nxtk_cq_count(3),
nxtk_graphData => nxtk_graphData(3),
nxtk_graphInfo => nxtk_graphInfo(3),
nxtk_cq_address => nxtk_cq_address(3),
nxtk_nq_address => nxtk_nq_address(3),
nxtk_reach_queue => nxtk_reach_queue(3),
-- MC3 request port signals
mc_req_ld => mc3_req_ld,
mc_req_st => mc3_req_st,
mc_req_size => mc3_req_size,
mc_req_vaddr => mc3_req_vaddr,
mc_req_wrd_rdctl => mc3_req_wrd_rdctl,
mc_rd_rq_stall => mc3_rd_rq_stall,
mc_wr_rq_stall => mc3_wr_rq_stall,
-- MC3 response port signals
mc_rsp_push => mc3_rsp_push,
mc_rsp_stall => mc3_rsp_stall,
mc_rsp_data => mc3_rsp_data,
mc_rsp_rdctl => mc3_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc3_req_flush,
mc_rsp_flush_cmplt => mc3_rsp_flush_cmplt
);
-- CyGraph Kernel 4
k4 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(3),
enable => nxtk_enable(3),
busy => nextk_busy(3),
done => kernel_done(4),
-- Kernel Parameters
kernel_id => x"04",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(3),
cq_count => nxtk_cq_count(3),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(4),
kernel_tx_vld => kernel_tx_vld(4),
kernel_tx_count => kernel_tx_count(4),
kernel_rx_done => kernel_tx_done(3),
kernel_rx_vld => kernel_tx_vld(3),
kernel_rx_count => kernel_tx_count(3),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(3),
graphInfo => nxtk_graphInfo(3),
cq_address => nxtk_cq_address(3),
nq_address => nxtk_nq_address(3),
reach_queue => nxtk_reach_queue(3),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(4),
nxtk_enable => nxtk_enable(4),
nextk_busy => nextk_busy(4),
nxtk_current_lvl => nxtk_current_lvl(4),
nxtk_cq_count => nxtk_cq_count(4),
nxtk_graphData => nxtk_graphData(4),
nxtk_graphInfo => nxtk_graphInfo(4),
nxtk_cq_address => nxtk_cq_address(4),
nxtk_nq_address => nxtk_nq_address(4),
nxtk_reach_queue => nxtk_reach_queue(4),
-- MC4 request port signals
mc_req_ld => mc4_req_ld,
mc_req_st => mc4_req_st,
mc_req_size => mc4_req_size,
mc_req_vaddr => mc4_req_vaddr,
mc_req_wrd_rdctl => mc4_req_wrd_rdctl,
mc_rd_rq_stall => mc4_rd_rq_stall,
mc_wr_rq_stall => mc4_wr_rq_stall,
-- MC4 response port signals
mc_rsp_push => mc4_rsp_push,
mc_rsp_stall => mc4_rsp_stall,
mc_rsp_data => mc4_rsp_data,
mc_rsp_rdctl => mc4_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc4_req_flush,
mc_rsp_flush_cmplt => mc4_rsp_flush_cmplt
);
-- CyGraph Kernel 5
k5 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(4),
enable => nxtk_enable(4),
busy => nextk_busy(4),
done => kernel_done(5),
-- Kernel Parameters
kernel_id => x"05",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(4),
cq_count => nxtk_cq_count(4),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(5),
kernel_tx_vld => kernel_tx_vld(5),
kernel_tx_count => kernel_tx_count(5),
kernel_rx_done => kernel_tx_done(4),
kernel_rx_vld => kernel_tx_vld(4),
kernel_rx_count => kernel_tx_count(4),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(4),
graphInfo => nxtk_graphInfo(4),
cq_address => nxtk_cq_address(4),
nq_address => nxtk_nq_address(4),
reach_queue => nxtk_reach_queue(4),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(5),
nxtk_enable => nxtk_enable(5),
nextk_busy => nextk_busy(5),
nxtk_current_lvl => nxtk_current_lvl(5),
nxtk_cq_count => nxtk_cq_count(5),
nxtk_graphData => nxtk_graphData(5),
nxtk_graphInfo => nxtk_graphInfo(5),
nxtk_cq_address => nxtk_cq_address(5),
nxtk_nq_address => nxtk_nq_address(5),
nxtk_reach_queue => nxtk_reach_queue(5),
-- MC1 request port signals
mc_req_ld => mc5_req_ld,
mc_req_st => mc5_req_st,
mc_req_size => mc5_req_size,
mc_req_vaddr => mc5_req_vaddr,
mc_req_wrd_rdctl => mc5_req_wrd_rdctl,
mc_rd_rq_stall => mc5_rd_rq_stall,
mc_wr_rq_stall => mc5_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc5_rsp_push,
mc_rsp_stall => mc5_rsp_stall,
mc_rsp_data => mc5_rsp_data,
mc_rsp_rdctl => mc5_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc5_req_flush,
mc_rsp_flush_cmplt => mc5_rsp_flush_cmplt
);
-- CyGraph Kernel 6
k6 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(5),
enable => nxtk_enable(5),
busy => nextk_busy(5),
done => kernel_done(6),
-- Kernel Parameters
kernel_id => x"06",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(5),
cq_count => nxtk_cq_count(5),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(6),
kernel_tx_vld => kernel_tx_vld(6),
kernel_tx_count => kernel_tx_count(6),
kernel_rx_done => kernel_tx_done(5),
kernel_rx_vld => kernel_tx_vld(5),
kernel_rx_count => kernel_tx_count(5),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(5),
graphInfo => nxtk_graphInfo(5),
cq_address => nxtk_cq_address(5),
nq_address => nxtk_nq_address(5),
reach_queue => nxtk_reach_queue(5),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(6),
nxtk_enable => nxtk_enable(6),
nextk_busy => nextk_busy(6),
nxtk_current_lvl => nxtk_current_lvl(6),
nxtk_cq_count => nxtk_cq_count(6),
nxtk_graphData => nxtk_graphData(6),
nxtk_graphInfo => nxtk_graphInfo(6),
nxtk_cq_address => nxtk_cq_address(6),
nxtk_nq_address => nxtk_nq_address(6),
nxtk_reach_queue => nxtk_reach_queue(6),
-- MC6 request port signals
mc_req_ld => mc6_req_ld,
mc_req_st => mc6_req_st,
mc_req_size => mc6_req_size,
mc_req_vaddr => mc6_req_vaddr,
mc_req_wrd_rdctl => mc6_req_wrd_rdctl,
mc_rd_rq_stall => mc6_rd_rq_stall,
mc_wr_rq_stall => mc6_wr_rq_stall,
-- MC6 response port signals
mc_rsp_push => mc6_rsp_push,
mc_rsp_stall => mc6_rsp_stall,
mc_rsp_data => mc6_rsp_data,
mc_rsp_rdctl => mc6_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc6_req_flush,
mc_rsp_flush_cmplt => mc6_rsp_flush_cmplt
);
-- CyGraph Kernel 7
k7 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(6),
enable => nxtk_enable(6),
busy => nextk_busy(6),
done => kernel_done(7),
-- Kernel Parameters
kernel_id => x"07",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(6),
cq_count => nxtk_cq_count(6),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(7),
kernel_tx_vld => kernel_tx_vld(7),
kernel_tx_count => kernel_tx_count(7),
kernel_rx_done => kernel_tx_done(6),
kernel_rx_vld => kernel_tx_vld(6),
kernel_rx_count => kernel_tx_count(6),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(6),
graphInfo => nxtk_graphInfo(6),
cq_address => nxtk_cq_address(6),
nq_address => nxtk_nq_address(6),
reach_queue => nxtk_reach_queue(6),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(7),
nxtk_enable => nxtk_enable(7),
nextk_busy => nextk_busy(7),
nxtk_current_lvl => nxtk_current_lvl(7),
nxtk_cq_count => nxtk_cq_count(7),
nxtk_graphData => nxtk_graphData(7),
nxtk_graphInfo => nxtk_graphInfo(7),
nxtk_cq_address => nxtk_cq_address(7),
nxtk_nq_address => nxtk_nq_address(7),
nxtk_reach_queue => nxtk_reach_queue(7),
-- MC7 request port signals
mc_req_ld => mc7_req_ld,
mc_req_st => mc7_req_st,
mc_req_size => mc7_req_size,
mc_req_vaddr => mc7_req_vaddr,
mc_req_wrd_rdctl => mc7_req_wrd_rdctl,
mc_rd_rq_stall => mc7_rd_rq_stall,
mc_wr_rq_stall => mc7_wr_rq_stall,
-- MC7 response port signals
mc_rsp_push => mc7_rsp_push,
mc_rsp_stall => mc7_rsp_stall,
mc_rsp_data => mc7_rsp_data,
mc_rsp_rdctl => mc7_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc7_req_flush,
mc_rsp_flush_cmplt => mc7_rsp_flush_cmplt
);
-- CyGraph Kernel 8
k8 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(7),
enable => nxtk_enable(7),
busy => nextk_busy(7),
done => kernel_done(8),
-- Kernel Parameters
kernel_id => x"08",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(7),
cq_count => nxtk_cq_count(7),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(8),
kernel_tx_vld => kernel_tx_vld(8),
kernel_tx_count => kernel_tx_count(8),
kernel_rx_done => kernel_tx_done(7),
kernel_rx_vld => kernel_tx_vld(7),
kernel_rx_count => kernel_tx_count(7),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(7),
graphInfo => nxtk_graphInfo(7),
cq_address => nxtk_cq_address(7),
nq_address => nxtk_nq_address(7),
reach_queue => nxtk_reach_queue(7),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(8),
nxtk_enable => nxtk_enable(8),
nextk_busy => nextk_busy(8),
nxtk_current_lvl => nxtk_current_lvl(8),
nxtk_cq_count => nxtk_cq_count(8),
nxtk_graphData => nxtk_graphData(8),
nxtk_graphInfo => nxtk_graphInfo(8),
nxtk_cq_address => nxtk_cq_address(8),
nxtk_nq_address => nxtk_nq_address(8),
nxtk_reach_queue => nxtk_reach_queue(8),
-- MC8 request port signals
mc_req_ld => mc8_req_ld,
mc_req_st => mc8_req_st,
mc_req_size => mc8_req_size,
mc_req_vaddr => mc8_req_vaddr,
mc_req_wrd_rdctl => mc8_req_wrd_rdctl,
mc_rd_rq_stall => mc8_rd_rq_stall,
mc_wr_rq_stall => mc8_wr_rq_stall,
-- MC8 response port signals
mc_rsp_push => mc8_rsp_push,
mc_rsp_stall => mc8_rsp_stall,
mc_rsp_data => mc8_rsp_data,
mc_rsp_rdctl => mc8_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc8_req_flush,
mc_rsp_flush_cmplt => mc8_rsp_flush_cmplt
);
-- CyGraph Kernel 9
k9 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(8),
enable => nxtk_enable(8),
busy => nextk_busy(8),
done => kernel_done(9),
-- Kernel Parameters
kernel_id => x"09",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(8),
cq_count => nxtk_cq_count(8),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(9),
kernel_tx_vld => kernel_tx_vld(9),
kernel_tx_count => kernel_tx_count(9),
kernel_rx_done => kernel_tx_done(8),
kernel_rx_vld => kernel_tx_vld(8),
kernel_rx_count => kernel_tx_count(8),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(8),
graphInfo => nxtk_graphInfo(8),
cq_address => nxtk_cq_address(8),
nq_address => nxtk_nq_address(8),
reach_queue => nxtk_reach_queue(8),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(9),
nxtk_enable => nxtk_enable(9),
nextk_busy => nextk_busy(9),
nxtk_current_lvl => nxtk_current_lvl(9),
nxtk_cq_count => nxtk_cq_count(9),
nxtk_graphData => nxtk_graphData(9),
nxtk_graphInfo => nxtk_graphInfo(9),
nxtk_cq_address => nxtk_cq_address(9),
nxtk_nq_address => nxtk_nq_address(9),
nxtk_reach_queue => nxtk_reach_queue(9),
-- MC9 request port signals
mc_req_ld => mc9_req_ld,
mc_req_st => mc9_req_st,
mc_req_size => mc9_req_size,
mc_req_vaddr => mc9_req_vaddr,
mc_req_wrd_rdctl => mc9_req_wrd_rdctl,
mc_rd_rq_stall => mc9_rd_rq_stall,
mc_wr_rq_stall => mc9_wr_rq_stall,
-- MC9 response port signals
mc_rsp_push => mc9_rsp_push,
mc_rsp_stall => mc9_rsp_stall,
mc_rsp_data => mc9_rsp_data,
mc_rsp_rdctl => mc9_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc9_req_flush,
mc_rsp_flush_cmplt => mc9_rsp_flush_cmplt
);
-- CyGraph Kernel 10
k10 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(9),
enable => nxtk_enable(9),
busy => nextk_busy(9),
done => kernel_done(10),
-- Kernel Parameters
kernel_id => x"0A",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(9),
cq_count => nxtk_cq_count(9),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(10),
kernel_tx_vld => kernel_tx_vld(10),
kernel_tx_count => kernel_tx_count(10),
kernel_rx_done => kernel_tx_done(9),
kernel_rx_vld => kernel_tx_vld(9),
kernel_rx_count => kernel_tx_count(9),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(9),
graphInfo => nxtk_graphInfo(9),
cq_address => nxtk_cq_address(9),
nq_address => nxtk_nq_address(9),
reach_queue => nxtk_reach_queue(9),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(10),
nxtk_enable => nxtk_enable(10),
nextk_busy => nextk_busy(10),
nxtk_current_lvl => nxtk_current_lvl(10),
nxtk_cq_count => nxtk_cq_count(10),
nxtk_graphData => nxtk_graphData(10),
nxtk_graphInfo => nxtk_graphInfo(10),
nxtk_cq_address => nxtk_cq_address(10),
nxtk_nq_address => nxtk_nq_address(10),
nxtk_reach_queue => nxtk_reach_queue(10),
-- MC10 request port signals
mc_req_ld => mc10_req_ld,
mc_req_st => mc10_req_st,
mc_req_size => mc10_req_size,
mc_req_vaddr => mc10_req_vaddr,
mc_req_wrd_rdctl => mc10_req_wrd_rdctl,
mc_rd_rq_stall => mc10_rd_rq_stall,
mc_wr_rq_stall => mc10_wr_rq_stall,
-- MC10 response port signals
mc_rsp_push => mc10_rsp_push,
mc_rsp_stall => mc10_rsp_stall,
mc_rsp_data => mc10_rsp_data,
mc_rsp_rdctl => mc10_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc10_req_flush,
mc_rsp_flush_cmplt => mc10_rsp_flush_cmplt
);
-- CyGraph Kernel 11
k11 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(10),
enable => nxtk_enable(10),
busy => nextk_busy(10),
done => kernel_done(11),
-- Kernel Parameters
kernel_id => x"0B",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(10),
cq_count => nxtk_cq_count(10),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(11),
kernel_tx_vld => kernel_tx_vld(11),
kernel_tx_count => kernel_tx_count(11),
kernel_rx_done => kernel_tx_done(10),
kernel_rx_vld => kernel_tx_vld(10),
kernel_rx_count => kernel_tx_count(10),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(10),
graphInfo => nxtk_graphInfo(10),
cq_address => nxtk_cq_address(10),
nq_address => nxtk_nq_address(10),
reach_queue => nxtk_reach_queue(10),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(11),
nxtk_enable => nxtk_enable(11),
nextk_busy => nextk_busy(11),
nxtk_current_lvl => nxtk_current_lvl(11),
nxtk_cq_count => nxtk_cq_count(11),
nxtk_graphData => nxtk_graphData(11),
nxtk_graphInfo => nxtk_graphInfo(11),
nxtk_cq_address => nxtk_cq_address(11),
nxtk_nq_address => nxtk_nq_address(11),
nxtk_reach_queue => nxtk_reach_queue(11),
-- MC11 request port signals
mc_req_ld => mc11_req_ld,
mc_req_st => mc11_req_st,
mc_req_size => mc11_req_size,
mc_req_vaddr => mc11_req_vaddr,
mc_req_wrd_rdctl => mc11_req_wrd_rdctl,
mc_rd_rq_stall => mc11_rd_rq_stall,
mc_wr_rq_stall => mc11_wr_rq_stall,
-- MC11 response port signals
mc_rsp_push => mc11_rsp_push,
mc_rsp_stall => mc11_rsp_stall,
mc_rsp_data => mc11_rsp_data,
mc_rsp_rdctl => mc11_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc11_req_flush,
mc_rsp_flush_cmplt => mc11_rsp_flush_cmplt
);
-- CyGraph Kernel 12
k12 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(11),
enable => nxtk_enable(11),
busy => nextk_busy(11),
done => kernel_done(12),
-- Kernel Parameters
kernel_id => x"0C",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(11),
cq_count => nxtk_cq_count(11),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(12),
kernel_tx_vld => kernel_tx_vld(12),
kernel_tx_count => kernel_tx_count(12),
kernel_rx_done => kernel_tx_done(11),
kernel_rx_vld => kernel_tx_vld(11),
kernel_rx_count => kernel_tx_count(11),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(11),
graphInfo => nxtk_graphInfo(11),
cq_address => nxtk_cq_address(11),
nq_address => nxtk_nq_address(11),
reach_queue => nxtk_reach_queue(11),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(12),
nxtk_enable => nxtk_enable(12),
nextk_busy => nextk_busy(12),
nxtk_current_lvl => nxtk_current_lvl(12),
nxtk_cq_count => nxtk_cq_count(12),
nxtk_graphData => nxtk_graphData(12),
nxtk_graphInfo => nxtk_graphInfo(12),
nxtk_cq_address => nxtk_cq_address(12),
nxtk_nq_address => nxtk_nq_address(12),
nxtk_reach_queue => nxtk_reach_queue(12),
-- MC12 request port signals
mc_req_ld => mc12_req_ld,
mc_req_st => mc12_req_st,
mc_req_size => mc12_req_size,
mc_req_vaddr => mc12_req_vaddr,
mc_req_wrd_rdctl => mc12_req_wrd_rdctl,
mc_rd_rq_stall => mc12_rd_rq_stall,
mc_wr_rq_stall => mc12_wr_rq_stall,
-- MC12 response port signals
mc_rsp_push => mc12_rsp_push,
mc_rsp_stall => mc12_rsp_stall,
mc_rsp_data => mc12_rsp_data,
mc_rsp_rdctl => mc12_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc12_req_flush,
mc_rsp_flush_cmplt => mc12_rsp_flush_cmplt
);
-- CyGraph Kernel 13
k13 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(12),
enable => nxtk_enable(12),
busy => nextk_busy(12),
done => kernel_done(13),
-- Kernel Parameters
kernel_id => x"0D",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(12),
cq_count => nxtk_cq_count(12),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(13),
kernel_tx_vld => kernel_tx_vld(13),
kernel_tx_count => kernel_tx_count(13),
kernel_rx_done => kernel_tx_done(12),
kernel_rx_vld => kernel_tx_vld(12),
kernel_rx_count => kernel_tx_count(12),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(12),
graphInfo => nxtk_graphInfo(12),
cq_address => nxtk_cq_address(12),
nq_address => nxtk_nq_address(12),
reach_queue => nxtk_reach_queue(12),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(13),
nxtk_enable => nxtk_enable(13),
nextk_busy => nextk_busy(13),
nxtk_current_lvl => nxtk_current_lvl(13),
nxtk_cq_count => nxtk_cq_count(13),
nxtk_graphData => nxtk_graphData(13),
nxtk_graphInfo => nxtk_graphInfo(13),
nxtk_cq_address => nxtk_cq_address(13),
nxtk_nq_address => nxtk_nq_address(13),
nxtk_reach_queue => nxtk_reach_queue(13),
-- MC13 request port signals
mc_req_ld => mc13_req_ld,
mc_req_st => mc13_req_st,
mc_req_size => mc13_req_size,
mc_req_vaddr => mc13_req_vaddr,
mc_req_wrd_rdctl => mc13_req_wrd_rdctl,
mc_rd_rq_stall => mc13_rd_rq_stall,
mc_wr_rq_stall => mc13_wr_rq_stall,
-- MC13 response port signals
mc_rsp_push => mc13_rsp_push,
mc_rsp_stall => mc13_rsp_stall,
mc_rsp_data => mc13_rsp_data,
mc_rsp_rdctl => mc13_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc13_req_flush,
mc_rsp_flush_cmplt => mc13_rsp_flush_cmplt
);
-- CyGraph Kernel 14
k14 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(13),
enable => nxtk_enable(13),
busy => nextk_busy(13),
done => kernel_done(14),
-- Kernel Parameters
kernel_id => x"0E",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(13),
cq_count => nxtk_cq_count(13),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(14),
kernel_tx_vld => kernel_tx_vld(14),
kernel_tx_count => kernel_tx_count(14),
kernel_rx_done => kernel_tx_done(13),
kernel_rx_vld => kernel_tx_vld(13),
kernel_rx_count => kernel_tx_count(13),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(13),
graphInfo => nxtk_graphInfo(13),
cq_address => nxtk_cq_address(13),
nq_address => nxtk_nq_address(13),
reach_queue => nxtk_reach_queue(13),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(14),
nxtk_enable => nxtk_enable(14),
nextk_busy => nextk_busy(14),
nxtk_current_lvl => nxtk_current_lvl(14),
nxtk_cq_count => nxtk_cq_count(14),
nxtk_graphData => nxtk_graphData(14),
nxtk_graphInfo => nxtk_graphInfo(14),
nxtk_cq_address => nxtk_cq_address(14),
nxtk_nq_address => nxtk_nq_address(14),
nxtk_reach_queue => nxtk_reach_queue(14),
-- MC14 request port signals
mc_req_ld => mc14_req_ld,
mc_req_st => mc14_req_st,
mc_req_size => mc14_req_size,
mc_req_vaddr => mc14_req_vaddr,
mc_req_wrd_rdctl => mc14_req_wrd_rdctl,
mc_rd_rq_stall => mc14_rd_rq_stall,
mc_wr_rq_stall => mc14_wr_rq_stall,
-- MC14 response port signals
mc_rsp_push => mc14_rsp_push,
mc_rsp_stall => mc14_rsp_stall,
mc_rsp_data => mc14_rsp_data,
mc_rsp_rdctl => mc14_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc14_req_flush,
mc_rsp_flush_cmplt => mc14_rsp_flush_cmplt
);
-- CyGraph Kernel 15
k15 : cygraph_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(14),
enable => nxtk_enable(14),
busy => nextk_busy(14),
done => kernel_done(15),
-- Kernel Parameters
kernel_id => x"0F",
ae_id => ae_id,
kernels_count => kernels_count,
current_level => nxtk_current_lvl(14),
cq_count => nxtk_cq_count(14),
-- kernels communication signals
kernel_tx_done => kernel_tx_done(15),
kernel_tx_vld => kernel_tx_vld(15),
kernel_tx_count => kernel_tx_count(15),
kernel_rx_done => kernel_tx_done(14),
kernel_rx_vld => kernel_tx_vld(14),
kernel_rx_count => kernel_tx_count(14),
-- Input Graph Pointers (Represented in Custom CSR) and queues pointers
graphData => nxtk_graphData(14),
graphInfo => nxtk_graphInfo(14),
cq_address => nxtk_cq_address(14),
nq_address => nxtk_nq_address(14),
reach_queue => nxtk_reach_queue(14),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(15),
nxtk_enable => nxtk_enable(15),
nextk_busy => nextk_busy(15),
nxtk_current_lvl => nxtk_current_lvl(15),
nxtk_cq_count => nxtk_cq_count(15),
nxtk_graphData => nxtk_graphData(15),
nxtk_graphInfo => nxtk_graphInfo(15),
nxtk_cq_address => nxtk_cq_address(15),
nxtk_nq_address => nxtk_nq_address(15),
nxtk_reach_queue => nxtk_reach_queue(15),
-- MC15 request port signals
mc_req_ld => mc15_req_ld,
mc_req_st => mc15_req_st,
mc_req_size => mc15_req_size,
mc_req_vaddr => mc15_req_vaddr,
mc_req_wrd_rdctl => mc15_req_wrd_rdctl,
mc_rd_rq_stall => mc15_rd_rq_stall,
mc_wr_rq_stall => mc15_wr_rq_stall,
-- MC15 response port signals
mc_rsp_push => mc15_rsp_push,
mc_rsp_stall => mc15_rsp_stall,
mc_rsp_data => mc15_rsp_data,
mc_rsp_rdctl => mc15_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc15_req_flush,
mc_rsp_flush_cmplt => mc15_rsp_flush_cmplt
);
-- master_tx_done <= '1';
-- master_tx_done <= '1' when ae_id = "00" else prvae_rx_data(31) when prvae_rx_vld = '1' else master_tx_done;
-- master_tx_count <= (others => '0') when cygraph_state = st_start and ae_id = "00" else
-- (others => '0') when enable = '1' else
-- ('0' & unsigned(prvae_rx_data(30 downto 0))) when prvae_rx_vld = '1' else master_tx_count;
-- k0_rx_vld <= master_tx_vld when ae_id = "00" else prvae_rx_vld;
nextk_busy(15) <= '0';
prvae_tx_vld <= '0';
prvae_tx_data <= (others => '0');
ae_ae : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
nxtae_done <= '0';
master_tx_done <= '0';
master_tx_count <= (others => '0');
done_sent_bw <= '0';
done_sent_fw <= '0';
nq_count_out <= (others => '0');
k0_rx_vld <= '0';
else
-- Control done_sent_fw
if (cygraph_state = st_start) then
done_sent_fw <= '0';
nq_count_out <= (others => '0');
elsif (prvae_rx_vld = '1' and prvae_rx_data(31) = '1') then
done_sent_fw <= '1';
nq_count_out <= x"00000000" & '0' & std_logic_vector(prvae_rx_data(30 downto 0));
end if;
-- Control nxtae_tx_vld, nxtae_tx_data
if (cygraph_state = st_start or cygraph_state = st_done or cygraph_state = st_idle or (ae_id = "00" and done_sent_fw = '1')) then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
else
nxtae_tx_vld <= kernel_tx_vld(15);
nxtae_tx_data <= kernel_tx_done(15) & std_logic_vector(resize(kernel_tx_count(15), 31));
end if;
-- Control master_tx_count
if (cygraph_state = st_start and ae_id = "00") then
master_tx_count <= (others => '0');
elsif (prvae_rx_vld = '1') then
master_tx_count <= ('0' & unsigned(prvae_rx_data(30 downto 0)));
end if;
-- Control master_tx_done, k0_rx_vld, master_tx_count
if (cygraph_state = st_start) then
master_tx_done <= '0';
k0_rx_vld <= '0';
else
if (ae_id = "00" and done_sent_fw = '1') then
master_tx_done <= '0';
k0_rx_vld <= '0';
elsif (ae_id = "00") then
master_tx_done <= '1';
k0_rx_vld <= master_tx_vld;
elsif (prvae_rx_vld = '1') then
master_tx_done <= prvae_rx_data(31);
k0_rx_vld <= '1';
else
master_tx_done <= master_tx_done;
k0_rx_vld <= '0';
end if;
end if;
-- Control nxtae_done, nxtae_count
if (cygraph_state = st_start) then
nxtae_done <= '0';
nxtae_count <= (others => '0');
else
if (ae_id = "11") then
nxtae_done <= kernel_tx_done(15);
nxtae_count <= std_logic_vector(kernel_tx_count(15));
elsif (nxtae_rx_vld = '1') then
nxtae_done <= '1';
nxtae_count <= nxtae_rx_data;
end if;
end if;
-- -- Control prvae_tx_vld, prvae_tx_data
-- if (cygraph_state = st_start) then
-- prvae_tx_vld <= '0';
-- prvae_tx_data <= (others => '0');
-- done_sent_bw <= '0';
-- elsif (kernel_tx_done(15) = '1' and done_sent_bw = '0' and nxtae_done = '1') then
-- prvae_tx_vld <= '1';
-- prvae_tx_data <= nxtae_count;
-- done_sent_bw <= '1';
-- else
-- prvae_tx_vld <= '0';
-- end if;
end if;
end if;
end process; -- ae_ae
master : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
busy <= '0';
done <= '0';
cygraph_state <= st_idle;
kernels_enable <= '0';
queue1_address <= (others => '0');
queue2_address <= (others => '0');
cq_address <= (others => '0');
nq_address <= (others => '0');
reach_queue <= (others => '0');
-- reset data
n <= (others => '0');
non_zeros <= (others => '0');
graphData <= (others => '0');
graphInfo <= (others => '0');
cq_count <= (others => '0');
current_level <= (others => '0');
else
case (cygraph_state) is
when st_idle =>
done <= '0';
if (enable = '1') then
busy <= '1';
n <= n_in;
non_zeros <= non_zeros_in;
graphData <= graphData_in;
graphInfo <= graphInfo_in;
queue1_address <= queue1_address_in;
queue2_address <= queue2_address_in;
reach_queue <= reach_queue_in;
current_level <= unsigned(current_level_in(31 downto 0));
cq_count <= unsigned(cq_count_in(31 downto 0));
kernels_enable <= '1'; -- set enable early, to allow k2k process in kernel to work
cygraph_state <= st_start;
else
busy <= '0';
kernels_enable <= '0';
cygraph_state <= st_idle;
end if ;
when st_start =>
if (kernels_busy = '0') then
kernels_enable <= '1';
cq_address <= queue1_address;
nq_address <= queue2_address;
cygraph_state <= st_wait;
else
cygraph_state <= st_start;
end if;
when st_wait =>
kernels_enable <= '0';
cygraph_state <= st_busy;
-- Wait ffor a level to be done
when st_busy =>
-- if (prvae_rx_vld = '1') then
-- nq_count_out <= x"00000000" & '0' & std_logic_vector(prvae_rx_data(30 downto 0));
-- end if;
if (kernels_busy = '0' and kernel_tx_done(15) = '1' and (ae_id /= "00" or (ae_id = "00" and done_sent_fw = '1'))) then
-- if (kernels_busy = '0' and kernel_tx_done = x"FFFF" and (ae_id /= "00" or (ae_id = "00" and done_sent_fw = '1'))) then
-- level is done
cygraph_state <= st_done;
else
cygraph_state <= st_busy;
end if;
-- Cygraph is done
when st_done =>
done <= '1';
busy <= '0';
cygraph_state <= st_idle;
when others =>
cygraph_state <= st_idle;
end case;
end if; -- end if rst
end if; -- end if clk
end process; -- master
-- Kernel-to-kenrel process
--- Start and control the kernel_tx_vld signals
k2k : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If kernel idle, reset signals
if (cygraph_state = st_start) then
-- if (cygraph_state = st_idle) then
k2k_start <= '0';
master_tx_vld <= '0';
-- elsif (cygraph_state = st_busy) then
else
-- If the start of the level, issue a vld signal
if (k2k_start = '0') then
master_tx_vld <= '1';
k2k_start <= '1';
else
-- if valid signal, pass it to next kernel in the ring
-- if (kernel_tx_vld(15) = '1') then
if (prvae_rx_vld = '1') then
master_tx_vld <= '1';
else
master_tx_vld <= '0';
end if;
end if;
-- else
-- k2k_start <= '0';
-- master_tx_vld <= '0';
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
end architecture; | apache-2.0 | 97a48d831908e0890afd644478b5377e | 0.622948 | 2.376416 | false | false | false | false |
willtmwu/vhdlExamples | Project/SPI_hw_interface.vhd | 1 | 11,499 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_hardware_interface.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: This module handles the CS for SPI_NRF
-- CS - Low active
-- CPOL = 0 (CPOL_LOW)
-- CPHA = 0 (CPHA_1Edge)
-- MSB Transfer
--
-- Burst mode reads and writes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_hw_interface is
Generic (
master_clk : integer := 100_000_000; -- Default 100Mhz clk
SCLK_rate : integer := 1_000_000 -- Default 1Mhz SCLK
);
Port ( clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
en : in STD_LOGIC; -- EN to latch in/out the data, must remain active for whole duration
data_byte_in : in STD_LOGIC_VECTOR(7 downto 0); -- Read in byte by byte to internal buffer before sending, always 32 bytes for msg must be given. If no data at least 0x00
data_byte_out : out STD_LOGIC_VECTOR(7 downto 0); -- Write the full message bytes back out to SPI controller.
wen : in STD_LOGIC; -- HIGH for 1 clk to send all within send buffer
ren : in STD_LOGIC; -- HIGH for 1 clk to start read process, before returning to idle
M_active : out STD_LOGIC; -- HIGH when active in either send or receive mode
M_finished : out STD_LOGIC; -- HIGH for 1 clk when finished
regLocation : in STD_LOGIC_VECTOR(7 downto 0); -- Location to write/read to, must include CMD bit
dataAmount : in STD_LOGIC_VECTOR(5 downto 0); -- Amount to write or read, to/form, 32 bytes max
-- NRF Chip control lines, CE pulses and transitions done by controller
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC
);
end SPI_hw_interface;
architecture Behavioral of SPI_hw_interface is
-- clkScalers for different SCLK if required
signal clockScalers : std_logic_vector(26 downto 0) := (others => '0');
signal forceReset : std_logic := '0';
-- For data loading/unloading
type DATA_FSM is (DATA_IDLE, DATA_LOAD);
signal DATA_STATE : DATA_FSM := DATA_IDLE;
signal counter : integer range 31 downto 0 := 0;
subtype byte is std_logic_vector(7 downto 0);
type message is array(31 downto 0) of byte; -- Maximum of 32 byte message
signal send_buffer : message := (others => (others => '0'));
signal recv_buffer : message := (others => (others => '0'));
-- For general dynamic sending
type SPI_FSM is (SPI_IDLE, SPI_REG, SPI_DATA_SEND, SPI_DATA_RECV);
signal SPI_STATE : SPI_FSM := SPI_IDLE;
signal data_shifter : std_logic_vector(7 downto 0) := (others => '0'); -- Byte to shift out
signal reg_location_I: std_logic_vector(7 downto 0) := (others => '0'); -- Byte given by controller
signal data_amount_I : integer range 32 downto 0 := 0; -- Amount given by controller, max 32 bytes
signal data_counter_I: integer range 33 downto 0 := 0; -- Counting bytes sent or received
signal bit_shifter : std_logic_vector(7 downto 0) := (others => '1'); -- Tracking bits shifted out
signal toRead : std_logic := '0'; -- toRead or write to the NRF.
signal toWrite : std_logic := '0';
signal CS_I : std_logic := '1'; -- Internal CS [CSN] link to outside
-- Scaling SCLK time signal and period
signal SCLK_I : std_logic := '0'; -- Internal link
signal SCLK_h : std_logic := '0'; -- Half SCLK synchro signal
signal SCLK_f : std_logic := '0'; -- Full SCLK period synchro signal
constant SCLK_limit : integer := master_CLK/SCLK_rate - 2; -- For counter, -2 to fix timing issues
constant SCLK_half : integer := master_CLK/SCLK_rate/2 - 2; -- For counter, half the SCLK Period
signal SCLK_counter : integer range SCLK_limit downto 0 := 0; -- SCLK Period counter
type SCLK_FSM is (SCLK_IDLE, SCLK_WAIT); -- Scaler Process FSM
signal SCLK_STATE_H : SCLK_FSM := SCLK_IDLE;
signal SCLK_STATE_F : SCLK_FSM := SCLK_IDLE;
begin
-- Direct signal connections
CS <= CS_I;
SCLK <= SCLK_I;
-- always start with reg location, then write or read specified amount. Manually bit-bash SCLK
process (masterReset, clk) begin
if (masterReset = '1') then
SPI_STATE <= SPI_IDLE;
MOSI <= '0';
SCLK_I <= '0';
M_active <= '0';
M_finished <= '0';
-- recv_buffer <= (others => (others => '0'));
elsif rising_edge(clk) then
case SPI_STATE is
when SPI_IDLE =>
if (wen = '1' or ren = '1') then
SPI_STATE <= SPI_REG;
toRead <= ren; -- Temporary, will need to reset after the reg location transition state
toWrite <= wen;
M_active <= '1'; -- Signal to outside
-- Load in the data
reg_location_I <= regLocation(6 downto 0) & '0'; -- Sending out the MSB already
data_amount_I <= to_Integer(unsigned(dataAmount));
data_counter_I <= 0;
CS_I <= '0';
forceReset <= '1';
-- Begin data shift out
MOSI <= regLocation(7); -- MSB Shifting
bit_shifter <= bit_shifter(6 downto 0) & '0';
else
SPI_STATE <= SPI_IDLE;
M_active <= '0';
data_amount_I <= 0;
forceReset <= '0';
bit_shifter <= (others => '1');
CS_I <= '1';
SCLK_I <= '0';
MOSI <= '0';
M_finished <= '0';
end if;
when SPI_REG =>
forceReset <= '0';
if (SCLK_H = '1') then
SCLK_I <= '1'; -- half delay, middle of BIT shifting. Pull SCLK high
elsif (SCLK_F = '1') then
SCLK_I <= '0'; -- Transition bit now
if( bit_shifter = "10000000") then --
bit_shifter <= (others => '1');
MOSI <= reg_location_I(7); -- Last Bit to send off
if(toWrite = '1')then
SPI_STATE <= SPI_DATA_SEND;
data_shifter <= send_buffer(0);
data_counter_I <= 1;
elsif (toRead = '1') then
SPI_STATE <= SPI_DATA_RECV;
data_counter_I <= 0;
end if;
-- toRead <= '0'; needed to force 1 SCLK delay
toWrite <= '0';
else
MOSI <= reg_location_I(7);
reg_location_I <= reg_location_I(6 downto 0) & '0';
bit_shifter <= bit_shifter(6 downto 0) & '0';
end if;
end if;
when SPI_DATA_SEND =>
if (SCLK_H = '1') then
if ( (data_counter_I = data_amount_I+1) and (bit_shifter = "11111110") ) then -- This is for the half delayed CS/CE
SPI_STATE <= SPI_IDLE;
M_active <= '0';
M_finished <= '1';
data_counter_I <= 0;
CS_I <= '1';
SCLK_I <= '0';
else
SCLK_I <= '1'; -- half delay
end if;
elsif (SCLK_F = '1') then
SCLK_I <= '0';
if ( bit_shifter = "10000000" ) then
-- clk in new byte, increment counter
MOSI <= data_shifter(7);
bit_shifter <= (others => '1');
if (data_counter_I <= 31) then
data_shifter <= send_buffer(data_counter_I);
end if;
data_counter_I <= data_counter_I + 1;
else
MOSI <= data_shifter(7);
data_shifter <= data_shifter(6 downto 0) & '0';
bit_shifter <= bit_shifter(6 downto 0) & '0';
end if;
end if;
when SPI_DATA_RECV =>
if (SCLK_H = '1') then
if (data_counter_I = data_amount_I) then
SPI_STATE <= SPI_IDLE;
M_active <= '0';
M_finished <= '1';
CS_I <= '1';
data_counter_I <= 0;
SCLK_I <= '0';
else
SCLK_I <= '1'; -- half delay
end if;
elsif (SCLK_F = '1') then
SCLK_I <= '0'; -- full delay
MOSI <= '1'; -- Change back to 1 when final NRF Link
if (toRead = '1') then
toRead <= '0';
bit_shifter <= (others => '1');
elsif ( bit_shifter = "00000000" ) then
-- clk in new byte, increment counter
recv_buffer(data_counter_I) <= data_shifter;
data_counter_I <= data_counter_I + 1;
bit_shifter <= "11111110";
else
bit_shifter <= bit_shifter(6 downto 0) & '0';
end if;
data_shifter(0) <= MISO; -- Always shifting in new data
data_shifter(7 downto 1) <= data_shifter(6 downto 0);
end if;
end case;
end if;
end process;
-- Scaling Process in all modules, able to obtain whichever scale module needs
process (clk, masterReset) begin
if (masterReset = '1') then
clockScalers <= (others => '0'); -- Asynchro Reset
elsif rising_edge(clk) then
if(forceReset = '1') then
clockScalers <= (others => '0'); -- Synchro Reset
else
clockScalers <= clockScalers + '1';
end if;
end if;
end process;
-- Load in the data, must remain in enable till all required data is loaded in. If no data, 0x00 should be clked in.
-- Cap at BUFF_MAX to prevent issues
process (clk, masterReset) begin
if (masterReset = '1') then
DATA_STATE <= DATA_IDLE;
counter <= 0;
-- send_buffer <= (others => (others => '0'));
data_byte_out <= (others => '0');
elsif rising_edge(clk) then
case DATA_STATE is
when DATA_IDLE =>
if(en = '1') then
DATA_STATE <= DATA_LOAD;
if (counter <= 31) then
send_buffer(counter) <= data_byte_in;
data_byte_out <= recv_buffer(counter);
else
data_byte_out <= (others => '0');
end if;
counter <= counter + 1;
else
DATA_STATE <= DATA_IDLE;
data_byte_out <= (others => '0');
end if;
when DATA_LOAD =>
if (en = '0') then
DATA_STATE <= DATA_IDLE;
counter <= 0;
else
if (counter <= 31) then
send_buffer(counter) <= data_byte_in;
data_byte_out <= recv_buffer(counter);
else
data_byte_out <= (others => '0');
end if;
counter <= counter + 1;
end if;
end case;
end if;
end process;
-- Different type of scaling process, 1 clk HIGH type scaling. Tested SCLK is OK
-- ___-___-___-___
-- FSM SCALE
-- SCLK scale
process (clk, masterReset) begin
if (masterReset = '1') then
SCLK_STATE_F <= SCLK_IDLE;
SCLK_F <= '0';
SCLK_counter <= 0;
elsif rising_edge(clk) then
if (forceReset = '1') then
SCLK_STATE_F <= SCLK_IDLE;
SCLK_F <= '0';
SCLK_counter <= 1;
else
case SCLK_STATE_F is
when SCLK_IDLE =>
if (SCLK_counter = SCLK_limit) then
SCLK_STATE_F <= SCLK_WAIT;
SCLK_F <= '1';
else
SCLK_STATE_F <= SCLK_IDLE;
SCLK_F <= '0';
SCLK_counter <= SCLK_counter + 1;
end if;
when SCLK_WAIT =>
SCLK_F <= '0';
SCLK_STATE_F <= SCLK_IDLE;
SCLK_counter <= 0;
end case;
end if;
end if;
end process;
--SCLK 0.5 Scale
process (clk, masterReset) begin
if (masterReset='1') then
SCLK_STATE_H <= SCLK_IDLE;
SCLK_H <= '0';
elsif rising_edge(clk) then
if (forceReset = '1') then
SCLK_STATE_H <= SCLK_IDLE;
SCLK_H <= '0';
else
case SCLK_STATE_H is
when SCLK_IDLE =>
if (SCLK_counter = SCLK_half) then
SCLK_STATE_H <= SCLK_WAIT;
SCLK_H <= '1';
else
SCLK_STATE_H <= SCLK_IDLE;
SCLK_H <= '0';
end if;
when SCLK_WAIT =>
SCLK_H <= '0';
SCLK_STATE_H <= SCLK_IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 29c1a912ca600ba245e24cb83164a0cd | 0.563962 | 3.096957 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_7/vhdl/cpu_engine.vhd | 1 | 12,526 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
else T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
end if;
end process;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_IMM <= X"FFFF";
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode... PORTATO FUORI
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end process;
end Behavioral;
| mit | ab18b43d30bad8e444f0c89304e3a66a | 0.551653 | 2.450313 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/harware_interface.vhd | 1 | 4,281 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p: out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component bcd_counter port (
rst : in std_logic;
en : in std_logic;
bcd_out : out std_logic_vector(7 downto 0);
clk : in std_logic
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
--Clock scaled signals
signal clk2Hz : std_logic := '0';
--Component Signals
signal en1 : std_logic := '0';
signal en2 : std_logic := '0';
--System Signals
TYPE timer_state_fsm IS (start, stop1, stop2);
signal timer_state : timer_state_fsm := stop2;
begin
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
k1 : bcd_counter port map (masterReset, en1, displayUpper(7 downto 0), clk2Hz);
k2 : bcd_counter port map (masterReset, en2, displayLower(7 downto 0), clk2Hz);
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
--clk2Hz <= clockScalers(26);
-- 3 of 24
process (clockScalers(23), masterReset )
variable count_scaler : std_logic_vector(2 downto 0) := (others => '0');
begin
if (masterReset = '1') then
count_scaler := (others => '0');
elsif (clockScalers(23)'event and clockScalers(23) = '1') then
count_scaler := count_scaler + '1';
if (count_scaler = 3) then
clk2Hz <= not(clk2Hz);
count_scaler := (others => '0');
end if;
end if;
end process;
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
--en1 <= '1' when (timer_state = start) else '0'
process (masterReset, buttonDown) begin
if (masterReset = '1') then
timer_state <= stop2;
en1 <= '0';
en2 <= '0';
elsif (buttonDown'event and buttonDown = '1') then
case timer_state is
when stop2 =>
en1 <= '1';
en2 <= '1';
timer_state <= start;
when start =>
en1 <= '0';
timer_state <= stop1;
when stop1 =>
en2 <= '0';
timer_state <= stop2;
end case;
end if;
end process;
end Behavioral; | apache-2.0 | af77b14674bdad92079e27bb953b4ee7 | 0.623452 | 3.060043 | false | false | false | false |
zambreno/RCL | FPGA_PUF/v1/puf_sram.vhd | 1 | 1,834 | ----------------------------------------------------------------------------------
-- Company: Iowa State University
-- Engineer: Aaron Mills
--
-- Create Date: 19:44:42 09/21/2011
-- Design Name:
-- Module Name: puf_sram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: a2b3 LUT configuration
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity puf_sram is
port(
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
Q1: out std_logic;
Q2: out std_logic
);
end puf_sram;
architecture Behavioral of puf_sram is
signal i1: std_logic;
signal i2: std_logic;
signal rstin: std_logic;
attribute keep: boolean;
attribute lock_pins: string;
attribute lock_pins of tri1 : label is "all";
attribute lock_pins of tri2 : label is "all";
begin
----A2B3
tri1 : LUT4_D
generic map (
INIT => X"ff33")
port map (
--LO => i2, -- LUT local output
O => i2, -- LUT general output
I0 => '0', -- LUT input
I1 => i1 , -- LUT input
I2 => '0', -- LUT input
I3 => rstin -- LUT input
);
tri2 : LUT4_D
generic map (
INIT => X"ff0f")
port map (
--LO => i1, -- LUT local output
O => i1, -- LUT general output
I0 => '0', -- LUT input
I1 => '0', -- LUT input
I2 => i2, -- LUT input
I3 => rstin -- LUT input
);
RST_DFF : FDCE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => rstin, -- Data output
C => clk, -- Clock input
CE => en, -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => rst -- Data input
);
Q1<=i1;
Q2<=i2;
end Behavioral;
| apache-2.0 | eefe49276a99bffd305881fc716866a9 | 0.548528 | 2.948553 | false | false | false | false |
willtmwu/vhdlExamples | Basic Event Logic/prac_synchro.vhd | 1 | 5,930 | ----------------------------------------------------------------------------------
-- Company: University of Queensland
-- Engineer: MDS
--
-- Create Date: 25/07/2014
-- Design Name:
-- Module Name: pracTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity prac_synchro is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end prac_synchro;
architecture Behavioral of prac_synchro is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component clockedRegister port (
D : in STD_LOGIC_VECTOR (15 downto 0);
E : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal currentState : std_logic_vector(2 downto 0);
signal openLock : std_logic := '0';
signal closeLock : std_logic := '0';
signal correctAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal incorrectAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal displayKey : std_logic_vector(15 downto 0);
signal upperKey : std_logic_vector(7 downto 0);
signal lowerKey : std_logic_vector(7 downto 0);
signal checkKey : std_logic_vector(15 downto 0);
signal regEnable : std_logic;
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : clockedRegister port map (
D (7 downto 0) => lowerKey,
D (15 downto 8) => upperKey,
E => regEnable,
clk => clockScalers(11),
reset => masterReset,
Q => checkKey
);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
logic_analyzer <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
regEnable <= '1';
process (button1, button2, submitButton, clk100mhz, masterReset) begin
if (masterReset = '1') then
openLock <= '0';
closeLock <= '0';
lowerKey <= (others => '0');
upperKey <= (others => '0');
displayKey <= (others => '0');
elsif (clk100mhz'event and clk100mhz = '1')then
if( slideSwitches(7 downto 0) /= "00000110"
and slideSwitches(7 downto 0) /= "00110011") then
openLock <= '0';
end if;
if (button1 = '1') then
openLock <= '0';
closeLock <= '0';
lowerKey <= displayKey(7 downto 0);
displayKey(7 downto 0) <= slideSwitches(7 downto 0);
elsif (button2 = '1') then
openLock <= '0';
closeLock <= '0';
upperKey <= displayKey(15 downto 8);
displayKey (15 downto 8) <= slideSwitches(7 downto 0);
elsif (submitButton = '1') then
if (lowerKey = "00000110" and upperKey = "00110011") then
openLock <= '1';
else
closeLock <= '1';
end if;
end if;
end if;
end process;
process (openLock , clockScalers) begin
LEDs (15 downto 2) <= clockScalers(26 downto 13);
if(openLock = '1') then
LEDs(0) <= '0';
LEDs(1) <= '1';
else
LEDs(0) <= '1';
LEDs(1) <= '0';
end if;
end process;
digit6 <= incorrectAttempts(7 downto 4);
digit5 <= incorrectAttempts(3 downto 0);
digit8 <= correctAttempts(7 downto 4);
digit7 <= correctAttempts(3 downto 0);
process (masterReset, openlock) begin
if (masterReset = '1') then
correctAttempts <= (others => '0');
elsif (openLock'event and openLock = '1' ) then
correctAttempts <= correctAttempts + '1';
end if;
end process;
process (masterReset, closelock) begin
if (masterReset = '1') then
incorrectAttempts <= (others => '0');
elsif (closeLock'event and closeLock = '1' ) then
incorrectAttempts <= incorrectAttempts + '1';
end if;
end process;
end Behavioral;
| apache-2.0 | 0e8655a2efc196a0d3b7e7b10aadcec8 | 0.612479 | 3.135907 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc_master.vhd | 1 | 24,477 | -- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_kernel - Behavioral
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- search : in std_logic;
done : out std_logic;
-- Input Graph Pointers (Represented in Custom CSR)
graph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
p1_rsp_q_wr_en : out std_logic;
p1_rsp_q_din : out std_logic_vector(63 downto 0);
p1_rsp_q_almost_full : in std_logic;
-- Process 2 signals
p2_scc_req_rd_enb : out std_logic;
p2_scc_req_dout : in std_logic_vector(63 downto 0);
p2_scc_req_valid : in std_logic;
p2_scc_req_empty : in std_logic;
p2_scc_req_almost_full : in std_logic;
p2_rinfo_req_rd_enb : out std_logic;
p2_rinfo_req_dout : in std_logic_vector(63 downto 0);
p2_rinfo_req_valid : in std_logic;
p2_rinfo_req_empty : in std_logic;
p2_rinfo_req_almost_full : in std_logic;
p2_scc_rsp_wr_en : out std_logic;
p2_scc_rsp_din : out std_logic_vector(0 downto 0);
p2_scc_rsp_almost_full : in std_logic;
p2_rinfo_rsp_wr_en : out std_logic;
p2_rinfo_rsp_din : out std_logic_vector(0 downto 0);
p2_rinfo_rsp_almost_full : in std_logic;
-- Process 3 signals
p3_done : in std_logic;
p3_scc_addr_rd_enb : out std_logic;
p3_scc_addr_dout : in std_logic_vector(63 downto 0);
p3_scc_addr_valid : in std_logic;
p3_scc_addr_empty : in std_logic;
p3_info_req_rd_enb : out std_logic;
p3_info_req_dout : in std_logic_vector(63 downto 0);
p3_info_req_valid : in std_logic;
p3_info_req_empty : in std_logic;
p3_id_q_rd_enb : out std_logic;
p3_id_q_dout : in std_logic_vector(63 downto 0);
p3_id_q_valid : in std_logic;
p3_id_q_empty : in std_logic;
p3_info_rsp_rd_enb : out std_logic;
p3_info_rsp_dout : in std_logic_vector(63 downto 0);
p3_info_rsp_valid : in std_logic;
p3_info_rsp_empty : in std_logic;
p3_info_rsp_wr_en : out std_logic;
p3_info_rsp_din : out std_logic_vector(63 downto 0);
p3_info_rsp_almost_full : in std_logic;
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end scc_master;
architecture Behavioral of scc_master is
type muxstatetype is (mx_start, mx_stall, mx_p1, mx_p2, mx_p3, mx_p4, mx_p5, mx_p6);
signal mux_state : muxstatetype;
signal done_count : integer range 0 to 3;
signal saved_state : std_logic_vector(7 downto 0);
signal saved_addr : std_logic_vector(63 downto 0);
signal saved_data : std_logic_vector(63 downto 0);
signal count : unsigned (63 downto 0);
signal p2_q_alt : std_logic;
signal p2_scc_rsp_wr_en_temp : std_logic;
signal p2_scc_rsp_din_temp : std_logic_vector(63 downto 0);
signal p2_rinfo_rsp_wr_en_temp : std_logic;
signal p2_rinfo_rsp_din_temp : std_logic_vector(63 downto 0);
begin
-- Requests Multiplexer
-- Read from the processes' request queues with the specific tag
Master : process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
done <= '0';
done_count <= 0;
-- reset master process control signals
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '0';
else
--- MULTIPLEX requests to memory controller
if (enable = '1') then
-- is memory controller asserting rd/wr stall?
if (mc_rd_rq_stall = '1' or mc_wr_rq_stall = '1') then
-- save addr/data
if (p1_req_q_valid = '1') then
-- Read from reach queue at this address
saved_state <= x"01";
saved_addr <= p1_req_q_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_scc_req_valid = '1') then
-- Read from SCC color value at this address
saved_state <= x"02";
saved_addr <= p2_scc_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p2_rinfo_req_valid = '1') then
-- Read rInfo (in CSR)
saved_state <= x"03";
saved_addr <= p2_rinfo_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_scc_addr_valid = '1') then
-- Color node
saved_state <= x"04";
saved_addr <= p3_scc_addr_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_info_req_valid = '1') then
-- Read Info (in CSR)
saved_state <= x"05";
saved_addr <= p3_info_req_dout;
saved_data <= (others => '0');
mux_state <= mx_stall;
elsif (p3_id_q_valid = '1' and p3_info_rsp_valid = '1') then
-- Update Info CSR
saved_state <= x"06";
saved_addr <= p3_id_q_dout;
saved_data <= p3_info_rsp_dout;
mux_state <= mx_stall;
else
saved_state <= saved_state;
saved_addr <= saved_addr;
saved_data <= saved_data;
mux_state <= mux_state;
end if;
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
-- If not a memory controller rd/wr stall
elsif (mc_rd_rq_stall = '0' and mc_wr_rq_stall = '0') then
if (mux_state = mx_stall) then
-- Issue a request, if comming from a stall
if (saved_state = x"01") then
-- Request from reach queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"02") then
-- Request SCC[id] Color
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"03") then
-- Request rInfo[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"04") then
-- Color node at SCC[id]
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl <= color;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"05") then
-- Read Info[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl(7 downto 0) <= saved_state;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (saved_state = x"06") then
-- Update Info[id] in (CSR)
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= saved_addr(47 downto 0);
mc_req_wrd_rdctl <= saved_data(63 downto 1) & '0';
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if;
elsif (mux_state = mx_p1 and p1_req_q_valid = '1') then
-- Request from reach queue
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p1_req_q_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"01";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p2 and p2_scc_req_valid = '1') then
-- Request SCC[id] Color
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p2_scc_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"02";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p3 and p2_rinfo_req_valid = '1') then
-- Request rInfo[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p2_rinfo_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"03";
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p4 and p3_scc_addr_valid = '1') then
-- Color node at SCC[id]
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= p3_scc_addr_dout(47 downto 0);
mc_req_wrd_rdctl <= color;
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p5 and p3_info_req_valid = '1') then
-- Read Info[id] (CSR of 64-bit)
mc_req_ld <= '1';
mc_req_st <= '0';
mc_req_size <= "11";
mc_req_vaddr <= p3_info_req_dout(47 downto 0);
mc_req_wrd_rdctl (7 downto 0) <= x"05";
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
elsif (mux_state = mx_p6 and p3_id_q_valid = '1' and p3_info_rsp_valid = '1') then
-- Update Info[id] in (CSR) to be unvisited
mc_req_ld <= '0';
mc_req_st <= '1';
mc_req_size <= "11";
mc_req_vaddr <= p3_id_q_dout(47 downto 0);
mc_req_wrd_rdctl <= p3_info_rsp_dout(63 downto 1) & '0';
-- Save information for next write request
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
else
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset saved state
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
end if; -- End mux states execution
-- Pop from queue if mux is ready
if ((mux_state = mx_start) or (mux_state = mx_stall)
or (mux_state = mx_p1 and p1_req_q_valid = '1')
or (mux_state = mx_p2 and p2_scc_req_valid = '1')
or (mux_state = mx_p3 and p2_rinfo_req_valid = '1')
or (mux_state = mx_p4 and p3_scc_addr_valid = '1')
or (mux_state = mx_p5 and p3_info_req_valid = '1')
or (mux_state = mx_p6 and p3_id_q_valid = '1' and p3_info_rsp_valid = '1')) then
if (p3_id_q_empty = '0' and p3_info_rsp_empty = '0') then
-- If process 3 info/addr queues are not empty, make a write request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '1';
p3_info_rsp_rd_enb <= '1';
mux_state <= mx_p6;
elsif (p3_scc_addr_empty = '0') then
-- If process 3 SCC queue isn't empty, make a write request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '1';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p4;
elsif (p3_info_req_empty = '0') then
-- If process 3 info req queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '1';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p5;
elsif (p2_rinfo_req_empty = '0' and p2_q_alt = '0') then
-- If process 2 rInfo queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '1';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '1'; -- Next time read from SCC queue
mux_state <= mx_p3;
elsif (p2_scc_req_empty = '0' and p2_q_alt = '1') then
-- If process 2 SCC queue isn't empty, make a read request
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '1';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
p2_q_alt <= '0'; -- Next time read from rInfo queue
mux_state <= mx_p2;
elsif (p1_req_q_empty = '0') then
-- If process 1 queue isn't empty, make a read request
p1_req_q_rd_enb <= '1';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_p1;
else
-- reset
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
mux_state <= mx_start;
end if;
else
-- Keep mux state
mux_state <= mux_state;
-- reset enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end if mux green light!
else
-- weird case, memory controller not ready yet
mux_state <= mux_state;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end check for rd/wr stall
-- if all processes are done and queues ar eempty go done
if (p3_done = '1' and p3_id_q_empty = '1' and p3_info_rsp_empty = '1' and p3_info_req_empty = '1' and p3_scc_addr_empty = '1'
and p2_rinfo_req_empty = '1' and p2_scc_req_empty = '1' and p1_req_q_empty = '1') then
if (done_count < 3) then
done <= '0';
done_count <= done_count + 1;
elsif (done_count = 3) then
done <= '1';
done_count <= 0;
end if;
else
done <= '0';
done_count <= 0;
end if;
else
done <= '0';
done_count <= 0;
-- reset master process control signals
mux_state <= mx_start;
saved_state <= x"00";
saved_addr <= (others => '0');
saved_data <= (others => '0');
-- reset memory controller signals
mc_req_ld <= '0';
mc_req_st <= '0';
mc_req_size <= (others => '0');
mc_req_vaddr <= (others => '0');
mc_req_wrd_rdctl <= (others => '0');
-- reset queues read enable signals
p1_req_q_rd_enb <= '0';
p2_scc_req_rd_enb <= '0';
p2_rinfo_req_rd_enb <= '0';
p3_scc_addr_rd_enb <= '0';
p3_info_req_rd_enb <= '0';
p3_id_q_rd_enb <= '0';
p3_info_rsp_rd_enb <= '0';
end if; -- end if enable
end if; -- end if rst
end if; -- end if clk
end process; -- Master
-- MC Response decoder process
mc_rsp_decoder : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p2_scc_rsp_wr_en <= '0';
p2_scc_rsp_din <= (others => '0');
p2_rinfo_rsp_wr_en <= '0';
p2_rinfo_rsp_din <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
mc_rsp_stall <= '0';
else
if (enable = '1') then
if (mc_rsp_push = '1') then
-- Get process 1 response
if (mc_rsp_rdctl(7 downto 0) = x"01") then
-- push results to p1 response queue
p1_rsp_q_wr_en <= '1';
p1_rsp_q_din <= mc_rsp_data;
-- reset others
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 2 SCC[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"02") then
-- push results to p2 SCC response queue
p2_scc_rsp_wr_en_temp <= '1';
p2_scc_rsp_din_temp <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 2 rInfo[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"03") then
-- push results to p2 rInfo response queue
p2_rinfo_rsp_wr_en_temp <= '1';
p2_rinfo_rsp_din_temp <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
-- Get process 3 Info[id] response
elsif (mc_rsp_rdctl(7 downto 0) = x"05") then
-- push results to p3 Info response queue
p3_info_rsp_wr_en <= '1';
p3_info_rsp_din <= mc_rsp_data;
-- reset others
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
end if;
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
end if;
-- Control mc_rsp_stall signal
if (p1_rsp_q_almost_full = '1' or p2_scc_rsp_almost_full = '1' or p2_rinfo_rsp_almost_full = '1'
or p3_info_rsp_almost_full = '1' or p2_scc_req_almost_full = '1' or p2_rinfo_req_almost_full = '1') then
mc_rsp_stall <= '1';
else
mc_rsp_stall <= '0';
end if;
-- elsif enable = '0'
else
p1_rsp_q_wr_en <= '0';
p1_rsp_q_din <= (others => '0');
p2_scc_rsp_wr_en_temp <= '0';
p2_scc_rsp_din_temp <= (others => '0');
p2_rinfo_rsp_wr_en_temp <= '0';
p2_rinfo_rsp_din_temp <= (others => '0');
p3_info_rsp_wr_en <= '0';
p3_info_rsp_din <= (others => '0');
mc_rsp_stall <= '0';
end if; -- end if enable
p2_scc_rsp_wr_en <= p2_scc_rsp_wr_en_temp;
p2_scc_rsp_din(0) <= or_reduce(p2_scc_rsp_din_temp);
p2_rinfo_rsp_wr_en <= p2_rinfo_rsp_wr_en_temp;
p2_rinfo_rsp_din(0) <= p2_rinfo_rsp_din_temp(0);
end if; -- end if rst
end if; -- end if clk
end process; -- end process rsp decoder
end Behavioral;
| apache-2.0 | 6e7ca7d583772e8eebd01e0296fdb10d | 0.481963 | 2.65046 | false | false | false | false |
jaruiz/light8080 | src/vhdl/testbench/light8080_tb_pkg.vhdl | 1 | 3,509 | --------------------------------------------------------------------------------
-- light8080_tb_pkg.vhdl -- Support package for Light8080 TBs.
--
-- Contains procedures and functions used to dump CPU traces, etc.
--
-- Please see the LICENSE file in the project root for license matters.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.mcu80_pkg.all;
package light8080_tb_pkg is
-- Maximum line size of for console output log. Lines longer than this will be
-- truncated.
constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
-- Console log line buffer --------------------------------------
signal con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
signal con_line_ix : integer;
-- Hex representation of std_logic_vector.
function hstr(slv: unsigned) return string;
-- Every fetch cycle, log the fetch address to file.
-- Loops until done =1.
procedure mon_cpu_trace (
signal clk : in std_logic;
signal reset : in std_logic;
signal done : inout std_logic;
signal con_line_buf : inout string(1 to CONSOLE_LOG_LINE_SIZE);
signal con_line_ix : inout integer;
file con_file : TEXT;
file log_file : TEXT);
end package;
package body light8080_tb_pkg is
function hstr(slv: unsigned) return string is
begin
return hstr(std_logic_vector(slv));
end function hstr;
procedure mon_cpu_trace (
signal clk : in std_logic;
signal reset : in std_logic;
signal done : inout std_logic;
signal con_line_buf : inout string(1 to CONSOLE_LOG_LINE_SIZE);
signal con_line_ix : inout integer;
file con_file : TEXT;
file log_file : TEXT) is
begin
while done = '0' loop
wait until clk'event and clk='1';
-- For the time being the log only contains fetch addresses.
if mon_fetch = '1' then
print(log_file, ""& hstr(mon_addr)& ": ");
end if;
-- Console logging ------------------------------------------------
if mon_uart_ce = '1' and mon_we = '1' and
mon_addr(1 downto 0) = "00" then
-- UART TX data goes to output after a bit of line-buffering
-- and editing
if mon_wdata = X"0A" then
-- CR received: print output string and clear it
print(con_file, con_line_buf(1 to con_line_ix));
print(con_line_buf(1 to con_line_ix));
con_line_ix <= 1;
con_line_buf <= (others => ' ');
elsif mon_wdata = X"0D" then
-- ignore LF. I should be doing the opposite...
elsif mon_wdata = X"04" then
-- EOT terminates simulation.
print("Execution terminated by SW -- EOT written to UART_DATA.");
done <= '1';
else
-- append char to output string
if con_line_ix < con_line_buf'high then
con_line_buf(con_line_ix) <=
character'val(to_integer(unsigned(mon_wdata)));
con_line_ix <= con_line_ix + 1;
end if;
end if;
end if;
end loop;
end procedure mon_cpu_trace;
end package body;
| lgpl-2.1 | 6dd43af3b1af368171154d876f9306a2 | 0.519806 | 4.172414 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/FA10/FA10_tb.vhd | 1 | 2,943 | library ieee;
use ieee.std_logic_1164.all;
entity FA10_tb is
end FA10_tb;
architecture tb of FA10_tb is
component FA10
port(
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0);
Sout : out std_logic_vector(9 downto 0);
Cout : out std_logic
);
end component;
signal A : std_logic_vector(9 downto 0);
signal B : std_logic_vector(9 downto 0);
signal Sout : std_logic_vector(9 downto 0);
signal Cout : std_logic;
begin
mapping: FA10 port map(A,B,Sout,Cout);
-- A(0)<='0';
-- A(1)<='0';
-- A(2)<='0';
-- A(3)<='0';
-- A(4)<='0';
-- A(5)<='0';
-- A(6)<='0';
-- A(7)<='0';
-- A(8)<='0';
-- A(9)<='0';
-- B(0)<='0';
-- B(1)<='0';
-- B(2)<='0';
-- B(3)<='0';
-- B(4)<='0';
-- B(5)<='0';
-- B(6)<='0';
-- B(7)<='0';
-- B(8)<='0';
-- B(9)<='0';
process
begin
A(0)<='0'; wait for 1 ns;
A(0)<='1'; wait for 1 ns;
end process;
process
begin
A(1)<='0'; wait for 2 ns;
A(1)<='1'; wait for 2 ns;
end process;
process
begin
A(2)<='0'; wait for 4 ns;
A(2)<='1'; wait for 4 ns;
end process;
process
begin
A(3)<='0'; wait for 8 ns;
A(3)<='1'; wait for 8 ns;
end process;
process
begin
A(4)<='0'; wait for 16 ns;
A(4)<='1'; wait for 16 ns;
end process;
process
begin
A(5)<='0'; wait for 32 ns;
A(5)<='1'; wait for 32 ns;
end process;
process
begin
A(6)<='0'; wait for 64 ns;
A(6)<='1'; wait for 64 ns;
end process;
process
begin
A(7)<='0'; wait for 128 ns;
A(7)<='1'; wait for 128 ns;
end process;
process
begin
A(8)<='0'; wait for 256 ns;
A(8)<='1'; wait for 256 ns;
end process;
process
begin
A(9)<='0'; wait for 512 ns;
A(9)<='1'; wait for 512 ns;
end process;
process
begin
B(0)<='0'; wait for 1024 ns;
B(0)<='1'; wait for 1024 ns;
end process;
process
begin
B(1)<='0'; wait for 2048 ns;
B(1)<='1'; wait for 2048 ns;
end process;
process
begin
B(2)<='0'; wait for 4096 ns;
B(2)<='1'; wait for 4096 ns;
end process;
process
begin
B(3)<='0'; wait for 8192 ns;
B(3)<='1'; wait for 8192 ns;
end process;
process
begin
B(4)<='0'; wait for 16384 ns;
B(4)<='1'; wait for 16384 ns;
end process;
process
begin
B(5)<='0'; wait for 32768 ns;
B(5)<='1'; wait for 32768 ns;
end process;
process
begin
B(6)<='0'; wait for 65536 ns;
B(6)<='1'; wait for 65536 ns;
end process;
process
begin
B(7)<='0'; wait for 131072 ns;
B(7)<='1'; wait for 131072 ns;
end process;
process
begin
B(8)<='0'; wait for 262144 ns;
B(8)<='1'; wait for 262144 ns;
end process;
process
begin
B(9)<='0'; wait for 524288 ns;
B(9)<='1'; wait for 524288 ns;
end process;
end tb;
configuration cfg_tb of FA10_tb is
for tb
end for;
end cfg_tb; | mit | a21bc78a6caa4aceac9010522a16fe49 | 0.513761 | 2.556907 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/DUT/tinyalu.vhd | 1 | 5,075 | -- *******************************************************************
-- Copyright 2008 Ray Salemi
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity tinyalu is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done : out std_logic;
result : out unsigned ( 15 downto 0 )
);
-- Declarations
end tinyalu;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
architecture rtl of tinyalu is
-- Architecture declarations
-- Internal signal declarations
signal done_aax : std_logic;
signal done_mult : std_logic;
signal result_aax : unsigned(15 downto 0);
signal result_mult : unsigned(15 downto 0);
signal start_single : std_logic; -- Start signal for single cycle ops
signal start_mult : std_logic; -- start signal for multiply
-- Implicit buffer signal declarations
signal done_internal : std_logic;
-- Component Declarations
-- pragma synthesis_off
component alu_firewall
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
done : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic
);
end component;
-- pragma synthesis_on
component single_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
end component;
component three_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
reset_n : in std_logic;
start : in std_logic;
done_mult : out std_logic;
result_mult : out unsigned (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : alu_firewall use entity work.alu_firewall;
for all : single_cycle use entity work.single_cycle;
for all : three_cycle use entity work.three_cycle;
-- pragma synthesis_on
begin
-- purpose: This block shunts the start signal to the correct block.
-- The multiply only sees the start signal when op(2) is '1'
-- type : combinational
-- inputs : op(2),start
-- outputs: start_mult, start_single
start_demux: process (op(2),start)
begin -- process start_demux
case op(2) is
when '0' =>
start_single <= start;
start_mult <= '0';
when '1' =>
start_single <= '0';
start_mult <= start;
when others => null;
end case;
end process start_demux;
result_mux : process(result_aax, result_mult, op)
begin
case op(2) is
when '0' => result <= result_aax;
when '1' => result <= result_mult;
when others => result <= (others => 'X');
end case;
end process result_mux;
done_mux : process(done_aax, done_mult, op)
begin
case op(2) is
when '0' => done_internal <= done_aax;
when '1' => done_internal <= done_mult;
when others => done_internal <= 'X';
end case;
end process done_mux;
-- Instance port mappings.
-- pragma synthesis_off
firewall : alu_firewall
port map (
A => A,
B => B,
clk => clk,
done => done_internal,
op => op,
reset_n => reset_n,
start => start);
-- pragma synthesis_on
add_and_xor : single_cycle
port map (
A => A,
B => B,
clk => clk,
op => op,
reset_n => reset_n,
start => start_single,
done_aax => done_aax,
result_aax => result_aax
);
mult : three_cycle
port map (
A => A,
B => B,
clk => clk,
reset_n => reset_n,
start => start_mult,
done_mult => done_mult,
result_mult => result_mult
);
-- Implicit buffered output assignments
done <= done_internal;
end rtl;
| mit | c419317941e92514a03d9f16fe1cae30 | 0.557635 | 3.731618 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/PIPO4/PIPO4_tb.vhd | 1 | 1,077 | library ieee;
use ieee.std_logic_1164.all;
entity PIPO4_tb is
end PIPO4_tb;
architecture tb of PIPO4_tb is
component PIPO4
port (Rin : in STD_LOGIC_VECTOR (3 downto 0);
CLK, preset, clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal Rin: std_logic_vector(3 downto 0);
signal CLK,Preset,Clear : std_logic := '1';
signal Rout: std_logic_vector(3 downto 0);
begin
mapping: PIPO4 port map(Rin,CLK,Preset,Clear,Rout);
process
begin
Rin(3) <= '0'; wait for 16 ps;
Rin(3) <= '1'; wait for 16 ps;
end process;
process
begin
Rin(2) <= '0'; wait for 8 ps;
Rin(2) <= '1'; wait for 8 ps;
end process;
process
begin
Rin(1) <= '0'; wait for 4 ps;
Rin(1) <= '1'; wait for 4 ps;
end process;
process
begin
Rin(0) <= '0'; wait for 2 ps;
Rin(0) <= '1'; wait for 2 ps;
end process;
process
begin
CLK <= '0'; wait for 1 ps;
CLK <= '1'; wait for 1 ps;
end process;
end tb;
configuration cfg_tb of PIPO4_tb is
for tb
end for;
end cfg_tb; | mit | 29b52acbf538f58208ff062f1d14be2e | 0.597029 | 2.775773 | false | false | false | false |
scarter93/RSA-Encryption | modular_exponentiation.vhd | 1 | 16,237 | -- Entity name: modular_exponentiation
-- Author: Luis Gallet
-- Contact: [email protected]
-- Date: March 8th, 2016
-- Description: Module responsible of performing encryption and decryption. It uses the
-- montgomery_multiplier.vhd to perform multiplication and modulo operations.
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity modular_exponentiation is
generic(WIDTH_IN : integer := 32
);
port( N : in unsigned(WIDTH_IN-1 downto 0); --Number
--Exp : in unsigned(WIDTH_IN-1 downto 0); --Exponent
--M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
enc_dec: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0) --Output
);
end entity;
architecture behavior of modular_exponentiation is
constant zero : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
--constant K : unsigned(WIDTH_IN-1 downto 0) := "00000111101101000101100111100010110001011000100100100000100010010110010001011000000100111101010010101101100110010001101000110100";
--------------------------------------1024 bit constants-----------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "0000001010100000001100001010001010110100011100011001101100010001000001111100111000001001000001001011010111111101001000111100111101010100011110110111110101101000100010000110011110010110101000011011000111111000010000101101110001010001111010011000001110011111100011110000010110100101010000110101000100011110101100110010001011100100001000001011111011101000011010110000000010001101001011100101000110111001110110100010101101110111000000110110011110101011110010100001011000111111111101000110000100100000110101001000001001110110101100100010011100001110111001111100010110110011010011001011000000111011101101100100001000001101001100100110110101111111001111101111010100100111010101111010001000010110000110111101110000010011110101100111111110010001010000101000111110101010001000011101100110100011010010001011000001110110111110110100101001011000010111001110010000001001000010001100110000101110111101100100111000110110001000100011111111011010001100110011101101100100000001110000000001000000001010101101010010001010010101000111000000111111"; --change to std_logic_vector
--constant M : unsigned (WIDTH_IN-1 downto 0) :="1000000110011101010001101100011101100110101011011110001011111011011111001101001101011000110011111000011111000101010011110010010111001100011011111011000011111101111000000011000101110101010000000111111111101000000100001100101101111111101011101100110110010000011001000100001001011011001010010001101010001101011000010110101010000010101001011000111111110000010101000101001111100010001110010100011111011010101000011100011110110111111000001100001011111010001001110001100010000010010110010001100110110110101000010010100111011111000000010011111101011100000111000111010001010111010010111001000000001101010110001101010101110001100010100001101111111010011100001010110011010001000110001101111110000111000100111101000000110011000001011000000110110110000000110110011011101111000111000101010101111110011110100001110111011101011001111000000000011101000000000100001011100001101011011011010110110111111001101100010010000000001011101101011100111000010110000101111010100010110001111011001001100110001110000010111011000010011001101011010100010001";
--constant enc_Exp : unsigned (WIDTH_IN-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001";
--constant dec_Exp : unsigned (WIDTH_IN-1 downto 0) := "0111001011101000111100101011010100011001100011010001001111101101000011011110111101111001100011110001001110111001100100111011111111011001000011010011010010000110111111110101101000011001101011111000001100110110010001001001110110000101101001110111110111001011100000110111011101101000110001100111101000101001110110011011000111001001111111011110101000101100100100010011011010000101000110110110111101011110100111111000101100100110101100111111011101101000001110110111110011111001001000100101010101000001111001001001011100101101110011010100000111110101010001000111101101101100000110011001010100101100000100010100110110000101100000111101100100011011011010101111111110000010110110101101110111010000110000001110101100110011010000000001111100110110100101010111111111111011110101011011001101000000111111010010101001100101000010001011101000001111110111110111010101010000100001001011011101101000010100101001111001000100100010001110111111101011111101100000001100110111110111000100100001011101111011001111110101101111011000110100111010011001";
-------------------------------------------------------------------------------------------------------
-------------------------------------512 bit constants------------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "01000001000100010101100011101011101101011111101101111100001011010111110011010011000111000011011001011101011110011110101110110010011100011010111001110111101110000010100001001011101100000001010010010001010100010110010000111000011111111100000000011000111011010000100010000010110010001000010000001101110010010001001001100110100100110000010010000101011101111110000111001010111001000001110110100110000000100000110001000001011000111001010111111101010111111100011100100000100010100100010000110000011110101000010101111011";
--constant M : unsigned (WIDTH_IN-1 downto 0) := "10000011010000010011110100010110101100001100010010011111110101011001010111110100011000111101001110110100010101111110010110101001010000100101110110110011010111100111100001101010111001100011010001001001100001011011110101100000110011101001110010101101000100000011000100000111010000000001010000100101001011111111101010110100110011101100011000111011110100110001111010000101100000101010111110111001101100111110001001000111011101101110000111100100011010111000000011110110010110111000101111000111100100000000000001011011";
--constant enc_Exp : unsigned(WIDTH_IN-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001";
--constant dec_Exp : unsigned(WIDTH_IN-1 downto 0) := "00100001111011111100111101001100101110111001110111001011001110011101110101010000110110000011001011010111110100010101011000110111010000100100101010011001111000110001011000111101100001011001001000000101011001001000100000000111101011001100010000010110100100011111010101111100011101111001100011001001101001100111111011101011010110110111011110011010011000100011100111100000111001001101001111011111100011101010000010011111010111101011101101010111001100100111000111011111101101011110010011001000111011000111111110001001";
-------------------------------------------------------------------------------------------------------
------------------------------------256 bit constants------------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "0000101101110010100110101100001100101001101001111100011111101000011000101001011001001110110101000001110010010010110001100111001111100100010101001011111110111011111000111100011011101001010001101001011000100000011101110000101101010010100110001110010001001100";
--constant M : unsigned (WIDTH_IN-1 downto 0) := "1001010000001011000100100011011110000011010001100011101100010101010001101101100111111101101100110101101111101011000010101101111101001001011010101011110111000100100101000011101110001111010010000110101011011000011111010110111001010111001101100011101010000011";
--constant dec_Exp : unsigned(WIDTH_IN-1 downto 0) := "0011001000110111010001110010100010011001010110001011101100110101110011100110000010100111000100111010110110111100000111100001111101010111110101000010000111110110111111011101010001100011111000011111101111000110100110110101111111110010100000111111100100100001";
--constant enc_Exp : unsigned(WIDTH_IN-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001";
-------------------------------------------------------------------------------------------------------
--------------------------------------128 bit constants------------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "00000110010001101110000100100000101111011101110010111101100011001010101111001011011010101000010100001011000100011101101000011110";
--constant M : unsigned (WIDTH_IN-1 downto 0) := "10000100010001111000010010000101100100110110101010010001101011001100101110000000001011000101001110000111011101010010011111010001";
--constant dec_Exp : unsigned(WIDTH_IN-1 downto 0) := "00101010110001011001000101000101001110111100100001111110101101000110111111011111100000001110100100110111010101101011010111000001";
--constant enc_Exp : unsigned(WIDTH_IN-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001";
-------------------------------------------------------------------------------------------------------
--------------------------------------32 bit constants------------------------------------------------
--constant K : unsigned (WIDTH_IN-1 downto 0) := "00000110010001101110000100100000";
--constant M : unsigned (WIDTH_IN-1 downto 0) := "10000100010001111000010010000101";
--constant dec_Exp : unsigned(WIDTH_IN-1 downto 0) := "00101010110001011001000101000101";
--constant enc_Exp : unsigned(WIDTH_IN-1 downto 0) := "00000000000000010000000000000001";
-------------------------------------------------------------------------------------------------------
-- Intermidiate signals
signal temp_A1,temp_A2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_B1, temp_B2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_d_ready, temp_d_ready2 : std_logic := '0';
signal temp_M1, temp_M2 : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal latch_in, latch_in2 : std_logic := '0';
signal temp_M : unsigned(WIDTH_IN-1 downto 0) := (WIDTH_IN-1 downto 0 => '0');
signal temp_C : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
-- FSM states
type STATE_TYPE is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10);
signal state: STATE_TYPE := s0;
component montgomery_multiplier
Generic(WIDTH_IN : integer := 8
);
Port( A : in unsigned(WIDTH_IN-1 downto 0);
B : in unsigned(WIDTH_IN-1 downto 0);
N : in unsigned(WIDTH_IN-1 downto 0);
latch : in std_logic;
clk : in std_logic;
reset : in std_logic;
data_ready : out std_logic;
M : out unsigned(WIDTH_IN-1 downto 0)
);
end component;
begin
-- Montgomery Multiplier components
mont_mult_1: montgomery_multiplier
generic map(WIDTH_IN => WIDTH_IN)
port map(
A => temp_A1,
B => temp_B1,
N => temp_M,
latch => latch_in,
clk => clk,
reset => reset,
data_ready => temp_d_ready,
M => temp_M1
);
mont_mult_2: montgomery_multiplier
generic map(WIDTH_IN => WIDTH_IN)
port map(
A => temp_A2,
B => temp_B2,
N => temp_M,
latch => latch_in2,
clk => clk,
reset => reset,
data_ready => temp_d_ready2,
M => temp_M2
);
C <= temp_C;
sqr_mult : Process(clk, reset, N)
variable count : integer := 0;
variable shift_count : integer := 0;
variable temp_N : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable P : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable P_old : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable R : unsigned(WIDTH_IN-1 downto 0):= (WIDTH_IN-1 downto 0 => '0');
variable temp_Exp : unsigned(WIDTH_IN-1 downto 0);
variable temp_mod : unsigned(WIDTH_IN-1 downto 0);
begin
if reset = '1' then
count := 0;
shift_count := 0;
temp_N := (others => '0');
P := (others => '0');
R := (others => '0');
temp_Exp := (others => '0');
temp_mod := (others => '0');
temp_M <= (others => '0');
state <= s0;
elsif rising_edge(clk) then
case state is
-- Check if there are new inputs available
when s0 =>
--(M = zero) OR (Exp = zero) OR
if((N = zero)) OR ((temp_M = M) AND (temp_N = N)) then
state <= s0;
else
temp_mod := M;
state <= s1;
end if;
-- If MSB of modulus is not 1 then shift it left until a 1 is found and count how many times it was shifted
when s1 =>
if(temp_mod(WIDTH_IN-1) = '1')then
if(enc_dec = '1')then
temp_Exp := enc_Exp;
else
temp_Exp := dec_Exp;
end if;
--temp_Exp := Exp;
temp_M <= M;
temp_N := N;
state <= s2;
else
temp_mod := (shift_left(temp_mod,natural(1)));
shift_count := shift_count + 1;
state <= s1;
end if;
-- Compute initial value of P and R
when s2 =>
if(unsigned(K) > zero)then
temp_A1 <= unsigned(K);
temp_B1 <= temp_N;
temp_A2 <= unsigned(K);
temp_B2 <= to_unsigned(1,WIDTH_IN);
latch_in <= '1';
latch_in2 <= '1';
if(temp_d_ready = '0') AND (temp_d_ready2 = '0')then
state <= s3;
end if;
else
state <= s2;
end if;
-- Assign the results of the computations
when s3 =>
latch_in <= '0';
latch_in2 <= '0';
if((temp_d_ready = '1') AND (temp_d_ready2 = '1')) then
P_old := temp_M1;
R := temp_M2;
state <= s4;
end if;
-- Check Listing 1 in report. This operation is inside the for loop and it is always performed
when s4 =>
temp_A1 <= P_old;
temp_B1 <= P_old;
latch_in <= '1';
if(temp_d_ready = '0')then
state <= s5;
end if;
-- If LSB of the exponent is 1 then compute R, else go to state 8
when s5 =>
latch_in <= '0';
if(temp_d_ready = '1')then
P := temp_M1;
if(temp_Exp(0) = '1')then
state <= s6;
else
state <= s8;
end if;
end if;
when s6 =>
temp_A2 <= R;
temp_B2 <= P_old;
latch_in2 <= '1';
if(temp_d_ready2 = '0')then
state <= s7;
end if;
when s7 =>
latch_in2 <= '0';
if(temp_d_ready2 = '1') then
R := temp_M2;
state <= s8;
end if;
-- If the statement is true, it means that we have checked all bits in the exponent or exponent is zero and we compute the output
when s8 =>
if (count = (WIDTH_IN-1)-shift_count) OR (temp_Exp = zero) then
temp_A1 <= to_unsigned(1,WIDTH_IN);
temp_B1 <= R;
state <= s9;
else -- if the statement is false, then we shift the exponent right and increment count
temp_Exp := (shift_right(temp_Exp, natural(1)));
P_old := P;
count := count + 1;
state <= s4;
end if;
when s9 =>
latch_in <= '1';
if(temp_d_ready ='0')then
state <= s10;
end if;
when s10 =>
latch_in <= '0';
if(temp_d_ready = '1') then
temp_C <= temp_M1;
temp_Exp := (others => '0');
count := 0;
shift_count := 0;
P := (others => '0');
R := (others => '0');
temp_mod := (others => '0');
state <= s0;
end if;
end case;
end if;
end process sqr_mult;
end behavior; | mit | b60360b9d2f1f753c90322bc187d28f4 | 0.764057 | 4.591912 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc_process3.vhd | 1 | 6,337 | -- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:57:25 06/23/2014
-- Module Name: scc_process3 - Behavioral
-- Description: if rInfo[id].visited = 1 and SCC[id] = 0: color the node
-- else: request node's info[id] to recover it by marking it unvisited
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_process3 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Process 3 information
p3_done : out std_logic;
p3_count : out unsigned(63 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graph_info : in std_logic_vector(63 downto 0);
scc_results : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count : in unsigned(63 downto 0);
-- Process 3 scc wr queue signals
p3_scc_addr_almost_full : in std_logic;
p3_scc_addr_wr_en : out std_logic;
p3_scc_addr_din : out std_logic_vector(63 downto 0);
-- Process 3 info req queue signals
p3_info_req_almost_full : in std_logic;
p3_info_req_wr_en : out std_logic;
p3_info_req_din : out std_logic_vector(63 downto 0);
-- Process 3 id queue signals
p3_id_q_almost_full : in std_logic;
p3_id_q_wr_en : out std_logic;
p3_id_q_din : out std_logic_vector(63 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 SCC response queue signals
p2_scc_rsp_rd_enb : out std_logic;
p2_scc_rsp_dout : in std_logic_vector(0 downto 0);
p2_scc_rsp_valid : in std_logic;
p2_scc_rsp_empty : in std_logic;
-- Process 2 rInfo response queue signals
p2_rinfo_rsp_rd_enb : out std_logic;
p2_rinfo_rsp_dout : in std_logic_vector(0 downto 0);
p2_rinfo_rsp_valid : in std_logic;
p2_rinfo_rsp_empty : in std_logic
);
end scc_process3;
architecture Behavioral of scc_process3 is
signal count_1 : unsigned (63 downto 0);
signal count_2 : unsigned (63 downto 0);
signal u_idx8 : unsigned (63 downto 0);
signal u_scc_addr : unsigned (63 downto 0);
signal u_graph_info : unsigned (63 downto 0);
begin
p3_count <= count_2;
u_idx8(63 downto 3) <= unsigned(p1_rsp_q_dout(60 downto 0));
u_idx8(2 downto 0) <= (others => '0');
u_scc_addr <= unsigned(scc_results);
u_graph_info <= unsigned(graph_info);
-- PLACE HOLDER
p3 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p3_done <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_scc_rsp_rd_enb <= '0';
p2_rinfo_rsp_rd_enb <= '0';
p3_scc_addr_wr_en <= '0';
p3_scc_addr_din <= (others => '0');
p3_info_req_wr_en <= '0';
p3_info_req_din <= (others => '0');
p3_id_q_wr_en <= '0';
p3_id_q_din <= (others => '0');
else
if (enable = '1') then
-- Pop from p1, p2 response queues if not empty and if p3 queues aren't full
if (p3_scc_addr_almost_full = '0' and p3_info_req_almost_full = '0' and p3_id_q_almost_full = '0'
and p1_rsp_q_empty = '0' and p2_scc_rsp_empty = '0' and p2_rinfo_rsp_empty = '0') then
p1_rsp_q_rd_enb <= '1';
p2_scc_rsp_rd_enb <= '1';
p2_rinfo_rsp_rd_enb <= '1';
else
p1_rsp_q_rd_enb <= '0';
p2_scc_rsp_rd_enb <= '0';
p2_rinfo_rsp_rd_enb <= '0';
end if;
-- Handle popped data
if (p1_rsp_q_valid = '1' and p2_scc_rsp_valid = '1' and p2_rinfo_rsp_valid = '1') then
count_1 <= count_1 + 1;
-- If SCC = 0 and rinfo[0] = 1, push the id to scc_addr
if (p2_scc_rsp_dout(0) = '0' and p2_rinfo_rsp_dout(0) = '1') then
-- mark node ID for color
p3_scc_addr_wr_en <= '1';
p3_scc_addr_din <= std_logic_vector(u_idx8 + u_scc_addr);
p3_info_req_wr_en <= '0';
p3_info_req_din <= (others => '0');
p3_id_q_wr_en <= '0';
p3_id_q_din <= (others => '0');
-- else, request info[0] and recover it
elsif (p2_scc_rsp_dout(0) = '0') then
count_2 <= count_2 + 1;
p3_scc_addr_wr_en <= '0';
p3_scc_addr_din <= (others => '0');
p3_info_req_wr_en <= '1';
p3_info_req_din <= std_logic_vector(u_idx8 + u_graph_info);
p3_id_q_wr_en <= '1';
p3_id_q_din <= std_logic_vector(u_idx8 + u_graph_info);
else
p3_scc_addr_wr_en <= '0';
p3_scc_addr_din <= (others => '0');
p3_info_req_wr_en <= '0';
p3_info_req_din <= (others => '0');
p3_id_q_wr_en <= '0';
p3_id_q_din <= (others => '0');
end if;
else
p3_scc_addr_wr_en <= '0';
p3_scc_addr_din <= (others => '0');
p3_info_req_wr_en <= '0';
p3_info_req_din <= (others => '0');
p3_id_q_wr_en <= '0';
p3_id_q_din <= (others => '0');
end if;
-- Process 2 is done if process 1 is done and count = p1_count
if (p2_done = '1' and count_1 = p2_count) then
p3_done <= '1';
end if;
else
p3_done <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_scc_rsp_rd_enb <= '0';
p2_rinfo_rsp_rd_enb <= '0';
p3_scc_addr_wr_en <= '0';
p3_scc_addr_din <= (others => '0');
p3_info_req_wr_en <= '0';
p3_info_req_din <= (others => '0');
p3_id_q_wr_en <= '0';
p3_id_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 2
end Behavioral;
| apache-2.0 | bb5a526c44ce687cd4e0c389368070b5 | 0.506549 | 2.669334 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/alu8.vhd | 3 | 7,815 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity alu8 is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
ALU_OP : in std_logic_vector( 4 downto 0);
XX : in std_logic_vector(15 downto 0);
YY : in std_logic_vector(15 downto 0);
ZZ : out std_logic_vector(15 downto 0)
);
end alu8;
architecture Behavioral of alu8 is
function sh_mask(Y : unsigned(3 downto 0);
YMAX : unsigned(3 downto 0);
LR : std_logic;
FILL : std_logic;
X : std_logic) return std_logic is
begin
if (YMAX >= Y) then -- Y small
if (LR = '1') then return X; -- LSL
else return FILL; -- LSR
end if;
else -- Y big
if (LR = '1') then return FILL; -- LSL
else return X; -- ASR/LSR
end if;
end if;
end;
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
function b16(A : std_logic) return std_logic_vector is
begin
return b8(A) & b8(A);
end;
function aoxn(A : std_logic_vector(3 downto 0)) return std_logic is
begin
case A is
-- and
when "0000" => return '0';
when "0001" => return '0';
when "0010" => return '0';
when "0011" => return '1';
-- or
when "0100" => return '0';
when "0101" => return '1';
when "0110" => return '1';
when "0111" => return '1';
-- xor
when "1000" => return '1';
when "1001" => return '0';
when "1010" => return '0';
when "1011" => return '1';
-- not Y
when "1100" => return '1';
when "1101" => return '0';
when "1110" => return '1';
when others => return '0';
end case;
end;
signal MD_OR : std_logic_vector(15 downto 0); -- Multiplicator/Divisor
signal PROD_REM : std_logic_vector(31 downto 0);
signal MD_OP : std_logic; -- operation D/M, S/U
signal QP_NEG : std_logic; -- product / quotient negative
signal RM_NEG : std_logic; -- remainder negative
begin
alumux: process(ALU_OP, MD_OP, XX, YY, QP_NEG, RM_NEG, PROD_REM)
variable MASKED_X : std_logic_vector(15 downto 0);
variable SCNT : unsigned(3 downto 0);
variable SFILL : std_logic;
variable ROL1 : std_logic_vector(15 downto 0);
variable ROL2 : std_logic_vector(15 downto 0);
variable ROL4 : std_logic_vector(15 downto 0);
variable ROL8 : std_logic_vector(15 downto 0);
variable X_GE_Y : std_logic; -- signed X >= Y
variable X_HS_Y : std_logic; -- unsigned X >= Y
variable X_HSGE_Y : std_logic; -- any X >= Y
variable X_EQ_Y : std_logic; -- signed X == Y
variable X_CMP_Y : std_logic;
begin
MASKED_X := XX and b16(ALU_OP(0));
SFILL := ALU_OP(0) and XX(15);
if (ALU_OP(1) = '1') then -- LSL
SCNT := UNSIGNED(YY(3 downto 0));
else -- LSR / ASR
SCNT := "0000" - UNSIGNED(YY(3 downto 0));
end if;
if (SCNT(0) = '0') then ROL1 := XX;
else ROL1 := XX(14 downto 0) & XX(15);
end if;
if (SCNT(1) = '0') then ROL2 := ROL1;
else ROL2 := ROL1(13 downto 0) & ROL1(15 downto 14);
end if;
if (SCNT(2) = '0') then ROL4 := ROL2;
else ROL4 := ROL2(11 downto 0) & ROL2(15 downto 12);
end if;
if (SCNT(3) = '0') then ROL8 := ROL4;
else ROL8 := ROL4(7 downto 0) & ROL4(15 downto 8);
end if;
if (XX = YY) then X_EQ_Y := '1';
else X_EQ_Y := '0';
end if;
if (UNSIGNED(XX) >= UNSIGNED(YY)) then X_HSGE_Y := '1';
else X_HSGE_Y := '0';
end if;
if (XX(15) /= YY(15)) then -- different sign/high bit
X_HS_Y := XX(15); -- X ia bigger iff high bit set
X_GE_Y := YY(15); -- X is bigger iff Y negative
else -- same sign/high bit: GE == HS
X_HS_Y := X_HSGE_Y;
X_GE_Y := X_HSGE_Y;
end if;
case ALU_OP is
when ALU_X_HS_Y => X_CMP_Y := X_HS_Y;
when ALU_X_LO_Y => X_CMP_Y := not X_HS_Y;
when ALU_X_HI_Y => X_CMP_Y := X_HS_Y and not X_EQ_Y;
when ALU_X_LS_Y => X_CMP_Y := not (X_HS_Y and not X_EQ_Y);
when ALU_X_GE_Y => X_CMP_Y := X_GE_Y;
when ALU_X_LT_Y => X_CMP_Y := not X_GE_Y;
when ALU_X_GT_Y => X_CMP_Y := X_GE_Y and not X_EQ_Y;
when ALU_X_LE_Y => X_CMP_Y := not (X_GE_Y and not X_EQ_Y);
when ALU_X_EQ_Y => X_CMP_Y := X_EQ_Y;
when others => X_CMP_Y := not X_EQ_Y;
end case;
ZZ <= X"0000";
case ALU_OP is
when ALU_X_HS_Y | ALU_X_LO_Y | ALU_X_HI_Y | ALU_X_LS_Y |
ALU_X_GE_Y | ALU_X_LT_Y | ALU_X_GT_Y | ALU_X_LE_Y |
ALU_X_EQ_Y | ALU_X_NE_Y =>
ZZ <= b16(X_CMP_Y);
when ALU_NEG_Y | ALU_X_SUB_Y =>
ZZ <= MASKED_X - YY;
when ALU_MOVE_Y | ALU_X_ADD_Y =>
ZZ <= MASKED_X + YY;
when ALU_X_AND_Y | ALU_X_OR_Y | ALU_X_XOR_Y | ALU_NOT_Y =>
for i in 0 to 15 loop
ZZ(i) <= aoxn(ALU_OP(1 downto 0) & XX(i) & YY(i));
end loop;
when ALU_X_LSR_Y | ALU_X_ASR_Y | ALU_X_LSL_Y =>
for i in 0 to 15 loop
ZZ(i) <= sh_mask(SCNT, CONV_UNSIGNED(i, 4),
ALU_OP(1), SFILL, ROL8(i));
end loop;
when ALU_X_MIX_Y =>
ZZ(15 downto 8) <= YY(7 downto 0);
ZZ( 7 downto 0) <= XX(7 downto 0);
when ALU_MUL_IU | ALU_MUL_IS |
ALU_DIV_IU | ALU_DIV_IS | ALU_MD_STP => -- mult/div ini/step
ZZ <= PROD_REM(15 downto 0);
when ALU_MD_FIN => -- mult/div
if (QP_NEG = '0') then ZZ <= PROD_REM(15 downto 0);
else ZZ <= X"0000" - PROD_REM(15 downto 0);
end if;
when others => -- modulo
if (RM_NEG = '0') then ZZ <= PROD_REM(31 downto 16);
else ZZ <= X"0000" - PROD_REM(31 downto 16);
end if;
end case;
end process;
muldiv: process(CLK_I)
variable POS_YY : std_logic_vector(15 downto 0);
variable POS_XX : std_logic_vector(15 downto 0);
variable DIFF : std_logic_vector(16 downto 0);
variable SUM : std_logic_vector(16 downto 0);
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
PROD_REM <= X"00000000"; -- product/remainder
MD_OR <= X"0000"; -- multiplicator/divisor
MD_OP <= '0'; -- mult(0)/div(1)
QP_NEG <= '0'; -- quotient/product negative
RM_NEG <= '0'; -- remainder negative
elsif (CE = '1') then
SUM := ('0' & PROD_REM(31 downto 16)) + ('0' & MD_OR);
DIFF := ('0' & PROD_REM(30 downto 15)) - ('0' & MD_OR);
if (XX(15) = '0') then POS_XX := XX;
else POS_XX := X"0000" - XX;
end if;
if (YY(15) = '0') then POS_YY := YY;
else POS_YY := X"0000" - YY;
end if;
case ALU_OP is
when ALU_MUL_IU | ALU_MUL_IS | ALU_DIV_IU | ALU_DIV_IS =>
MD_OP <= ALU_OP(1); -- div / mult
MD_OR <= POS_YY; -- multiplicator/divisor
QP_NEG <= ALU_OP(0) and (XX(15) xor YY(15));
RM_NEG <= ALU_OP(0) and XX(15);
PROD_REM <= X"0000" & POS_XX;
when ALU_MD_STP =>
if (MD_OP = '0') then -- multiplication step
PROD_REM(15 downto 0) <= PROD_REM(16 downto 1);
if (PROD_REM(0) = '0') then
PROD_REM(31 downto 15) <=
'0' & PROD_REM(31 downto 16);
else
PROD_REM(31 downto 15) <= SUM;
end if;
else -- division step
if (DIFF(16) = '1') then -- carry: small remainder
PROD_REM(31 downto 16) <= PROD_REM(30 downto 15);
else
PROD_REM(31 downto 16) <= DIFF(15 downto 0);
end if;
PROD_REM(15 downto 1) <= PROD_REM(14 downto 0);
PROD_REM(0) <= not DIFF(16);
end if;
when others =>
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 14c8f7e50dc7bff56d747511d0f2715a | 0.540243 | 2.469975 | false | false | false | false |
jaruiz/light8080 | src/vhdl/rtl/mcu/mcu80_uart.vhdl | 1 | 18,685 | --##############################################################################
-- mcu80_uart.vhdl -- Basic, hardwired RS232 UART.
--
-- Most operational parameters are hardcoded: 8 bit words, no parity, 1 stop
-- bit. The only parameter that can be configured in run time is the baud rate.
--
-- The receiver logic is a simplified copy of the 8051 UART. The bit period is
-- split in 16 sampling periods, and 3 samples are taken at the center of each
-- bit period. The bit value is decided by majority. The receiver logic has some
-- error recovery capability that should make this core reliable enough for
-- actual application use -- yet, the core does not have a formal test bench.
--
-- See usage notes below.
--
--------------------------------------------------------------------------------
-- Please see the LICENSE file in the project root for license matters.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- UART programmer model
--------------------------------------------------------------------------------
--
-- The UART has a number of configuration registers addressable with input
-- signal addr_i:
--
-- [00] => Data buffer, both transmission and reception.
-- [01] => Status/control register (r/w).
-- [10] => Bit period register, low byte.
-- [11] => Bit period register, high byte.
--
--
-- Data buffers:
----------------
--
-- The same address [00b] is used for both the receive buffer and the
-- transmision buffer.
--
-- Writing to the data buffer when flag TxRdy is high will trigger a
-- transmission and clear flag TxRdy.
-- Writing to the data buffer when flag TxRdy is clear will have no effect.
--
-- Reading the data register when flag RxRdy is high will return the last
-- received data byte, and will clear flag RxRdy but NOT RxIrq.
-- Reading the register when flag RxRdy is clear will return indeterminate data,
-- which in practice will usually be the last byte received.
--
-- Interrupts:
--------------
--
-- The core has two interrupt sources tied to a single external irq line. The
-- sources are these:
--
-- -# Receiver interrupt: Raised when the stop bit is sampled and determined
-- to be valid (about the middle of the bit period).
-- If the stop bit is not valid (not high) then the interrupt is not
-- triggered. If a start bit is determined to be spurious (i.e. the falling
-- edge is detected but the bit value when sampled is not 0) then the
-- interrupt is not triggered.
-- This interrupt sets flag RxIrw in the status register.
-- -# Transmitter interrupt: Raised at the end of the transmission of the stop
-- bit.
-- This interrupt sets flag TxIrq in the status register 1 clock cycle after
-- the interrupt is raised.
--
-- The core does not have any interrupt enable mask. If any interrupt source
-- triggers, the output irq_o is asserted for one cycle. This is all the extent
-- of the interrupt processing done by this module: this UART needs a separate
-- interrupt controller to interface the light8080 core.
--
-- Error detection:
-------------------
--
-- The core is capable of detecting and recovering from these error conditions:
--
-- -# When a start bit is determined to be spurious (i.e. the falling edge is
-- detected but the bit value when sampled is not 0) then the core returns to
-- its idle state (waiting for a new start bit).
-- -# If a stop bit is determined to be invalid (not 1 when sampled), the
-- reception interrupt is not triggered and the received byte is discarded.
-- -# When the 3 samples taken from the center of a bit period are not equal,
-- the bit value is decided by majority.
--
-- In none of the 3 cases does the core raise any error flag. It would be very
-- easy to include those flags in the core, but it would take a lot more time
-- to test them minimally and that's why they haven't been included.
--
-- Status register flags:
-------------------------
--
-- 7 6 5 4 3 2 1 0
-- +-------+-------+-------+-------+-------+-------+-------+-------+
-- | 0 | 0 | RxIrq | TxIrq | 0 | 0 | RxRdy | TxRdy |
-- +-------+-------+-------+-------+-------+-------+-------+-------+
-- h h W1C W1C h h r r
--
-- Bits marked 'h' are hardwired and can't be modified.
-- Bits marked 'r' are read only; they are set and clear by the core.
-- Bits marked W1C ('Write 1 Clear') are set by the core when an interrupt
-- has been triggered and must be cleared by the software by writing a '1'.
--
-- -# Status bit TxRdy is high when there isn't any transmission in progress.
-- It is cleared when data is written to the transmission buffer and is
-- raised at the same time the transmission interrupt is triggered.
-- -# Status bit RxRdy is raised at the same time the receive interrupt is
-- triggered and is cleared when the data register is read.
-- -# Status bit TxIrq is raised when the transmission interrupt is triggered
-- and is cleared when a 1 is written to it.
-- -# Status bit RxIrq is raised when the reception interrupt is triggered
-- and is cleared when a 1 is written to it.
--
-- When writing to the status/control registers, only flags TxIrq and RxIrq are
-- affected, and only when writing a '1' as explained above. All other flags
-- are read-only.
--
-- Baud rate configuration:
---------------------------
--
-- The baud rate is determined by the value of 14-bit register 'bit_period_reg'.
-- This register holds the length of the bit period in clock cycles and its
-- value may be hardcoded or configured at run time.
--
-- When generic HARDWIRED is true, bit_period_reg is hardwired with a value
-- computed from the value of generic BAUD_RATE. The bit period computation
-- needs to know the master clock rate, which should be given in generic
-- CLOCK_RATE.
-- Writes to the baud registers when HARDWIRED is true will be ignored.
--
-- When generic HARDWIRED is false, generics BAUD_RATE and CLOCK_RATE determine
-- the reset value of bit_period_reg, but the register can be changed at run
-- time by writing at addresses [10b] and [11b], which access the low and high
-- bytes of the register, respectively.
-- Reading from those register addresses returns the value of the status
-- register (a LUT saving measure) so the registers are effectively write-only.
--
--------------------------------------------------------------------------------
-- Core interface signals:
--
-- clk_i: Clock input, active rising edge.
-- reset_i: Synchronous reset.
-- txd_o: TxD UART output.
-- rxd_i: RxD UART input -- synchronization logic included.
-- irq_o: Interrupt output, asserted for 1 cycle when triggered.
-- data_i: Data bus, input.
-- data_o: Data bus, output.
-- addr_i: Register selection address (see above).
-- wr_i: Write enable input.
-- rd_i: Read enable input.
-- ce_i: Chip enable, must be active at the same time as wr_i or rd_i.
--
--
-- A detailed explanation of the interface timing will not be given. The core
-- reads and writes like a synchronous memory. There's usage examples in other
-- project files.
--------------------------------------------------------------------------------
entity mcu80_uart is
generic (
HARDWIRED : boolean := true; -- Baud rate hardwired to constant value
BAUD_RATE : integer := 19200; -- Default (or hardwired) baud rate
CLOCK_FREQ : integer := 50E6 -- Clock rate
);
port (
rxd_i : in std_logic;
txd_o : out std_logic;
irq_o : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
addr_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
ce_i : in std_logic;
clk_i : in std_logic;
reset_i : in std_logic
);
end mcu80_uart;
architecture hardwired of mcu80_uart is
-- Bit period expressed in master clock cycles
constant DEFAULT_BIT_PERIOD : integer := (CLOCK_FREQ / BAUD_RATE);
-- Bit sampling period is 1/16 of the baud rate.
constant DEFAULT_SAMPLING_PERIOD : integer := DEFAULT_BIT_PERIOD / 16;
--##############################################################################
-- Common signals
signal reset : std_logic;
signal clk : std_logic;
signal bit_period_reg : unsigned(13 downto 0);
signal sampling_period : unsigned(9 downto 0);
-- Interrupt & status register signals
signal tx_irq_flag : std_logic;
signal rx_irq_flag : std_logic;
signal load_stat_reg : std_logic;
signal load_tx_reg : std_logic;
-- Receiver signals
signal rxd_q : std_logic;
signal tick_ctr : unsigned(3 downto 0);
signal state : unsigned(3 downto 0);
signal next_state : unsigned(3 downto 0);
signal start_bit_detected : std_logic;
signal reset_tick_ctr : std_logic;
signal stop_bit_sampled : std_logic;
signal load_rx_buffer : std_logic;
signal stop_error : std_logic;
signal samples : std_logic_vector(2 downto 0);
signal sampled_bit : std_logic;
signal do_shift : std_logic;
signal rx_buffer : std_logic_vector(7 downto 0);
signal rx_shift_reg : std_logic_vector(9 downto 0);
signal tick_ctr_enable : std_logic;
signal tick_baud_ctr : unsigned(10 downto 0);
signal rx_rdy_flag : std_logic;
signal rx_irq : std_logic;
signal set_rx_rdy_flag : std_logic;
signal rxd : std_logic;
signal read_rx : std_logic;
signal status : std_logic_vector(7 downto 0);
-- Transmitter signals
signal tx_counter : unsigned(13 downto 0);
signal tx_data : std_logic_vector(10 downto 0);
signal tx_ctr_bit : unsigned(3 downto 0);
signal tx_busy : std_logic;
signal tx_irq : std_logic;
begin
-- Rename the most commonly used inputs to get rid of the i/o suffix
clk <= clk_i;
reset <= reset_i;
rxd <= rxd_i;
-- Serial port status byte -- only 2 status flags
status <=
"00" & rx_irq_flag & tx_irq_flag & -- Interrupt flags
"00" & rx_rdy_flag & (not tx_busy); -- State flags
-- Read register multiplexor
with addr_i select data_o <=
rx_buffer when "00",
status when others;
load_tx_reg <= '1' when wr_i = '1' and ce_i = '1' and addr_i = "00" else '0';
load_stat_reg <= '1' when wr_i = '1' and ce_i = '1' and addr_i = "01" else '0';
read_rx <= '1' when rd_i = '1' and ce_i = '1' else '0';
rx_irq <= set_rx_rdy_flag;
irq_o <= rx_irq or tx_irq;
interrupt_flags:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
rx_irq_flag <= '0';
tx_irq_flag <= '0';
else
if set_rx_rdy_flag='1' then
rx_irq_flag <= '1';
elsif load_stat_reg='1' and data_i(5)='1' then
rx_irq_flag <= '0';
end if;
if tx_irq='1' then
tx_irq_flag <= '1';
elsif load_stat_reg='1' and data_i(4)='1' then
tx_irq_flag <= '0';
end if;
end if;
end if;
end process interrupt_flags;
baud_rate_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
bit_period_reg <= to_unsigned(DEFAULT_BIT_PERIOD,14);
else
if wr_i = '1' and ce_i = '1' then
if addr_i = "10" then
bit_period_reg(7 downto 0) <= unsigned(data_i);
elsif addr_i = "11" then
bit_period_reg(13 downto 8) <= unsigned(data_i(5 downto 0));
end if;
end if;
end if;
end if;
end process baud_rate_registers;
sampling_period <= bit_period_reg(13 downto 4);
-- Receiver --------------------------------------------------------------------
baud_counter:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_baud_ctr <= (others => '0');
else
if tick_baud_ctr=sampling_period then
tick_baud_ctr <= (others => '0');
else
tick_baud_ctr <= tick_baud_ctr + 1;
end if;
end if;
end if;
end process baud_counter;
tick_ctr_enable<= '1' when tick_baud_ctr=sampling_period else '0';
-- Register RxD at the bit sampling rate -- 16 times the baud rate.
rxd_input_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rxd_q <= '0';
else
if tick_ctr_enable='1' then
rxd_q <= rxd;
end if;
end if;
end if;
end process rxd_input_register;
-- We detect the start bit when...
start_bit_detected <= '1' when
state="0000" and -- ...we're waiting for the start bit...
rxd_q='1' and rxd='0' -- ...and we see RxD going 1-to-0
else '0';
-- As soon as we detect the start bit we synchronize the bit sampler to
-- the start bit's falling edge.
reset_tick_ctr <= '1' when start_bit_detected='1' else '0';
-- We have seen the end of the stop bit when...
stop_bit_sampled <= '1' when
state="1010" and -- ...we're in the stop bit period...
tick_ctr="1011" -- ...and we get the 11th sample in the bit period
else '0';
-- Load the RX buffer with the shift register when...
load_rx_buffer <= '1' when
stop_bit_sampled='1' and -- ...we've just seen the end of the stop bit...
sampled_bit='1' -- ...and its value is correct (1)
else '0';
-- Conversely, we detect a stop bit error when...
stop_error <= '1' when
stop_bit_sampled='1' and -- ...we've just seen the end of the stop bit...
sampled_bit='0' -- ...and its value is incorrect (0)
else '0';
-- tick_ctr is a counter 16 times faster than the baud rate that is aligned to
-- the falling edge of the start bit, so that when tick_ctr=0 we're close to
-- the start of a bit period.
bit_sample_counter:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tick_ctr <= "0000";
else
if tick_ctr_enable='1' then
-- Restart counter when it reaches 15 OR when the falling edge
-- of the start bit is detected; this is how we synchronize to the
-- start bit.
if tick_ctr="1111" or reset_tick_ctr='1' then
tick_ctr <= "0000";
else
tick_ctr <= tick_ctr + 1;
end if;
end if;
end if;
end if;
end process bit_sample_counter;
-- Main RX state machine:
-- 0 -> waiting for start bit
-- 1 -> sampling start bit
-- 2..9 -> sampling data bit 0 to 7
-- 10 -> sampling stop bit
next_state <=
-- Start sampling the start bit when we detect the falling edge
"0001" when state="0000" and start_bit_detected='1' else
-- Return to idle state if the start bit is not a clean 0
"0000" when state="0001" and tick_ctr="1010" and sampled_bit='1' else
-- Return to idle state at the end of the stop bit period
"0000" when state="1010" and tick_ctr="1111" else
-- Otherwise, proceed to next bit period at the end of each period
state + 1 when tick_ctr="1111" and do_shift='1' else
state;
rx_state_machine_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
state <= "0000";
else
if tick_ctr_enable='1' then
state <= next_state;
end if;
end if;
end if;
end process rx_state_machine_register;
-- Collect 3 RxD samples from the 3 central sampling periods of the bit period.
rx_sampler:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
samples <= "000";
else
if tick_ctr_enable='1' then
if tick_ctr="0111" then
samples(0) <= rxd;
end if;
if tick_ctr="1000" then
samples(1) <= rxd;
end if;
if tick_ctr="1001" then
samples(2) <= rxd;
end if;
end if;
end if;
end if;
end process rx_sampler;
-- Decide the value of the RxD bit by majority
with samples select
sampled_bit <= '0' when "000",
'0' when "001",
'0' when "010",
'1' when "011",
'0' when "100",
'1' when "101",
'1' when "110",
'1' when others;
rx_buffer_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_buffer <= "00000000";
set_rx_rdy_flag <= '0';
else
if tick_ctr_enable='1' and load_rx_buffer='1' and rx_rdy_flag='0' then
rx_buffer <= rx_shift_reg(8 downto 1);
set_rx_rdy_flag <= '1';
else
set_rx_rdy_flag <= '0';
end if;
end if;
end if;
end process rx_buffer_register;
rx_flag:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_rdy_flag <= '0';
else
if set_rx_rdy_flag='1' then
rx_rdy_flag <= '1';
else
if read_rx = '1' then
rx_rdy_flag <= '0';
end if;
end if;
end if;
end if;
end process rx_flag;
-- RX shifter control: shift in any state other than idle state (0)
do_shift <= state(0) or state(1) or state(2) or state(3);
rx_shift_register:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
rx_shift_reg <= "1111111111";
else
if tick_ctr_enable='1' then
if tick_ctr="1010" and do_shift='1' then
rx_shift_reg(9) <= sampled_bit;
rx_shift_reg(8 downto 0) <= rx_shift_reg(9 downto 1);
end if;
end if;
end if;
end if;
end process rx_shift_register;
-- Transmitter -----------------------------------------------------------------
main_tx_process:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
tx_data <= "10111111111";
tx_busy <= '0';
tx_irq <= '0';
tx_ctr_bit <= "0000";
tx_counter <= (others => '0');
elsif load_tx_reg='1' and tx_busy='0' then
tx_data <= "1"&data_i&"01";
tx_busy <= '1';
else
if tx_busy='1' then
if tx_counter = bit_period_reg then
tx_counter <= (others => '0');
tx_data(9 downto 0) <= tx_data(10 downto 1);
tx_data(10) <= '1';
if tx_ctr_bit = "1010" then
tx_busy <= '0';
tx_irq <= '1';
tx_ctr_bit <= "0000";
else
tx_ctr_bit <= tx_ctr_bit + 1;
end if;
else
tx_counter <= tx_counter + 1;
end if;
else
tx_irq <= '0';
end if;
end if;
end if;
end process main_tx_process;
txd_o <= tx_data(0);
end hardwired;
| lgpl-2.1 | c8d102e3bd6e3a7140864be90d60b75a | 0.587102 | 3.624636 | false | false | false | false |
scarter93/RSA-Encryption | montgomery_multiplier.vhd | 1 | 2,891 | -- Entity name: montgomery_multiplier
-- Author: Stephen Carter
-- Contact: [email protected]
-- Date: March 10th, 2016
-- Description: Performs modular multiplication. See paper for more information. Designed for use with RSA Encryption.
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity montgomery_multiplier is
Generic(WIDTH_IN : integer := 8
);
Port( A : in unsigned(WIDTH_IN-1 downto 0);
B : in unsigned(WIDTH_IN-1 downto 0);
N : in unsigned(WIDTH_IN-1 downto 0);
latch : in std_logic;
clk : in std_logic;
reset : in std_logic;
data_ready : out std_logic;
M : out unsigned(WIDTH_IN-1 downto 0)
);
end entity;
architecture behavioral of montgomery_multiplier is
-- Signals
Signal M_temp : unsigned(WIDTH_IN+1 downto 0) := (others => '0');
Signal state : integer := 0;
Signal count : integer := 0;
Signal B_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal A_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal B_zeros : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal N_temp : unsigned(WIDTH_IN-1 downto 0);
Begin
-- Process to perform mod mult operation
compute_M : Process(clk,latch,reset)
Begin
if reset = '0' and rising_edge(clk) then
case state is
when 0 =>
-- latch data when latch high
if latch = '1' then
data_ready <= '0';
M_temp <= (others => '0');
count <= 0;
B_reg <= B;
A_reg <= A;
N_temp <= N;
state <= 1;
end if;
when 1 =>
-- perform appropriate add and shift
-- check to see if we add B or not
if A_reg(0) = '1' then
-- check to see if we add N and B
if (M_temp(0) xor B_reg(0)) = '1' then
M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg + N), integer(1)));
else
M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg), integer(1)));
end if;
else
--check to see if we need to add modulus
if M_temp(0) = '1' then
M_temp <= unsigned(shift_right(unsigned(M_temp + N), integer(1)));
else
M_temp <= unsigned(shift_right(unsigned(M_temp), integer(1)));
end if;
end if;
-- check to see if multiply is complete
if N_temp = to_unsigned(integer(1), WIDTH_IN) then
state <= 2;
else
state <= 1;
end if;
-- Update the A and N value used to update values
N_temp <= unsigned(shift_right(unsigned(N_temp), integer(1)));
A_reg <= unsigned(shift_right(unsigned(A_reg), integer(1)));
when 2 =>
--update output values and return to default state
if( M_temp > N) then
M <= M_temp(WIDTH_IN-1 downto 0) - N;
else
M <= M_temp(WIDTH_IN-1 downto 0);
end if;
data_ready <= '1';
state <= 0;
when others =>
state <= 0;
end case;
end if;
end Process;
end architecture;
| mit | 0a9b31ff9f4a2b9081a5c239d34c2997 | 0.597371 | 3.030398 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/uart._baudgen.vhd | 1 | 2,581 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_baudgen is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
RD : in std_logic;
WR : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_SEROUT : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_READY : out std_logic;
TX_BUSY : out std_logic
);
end uart_baudgen;
architecture Behavioral of uart_baudgen is
COMPONENT baudgen
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
PORT(
CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
END COMPONENT;
signal CE_16 : std_logic;
signal RX_FLAG : std_logic;
signal RX_OLD_FLAG : std_logic;
signal TX_FLAG : std_logic;
signal TX_FLAGQ : std_logic;
signal LTX_DATA : std_logic_vector(7 downto 0);
signal LRX_READY : std_logic;
begin
RX_READY <= LRX_READY;
TX_BUSY <= TX_FLAG xor TX_FLAGQ;
baud: baudgen
GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
PORT MAP(
CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16
);
urt: uart
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
TX_DATA => LTX_DATA,
TX_FLAG => TX_FLAG,
TX_SEROUT => TX_SEROUT,
TX_FLAGQ => TX_FLAGQ,
RX_SERIN => RX_SERIN,
RX_DATA => RX_DATA,
RX_FLAG => RX_FLAG
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
TX_FLAG <= '0';
LTX_DATA <= X"33";
else
if (RD = '1') then -- read Rx data
LRX_READY <= '0';
end if;
if (WR = '1') then -- write Tx data
TX_FLAG <= not TX_FLAG;
LTX_DATA <= TX_DATA;
end if;
if (RX_FLAG /= RX_OLD_FLAG) then
LRX_READY <= '1';
end if;
RX_OLD_FLAG <= RX_FLAG;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 18b82a5090f14abe2a510f0f44f1a0fc | 0.576521 | 2.633673 | false | false | false | false |
jaruiz/light8080 | boards/zybo/zybo_top.vhdl | 1 | 2,197 | --
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
entity ZYBO_TOP is
port(
-- Clock from Ethernet PHY. @note1.
clk_125MHz_i : in std_logic;
-- Pushbuttons.
buttons_i : in std_logic_vector(3 downto 0);
-- Switches.
switches_i : in std_logic_vector(3 downto 0);
-- LEDs.
leds_o : out std_logic_vector(3 downto 0);
-- PMOD E (Std) connector -- PMOD UART (Digilent).
pmod_e_2_txd_o : out std_logic;
pmod_e_3_rxd_i : in std_logic
);
end entity ZYBO_TOP;
architecture rtl of ZYBO_TOP is
signal clk : std_logic;
signal reset : std_logic;
signal extint : std_logic_vector(3 downto 0);
signal iop1 : std_logic_vector(7 downto 0);
signal iop2 : std_logic_vector(7 downto 0);
begin
clk <= clk_125MHz_i;
reset <= buttons_i(3);
-- Light8080 MCU and glue logic ----------------------------------------------
mcu: entity work.mcu80
generic map (
OBJ_CODE => work.obj_code_pkg.object_code,
UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable.
UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller.
BAUD_RATE => 115200, -- UART baud rate.
CLOCK_FREQ => 125E6 -- Clock frequency in Hz.
)
port map (
clk => clk,
reset => reset,
p1_i => iop1,
p2_o => iop2,
extint_i => extint,
txd_o => pmod_e_2_txd_o,
rxd_i => pmod_e_3_rxd_i
);
extint <= iop2(7 downto 4);
iop1(3 downto 0) <= switches_i;
iop1(7 downto 4) <= buttons_i;
-- Smoke test logic (to be removed when up and running) ----------------------
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
leds_o <= "1010";
else
leds_o <= iop2(3 downto 0);
end if;
end if;
end process;
end;
-- @note1: Clock active if PHYRSTB is high. PHYRSTB pin unused, pulled high.
| lgpl-2.1 | 412e1474b0744ea6a101c4f9f7d482d1 | 0.531634 | 3.411491 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/FAM/FAM_tb.vhd | 1 | 1,022 | library ieee;
use ieee.std_logic_1164.all;
entity FAM_tb is
end FAM_tb;
architecture tb of FAM_tb is
component FAM is
port( X, Y, B, Cin : in std_logic;
Sout, Cout : out std_logic);
end component;
signal X, Y, B, Cin, Sout, Cout : std_logic;
begin
mapping: FAM port map(X, Y, B, Cin, Sout, Cout);
--concurrent processes
process
begin
X <= '0'; wait for 40 ns;
X <= '1'; wait for 40 ns;
end process;
process
begin
Y <= '0'; wait for 20 ns;
Y <= '1'; wait for 20 ns;
end process;
process
begin
B <= '0'; wait for 10 ns;
B <= '1'; wait for 10 ns;
end process;
process
begin
Cin <= '0'; wait for 5 ns;
Cin <= '1'; wait for 5 ns;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of FAM_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END | mit | 11eb5d4c6e07c60ecc9ff0473b35cedd | 0.465753 | 3.74359 | false | false | false | false |
rkrajnc/minimig-de1 | rtl/tg68k/TG68K_Pack.vhd | 2 | 8,142 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package TG68K_Pack is
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
constant opcMOVE : integer := 0; --
constant opcMOVEQ : integer := 1; --
constant opcMOVESR : integer := 2; --
constant opcADD : integer := 3; --
constant opcADDQ : integer := 4; --
constant opcOR : integer := 5; --
constant opcAND : integer := 6; --
constant opcEOR : integer := 7; --
constant opcCMP : integer := 8; --
constant opcROT : integer := 9; --
constant opcCPMAW : integer := 10;
constant opcEXT : integer := 11; --
constant opcABCD : integer := 12; --
constant opcSBCD : integer := 13; --
constant opcBITS : integer := 14; --
constant opcSWAP : integer := 15; --
constant opcScc : integer := 16; --
constant andiSR : integer := 17; --
constant eoriSR : integer := 18; --
constant oriSR : integer := 19; --
constant opcMULU : integer := 20; --
constant opcDIVU : integer := 21; --
constant dispouter : integer := 22; --
constant rot_nop : integer := 23; --
constant ld_rot_cnt : integer := 24; --
constant writePC_add : integer := 25; --
constant ea_data_OP1 : integer := 26; --
constant ea_data_OP2 : integer := 27; --
constant use_XZFlag : integer := 28; --
constant get_bfoffset : integer := 29; --
constant save_memaddr : integer := 30; --
constant opcCHK : integer := 31; --
constant movec_rd : integer := 32; --
constant movec_wr : integer := 33; --
constant Regwrena : integer := 34; --
constant update_FC : integer := 35; --
constant linksp : integer := 36; --
constant movepl : integer := 37; --
constant update_ld : integer := 38; --
constant OP1addr : integer := 39; --
constant write_reg : integer := 40; --
constant changeMode : integer := 41; --
constant ea_build : integer := 42; --
constant trap_chk : integer := 43; --
constant store_ea_data : integer := 44; --
constant addrlong : integer := 45; --
constant postadd : integer := 46; --
constant presub : integer := 47; --
constant subidx : integer := 48; --
constant no_Flags : integer := 49; --
constant use_SP : integer := 50; --
constant to_CCR : integer := 51; --
constant to_SR : integer := 52; --
constant OP2out_one : integer := 53; --
constant OP1out_zero : integer := 54; --
constant mem_addsub : integer := 55; --
constant addsub : integer := 56; --
constant directPC : integer := 57; --
constant direct_delta : integer := 58; --
constant directSR : integer := 59; --
constant directCCR : integer := 60; --
constant exg : integer := 61; --
constant get_ea_now : integer := 62; --
constant ea_to_pc : integer := 63; --
constant hold_dwr : integer := 64; --
constant to_USP : integer := 65; --
constant from_USP : integer := 66; --
constant write_lowlong : integer := 67; --
constant write_reminder : integer := 68; --
constant movem_action : integer := 69; --
constant briefext : integer := 70; --
constant get_2ndOPC : integer := 71; --
constant mem_byte : integer := 72; --
constant longaktion : integer := 73; --
constant opcRESET : integer := 74; --
constant opcBF : integer := 75; --
constant opcBFwb : integer := 76; --
constant s2nd_hbits : integer := 77; --
-- constant : integer := 75; --
-- constant : integer := 76; --
-- constant : integer := 7; --
-- constant : integer := 7; --
-- constant : integer := 7; --
constant lastOpcBit : integer := 77;
component TG68K_ALU
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end component;
end;
| gpl-3.0 | 4a47086d87931bf862c4079f4af424db | 0.498649 | 3.689171 | false | false | false | false |
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