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Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/cpu_engine.vhd | 1 | 11,197 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( CLK_I : in std_logic;
T2 : out std_logic;
CLR : in std_logic;
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- input/output
INT : in std_logic;
IO_ADR : out std_logic_vector(7 downto 0);
IO_RD : out std_logic;
IO_WR : out std_logic;
IO_RDAT : in std_logic_vector( 7 downto 0);
-- external memory
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0);
HALT : out std_logic
);
end cpu_engine;
architecture Behavioral of cpu_engine is
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_M : out std_logic;
D_WE_SP : out SP_OP;
-- input/output
IO_RD : out std_logic;
IO_WR : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
-- input/output
IO_RDAT : in std_logic_vector( 7 downto 0);
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal LT2 : std_logic;
-- memory signals
signal MEM_WDAT : std_logic_vector(7 downto 0);
signal MEM_RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO_RD : std_logic;
signal D_IO_WR : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_MEM_WE : std_logic;
signal MEM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
signal C_MQ : std_logic_vector(7 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal LXM_RDAT : std_logic_vector(7 downto 0);
signal OPCS : std_logic;
signal RDATS : std_logic;
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => MEM_WE,
WDAT => MEM_WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => MEM_RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_M => D_MEM_WE,
D_WE_SP => D_WE_SP,
IO_RD => D_IO_RD,
IO_WR => D_IO_WR,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
M_RDAT => MEM_RDAT,
ADR => ADR,
MQ => MEM_WDAT,
IO_RDAT => IO_RDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= '1';
T2 <= LT2;
IO_ADR <= ADR(7 downto 0);
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
XM_WDAT <= MEM_WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
LT2 <= not LT2;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '1') then
RDATS <= ADR(15) or ADR(14) or ADR(13);
LXM_RDAT <= XM_RDAT;
end if;
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '0') then
OPCS <= M_PC(15) or M_PC(14) or M_PC(13);
XM_OPC <= XM_RDAT;
end if;
end if;
end process;
process(OPCS, LM_OPC, XM_OPC)
begin
if (OPCS = '0') then M_OPC <= LM_OPC;
else M_OPC <= XM_OPC;
end if;
end process;
process(RDATS, LXM_RDAT, LM_RDAT)
begin
if (RDATS = '0') then MEM_RDAT <= LM_RDAT;
else MEM_RDAT <= LXM_RDAT;
end if;
end process;
process(LT2, M_PC, ADR, MEM_WE)
begin
if (LT2 = '0') then -- opcode fetch
XM_ADR <= M_PC;
XM_WE <= '0';
XM_CE <= M_PC(15) or M_PC(14) or M_PC(13);
else -- data
XM_ADR <= ADR;
XM_WE <= MEM_WE;
XM_CE <= ADR(15) or ADR(14) or ADR(13);
end if;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '1') then
if (CLR = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_IMM <= X"FFFF";
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
MEM_WE <= '0';
elsif (CE = '1') then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
IO_RD <= D_IO_RD;
IO_WR <= D_IO_WR;
MEM_WE <= D_MEM_WE;
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode...
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | cfe97c9978601caf13d0c41679303a0d | 0.536394 | 2.424118 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_3/testbench.vhdl | 1 | 1,357 |
--------- Test bench -----------------
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench is
end entity;
architecture behaviorial of testbench is
component memory256x8 is
port (
ck : in std_logic;
we : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end component;
component processor is
port (
rst : in std_logic;
ck : in std_logic;
we : out std_logic;
address : out std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end component;
signal a,dp2m,dm2p : std_logic_vector(7 downto 0);
signal ck, we,reset : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
mem: memory256x8
port map ( ck => ck, we => we, address => a, datain => dp2m, dataout => dm2p) ;
proc: processor
port map ( rst => reset, ck => ck, we => we, address => a, datain => dm2p, dataout => dp2m) ;
clock_process : process
begin
ck <= '1';
wait for 0.5 ns;
ck <= '0';
wait for 0.5 ns;
end process;
reset_process : process
begin
reset <= '1' ;
wait for 1.1 ns;
reset <= '0' ;
wait;
end process;
end;
| unlicense | a765f075d4a436024b883d1067893c0d | 0.576271 | 3.246411 | false | true | false | false |
willtmwu/vhdlExamples | Project/SPI_ctrlr.vhd | 1 | 34,245 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_Ctrlr.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Controls the state of the NRF chip for register read and write,
-- as well as packet encoding and decoding
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
use work.project_nrf_subprogV2.all;
entity SPI_ctrlr is
Port ( clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
-- Enable lines
m_en : in STD_LOGIC; -- EN to enable the module, begin initalisation
m_ready : out STD_LOGIC; -- HIGH to say when NRF is ready
-- Transmission Seleect Lines
sTransmissionLines : in STD_LOGIC_VECTOR(2 downto 0);
-- SEND CMD LINES
send_now : in std_logic; -- HIGH for 1 clock cycle
send_message : in std_logic_vector(55 downto 0); -- Packet Type(0x20), 4 byte/address. 7 byte payload(Any Identifiers need to be specified by mem controller). Full packet encryption.
send_active : out STD_LOGIC; -- Active in send mode
-- RECV CMD LINES
recv_dtr : out STD_LOGIC; -- HIGH 1 clk cycle, latch out the data
recv_message : out STD_LOGIC_VECTOR(55 downto 0); -- Latch out the data per byte
recv_active : out STD_LOGIC; -- Currently still active in latching out the data, undecoded
-- Hamming Error passed in from the switches
hamming_err : in STD_LOGIC_vector(7 downto 0); -- Error passed in from the switches, in top controller
-- Control Assignment lines for the NRF chip
IRQ : in STD_LOGIC;
CE : out STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
LED_SPI : out STD_LOGIC_VECTOR(2 downto 0)
);
end SPI_ctrlr;
architecture Behavioral of SPI_ctrlr is
COMPONENT SPI_hw_interface
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
en : IN std_logic;
data_byte_in : IN std_logic_vector(7 downto 0);
data_byte_out : OUT std_logic_vector(7 downto 0);
wen : IN std_logic;
ren : IN std_logic;
M_active : INOUT std_logic;
M_finished : out std_logic;
regLocation : IN std_logic_vector(7 downto 0);
dataAmount : IN std_logic_vector(5 downto 0);
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic
);
END COMPONENT;
-- Initialisation constants
constant NRF_DEF_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(50, 8));
constant NRF_PACKET_TYPE : std_logic_vector(7 downto 0) := x"20";
constant NRF_DEF_SEND_ADDR : std_logic_vector(39 downto 0) := x"0012345678";
constant NRF_DEF_RECV_ADDR : std_logic_vector(39 downto 0) := x"0042913306"; -- Not used use for NRF_Register, sys default xE7E7E7E7E7
-- Base Station Channels, must reset to configure
constant NRF_PSNL_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(41, 8));
constant NRF_PSNL_SEND_ADDR : std_logic_vector(39 downto 0) := x"0042762090";
constant NRF_PSNL_RECV_ADDR : std_logic_vector(39 downto 0) := x"0042913306";
constant NRF_DEF_REG_RECV : std_logic_vector(39 downto 0) := x"E7E7E7E7E7";
-- ALL Base channel data
constant NRF_B1_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(43, 8));
constant NRF_B1_SEND_ADDR : std_logic_vector(39 downto 0) := x"0012345678";
constant NRF_B2_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(46, 8));
constant NRF_B2_SEND_ADDR : std_logic_vector(39 downto 0) := x"0012345679";
constant NRF_B3_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(48, 8));
constant NRF_B3_SEND_ADDR : std_logic_vector(39 downto 0) := x"001234567A";
constant NRF_B4_CH : std_logic_vector(7 downto 0) := std_logic_vector(IEEE.numeric_std.to_unsigned(50, 8));
constant NRF_B4_SEND_ADDR : std_logic_vector(39 downto 0) := x"001234567B";
-- Register Location/CMD and Expected Values
constant NRF_READ_REG : std_logic_vector(7 downto 0) := x"00";
constant NRF_WRITE_REG : std_logic_vector(7 downto 0) := x"20";
constant NRF_EN_AA : std_logic_vector(7 downto 0) := x"01"; -- 'Enable Auto Acknowledgment' register address
constant NRF_RD_RX_PLOAD : std_logic_vector(7 downto 0) := x"61";
constant NRF_WR_TX_PLOAD : std_logic_vector(7 downto 0) := x"A0";
constant NRF_RX_PW_P0 : std_logic_vector(7 downto 0) := x"11"; -- 'RX payload width, pipe0' register address
constant NRF_FLUSH_TX : std_logic_vector(7 downto 0) := x"E1";
constant NRF_FLUSH_RX : std_logic_vector(7 downto 0) := x"E2";
constant NRF_ACTIVATE : std_logic_vector(7 downto 0) := x"50"; -- Not sure if required
constant NRF_CONFIG : std_logic_vector(7 downto 0) := x"00";
constant NRF_EN_RX_ADDR : std_logic_vector(7 downto 0) := x"02";
constant NRF_RF_CH : std_logic_vector(7 downto 0) := x"05";
constant NRF_RF_SETUP : std_logic_vector(7 downto 0) := x"06";
constant NRF_STATUS : std_logic_vector(7 downto 0) := x"07";
constant NRF_RX_ADDR_P0 : std_logic_vector(7 downto 0) := x"0A";
constant NRF_TX_ADDR : std_logic_vector(7 downto 0) := x"10";
constant NRF_RX_DR : std_logic_vector(7 downto 0) := x"40";
constant NRF_TX_DS : std_logic_vector(7 downto 0) := x"20";
constant NRF_MAX_RT : std_logic_vector(7 downto 0) := x"10";
-- Signals for Controller
type CTRL_FSM is ( CTRL_IDLE,
CTRL_TX_ADDR, CTRL_RX_ADDR,
CTRL_EN_AA, CTRL_EN_RX_ADDR,
CTRL_RX_PW_P0,
CTRL_RF_CH,
CTRL_RF_SETUP,
CTRL_NRF_CONFIG,
-- Now finished initialisation and ready for normal operation
CTRL_MODE_RX, -- Re-entry required, for rentry into RX_MODE
CTRL_FULL_CHECK, -- Check the Status on LA
CTRL_READY, -- IDLE State after initalisation, Watchdog to enter CHECK_STATUS
CTRL_CHECK_STATUS, -- Check Status for FIFO Ready, back to CTRL_READY if no message. Enter READ_RX_FIFO if FIFO ready
CTRL_READ_RX_FIFO, -- READ out the message and decode, ready to latch out the message. Read active begun
CTRL_FLUSH_RX, -- Flush Register
CTRL_CLEAR_STATUS, -- Reentry to Mode_RX, after clear by Write 1
CTRL_WRIT_SETUP, -- Write to Config to go to TX Mode
CTRL_WRIT_SEND, -- Encrypt Message and Send now, to TX FIFO Buffer
CTRL_TX_PULSE, -- Pulse 10us
CTRL_NRF_SETTLE -- Settle at least for 800us, for either TX or after CLEAR_STATUS
); -- Implement check methods. Signal RED on error. But continue intialisation
signal CTRL_STATE : CTRL_FSM := CTRL_IDLE;
constant CTRL_DELAY : integer := 100; -- Roughly at least 1 SCLK Between each state execution
signal CTRL_WAIT_COUNTER : integer range 100 downto 0 := 0;
-- Watchdog signal generation, for CHECK_STATUS entry
signal WD_T_Sig : std_logic := '0'; -- Watch dog siganl ___-___-___-___
type WD_FSM is (WD_IDLE, WD_SIG);
signal WD_STATE : WD_FSM := WD_IDLE;
signal WD_F_Reset : std_logic := '0'; -- Force synchro reset
constant delay_scaler : integer := 26; -- Change to 26 for actual hardware testing, check on clk scaling
signal clockScalers : std_logic_vector(26 downto 0) := (others => '0');
-- Message Buffer
subtype byte is std_logic_vector(7 downto 0); -- Byte type
type message_buffer is array(15 downto 0) of byte; -- Maximum of 16 byte message, unencoded message
signal NRF_message : message_buffer := (others => (others => '0')); -- TX message
signal NRF_reply : message_buffer := (others => (others => '0')); -- RX message
signal NRF_L_Check : std_logic := '0'; -- Sync to write upper or lower
signal message_h_word : std_logic_vector(15 downto 0) := (others => '0');
-- Signals for SPI Burst Module
signal CTRL_PREP : std_logic := '0'; -- To know if SPI data loaded, prepared
signal CTRL_counter : integer range 32 downto 0 := 0; -- Mainly, to count how many bytes to load data in
signal CTRL_pulse_count : integer range 1000 downto 0 := 0; -- 10us Exact Pulse
signal CTRL_settle_count: integer range 80000 downto 0 := 0; -- At least 800us, for base station settling
-- Sub module lines
signal SPI_en : std_logic := '0'; -- CLK in data
signal SPI_Byte_in : std_logic_vector(7 downto 0) := (others => '0'); -- Byte clked in on SPI_EN
signal SPI_Byte_out : std_logic_vector(7 downto 0); -- Byte clked out on SPI_EN
signal SPI_wen : std_logic := '0'; -- Pulse 1 HIGH Clk to send data
signal SPI_ren : std_logic := '0'; -- Pulse 1 HIGH Clk to read from register
signal SPI_active : std_logic; -- Active HIGH
signal SPI_finish : std_logic; -- Pulses OUT on FINISH
signal SPI_regLocation : std_logic_vector(7 downto 0) := (others => '0'); -- Register Location to send data
signal SPI_dataAmount : std_logic_vector(5 downto 0) := (others => '0'); -- Amount to send, exact bytes 1-32
-- REGISTER SIGNALS
signal NRF_REG_SET_CH : std_logic_vector(7 downto 0) := NRF_DEF_CH;
signal NRF_REG_SEND_ADDR : std_logic_vector(39 downto 0) := NRF_DEF_SEND_ADDR;
signal NRF_REG_RECV_ADDR : std_logic_vector(39 downto 0) := NRF_DEF_REG_RECV;
begin
M_S: SPI_hw_interface PORT MAP (
clk, masterReset,
SPI_en,
SPI_Byte_in,
SPI_Byte_out,
SPI_wen,
SPI_ren,
SPI_active,
SPI_finish,
SPI_regLocation,
SPI_dataAmount,
CS, SCLK, MOSI, MISO -- NRF Lines
);
with sTransmissionLines select
NRF_REG_SET_CH <= NRF_B1_CH when "001",
NRF_B2_CH when "010",
NRF_B3_CH when "011",
NRF_B4_CH when "100",
NRF_PSNL_CH when "101",
NRF_DEF_CH when others;
with sTransmissionLines select
NRF_REG_SEND_ADDR <= NRF_B1_SEND_ADDR when "001",
NRF_B2_SEND_ADDR when "010",
NRF_B3_SEND_ADDR when "011",
NRF_B4_SEND_ADDR when "100",
NRF_PSNL_SEND_ADDR when "101",
NRF_DEF_SEND_ADDR when others;
with sTransmissionLines select
NRF_REG_RECV_ADDR <= NRF_PSNL_RECV_ADDR when "101",
NRF_DEF_REG_RECV when others;
-- Default TX Payload Headers
NRF_Message(0) <= NRF_PACKET_TYPE;
NRF_Message(1) <= NRF_REG_SEND_ADDR(7 downto 0);
NRF_Message(2) <= NRF_REG_SEND_ADDR(15 downto 8);
NRF_Message(3) <= NRF_REG_SEND_ADDR(23 downto 16);
NRF_Message(4) <= NRF_REG_SEND_ADDR(31 downto 24);
-- Student Number is Switched to LSByte
NRF_Message(5) <= NRF_DEF_RECV_ADDR(31 downto 24);
NRF_Message(6) <= NRF_DEF_RECV_ADDR(23 downto 16);
NRF_Message(7) <= NRF_DEF_RECV_ADDR(15 downto 8);
NRF_Message(8) <= NRF_DEF_RECV_ADDR(7 downto 0);
process(clk, masterReset)
begin
if(masterReset = '1') then
CTRL_STATE <= CTRL_IDLE; -- IDLE State, uninitialised
CE <= '0'; -- Was 1 on idle, CHECK
SPI_wen <= '0'; -- Submodule Control, WRIT register pulse
SPI_ren <= '0'; -- Submodule Control, READ register pulse
M_ready <= '0'; -- Outside feedback, Controller not yet ready
SEND_ACTIVE <= '0'; -- Outside feedback, Controller in SEND state
RECV_ACTIVE <= '0'; -- Outside feedback, Controller in RECV state
RECV_dtr <= '0'; -- DTR Pulse when data on latch (RECV_Message) and ready
RECV_message <= (others => '0');
CTRL_wait_counter <= 0; -- State delay counter
CTRL_prep <= '0'; -- State internal synchro, to know when state prepated for re-entry
CTRL_counter <= 0; -- Byte sent counter
CTRL_pulse_count <= 0; -- Count for Pulse generation
CTRL_settle_count <= 0; -- Settle on state transition
NRF_L_Check <= '0'; -- Signal to synchro upper and lower byte encoded sending
WD_F_Reset <= '0'; -- Force watchdog reset on CTRL_Ready idle re-entry
-- SEND and RECV buffer signals
message_h_word <= (others => '0');
--NRF_Reply <= (others => (others => '0'));
--NRF_Message(9 to 15) <= (others => '0');
elsif rising_edge(clk) then
case CTRL_STATE is
when CTRL_IDLE =>
if(m_en = '1') then
CE <= '0';
CTRL_prep <= '0';
CTRL_STATE <= CTRL_TX_ADDR;
M_ready <= '0';
WD_F_Reset <= '0';
SEND_ACTIVE <= '0';
RECV_ACTIVE <= '0';
NRF_L_check <= '0';
CTRL_counter <= 0;
CTRL_pulse_count <= 0;
CTRL_settle_count <= 0;
recv_dtr <= '0';
recv_message <= (others => '0');
else
CTRL_STATE <= CTRL_IDLE;
CE <= '0'; -- WAS '1' on IDLE, CHECK
SPI_wen <= '0';
SPI_ren <= '0';
M_ready <= '0';
WD_F_Reset <= '0';
SEND_ACTIVE <= '0';
RECV_ACTIVE <= '0';
NRF_L_Check <= '0';
CTRL_counter <= 0;
recv_dtr <= '0';
recv_message <= (others => '0');
message_h_word <= (others => '0');
NRF_Reply <= (others => (others => '0'));
end if;
when CTRL_TX_ADDR =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_RX_ADDR;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_PREP = '0') then
if (CTRL_Counter < 5) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in, LSB Send
if (CTRL_Counter = 0) then
SPI_Byte_in <= NRF_REG_SEND_ADDR(7 downto 0);
elsif (CTRL_Counter = 1) then
SPI_Byte_in <= NRF_REG_SEND_ADDR(15 downto 8);
elsif (CTRL_Counter = 2) then
SPI_Byte_in <= NRF_REG_SEND_ADDR(23 downto 16);
elsif (CTRL_Counter = 3) then
SPI_Byte_in <= NRF_REG_SEND_ADDR(31 downto 24);
elsif (CTRL_Counter = 4) then
SPI_Byte_in <= NRF_REG_SEND_ADDR(39 downto 32);
end if;
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_TX_ADDR or NRF_WRITE_REG);
SPI_dataAmount <= "000101"; -- 5 Bytes
end if;
else
SPI_wen <= '0';
end if;
end if;
when CTRL_RX_ADDR =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_EN_AA;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 5) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in, LSB Send
-- SPI_Byte_in <= (others => '0');
if (CTRL_Counter = 0) then
SPI_Byte_in <= NRF_REG_RECV_ADDR(7 downto 0);
elsif (CTRL_Counter = 1) then
SPI_Byte_in <= NRF_REG_RECV_ADDR(15 downto 8);
elsif (CTRL_Counter = 2) then
SPI_Byte_in <= NRF_REG_RECV_ADDR(23 downto 16);
elsif (CTRL_Counter = 3) then
SPI_Byte_in <= NRF_REG_RECV_ADDR(31 downto 24);
elsif (CTRL_Counter = 4) then
SPI_Byte_in <= NRF_REG_RECV_ADDR(39 downto 32);
end if;
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_RX_ADDR_P0 or NRF_WRITE_REG);
SPI_dataAmount <= "000101"; -- 5 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_EN_AA =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_EN_RX_ADDR;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= (others => '0'); -- Disable Auto.ACK
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_EN_AA or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_EN_RX_ADDR =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_RX_PW_P0;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= "00000001"; -- Enable Pipe0
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_EN_RX_ADDR or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_RX_PW_P0 =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_RF_CH;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= "00100000"; -- Enable Pipe0
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_RX_PW_P0 or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_RF_CH => -- Skipped CE
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_RF_SETUP;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= NRF_REG_SET_CH;
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_RF_CH or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_RF_SETUP =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_NRF_CONFIG;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= "00000110"; -- TX_PWR:0dBm, Datarate:1Mbps
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_RF_SETUP or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_NRF_CONFIG =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_MODE_RX;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
CTRL_pulse_count <= 0;
CTRL_settle_count <= 0;
recv_dtr <= '0'; --
recv_message <= (others => '0'); --
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= x"32"; -- Set PWR_UP bit, enable CRC(2 unsigned chars) & Prim:TX. MAX_RT & TX_DS enabled..
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_CONFIG or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_MODE_RX =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_FULL_CHECK;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CE <= '1';
CTRL_WAIT_COUNTER <= 0;
CTRL_pulse_count <= 0;
CTRL_settle_count <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= x"33"; -- Set PWR_UP bit, disable CRC(2 unsigned chars) & Prim:RX.
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_CONFIG or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_FULL_CHECK =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_READY;
M_ready <= '1';
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
WD_F_RESET <= '1';
CTRL_SETTLE_COUNT <= 0;
message_h_word <= (others => '0');
NRF_Reply <= (others => (others => '0'));
else
if (CTRL_SETTLE_COUNT = 13000) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= x"ff"; -- Set PWR_UP bit, disable CRC(2 unsigned chars) & Prim:RX.
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_ren <= '1';
SPI_Reglocation <= (NRF_CONFIG or NRF_READ_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_ren <= '0';
end if;
else
CTRL_SETTLE_COUNT <= CTRL_SETTLE_COUNT + 1;
end if;
end if;
when CTRL_READY =>
if (send_now = '1') then
CTRL_STATE <= CTRL_WRIT_SETUP;
SEND_ACTIVE <= '1';
-- Lower Message(0) to Higher Packet(15)
NRF_Message(9) <= send_message(55 downto 48);
NRF_Message(10) <= send_message(47 downto 40);
NRF_Message(11) <= send_message(39 downto 32);
NRF_Message(12) <= send_message(31 downto 24);
NRF_Message(13) <= send_message(23 downto 16);
NRF_Message(14) <= send_message(15 downto 8);
NRF_Message(15) <= send_message(7 downto 0);
-- NRF_Message(9) <= send_message(7 downto 0);
-- NRF_Message(10) <= send_message(15 downto 8);
-- NRF_Message(11) <= send_message(23 downto 16);
-- NRF_Message(12) <= send_message(31 downto 24);
-- NRF_Message(13) <= send_message(39 downto 32);
-- NRF_Message(14) <= send_message(47 downto 40);
-- NRF_Message(15) <= send_message(55 downto 48);
message_h_word <= Hamming_Byte_encoder(NRF_Message(0)); -- Set Counter to 1 on follow state
CTRL_Prep <= '0';
CTRL_Counter <= 0;
CTRL_WAIT_COUNTER <= 0;
-- elsif(WD_T_SIG = '1') then
elsif (IRQ = '0') then
CTRL_STATE <= CTRL_CHECK_STATUS;
CTRL_Prep <= '0';
CTRL_Counter <= 0;
CTRL_WAIT_COUNTER <= 0;
RECV_ACTIVE <= '1';
else
WD_F_RESET <= '0';
SEND_ACTIVE <= '0';
RECV_ACTIVE <= '0';
NRF_L_Check <= '0';
CTRL_pulse_count <= 0;
CTRL_settle_count <= 0;
end if;
when CTRL_CHECK_STATUS =>
if (SPI_finish = '1') then
CTRL_Counter <= 1; -- Synchro for event call
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then -- Always have some delay
if ( (CTRL_PREP = '0') and (CTRL_Counter = 0) ) then
SPI_Reglocation <= (NRF_STATUS or NRF_READ_REG);
SPI_dataAmount <= "000001";
SPI_ren <= '1';
CTRL_Counter <= 0;
CTRL_PREP <= '1';
else
if (CTRL_Counter = 0) then
SPI_ren <= '0';
elsif (CTRL_Counter = 1) then
SPI_en <= '1';
CTRL_Counter <= CTRL_Counter + 1;
elsif (CTRL_Counter = 2) then
SPI_en <= '0';
CTRL_Counter <= CTRL_Counter + 1;
elsif (CTRL_Counter = 3) then
if ( (SPI_Byte_out and NRF_RX_DR) = NRF_RX_DR ) then
CTRL_STATE <= CTRL_READ_RX_FIFO;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
else
CTRL_STATE <= CTRL_READY;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
end if;
end if;
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_READ_RX_FIFO =>
if (SPI_finish = '1') then
CTRL_Counter <= 1; -- Synchro for event call
CTRL_Prep <= '0';
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then -- Always have some delay
if ( (CTRL_PREP = '0') and (CTRL_Counter = 0) ) then
SPI_Reglocation<= (NRF_RD_RX_PLOAD or NRF_READ_REG);
SPI_dataAmount <= "100000";
SPI_ren <= '1';
CTRL_PREP <= '1';
CTRL_Counter <= 0;
else
if (CTRL_Counter = 0) then
SPI_ren <= '0';
elsif (CTRL_Counter = 1) then
SPI_en <= '1';
CTRL_Counter <= CTRL_Counter + 1;
elsif (CTRL_Counter = 2) then
CTRL_Counter <= CTRL_Counter + 1;
elsif (CTRL_Counter <= 19) then
if (CTRL_Prep = '0') then
CTRL_Prep <= '1';
message_h_word(7 downto 0) <= SPI_Byte_out;
if (CTRL_Counter > 3) then
NRF_Reply(CTRL_Counter - 4) <= Hamming_Byte_decoder(message_h_word);
end if;
elsif (CTRL_Prep = '1') then
CTRL_Prep <= '0';
message_h_word(15 downto 8) <= SPI_Byte_out;
CTRL_Counter <= CTRL_Counter + 1;
end if;
else
-- Transition
CTRL_STATE <= CTRL_FLUSH_RX;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
message_h_word <= (others => '0');
SPI_en <= '0';
end if;
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_FLUSH_RX =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_CLEAR_STATUS;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
CE <= '0';
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= x"00"; -- Clear RX FIFO
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_FLUSH_RX or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_CLEAR_STATUS => -- Time to release the message data, dtr and message
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_NRF_SETTLE;
CTRL_PREP <= '0';
CTRL_counter <= 0;
CTRL_WAIT_COUNTER <= 0;
recv_dtr <= '1';
-- Move out the data
recv_message(7 downto 0) <= NRF_REPLY(15);
recv_message(15 downto 8) <= NRF_REPLY(14);
recv_message(23 downto 16) <= NRF_REPLY(13);
recv_message(31 downto 24) <= NRF_REPLY(12);
recv_message(39 downto 32) <= NRF_REPLY(11);
recv_message(47 downto 40) <= NRF_REPLY(10);
recv_message(55 downto 48) <= NRF_REPLY(9);
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= "01111110"; -- Clear RX_DR, TX_DS and MAX_RT by Write 1
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_STATUS or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_WRIT_SETUP =>
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_WRIT_SEND;
CTRL_PREP <= '0';
CTRL_counter <= 1;
CTRL_WAIT_COUNTER <= 0;
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then
if (CTRL_PREP = '0') then
if (CTRL_Counter < 1) then
SPI_EN <= '1'; -- Enable SPI CLK Module data in
SPI_Byte_in <= x"32"; -- Set PWR_UP bit, enable CRC(2 unsigned chars) & Prim:TX.
CTRL_Counter <= CTRL_Counter + 1;
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_CONFIG or NRF_WRITE_REG);
SPI_dataAmount <= "000001"; -- 1 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_WRIT_SEND =>
-- Start with message clking in, 32 bytes
if (SPI_finish = '1') then
CTRL_STATE <= CTRL_TX_PULSE;
CE <= '0';
CTRL_PREP <= '0';
CTRL_counter <= 0; -- Amount of bytes sent
CTRL_WAIT_COUNTER <= 0; -- Wait for CSN DELAY
else
if (CTRL_WAIT_COUNTER = CTRL_DELAY) then -- 1 SCLK DELAY
if (CTRL_PREP = '0') then
if (CTRL_Counter < 17) then
if (NRF_L_Check = '0') then
NRF_L_CHECK <= '1';
SPI_Byte_in <= message_h_word(7 downto 0) XOR hamming_err;
elsif (NRF_L_Check = '1') then
NRF_L_CHECK <= '0';
SPI_Byte_in <= message_h_word(15 downto 8) XOR hamming_err;
if (CTRL_Counter < 16) then
message_h_word <= Hamming_Byte_encoder(NRF_Message(CTRL_Counter));
end if;
CTRL_Counter <= CTRL_Counter + 1;
end if;
SPI_EN <= '1'; -- Enable SPI CLK Module data in
else
SPI_EN <= '0';
CTRL_PREP <= '1';
SPI_wen <= '1';
SPI_Reglocation <= (NRF_WR_TX_PLOAD);
SPI_dataAmount <= "100000"; -- 32 Bytes
end if;
else
SPI_wen <= '0';
end if;
else
CTRL_WAIT_COUNTER <= CTRL_WAIT_COUNTER + 1;
end if;
end if;
when CTRL_TX_PULSE => -- Consider Pulse Delay
if(CTRL_PULSE_COUNT = 1000)then
if (CTRL_PREP = '0') then
CTRL_Prep <= '1';
CE <= '1';
CTRL_STATE <= CTRL_TX_Pulse;
CTRL_Pulse_count <= 0;
else
CTRL_Prep <= '0';
CE <= '0';
CTRL_STATE <= CTRL_NRF_SETTLE;
end if;
CTRL_Counter <= 0;
else
CTRL_PULSE_COUNT <= CTRL_PULSE_COUNT + 1;
end if;
when CTRL_NRF_SETTLE =>
if (CTRL_SETTLE_COUNT = 80000) then -- Reduce, delay it is not the issue
CTRL_SETTLE_COUNT <= 0;
CTRL_STATE <= CTRL_MODE_RX;
else
CTRL_SETTLE_COUNT <= CTRL_SETTLE_COUNT + 1;
recv_dtr <= '0';
end if;
end case;
end if;
end process;
-- Watchdog Process
process (clk, masterReset) begin
if (masterReset = '1') then
WD_STATE <= WD_IDLE;
WD_T_SIG <= '0';
elsif rising_edge(clk) then
if (WD_F_Reset = '1') then
WD_STATE <= WD_IDLE;
WD_T_SIG <= '0';
else
case WD_STATE is
when WD_IDLE =>
if (clockScalers(delay_scaler) = '1') then
WD_STATE <= WD_SIG;
WD_T_SIG <= '1';
else
WD_STATE <= WD_IDLE;
WD_T_SIG <= '0';
end if;
when WD_SIG =>
WD_T_SIG <= '0';
if (clockScalers(delay_scaler) = '0') then
WD_STATE <= WD_IDLE;
end if;
end case;
end if;
end if;
end process;
-- Scaling Process in all modules, able to obtain whichever scale module needs
process (clk, masterReset) begin
if (masterReset = '1') then
clockScalers <= (others => '0'); -- Asynchro Reset
elsif rising_edge(clk) then
if (WD_F_Reset = '1') then
clockScalers <= (others => '0');
else
clockScalers <= clockScalers + '1';
end if;
end if;
end process;
end Behavioral; | apache-2.0 | c4942573e24aa7dc77feaeba89fbd478 | 0.529712 | 3.070199 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/memory.vhd | 2 | 14,129 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
| mit | 8ca1a8a92a36134125ad2a40fdd0756a | 0.494798 | 2.058421 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl_reset_gating.vhd | 1 | 3,951 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
entity std_ovl_reset_gating is
generic (
reset_polarity : ovl_reset_polarity := OVL_ACTIVE_EDGES_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_logic;
enable : in std_logic;
reset_n : out std_logic
);
end entity std_ovl_reset_gating;
architecture rtl of std_ovl_reset_gating is
signal greset : std_logic;
constant gating_on : boolean := controls.gating_ctrl = OVL_ON;
constant reset_polarity_ctrl : ovl_reset_polarity_natural :=
ovl_get_ctrl_val(reset_polarity, controls.reset_polarity_default);
constant gating_type_ctrl : ovl_gating_type_natural :=
ovl_get_ctrl_val(gating_type, controls.gating_type_default);
begin
ovl_on_gen : if ((controls.assert_ctrl = OVL_ON) or (controls.cover_ctrl = OVL_ON)) generate
----------------------------------------------------------------------------
-- Global reset --
----------------------------------------------------------------------------
ovl_global_reset_on_gen : if (controls.global_reset_ctrl = OVL_ON) generate
reset_n <= ovl_global_reset_signal;
end generate ovl_global_reset_on_gen;
ovl_global_reset_off_gen : if (controls.global_reset_ctrl = OVL_OFF) generate
--------------------------------------------------------------------------
-- Gated reset --
--------------------------------------------------------------------------
ovl_gate_reset_gen : if (gating_on and (gating_type_ctrl = OVL_GATE_RESET)) generate
greset <= reset and enable;
end generate ovl_gate_reset_gen;
--------------------------------------------------------------------------
-- Non-gated reset --
--------------------------------------------------------------------------
ovl_no_gate_reset_gen : if (gating_on and (gating_type_ctrl /= OVL_GATE_RESET)) generate
greset <= reset;
end generate ovl_no_gate_reset_gen;
--------------------------------------------------------------------------
-- Gating off --
--------------------------------------------------------------------------
ovl_gating_off_gen : if (not gating_on) generate
greset <= reset;
end generate ovl_gating_off_gen;
------------------------------------------------------------------------
-- Inverted reset --
------------------------------------------------------------------------
ovl_reset_active_high_gen : if (reset_polarity_ctrl = OVL_ACTIVE_HIGH) generate
reset_n <= not greset;
end generate ovl_reset_active_high_gen;
------------------------------------------------------------------------
-- Non-inverted reset --
------------------------------------------------------------------------
ovl_reset_active_low_gen : if (reset_polarity_ctrl = OVL_ACTIVE_LOW) generate
reset_n <= greset;
end generate ovl_reset_active_low_gen;
end generate ovl_global_reset_off_gen;
end generate ovl_on_gen;
ovl_off_gen : if ((controls.assert_ctrl = OVL_OFF) and (controls.cover_ctrl = OVL_OFF)) generate
reset_n <= '0';
end generate ovl_off_gen;
end architecture rtl;
| mit | dd3ee15ac598e477fbf4ae62cf15d88e | 0.419894 | 4.754513 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | ProgramaVHDL/LogicaDeCola.vhd | 1 | 5,241 | -----------------------------------------
-- Autores: Vinicius Cerutti e Yuri Bittencourt
-- Disciplina: Organização e arquitetura de Computadores II
-- T1 - Comunicação Serial Periférico-Processador
-- Parte da lógica de cola que tem como objetivo de mapear os
-- endereços do periferico junto com os da mémoria
-----------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FsmLogicaCola is
port(
clock: in std_logic;
reset: in std_logic;
data: inout std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
ce: in std_logic;
rw: in std_logic;
mem_ce : out std_logic;
rx_data: out std_logic_vector (7 downto 0);
rx_start: out std_logic;
rx_busy: in std_logic;
tx_data: in std_logic_vector (7 downto 0);
tx_av: in std_logic
);
end FsmLogicaCola;
architecture FsmLogicaCola of FsmLogicaCola is
type State_type is (a,b,c,d);
signal State_next, State : State_type;
signal ce_Serial : std_logic;
signal auxData : std_logic_vector (31 downto 0);
signal tx_dataReg, rx_dataReg : std_logic_vector (7 downto 0);
signal loadRxDataReg, loadTx_dataReg : std_logic := '0';
signal tx_dado_ja_lido : std_logic := '0';
signal valor_tx_av : std_logic;
begin
ce_Serial <= '1' when (ce='0' and address >= x"10008000" and address <= x"10008004") else '0'; -- chip enable que habilita a escrita e leitura para o periferico
mem_ce <= '1' when (ce_Serial = '1' or ce='1') else '0';
-- Registrador para salvar o valor de rx_data
process (clock,reset)
begin
if (reset = '1') then
rx_dataReg <= x"00";
else if rising_edge(clock) then
if (loadRxDataReg = '1') then
rx_dataReg <= data(7 downto 0);
end if;
end if;
end if;
end process;
-- Registrador para salvar o valor de tx_data
process (clock,reset)
begin
if (reset = '1') then
tx_dataReg <= x"00";
else if rising_edge(clock) then
if (loadTx_dataReg = '1') then
tx_dataReg <= tx_data;
end if;
end if;
end if;
end process;
-- Registrador para salvar o valor de tx_av
-- habilita quando o ciclo de tx_av for igual 1 e desabilita
-- quando aquele dado ja foi lido pela CPU
process (tx_av,reset,tx_dado_ja_lido)
begin
if (reset = '1') then
valor_tx_av <= '0';
elsif(tx_av = '1') then
valor_tx_av <= '1';
elsif (tx_dado_ja_lido = '1') then
valor_tx_av <= '0';
end if;
end process;
process (reset, clock)
begin
if (reset = '1') then
State <= a;
elsif (clock'EVENT and clock = '1') then
State <= State_next;
end if;
end process;
process (State, ce_Serial,rw,rx_busy)
begin
case State is
when a =>
auxData <= x"00000000";
rx_start <= '0';
tx_dado_ja_lido <= '0';
if (ce_Serial ='1') then -- que dizer que não estou mexendo com a memoria e sim com periferico
-- leitura do endereço rx_busy
if (address = x"10008004" and rw = '1') then
if (rx_busy = '0') then
auxData <= x"00000000";
State_next <= b;
else
auxData <= x"00000001";
State_next <= a;
end if;
end if;
-- leitura do endereço tx_av
if (address = x"10008001" and rw = '1') then
if(valor_tx_av = '1') then
auxData <= x"0000000"&"000"&valor_tx_av;
loadTx_dataReg <='1';
State_next <= d;
else
auxData <= x"0000000"&"000"&valor_tx_av;
State_next <= a;
end if;
end if;
else State_next <= a;
end if;
when b =>
-- escrita no endereço rx_data
if (ce_Serial = '1' and address = x"10008002" and rw = '0') then
loadRxDataReg <= '1';
rx_start <= '1';
State_next <= c;
else State_next <= b;
end if;
when c =>
rx_start <='0';
-- verificar se aquele dado foi enviado
loadRxDataReg <= '0';
-- leitura do endereço rx_busy
if (ce_Serial = '1' and address = x"10008004" and rw = '1') then
if (rx_busy = '0') then
auxData <= x"00000000";
State_next <= b;
else
auxData <= x"00000001";
State_next <= c;
end if;
else if (rx_busy = '0') then -- outras instrucoes
State_next <= a;
else
State_next <= c;
end if;
end if;
when d =>
-- Leitura no endereço tx_data
if (ce_Serial = '1' and address = x"10008000" and rw = '1') then
loadTx_dataReg <='0';
-- se o valor de tx_data for negativo
if(tx_dataReg(7) = '1') then
auxData <= x"FFFFFF"&tx_dataReg;
else
auxData <= x"000000"&tx_dataReg;
end if;
tx_dado_ja_lido <= '1';
State_next <= a;
else
State_next <= d;
end if;
when others =>
State_next <= a;
end case;
end process;
rx_data <= rx_dataReg;
data <= auxData when (ce_Serial='1' and rw ='1') else (others=>'Z');
end FsmLogicaCola; | mit | fad0d25904d74a8f7f6f005fd52772ca | 0.543907 | 3.128067 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_1/register_n.vhdl | 1 | 785 | -- register_1
-- An N-bit register.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity register_n is
generic(n: integer);
port(
clk, enable, reset: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0)
);
end entity;
architecture rtl of register_n is
component register_1 is
port(
enable, clk, d, reset: in std_logic;
q: out std_logic
);
end component;
begin
addloop:
for i in 0 to n-1 generate
begin
register_1_instance: register_1 port map(
clk => clk,
d => d(i),
reset => reset,
enable => enable,
q => q(i)
);
end generate;
end architecture;
| unlicense | fbf0c62bf1146b37dd6d5549fa087561 | 0.533758 | 3.617512 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/counter.vhd | 1 | 803 | library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
entity counter is
generic(
clk_period : time;
counter_time : time
);
port(
ctrl : in ctrl_t;
done : out std_logic
);
end;
architecture rtl of counter is
constant count_max : integer := counter_time / clk_period;
signal count : integer range 0 to count_max;
begin
counter_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
count <= 0;
done <= '0';
else
if count < count_max then
count <= count + 1;
done <= '0';
else
count <= 0;
done <= '1';
end if;
end if;
end if;
end process counter_proc;
end;
| bsd-2-clause | c0c193c3b2eaff24ccab0f8b9a3b89c4 | 0.560399 | 3.446352 | false | false | false | false |
willtmwu/vhdlExamples | Moving Averager/fetch_register.vhd | 1 | 1,767 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fetch_register is
Port ( mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
mem_amount : in STD_LOGIC_VECTOR(4 downto 0);
--reg_val_lower : out STD_LOGIC_VECTOR(64 downto 0);
--reg_val_upper : out STD_LOGIC_VECTOR(64 downto 0);
reg_val : out STD_LOGIC_VECTOR(127 downto 0);
masterReset : in STD_LOGIC;
clk : in STD_LOGIC
);
end fetch_register;
architecture Behavioral of fetch_register is
type RAM is array (0 to 63) of integer range 0 to 255;
signal V : RAM := ( 12, 23, 222, 12, 231,42, 56, 121, 78,76,
23, 119, 12, 45, 55,100, 21, 3, 96, 34,
67, 1,1, 54, 133,55, 0, 5, 88, 64,
88, 123, 123, 24, 133,99, 25, 44, 98, 66,
200, 255, 20, 45, 255,255, 255, 255, 255, 54,
1, 251, 49, 234, 77,23, 33, 94, 66, 88,
222,12, 73, 75 );
begin
process (masterReset, clk)
variable address : integer range 0 to 64;
variable temp : std_logic_vector(127 downto 0);
begin
if (masterReset = '1') then
--reg_val_lower <= (others => '0');
--reg_val_upper <= (others => '0');
reg_val <= (others => '0');
elsif (clk'event and clk = '1') then
temp := (others => '0');
for I in 0 to conv_integer( IEEE.std_logic_arith.unsigned(mem_amount-1)) loop
--lowerAddr := 8*I;
--upperAddr := lowerAddr + 7;
address := conv_integer( IEEE.std_logic_arith.unsigned(mem_addr));
temp( (8*I + 7) downto 8*I) := std_logic_vector(IEEE.numeric_std.to_unsigned(V(address + I), 8));
--counter := counter + 1;
end loop;
reg_val <= temp;
end if;
end process;
end Behavioral; | apache-2.0 | 06cab29a73d9e1bdce4ad1a6c2b87d69 | 0.588568 | 2.782677 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/cpu_pack.vhd | 1 | 7,770 | -- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
type op_category is (
INTR,
HALT_WAIT,
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i,
JMP_RRZ_i,
CALL_i,
CALL_RR,
RET,
MOVE_SPi_RR,
MOVE_SPi_RS,
MOVE_SPi_RU,
MOVE_SPi_LL,
MOVE_SPi_LS,
MOVE_SPi_LU,
MOVE_RR_dSP,
MOVE_R_dSP,
-- 1X
AND_RR_i,
OR_RR_i,
XOR_RR_i,
SEQ_RR_i,
SNE_RR_i,
SGE_RR_i,
SGT_RR_i,
SLE_RR_i,
-- 2X
SLT_RR_i,
SHS_RR_i,
SHI_RR_i,
SLS_RR_i,
SLO_RR_i,
CLRW_dSP,
CLRB_dSP,
IN_ci_RU,
OUT_R_ci,
-- 3X
AND_LL_RR,
OR_LL_RR,
XOR_LL_RR,
SEQ_LL_RR,
SNE_LL_RR,
SGE_LL_RR,
SGT_LL_RR,
SLE_LL_RR,
SLT_LL_RR,
SHS_LL_RR,
SHI_LL_RR,
SLS_LL_RR,
SLO_LL_RR,
LNOT_RR,
NEG_RR,
NOT_RR,
-- 4X
MOVE_LL_RR,
MOVE_LL_cRR,
MOVE_L_cRR,
MOVE_RR_LL,
MOVE_RR_cLL,
MOVE_R_cLL,
MOVE_cRR_RR,
MOVE_cRR_RS,
MOVE_cRR_RU,
MOVE_ci_RR,
MOVE_ci_RS,
MOVE_ci_RU,
MOVE_ci_LL,
MOVE_ci_LS,
MOVE_ci_LU,
MOVE_RR_SP,
-- 5X
LSL_RR_i,
ASR_RR_i,
LSR_RR_i,
LSL_LL_RR,
ASR_LL_RR,
LSR_LL_RR,
ADD_LL_RR,
SUB_LL_RR,
MOVE_RR_ci,
MOVE_R_ci,
MOVE_RR_uSP,
MOVE_R_uSP,
-- 6X
MOVE_uSP_RR,
MOVE_uSP_RS,
MOVE_uSP_RU,
MOVE_uSP_LL,
MOVE_uSP_LS,
MOVE_uSP_LU,
LEA_uSP_RR,
MOVE_dRR_dLL,
MOVE_RRi_LLi,
-- 7X
MUL_IS,
MUL_IU,
DIV_IS,
DIV_IU,
MD_STEP,
MD_FIN,
MOD_FIN,
EI,
RETI,
DI,
-- 9X ... FX
ADD_RR_I,
SUB_RR_I,
MOVE_I_RR,
ADD_SP_I,
SEQ_LL_I,
MOVE_I_LL,
undef );
type SP_OP is ( SP_NOP, SP_INC, SP_LOAD );
-- ALU codes
--
constant ALU_X_HS_Y : std_logic_vector(4 downto 0) := "00000";
constant ALU_X_LO_Y : std_logic_vector(4 downto 0) := "00001";
constant ALU_X_HI_Y : std_logic_vector(4 downto 0) := "00010";
constant ALU_X_LS_Y : std_logic_vector(4 downto 0) := "00011";
constant ALU_X_GE_Y : std_logic_vector(4 downto 0) := "00100";
constant ALU_X_LT_Y : std_logic_vector(4 downto 0) := "00101";
constant ALU_X_GT_Y : std_logic_vector(4 downto 0) := "00110";
constant ALU_X_LE_Y : std_logic_vector(4 downto 0) := "00111";
constant ALU_X_EQ_Y : std_logic_vector(4 downto 0) := "01000";
constant ALU_X_NE_Y : std_logic_vector(4 downto 0) := "01001";
constant ALU_NEG_Y : std_logic_vector(4 downto 0) := "01100";
constant ALU_X_SUB_Y : std_logic_vector(4 downto 0) := "01101";
constant ALU_MOVE_Y : std_logic_vector(4 downto 0) := "01110";
constant ALU_X_ADD_Y : std_logic_vector(4 downto 0) := "01111";
constant ALU_X_AND_Y : std_logic_vector(4 downto 0) := "10000";
constant ALU_X_OR_Y : std_logic_vector(4 downto 0) := "10001";
constant ALU_X_XOR_Y : std_logic_vector(4 downto 0) := "10010";
constant ALU_NOT_Y : std_logic_vector(4 downto 0) := "10011";
constant ALU_X_LSR_Y : std_logic_vector(4 downto 0) := "10100";
constant ALU_X_ASR_Y : std_logic_vector(4 downto 0) := "10101";
constant ALU_X_LSL_Y : std_logic_vector(4 downto 0) := "10110";
constant ALU_X_MIX_Y : std_logic_vector(4 downto 0) := "10111";
constant ALU_MUL_IU : std_logic_vector(4 downto 0) := "11000";
constant ALU_MUL_IS : std_logic_vector(4 downto 0) := "11001";
constant ALU_DIV_IU : std_logic_vector(4 downto 0) := "11010";
constant ALU_DIV_IS : std_logic_vector(4 downto 0) := "11011";
constant ALU_MD_STP : std_logic_vector(4 downto 0) := "11100";
constant ALU_MD_FIN : std_logic_vector(4 downto 0) := "11101";
constant ALU_MOD_FIN : std_logic_vector(4 downto 0) := "11110";
constant ALU_ANY : std_logic_vector(4 downto 0) := ALU_X_AND_Y;
--------------------------------------------------------------
constant SA_43_0 : std_logic_vector(1 downto 0) := "00";
constant SA_43_FFFF : std_logic_vector(1 downto 0) := "01"; -- last bit 1 !!!
constant SA_43_I16 : std_logic_vector(1 downto 0) := "10";
constant SA_43_I8S : std_logic_vector(1 downto 0) := "11";
constant SA_21_0 : std_logic_vector(1 downto 0) := "00";
constant SA_21_LL : std_logic_vector(1 downto 0) := "01";
constant SA_21_RR : std_logic_vector(1 downto 0) := "10";
constant SA_21_SP : std_logic_vector(1 downto 0) := "11";
constant ADR_cSP_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '0';
constant ADR_cRR_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '0';
constant ADR_cLL_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '0';
constant ADR_cI16_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '0';
constant ADR_16SP_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '0';
constant ADR_8SP_L : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '0';
constant ADR_IO : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_0 & '0';
constant ADR_cSP_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '1';
constant ADR_cRR_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '1';
constant ADR_cLL_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '1';
constant ADR_cI16_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '1';
constant ADR_16SP_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '1';
constant ADR_8SP_H : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '1';
constant ADR_dSP : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '0';
constant ADR_dRR : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_RR & '0';
constant ADR_dLL : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_LL & '0';
constant ADR_SPi : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '1';
constant ADR_RRi : std_logic_vector(4 downto 0) := ADR_cRR_L;
constant ADR_LLi : std_logic_vector(4 downto 0) := ADR_cLL_L;
--------------------------------------------------------------
constant SX_LL : std_logic_vector(1 downto 0) := "00";
constant SX_RR : std_logic_vector(1 downto 0) := "01";
constant SX_SP : std_logic_vector(1 downto 0) := "10";
constant SX_PC : std_logic_vector(1 downto 0) := "11";
constant SX_ANY : std_logic_vector(1 downto 0) := SX_RR;
--------------------------------------------------------------
constant SY_SY0 : std_logic_vector(3 downto 0) := "0000";
constant SY_SY1 : std_logic_vector(3 downto 0) := "0001";
constant SY_SY2 : std_logic_vector(3 downto 0) := "0010";
constant SY_SY3 : std_logic_vector(3 downto 0) := "0011";
constant SY_I16 : std_logic_vector(3 downto 0) := "0100";
constant SY_RR : std_logic_vector(3 downto 0) := "0101";
constant SY_SI8 : std_logic_vector(3 downto 0) := "1000";
constant SY_UI8 : std_logic_vector(3 downto 0) := "1001";
constant SY_SQ : std_logic_vector(3 downto 0) := "1010";
constant SY_UQ : std_logic_vector(3 downto 0) := "1011";
constant SY_SM : std_logic_vector(3 downto 0) := "1100";
constant SY_UM : std_logic_vector(3 downto 0) := "1101";
constant SY_IO : std_logic_vector(3 downto 0) := "1110";
constant SY_ANY : std_logic_vector(3 downto 0) := SY_RR;
--------------------------------------------------------------
constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- count up
constant PC_JMP : std_logic_vector(2 downto 0) := "001"; -- JMP/CALL
constant PC_RETH : std_logic_vector(2 downto 0) := "010"; -- RET (H)
constant PC_RETL : std_logic_vector(2 downto 0) := "011"; -- RET (L)
constant PC_WAIT : std_logic_vector(2 downto 0) := "100"; -- WAIT
constant PC_JPRR : std_logic_vector(2 downto 0) := "101"; -- JMP (RR)
constant PC_INT : std_logic_vector(2 downto 0) := "110"; -- INT
--------------------------------------------------------------
end cpu_pack;
package body cpu_pack is
end cpu_pack;
| mit | f91db8cf74918e75f17b9e228ea71f8d | 0.585714 | 2.398889 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/sinewave/sine_rom_tb.vhd | 1 | 930 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
-- Used only for midi_note_t and midi_note_arr_t
use virtual_button_lib.midi_pkg.all;
entity sine_rom_tb is
end;
architecture behavioural of sine_rom_tb is
signal ctrl : ctrl_t;
signal midi_nos : midi_note_arr_t := (60, 80);
signal pcm_out : signed(15 downto 0);
signal new_pcm_out : std_logic;
begin
clk_proc : process is
begin
ctrl.clk <= '0';
wait for 1 ns;
ctrl.clk <= '1';
wait for 1 ns;
end process;
many_sines_1 : entity work.many_sines
port map (
ctrl => ctrl,
midi_nos => midi_nos,
pcm_out => pcm_out,
new_pcm_out => new_pcm_out);
tb : process
begin
ctrl.reset_n <= '0';
wait for 1 us;
ctrl.reset_n <= '1';
wait;
end process tb;
end;
| bsd-2-clause | bf2c6685886873a0c76867cf02720d0f | 0.616129 | 2.961783 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/opcode_decoder.vhd | 1 | 32,122 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle;
INT : IN std_logic;
RRZ : IN std_logic;
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_M : out std_logic;
D_WE_SP : out SP_OP;
-- input/output
IO_RD : out std_logic;
IO_WR : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal SERVE_INT : std_logic;
signal INT_ACK : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_ACK <= '0';
HALTED <= '0';
elsif (CE = '1') then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_ACK <= SERVE_INT;
end if;
end if;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_ACK, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_M <= '0';
D_WE_SP <= SP_NOP;
IO_RD <= '0';
IO_WR <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
SERVE_INT <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_ACK = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
SERVE_INT <= IS_M1; -- assert INT_ACK in M2
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_INT);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= '1';
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M2, PC_JMP);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_JPRR);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= '1';
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
D_WE_M <= IS_M1_M2;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= '1';
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= '1';
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= IS_M1;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_IO;
D_SA <= ADR_IO;
IO_RD <= IS_M2;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
IO_WR <= IS_M2;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_SMQ <= IS_M2;
D_WE_M <= IS_M1_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_M <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_SMQ <= IS_M2;
D_WE_M <= IS_M1_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_M <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= not IS_M1; -- M2 or M3
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M2;
D_SA <= ADR_cI16_L;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= not IS_M1;
D_SMQ <= IS_M3;
D_SA <= hadr(IS_M3, ADR_16SP_H);
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M2;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M2;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M1;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_16SP_H);
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_WE_RR <= IS_M2_M3;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_LL <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_8SP_H);
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_WE_LL <= IS_M2_M3;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_WE_M <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_WE_M <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= '1';
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= '1';
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
| mit | 4a1a6fe610ef60c03774c1811ea86183 | 0.424071 | 2.245509 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/select_yy.vhd | 1 | 3,085 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity select_yy is
Port( SY : in std_logic_vector( 3 downto 0);
IMM : in std_logic_vector(15 downto 0);
QUICK : in std_logic_vector( 3 downto 0);
M_RDAT : in std_logic_vector( 7 downto 0);
IO_RDAT : in std_logic_vector( 7 downto 0);
RR : in std_logic_vector(15 downto 0);
YY : out std_logic_vector(15 downto 0)
);
end select_yy;
architecture Behavioral of select_yy is
function b4(A : std_logic) return std_logic_vector is
begin
return A & A & A & A;
end;
function b8(A : std_logic) return std_logic_vector is
begin
return b4(A) & b4(A);
end;
begin
-- bits 1..0
--
s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), M_RDAT(1 downto 0),
IO_RDAT(1 downto 0), RR(1 downto 0))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0);
when SY_RR => YY(1 downto 0) <= RR (1 downto 0);
when SY_SQ | SY_UQ => YY(1 downto 0) <= QUICK (1 downto 0);
when SY_SM | SY_UM => YY(1 downto 0) <= M_RDAT (1 downto 0);
when SY_IO => YY(1 downto 0) <= IO_RDAT(1 downto 0);
when others => YY(1 downto 0) <= SY (1 downto 0);
end case;
end process;
-- bits 3..2
--
s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), M_RDAT(3 downto 2),
IO_RDAT(3 downto 2), RR(3 downto 2))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2);
when SY_RR => YY(3 downto 2) <= RR (3 downto 2);
when SY_SQ | SY_UQ => YY(3 downto 2) <= QUICK (3 downto 2);
when SY_SM | SY_UM => YY(3 downto 2) <= M_RDAT (3 downto 2);
when SY_IO => YY(3 downto 2) <= IO_RDAT(3 downto 2);
when others => YY(3 downto 2) <= "00";
end case;
end process;
-- bits 7..4
--
s_7_4: process(SY, IMM(7 downto 4), QUICK(3), M_RDAT(7 downto 4),
IO_RDAT(7 downto 4), RR(7 downto 4))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4);
when SY_RR => YY(7 downto 4) <= RR (7 downto 4);
when SY_SQ => YY(7 downto 4) <= b4(QUICK(3));
when SY_SM | SY_UM => YY(7 downto 4) <= M_RDAT (7 downto 4);
when SY_IO => YY(7 downto 4) <= IO_RDAT(7 downto 4);
when others => YY(7 downto 4) <= "0000";
end case;
end process;
-- bits 15..8
--
s_15_8: process(SY, IMM(15 downto 7), QUICK(3), M_RDAT(7), RR(15 downto 8))
begin
case SY is
when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8);
when SY_SI8 => YY(15 downto 8) <= b8(IMM(7));
when SY_RR => YY(15 downto 8) <= RR(15 downto 8);
when SY_SQ => YY(15 downto 8) <= b8(QUICK(3));
when SY_SM => YY(15 downto 8) <= b8(M_RDAT(7));
when others => YY(15 downto 8) <= "00000000";
end case;
end process;
end Behavioral;
| mit | cae172e24afb72cc78228cc04ec9363c | 0.580227 | 2.520425 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_3/memory256x8.vhdl | 1 | 1,155 |
----------------------------------------------------------------------
--- A synchronous memory
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity memory256x8 is
port (
ck : in std_logic;
we : in std_logic; -- write enable
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end entity memory256x8;
architecture rtl of memory256x8 is
type ram_array is array (0 to 255) of std_logic_vector(7 downto 0);
-- this ram has its first two bytes initialized, you may add more
signal ram : ram_array := (
x"20", x"21", x"22", x"23", x"24", x"7F", x"01",
others => x"00");
begin
ram_process: process(ck) is
begin
if rising_edge(ck) then
-- note that the two following statements are sequential
if we = '1' then -- write enable
ram(to_integer(unsigned(address))) <= datain;
end if;
dataout <= ram(to_integer(unsigned(address)));
end if;
end process ram_process;
end architecture rtl;
| unlicense | 281564bef63c913ef4bf8c3eab7b5882 | 0.561039 | 3.678344 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/memory.vhd | 2 | 14,095 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
use work.mem_content.All;
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
architecture Behavioral of memory is
signal ENA : std_logic;
signal ENB : std_logic;
signal WR_0 : std_logic;
signal WR_1 : std_logic;
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
begin
ENA <= CE and not T2;
ENB <= CE and T2;
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
process(CLK_I) -- new
begin
if (rising_edge(CLK_I) and T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end process;
process(LADR, OUT_0, OUT_1)
begin
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
end process;
process(CLK_I)
begin
if (rising_edge(CLK_I) and T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end process;
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
end Behavioral;
| mit | ce92e88611860dd657f697d2bc4912b0 | 0.495069 | 2.057965 | false | false | false | false |
rkrajnc/minimig-de1 | rtl/tg68k/TG68K_ALU.vhd | 2 | 32,041 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.TG68K_Pack.all;
entity TG68K_ALU is
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : bit;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : bit;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
-- signal in_width : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
-- signal bf_result : std_logic_vector(31 downto 0);
-- signal bf_offset : std_logic_vector(5 downto 0);
-- signal bf_width : std_logic_vector(5 downto 0);
-- signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
-- signal bf_out : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_set1 : std_logic_vector(39 downto 0);
signal inmux0 : std_logic_vector(39 downto 0);
signal inmux1 : std_logic_vector(39 downto 0);
signal inmux2 : std_logic_vector(39 downto 0);
signal inmux3 : std_logic_vector(31 downto 0);
signal copymux0 : std_logic_vector(39 downto 0);
signal copymux1 : std_logic_vector(39 downto 0);
signal copymux2 : std_logic_vector(39 downto 0);
signal copymux3 : std_logic_vector(31 downto 0);
signal bf_set2 : std_logic_vector(31 downto 0);
-- signal bf_set3 : std_logic_vector(31 downto 0);
signal shift : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
-- signal offset : std_logic_vector(5 downto 0);
-- signal width : std_logic_vector(5 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal mux : std_logic_vector(3 downto 0);
signal bitnr : std_logic_vector(4 downto 0);
signal mask : std_logic_vector(31 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal bf_s32 : std_logic;
signal index : std_logic_vector(4 downto 0);
-- signal i : integer range 0 to 31;
-- signal i : integer range 0 to 31;
-- signal i : std_logic_vector(5 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
BEGIN
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
IF exec(opcBFwb)='1' THEN
ALUout <= result(31 downto 0);
IF bf_fffo='1' THEN
ALUout <= (OTHERS =>'0');
ALUout(5 downto 0) <= bf_firstbit + bf_shift;
END IF;
END IF;
OP1in <= addsub_q;
IF exec(opcABCD)='1' THEN
OP1in(7 downto 0) <= bcd_a(7 downto 0);
ELSIF exec(opcSBCD)='1' THEN
OP1in(7 downto 0) <= bcd_s(7 downto 0);
ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
OP1in <= result_mulu(31 downto 0);
ELSE
OP1in <= result_mulu(63 downto 32);
END IF;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
-- IF exe_opcode(15)='1' THEN
OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
ELSE --64bit
IF exec(write_reminder)='1' THEN
OP1in <= result_div(63 downto 32);
ELSE
OP1in <= result_div(31 downto 0);
END IF;
END IF;
ELSIF exec(opcOR)='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec(opcAND)='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec(opcScc)='1' THEN
OP1in(7 downto 0) <= (others=>exe_condition);
ELSIF exec(opcEOR)='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
ELSIF exec(opcROT)='1' THEN
OP1in <= rot_out;
ELSIF exec(opcSWAP)='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec(opcBITS)='1' THEN
OP1in <= bits_out;
ELSIF exec(opcBF)='1' THEN
OP1in <= bf_datareg;
ELSIF exec(opcMOVESR)='1' THEN
OP1in(7 downto 0) <= Flags;
IF exe_datatype="00" THEN
OP1in(15 downto 8) <= "00000000";
ELSE
OP1in(15 downto 8) <= FlagsSR;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
BEGIN
addsub_a <= OP1out;
IF exec(get_bfoffset)='1' THEN
IF sndOPC(11)='1' THEN
addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
ELSE
addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
END IF;
END IF;
IF exec(subidx)='1' THEN
opaddsub <= '1';
ELSE
opaddsub <= '0';
END IF;
c_in(0) <='0';
addsub_b <= OP2out;
IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
IF exec(movem_action)='1' THEN
addsub_b <= "00000000000000000000000000000110";
ELSE
addsub_b <= "00000000000000000000000000000100";
END IF;
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
c_in(0) <= '1';
END IF;
opaddsub <= exec(addsub);
END IF;
IF opaddsub='0' OR long_start='1' THEN --ADD
notaddsub_b <= '0'&addsub_b&c_in(0);
ELSE --SUB
notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
END IF;
add_result <= (('0'&addsub_a¬addsub_b(0))+notaddsub_b);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (OP1out, OP2out, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
bcd_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC, reg_QB)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bchg <= '0';
bset <= '0';
CASE opcode(7 downto 6) IS
WHEN "01" => --bchg
bchg <= '1';
WHEN "11" => --bset
bset <= '1';
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
IF exe_opcode(8)='0' THEN
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= sndOPC(4 downto 0);
ELSE
bit_number <= "00"&sndOPC(2 downto 0);
END IF;
ELSE
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= reg_QB(4 downto 0);
ELSE
bit_number <= "00"®_QB(2 downto 0);
END IF;
END IF;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
END PROCESS;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
bf_s32 <= '0';
CASE opcode(10 downto 8) IS
WHEN "010" => bf_bchg <= '1'; --BFCHG
WHEN "011" => bf_exts <= '1'; --BFEXTS
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
WHEN "101" => bf_fffo <= '1'; --BFFFO
WHEN "110" => bf_bset <= '1'; --BFSET
WHEN "111" => bf_ins <= '1'; --BFINS
bf_s32 <= '1';
WHEN OTHERS => NULL;
END CASE;
IF opcode(4 downto 3)="00" THEN
bf_d32 <= '1';
END IF;
bf_ext_out <= result(39 downto 32);
END IF;
END IF;
shift <= bf_ext_in&OP2out;
IF bf_s32='1' THEN
shift(39 downto 32) <= OP2out(7 downto 0);
END IF;
IF bf_shift(0)='1' THEN
inmux0 <= shift(0)&shift(39 downto 1);
ELSE
inmux0 <= shift;
END IF;
IF bf_shift(1)='1' THEN
inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
ELSE
inmux1 <= inmux0;
END IF;
IF bf_shift(2)='1' THEN
inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
ELSE
inmux2 <= inmux1;
END IF;
IF bf_shift(3)='1' THEN
inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
ELSE
inmux3 <= inmux2(31 downto 0);
END IF;
IF bf_shift(4)='1' THEN
bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
ELSE
bf_set2(31 downto 0) <= inmux3;
END IF;
IF bf_loffset(4)='1' THEN
copymux3 <= sign(15 downto 0)&sign(31 downto 16);
ELSE
copymux3 <= sign;
END IF;
IF bf_loffset(3)='1' THEN
copymux2(31 downto 0) <= copymux3(23 downto 0)©mux3(31 downto 24);
ELSE
copymux2(31 downto 0) <= copymux3;
END IF;
IF bf_d32='1' THEN
copymux2(39 downto 32) <= copymux3(7 downto 0);
ELSE
copymux2(39 downto 32) <= "11111111";
END IF;
IF bf_loffset(2)='1' THEN
copymux1 <= copymux2(35 downto 0)©mux2(39 downto 36);
ELSE
copymux1 <= copymux2;
END IF;
IF bf_loffset(1)='1' THEN
copymux0 <= copymux1(37 downto 0)©mux1(39 downto 38);
ELSE
copymux0 <= copymux1;
END IF;
IF bf_loffset(0)='1' THEN
copy <= copymux0(38 downto 0)©mux0(39);
ELSE
copy <= copymux0;
END IF;
result_tmp <= bf_ext_in&OP1out;
IF bf_ins='1' THEN
datareg <= reg_QB;
ELSE
datareg <= bf_set2;
END IF;
IF bf_ins='1' THEN
result(31 downto 0) <= bf_set2;
result(39 downto 32) <= bf_set2(7 downto 0);
ELSIF bf_bchg='1' THEN
result(31 downto 0) <= NOT OP1out;
result(39 downto 32) <= NOT bf_ext_in;
ELSE
result <= (OTHERS => '0');
END IF;
IF bf_bset='1' THEN
result <= (OTHERS => '1');
END IF;
sign <= (OTHERS => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
FOR i in 0 to 31 LOOP
IF i>bf_width(4 downto 0) THEN
datareg(i) <= '0';
sign(i) <= '1';
END IF;
END LOOP;
FOR i in 0 to 39 LOOP
IF copy(i)='1' THEN
result(i) <= result_tmp(i);
END IF;
END LOOP;
IF bf_exts='1' AND bf_NFlag='1' THEN
bf_datareg <= datareg OR sign;
ELSE
bf_datareg <= datareg;
END IF;
-- bf_datareg <= copy(31 downto 0);
-- result(31 downto 0)<=datareg;
--BFFFO
mask <= datareg;
bf_firstbit <= '0'&bitnr;
bitnr <= "11111";
IF mask(31 downto 28)="0000" THEN
IF mask(27 downto 24)="0000" THEN
IF mask(23 downto 20)="0000" THEN
IF mask(19 downto 16)="0000" THEN
bitnr(4) <= '0';
IF mask(15 downto 12)="0000" THEN
IF mask(11 downto 8)="0000" THEN
bitnr(3) <= '0';
IF mask(7 downto 4)="0000" THEN
bitnr(2) <= '0';
mux <= mask(3 downto 0);
ELSE
mux <= mask(7 downto 4);
END IF;
ELSE
mux <= mask(11 downto 8);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(15 downto 12);
END IF;
ELSE
mux <= mask(19 downto 16);
bitnr(3) <= '0';
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(23 downto 20);
bitnr(3) <= '0';
END IF;
ELSE
mux <= mask(27 downto 24);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(31 downto 28);
END IF;
IF mux(3 downto 2)="00" THEN
bitnr(1) <= '0';
IF mux(1)='0' THEN
bitnr(0) <= '0';
END IF;
ELSE
IF mux(3)='0' THEN
bitnr(0) <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
BEGIN
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => NULL;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => NULL;
END CASE;
IF exec(rot_nop)='1' THEN
rot_out <= OP1out;
rot_X <= Flags(4);
IF rot_bits="10" THEN --ROXL, ROXR
rot_C <= Flags(4);
ELSE
rot_C <= '0';
END IF;
ELSE
IF exe_opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
ELSE --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
BEGIN
IF exec(andiSR)='1' THEN
CCRin <= Flags AND last_data_read(7 downto 0);
ELSIF exec(eoriSR)='1' THEN
CCRin <= Flags XOR last_data_read(7 downto 0);
ELSIF exec(oriSR)='1' THEN
CCRin <= Flags OR last_data_read(7 downto 0);
ELSE
CCRin <= OP2out(7 downto 0);
END IF;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF exe_datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec(opcABCD)='1' THEN
set_flags(0) <= bcd_a(8);
ELSIF exec(opcSBCD)='1' THEN
set_flags(0) <= bcd_s(8);
END IF;
ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
IF exec(directSR)='1' OR set_stop='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(directCCR)='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(opcROT)='1' THEN
asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
ELSE
asl_VFlag <= '0';
END IF;
IF exec(to_CCR)='1' THEN
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
ELSIF Z_error='1' THEN
IF exe_opcode(8)='0' THEN
Flags(3 downto 0) <= reg_QA(31)&"000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF exec(no_Flags)='0' THEN
IF exec(opcADD)='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
Flags(4) <= rot_X;
END IF;
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) AND Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
IF exec(opcBF)='1' THEN
Flags(3) <= bf_NFlag;
END IF;
ELSIF exec(opcROT)='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN --ASL/ASR
Flags(1) <= '1';
ELSE
Flags(1) <= '0';
END IF;
ELSIF exec(opcBITS)='1' THEN
Flags(2) <= NOT one_bit_in;
ELSIF exec(opcCHK)='1' THEN
IF exe_datatype="01" THEN --Word
Flags(3) <= OP1out(15);
ELSE
Flags(3) <= OP1out(31);
END IF;
IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
Flags(2) <='1';
ELSE
Flags(2) <='0';
END IF;
Flags(1 downto 0) <= "00";
END IF;
END IF;
END IF;
Flags(7 downto 5) <= "000";
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
BEGIN
IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
muls_msb <= mulu_reg(63);
ELSE
muls_msb <= '0';
END IF;
IF signedOP='1' AND faktorB(31)='1' THEN
mulu_sign <= '1';
ELSE
mulu_sign <= '0';
END IF;
IF MUL_Mode=0 THEN -- 16 Bit
result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));
ELSE
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));
END IF;
END IF;
ELSE -- 32 Bit
result_mulu <= muls_msb&mulu_reg(63 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));
ELSE
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));
END IF;
END IF;
END IF;
IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (OTHERS=>'0');
ELSE
faktorB <= OP2out;
END IF;
IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
set_mV_Flag <= '0';
ELSE
set_mV_Flag <= '1';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
IF micro_state=mul1 THEN
mulu_reg(63 downto 32) <= (OTHERS=>'0');
IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0-reg_QA;
ELSE
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
END IF;
ELSIF exec(opcMULU)='0' THEN
mulu_reg <= result_mulu;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
BEGIN
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
divisor(15 downto 0) <= (OTHERS=> '0');
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
divisor(47 downto 16) <= reg_QA;
ELSE
divisor(31 downto 0) <= reg_QA;
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
divisor(63 downto 32) <= reg_QB;
END IF;
END IF;
IF signedOP='1' OR opcode(15)='0' THEN
OP2outext <= OP2out(31 downto 16);
ELSE
OP2outext <= (OTHERS=> '0');
END IF;
IF signedOP='1' AND OP2out(31) ='1' THEN
div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
ELSE
div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
END IF;
IF DIV_Mode=0 THEN
div_bit <= div_sub(16);
ELSE
div_bit <= div_sub(32);
END IF;
IF div_bit='1' THEN
div_quot(63 downto 32) <= div_reg(62 downto 31);
ELSE
div_quot(63 downto 32) <= div_sub(31 downto 0);
END IF;
div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' ) --Overflow DIVS
OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN --Overflow DIVU
set_V_Flag <= '1';
ELSE
set_V_Flag <= '0';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
V_Flag <= set_V_Flag;
signedOP <= divs;
IF micro_state=div1 THEN
nozero <= '0';
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
OP1_sign <= '1';
div_reg <= 0-divisor;
ELSE
OP1_sign <= '0';
div_reg <= divisor;
END IF;
ELSE
div_reg <= div_quot;
nozero <= NOT div_bit OR nozero;
END IF;
IF micro_state=div2 THEN
div_qsign <= NOT div_bit;
div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
IF DIV_Mode=0 THEN
div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
ELSE
div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
END IF;
END IF;
IF exec(write_reminder)='0' THEN
-- IF exec_DIVU='0' THEN
IF div_neg='1' THEN
result_div(31 downto 0) <= 0-div_quot(31 downto 0);
ELSE
result_div(31 downto 0) <= div_quot(31 downto 0);
END IF;
IF OP1_sign='1' THEN
result_div(63 downto 32) <= 0-div_quot(63 downto 32);
ELSE
result_div(63 downto 32) <= div_quot(63 downto 32);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
| gpl-3.0 | e90975af22fd9375d8729892657dd50c | 0.522736 | 3.010241 | false | false | false | false |
willtmwu/vhdlExamples | Finite State Machines/hardware_tester_fsm.vhd | 1 | 4,151 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_tester_fsm is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_tester_fsm;
architecture Behavioral of hardware_tester_fsm is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component fsm_prac4 PORT (
X : IN STD_LOGIC;
RESET : IN STD_LOGIC;
clk100mhz : IN STD_LOGIC;
Z : OUT STD_LOGIC;
DEBUG_CHECK : OUT STD_LOGIC_VECTOR(3 downto 0);
DEBUG_OUT : OUT STD_LOGIC_VECTOR(3 downto 0));
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal displayKey : std_logic_vector(15 downto 0);
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
signal X,RESET,Z : std_logic;
signal DEBUG_CHECK, DEBUG_OUT : std_logic_vector (3 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
signal shift_pattern : std_logic_vector (15 downto 0) := (others => '0');
--signal counting_vect : std_logic_vector (3 downto 0) := (others => '0');
begin
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : fsm_prac4 port map (X, RESET, clockScalers(11), Z, DEBUG_CHECK, DEBUG_OUT);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer(0) <= Z;
--logic_analyzer(1) <= X;
logic_analyzer(2) <= clk100mHz;
logic_analyzer(3) <= clockScalers(11);
logic_analyzer(7 downto 4) <= DEBUG_CHECK;
--RESET <= NOT(masterReset);
RESET <= '1';
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
displayKey <= shift_pattern;
process(masterReset, clockScalers(11), button1) begin
if (masterReset = '1') then
shift_pattern <= (others => '0');
elsif (clockScalers(11)'event and clockScalers(11) = '1') then
if (button1 = '1') then
shift_pattern <= slideSwitches;
end if;
end if;
end process;
process (clockScalers(11))
--variable counter : counter_bit_int := 15;
variable counting_vect : integer := 0;
begin
--wait until submitButton'event and submitButton = '1' ;
if (clockScalers(11)'event and clockScalers(11) = '1') then
if (counting_vect >= 0) then
X <= shift_pattern(counting_vect);
logic_analyzer(1) <= shift_pattern(counting_vect);
counting_vect := counting_vect - 1;
else
counting_vect := 15;
end if;
end if;
end process;
end Behavioral; | apache-2.0 | a1b27e5bc0c203d62c8173c58f8d7ba0 | 0.652614 | 2.941885 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/spi_accel.vhd | 1 | 7,324 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity spi_accel is
Port ( clk100MHz : in STD_LOGIC;
masterReset : in STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
READY : inout STD_LOGIC;
X_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Y_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Z_VAL : out STD_LOGIC_VECTOR(7 downto 0));
end spi_accel;
architecture Behavioral of spi_accel is
constant READ_CMD : std_logic_vector (7 downto 0) := x"0B";
constant WRITE_CMD : std_logic_vector (7 downto 0) := x"0A";
constant POWER_CTL_REG : std_logic_vector (7 downto 0) := x"2D";
constant POWER_CTL_VAL : std_logic_vector (7 downto 0) := x"02";
--"01000000";
--"01010000"
--Can use burst read
constant X_REG : std_logic_vector (7 downto 0) := x"08";
signal X_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
constant Y_REG : std_logic_vector (7 downto 0) := x"09";
signal Y_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
constant Z_REG : std_logic_vector (7 downto 0) := x"0A";
signal Z_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
--signal CS : std_logic := '1';
--signal MOSI : std_logic := '0';
--signal MISO : std_logic := '0';
--Initialise Finished -> READY
--signal READY : std_logic := '0';
signal byteCounter : integer range 0 to 7 := 7;
signal byteCounter_delayed : integer range 0 to 7 := 0;
--Intialiser FSM
type SPI_FSM is (CMD, PWR_REG, VAL, DONE, CMD_R, ACC_REG, VAL_ACC, IDLE);
signal SPI_STATE : SPI_FSM := CMD;
signal SPI_STATE_DEBUG : SPI_FSM := CMD;
--Burst Read Accel FSM
type BURST_FSM is (X_VAL_S, Y_VAL_S, Z_VAL_S);
signal BURST_STATE : BURST_FSM := X_VAL_S;
signal BURST_STATE_DEBUG : BURST_FSM := X_VAL_S;
--Clk Scaled Signals
signal clk3Hz : std_logic := '0';
signal clk1MHz : std_logic := '0';
signal clockScalers : std_logic_vector (26 downto 0) := (others => '0');
--Edge Detector
signal clkEdge : std_logic := '0';
type DETECT_FSM is (WAITING, DELAY1, DELAY2);
signal DETECT_STATE : DETECT_FSM := WAITING;
BEGIN
--1MHz Scalar SPI SCLK
--process (masterReset,clk100Mhz)
-- variable wdCounter : std_logic_vector (7 downto 0) := (others => '0');
-- begin
-- if (masterReset = '1') then
-- wdCounter := "00000000";
-- elsif (clk100Mhz'event and clk100Mhz = '1') then
-- wdCounter := wdCounter + '1';
-- if (wdCounter = "00000111") then
-- clk1Mhz <= not(clk1Mhz);
-- wdCounter := "00000000";
-- end if;
-- end if;
--end process;
--300ms watchdog timer
process (masterReset, clk1Mhz)
--Falling edge detector
begin
if (masterReset = '1') then
clk3Hz <= '0';
clkEdge <= '0';
DETECT_STATE <= WAITING;
elsif ( clk1Mhz'event and clk1Mhz = '0') then
if(clkEdge = '1' and clockScalers(24) = '0') then
DETECT_STATE <= DELAY1;
clk3Hz <= '1';
else
case DETECT_STATE is
when DELAY1 => DETECT_STATE <= DELAY2;
when DELAY2 =>
if (READY = '0') then
DETECT_STATE <= WAITING;
end if;
when WAITING =>
clk3Hz <= '0';
end case;
end if;
clkEdge <= clockScalers(24);
end if;
end process;
process (clk100Mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
clk1Mhz <= clockScalers(5);
--SCLK <= not(clk1Mhz);
SCLK <= (clk1Mhz);
READY <= '1' when ( (SPI_STATE_DEBUG = IDLE) or (SPI_STATE_DEBUG = DONE) ) else '0';
X_VAL <= X_VAL_R;
Y_VAL <= Y_VAL_R;
Z_VAL <= Z_VAL_R;
--SPI FSM LOOP
process (masterReset, clk1Mhz) begin
if (masterReset = '1') then
CS <= '1';
SPI_STATE <= CMD;
BURST_STATE <= X_VAL_S;
byteCounter <= 7;
X_VAL_R <= (others => '0');
Y_VAL_R <= (others => '0');
Z_VAL_R <= (others => '0');
elsif (clk1Mhz'event and clk1Mhz = '0') then
--FSM Sent Data loop
case SPI_STATE is
when CMD =>
CS <= '0';
MOSI <= WRITE_CMD(byteCounter);
when PWR_REG =>
CS <= '0';
MOSI <= POWER_CTL_REG(byteCounter);
when VAL =>
CS <= '0';
MOSI <= POWER_CTL_VAL(byteCounter);
when CMD_R =>
CS <= '0';
MOSI <= READ_CMD(byteCounter);
when ACC_REG =>
CS <= '0';
MOSI <= X_REG(byteCounter);
when VAL_ACC =>
CS <= '0';
MOSI <= '1';
--Burst FSM Read/Load
case BURST_STATE_DEBUG is
when X_VAl_S =>
--X_VAL_R(byteCounter) <= MISO;
X_VAL_R(byteCounter_delayed) <= MISO;
when Y_VAl_S =>
--Y_VAL_R(byteCounter) <= MISO;
Y_VAL_R(byteCounter_delayed) <= MISO;
when Z_VAl_S =>
--Z_VAL_R(byteCounter) <= MISO;
Z_VAL_R(byteCounter_delayed) <= MISO;
end case;
when others =>
if (BURST_STATE_DEBUG = Z_VAL_S) then
Z_VAL_R(0) <= MISO;
end if;
CS <= '1';
MOSI <= '0';
end case;
if (byteCounter = 0) then
--Secondary FSM Switch/Transition Loop
case SPI_STATE is
when CMD => SPI_STATE <= PWR_REG;
when PWR_REG => SPI_STATE <= VAL;
when VAL => SPI_STATE <= DONE;
when DONE =>
cs <= '1';
if (clk3Hz = '1') then
SPI_STATE <= CMD_R;
end if;
when CMD_R => SPI_STATE <= ACC_REG;
when ACC_REG => SPI_STATE <= VAL_ACC;
when VAL_ACC =>
--Only Transition on Burst FSM
if (BURST_STATE = Z_VAL_S) then
SPI_STATE <= IDLE;
end if;
case BURST_STATE is
when X_VAl_S => BURST_STATE <= Y_VAL_S;
when Y_VAl_S => BURST_STATE <= Z_VAL_S;
when Z_VAl_S => BURST_STATE <= X_VAL_S;
end case;
when IDLE =>
cs <= '1';
if (clk3Hz = '1') then
SPI_STATE <= CMD_R;
end if;
end case;
byteCounter <= 7;
else
byteCounter <= byteCounter - 1;
end if;
end if;
end process;
--Delayed Clock
process (masterReset, clk1Mhz) begin
if (masterReset = '1') then
byteCounter_delayed <= 0;
SPI_STATE_DEBUG <= CMD;
BURST_STATE_DEBUG <= X_VAL_S;
elsif (clk1Mhz'event and clk1Mhz = '0') then
byteCounter_delayed <= byteCounter;
SPI_STATE_DEBUG <= SPI_STATE;
BURST_STATE_DEBUG <= BURST_STATE;
end if;
end process;
END Behavioral;
| apache-2.0 | 94fb6d7dae9b3df1c95d18d9591c9fad | 0.505598 | 3.375115 | false | false | false | false |
scarter93/RSA-Encryption | montgomery_comparison.vhd | 1 | 3,644 | -- Entity name: montgomery_comparison
-- Author: Luis Gallet, Jacob Barnett
-- Contact: [email protected], [email protected]
-- Date: March 28th, 2016
-- Description:
-- This module performs (A x B) mod n, which emulates the functionality of
-- montgomery_multiplier.vhd.
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lpm;
use lpm.lpm_components.all;
entity montgomery_comparison is
Generic(WIDTH_IN : integer := 8
);
Port( A : in unsigned(WIDTH_IN-1 downto 0);
B : in unsigned(WIDTH_IN-1 downto 0);
N : in unsigned(WIDTH_IN-1 downto 0);
latch : in std_logic;
clk : in std_logic;
reset : in std_logic;
data_ready : out std_logic;
M : out unsigned(WIDTH_IN-1 downto 0)
);
end entity;
architecture behavioral of montgomery_comparison is
-- Intermidiate signals
signal A_temp : unsigned(WIDTH_IN-1 downto 0):= (others => '0');
signal B_temp : unsigned(WIDTH_IN-1 downto 0):= (others => '0');
signal N_temp : unsigned(WIDTH_IN-1 downto 0):= (others => '0');
signal M_temp : std_logic_vector(WIDTH_IN-1 downto 0):= (others => '0');
signal M_temp_old : std_logic_vector(WIDTH_IN-1 downto 0):= (others => '0');
signal mult_zero : std_logic_vector(2*WIDTH_IN-1 downto 0) := (others => '0');
signal mult_undefined : std_logic_vector(2*WIDTH_IN-1 downto 0) := (others => 'U');
signal rem_zero : std_logic_vector(WIDTH_IN-1 downto 0) := (others => '0');
signal rem_undefined : std_logic_vector(WIDTH_IN-1 downto 0) := (others => 'U');
signal mult_result : std_logic_vector(2*WIDTH_IN-1 downto 0) := (others => '0');
signal temp_mult_result : std_logic_vector(2*WIDTH_IN-1 downto 0) := (others => '0');
signal state : integer := 0;
Begin
-- LPM multiplier and divider components
mult: LPM_MULT
generic map(
LPM_WIDTHA => WIDTH_IN,
LPM_WIDTHB => WIDTH_IN,
LPM_WIDTHP => 2*WIDTH_IN,
LPM_PIPELINE => WIDTH_IN
)
port map(
DATAA => std_logic_vector(A_temp),
DATAB => std_logic_vector(B_temp),
CLOCK => clk,
RESULT => mult_result
);
divide: LPM_DIVIDE
generic map(
LPM_WIDTHN => 2*WIDTH_IN,
LPM_WIDTHD => WIDTH_IN,
LPM_PIPELINE => 2*WIDTH_IN
)
port map(
numer => temp_mult_result,
denom => std_logic_vector(N_temp),
clock => clk,
remain => M_temp
);
compute: process(clk, A, B, N, latch, reset)
variable mult_count, div_count : integer := 0;
begin
if reset = '0' and rising_edge(clk) then
case state is
-- Reset values to begin a new operation
when 0 =>
if latch = '1' then
data_ready <= '0';
mult_count := 0;
div_count := 0;
B_temp <= B;
A_temp <= A;
N_temp <= N;
state <= 1;
end if;
-- If the multiplication is done, then start the division
when 1 =>
if (mult_count = WIDTH_IN) then
temp_mult_result <= mult_result;
state <= 2;
else -- increment multiplication counter if the operation is not done
mult_count := mult_count + 1;
state <= 1;
end if;
-- If division is done, then output the remainder and data ready is 1
when 2 =>
if (div_count = 2*WIDTH_IN) then
data_ready <='1';
M_temp_old <= M_temp;
M <= unsigned(M_temp);
state <= 0;
else -- increment the division counter and set data ready to 0
data_ready <= '0';
div_count := div_count + 1;
state <= 2;
end if;
when others =>
state <= 0;
end case;
end if;
end process;
end architecture;
| mit | 367f54556b89429dba1f16e3f5694c39 | 0.598793 | 3.041736 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | ProgramaVHDL/MIPS-MC_SingleEdge.vhd | 2 | 27,426 | -------------------------------------------------------------------------
--
-- I M P L E M E N T A Ç Ã O P A R C I A L D O M I P S (nov/2010)
--
-- Professores Fernando Moraes / Ney Calazans
--
-- ==> The top-level processor entity is MRstd
-- 21/06/2010 (Ney) - Bug corrigido no mux que gera op1 - agora recebe
-- npc e não pc.
-- 17/11/2010 (Ney) - Bugs corrigidos:
-- 1 - Decodificação das instruções BGEZ e BLEZ estava
-- incompleta
-- 2 - Definição de que linhas escolhem o registrador a
-- ser escrito nas instruções de deslocamento
-- (SSLL, SLLV, SSRA, SRAV, SSRL e SRLV)
-- 05/06/2012 (Ney) - Mudanças menores em nomenclatura
-- 19/11/2015 (Ney) - Mudança para MIPS-MC Single Clock Edge
-- Além das mudanças óbvias de sensibilidade de elementos de
-- memória para somente borda de subida, também mudou-se o
-- ponto de onde as entradas de dados do multiplicador e do
-- divisor provém, agora direto do banco de registradores e não
-- dos registradores RA e RB. Ainda, mudou-se a estrutura dos
-- blocos de dados e controle. O Bloco de Controle agora
-- contém o PC, o NPC e o IR e naturalmente a interface com
-- a memória de instruções. Foi eliminado o estado Sidle,
-- por não ser mais necessário.
-- 04/07/2016 (Ney) - Diversas revisões em nomes de sinais para
-- aumentar a intuitividade da descrição, mudança do
-- nome do processador para MIPS_S (ver documentação, versão 2.0
-- ou superior).
-- 05/08/2016 (Ney) - Correcao e adaptacao dos nomes de sinais e
-- blocos para facilitar aprendizado. Processador agora se chama
-- MIPS_MCS (MIPS Multi-Ciclo Single Edge)
-------------------------------------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- package com os tipos básicos auxiliares para descrever o processador
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
package p_MIPS_MCS is
-- inst_type define as instruções decodificáveis pelo bloco de controle
type inst_type is
( ADDU, SUBU, AAND, OOR, XXOR, NNOR, SSLL, SLLV, SSRA, SRAV,
SSRL, SRLV,ADDIU, ANDI, ORI, XORI, LUI, LBU, LW, SB, SW, SLT,
SLTU, SLTI, SLTIU, BEQ, BGEZ, BLEZ, BNE, J, JAL, JALR, JR,
MULTU, DIVU, MFHI, MFLO, invalid_instruction);
type microinstruction is record
CY1: std_logic; -- command of the first stage
CY2: std_logic; -- " of the second stage
walu: std_logic; -- " of the third stage
wmdr: std_logic; -- " of the fourth stage
wpc: std_logic; -- PC write enable
wreg: std_logic; -- register bank write enable
whilo: std_logic; -- habilitação de escrita nos registradores HI e LO
ce: std_logic; -- Chip enable and R_W controls
rw: std_logic;
bw: std_logic; -- Byte-word control (mem write only)
i: inst_type; -- operation specification
rst_md:std_logic; -- mult and div initialization
end record;
end p_MIPS_MCS;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Registrador de uso geral - sensível à borda de subida do relógio (ck),
-- com reset assíncrono (rst) e habilitação de escrita (ce)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
entity regnbits is
generic( INIT_VALUE : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0') );
port( ck, rst, ce : in std_logic;
D : in STD_LOGIC_VECTOR (31 downto 0);
Q : out STD_LOGIC_VECTOR (31 downto 0)
);
end regnbits;
architecture regnbits of regnbits is
begin
process(ck, rst)
begin
if rst = '1' then
Q <= INIT_VALUE(31 downto 0);
elsif ck'event and ck = '1' then
if ce = '1' then
Q <= D;
end if;
end if;
end process;
end regnbits;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Banco de Registradores (R0..R31) - 31 registradores de 32 bits
-- Trata-se de uma memória com três portas de acesso, não confundir
-- com a memória principal do processador.
-- São duas portas de leitura (sinais AdRP1+DataRP1 e AdRP2+DataRP2) e
-- uma porta de escrita (dedfinida pelo conjunto de sinais
-- ck, rst, ce, AdWP e DataWP).
-- Os endereços de cada porta (AdRP1, AdRP2 e AdWP) são obviamente de
-- 5 bits (pois 2^5=32), enquanto que os barramentos de dados de
-- saída (DataRP1, DataRP2) e de entrada (DataWP) são de 32 bits.
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use work.p_MIPS_MCS.all;
entity reg_bank is
port( ck, rst, ce : in std_logic;
AdRP1, AdRP2, AdWP : in std_logic_vector( 4 downto 0);
DataWP : in std_logic_vector(31 downto 0);
DataRP1, DataRP2: out std_logic_vector(31 downto 0)
);
end reg_bank;
architecture reg_bank of reg_bank is
type wirebank is array(0 to 31) of std_logic_vector(31 downto 0);
signal reg : wirebank ;
signal wen : std_logic_vector(31 downto 0) ;
begin
g1: for i in 0 to 31 generate
-- Remember register $0 is the constant 0, not a register.
-- This is implemented by never enabling writes to register $0
wen(i) <= '1' when i/=0 and AdWP=i and ce='1' else '0';
-- Remember register $29, the stack pointer, points to some place
-- near the bottom of the data memory, not the usual place
-- assigned by the MIPS simulator!!
g2: if i=29 generate -- SP --- x10010000 + x800 -- top of stack
r29: entity work.regnbits generic map(INIT_VALUE=>x"10010800")
port map(ck=>ck, rst=>rst, ce=>wen(i), D=>DataWP, Q=>reg(i));
end generate;
g3: if i/=29 generate
rx: entity work.regnbits
port map(ck=>ck, rst=>rst, ce=>wen(i), D=>DataWP, Q=>reg(i));
end generate;
end generate g1;
DataRP1 <= reg(CONV_INTEGER(AdRP1)); -- source1 selection
DataRP2 <= reg(CONV_INTEGER(AdRP2)); -- source2 selection
end reg_bank;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ALU - Uma unidade lógico-aritmética puramente combinacional, cuja
-- saída depende dos valores nas suas entradas de dados op1 e op2, cada
-- uma de 32 bits e da instrução sendo executada pelo processador
-- que é informada via o sinal de controle op_alu.
--
-- 22/11/2004 (Ney Calazans) - subtle error correction was done for J!
-- Part of the work for J has been done before, by shifting IR(15 downto 0)
-- left by two bits before writing data to the IMED register.
--
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.p_MIPS_MCS.all;
entity alu is
port( op1, op2 : in std_logic_vector(31 downto 0);
outalu : out std_logic_vector(31 downto 0);
op_alu : in inst_type
);
end alu;
architecture alu of alu is
signal menorU, menorS : std_logic ;
begin
menorU <= '1' when op1 < op2 else '0';
menorS <= '1' when ieee.Std_Logic_signed."<"(op1, op2) else '0' ; -- signed
outalu <=
op1 - op2 when op_alu=SUBU else
op1 and op2 when op_alu=AAND or op_alu=ANDI else
op1 or op2 when op_alu=OOR or op_alu=ORI else
op1 xor op2 when op_alu=XXOR or op_alu=XORI else
op1 nor op2 when op_alu=NNOR else
op2(15 downto 0) & x"0000" when op_alu=LUI else
(0=>menorU, others=>'0') when op_alu=SLTU or op_alu=SLTIU else
(0=>menorS, others=>'0') when op_alu=SLT or op_alu=SLTI else
op1(31 downto 28) & op2(27 downto 0) when op_alu=J or op_alu=JAL else
op1 when op_alu=JR or op_alu=JALR else
to_StdLogicVector(to_bitvector(op1) sll CONV_INTEGER(op2(10 downto 6))) when
op_alu=SSLL else
to_StdLogicVector(to_bitvector(op2) sll CONV_INTEGER(op1(5 downto 0))) when
op_alu=SLLV else
to_StdLogicVector(to_bitvector(op1) sra CONV_INTEGER(op2(10 downto 6))) when
op_alu=SSRA else
to_StdLogicVector(to_bitvector(op2) sra CONV_INTEGER(op1(5 downto 0))) when
op_alu=SRAV else
to_StdLogicVector(to_bitvector(op1) srl CONV_INTEGER(op2(10 downto 6))) when
op_alu=SSRL else
to_StdLogicVector(to_bitvector(op2) srl CONV_INTEGER(op1(5 downto 0))) when
op_alu=SRLV else
op1 + op2; -- default for ADDU,ADDIU,LBU,LW,SW,SB,BEQ,BGEZ,BLEZ,BNE
end alu;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Descrição Estrutural do Bloco de Dados
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_signed.all; -- needed for comparison instructions SLTx
use IEEE.Std_Logic_arith.all; -- needed for comparison instructions SLTxU
use work.p_MIPS_MCS.all;
entity datapath is
port( ck, rst : in std_logic;
d_address : out std_logic_vector(31 downto 0);
data : inout std_logic_vector(31 downto 0);
inst_branch_out, salta_out : out std_logic;
end_mul : out std_logic;
end_div : out std_logic;
RESULT_OUT : out std_logic_vector(31 downto 0);
uins : in microinstruction;
IR_IN : in std_logic_vector(31 downto 0);
NPC_IN : in std_logic_vector(31 downto 0)
);
end datapath;
architecture datapath of datapath is
signal result, R1, R2, RS, RT, RIN, sign_extend, cte_im, IMED, op1, op2,
outalu, RALU, MDR, mdr_int, HI, LO,
quociente, resto, D_Hi, D_Lo : std_logic_vector(31 downto 0) := (others=> '0');
signal adD, adS : std_logic_vector(4 downto 0) := (others=> '0');
signal inst_branch, inst_R_sub, inst_I_sub: std_logic;
signal salta : std_logic := '0';
signal produto : std_logic_vector(63 downto 0);
begin
-- auxiliary signals
inst_branch <= '1' when uins.i=BEQ or uins.i=BGEZ or uins.i=BLEZ or uins.i=BNE else
'0';
inst_branch_out <= inst_branch;
-- inst_R_sub is a subset of R-type instructions
inst_R_sub <= '1' when uins.i=ADDU or uins.i=SUBU or uins.i=AAND
or uins.i=OOR or uins.i=XXOR or uins.i=NNOR else
'0';
-- inst_I is a subset of I-type instructions
inst_I_sub <= '1' when uins.i=ADDIU or uins.i=ANDI or uins.i=ORI or uins.i=XORI else
'0';
--==============================================================================
-- second stage
--==============================================================================
-- The then clause is only used for logic shifts with a shamt field
M3: adS <= IR_IN(20 downto 16) when uins.i=SSLL or uins.i=SSRA or uins.i=SSRL else
IR_IN(25 downto 21);
REGS: entity work.reg_bank(reg_bank) port map
(AdRP1=>adS, DataRP1=>R1, AdRP2=>IR_IN(20 downto 16), DataRP2=>R2,
ck=>ck, rst=>rst, ce=>uins.wreg, AdWP=>adD, DataWP=>RIN);
-- sign extension
sign_extend <= x"FFFF" & IR_IN(15 downto 0) when IR_IN(15)='1' else
x"0000" & IR_IN(15 downto 0);
-- Immediate constant
M5: cte_im <= sign_extend(29 downto 0) & "00" when inst_branch='1' else
-- branch address adjustment for word frontier
"0000" & IR_IN(25 downto 0) & "00" when uins.i=J or uins.i=JAL else
-- J/JAL are word addressed. MSB four bits are defined at the ALU, not here!
x"0000" & IR_IN(15 downto 0) when uins.i=ANDI or uins.i=ORI or uins.i=XORI else
-- logic instructions with immediate operand are zero extended
sign_extend;
-- The default case is used by addiu, lbu, lw, sbu and sw instructions
-- second stage registers
RSreg: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.CY2, D=>R1, Q=>RS);
RTreg: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.CY2, D=>R2, Q=>RT);
RIM: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.CY2, D=>cte_im, Q=>IMED);
--==============================================================================
-- third stage
--==============================================================================
-- select the first ALU operand
M6: op1 <= NPC_IN when inst_branch='1' else
RS;
-- select the second ALU operand
M7: op2 <= RT when inst_R_sub='1' or uins.i=SLTU or uins.i=SLT or uins.i=JR
or uins.i=SLLV or uins.i=SRAV or uins.i=SRLV else
IMED;
-- ALU instantiation
DALU: entity work.alu port map (op1=>op1, op2=>op2, outalu=>outalu, op_alu=>uins.i);
-- ALU register
Reg_ALU: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.walu,
D=>outalu, Q=>RALU);
-- evaluation of conditions to take the branch instructions
salta <= '1' when ( (RS=RT and uins.i=BEQ) or (RS>=0 and uins.i=BGEZ) or
(RS<=0 and uins.i=BLEZ) or (RS/=RT and uins.i=BNE) ) else
'0';
salta_out <= salta;
-- multiplier and divider instantiations
inst_mult: entity work.multiplica
port map (Mcando=>R1, Mcador=>R2, clock=>ck,
start=>uins.rst_md, endop=>end_mul, produto=>produto);
inst_div: entity work.divide
generic map (32)
port map (divisor=>R2,dividendo=>R1, clock=>ck,
start=>uins.rst_md, endop=>end_div, quociente=>quociente, resto=>resto);
D_Hi <= produto(63 downto 32) when uins.i=MULTU else
resto;
D_Lo <= produto(31 downto 0) when uins.i=MULTU else
quociente;
-- HI and LO registers
REG_HI: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.whilo,
D=>D_Hi, Q=>HI);
REG_LO: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.whilo,
D=>D_Lo, Q=>LO);
--==============================================================================
-- fourth stage
--==============================================================================
d_address <= RALU;
-- tristate to control memory write
data <= RT when (uins.ce='1' and uins.rw='0') else (others=>'Z');
-- single byte reading from memory -- assuming the processor is little endian
M8: mdr_int <= data when uins.i=LW else
x"000000" & data(7 downto 0);
RMDR: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins.wmdr,
D=>mdr_int, Q=>MDR);
M9: result <= MDR when uins.i=LW or uins.i=LBU else
HI when uins.i=MFHI else
LO when uins.i=MFLO else
RALU;
--==============================================================================
-- fifth stage
--==============================================================================
-- signal to be written into the register bank
M2: RIN <= NPC_IN when (uins.i=JALR or uins.i=JAL) else result;
-- register bank write address selection
M4: adD <= "11111" when uins.i=JAL else -- JAL writes in register $31
IR_IN(15 downto 11) when (inst_R_sub='1'
or uins.i=SLTU or uins.i=SLT
or uins.i=JALR
or uins.i=MFHI or uins.i=MFLO
or uins.i=SSLL or uins.i=SLLV
or uins.i=SSRA or uins.i=SRAV
or uins.i=SSRL or uins.i=SRLV) else
IR_IN(20 downto 16) -- inst_I_sub='1' or uins.i=SLTIU or uins.i=SLTI
; -- or uins.i=LW or uins.i=LBU or uins.i=LUI, or default
RESULT_OUT <= result;
end datapath;
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Descrição do Bloco de Controle (mista, estrutural-comportamental)
--------------------------------------------------------------------------
--------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
use work.p_MIPS_MCS.all;
entity control_unit is
port( ck, rst : in std_logic;
inst_branch_in, salta_in : in std_logic;
end_mul, end_div : in std_logic;
i_address : out std_logic_vector(31 downto 0);
instruction : in std_logic_vector(31 downto 0);
RESULT_IN : in std_logic_vector(31 downto 0);
uins : out microinstruction;
IR_OUT : out std_logic_vector(31 downto 0);
NPC_OUT : out std_logic_vector(31 downto 0)
);
end control_unit;
architecture control_unit of control_unit is
type type_state is (Sfetch, Sreg, Salu, Swbk, Sld, Sst, Ssalta); -- Sidle,
signal PS, NS : type_state;
signal i : inst_type;
signal uins_int : microinstruction;
signal dtpc, npc, pc, incpc, IR : std_logic_vector(31 downto 0);
begin
--==============================================================================
-- Instruction fetch and PC increment
--==============================================================================
M1: dtpc <= RESULT_IN when (inst_branch_in='1' and salta_in='1') or uins_int.i=J
or uins_int.i=JAL or uins_int.i=JALR or uins_int.i=JR else
npc;
NPC_OUT <= npc;
-- Code memory starting address: beware of the OFFSET!
-- The one below (x"00400000") serves for code generated
-- by the MARS simulator
RPC: entity work.regnbits generic map(INIT_VALUE=>x"00400000")
port map(ck=>ck, rst=>rst, ce=>uins_int.wpc, D=>dtpc, Q=>pc);
incpc <= pc + 4;
RNPC: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins_int.CY1,
D=>incpc, Q=>npc);
RIR: entity work.regnbits port map(ck=>ck, rst=>rst, ce=>uins_int.CY1,
D=>instruction, Q=>IR);
IR_OUT <= IR ; -- IR is the Instruction Register
i_address <= pc; -- connects PC output to the instruction memory address bus
----------------------------------------------------------------------------------------
-- BLOCK (1/3) - INSTRUCTION DECODING and ALU operation definition.
-- This block generates one signal (i) of the Control Unit Output Function
----------------------------------------------------------------------------------------
i <= ADDU when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100001" else
SUBU when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100011" else
AAND when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100100" else
OOR when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100101" else
XXOR when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100110" else
NNOR when IR(31 downto 26)="000000" and IR(10 downto 0)="00000100111" else
SSLL when IR(31 downto 21)="00000000000" and IR(5 downto 0)="000000" else
SLLV when IR(31 downto 26)="000000" and IR(10 downto 0)="00000000100" else
SSRA when IR(31 downto 21)="00000000000" and IR(5 downto 0)="000011" else
SRAV when IR(31 downto 26)="000000" and IR(10 downto 0)="00000000111" else
SSRL when IR(31 downto 21)="00000000000" and IR(5 downto 0)="000010" else
SRLV when IR(31 downto 26)="000000" and IR(10 downto 0)="00000000110" else
ADDIU when IR(31 downto 26)="001001" else
ANDI when IR(31 downto 26)="001100" else
ORI when IR(31 downto 26)="001101" else
XORI when IR(31 downto 26)="001110" else
LUI when IR(31 downto 26)="001111" else
LW when IR(31 downto 26)="100011" else
LBU when IR(31 downto 26)="100100" else
SW when IR(31 downto 26)="101011" else
SB when IR(31 downto 26)="101000" else
SLTU when IR(31 downto 26)="000000" and IR(5 downto 0)="101011" else
SLT when IR(31 downto 26)="000000" and IR(5 downto 0)="101010" else
SLTIU when IR(31 downto 26)="001011" else
SLTI when IR(31 downto 26)="001010" else
BEQ when IR(31 downto 26)="000100" else
BGEZ when IR(31 downto 26)="000001" and IR(20 downto 16)="00001" else
BLEZ when IR(31 downto 26)="000110" and IR(20 downto 16)="00000" else
BNE when IR(31 downto 26)="000101" else
J when IR(31 downto 26)="000010" else
JAL when IR(31 downto 26)="000011" else
JALR when IR(31 downto 26)="000000" and IR(20 downto 16)="00000"
and IR(10 downto 0) = "00000001001" else
JR when IR(31 downto 26)="000000" and IR(20 downto 0)="000000000000000001000" else
MULTU when IR(31 downto 26)="000000" and IR(15 downto 0)="0000000000011001" else
DIVU when IR(31 downto 26)="000000" and IR(15 downto 0)="0000000000011011" else
MFHI when IR(31 downto 16)=x"0000" and IR(10 downto 0)="00000010000" else
MFLO when IR(31 downto 16)=x"0000" and IR(10 downto 0)="00000010010" else
invalid_instruction ; -- IMPORTANT: default condition is invalid instruction;
assert i /= invalid_instruction
report "******************* INVALID INSTRUCTION *************"
severity error;
uins_int.i <= i; -- this instructs the alu to execute its expected operation, if any
----------------------------------------------------------------------------------------
-- BLOCK (2/3) - DATAPATH REGISTERS load control signals generation.
-- This block generates all other signals of the Control Unit Output Function
----------------------------------------------------------------------------------------
uins_int.CY1 <= '1' when PS=Sfetch else '0';
uins_int.CY2 <= '1' when PS=Sreg else '0';
uins_int.walu <= '1' when PS=Salu else '0';
uins_int.wmdr <= '1' when PS=Sld else '0';
uins_int.wreg <= '1' when PS=Swbk or (PS=Ssalta and (i=JAL or i=JALR)) else '0';
uins_int.rw <= '0' when PS=Sst else '1';
uins_int.ce <= '1' when PS=Sld or PS=Sst else '0';
uins_int.bw <= '0' when PS=Sst and i=SB else '1';
uins_int.wpc <= '1' when PS=Swbk or PS=Sst or PS=Ssalta
or (PS=Salu and ((i=MULTU and end_mul='1')
or (i=DIVU and end_div='1'))) else '0';
uins_int.whilo <= '1' when (PS=Salu and end_mul='1' and i=MULTU)
or (PS=Salu and end_div='1' and i=DIVU)
else '0';
uins_int.rst_md <= '1' when PS=Sreg and (i=MULTU or i=DIVU) else '0';
uins <= uins_int;
---------------------------------------------------------------------------------------------
-- BLOCK (3/3) - Sequential part of the control unit - two processes implementing the
-- Control Unit state register and the (combinational) next-state function
---------------------------------------------------------------------------------------------
process(rst, ck)
begin
if rst='1' then
PS <= Sfetch;
-- Sfetch is the state the machine stays while processor is being reset
elsif ck'event and ck='1' then
PS <= NS;
end if;
end process;
process(PS, i, end_mul, end_div)
begin
case PS is
-- first stage: read the instruction pointed to by the PC
--
when Sfetch=>NS <= Sreg;
-- second stage: read the register bank and produce immediate data,
-- if needed
when Sreg=>NS <= Salu;
-- third stage: alu operation
--
when Salu =>if (i=LBU or i=LW) then
NS <= Sld;
elsif (i=SB or i=SW) then
NS <= Sst;
elsif (i=J or i=JAL or i=JALR or i=JR or i=BEQ
or i=BGEZ or i=BLEZ or i=BNE) then
NS <= Ssalta;
elsif ((i=MULTU and end_mul='0') or (i=DIVU and end_div='0')) then
NS <= Salu;
elsif ((i=MULTU and end_mul='1') or (i=DIVU and end_div='1')) then
NS <= Sfetch;
else
NS <= Swbk;
end if;
-- fourth stage: data memory operation
--
when Sld=> NS <= Swbk;
-- forth or fifth cycle: last for most instructions - GO BACK TO FETCH
--
when Sst | Ssalta | Swbk=>
NS <= Sfetch;
end case;
end process;
end control_unit;
--------------------------------------------------------------------------
-- Processador MIPS_S completo, onde se instanciam BD e BC
--------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_MIPS_MCS.all;
entity MIPS_MCS is
port( clock, reset: in std_logic;
ce, rw, bw: out std_logic;
i_address, d_address: out std_logic_vector(31 downto 0);
instruction: in std_logic_vector(31 downto 0);
data: inout std_logic_vector(31 downto 0));
end MIPS_MCS;
architecture MIPS_MCS of MIPS_MCS is
signal IR, NPC, RESULT: std_logic_vector(31 downto 0);
signal uins: microinstruction;
signal inst_branch, salta, end_mul, end_div: std_logic;
begin
dp: entity work.datapath
port map(ck=>clock, rst=>reset, d_address=>d_address, data=>data,
inst_branch_out=>inst_branch, salta_out=>salta,
end_mul=>end_mul, end_div=>end_div, RESULT_OUT=>RESULT,
uins=>uins, IR_IN=>IR, NPC_IN=>NPC);
ct: entity work.control_unit port map( ck=>clock, rst=>reset,
i_address=>i_address, instruction=>instruction,
inst_branch_in=>inst_branch, salta_in=>salta,
end_mul=>end_mul, end_div=>end_div, RESULT_IN=>RESULT,
uins=>uins, IR_OUT=>IR, NPC_OUT=>NPC);
ce <= uins.ce;
rw <= uins.rw;
bw <= uins.bw;
end MIPS_MCS; | mit | a048ddd6eae878bb4ebadee4945f8409 | 0.515934 | 3.683815 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Simple/bcd_1_adder.vhd | 1 | 1,482 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_1_adder is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end bcd_1_adder;
--algorithm
-- If A + B <= 9 then -- assume both A and B are valid BCD numbers
-- RESULT = A + B ;
-- CARRY = 0 ;
-- else
-- RESULT = A + B + 6 ;
-- CARRY = 1;
-- end if ;
architecture bcd_1_adder_arch of bcd_1_adder is
begin
--BCD adder logic
process (A,B,C_IN)
variable temp : std_logic_vector(3 downto 0);
variable overflow : boolean;
begin
temp := A + B + C_IN;
overflow := A(0) and B(0) and A(1) and B(1) and A(2) and B(2) and A(3) and B(3) and C_IN;
if (temp <= 9) then
SUM <= temp + overflow*6;
C_OUT <= overflow;
else
SUM <= (temp + 6);
C_OUT <= '1';
end if;
-- if (A >0 and B >0 and A + B < 9) then
-- SUM <= temp+6;
-- C_OUT <= '1';
-- else
-- if ( temp <= 9 ) then
-- SUM <= temp;
-- C_OUT <= '0';
-- else
-- SUM <= (temp + 6);
-- C_OUT <= '1';
-- end if;
-- end if;
-- if ( ('0'&A) + ('0'&B) + C_IN <= 9 ) then
-- SUM <= (A + B + C_IN);
-- C_OUT <= '0';
-- else
-- SUM <= (A + B + C_IN + 6);
-- C_OUT <= '1';
-- end if;
end process;
end bcd_1_adder_arch;
| apache-2.0 | bd8769018c54f28688de63571ad2b20f | 0.487854 | 2.405844 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/Input_data_controller/Input_data_controller.vhd | 1 | 558 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Input_data_controller is
port( data_in: in STD_LOGIC_VECTOR(3 downto 0);
data_ready : in STD_LOGIC);
end Input_data_controller;
architecture Input_data_controller_arch of Input_data_controller is
signal count_in,count_out: STD_LOGIC_VECTOR(3 downto 0);
begin
process(in_ready)
if count_in<19 then
if(in_ready='1')
PIPO_21x4_data_in <= data_in;
PIPO_21x4_clock <= '0';
PIPO_21x4_clock <= '1';
count_in <= count_in + 1;
end if;
end if;
end process;
end Input_data_controller_arch;
| mit | 7f1775a3b7a4cdb643c55ca6e3c3981b | 0.697133 | 2.619718 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/std_ovl_procs_syn.vhd | 1 | 20,837 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
package std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
);
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string;
------------------------------------------------------------------------------
-- cover_item_set
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package std_ovl_procs;
package body std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string is
variable new_default : ovl_msg_default_type := (others => NUL);
begin
new_default(1 to default'high) := default;
return new_default;
end function ovl_set_msg;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
) is
begin
end procedure ovl_print_init_count_proc;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
) is
begin
end procedure ovl_error_proc;
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
) is
begin
end procedure ovl_init_msg_proc;
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
) is
begin
end procedure ovl_cover_proc;
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
) is
begin
end procedure ovl_finish_proc;
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE);
end function ovl_2state_is_on;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE) and
(property_type_ctrl /= OVL_ASSERT_2STATE) and
(property_type_ctrl /= OVL_ASSUME_2STATE) and
(controls.xcheck_ctrl = OVL_ON) and
((controls.implicit_xcheck_ctrl = OVL_ON) or explicit_x_check);
end function ovl_xcheck_is_on;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural is
begin
if (instance_val = OVL_NOT_SET) then
return default_ctrl_val;
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string is
variable msg_default_width : integer := ovl_msg_default_type'high;
begin
if (instance_val = OVL_MSG_NOT_SET) then
-- get width of msg_default value
for i in 1 to ovl_msg_default_type'high loop
if (default_ctrl_val(i) = NUL) then
msg_default_width := i - 1;
exit;
end if;
end loop;
return default_ctrl_val(1 to msg_default_width);
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- cover_item_set
-- determines if a bit in the level integer is set or not.
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean is
begin
return ((level mod (item * 2)) >= item);
end function cover_item_set;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean is
begin
return false;
end function ovl_is_x;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean is
begin
return false;
end function ovl_is_x;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result or v(i);
end if;
exit when result = '1';
end loop;
return result;
end function or_reduce;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result and v(i);
end if;
exit when result = '0';
end loop;
return result;
end function and_reduce;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result xor v(i);
end if;
end loop;
return result;
end function xor_reduce;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) sll r);
end function "sll";
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) srl r);
end function "srl";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
return unsigned(l) > r;
end function ">";
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
return unsigned(l) < r;
end function "<";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package body std_ovl_procs;
| mit | 0d64f91c45ecc1f1d7c7704df16bf816 | 0.326055 | 6.036211 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/Rev_XLNX_5/vhdl/opcode_fetch.vhd | 1 | 1,454 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LPC <= X"0000";
elsif (CE = '1' and T2 = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end process;
end Behavioral;
| mit | 038ba25b40447ff52db4b5396053a434 | 0.607978 | 2.774809 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl_procs.vhd | 1 | 26,454 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
-- NOTE : This file is not suitable for use with synthesis tools, use
-- std_ovl_procs_syn.vhd instead.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use std.textio.all;
package std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
);
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string;
------------------------------------------------------------------------------
-- cover_item_set
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
type err_array is array (ovl_severity_level_natural) of string (1 to 16);
constant err_typ : err_array := (OVL_FATAL => " OVL_FATAL",
OVL_ERROR => " OVL_ERROR",
OVL_WARNING => " OVL_WARNING",
OVL_INFO => " OVL_INFO");
end package std_ovl_procs;
package body std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string is
variable new_default : ovl_msg_default_type := (others => NUL);
begin
new_default(1 to default'high) := default;
return new_default;
end function ovl_set_msg;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
) is
variable ln : line;
begin
if ((controls.init_msg_ctrl = OVL_ON) and (controls.init_count_ctrl = OVL_ON)) then
writeline(output, ln);
write(ln, "OVL_METRICS: " & integer'image(ovl_init_count) & " OVL assertions initialized");
writeline(output, ln);
writeline(output, ln);
end if;
end procedure ovl_print_init_count_proc;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
) is
variable ln : line;
constant severity_level_ctrl : ovl_severity_level_natural :=
ovl_get_ctrl_val(severity_level, controls.severity_level_default);
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
constant msg_ctrl : string :=
ovl_get_ctrl_val(msg, controls.msg_default);
begin
error_count := error_count + 1;
if (error_count <= controls.max_report_error) then
case (property_type_ctrl) is
when OVL_ASSERT | OVL_ASSUME | OVL_ASSERT_2STATE | OVL_ASSUME_2STATE =>
write(ln, err_typ(severity_level_ctrl) & " : "
& assert_name & " : "
& msg_ctrl & " : "
& err_msg
& " : severity " & ovl_severity_level'image(severity_level_ctrl)
& " : time " & time'image(now)
& " " & path);
writeline(output, ln);
when OVL_IGNORE => null;
end case;
end if;
if ((severity_level_ctrl = OVL_FATAL) and (controls.finish_ctrl = OVL_ON)) then
fatal_sig <= '1';
end if;
end procedure ovl_error_proc;
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
) is
variable ln : line;
constant severity_level_ctrl : ovl_severity_level_natural :=
ovl_get_ctrl_val(severity_level, controls.severity_level_default);
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
constant msg_ctrl : string :=
ovl_get_ctrl_val(msg, controls.msg_default);
begin
if (controls.init_count_ctrl = OVL_ON) then
ovl_init_count := ovl_init_count + 1;
else
case (property_type_ctrl) is
when OVL_ASSERT | OVL_ASSUME | OVL_ASSERT_2STATE | OVL_ASSUME_2STATE =>
write(ln, "OVL_NOTE: " & OVL_VERSION & ": "
& assert_name
& " initialized @ " & path
& " Severity: " & ovl_severity_level'image(severity_level_ctrl)
& ", Message: " & msg_ctrl);
writeline(output, ln);
when OVL_IGNORE => NULL;
end case;
end if;
end procedure ovl_init_msg_proc;
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
) is
variable ln : line;
begin
cover_count := cover_count + 1;
if (cover_count <= controls.max_report_cover_point) then
write(ln, "OVL_COVER_POINT : "
& assert_name & " : "
& cvr_msg & " : "
& "time " & time'image(now)
& " " & path);
writeline(output, ln);
end if;
end procedure ovl_cover_proc;
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
) is
variable ln : line;
variable runtime_after_fatal_time : time;
begin
if (fatal_sig = '1') then
-- convert string to time
write(ln, runtime_after_fatal);
read(ln, runtime_after_fatal_time);
wait for runtime_after_fatal_time;
report " OVL : Simulation stopped due to a fatal error : " & assert_name & " : " & "time " &
time'image(now) & " " & path severity failure;
end if;
end procedure ovl_finish_proc;
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE);
end function ovl_2state_is_on;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE) and
(property_type_ctrl /= OVL_ASSERT_2STATE) and
(property_type_ctrl /= OVL_ASSUME_2STATE) and
(controls.xcheck_ctrl = OVL_ON) and
((controls.implicit_xcheck_ctrl = OVL_ON) or explicit_x_check);
end function ovl_xcheck_is_on;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural is
begin
if (instance_val = OVL_NOT_SET) then
return default_ctrl_val;
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string is
variable msg_default_width : integer := ovl_msg_default_type'high;
begin
if (instance_val = OVL_MSG_NOT_SET) then
-- get width of msg_default value
for i in 1 to ovl_msg_default_type'high loop
if (default_ctrl_val(i) = NUL) then
msg_default_width := i - 1;
exit;
end if;
end loop;
return default_ctrl_val(1 to msg_default_width);
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- cover_item_set
-- determines if a bit in the level integer is set or not.
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean is
begin
return ((level mod (item * 2)) >= item);
end function cover_item_set;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean is
begin
return is_x(s);
end function ovl_is_x;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean is
begin
return is_x(s);
end function ovl_is_x;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result or v(i);
end if;
exit when result = '1';
end loop;
return result;
end function or_reduce;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result and v(i);
end if;
exit when result = '0';
end loop;
return result;
end function and_reduce;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result xor v(i);
end if;
end loop;
return result;
end function xor_reduce;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) sll r);
end function "sll";
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) srl r);
end function "srl";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- private functions used by "<" and ">" functions --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned_num_bits
------------------------------------------------------------------------------
function unsigned_num_bits (arg: natural) return natural is
variable nbits: natural;
variable n: natural;
begin
n := arg;
nbits := 1;
while n > 1 loop
nbits := nbits+1;
n := n / 2;
end loop;
return nbits;
end unsigned_num_bits;
------------------------------------------------------------------------------
-- to_unsigned
------------------------------------------------------------------------------
function to_unsigned (arg, size: natural) return std_logic_vector is
variable result: std_logic_vector(size-1 downto 0);
variable i_val: natural := arg;
begin
for i in 0 to result'left loop
if (i_val mod 2) = 0 then
result(i) := '0';
else result(i) := '1';
end if;
i_val := i_val/2;
end loop;
return result;
end to_unsigned;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
if is_x(l) then return false; end if;
if unsigned_num_bits(r) > l'length then return false; end if;
return not (l <= to_unsigned(r, l'length));
end function ">";
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
if is_x(l) then return false; end if;
if unsigned_num_bits(r) > l'length then return 0 < r; end if;
return (l < to_unsigned(r, l'length));
end function "<";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package body std_ovl_procs;
| mit | c07763d6909ac4595b4c6a2e7e1caec7 | 0.355674 | 5.482694 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/spi/spi_rx.vhd | 1 | 4,502 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
----------------------------------------------------------------------------------------------------
entity spi_rx is
generic(
--debug
cpol : in integer;
cpha : in integer
);
port (
ctrl : in ctrl_t;
sclk : in std_logic;
cs_n : in std_logic;
mosi : in std_logic;
data : out std_logic_vector(spi_word_length - 1 downto 0);
new_data : out std_logic
);
end entity spi_rx;
----------------------------------------------------------------------------------------------------
architecture rtl of spi_rx is
----------------------------------------------------------------------------------------------------
-- Prevent metastability.
----------------------------------------------------------------------------------------------------
signal sclk_d1, sclk_d2 : std_logic;
signal cs_n_d1, cs_n_d2 : std_logic;
signal mosi_d1, mosi_d2 : std_logic;
----------------------------------------------------------------------------------------------------
-- Internal signal declarations
----------------------------------------------------------------------------------------------------
type state_t is (disabled, wait_until_time_to_capture, hold_data);
signal state : state_t;
signal sclk_d3 : std_logic;
signal bit_index : integer range 0 to spi_word_length - 1;
begin
prevent_metastability : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
sclk_d1 <= sclk;
sclk_d2 <= sclk_d1;
cs_n_d1 <= cs_n;
cs_n_d2 <= cs_n_d1;
mosi_d1 <= mosi;
mosi_d2 <= mosi_d1;
end if;
end process prevent_metastability;
delay_sclk : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
sclk_d3 <= sclk_d2;
end if;
end process delay_sclk;
fsm_nextstate : process (ctrl.clk) is
-- This function abstracts away the decisionmaking about what to do given different values of cpol and cpha.
-- Hopefully, because cpol and cpha are constant in this block, the FPGA will not synthesize the parts
-- of the if statements which are not reached.
function is_it_time_to_capture(the_sclk : in std_logic;
the_sclk_d : in std_logic;
the_cpha : in integer;
the_cpol : in integer) return boolean is
begin
if the_cpol = 0 and the_cpha = 0 then
return the_sclk_d = '0' and the_sclk = '1';
elsif the_cpol = 0 and the_cpha = 1 then
return the_sclk_d = '1' and the_sclk = '0';
elsif the_cpol = 1 and the_cpha = 0 then
return the_sclk_d = '1' and the_sclk = '0';
-- otherwise the_cpol = 1 and the_cpha = 1
else
return the_sclk_d = '0' and the_sclk = '1';
end if;
end is_it_time_to_capture;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
state <= disabled;
bit_index <= spi_word_length - 1;
data <= (others => '0');
new_data <= '0';
else
new_data <= '0';
if cs_n_d2 = '1' then
state <= disabled;
else
-- cs is enabled. Let's do stuff!
case state is
when disabled =>
state <= wait_until_time_to_capture;
bit_index <= spi_word_length - 1;
when wait_until_time_to_capture =>
if is_it_time_to_capture(sclk_d2, sclk_d3, cpha, cpol) then
data(bit_index) <= mosi_d2;
--We could push this functionality into another state if necessary.
if bit_index = 0 then
bit_index <= spi_word_length - 1;
new_data <= '1';
state <= hold_data;
else
bit_index <= bit_index - 1;
end if;
end if;
-- This state exists to guarantee that data will be valid in the clock cycle after
-- new_data is flagged.
when hold_data =>
state <= wait_until_time_to_capture;
end case;
end if;
end if;
end if;
end process fsm_nextstate;
end architecture rtl;
----------------------------------------------------------------------------------------------------
| bsd-2-clause | 35f3a70258626369d0e768bf4e517351 | 0.461795 | 4.184015 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_never.vhd | 1 | 1,153 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never;
| mit | 7b68418b4ced2d2f9cfd2c670d96c0d5 | 0.543799 | 3.441791 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/sinewave/temp_midi_note_player_tb.vhd | 1 | 1,021 | -- TestBench Template
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.midi_pkg.all;
entity tb is
end tb;
architecture behavioural of tb is
signal ctrl : ctrl_t;
signal midi_no : midi_note_t;
signal pcm_out : signed(15 downto 0);
signal new_pcm_out : std_logic;
begin
temp_midi_note_player_1 : entity work.temp_midi_note_player
port map (
ctrl => ctrl,
midi_no => midi_no,
pcm_out => pcm_out,
new_pcm_out => new_pcm_out);
clk_gen : process
begin
ctrl.clk <= '0';
wait for clk_period / 2;
ctrl.clk <= '1';
wait for clk_period / 2;
end process;
-- Test Bench Statements
tb : process
begin
ctrl.reset_n <= '0';
wait for 5 * clk_period; -- wait until global set/reset completes
ctrl.reset_n <= '1';
midi_no <= 21;
wait;
end process tb;
end;
| bsd-2-clause | e6885785e95f564a9dd7171c6c51f4e7 | 0.615083 | 3.141538 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_range_rtl.vhd | 1 | 6,299 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_range is
constant assert_name : string := "OVL_RANGE";
constant path : string := "";
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY);
constant cover_corner : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_CORNER);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal test_expr_x01 : std_logic_vector(width - 1 downto 0);
signal prev_test_expr : std_logic_vector(width - 1 downto 0);
shared variable error_count : natural;
shared variable cover_count : natural;
begin
test_expr_x01 <= to_x01(test_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif (not ovl_is_x(test_expr_x01)) then
if((unsigned(test_expr_x01) < min) or (unsigned(test_expr_x01) > max)) then
fire(0) <= '1';
ovl_error_proc("Test expression evaluates to a value outside the range specified by parameters min and max", severity_level,
property_type, assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif (ovl_is_x(test_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_sanity or cover_corner)) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
prev_test_expr <= test_expr_x01;
if (reset_n = '0') then
fire(2) <= '0';
else
fire(2) <= '0';
if (cover_sanity and (test_expr_x01 /= prev_test_expr) and
not ovl_is_x(test_expr_x01) and not ovl_is_x(prev_test_expr)) then
ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
if (cover_corner and (unsigned(test_expr_x01) = min) and not ovl_is_x(test_expr_x01)) then
ovl_cover_proc("test_expr_at_min covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
if (cover_corner and (unsigned(test_expr_x01) = max) and not ovl_is_x(test_expr_x01)) then
ovl_cover_proc("test_expr_at_max covered", assert_name, path, controls, cover_count);
fire(2) <= '1';
end if;
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not(cover_sanity) and not(cover_corner))) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit | 35735701e13b9668cb0d5ee69aaa4ac9 | 0.487855 | 3.907568 | false | true | false | false |
tommylommykins/logipi-midi-player | hdl/spi/spi_tx_ram_controller.vhd | 1 | 4,330 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity spi_tx_ram_controller is
generic(
tx_max_block_size : integer
);
port(
ctrl : in ctrl_t;
contents_count : in integer;
data_fully_latched : in std_logic;
next_tx_word : in std_logic_vector(15 downto 0);
latched_data : in std_logic_vector(7 downto 0);
tx_byte : out std_logic_vector(7 downto 0);
dequeue : out std_logic
);
end;
architecture rtl of spi_tx_ram_controller is
-- We need to latch the number of bytes being sent if we are in the middle of
-- a message
signal remaining_words_this_msg : integer range 0 to tx_max_block_size * 2;
signal header_byte : std_logic_vector(7 downto 0);
signal data_fully_latched_d1 : std_logic;
signal data_fully_latched_re : std_logic;
signal next_tx_word_held : std_logic_vector(15 downto 0);
constant bytes_per_word : integer := 2;
signal remaining_bytes_this_word : integer range 0 to bytes_per_word - 1 ;
signal next_tx_byte : std_logic_vector(7 downto 0);
type state_t is (tx_header, init_msg, init_word, init_byte, tx_byte_state);
signal state : state_t;
begin
fsm_nextstate : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
state <= tx_header;
else
case state is
when tx_header =>
if latched_data /= "00000000" and data_fully_latched_re = '1' then
state <= init_msg;
end if;
when init_msg =>
state <= tx_byte_state;
when init_word =>
state <= tx_byte_state;
when init_byte =>
state <= tx_byte_state;
when tx_byte_state =>
-- if we are definitely sure the current byte has been sent, then
-- prepare to send the next one.
if data_fully_latched_re = '1' then
if remaining_words_this_msg = 1 and remaining_bytes_this_word = 0 then
state <= tx_header;
elsif remaining_bytes_this_word = 0 then
state <= init_word;
else
state <= init_byte;
end if;
end if;
end case;
end if;
end if;
end process;
fsm_outputs : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
dequeue <= '0';
else
dequeue <= '0';
case state is
when tx_header =>
tx_byte <= header_byte;
when init_msg =>
remaining_words_this_msg <= to_integer(unsigned(latched_data) / 2);
remaining_bytes_this_word <= bytes_per_word - 1;
next_tx_word_held <= next_tx_word;
dequeue <= '1';
when init_word =>
remaining_words_this_msg <= remaining_words_this_msg - 1;
remaining_bytes_this_word <= bytes_per_word - 1;
next_tx_word_held <= next_tx_word;
dequeue <= '1';
when init_byte =>
remaining_bytes_this_word <= remaining_bytes_this_word - 1;
when tx_byte_state =>
tx_byte <= next_tx_byte;
end case;
end if;
end if;
end process;
header_byte <=
std_logic_vector(to_unsigned(tx_max_block_size * bytes_per_word, header_byte'length)) when contents_count > tx_max_block_size
else
std_logic_vector(to_unsigned(contents_count * bytes_per_word, header_byte'length));
calc_next_tx_byte : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
case remaining_bytes_this_word is
when 1 => next_tx_byte <= next_tx_word_held(7 downto 0);
when others => next_tx_byte <= next_tx_word_held(15 downto 8);
end case;
end if;
end process;
calc_data_fully_latched_re : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
data_fully_latched_d1 <= data_fully_latched;
if data_fully_latched = '1' and data_fully_latched_d1 = '0' then
data_fully_latched_re <= '1';
else
data_fully_latched_re <= '0';
end if;
end if;
end process;
end;
| bsd-2-clause | aee0ef18625e3f01d4f1d8824916f485 | 0.57321 | 3.575557 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/select_yy.vhd | 3 | 2,763 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity select_yy is
Port( SY : in std_logic_vector( 3 downto 0);
IMM : in std_logic_vector(15 downto 0);
QUICK : in std_logic_vector( 3 downto 0);
RDAT : in std_logic_vector( 7 downto 0);
RR : in std_logic_vector(15 downto 0);
YY : out std_logic_vector(15 downto 0)
);
end select_yy;
architecture Behavioral of select_yy is
function b4(A : std_logic) return std_logic_vector is
begin
return A & A & A & A;
end;
function b8(A : std_logic) return std_logic_vector is
begin
return b4(A) & b4(A);
end;
begin
-- bits 1..0
--
s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), RDAT(1 downto 0),
RR(1 downto 0))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0);
when SY_RR => YY(1 downto 0) <= RR (1 downto 0);
when SY_SQ | SY_UQ => YY(1 downto 0) <= QUICK(1 downto 0);
when SY_SM | SY_UM => YY(1 downto 0) <= RDAT (1 downto 0);
when others => YY(1 downto 0) <= SY (1 downto 0);
end case;
end process;
-- bits 3..2
--
s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), RDAT(3 downto 2),
RR(3 downto 2))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2);
when SY_RR => YY(3 downto 2) <= RR (3 downto 2);
when SY_SQ | SY_UQ => YY(3 downto 2) <= QUICK(3 downto 2);
when SY_SM | SY_UM => YY(3 downto 2) <= RDAT (3 downto 2);
when others => YY(3 downto 2) <= "00";
end case;
end process;
-- bits 7..4
--
s_7_4: process(SY, IMM(7 downto 4), QUICK(3), RDAT(7 downto 4),
RR(7 downto 4))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4);
when SY_RR => YY(7 downto 4) <= RR (7 downto 4);
when SY_SQ => YY(7 downto 4) <= b4(QUICK(3));
when SY_SM | SY_UM => YY(7 downto 4) <= RDAT (7 downto 4);
when others => YY(7 downto 4) <= "0000";
end case;
end process;
-- bits 15..8
--
s_15_8: process(SY, IMM(15 downto 7), QUICK(3), RDAT(7), RR(15 downto 8))
begin
case SY is
when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8);
when SY_SI8 => YY(15 downto 8) <= b8(IMM(7));
when SY_RR => YY(15 downto 8) <= RR(15 downto 8);
when SY_SQ => YY(15 downto 8) <= b8(QUICK(3));
when SY_SM => YY(15 downto 8) <= b8(RDAT(7));
when others => YY(15 downto 8) <= "00000000";
end case;
end process;
end Behavioral;
| mit | 0a2bdce905249648a151ef9dd0d7c20f | 0.583786 | 2.553604 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart._baudgen.vhd | 3 | 2,497 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_baudgen is
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
RD : in std_logic;
WR : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_SEROUT : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_READY : out std_logic;
TX_BUSY : out std_logic
);
end uart_baudgen;
architecture Behavioral of uart_baudgen is
COMPONENT baudgen
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
CE_16 : OUT std_logic
);
END COMPONENT;
COMPONENT uart
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
END COMPONENT;
signal CE_16 : std_logic;
signal RX_FLAG : std_logic;
signal RX_OLD_FLAG : std_logic;
signal TX_FLAG : std_logic;
signal TX_FLAGQ : std_logic;
signal LTX_DATA : std_logic_vector(7 downto 0);
signal LRX_READY : std_logic;
begin
RX_READY <= LRX_READY;
TX_BUSY <= TX_FLAG xor TX_FLAGQ;
baud: baudgen
GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
PORT MAP(
CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16
);
urt: uart
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16,
TX_DATA => LTX_DATA,
TX_FLAG => TX_FLAG,
TX_SEROUT => TX_SEROUT,
TX_FLAGQ => TX_FLAGQ,
RX_SERIN => RX_SERIN,
RX_DATA => RX_DATA,
RX_FLAG => RX_FLAG
);
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
TX_FLAG <= '0';
LTX_DATA <= X"33";
else
if (RD = '1') then -- read Rx data
LRX_READY <= '0';
end if;
if (WR = '1') then -- write Tx data
TX_FLAG <= not TX_FLAG;
LTX_DATA <= TX_DATA;
end if;
if (RX_FLAG /= RX_OLD_FLAG) then
LRX_READY <= '1';
end if;
RX_OLD_FLAG <= RX_FLAG;
end if;
end if;
end process;
end Behavioral;
| mit | 708de18bd613317854677d45d218e7e0 | 0.588706 | 2.587565 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_one_hot.vhd | 1 | 1,171 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_one_hot is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_one_hot;
| mit | a4f645f664a1fde157c0ebbde7062569 | 0.566183 | 3.326705 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod03_interfaces/class_examples/class_based/memory.vhd | 1 | 928 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity memory is
port (
clk : in std_logic;
rd : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
data : inout std_logic_vector (15 downto 0)
);
end memory;
architecture rtl of memory is
type ram_type is array (65535 downto 0) of std_logic_vector(15 downto 0);
signal mem : ram_type;
begin -- rtl
writemem: process (clk)
begin -- process writemem
if (clk'event and clk='1') then
if wr = '1' then
mem(conv_integer(addr)) <= data;
end if;
end if;
end process writemem;
readmem: process (rd, addr)
begin -- process readmem
if rd = '1' then
data <= mem(conv_integer(addr));
else
data <= (data'range => 'Z');
end if;
end process readmem;
end rtl;
| mit | 04950d4500a86fc10808e249b6377f13 | 0.587284 | 3.244755 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/cpu_pack.vhd | 3 | 7,710 | -- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
type op_category is (
INTR,
HALT_WAIT,
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i,
JMP_RRZ_i,
CALL_i,
CALL_RR,
RET,
MOVE_SPi_RR,
MOVE_SPi_RS,
MOVE_SPi_RU,
MOVE_SPi_LL,
MOVE_SPi_LS,
MOVE_SPi_LU,
MOVE_RR_dSP,
MOVE_R_dSP,
-- 1X
AND_RR_i,
OR_RR_i,
XOR_RR_i,
SEQ_RR_i,
SNE_RR_i,
SGE_RR_i,
SGT_RR_i,
SLE_RR_i,
-- 2X
SLT_RR_i,
SHS_RR_i,
SHI_RR_i,
SLS_RR_i,
SLO_RR_i,
CLRW_dSP,
CLRB_dSP,
IN_ci_RU,
OUT_R_ci,
-- 3X
AND_LL_RR,
OR_LL_RR,
XOR_LL_RR,
SEQ_LL_RR,
SNE_LL_RR,
SGE_LL_RR,
SGT_LL_RR,
SLE_LL_RR,
SLT_LL_RR,
SHS_LL_RR,
SHI_LL_RR,
SLS_LL_RR,
SLO_LL_RR,
LNOT_RR,
NEG_RR,
NOT_RR,
-- 4X
MOVE_LL_RR,
MOVE_LL_cRR,
MOVE_L_cRR,
MOVE_RR_LL,
MOVE_RR_cLL,
MOVE_R_cLL,
MOVE_cRR_RR,
MOVE_cRR_RS,
MOVE_cRR_RU,
MOVE_ci_RR,
MOVE_ci_RS,
MOVE_ci_RU,
MOVE_ci_LL,
MOVE_ci_LS,
MOVE_ci_LU,
MOVE_RR_SP,
-- 5X
LSL_RR_i,
ASR_RR_i,
LSR_RR_i,
LSL_LL_RR,
ASR_LL_RR,
LSR_LL_RR,
ADD_LL_RR,
SUB_LL_RR,
MOVE_RR_ci,
MOVE_R_ci,
MOVE_RR_uSP,
MOVE_R_uSP,
-- 6X
MOVE_uSP_RR,
MOVE_uSP_RS,
MOVE_uSP_RU,
MOVE_uSP_LL,
MOVE_uSP_LS,
MOVE_uSP_LU,
LEA_uSP_RR,
MOVE_dRR_dLL,
MOVE_RRi_LLi,
-- 7X
MUL_IS,
MUL_IU,
DIV_IS,
DIV_IU,
MD_STEP,
MD_FIN,
MOD_FIN,
EI,
RETI,
DI,
-- 9X ... FX
ADD_RR_I,
SUB_RR_I,
MOVE_I_RR,
ADD_SP_I,
SEQ_LL_I,
MOVE_I_LL,
undef );
type SP_OP is ( SP_NOP, SP_INC, SP_LOAD );
-- ALU codes
--
constant ALU_X_HS_Y : std_logic_vector(4 downto 0) := "00000";
constant ALU_X_LO_Y : std_logic_vector(4 downto 0) := "00001";
constant ALU_X_HI_Y : std_logic_vector(4 downto 0) := "00010";
constant ALU_X_LS_Y : std_logic_vector(4 downto 0) := "00011";
constant ALU_X_GE_Y : std_logic_vector(4 downto 0) := "00100";
constant ALU_X_LT_Y : std_logic_vector(4 downto 0) := "00101";
constant ALU_X_GT_Y : std_logic_vector(4 downto 0) := "00110";
constant ALU_X_LE_Y : std_logic_vector(4 downto 0) := "00111";
constant ALU_X_EQ_Y : std_logic_vector(4 downto 0) := "01000";
constant ALU_X_NE_Y : std_logic_vector(4 downto 0) := "01001";
constant ALU_NEG_Y : std_logic_vector(4 downto 0) := "01100";
constant ALU_X_SUB_Y : std_logic_vector(4 downto 0) := "01101";
constant ALU_MOVE_Y : std_logic_vector(4 downto 0) := "01110";
constant ALU_X_ADD_Y : std_logic_vector(4 downto 0) := "01111";
constant ALU_X_AND_Y : std_logic_vector(4 downto 0) := "10000";
constant ALU_X_OR_Y : std_logic_vector(4 downto 0) := "10001";
constant ALU_X_XOR_Y : std_logic_vector(4 downto 0) := "10010";
constant ALU_NOT_Y : std_logic_vector(4 downto 0) := "10011";
constant ALU_X_LSR_Y : std_logic_vector(4 downto 0) := "10100";
constant ALU_X_ASR_Y : std_logic_vector(4 downto 0) := "10101";
constant ALU_X_LSL_Y : std_logic_vector(4 downto 0) := "10110";
constant ALU_X_MIX_Y : std_logic_vector(4 downto 0) := "10111";
constant ALU_MUL_IU : std_logic_vector(4 downto 0) := "11000";
constant ALU_MUL_IS : std_logic_vector(4 downto 0) := "11001";
constant ALU_DIV_IU : std_logic_vector(4 downto 0) := "11010";
constant ALU_DIV_IS : std_logic_vector(4 downto 0) := "11011";
constant ALU_MD_STP : std_logic_vector(4 downto 0) := "11100";
constant ALU_MD_FIN : std_logic_vector(4 downto 0) := "11101";
constant ALU_MOD_FIN : std_logic_vector(4 downto 0) := "11110";
constant ALU_ANY : std_logic_vector(4 downto 0) := ALU_X_AND_Y;
--------------------------------------------------------------
constant SA_43_0 : std_logic_vector(1 downto 0) := "00";
constant SA_43_FFFF : std_logic_vector(1 downto 0) := "01"; -- last bit 1 !!!
constant SA_43_I16 : std_logic_vector(1 downto 0) := "10";
constant SA_43_I8S : std_logic_vector(1 downto 0) := "11";
constant SA_21_0 : std_logic_vector(1 downto 0) := "00";
constant SA_21_LL : std_logic_vector(1 downto 0) := "01";
constant SA_21_RR : std_logic_vector(1 downto 0) := "10";
constant SA_21_SP : std_logic_vector(1 downto 0) := "11";
constant ADR_cSP_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '0';
constant ADR_cRR_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '0';
constant ADR_cLL_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '0';
constant ADR_cI16_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '0';
constant ADR_16SP_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '0';
constant ADR_8SP_L : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '0';
constant ADR_IO : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_0 & '0';
constant ADR_cSP_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '1';
constant ADR_cRR_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '1';
constant ADR_cLL_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '1';
constant ADR_cI16_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '1';
constant ADR_16SP_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '1';
constant ADR_8SP_H : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '1';
constant ADR_dSP : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '0';
constant ADR_dRR : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_RR & '0';
constant ADR_dLL : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_LL & '0';
constant ADR_SPi : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '1';
constant ADR_RRi : std_logic_vector(4 downto 0) := ADR_cRR_L;
constant ADR_LLi : std_logic_vector(4 downto 0) := ADR_cLL_L;
--------------------------------------------------------------
constant SX_LL : std_logic_vector(1 downto 0) := "00";
constant SX_RR : std_logic_vector(1 downto 0) := "01";
constant SX_SP : std_logic_vector(1 downto 0) := "10";
constant SX_PC : std_logic_vector(1 downto 0) := "11";
constant SX_ANY : std_logic_vector(1 downto 0) := SX_RR;
--------------------------------------------------------------
constant SY_SY0 : std_logic_vector(3 downto 0) := "0000";
constant SY_SY1 : std_logic_vector(3 downto 0) := "0001";
constant SY_SY2 : std_logic_vector(3 downto 0) := "0010";
constant SY_SY3 : std_logic_vector(3 downto 0) := "0011";
constant SY_I16 : std_logic_vector(3 downto 0) := "0100";
constant SY_RR : std_logic_vector(3 downto 0) := "0101";
constant SY_SI8 : std_logic_vector(3 downto 0) := "1000";
constant SY_UI8 : std_logic_vector(3 downto 0) := "1001";
constant SY_SQ : std_logic_vector(3 downto 0) := "1010";
constant SY_UQ : std_logic_vector(3 downto 0) := "1011";
constant SY_SM : std_logic_vector(3 downto 0) := "1100";
constant SY_UM : std_logic_vector(3 downto 0) := "1101";
constant SY_ANY : std_logic_vector(3 downto 0) := SY_RR;
--------------------------------------------------------------
constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- count up
constant PC_JMP : std_logic_vector(2 downto 0) := "001"; -- JMP/CALL
constant PC_RETH : std_logic_vector(2 downto 0) := "010"; -- RET (H)
constant PC_RETL : std_logic_vector(2 downto 0) := "011"; -- RET (L)
constant PC_WAIT : std_logic_vector(2 downto 0) := "100"; -- WAIT
constant PC_JPRR : std_logic_vector(2 downto 0) := "101"; -- JMP (RR)
constant PC_INT : std_logic_vector(2 downto 0) := "110"; -- INT
--------------------------------------------------------------
end cpu_pack;
package body cpu_pack is
end cpu_pack;
| mit | 91d81f00ad4980d8724ddd6bb2c87d72 | 0.585344 | 2.396643 | false | false | false | false |
Lyrositor/insa | 3if/ao/tp-ao_1/memory256x8.vhdl | 1 | 1,122 |
----------------------------------------------------------------------
--- An asynchronous memory
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity memory256x8 is
port (
ck : in std_logic;
we : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end entity memory256x8;
architecture rtl of memory256x8 is
type ram_array is array (0 to 255) of std_logic_vector(7 downto 0);
signal ram : ram_array := (
"01001100", "00010001",
"01001101", "00000111",
"00110010", "11100010",
"01000010", "10011111",
others => "UUUUUUUU");
begin
dataout <= "UUUUUUUU" when address="UUUUUUUU"
else ram(to_integer(unsigned(address))) after 0.2 ns ;
ram_process: process(ck) is
begin
if rising_edge(ck) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
end if;
end process ram_process;
end architecture rtl;
| unlicense | 06db6c597f837e06de32e2cbc505e290 | 0.552585 | 3.80339 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/ds1722.vhd | 1 | 3,884 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
T2: in std_logic;
RESET: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
architecture DS1722_arch of DS1722 is
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
signal state : BIG_STATE;
signal bit_count: INTEGER range 0 to 7;
signal Write: std_logic;
begin
-- Set up counter to sample digital themometer.
process (CLK_I, RESET)
begin
if (RESET = '1') then --asynchronous RESET active High
counter <= "00000000";
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
counter <= counter + "00000001";
end if;
end if;
end process;
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
Write <= ADDRESS(7);
-- process to convert byte commands to SPI and SPI to byte.
process (CLK_I, RESET)
begin
if (RESET='1') then --asynchronous RESET active High
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
if (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end if;
end process;
end DS1722_arch;
| mit | fc1d5d7b1e50bde50fa961e3601b9b24 | 0.510556 | 2.857984 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/ovl_always.vhd | 1 | 1,155 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_always is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
test_expr : in std_logic;
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_always;
| mit | c7b00bd3b9fc3fd4a94291c399ce317a | 0.544589 | 3.468468 | false | false | false | false |
Lyrositor/insa | 3if/ao/tp-ao_1/processor.vhdl | 1 | 7,060 |
----------------------------------------------------------------------
--- Processor
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity processor is
port (
rst : in std_logic;
ck : in std_logic;
we : out std_logic;
ma : out std_logic_vector(7 downto 0);
mdi : in std_logic_vector(7 downto 0);
mdo : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of processor is
component reg8bits is
port (
rst : in std_logic;
ck : in std_logic;
ce : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
subtype state is std_logic_vector(3 downto 0);
-- State encoding:
constant LoadInstr: state := "0000";
constant InstrLoaded: state := "0001";
constant LoadCst : state := "0010";
constant CstLoaded : state := "0011";
constant WriteBack: state := "0100";
constant ReadMem : state := "0101";
constant WriteMem : state := "0110";
constant IllegalInstr: state := "1111";
-- Registers to hold the current state and the next state
signal currentState, nextState : state;
--registers output and input
signal instr, cst,
a, b, aluOut, regABIn, arg1, arg2,
pc, pcIn, pcOffset, nextPC : std_logic_vector(7 downto 0);
-- decomposition of input word
signal destS, arg1S, arg2S, jr : std_logic;
signal codeOp : std_logic_vector(3 downto 0);
signal cond : std_logic_vector(1 downto 0);
signal offset : std_logic_vector(4 downto 0);
-- all the clock enable signale
signal ceInstr, ceCst, ceA, ceB, ceDest, ceFlags, cePC, ja, progFetch : std_logic;
-- other signals en vrac
signal Z, C, N, aluZ, aluC, aluN, condTrue: std_logic;
signal addResult, subResult: std_logic_vector(8 downto 0);
-- for the FSM
signal instrIsJA, instrIsJR, instrIsALU, instrIsCmp, instrIsNotOrCp, instrIsMem, oneWordInstr: std_logic;
begin
-- All the registers in the design (except the control unit)
regPC: reg8bits port map (rst=>rst, ck=>ck, ce=>cePC, di=>pcIn, do=>pc );
regInstr: reg8bits port map (rst=>rst, ck=>ck, ce=>ceInstr, di=>mdi, do=>instr );
regCst: reg8bits port map (rst=>rst, ck=>ck, ce=>ceCst, di=>mdi, do=>cst );
regA: reg8bits port map (rst=>rst, ck=>ck, ce=>ceA, di=>regABIn, do=>a );
regB: reg8bits port map (rst=>rst, ck=>ck, ce=>ceB, di=>regABIn, do=>b );
-- The multiplexer on ma and PC
ma <= pc when progFetch='1' else arg2;
-- the input of regPC
pcOffset <= "00000001" when jr='0'
else offset(4) & offset(4) & offset(4) & offset; -- sign extension
nextPC <= std_logic_vector(unsigned(pc) + unsigned(pcOffset));
pcIn <= cst when ja='1' else nextPC;
--the input of regA and regB
regABIn <= mdi when codeOp="1101" else aluOut;
-- Decomposition of the instruction word
codeOp <= instr(6 downto 3);
destS <= instr(0);
arg1S <= instr(1);
arg2S <= instr(2);
offset <= instr(4 downto 0);
cond <= instr(6 downto 5);
-- the multiplexers selecting arg1 and arg2
arg1 <= a when arg1S='0' else b;
arg2 <= a when arg2S='0' else cst;
-- ALU internals
-- the adder/subtractor
addResult <= std_logic_vector(signed('0' & arg1) + signed('0' & arg2));
subResult <= std_logic_vector(signed('0' & arg1) - signed('0' & arg2));
-- the following is the VHDL for a big multiplexer. Go draw it!
with codeOp select
aluOut <=
addResult(7 downto 0) when "0000",
subResult(7 downto 0) when "0001",
arg1 and arg2 when "0010",
arg1 or arg2 when "0011",
arg1 xor arg2 when "0100",
'0' & arg1(7 downto 1) when "0101", -- lsr
subResult(7 downto 0) when "0110", -- cmp
arg1 xor (7 downto 0 => arg2S) when "1000",
arg2 when "1001",
x"00" when others;
-- flags
aluC <= addResult(8) when codeOp="0000" else
subResult(8) when codeOp="0001" or codeOp="0110" else
arg1(0) when codeOp="0101" else '0';
aluZ <= '1' when aluOut = x"00" else '0';
aluN <= aluOut(7);
ceFlags <= instrIsALU and not codeOp(3);
regFlags: process(ck) is
begin
if rising_edge(ck) then
if rst = '1' then
C <= '0';
Z <= '0';
N <= '0';
else
if ceFlags = '1' then
C <= aluC;
Z <= aluZ;
N <= aluN;
end if;
end if;
end if;
end process;
ceA <= ceDest and not destS;
ceB <= ceDest and destS;
mdo <= arg1;
-- The FSM register
stateReg: process(ck) is
begin if rising_edge(ck) then
if rst = '1' then currentState <= "0000";
else currentState <= nextState;
end if; end if;
end process;
-- A few intermediate signals to simplify the FSM, add more if you need to
instrIsALU <= '1' when instrIsJR='0' and (codeOp="0000" or codeOp="0001" or codeOp="0010" or codeOp="0011" or codeOp="0100" or codeOp="0101" or codeOp="0110" or codeOp="1000" or codeOp="1001") else '0';
instrIsJA <= '1' when instr(7 downto 3) = "01111" else '0';
instrIsJR <= instr(7);
instrIsMem <= '1' when instrIsJR='0' and (codeOp="1101" or codeOp="1110") else '0';
InstrIsNotOrCp <= '1' when (instr(7 downto 3) = "01000") else '0';
InstrIsCmp <= '1' when (instr(7 downto 3) = "00110") else '0';
-- Is the instruction coded on 1 byte or on two?
oneWordInstr <= instrIsJR or InstrIsNotOrCp or ((instrIsALU or instrIsMem) and not arg2S);
-- The FSM transition function: TODO
nextState <=
LoadInstr when currentState=WriteBack or (currentState=CstLoaded and ja='1') else
InstrLoaded when currentState=LoadInstr else
WriteBack when (currentState=InstrLoaded and oneWordInstr='1') or currentState=CstLoaded else
LoadCst when currentState=InstrLoaded and oneWordInstr='0' else
CstLoaded when currentState=LoadCst else
ReadMem when codeOp="1101" and ((currentState=InstrLoaded and oneWordInstr='1') or currentState=CstLoaded) else
WriteMem when codeOp="1110" and ((currentState=InstrLoaded and oneWordInstr='1') or currentState=CstLoaded) else IllegalInstr;
-- The FSM output function: TODO
ceInstr <='1' when currentState=LoadInstr else '0';
progFetch <= '1' when currentState=LoadInstr or currentState=LoadCst else '0';
ceDest <='1' when (currentState=WriteBack or currentState=ReadMem) and not (jr='1' or codeOp="0110" or codeOp="1110" or codeOp="1111") else '0';
cePC <='1' when currentState=InstrLoaded or currentState=CstLoaded else '0';
ceCst <= '1' when currentState=LoadCst else '0';
we <= '1' when currentState=WriteMem else '0';
condTrue <= '1' when instrIsJR='1' and (cond = "00" or (cond = "01" and Z='1') or (cond = "10" and C='1') or (cond = "11" and N='1')) else '0';
ja <= instrIsJA;
jr <= instrIsJR when condTrue='1' else '0';
end architecture rtl;
| unlicense | f1751ab1190b5ba919c556d78719acf2 | 0.611473 | 3.353919 | false | false | false | false |
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II | MaterialDeAuxilo/serial/serial_tb.vhd | 1 | 4,677 | -------------------------------------------------------------------------
-- TEST_BENCH PARA SIMULACAO DA SERIAL
-- Simular por 100 microssegundos
-------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity serial_tb is
end serial_tb;
architecture serial_tb of serial_tb is
signal sckg, reset, txd, rx_start, rxd :std_logic;
signal av, ack: std_logic;
signal Sin, Sout : std_logic_vector(7 downto 0);
constant B1 : time := 1000 ns;
constant B2 : time := B1*2;
constant B3 : time := B1*3;
constant B4 : time := B1*4;
constant B5 : time := B1*5;
constant B6 : time := B1*6;
constant B7 : time := B1*7;
constant B8 : time := B1*8;
constant B9 : time := B1*9;
constant B10 : time := B1*10;
begin
-------------------------------------------------------------------------------------
serial_inst : entity work.serialinterface port map (
clock => sckg,
reset => reset,
rx_data => sin,
rx_start => rx_start,
rx_busy => ack,
rxd => rxd,
txd => txd,
tx_data => sout,
tx_av => av
);
-------------------------------------------------------------------------------------
-- Processo que simula o hospedeiro enviando dados para o periférico.
-- Manda-se dados depois que a simulação já está executando por 20 microssegundos.
--
-- Assume-se que antes disto o periférico já programou a velocidade da interface
-- serial para adaptá-la a sua velocidade (ver abaixo o processo que simula o
-- periférico)
--
-- Envia-se 4 valores de 8 bits na seguinte ordem, a intervalos de 20 microssegundos:
-- 0x37, 0x9A, 0x00 e 0xFF
--
-- O processo está concluído após uns 100 microssegundos.
-------------------------------------------------------------------------------------
sin <=(others=>'0'),
x"37" after 20 us, x"9A" after 40 us,
x"00" after 60 us, x"FF" after 80 us;
rx_start <= '0', '1' after 20020 ns, '0' after 20070 ns,
'1' after 42020 ns, '0' after 42090 ns,
'1' after 62020 ns, '0' after 62090 ns,
'1' after 82020 ns, '0' after 82090 ns;
-------------------------------------------------------------------------------------
-- Processo de geração do clock para o hospedeiro e para a interface serial. O clock
-- apresenta uma frequencia em torno de 30MHz
-------------------------------------------------------------------------------------
process -- gera o clock
begin
sckg <= '1', '0' after 16.66 ns;
wait for 33ns;
end process;
reset <='1', '0' after 20ns; -- gera o reset
-------------------------------------------------------------------------------------
-- Processo que simula o periférico enviando dados para o hospedeiro.
-- Primeiro o periférico programa a MEF de autobaud, enviando o valor de
-- aferição de velocidade 0x55H. Em seguida o processo envia 4 valores de 8 bits:
-- 0x87, 0x5F, 0x00 e 0xFF
-- O processo está concluído após 56,496 microssegundos.
-- Se a simulação continuar depois de uns 100 microssegundos o processo de
-- envio do periférico começa a ser repetido.
-------------------------------------------------------------------------------------
process -- 55H (valor de aferição), 87H, 5FH, 00H, FFH
begin
txd <= '1', '0' after B1, '1' after B2,
'0' after B3, '1' after B4,
'0' after B5, '1' after B6,
'0' after B7, '1' after B8,
'0' after B9, '1' after B10;
wait for B1*11;
txd <= '0', '1' after B1,
'1' after B2, '1' after B3,
'0' after B4, '0' after B5,
'0' after B6, '0' after B7,
'1' after B8, '1' after B9;
wait for B1*10;
txd <= '0', '1' after B1,
'1' after B2, '1' after B3,
'1' after B4, '1' after B5,
'0' after B6, '1' after B7,
'0' after B8, '1' after B9;
wait for B1*16;
txd <= '0', '0' after B1,
'0' after B2, '0' after B3,
'0' after B4, '0' after B5,
'0' after B6, '0' after B7,
'0' after B8, '1' after B9;
wait for B1*10;
txd <= '0', '1' after B1,
'1' after B2, '1' after B3,
'1' after B4, '1' after B5,
'1' after B6, '1' after B7,
'1' after B8, '1' after B9;
wait for B1*10;
wait for 50us; -- acrescentado para evitar que processo repita depois de apenas uns
-- 50 microssegundos
end process;
end serial_tb; | mit | 559fa471c9b8c79f1ba4099814dacb73 | 0.48236 | 3.28903 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/temperature.vhd | 1 | 3,153 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity temperature is
PORT( CLK_I : in STD_LOGIC;
T2 : in STD_LOGIC;
CLR : in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
TEMP_SPI : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC
);
end temperature;
architecture behavioral of temperature is
component DS1722
PORT( RESET : in std_logic;
CLK_I : in std_logic;
T2 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
ADDRESS : in std_logic_vector(7 downto 0);
START : in std_logic;
DONE : out std_logic;
TEMP_SPI : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC
);
end component;
signal TEMP_DATA_IN : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_DATA_OUT : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_ADDRESS : STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_START : std_logic;
signal TEMP_DONE : std_logic;
type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE,
TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE);
signal TEMP_state : TEMPERATURE_STATES;
begin
tsensor: DS1722
PORT MAP( CLK_I => CLK_I,
T2 => T2,
RESET => CLR,
DATA_IN => TEMP_DATA_IN,
DATA_OUT => TEMP_DATA_OUT,
ADDRESS => TEMP_ADDRESS,
START => TEMP_START,
DONE => TEMP_DONE,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
-- State machine to step though the process of getting data from the Digital Thermometer.
process (CLR, CLK_I)
begin
if (CLR = '1') then
TEMP_state <= TEMP_IDLE;
TEMP_START <= '0';
TEMP_ADDRESS <= "00000000";
TEMP_DATA_IN <= "00000000";
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
case TEMP_state is
when TEMP_IDLE =>
TEMP_START <= '0';
TEMP_ADDRESS <= "00000000";
TEMP_DATA_IN <= "00000000";
TEMP_state <= TEMP_SETUP;
when TEMP_SETUP =>
TEMP_ADDRESS <= "10000000";
TEMP_DATA_IN <= "11101000";
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_SETUP_COMPLETE;
TEMP_START <= '0';
else
TEMP_state <= TEMP_SETUP;
TEMP_START <= '1';
end if;
when TEMP_SETUP_COMPLETE =>
TEMP_START <= '0';
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_SETUP_COMPLETE;
else
TEMP_state <= TEMP_GET_DATA;
end if;
when TEMP_GET_DATA =>
TEMP_ADDRESS <= "00000010";
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_GET_DATA_COMPLETE;
DATA_OUT <= TEMP_DATA_OUT;
TEMP_START <= '0';
else
TEMP_state <= TEMP_GET_DATA;
TEMP_START <= '1';
end if;
when TEMP_GET_DATA_COMPLETE =>
TEMP_START <= '0';
if (TEMP_DONE = '1') then
TEMP_state <= TEMP_GET_DATA_COMPLETE;
else
TEMP_state <= TEMP_GET_DATA;
end if;
end case;
end if;
end if;
end process;
end behavioral;
| mit | af311797f9f807903bf9bfce6c7ce38b | 0.576277 | 2.807658 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/ws2812/ws2812_constant_colours.vhd | 1 | 762 | library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.ws2812_data.all;
package ws2812_constant_colours is
constant ws2812_clear : ws2812_t := lighten_ws2812(ws2812_t'(000, 000, 000), 0.05);
constant ws2812_green : ws2812_t := lighten_ws2812(ws2812_t'(000, 128, 000), 0.05);
constant ws2812_red : ws2812_t := lighten_ws2812(ws2812_t'(128, 000, 000), 0.05);
constant ws2812_blue : ws2812_t := lighten_ws2812(ws2812_t'(000, 000, 128), 0.05);
constant ws2812_purple : ws2812_t := lighten_ws2812(ws2812_t'(128, 000, 128), 0.05);
constant ws2812_pink : ws2812_t := lighten_ws2812(ws2812_t'(255, 192, 203), 0.05);
constant ws2812_yellow : ws2812_t := lighten_ws2812(ws2812_t'(255, 255, 000), 0.05);
end;
| bsd-2-clause | a6a0bc30bea3a8a78d34d2db443bbe91 | 0.688976 | 2.609589 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/track_decoder_tb/track_decoder_tb.vhd | 1 | 3,470 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.uart_constants.all;
use virtual_button_lib.uart_functions.all;
entity track_decoder_tb is end;
architecture tb of track_decoder_tb is
signal clk_50mhz : std_logic;
signal pb_0 : std_logic := '0';
signal pb_1 : std_logic := '0';
signal sw_0 : std_logic := '1';
signal sw_1 : std_logic := '0';
signal led_0 : std_logic;
signal led_1 : std_logic;
signal pi_to_fpga_pin : std_logic := '1';
signal fpga_to_pi_pin : std_logic;
signal light_square_data : std_logic;
constant cpol : integer := 0;
constant cpha : integer := 0;
signal send : boolean;
signal force_cs_low : boolean := false;
signal ready : boolean;
signal data : std_logic_vector(7 downto 0);
signal cs_n : std_logic := '1';
signal sclk : std_logic;
signal mosi : std_logic := '0';
signal miso : std_logic;
constant block_size : integer := 200;
begin
mock_spi_master_1 : entity work.mock_spi_master
port map (
frequency => 5_000_000,
cpol => cpol,
cpha => cpha,
send => send,
force_cs_low => force_cs_low,
ready => ready,
data => data,
cs_n => cs_n,
sclk => sclk,
mosi => mosi);
top_1 : entity work.top
port map (
clk_50mhz => clk_50mhz,
pb_0 => pb_0,
pb_1 => pb_1,
sw_0 => sw_0,
sw_1 => sw_1,
led_0 => led_0,
led_1 => led_1,
pi_to_fpga_pin => pi_to_fpga_pin,
fpga_to_pi_pin => fpga_to_pi_pin,
sclk => sclk,
cs_n => cs_n,
mosi => mosi,
miso => miso,
light_square_data => light_square_data);
-- Clock process definitions
clk_process : process
begin
clk_50mhz <= '0';
wait for clk_period/2;
clk_50mhz <= '1';
wait for clk_period/2;
end process;
stim_proc : process
type charfile is file of character;
file midi_file : charfile;
variable remaining_bytes : integer := 0;
variable read_char : character;
variable midi_byte : std_logic_vector(7 downto 0);
begin
sw_0 <= '0';
wait for 1 us;
sw_0 <= '1';
wait for 1 us;
--file_open(midi_file, "does.mid", read_mode);
file_open(midi_file, "deck.mid", read_mode);
while not endfile(midi_file) loop
if remaining_bytes /= 0 then
read(midi_file, read_char);
midi_byte := std_logic_vector(to_unsigned(character'pos(read_char), 8));
end if;
if not ready then
wait until ready;
end if;
if remaining_bytes = 0 then
data <= std_logic_vector(to_unsigned(block_size, 8));
remaining_bytes := block_size;
else
data <= midi_byte;
remaining_bytes := remaining_bytes - 1;
end if;
wait for 1 ps;
send <= true;
wait for 1 ps;
send <= false;
wait for 1 ps;
end loop;
uart_send(std_logic_vector(to_unsigned(character'pos('q'), 8)), 115200, pi_to_fpga_pin);
wait;
end process;
end;
| bsd-2-clause | ee9f7c0f60605b5fdd0a0ac86f0a02d0 | 0.52536 | 3.456175 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/syn_src/ovl_implication_rtl.vhd | 1 | 5,562 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_implication is
constant assert_name : string := "OVL_IMPLICATION";
constant path : string := "";
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal antecedent_expr_x01 : std_logic;
signal consequent_expr_x01 : std_logic;
shared variable error_count : natural;
shared variable cover_count : natural;
begin
antecedent_expr_x01 <= to_x01(antecedent_expr);
consequent_expr_x01 <= to_x01(consequent_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif ((antecedent_expr_x01 = '1') and (consequent_expr_x01 = '0')) then
fire(0) <= '1';
ovl_error_proc("Antecedent does not have consequent", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((consequent_expr_x01 = '0') and ovl_is_x(antecedent_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("antecedent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif ((antecedent_expr_x01 = '1') and (ovl_is_x(consequent_expr_x01))) then
fire(1) <= '1';
ovl_error_proc("consequent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (antecedent_expr_x01 = '1') then
fire(2) <= '1';
ovl_cover_proc("antecedent covered", assert_name, path, controls, cover_count);
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not cover_basic)) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
| mit | 5123a3c31e5e7506b8a9a0ee9fdac0a9 | 0.486336 | 3.941885 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/top.vhd | 1 | 5,473 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.sine_lut_pkg.all;
use virtual_button_lib.midi_pkg.all;
entity top is
port(
clk_50mhz : in std_logic;
pb_0 : in std_logic;
pb_1 : in std_logic;
sw_0 : in std_logic;
sw_1 : in std_logic;
led_0 : out std_logic;
led_1 : out std_logic;
--uart interface
pi_to_fpga_pin : in std_logic;
fpga_to_pi_pin : out std_logic;
-- spi interface
sclk : in std_logic;
cs_n : in std_logic;
mosi : in std_logic;
miso : out std_logic;
-- light square output
light_square_data : out std_logic
);
end top;
architecture rtl of top is
signal ctrl : ctrl_t;
signal clk : std_logic;
-- uart signals
signal uart_rx_data : std_logic_vector(7 downto 0);
signal uart_received : std_logic;
signal uart_framing_error : std_logic;
signal run_counter_dbg : std_logic;
-- button signals
signal buttons : button_arr;
-- spi signals
signal miso_int : std_logic;
signal spi_new_mcu_to_fpga_data : std_logic;
signal spi_mcu_to_fpga_data : std_logic_vector(spi_word_length - 1 downto 0);
signal spi_fpga_to_mcu_data : std_logic_vector(15 downto 0);
signal spi_enqueue_fpga_to_mcu_data : std_logic;
signal spi_contents_count : integer range 0 to spi_tx_ram_depth;
signal spi_tx_buffer_full : std_logic;
signal enable_spi_tx : std_logic;
--midi signals
signal pcm_out : signed(15 downto 0);
signal new_pcm_out : std_logic;
signal enable_decoder : std_logic;
signal errors : errors_t;
signal midi_nos : midi_note_arr_t;
-- midi ram signals
signal midi_ram_empty : std_logic;
signal midi_ram_full : std_logic;
signal midi_ram_contents_count : natural range 0 to midi_file_rx_bram_depth;
begin
uart_top_1 : entity virtual_button_lib.uart_top
port map (
ctrl => ctrl,
uart_rx => pi_to_fpga_pin,
uart_tx => fpga_to_pi_pin,
rx_data => uart_rx_data,
received => uart_received,
framing_error => uart_framing_error,
run_counter_dbg => run_counter_dbg
);
many_buttons_1 : entity virtual_button_lib.many_buttons
port map (
ctrl => ctrl,
data => uart_rx_data,
new_data => uart_received,
buttons => buttons
);
spi_top_1 : entity virtual_button_lib.spi_top
generic map (
tx_ram_depth => spi_tx_ram_depth,
tx_max_block_size => spi_tx_max_block_size,
cpol => 0,
cpha => 0)
port map (
ctrl => ctrl,
cs_n => cs_n,
sclk => sclk,
mosi => mosi,
miso => miso_int,
new_mcu_to_fpga_data => spi_new_mcu_to_fpga_data,
mcu_to_fpga_data => spi_mcu_to_fpga_data,
enqueue_fpga_to_mcu_data => spi_enqueue_fpga_to_mcu_data,
fpga_to_mcu_data => spi_fpga_to_mcu_data,
full => spi_tx_buffer_full,
contents_count => spi_contents_count
);
spi_fpga_to_mcu_data <= std_logic_vector(pcm_out);
temp_midi_note_player_1 : entity work.many_sines
port map (
ctrl => ctrl,
midi_nos => midi_nos,
pcm_out => pcm_out,
new_pcm_out => new_pcm_out);
spi_enqueue_fpga_to_mcu_data <= new_pcm_out;
midi_top_1 : entity virtual_button_lib.midi_top
port map (
ctrl => ctrl,
buttons => buttons,
enqueue => spi_new_mcu_to_fpga_data,
write_in_data => spi_mcu_to_fpga_data,
midi_nos => midi_nos,
empty => midi_ram_empty,
full => midi_ram_full,
enable_decoder => enable_decoder,
errors => errors,
contents_count => midi_ram_contents_count);
debug_light_generator_1 : entity virtual_button_lib.debug_light_generator
generic map(
spi_tx_max_block_size => spi_tx_max_block_size,
spi_tx_ram_depth => spi_tx_ram_depth
)
port map (
ctrl => ctrl,
spi_tx_buffer_full => spi_tx_buffer_full,
contents_count => spi_contents_count,
buttons => buttons,
cs_n => cs_n,
enable_spi_tx => enable_spi_tx,
uart_framing_error => uart_framing_error,
midi_ram_contents_count => midi_ram_contents_count,
enable_decoder => enable_decoder,
errors => errors,
run_counter_dbg => run_counter_dbg,
light_square_data => light_square_data
);
-----------------------------------------------------------------------------
ctrl.clk <= clk_50mhz;
resetting : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if buttons(r).pressed = '1' or sw_0 = '0' then
ctrl.reset_n <= '0';
else
ctrl.reset_n <= '1';
end if;
end if;
end process resetting;
tom_is_the_best : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
led_0 <= '0';
else
led_0 <= pb_0 xor sw_0 xor pb_1 xor sw_1;
end if;
end if;
end process;
-- Enable/disable spi data transmission.
enable_spi_tx <= '1';
led_1 <= '0';
miso <= miso_int;
end rtl;
| bsd-2-clause | f0ac0ea6c0f07f514c65b4b34d5a3068 | 0.563859 | 3.300965 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/HAM/HAM_tb.vhd | 1 | 1,482 |
library ieee;
use ieee.std_logic_1164.all;
entity HAM_tb is
end HAM_tb;
architecture tb of HAM_tb is
component HAM is
port( X, Y , B : in std_logic;
Sout, Cout : out std_logic);
end component;
signal X, Y , B, Sout, Cout : std_logic;
begin
mapping: HAM port map(X, Y, B, Sout, Cout);
process
begin
X <= '0';
Y <= '0';
B <= '0';
wait for 5 ns;
X <= '0';
Y <= '0';
B <= '0';
wait for 5 ns;
X <= '0';
Y <= '0';
B <= '1';
wait for 5 ns;
X <= '0';
Y <= '0';
B <= '1';
wait for 5 ns;
X <= '0';
Y <= '1';
B <= '0';
wait for 5 ns;
X <= '0';
Y <= '1';
B <= '0';
wait for 5 ns;
X <= '0';
Y <= '1';
B <= '1';
wait for 5 ns;
X <= '0';
Y <= '1';
B <= '1';
wait for 5 ns;
X <= '1';
Y <= '0';
B <= '0';
wait for 5 ns;
X <= '1';
Y <= '0';
B <= '0';
wait for 5 ns;
X <= '1';
Y <= '0';
B <= '1';
wait for 5 ns;
X <= '1';
Y <= '0';
B <= '1';
wait for 5 ns;
X <= '1';
Y <= '1';
B <= '0';
wait for 5 ns;
X <= '1';
Y <= '1';
B <= '0';
wait for 5 ns;
X <= '1';
Y <= '1';
B <= '1';
wait for 5 ns;
X <= '1';
Y <= '1';
B <= '1';
wait for 5 ns;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of HAM_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END | mit | 97f5039fe0bb41278d174863afc11544 | 0.358974 | 2.555172 | false | false | false | false |
willtmwu/vhdlExamples | Project/harware_interface.vhd | 1 | 8,445 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: hardware_interface.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Interface to PIN/PORT and combines/split signals
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
LIBRARY work;
use work.project_nrf_subprog.all;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0);
RGB1_Red : OUT std_logic;
RGB1_Green : OUT std_logic;
RGB1_Blue : OUT std_logic;
RGB2_Red : OUT std_logic;
RGB2_Green : OUT std_logic;
RGB2_Blue : OUT std_logic;
JD_I : in STD_LOGIC_VECTOR(1 downto 0);
JD_O : out std_logic_vector(5 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
--Central Button
signal masterReset : std_logic := '0';
signal buttonLeft : std_logic := '0';
signal buttonRight : std_logic := '0';
signal buttonUp : std_logic := '0';
signal buttonDown : std_logic := '0';
-- Create 1 HIGH CLK signal, for button debouncing
type DEBOUNCE_FSM is (DB_IDLE, DB_HIGH);
signal bLeftSig : std_logic := '0';
signal bLeft_state : DEBOUNCE_FSM := DB_IDLE;
signal bRightSig : std_logic := '0';
signal bRight_state : DEBOUNCE_FSM := DB_IDLE;
signal bUpSig : std_logic := '0';
signal bUp_state : DEBOUNCE_FSM := DB_IDLE;
signal bDownSig : std_logic := '0';
signal bDown_state : DEBOUNCE_FSM := DB_IDLE;
signal displayLower : std_logic_vector(15 downto 0) := (others => '0');
signal displayUpper : std_logic_vector(15 downto 0) := (others => '0');
signal clockScalers : std_logic_vector(26 downto 0) := (others => '0');
signal hamming_error : std_logic_vector(7 downto 0) := (others => '0');
signal data_nib : std_logic_vector(3 downto 0) := (others => '0');
signal LED_UART : std_logic_vector(2 downto 0) := (others => '0');
signal LED_SPI : std_logic_vector(2 downto 0) := (others => '0');
signal MISO : std_logic := '0'; -- In Lines JD_I
signal MOSI : std_logic; -- OUT line JD_O
signal SCLK : std_logic; -- OUT
signal CS : std_logic; -- OUT
signal CE : std_logic; -- OUT
signal IRQ : std_logic := '0'; -- OUT
signal sTransmissionChange : std_logic_vector(2 downto 0) := (others => '0');
signal sHighSpeedTrans : std_logic := '0';
COMPONENT top_controller
Port (
clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
bSend : in STD_LOGIC; -- Right Button
bModeChange : in STD_LOGIC; -- Up Button
bEnterData : in STD_LOGIC; -- Bottom Button
bCount : in STD_LOGIC; -- Left Button
sTransmission : in STD_LOGIC_VECTOR(2 downto 0);
sHighSpeed : in STD_LOGIC;
displayLower : out STD_LOGIC_VECTOR(15 downto 0);
displayUpper : out STD_LOGIC_VECTOR(15 downto 0);
data_nib : in std_logic_vector(3 downto 0);
-- NRF CTRL Lines fed down to SPI_CTRL
hamming_err : IN std_logic_vector(7 downto 0);
IRQ : in std_logic;
CE : OUT std_logic;
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic;
LED_SPI : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
begin
D1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
-- Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
-- Button Debouncing -- Generate HIGH for 1 CLK Cycle
-- LEFT Button
process begin
if (masterReset = '1') then
bLeftSig <= '0';
bLeft_State <= DB_IDLE;
elsif rising_edge(clk100mHz) then
case bLeft_State is
when DB_IDLE =>
if (buttonLeft = '1') then
bLeftSig <= '1';
bLeft_State <= DB_HIGH;
else
bLeftSig <= '0';
bLeft_State <= DB_IDLE;
end if;
when DB_HIGH =>
bLeftSig <= '0';
if (buttonLeft = '0') then
bLeft_State <= DB_IDLE;
end if;
end case;
end if;
end process;
-- Right Button
process begin
if (masterReset = '1') then
bRightSig <= '0';
bRight_State <= DB_IDLE;
elsif rising_edge(clk100mHz) then
case bRight_State is
when DB_IDLE =>
if (buttonright = '1') then
bRightSig <= '1';
bRight_State <= DB_HIGH;
else
bRightSig <= '0';
bRight_State <= DB_IDLE;
end if;
when DB_HIGH =>
bRightSig <= '0';
if (buttonRight = '0') then
bRight_State <= DB_IDLE;
end if;
end case;
end if;
end process;
-- Up Button
process begin
if (masterReset = '1') then
bUpSig <= '0';
bUp_State <= DB_IDLE;
elsif rising_edge(clk100mHz) then
case bUp_State is
when DB_IDLE =>
if (buttonUp = '1') then
bUpSig <= '1';
bUp_State <= DB_HIGH;
else
bUpSig <= '0';
bUp_State <= DB_IDLE;
end if;
when DB_HIGH =>
bUpSig <= '0';
if (buttonUp = '0') then
bUp_State <= DB_IDLE;
end if;
end case;
end if;
end process;
-- Down Button
process begin
if (masterReset = '1') then
bDownSig <= '0';
bDown_State <= DB_IDLE;
elsif rising_edge(clk100mHz) then
case bDown_State is
when DB_IDLE =>
if (buttonDown = '1') then
bDownSig <= '1';
bDown_State <= DB_HIGH;
else
bDownSig <= '0';
bDown_State <= DB_IDLE;
end if;
when DB_HIGH =>
bDownSig <= '0';
if (buttonDown = '0') then
bDown_State <= DB_IDLE;
end if;
end case;
end if;
end process;
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif rising_edge(clk100mhz) then
clockScalers <= clockScalers + '1';
end if;
end process;
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
-- Tri-Colour Debug LED
hamming_error <= slideSwitches(11 downto 4);
data_nib <= slideSwitches(3 downto 0);
sTransmissionChange <= slideSwitches(15 downto 13);
sHighSpeedTrans <= slideSwitches(12);
RGB1_Red <= LED_UART(0);
RGB1_Green <= LED_UART(1);
RGB1_Blue <= LED_UART(2);
RGB2_Red <= LED_SPI(0);
RGB2_Green <= LED_SPI(1);
RGB2_Blue <= LED_SPI(2);
-- SPI Control Lines
MISO <= JD_I(0);
JD_O(0) <= MOSI;
JD_O(1) <= SCLK;
JD_O(2) <= CS;
JD_O(3) <= CE;
IRQ <= JD_I(1);
JD_O(4) <= '0';
JD_O(5) <= '0';
CT_S : top_controller PORT MAP (
clk100mHz,
masterReset,
bRightSig,
bUpSig,
bDownSig,
bLeftSig,
sTransmissionChange,
sHighSpeedTrans,
displayLower,
displayUpper,
data_nib,
hamming_error,
IRQ,
CE,
CS,
SCLK,
MOSI,
MISO,
LED_SPI
);
end Behavioral; | apache-2.0 | fe66982df946135d11fcf543b26b1e51 | 0.591119 | 2.828198 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/process2.vhd | 1 | 12,544 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 2:
-- Read p1 response, get start, end address
-- request neighbors id from graphData
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process2 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_busy : out std_logic;
p2_count_1 : out unsigned(31 downto 0);
p2_count_2 : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphData : in std_logic_vector(63 downto 0);
-- Process 1 information
p1_done : in std_logic;
p1_count : in unsigned(31 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_en : in std_logic;
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 request queue signals
p2_req_q_almost_full : in std_logic;
p2_req_q_wr_en : out std_logic;
p2_req_q_din : out std_logic_vector(63 downto 0)
);
end entity ; -- process2
architecture arch of process2 is
type state_type is (s0, s1, s2, s3);
signal p2_state : state_type;
signal p2_done_out : std_logic;
signal count_1 : unsigned(31 downto 0);
signal count_2 : unsigned(31 downto 0);
signal p2_start_index : unsigned(31 downto 0);
signal p2_neigh_count : unsigned(30 downto 0);
signal busy : std_logic;
begin
-- assign count signals
p2_count_1 <= count_1;
p2_count_2 <= count_2;
-- assign p2_done signal
p2_done <= p2_done_out;
--p2_done <= '1' when started = '1' and p1_done = '1' and busy = '0' and p1_count = count_1 else '0';
p2_busy <= busy;
p2: process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p2_state <= s0;
p2_done_out <= '0';
busy <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
p2_start_index <= (others => '0');
p2_neigh_count <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
else
if (started = '1') then
case (p2_state) is
-- Start:
when s0 =>
-- If p1_rsp_q NOT empty, pop, go to s1
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
-- if p1_rsp_q empty, keep waiting
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
-- Reset Signals
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
-- Request a neighbor
when s1 =>
-- There at least one neighbor to request
if (p1_rsp_q_valid = '1' and unsigned(p1_rsp_q_dout(31 downto 1)) > 0) then
-- p2_req_q is ready, request a neighbor
if (p2_req_q_almost_full = '0') then
p2_req_q_wr_en <= '1';
p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * unsigned(p1_rsp_q_dout(63 downto 32)), 64));
count_2 <= count_2 + 1;
-- There is more neighbors, go to s2
if (unsigned(p1_rsp_q_dout(31 downto 1)) > 1) then
p2_start_index <= unsigned(p1_rsp_q_dout(63 downto 32)) + 1;
p2_neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1)) - 1;
p2_state <= s2;
-- Reset signals
p1_rsp_q_rd_enb <= '0';
-- It was just one neighbor
else
-- Pop next, keep this state
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
-- Nothing to pop, go to s0
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
end if;
-- p2_req_q is NOT ready
else
-- Save start index and neighbors count, go to s2
p2_start_index <= unsigned(p1_rsp_q_dout(63 downto 32));
p2_neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1));
p2_state <= s2;
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
end if;
-- No neighbors to request
elsif (p1_rsp_q_valid = '1') then
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
-- Data isn't ready yet, keep waiting in s1
else
p2_state <= s1;
-- reset signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
end if;
-- Request more neighbors
when s2 =>
-- There at least one neighbor to request
if (p2_neigh_count > 0) then
-- p2_req_q is ready, request a neighbor
if (p2_req_q_almost_full = '0') then
p2_req_q_wr_en <= '1';
p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * p2_start_index, 64));
count_2 <= count_2 + 1;
p2_start_index <= p2_start_index + 1;
p2_neigh_count <= p2_neigh_count - 1;
-- There is more neighbors, go to s2
if (p2_neigh_count > 1) then
p2_state <= s2;
-- Reset signals
p1_rsp_q_rd_enb <= '0';
-- It was just one neighbor
else
-- Pop next, keep this state
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
-- Nothing to pop, go to s0
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
end if;
-- p2_req_q is NOT ready (i.e. full)
else
-- Save start index and neighbors count, go to s2
p2_start_index <= p2_start_index;
p2_neigh_count <= p2_neigh_count;
p2_state <= s2;
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
end if;
-- No neighbors to request
else
if (p1_rsp_q_empty = '0') then
p1_rsp_q_rd_enb <= '1';
count_1 <= count_1 + 1;
p2_state <= s1;
else
p1_rsp_q_rd_enb <= '0';
p2_state <= s0;
end if;
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
end if;
-- Uknown state
when others =>
-- Reset Signals
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
p2_state <= s0;
end case;
if (p1_done = '1' and count_1 >= p1_count and p2_state = s0 and p2_neigh_count = 0 and p1_rsp_q_valid = '0' and p1_rsp_q_empty = '1') then
p2_done_out <= '1';
else
p2_done_out <= '0';
end if;
-- if (busy = '1') then
-- -- If only one neighbor, and p2 queue not full
-- if (p2_neigh_count = 1 and p2_req_q_almost_full = '0') then
-- -- request the only neighbor
-- p2_req_q_wr_en <= '1';
-- p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * p2_start_index, 64));
-- -- wait for next valid
-- busy <= '0';
-- p2_start_index <= (others => '0');
-- p2_neigh_count <= (others => '0');
-- -- Increment counts
-- count_2 <= count_2 + 1;
-- -- If more than one neighbor, and p2 queue is not full
-- elsif (p2_neigh_count > 1 and p2_req_q_almost_full = '0') then
-- -- request the only neighbor
-- p2_req_q_wr_en <= '1';
-- p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * p2_start_index, 64));
-- busy <= '1';
-- p2_start_index <= p2_start_index + 1;
-- p2_neigh_count <= p2_neigh_count - 1;
-- -- Increment counts
-- count_2 <= count_2 + 1;
-- -- If p2 queue is full and there is neighbors
-- elsif (p2_neigh_count >= 1 and p2_req_q_almost_full = '1') then
-- -- Keep busy
-- busy <= '1';
-- p2_req_q_wr_en <= '0';
-- p2_req_q_din <= (others => '0');
-- -- Else!
-- else
-- busy <= '0';
-- p2_start_index <= (others => '0');
-- p2_neigh_count <= (others => '0');
-- p2_req_q_wr_en <= '0';
-- p2_req_q_din <= (others => '0');
-- end if;
-- elsif (busy = '0' and p1_rsp_q_valid = '1') then
-- -- If only one neighbor, and p2 queue not full
-- if (unsigned(p1_rsp_q_dout(31 downto 1)) = 1 and p2_req_q_almost_full = '0') then
-- -- request the only neighbor
-- p2_req_q_wr_en <= '1';
-- p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * unsigned(p1_rsp_q_dout(63 downto 32)), 64));
-- -- wait for next valid
-- busy <= '0';
-- p2_start_index <= (others => '0');
-- p2_neigh_count <= (others => '0');
-- -- Increment counts
-- count_2 <= count_2 + 1;
-- -- If more than one neighbor, and p2 queue is not full
-- elsif (unsigned(p1_rsp_q_dout(31 downto 1)) > 1 and p2_req_q_almost_full = '0') then
-- -- request the only neighbor
-- p2_req_q_wr_en <= '1';
-- p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * unsigned(p1_rsp_q_dout(63 downto 32)), 64));
-- busy <= '1';
-- p2_start_index <= unsigned(p1_rsp_q_dout(63 downto 32)) + 1;
-- p2_neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1)) - 1;
-- -- Increment counts
-- count_2 <= count_2 + 1;
-- -- If p2 queue is full and there is neighbors
-- elsif (unsigned(p1_rsp_q_dout(31 downto 1)) >= 1 and p2_req_q_almost_full = '1') then
-- -- Save start index and neighbors count
-- p2_start_index <= unsigned(p1_rsp_q_dout(63 downto 32));
-- p2_neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1));
-- -- Go busy
-- busy <= '1';
-- p2_req_q_wr_en <= '0';
-- p2_req_q_din <= (others => '0');
-- -- Else!
-- else
-- busy <= '0';
-- p2_start_index <= (others => '0');
-- p2_neigh_count <= (others => '0');
-- p2_req_q_wr_en <= '0';
-- p2_req_q_din <= (others => '0');
-- end if;
-- else
-- busy <= '0';
-- p2_req_q_wr_en <= '0';
-- p2_req_q_din <= (others => '0');
-- p2_start_index <= (others => '0');
-- p2_neigh_count <= (others => '0');
-- end if;
-- -- if not busy, pop
-- if (p1_rsp_q_empty = '0' and p2_req_q_almost_full = '0' and p1_count > count_1 and p1_rsp_q_rd_en = '0') then
-- if ((busy = '0' and p1_rsp_q_valid = '1' and unsigned(p1_rsp_q_dout(31 downto 1)) <= 1) or (busy = '0' and p1_rsp_q_valid = '0') or (busy = '1' and p2_neigh_count <= 1)) then
-- p1_rsp_q_rd_enb <= '1';
-- else
-- p1_rsp_q_rd_enb <= '0';
-- end if;
-- else
-- p1_rsp_q_rd_enb <= '0';
-- end if;
-- if (p1_rsp_q_valid = '1') then
-- count_1 <= count_1 + 1;
-- end if ;
-- -- Process 2 is done if process 1 is done and p1_count = count_1
-- if (p1_done = '1' and count_1 >= p1_count and busy = '0' and p2_neigh_count = 0 and p1_rsp_q_valid = '0') then
-- p2_done_out <= '1';
-- else
-- p2_done_out <= '0';
-- end if;
else
-- reset everything
p2_state <= s0;
p2_done_out <= '0';
busy <= '0';
count_1 <= (others => '0');
count_2 <= (others => '0');
p2_start_index <= (others => '0');
p2_neigh_count <= (others => '0');
p1_rsp_q_rd_enb <= '0';
p2_req_q_wr_en <= '0';
p2_req_q_din <= (others => '0');
end if; -- end if started
end if; -- end if rst
end if; -- end if clk
end process; -- p2
end architecture; -- arch
| apache-2.0 | 75e6ce4a0a1f697f0d876c4116378864 | 0.480548 | 2.542359 | false | false | false | false |
scarter93/RSA-Encryption | test_module.vhd | 1 | 1,539 | library ieee;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.math_real.all;
library lpm;
use lpm.lpm_components.all;
entity test_module is
Generic( WIDTH_IN : integer := 8
);
Port( N : in integer; --Number
Exp : in real; --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
--latch_in: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0)
);
end entity;
architecture structural of test_module is
signal result : real;
signal result2 : unsigned(WIDTH_IN*WIDTH_IN-1 downto 0);
begin
--divide: LPM_DIVIDE
-- generic map(
-- LPM_WIDTHN => 2*WIDTH_IN,
-- LPM_WIDTHD => WIDTH_IN
-- );
-- port map(
-- numer => ,
-- denom => ,
-- remain =>
-- );
--
--
-- mult : LPM_MULT
-- generic(LPM_WIDTHA : WIDTH_IN;
-- LPM_WIDTHB : WIDTH_IN;
-- LPM_WIDTHS : natural := 1;
-- LPM_WIDTHP : 2*WIDTH_IN;
-- LPM_REPRESENTATION : string := "UNSIGNED";
-- LPM_TYPE: string := L_MULT;
-- LPM_HINT : string := "UNUSED"
-- );
-- port(DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
-- DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
-- ACLR : in std_logic := '0';
-- CLOCK : in std_logic := '0';
-- CLKEN : in std_logic := '1';
-- SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
-- RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0)
--);
--
result <= N**Exp;
result2 <= to_unsigned(integer(result), WIDTH_IN*WIDTH_IN);
C <= result2 mod M;
end architecture; | mit | 17a86e62dc9ad344d8170674452d554d | 0.62833 | 2.635274 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_32_512.vhd | 1 | 70,101 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_32_512.vhd
-- /___/ /\ Timestamp: Mon Jul 14 15:36:13 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_32_512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_32_512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end fifo_generator_32_512;
architecture STRUCTURE of fifo_generator_32_512 is
signal N0 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal N23 : STD_LOGIC;
signal N25 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_5 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000121 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000188_10 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000214_11 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000286_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000069 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_N3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i108_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000131_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000164_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00002_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000067_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb157_46 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_48 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_N3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_81 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_82 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_83 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_84 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_88 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_90 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_91 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_92 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_93 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_5;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_48;
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_5
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_90,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_81
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_90
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_83,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_84
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_92,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_93
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_88,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_82,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_83
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_92,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_91
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_91,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_92
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_83,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_82
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_88
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_48
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_89,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_93,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_91,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_84,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_82,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_111 : LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_N3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_11 : LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_N3,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_111 : LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_N3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_11 : LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_N3,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47,
I1 => wr_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i108 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i108_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb127 : LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000121
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb157 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_81,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb157_46
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb178 : LUT6
generic map(
INIT => X"BABABA32AAAAAA22"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb157_46,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000121,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000069,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000067 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000067_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000131 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000131_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000188 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000188_10
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000214 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000188_10,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000214_11
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000323 : LUT6
generic map(
INIT => X"BBAAB3A2AAAAA2A2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000121,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000214_11,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000069,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000286_12,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i124_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => N19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i124 : LUT6
generic map(
INIT => X"0000842100000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I4 => N19,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i108_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000175 : LUT5
generic map(
INIT => X"FF20FF22"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_81,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00002_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000164_42,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb75_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => N21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb75 : LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I4 => N21,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000069
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000164_SW0 : LUT5
generic map(
INIT => X"5FDFF5FD"
)
port map (
I0 => wr_en,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => N23
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000164 : LUT6
generic map(
INIT => X"0000210000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000067_44,
I4 => N23,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000131_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000164_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000286_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => N25
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000286 : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I4 => N25,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000286_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00002 : LUT4
generic map(
INIT => X"FF75"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_47,
I2 => wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_7,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00002_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_12 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_12 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_11 : LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_11 : LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP :
RAMB18SDP
generic map(
DO_REG => 0,
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
SRVAL => X"000000000"
)
port map (
RDCLK => clk,
WRCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
REGCE => N0,
SSR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDADDR(8) => N0,
RDADDR(7) => N0,
RDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
WRADDR(8) => N0,
WRADDR(7) => N0,
WRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED
,
WE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | cb838018f8f4920b5ab89f0151fc0a2e | 0.669719 | 2.676326 | false | false | false | false |
jaruiz/light8080 | src/vhdl/rtl/mcu/mcu80_irq.vhdl | 1 | 6,591 | --##############################################################################
-- mcu80_l80irq : Interrupt controller for light8080-based mcu80 MCU.
--##############################################################################
--
-- This is a basic interrupt controller for the light8080 core. It is meant for
-- demonstration purposes only (demonstration of the light8080 core) and has
-- not passed any serious verification test bench.
-- It has been built on the same principles as the rest of the modules in this
-- project: no more functionality than strictly needed, minimized area.
--
-- The interrupt controller operates under these rules:
--
-- -# All interrupt inputs are active at rising edge.
-- -# No logic is included for input sinchronization. You must take care to
-- prevent metastability issues yourself by the usual means.
-- -# If a new edge is detected before the first is serviced, it is lost.
-- -# As soon as a rising edge in enabled irq input K is detected, bit K in the
-- interrupt pending register 'irq_pending_reg' will be asserted.
-- Than is, disabled interrupts never get detected at all.
-- -# Output cpu_intr_o will be asserted as long as there's a bit asserted in
-- the interrupt pending register.
-- -# For each interrupt there is a predefined priority level and a predefined
-- interrupt vector -- see comments below.
-- -# As soon as an INTA cycle is done by the CPU (inta=1 and fetch=1) the
-- following will happen:
-- * The module will supply the interrupt vector of the highes priority
-- pending interrupt.
-- * The highest priority pending interrupt bit in the pending interrupt
-- register will be deasserted -- UNLESS the interrupts happens to trigger
-- again at the same time, in which case the pending bit will remain
-- asserted.
-- * If there are no more interrupts pending, the cpu_intr_o output will
-- be deasserted.
-- -# The CPU will have its interrupts disabled from the INTA cycle to the
-- execution of instruction EI.
-- -# The cpu_intr_o will be asserted for a single cycle.
-- -# The irq vectors are hardcoded to RST instructions (single byte calls).
--
-- The priorities and vectors are hardcoded to the following values:
--
-- irq_i(3) Priority 3 Vector RST 7
-- irq_i(2) Priority 2 Vector RST 5
-- irq_i(1) Priority 1 Vector RST 3
-- irq_i(0) Priority 0 Vector RST 1
--
-- (Priority order: 3 > 2 > 1 > 0).
--
-- This module is used in the mcu80 module, for which a basic test bench
-- exists. Both can be used as usage example.
-- The module and its application is so simple than no documentation other than
-- these comments should be necessary.
--
-- Please see the LICENSE file in the project root for license matters.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--##############################################################################
--
--##############################################################################
entity mcu80_irq is
port (
cpu_inta_i : in std_logic;
cpu_intr_o : out std_logic;
cpu_fetch_i : in std_logic;
data_we_i : in std_logic;
addr_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
irq_i : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic
);
end mcu80_irq;
--##############################################################################
--
--##############################################################################
architecture hardwired of mcu80_irq is
-- irq_pending: 1 when irq[i] is pending service
signal irq_pending_reg : std_logic_vector(3 downto 0);
-- irq_enable: 1 when irq[i] is enabled
signal irq_enable_reg : std_logic_vector(3 downto 0);
-- irq_q: registered irq input used to catch rising edges
signal irq_q : std_logic_vector(3 downto 0);
-- irq_trigger: asserted to 1 when a rising edge is detected
signal irq_trigger : std_logic_vector(3 downto 0);
signal irq_clear : std_logic_vector(3 downto 0);
signal irq_clear_mask:std_logic_vector(3 downto 0);
signal data_rd : std_logic_vector(7 downto 0);
signal vector : std_logic_vector(7 downto 0);
signal irq_level : std_logic_vector(2 downto 0);
begin
edge_detection:
for i in 0 to 3 generate
begin
irq_trigger(i) <= '1' when -- IRQ(i) is triggered when...
irq_q(i)='0' and -- ...we see a rising edge...
irq_i(i)='1' and
irq_enable_reg(i)='1' -- ...and the irq input us enabled.
else '0';
end generate edge_detection;
interrupt_pending_reg:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
irq_pending_reg <= (others => '0');
irq_q <= (others => '0');
else
irq_pending_reg <= (irq_pending_reg and (not irq_clear)) or irq_trigger;
irq_q <= irq_i;
end if;
end if;
end process interrupt_pending_reg;
with irq_level select irq_clear_mask <=
"1000" when "111",
"0100" when "101",
"0010" when "011",
"0001" when others;
irq_clear <= irq_clear_mask when cpu_inta_i='1' and cpu_fetch_i='1' else "0000";
interrupt_enable_reg:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- All interrupts disabled at reset
irq_enable_reg <= (others => '0');
else
if data_we_i = '1' and addr_i = '0' then
irq_enable_reg <= data_i(3 downto 0);
end if;
end if;
end if;
end process interrupt_enable_reg;
-- Interrupt priority & vector decoding
irq_level <=
"001" when irq_pending_reg(0) = '1' else
"011" when irq_pending_reg(1) = '1' else
"110" when irq_pending_reg(2) = '1' else
"111";
-- Raise interrupt request when there's any irq pending
cpu_intr_o <= '1' when irq_pending_reg /= "0000" else '0';
-- The IRQ vector is hardcoded to a RST instruction, whose opcode is
-- RST <n> ---> 11nnn111
process(clk)
begin
if clk'event and clk='1' then
if cpu_inta_i='1' and cpu_fetch_i='1' then
vector <= "11" & irq_level & "111";
end if;
end if;
end process;
-- There's only an internal register, the irq enable register, so we
-- don't need an output register mux.
data_rd <= "0000" & irq_enable_reg;
-- The mdule will output the register being read, if any, OR the irq vector.
data_o <= vector when cpu_inta_i = '1' else data_rd;
end hardwired;
| lgpl-2.1 | 969ea4f3fac770a0c35f55abd10f1b2f | 0.601123 | 3.725834 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/ds1722.vhd | 3 | 3,623 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity DS1722 is
Port( CLK_I: in std_logic;
RST_I: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
architecture DS1722_arch of DS1722 is
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
signal state : BIG_STATE;
signal bit_count: INTEGER range 0 to 7;
signal Write: std_logic;
begin
-- divide CLK_I by 256
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then counter <= "00000000";
else counter <= counter + "00000001";
end if;
end if;
end process;
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
Write <= ADDRESS(7);
-- convert byte commands to SPI and SPI to byte.
--
process (CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end process;
end DS1722_arch;
| mit | 4161f664e49b3fbddba6363d1d6efc9e | 0.510903 | 2.75933 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/spi/circular_queue.vhd | 1 | 3,490 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity circular_queue is
generic(
queue_depth : positive;
queue_width : positive
);
port (
ctrl : in ctrl_t;
enqueue : in std_logic;
dequeue : in std_logic;
write_in_data : in std_logic_vector(queue_width - 1 downto 0);
read_out_data : out std_logic_vector(queue_width - 1 downto 0);
empty : out std_logic;
full : out std_logic;
contents_count : out natural range 0 to queue_depth
);
end circular_queue;
architecture rtl of circular_queue is
constant addr_length : integer := integer(ceil(log2(real(queue_depth))));
constant data_width : integer := 8;
--ram signals
signal write_enable : std_logic;
signal read_addr : unsigned(addr_length - 1 downto 0) := (others => '0');
signal next_write_addr : unsigned(addr_length - 1 downto 0) := (others => '0');
--
signal full_int : std_logic := '0';
signal empty_int : std_logic := '0';
signal contents_count_int : natural range 0 to queue_depth;
begin
ram_1 : entity virtual_button_lib.ram
generic map(
depth => queue_depth,
width => queue_width
)
port map (
ctrl => ctrl,
read_addr => read_addr,
next_write_addr => next_write_addr,
write_enable => write_enable,
write_in => write_in_data,
read_out => read_out_data);
calc_contents_count : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
-- the true part is needed because otherwise contents_count would be 0
-- when the fifo was full.
if full_int = '1' then
contents_count_int <= queue_depth;
else
contents_count_int <= natural(to_integer(next_write_addr - read_addr));
end if;
end if;
end process;
full <= full_int;
empty <= empty_int;
contents_count <= contents_count_int;
write_enable <= '1' when full_int = '0' and enqueue = '1'
else '0';
--allow a dequeue to be performed, except when there is nothing left to read.
dequeue_something : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
read_addr <= to_unsigned(0, read_addr'length);
empty_int <= '1';
else
if dequeue = '1' and empty_int = '0' then
read_addr <= read_addr + 1;
if next_write_addr = read_addr + 1 then
empty_int <= '1';
end if;
end if;
if enqueue = '1' and empty_int = '1' then
empty_int <= '0';
end if;
end if;
end if;
end process;
--Allow a write to be performed, except when there is no more room
update_write_address : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
next_write_addr <= to_unsigned(0, next_write_addr'length);
full_int <= '0';
else
if enqueue = '1' and full_int = '0' then
next_write_addr <= next_write_addr + 1;
if next_write_addr + 1 = read_addr then
full_int <= '1';
end if;
end if;
if dequeue = '1' and full_int = '1' then
full_int <= '0';
end if;
end if;
end if;
end process;
end;
| bsd-2-clause | 4e4b96662588f30e62b78f13b11ec9a2 | 0.570774 | 3.504016 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/rtl-debugging/debug_light_generator.vhd | 1 | 5,306 | library ieee;
use ieee.STD_LOGIC_1164.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.ws2812_data.all;
use virtual_button_lib.ws2812_constant_colours.all;
use virtual_button_lib.midi_pkg.all;
entity debug_light_generator is
generic(
spi_tx_max_block_size : integer;
spi_tx_ram_depth : integer
);
port(
ctrl : in ctrl_t;
spi_tx_buffer_full : in std_logic;
contents_count : in integer range 0 to spi_tx_ram_depth;
buttons : in button_arr;
cs_n : in std_logic;
enable_spi_tx : in std_logic;
uart_framing_error : in std_logic;
midi_ram_contents_count : in integer range 0 to midi_file_rx_bram_depth;
enable_decoder : in std_logic;
errors : in errors_t;
run_counter_dbg : in std_logic;
light_square_data : out std_logic
);
end;
architecture rtl of debug_light_generator is
constant num_leds : integer := 64;
signal led_index : integer range 0 to num_leds := 0;
signal ws2812_data : ws2812_array_t(0 to num_leds - 1);
signal current_ws2812 : ws2812_t;
signal contents_count_debug : ws2812_array_t(0 to 7);
signal midi_ram_contents_count_debug : ws2812_array_t(0 to 7);
-- whenever the tx buffer fills all the way up, display a light for 0.5 sec.
signal held_spi_tx_buffer_full : std_logic;
constant spi_tx_buffer_full_counter_limit : integer := 5 sec / clk_period;
signal spi_tx_buffer_full_counter : integer range 0 to spi_tx_buffer_full_counter_limit;
begin
ws2812_drv_1 : entity virtual_button_lib.ws2812_drv
generic map (
num_leds => num_leds)
port map (
ctrl => ctrl,
data_in => current_ws2812,
current_led => led_index,
data_out => light_square_data);
current_ws2812 <= ws2812_data(led_index);
ws2812_colour_select : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
ws2812_data(0) <= ws2812_red;
else
ws2812_data(0) <= ws2812_green;
end if;
-- debug spi transmitter
if held_spi_tx_buffer_full = '1' then
ws2812_data(1) <= ws2812_red;
elsif enable_spi_tx = '1' then
ws2812_data(1) <= ws2812_green;
else
ws2812_data(1) <= ws2812_blue;
end if;
if spi_tx_buffer_full = '1' then
ws2812_data(2) <= ws2812_red;
else
ws2812_data(2) <= ws2812_blue;
end if;
-- uart framing error
if uart_framing_error = '1' then
ws2812_data(3) <= ws2812_blue;
else
ws2812_data(3) <= ws2812_red;
end if;
-- Monitor SPI behaviour
if cs_n = '0' then
ws2812_data(7) <= ws2812_green;
else
ws2812_data(7) <= ws2812_blue;
end if;
ws2812_data(8 to 15) <= contents_count_debug;
ws2812_data(16 to 23) <= midi_ram_contents_count_debug;
if enable_decoder = '1' then
ws2812_data(24) <= ws2812_green;
else
ws2812_data(24) <= ws2812_blue;
end if;
if enable_decoder = '0' then
ws2812_data(25) <= ws2812_blue;
else
if errors.no_mthd = '1' then
ws2812_data(25) <= ws2812_red;
else
ws2812_data(25) <= ws2812_green;
end if;
end if;
if enable_decoder = '0' then
ws2812_data(26) <= ws2812_blue;
else
if errors.not_format_1 = '1' then
ws2812_data(26) <= ws2812_red;
else
ws2812_data(26) <= ws2812_green;
end if;
end if;
-- uart rx run_counter
if run_counter_dbg = '1' then
ws2812_data(60) <= ws2812_blue;
else
ws2812_data(60) <= ws2812_clear;
end if;
if buttons(o).toggle = '1' then
ws2812_data <= (others => ws2812_clear);
end if;
end if;
end process ws2812_colour_select;
hold_full_for_time_secs : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
held_spi_tx_buffer_full <= '0';
spi_tx_buffer_full_counter <= 0;
else
if spi_tx_buffer_full = '1' then
spi_tx_buffer_full_counter <= 0;
held_spi_tx_buffer_full <= '1';
else
if spi_tx_buffer_full_counter < spi_tx_buffer_full_counter_limit then
spi_tx_buffer_full_counter <= spi_tx_buffer_full_counter + 1;
else
held_spi_tx_buffer_full <= '0';
end if;
end if;
end if;
end if;
end process;
debug_spi_contents_count : entity virtual_button_lib.debug_contents_count
generic map (
spi_tx_ram_depth => spi_tx_ram_depth)
port map (
ctrl => ctrl,
contents_count => contents_count,
contents_count_debug => contents_count_debug);
debug_midi_contents_count : entity virtual_button_lib.debug_contents_count
generic map (
spi_tx_ram_depth => midi_file_rx_bram_depth)
port map (
ctrl => ctrl,
contents_count => midi_ram_contents_count,
contents_count_debug => midi_ram_contents_count_debug);
end;
| bsd-2-clause | ac7d2510f0f57399eee8154ba3fde59d | 0.580475 | 3.2977 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/Board_cpu.vhd | 1 | 3,581 | --
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity board_cpu is
PORT ( CLK40 : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
CLK_OUT : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
ENABLE_N : out STD_LOGIC;
DEACTIVATE_N : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
XM_CE_N : out STD_LOGIC;
XM_OE_N : out STD_LOGIC;
XM_WE_N : inout STD_LOGIC;
XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
);
end board_cpu;
architecture behavioral of board_cpu is
COMPONENT cpu16
PORT( CLK_I : in STD_LOGIC;
T2 : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
END COMPONENT;
signal XM_WDAT : std_logic_vector( 7 downto 0);
signal XM_RDAT : std_logic_vector( 7 downto 0);
signal MEM_T : std_logic;
signal XM_WE : std_logic;
signal WE_N : std_logic;
signal DEL_WE_N : std_logic;
signal XM_CE : std_logic;
begin
cp: cpu16
PORT MAP( CLK_I => CLK40,
T2 => CLK_OUT,
SWITCH => SWITCH,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
XM_ADR(14 downto 0) => XM_ADR,
XM_ADR(15) => open,
XM_RDAT => XM_RDAT,
XM_WDAT => XM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SEG1 => SEG1,
SEG2 => SEG2,
LED => LED
);
ENABLE_N <= '0';
DEACTIVATE_N <= '1';
MEM_T <= DEL_WE_N; -- active low
WE_N <= not XM_WE;
XM_OE_N <= XM_WE;
XM_CE_N <= not XM_CE;
p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
end behavioral;
| mit | d974bd5c42fbb7e63e643958c13f5eb8 | 0.559341 | 2.352825 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/std_ovl_u_components.vhd | 1 | 33,122 | -- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
package std_ovl_u_components is
------------------------------------------------------------------------------
-- ovl_always
------------------------------------------------------------------------------
component ovl_always
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_always;
------------------------------------------------------------------------------
-- ovl_never
------------------------------------------------------------------------------
component ovl_never
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never;
------------------------------------------------------------------------------
-- ovl_next
------------------------------------------------------------------------------
component ovl_next
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : positive := 1;
check_overlapping : ovl_chk_overlap := OVL_CHK_OVERLAP_OFF;
check_missing_start : ovl_ctrl := OVL_OFF;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_next;
------------------------------------------------------------------------------
-- ovl_cycle_sequence
------------------------------------------------------------------------------
component ovl_cycle_sequence
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : ovl_positive_2 := 2;
necessary_condition : ovl_necessary_condition := OVL_TRIGGER_ON_MOST_PIPE;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
event_sequence : in std_ulogic_vector(num_cks - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_cycle_sequence;
------------------------------------------------------------------------------
-- ovl_zero_one_hot
------------------------------------------------------------------------------
component ovl_zero_one_hot
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_zero_one_hot;
------------------------------------------------------------------------------
-- ovl_range
------------------------------------------------------------------------------
component ovl_range
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
min : natural := 0;
max : natural := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_range;
------------------------------------------------------------------------------
-- ovl_one_hot
------------------------------------------------------------------------------
component ovl_one_hot
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_one_hot;
------------------------------------------------------------------------------
-- ovl_never_unknown
------------------------------------------------------------------------------
component ovl_never_unknown
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
qualifier : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never_unknown;
------------------------------------------------------------------------------
-- ovl_never_unknown_async
------------------------------------------------------------------------------
component ovl_never_unknown_async
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_never_unknown_async;
------------------------------------------------------------------------------
-- ovl_implication
------------------------------------------------------------------------------
component ovl_implication
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
antecedent_expr : in std_ulogic;
consequent_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end component ovl_implication;
end package std_ovl_u_components;
--------------------------------------------------------------------------------
-- ovl_always
--------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
use accellera_ovl_vhdl.std_ovl_components.all;
entity ovl_always is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_always;
architecture str of ovl_always is
begin
u : entity accellera_ovl_vhdl.ovl_always
generic map (
severity_level => severity_level,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
test_expr => test_expr,
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_never
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_never is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never;
architecture str of ovl_never is
begin
u : entity accellera_ovl_vhdl.ovl_never
generic map (
severity_level => severity_level,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
test_expr => test_expr,
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_next
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_next is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : positive := 1;
check_overlapping : ovl_chk_overlap := OVL_CHK_OVERLAP_OFF;
check_missing_start : ovl_ctrl := OVL_OFF;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
start_event : in std_ulogic;
test_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_next;
architecture str of ovl_next is
begin
u : entity accellera_ovl_vhdl.ovl_next
generic map (
severity_level => severity_level,
num_cks => num_cks,
check_overlapping => check_overlapping,
check_missing_start => check_missing_start,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
start_event => start_event,
test_expr => test_expr,
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_cycle_sequence
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_cycle_sequence is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
num_cks : ovl_positive_2 := 2;
necessary_condition : ovl_necessary_condition := OVL_TRIGGER_ON_MOST_PIPE;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
event_sequence : in std_ulogic_vector(num_cks - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_cycle_sequence;
architecture str of ovl_cycle_sequence is
begin
u : entity accellera_ovl_vhdl.ovl_cycle_sequence
generic map (
severity_level => severity_level,
num_cks => num_cks,
necessary_condition => necessary_condition,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
event_sequence => std_logic_vector(event_sequence),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_zero_one_hot
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_zero_one_hot is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_zero_one_hot;
architecture str of ovl_zero_one_hot is
begin
u : entity accellera_ovl_vhdl.ovl_zero_one_hot
generic map (
severity_level => severity_level,
width => width,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
test_expr => std_logic_vector(test_expr),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_range
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_range is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
min : natural := 0;
max : natural := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_range;
architecture str of ovl_range is
begin
u : entity accellera_ovl_vhdl.ovl_range
generic map (
severity_level => severity_level,
width => width,
min => min,
max => max,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
test_expr => std_logic_vector(test_expr),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_one_hot
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_one_hot is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 32;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_one_hot;
architecture str of ovl_one_hot is
begin
u : entity accellera_ovl_vhdl.ovl_one_hot
generic map (
severity_level => severity_level,
width => width,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
test_expr => std_logic_vector(test_expr),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_never_unknown
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_never_unknown is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
qualifier : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown;
architecture str of ovl_never_unknown is
begin
u : entity accellera_ovl_vhdl.ovl_never_unknown
generic map (
severity_level => severity_level,
width => width,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
qualifier => qualifier,
test_expr => std_logic_vector(test_expr),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_never_unknown_async
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_never_unknown_async is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
reset : in std_ulogic;
enable : in std_ulogic;
test_expr : in std_ulogic_vector(width - 1 downto 0);
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown_async;
architecture str of ovl_never_unknown_async is
begin
u : entity accellera_ovl_vhdl.ovl_never_unknown_async
generic map (
severity_level => severity_level,
width => width,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
reset => reset,
enable => enable,
test_expr => std_logic_vector(test_expr),
std_ulogic_vector(fire) => fire
);
end architecture str;
---------------------------------------------------------------------------------
-- ovl_implication
---------------------------------------------------------------------------------
library ieee, accellera_ovl_vhdl;
use ieee.std_logic_1164.all;
use accellera_ovl_vhdl.std_ovl.all;
entity ovl_implication is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
enable : in std_ulogic;
antecedent_expr : in std_ulogic;
consequent_expr : in std_ulogic;
fire : out std_ulogic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_implication;
architecture str of ovl_implication is
begin
u : entity accellera_ovl_vhdl.ovl_implication
generic map (
severity_level => severity_level,
property_type => property_type,
msg => msg,
coverage_level => coverage_level,
clock_edge => clock_edge,
reset_polarity => reset_polarity,
gating_type => gating_type,
controls => controls
)
port map (
clock => clock,
reset => reset,
enable => enable,
antecedent_expr => antecedent_expr,
consequent_expr => consequent_expr,
std_ulogic_vector(fire) => fire
);
end architecture str;
| mit | d921a4321447d12f721845b72c01a036 | 0.483425 | 3.908662 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc_kernel.vhd | 1 | 35,046 | -- Author: Osama G. Attia
-- email: ogamal [at] iastate dot edu
-- Create Date: 16:48:40 06/23/2014
-- Module Name: scc_kernel - Behavioral
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity scc_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
-- kernels communication signals
kernel_tx_vld : out std_logic; -- 1 if found nextv
kernel_tx_nextv : out std_logic_vector(63 downto 0);
kernel_rx_vld : in std_logic;
kernel_rx_nextv : in std_logic_vector(63 downto 0);
-- Input Graph Prameters (Represented in Custom CSR)
N : in std_logic_vector(63 downto 0);
graph_info : in std_logic_vector(63 downto 0);
rgraph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0); -- Color to be used to color nodes
fw_queue : in std_logic_vector(63 downto 0); -- FW Reach queue pointer (could be FW or BW reach queue)
fw_count : in std_logic_vector(63 downto 0); -- Number of nodes in FW reach queue
bw_queue : in std_logic_vector(63 downto 0); -- BW Reach queue pointer (could be FW or BW reach queue)
bw_count : in std_logic_vector(63 downto 0); -- Number of nodes in BW reach queue
scc_results : in std_logic_vector(63 downto 0); -- Where we store the color of each node
-- Parameters for next kernel
nxtk_rst : out std_logic;
nxtk_enable : out std_logic;
nextk_busy : in std_logic;
nextk_done : in std_logic;
nxtk_N : out std_logic_vector(63 downto 0);
nxtk_graph_info : out std_logic_vector(63 downto 0);
nxtk_rgraph_info : out std_logic_vector(63 downto 0);
nxtk_color : out std_logic_vector(63 downto 0);
nxtk_fw_queue : out std_logic_vector(63 downto 0);
nxtk_fw_count : out std_logic_vector(63 downto 0);
nxtk_bw_queue : out std_logic_vector(63 downto 0);
nxtk_bw_count : out std_logic_vector(63 downto 0);
nxtk_scc_results : out std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0);
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic
);
end scc_kernel;
architecture Behavioral of scc_kernel is
component scc_process1 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
-- Queue pointers
reach_count : in std_logic_vector(63 downto 0); -- Number of nodes in reachability queue
reach_queue : in std_logic_vector(63 downto 0); -- Reach queue pointer (could be FW or BW reach queue)
-- Process 1 signals
p1_done : out std_logic;
-- Process 1 req queue signals
p1_req_q_almost_full : in std_logic;
p1_req_q_wr_en : out std_logic;
p1_req_q_din : out std_logic_vector(63 downto 0)
);
end component;
component scc_process2 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Process 2 information
p2_done : out std_logic;
p2_count : out unsigned(63 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
rgraph_info : in std_logic_vector(63 downto 0);
scc_results : in std_logic_vector(63 downto 0);
-- Process 2 information
p1_done : in std_logic;
p1_count : in unsigned(63 downto 0);
-- Process 2 SCC req queue signals
p2_scc_req_almost_full : in std_logic;
p2_scc_req_wr_en : out std_logic;
p2_scc_req_din : out std_logic_vector(63 downto 0);
-- Process 2 rInfo req queue signals
p2_rInfo_req_almost_full : in std_logic;
p2_rInfo_req_wr_en : out std_logic;
p2_rInfo_req_din : out std_logic_vector(63 downto 0);
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
component scc_process3 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
-- Process 3 information
p3_done : out std_logic;
p3_count : out unsigned(63 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graph_info : in std_logic_vector(63 downto 0);
scc_results : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count : in unsigned(63 downto 0);
-- Process 3 scc wr queue signals
p3_scc_addr_almost_full : in std_logic;
p3_scc_addr_wr_en : out std_logic;
p3_scc_addr_din : out std_logic_vector(63 downto 0);
-- Process 3 info req queue signals
p3_info_req_almost_full : in std_logic;
p3_info_req_wr_en : out std_logic;
p3_info_req_din : out std_logic_vector(63 downto 0);
-- Process 3 id queue signals
p3_id_q_almost_full : in std_logic;
p3_id_q_wr_en : out std_logic;
p3_id_q_din : out std_logic_vector(63 downto 0);
-- Process 1 response queue signals
p1_rsp_q_rd_enb : out std_logic;
p1_rsp_q_dout : in std_logic_vector(63 downto 0);
p1_rsp_q_valid : in std_logic;
p1_rsp_q_empty : in std_logic;
-- Process 2 SCC response queue signals
p2_scc_rsp_rd_enb : out std_logic;
p2_scc_rsp_dout : in std_logic_vector(0 downto 0);
p2_scc_rsp_valid : in std_logic;
p2_scc_rsp_empty : in std_logic;
-- Process 2 rInfo response queue signals
p2_rinfo_rsp_rd_enb : out std_logic;
p2_rinfo_rsp_dout : in std_logic_vector(0 downto 0);
p2_rinfo_rsp_valid : in std_logic;
p2_rinfo_rsp_empty : in std_logic
);
end component;
component scc_master is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
done : out std_logic;
-- Input Graph Pointers (Represented in Custom CSR)
graph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_req_q_rd_enb : out std_logic;
p1_req_q_dout : in std_logic_vector(63 downto 0);
p1_req_q_valid : in std_logic;
p1_req_q_empty : in std_logic;
p1_rsp_q_wr_en : out std_logic;
p1_rsp_q_din : out std_logic_vector(63 downto 0);
p1_rsp_q_almost_full : in std_logic;
-- Process 2 signals
p2_scc_req_rd_enb : out std_logic;
p2_scc_req_dout : in std_logic_vector(63 downto 0);
p2_scc_req_valid : in std_logic;
p2_scc_req_empty : in std_logic;
p2_scc_req_almost_full : in std_logic;
p2_rinfo_req_rd_enb : out std_logic;
p2_rinfo_req_dout : in std_logic_vector(63 downto 0);
p2_rinfo_req_valid : in std_logic;
p2_rinfo_req_empty : in std_logic;
p2_rinfo_req_almost_full : in std_logic;
p2_scc_rsp_wr_en : out std_logic;
p2_scc_rsp_din : out std_logic_vector(0 downto 0);
p2_scc_rsp_almost_full : in std_logic;
p2_rinfo_rsp_wr_en : out std_logic;
p2_rinfo_rsp_din : out std_logic_vector(0 downto 0);
p2_rinfo_rsp_almost_full : in std_logic;
-- Process 3 signals
p3_done : in std_logic;
p3_scc_addr_rd_enb : out std_logic;
p3_scc_addr_dout : in std_logic_vector(63 downto 0);
p3_scc_addr_valid : in std_logic;
p3_scc_addr_empty : in std_logic;
p3_info_req_rd_enb : out std_logic;
p3_info_req_dout : in std_logic_vector(63 downto 0);
p3_info_req_valid : in std_logic;
p3_info_req_empty : in std_logic;
p3_id_q_rd_enb : out std_logic;
p3_id_q_dout : in std_logic_vector(63 downto 0);
p3_id_q_valid : in std_logic;
p3_id_q_empty : in std_logic;
p3_info_rsp_rd_enb : out std_logic;
p3_info_rsp_dout : in std_logic_vector(63 downto 0);
p3_info_rsp_valid : in std_logic;
p3_info_rsp_empty : in std_logic;
p3_info_rsp_wr_en : out std_logic;
p3_info_rsp_din : out std_logic_vector(63 downto 0);
p3_info_rsp_almost_full : in std_logic;
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
component fifo_generator_64_16 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
component fifo_generator_1_d512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(0 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(0 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
component fifo_generator_64_512 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
component fifo_generator_64_d16 is
PORT (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic
);
end component;
-- KERNEL CONTROL signals
signal k_rst : std_logic;
signal k_busy : std_logic;
signal k_done : std_logic;
signal started : std_logic;
signal info_addr : std_logic_vector(63 downto 0);
signal rinfo_addr : std_logic_vector(63 downto 0);
signal reach_queue : std_logic_vector(63 downto 0);
signal reach_count : std_logic_vector(63 downto 0);
signal found_nextv : std_logic; -- 1 if found a possible next start
signal nextk_done_cache : std_logic;
type state_type is (st_idle, st_fw, st_fw_wait, st_bw, st_bw_wait, st_search, st_search_wait, st_flush, st_done);
signal kernel_state : state_type;
-- Master process signals
signal master_done : std_logic;
-- Process 1 signals
signal p1_done : std_logic;
signal p1_count : unsigned(63 downto 0);
signal p1_req_q_rd_enb : std_logic;
signal p1_rsp_q_rd_enb : std_logic;
signal p1_req_q_almost_full : std_logic;
signal p1_req_q_wr_en : std_logic;
signal p1_req_q_rd_en : std_logic;
signal p1_req_q_din : std_logic_vector(63 downto 0);
signal p1_req_q_dout : std_logic_vector(63 downto 0);
signal p1_req_q_valid : std_logic;
signal p1_req_q_full : std_logic;
signal p1_req_q_empty : std_logic;
signal p1_rsp_q_almost_full : std_logic;
signal p1_rsp_q_wr_en : std_logic;
signal p1_rsp_q_rd_en : std_logic;
signal p1_rsp_q_din : std_logic_vector(63 downto 0);
signal p1_rsp_q_dout : std_logic_vector(63 downto 0);
signal p1_rsp_q_valid : std_logic;
signal p1_rsp_q_full : std_logic;
signal p1_rsp_q_empty : std_logic;
-- Process 2 signals
signal p2_done : std_logic;
signal p2_count : unsigned(63 downto 0);
signal p2_scc_req_rd_enb : std_logic;
signal p2_rinfo_req_rd_enb : std_logic;
signal p2_scc_rsp_rd_enb : std_logic;
signal p2_rinfo_rsp_rd_enb : std_logic;
signal p2_scc_req_almost_full : std_logic;
signal p2_scc_req_wr_en : std_logic;
signal p2_scc_req_rd_en : std_logic;
signal p2_scc_req_din : std_logic_vector(63 downto 0);
signal p2_scc_req_dout : std_logic_vector(63 downto 0);
signal p2_scc_req_valid : std_logic;
signal p2_scc_req_full : std_logic;
signal p2_scc_req_empty : std_logic;
signal p2_rinfo_req_almost_full : std_logic;
signal p2_rinfo_req_wr_en : std_logic;
signal p2_rinfo_req_rd_en : std_logic;
signal p2_rinfo_req_din : std_logic_vector(63 downto 0);
signal p2_rinfo_req_dout : std_logic_vector(63 downto 0);
signal p2_rinfo_req_valid : std_logic;
signal p2_rinfo_req_full : std_logic;
signal p2_rinfo_req_empty : std_logic;
signal p2_scc_rsp_almost_full : std_logic;
signal p2_scc_rsp_wr_en : std_logic;
signal p2_scc_rsp_rd_en : std_logic;
signal p2_scc_rsp_din : std_logic_vector(0 downto 0);
signal p2_scc_rsp_dout : std_logic_vector(0 downto 0);
signal p2_scc_rsp_valid : std_logic;
signal p2_scc_rsp_full : std_logic;
signal p2_scc_rsp_empty : std_logic;
signal p2_rinfo_rsp_almost_full : std_logic;
signal p2_rinfo_rsp_wr_en : std_logic;
signal p2_rinfo_rsp_rd_en : std_logic;
signal p2_rinfo_rsp_din : std_logic_vector(0 downto 0);
signal p2_rinfo_rsp_dout : std_logic_vector(0 downto 0);
signal p2_rinfo_rsp_valid : std_logic;
signal p2_rinfo_rsp_full : std_logic;
signal p2_rinfo_rsp_empty : std_logic;
-- Process 3 signals
signal p3_done : std_logic;
signal p3_count : unsigned(63 downto 0);
signal p3_scc_addr_rd_enb : std_logic;
signal p3_info_req_rd_enb : std_logic;
signal p3_id_q_rd_enb : std_logic;
signal p3_info_rsp_rd_enb : std_logic;
signal p3_scc_addr_almost_full : std_logic;
signal p3_scc_addr_wr_en : std_logic;
signal p3_scc_addr_rd_en : std_logic;
signal p3_scc_addr_din : std_logic_vector(63 downto 0);
signal p3_scc_addr_dout : std_logic_vector(63 downto 0);
signal p3_scc_addr_valid : std_logic;
signal p3_scc_addr_full : std_logic;
signal p3_scc_addr_empty : std_logic;
signal p3_info_req_almost_full : std_logic;
signal p3_info_req_wr_en : std_logic;
signal p3_info_req_rd_en : std_logic;
signal p3_info_req_din : std_logic_vector(63 downto 0);
signal p3_info_req_dout : std_logic_vector(63 downto 0);
signal p3_info_req_valid : std_logic;
signal p3_info_req_full : std_logic;
signal p3_info_req_empty : std_logic;
signal p3_id_q_almost_full : std_logic;
signal p3_id_q_wr_en : std_logic;
signal p3_id_q_rd_en : std_logic;
signal p3_id_q_din : std_logic_vector(63 downto 0);
signal p3_id_q_dout : std_logic_vector(63 downto 0);
signal p3_id_q_valid : std_logic;
signal p3_id_q_full : std_logic;
signal p3_id_q_empty : std_logic;
signal p3_info_rsp_almost_full : std_logic;
signal p3_info_rsp_wr_en : std_logic;
signal p3_info_rsp_rd_en : std_logic;
signal p3_info_rsp_din : std_logic_vector(63 downto 0);
signal p3_info_rsp_dout : std_logic_vector(63 downto 0);
signal p3_info_rsp_valid : std_logic;
signal p3_info_rsp_full : std_logic;
signal p3_info_rsp_empty : std_logic;
-- Queues masks make sure that rd signals of synched queus are synched correctly
signal queues_mask1 : std_logic;
signal queues_mask2 : std_logic;
begin
busy <= k_busy or nextk_busy;
done <= k_done;
-- mask rd enable signals with empty signals
queues_mask1 <= not (p1_rsp_q_empty or p2_scc_rsp_empty or p2_rinfo_rsp_empty);
queues_mask2 <= not (p3_id_q_empty or p3_info_rsp_empty);
p1_req_q_rd_en <= p1_req_q_rd_enb and not p1_req_q_empty;
p1_rsp_q_rd_en <= p1_rsp_q_rd_enb and queues_mask1;
p2_scc_req_rd_en <= p2_scc_req_rd_enb and not p2_scc_req_empty;
p2_rinfo_req_rd_en <= p2_rinfo_req_rd_enb and not p2_rinfo_req_empty;
p2_scc_rsp_rd_en <= p2_scc_rsp_rd_enb and queues_mask1;
p2_rinfo_rsp_rd_en <= p2_rinfo_rsp_rd_enb and queues_mask1;
p3_scc_addr_rd_en <= p3_scc_addr_rd_enb and not p3_scc_addr_empty;
p3_info_req_rd_en <= p3_info_req_rd_enb and not p3_info_req_empty;
p3_id_q_rd_en <= p3_id_q_rd_enb and queues_mask2;
p3_info_rsp_rd_en <= p3_info_rsp_rd_enb and queues_mask2;
p1: scc_process1
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => started,
-- Kernel Parameters
kernel_id => kernel_id,
ae_id => ae_id,
kernels_count => kernels_count,
-- Queue pointers
reach_count => reach_count,
reach_queue => reach_queue,
-- Process 1 signals
p1_done => p1_done,
-- Process 1 req queue signals
p1_req_q_almost_full => p1_req_q_almost_full,
p1_req_q_wr_en => p1_req_q_wr_en,
p1_req_q_din => p1_req_q_din
);
p2: scc_process2
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => started,
-- Process 2 information
p2_done => p2_done,
p2_count => p2_count,
-- Input Graph Pointers (Represented in Custom CSR)
rgraph_info => rinfo_addr,
scc_results => scc_results,
-- Process 2 information
p1_done => p1_done,
p1_count => p1_count,
-- Process 2 SCC req queue signals
p2_scc_req_almost_full => p2_scc_req_almost_full,
p2_scc_req_wr_en => p2_scc_req_wr_en,
p2_scc_req_din => p2_scc_req_din,
-- Process 2 rInfo req queue signals
p2_rInfo_req_almost_full => p2_rInfo_req_almost_full,
p2_rInfo_req_wr_en => p2_rInfo_req_wr_en,
p2_rInfo_req_din => p2_rInfo_req_din,
-- MC response port signals
mc_rsp_push => mc_rsp_push,
mc_rsp_data => mc_rsp_data,
mc_rsp_rdctl => mc_rsp_rdctl
);
p3: scc_process3
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => started,
-- Process 3 information
p3_done => p3_done,
p3_count => p3_count,
-- Input Graph Pointers (Represented in Custom CSR)
graph_info => info_addr,
scc_results => scc_results,
-- Process 2 information
p2_done => p2_done,
p2_count => p2_count,
-- Process 3 scc wr queue signals
p3_scc_addr_almost_full => p3_scc_addr_almost_full,
p3_scc_addr_wr_en => p3_scc_addr_wr_en,
p3_scc_addr_din => p3_scc_addr_din,
-- Process 3 info req queue signals
p3_info_req_almost_full => p3_info_req_almost_full,
p3_info_req_wr_en => p3_info_req_wr_en,
p3_info_req_din => p3_info_req_din,
-- Process 3 id queue signals
p3_id_q_almost_full => p3_id_q_almost_full,
p3_id_q_wr_en => p3_id_q_wr_en,
p3_id_q_din => p3_id_q_din,
-- Process 1 response queue signals
p1_rsp_q_rd_enb => p1_rsp_q_rd_enb,
p1_rsp_q_dout => p1_rsp_q_dout,
p1_rsp_q_valid => p1_rsp_q_valid,
p1_rsp_q_empty => p1_rsp_q_empty,
-- Process 2 SCC response queue signals
p2_scc_rsp_rd_enb => p2_scc_rsp_rd_enb,
p2_scc_rsp_dout => p2_scc_rsp_dout,
p2_scc_rsp_valid => p2_scc_rsp_valid,
p2_scc_rsp_empty => p2_scc_rsp_empty,
-- Process 2 rInfo response queue signals
p2_rinfo_rsp_rd_enb => p2_rinfo_rsp_rd_enb,
p2_rinfo_rsp_dout => p2_rinfo_rsp_dout,
p2_rinfo_rsp_valid => p2_rinfo_rsp_valid,
p2_rinfo_rsp_empty => p2_rinfo_rsp_empty
);
p_master: scc_master
port map (
-- control signals
clk => clk,
rst => k_rst,
enable => started,
done => master_done,
-- Input Graph Pointers (Represented in Custom CSR)
graph_info => info_addr,
-- SCC intersection parameters
color => color,
-- Process 1 signals
p1_req_q_rd_enb => p1_req_q_rd_enb,
p1_req_q_dout => p1_req_q_dout,
p1_req_q_valid => p1_req_q_valid,
p1_req_q_empty => p1_req_q_empty,
p1_rsp_q_wr_en => p1_rsp_q_wr_en,
p1_rsp_q_din => p1_rsp_q_din,
p1_rsp_q_almost_full => p1_rsp_q_almost_full,
-- Process 2 signals
p2_scc_req_rd_enb => p2_scc_req_rd_enb,
p2_scc_req_dout => p2_scc_req_dout,
p2_scc_req_valid => p2_scc_req_valid,
p2_scc_req_empty => p2_scc_req_empty,
p2_scc_req_almost_full => p2_scc_req_almost_full,
p2_rinfo_req_rd_enb => p2_rinfo_req_rd_enb,
p2_rinfo_req_dout => p2_rinfo_req_dout,
p2_rinfo_req_valid => p2_rinfo_req_valid,
p2_rinfo_req_empty => p2_rinfo_req_empty,
p2_rinfo_req_almost_full => p2_rinfo_req_almost_full,
p2_scc_rsp_wr_en => p2_scc_rsp_wr_en,
p2_scc_rsp_din => p2_scc_rsp_din,
p2_scc_rsp_almost_full => p2_scc_rsp_almost_full,
p2_rinfo_rsp_wr_en => p2_rinfo_rsp_wr_en,
p2_rinfo_rsp_din => p2_rinfo_rsp_din,
p2_rinfo_rsp_almost_full => p2_rinfo_rsp_almost_full,
-- Process 3 signals
p3_done => p3_done,
p3_scc_addr_rd_enb => p3_scc_addr_rd_enb,
p3_scc_addr_dout => p3_scc_addr_dout,
p3_scc_addr_valid => p3_scc_addr_valid,
p3_scc_addr_empty => p3_scc_addr_empty,
p3_info_req_rd_enb => p3_info_req_rd_enb,
p3_info_req_dout => p3_info_req_dout,
p3_info_req_valid => p3_info_req_valid,
p3_info_req_empty => p3_info_req_empty,
p3_id_q_rd_enb => p3_id_q_rd_enb,
p3_id_q_dout => p3_id_q_dout,
p3_id_q_valid => p3_id_q_valid,
p3_id_q_empty => p3_id_q_empty,
p3_info_rsp_rd_enb => p3_info_rsp_rd_enb,
p3_info_rsp_dout => p3_info_rsp_dout,
p3_info_rsp_valid => p3_info_rsp_valid,
p3_info_rsp_empty => p3_info_rsp_empty,
p3_info_rsp_wr_en => p3_info_rsp_wr_en,
p3_info_rsp_din => p3_info_rsp_din,
p3_info_rsp_almost_full => p3_info_rsp_almost_full,
-- MC request port signals
mc_req_ld => mc_req_ld,
mc_req_st => mc_req_st,
mc_req_size => mc_req_size,
mc_req_vaddr => mc_req_vaddr,
mc_req_wrd_rdctl => mc_req_wrd_rdctl,
mc_rd_rq_stall => mc_rd_rq_stall,
mc_wr_rq_stall => mc_wr_rq_stall,
-- MC response port signals
mc_rsp_push => mc_rsp_push,
mc_rsp_stall => mc_rsp_stall,
mc_rsp_data => mc_rsp_data,
mc_rsp_rdctl => mc_rsp_rdctl
);
-- Process 1 request queue
p1_req_q : fifo_generator_64_16
port map (
clk => clk,
rst => k_rst,
almost_full => p1_req_q_almost_full,
wr_en => p1_req_q_wr_en,
rd_en => p1_req_q_rd_enb,
din => p1_req_q_din,
dout => p1_req_q_dout,
full => p1_req_q_full,
empty => p1_req_q_empty,
valid => p1_req_q_valid
);
-- process 1 response queue
p1_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p1_rsp_q_almost_full,
wr_en => p1_rsp_q_wr_en,
rd_en => p1_rsp_q_rd_en,
din => p1_rsp_q_din,
dout => p1_rsp_q_dout,
full => p1_rsp_q_full,
empty => p1_rsp_q_empty,
valid => p1_rsp_q_valid
);
-- process 2 SCC request queue
p2_scc_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_scc_req_almost_full,
wr_en => p2_scc_req_wr_en,
rd_en => p2_scc_req_rd_en,
din => p2_scc_req_din,
dout => p2_scc_req_dout,
full => p2_scc_req_full,
empty => p2_scc_req_empty,
valid => p2_scc_req_valid
);
-- process 2 rInfo request queue
p2_rinfo_req_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_rinfo_req_almost_full,
wr_en => p2_rinfo_req_wr_en,
rd_en => p2_rinfo_req_rd_en,
din => p2_rinfo_req_din,
dout => p2_rinfo_req_dout,
full => p2_rinfo_req_full,
empty => p2_rinfo_req_empty,
valid => p2_rinfo_req_valid
);
-- process 2 SCC response queue
p2_scc_rsp_q : fifo_generator_1_d512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_scc_rsp_almost_full,
wr_en => p2_scc_rsp_wr_en,
rd_en => p2_scc_rsp_rd_en,
din => p2_scc_rsp_din,
dout => p2_scc_rsp_dout,
full => p2_scc_rsp_full,
empty => p2_scc_rsp_empty,
valid => p2_scc_rsp_valid
);
-- process 2 rInfo response queue
p2_rinfo_rsp_q : fifo_generator_1_d512
port map (
clk => clk,
rst => k_rst,
almost_full => p2_rinfo_rsp_almost_full,
wr_en => p2_rinfo_rsp_wr_en,
rd_en => p2_rinfo_rsp_rd_en,
din => p2_rinfo_rsp_din,
dout => p2_rinfo_rsp_dout,
full => p2_rinfo_rsp_full,
empty => p2_rinfo_rsp_empty,
valid => p2_rinfo_rsp_valid
);
-- process 3 scc write request queue (nodes to be colored)
p3_scc_addr_q : fifo_generator_64_16
port map (
clk => clk,
rst => k_rst,
almost_full => p3_scc_addr_almost_full,
wr_en => p3_scc_addr_wr_en,
rd_en => p3_scc_addr_rd_en,
din => p3_scc_addr_din,
dout => p3_scc_addr_dout,
full => p3_scc_addr_full,
empty => p3_scc_addr_empty,
valid => p3_scc_addr_valid
);
-- process 3 info request queue
p3_info_req_q : fifo_generator_64_16
port map (
clk => clk,
rst => k_rst,
almost_full => p3_info_req_almost_full,
wr_en => p3_info_req_wr_en,
rd_en => p3_info_req_rd_en,
din => p3_info_req_din,
dout => p3_info_req_dout,
full => p3_info_req_full,
empty => p3_info_req_empty,
valid => p3_info_req_valid
);
-- process 3 id queue (nodes that have to be recovered)
p3_id_q : fifo_generator_64_16
port map (
clk => clk,
rst => k_rst,
almost_full => p3_id_q_almost_full,
wr_en => p3_id_q_wr_en,
rd_en => p3_id_q_rd_en,
din => p3_id_q_din,
dout => p3_id_q_dout,
full => p3_id_q_full,
empty => p3_id_q_empty,
valid => p3_id_q_valid
);
-- process 3 info response queue
p3_info_rsp_q : fifo_generator_64_512
port map (
clk => clk,
rst => k_rst,
almost_full => p3_info_rsp_almost_full,
wr_en => p3_info_rsp_wr_en,
rd_en => p3_info_rsp_rd_en,
din => p3_info_rsp_din,
dout => p3_info_rsp_dout,
full => p3_info_rsp_full,
empty => p3_info_rsp_empty,
valid => p3_info_rsp_valid
);
-- Avoid rst signal fanout problem
p_rst : process(clk)
begin
if (rising_edge(clk)) then
k_rst <= rst;
if (k_rst = '1') then
nxtk_rst <= '0';
nxtk_enable <= '0';
nxtk_N <= (others => '0');
nxtk_graph_info <= (others => '0');
nxtk_rgraph_info <= (others => '0');
nxtk_color <= (others => '0');
nxtk_fw_queue <= (others => '0');
nxtk_fw_count <= (others => '0');
nxtk_bw_queue <= (others => '0');
nxtk_bw_count <= (others => '0');
nxtk_scc_results <= (others => '0');
nextk_done_cache <= '0';
else
if (nextk_done = '1') then
nextk_done_cache <= '1';
end if;
nxtk_rst <= rst;
nxtk_enable <= enable;
nxtk_N <= N;
nxtk_graph_info <= graph_info;
nxtk_rgraph_info <= rgraph_info;
nxtk_color <= color;
nxtk_fw_queue <= fw_queue;
nxtk_fw_count <= fw_count;
nxtk_bw_queue <= bw_queue;
nxtk_bw_count <= bw_count;
nxtk_scc_results <= scc_results;
end if;
end if;
end process; -- rst
-- KERNEL CONTROL
p0 : process(clk, k_rst)
begin
if rising_edge(clk) then
if (k_rst = '1') then
k_busy <= '0';
k_done <= '0';
started <= '0';
info_addr <= (others => '0');
rinfo_addr <= (others => '0');
reach_queue <= (others => '0');
reach_count <= (others => '0');
mc_req_flush <= '0';
kernel_state <= st_idle;
else
case(kernel_state) is
when st_idle =>
k_done <= '0';
if (enable = '1') then
k_busy <= '1';
started <= '1';
info_addr <= graph_info;
rinfo_addr <= rgraph_info;
reach_queue <= fw_queue;
reach_count <= fw_count;
kernel_state <= st_fw_wait;
else
k_busy <= '0';
started <= '0';
info_addr <= (others => '0');
rinfo_addr <= (others => '0');
reach_queue <= (others => '0');
reach_count <= (others => '0');
kernel_state <= st_idle;
end if ;
when st_fw_wait =>
if (master_done = '1') then
started <= '0';
kernel_state <= st_bw;
else
started <= '1';
kernel_state <= st_fw_wait;
end if;
when st_bw =>
started <= '1';
info_addr <= rgraph_info;
rinfo_addr <= graph_info;
reach_queue <= bw_queue;
reach_count <= bw_count;
kernel_state <= st_bw_wait;
when st_bw_wait =>
if (master_done = '1') then
started <= '0';
mc_req_flush <= '1';
kernel_state <= st_flush;
-- elsif (master_done = '1' and found_nextv = '0') then
-- started <= '0';
-- kernel_state <= st_search;
else
started <= '1';
kernel_state <= st_bw_wait;
end if;
when st_flush =>
mc_req_flush <= '0';
if (mc_rsp_flush_cmplt = '1') then
kernel_state <= st_done;
else
kernel_state <= st_flush;
end if;
when st_done =>
if (nextk_done_cache = '1') then
k_busy <= '0';
k_done <= '1';
started <= '0';
kernel_state <= st_idle;
else
kernel_state <= st_done;
end if;
when others =>
kernel_state <= st_idle;
end case ;
end if; -- end if rst
end if; -- end if clk
end process; -- end process 0
-- Kernel-to-kernel communication
k2k : process(clk, k_rst)
begin
if rising_edge(clk) then
if (k_rst = '1') then
found_nextv <= '0';
kernel_tx_vld <= '0';
kernel_tx_nextv <= (others => '0');
else
if (enable = '1') then
found_nextv <= '0';
kernel_tx_vld <= '0';
kernel_tx_nextv <= (others => '0');
elsif (kernel_rx_vld = '1' and found_nextv = '0') then
found_nextv <= '1';
kernel_tx_vld <= '1';
kernel_tx_nextv <= kernel_rx_nextv;
-- elsif (kernel_state = st_search and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"07") then
-- found_nextv <= '1';
-- kernel_tx_vld <= '1';
-- kernel_tx_nextv <= mc_rsp_data;
elsif (p3_id_q_wr_en = '1' and found_nextv = '0') then
found_nextv <= '1';
kernel_tx_vld <= '1';
kernel_tx_nextv <= p1_rsp_q_dout; -- kernel_tx_nextv <= p3_id_q_din;
else
kernel_tx_vld <= '0';
found_nextv <= found_nextv;
end if;
end if; -- end if rst
end if; -- end if clk
end process; -- end process requests multiplexer
p1count : process (clk, k_rst)
begin
if (rising_edge(clk)) then
if (k_rst = '1' or started /= '1') then
p1_count <= (others => '0');
else
if (p1_req_q_wr_en = '1') then
p1_count <= p1_count + 1;
end if;
end if;
end if;
end process; -- p1count
end Behavioral;
| apache-2.0 | cab2061d340dd56da745abcdf4508682 | 0.540404 | 2.73178 | false | false | false | false |
zambreno/RCL | parallelCyGraph/vhdl/project/testbench/process3_tb.vhd | 1 | 3,562 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description: Process 3 testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
ENTITY process3_tb IS
END process3_tb;
ARCHITECTURE behavior OF process3_tb IS
component process3
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 signals
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal started : std_logic := '0';
signal graphInfo : std_logic_vector(63 downto 0) := (others => '0');
signal p2_done : std_logic := '0';
signal p2_count_2 : std_logic_vector(31 downto 0) := (others => '0');
signal p3_req_q_almost_full : std_logic := '0';
signal p3_req_q_full : std_logic := '0';
signal mc_rsp_push : std_logic := '0';
signal mc_rsp_data : std_logic_vector(63 downto 0) := (others => '0');
signal mc_rsp_rdctl : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal p3_done : std_logic;
signal p3_count : std_logic_vector(31 downto 0);
signal p3_req_q_wr_en : std_logic;
signal p3_req_q_din : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: process3
port map (
-- control signals
clk => clk,
rst => rst,
started => started,
-- Process 3 signals
p3_done => p3_done,
p3_count => p3_count,
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo => graphInfo,
-- Process 2 information
p2_done => p2_done,
p2_count_2 => p2_count_2,
-- Process 3 req queue signals
p3_req_q_almost_full => p3_req_q_almost_full,
p3_req_q_wr_en => p3_req_q_wr_en,
p3_req_q_din => p3_req_q_din,
p3_req_q_full => p3_req_q_full,
-- MC response port signals
mc_rsp_push => mc_rsp_push,
mc_rsp_data => mc_rsp_data,
mc_rsp_rdctl => mc_rsp_rdctl
);
-- Clock process definitions
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| apache-2.0 | c0df5f0708dc1ac92fe51c2200c06b5b | 0.537339 | 3.16341 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/sinewave/sine_lut_pkg.vhd | 1 | 2,624 | -- Functions for implementing the sine wave lookup tables which are described
-- in midi_pkg.vhd.
--
-- The actual sine wave LUTs will take advantage of that fact that sine waves
-- have two axes of symmetry. Thus only 1/4 of a sinewave is stored in the
-- lookup tables. midi_pkg will never know this.
--
-- This sine lut will go into block ram. For whatever number of brams are used
-- to hold the sine lut, we will aim to fill them all the way up. the the size
-- of the LUT is expressed in terms of block rams
-- TODO: this package seems very friendly with midi_pkg, which is currently more
-- interested in the details of sine generation than anything really to do with
-- midi. Sort it out so that it makes more sense.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
package sine_lut_pkg is
-- Each bram is 1024 entries long.
constant sine_addr_max : integer := sine_lut_bram_depth * 4 - 1;
-- The width of each entry is 16 bits. This will be inefficient when
-- num_lut_entries is low, because num_lut_entries will not provide enough
-- precision to make use of 16 bits of width.
--
-- However since Spartan 6 block RAM can only store data of widths 1, 2, 4, 8,
-- 16 and 32, no other width makes sense. 8 bits will give poor fidelity and 32
-- bits will give wasteful fidelity.
-- TWEAKABLE
constant lut_width : integer := 16;
type sine_lut_arr is array (0 to sine_lut_bram_depth - 1) of signed(lut_width - 1 downto 0);
-- Function to produce the constant data needed for the LUT.
-- Should be run at elaboration time only.
function calc_sine_lut return sine_lut_arr;
end;
package body sine_lut_pkg is
function calc_sine_lut return sine_lut_arr is
variable ret : sine_lut_arr;
-- The proportion of the way we are round the first quarter of a circle.
-- VHDL sine is in radians, so this will count from 0 to pi.
variable proportion : real;
begin
-- TODO: Some of the mathsy code here is a bit ugly. Can I make it prettier?
for i in 0 to sine_lut_bram_depth - 1 loop
proportion := 0.25 * real(i) * (math_2_pi / real(sine_lut_bram_depth));
ret(i) := to_signed(integer(sin(proportion) *
real(2**(lut_width - 1))), lut_width);
-- correct an error where sin(x) = 1 is recorded as sin(x) = -1
if i /= 0 then
if ret(i) = -(2**(lut_width-1)) and ret(i - 1) > 0 then
ret(i) := ret(i - 1);
end if;
end if;
end loop;
return ret;
end;
end;
| bsd-2-clause | 676855e7e97bc82915a0a297d6cccd31 | 0.673399 | 3.508021 | false | false | false | false |
willtmwu/vhdlExamples | Basic Event Logic/practop_asynchro.vhd | 1 | 6,165 | ----------------------------------------------------------------------------------
-- Company: University of Queensland
-- Engineer: MDS
--
-- Create Date: 25/07/2014
-- Design Name:
-- Module Name: pracTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practop_asynchro is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end practop_asynchro;
architecture Behavioral of practop_asynchro is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component clockedRegister port (
D : in STD_LOGIC_VECTOR (15 downto 0);
E : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal currentState : std_logic_vector(2 downto 0);
signal openLock : std_logic := '0';
signal closeLock : std_logic := '0';
signal correctAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal incorrectAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal displayKey : std_logic_vector(15 downto 0);
signal upperKey : std_logic_vector(7 downto 0);
signal lowerKey : std_logic_vector(7 downto 0);
signal checkKey : std_logic_vector(15 downto 0);
signal regEnable : std_logic;
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : clockedRegister port map (
D (7 downto 0) => lowerKey,
D (15 downto 8) => upperKey,
E => regEnable,
clk => clk100mhz,
reset => masterReset,
Q => checkKey
);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
logic_analyzer <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
regEnable <= '1';
process (masterReset, button1, displayKey) begin
if (masterReset = '1') then
lowerKey <= (others => '0');
displayKey(7 downto 0) <= "00000000";
elsif (button1'event and button1 = '1') then
displayKey(7 downto 0) <= slideSwitches(7 downto 0);
lowerKey <= slideSwitches(7 downto 0);
end if;
end process;
process (masterReset, button2, displayKey) begin
if (masterReset = '1') then
upperKey <= (others => '0');
displayKey (15 downto 8) <= "00000000";
elsif (button2'event and button2 = '1') then
displayKey (15 downto 8) <= slideSwitches(7 downto 0);
upperKey <= slideSwitches(7 downto 0);
end if;
end process;
--digit6 <= lowerKey(7 downto 4);
--digit5 <= lowerKey(3 downto 0);
--digit8 <= lowerKey(7 downto 4);
--digit7 <= lowerKey(3 downto 0);
process (masterReset, submitButton, button1, button2, displayKey) begin
if (masterReset = '1' or button1 = '1' or button2 = '1') then
openLock <= '0';
closeLock <= '0';
elsif (submitButton'event and submitButton = '1') then
if (lowerKey = "11111111" and upperKey = "11111110") then
openLock <= '1';
closeLock <= '0';
else
openLock <= '0';
closeLock <= '1';
end if;
end if;
end process;
process (openLock , clockScalers) begin
LEDs (15 downto 2) <= clockScalers(26 downto 13);
if(openLock = '1') then
LEDs(0) <= '0';
LEDs(1) <= '1';
else
LEDs(0) <= '1';
LEDs(1) <= '0';
end if;
end process;
digit6 <= incorrectAttempts(7 downto 4);
digit5 <= incorrectAttempts(3 downto 0);
digit8 <= correctAttempts(7 downto 4);
digit7 <= correctAttempts(3 downto 0);
process (masterReset, openlock) begin
if (masterReset = '1') then
correctAttempts <= (others => '0');
elsif (openLock'event and openLock = '1' ) then
correctAttempts <= correctAttempts + '1';
end if;
end process;
process (masterReset, closelock) begin
if (masterReset = '1') then
incorrectAttempts <= (others => '0');
elsif (closeLock'event and closeLock = '1' ) then
incorrectAttempts <= incorrectAttempts + '1';
end if;
end process;
end Behavioral;
| apache-2.0 | 37eb17922ecefb6bd190e73a6c1df585 | 0.624006 | 3.118361 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/PIPO10/PIPO10_tb.vhd | 1 | 2,050 | library ieee;
use ieee.std_logic_1164.all;
entity PIPO10_tb is
end PIPO10_tb;
architecture tb of PIPO10_tb is
component PIPO10
port ( Rin : in STD_LOGIC_VECTOR (9 downto 0);
CLK, Preset, Clear: in STD_LOGIC;
Rout : out STD_LOGIC_VECTOR (9 downto 0));
end component;
signal Rin: std_logic_vector(9 downto 0);
signal CLK,Preset,Clear : std_logic := '1';
signal Rout: std_logic_vector(9 downto 0);
-- constant CLK_period : time := 5 ns;
begin
-- preset<='1';
-- clear<='1';
mapping: PIPO10 port map(Rin,CLK,Preset,Clear,Rout);
-- process
-- begin
-- CLK <= '0';
-- wait for CLK_period/2;
-- CLK <= '1';
-- wait for CLK_period/2;
-- end process;
process
begin
Rin(9) <= '0'; wait for 1024 ps;
Rin(9) <= '1'; wait for 1024 ps;
end process;
process
begin
Rin(8) <= '0'; wait for 512 ps;
Rin(8) <= '1'; wait for 512 ps;
end process;
process
begin
Rin(7) <= '0'; wait for 256 ps;
Rin(7) <= '1'; wait for 256 ps;
end process;
process
begin
Rin(6) <= '0'; wait for 128 ps;
Rin(6) <= '1'; wait for 128 ps;
end process;
process
begin
Rin(5) <= '0'; wait for 64 ps;
Rin(5) <= '1'; wait for 64 ps;
end process;
process
begin
Rin(4) <= '0'; wait for 32 ps;
Rin(4) <= '1'; wait for 32 ps;
end process;
process
begin
Rin(3) <= '0'; wait for 16 ps;
Rin(3) <= '1'; wait for 16 ps;
end process;
process
begin
Rin(2) <= '0'; wait for 8 ps;
Rin(2) <= '1'; wait for 8 ps;
end process;
process
begin
Rin(1) <= '0'; wait for 4 ps;
Rin(1) <= '1'; wait for 4 ps;
end process;
process
begin
Rin(0) <= '0'; wait for 2 ps;
Rin(0) <= '1'; wait for 2 ps;
end process;
process
begin
CLK <= '0'; wait for 1 ps;
CLK <= '1'; wait for 1 ps;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of PIPO10_tb is
for tb
end for;
end cfg_tb; | mit | c64d92fb9c584ca54eaccae0e9a6ab78 | 0.52878 | 2.887324 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_1/adder.vhdl | 1 | 917 | -- adder
-- An N-bit adder, with carrying.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity adder is
generic(n: integer);
port(
x: in std_logic_vector(n-1 downto 0);
y: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic
);
end entity;
architecture rtl of adder is
component fulladder is
port(
x, y, cin: in std_logic;
cout, sum: out std_logic
);
end component;
signal c : std_logic_vector(n downto 0);
begin
c(0) <= cin;
addloop:
for i in 0 to n-1 generate
begin
fulladder_instance: fulladder port map (
x => x(i),
y => y(i),
cin => c(i),
cout => c(i+1),
sum => s(i)
);
end generate;
cout <= c(n);
end architecture;
| unlicense | b256e9327d42ae9155b67d45190fd6c0 | 0.513631 | 3.473485 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/midi_ram_top.vhd | 1 | 3,514 | -- Top level file for midi ram. Support a simple write interface and a more
-- complex read interface.
--
-- The write interface is a single-clock interface. When enqueue is strobed,
-- data present on that clock cycle will be written into ram.
--
-- The read interface supports the reading of multiple bytes of data. A start
-- address and a num
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity midi_ram_top is
generic (
max_read_bytes : integer;
queue_width : integer
);
port(
-- clocking interfaces
ctrl : in ctrl_t;
-- write interface
enqueue : in std_logic;
write_in_data : in std_logic_vector(queue_width - 1 downto 0);
-- ram statuses
empty : out std_logic;
full : out std_logic;
contents_count : out natural range 0 to midi_file_rx_bram_depth;
-- read interface
read_start_addr : in unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
read_num_bytes : in integer range 0 to max_read_bytes;
read_en : in std_logic;
read_busy : out std_logic;
midi_ram_out : out std_logic_vector((max_read_bytes * 8) - 1 downto 0)
);
end;
architecture rtl of midi_ram_top is
signal read_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal current_read_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
signal byte_counter : integer range 0 to max_read_bytes;
signal read_en_d1 : std_logic;
signal midi_ram_out_int : std_logic_vector((max_read_bytes * 8) - 1 downto 0);
signal read_out_data : std_logic_vector(7 downto 0);
type state_t is (idle, read_1, read_2);
signal state : state_t;
begin
midi_ram_1 : entity virtual_button_lib.midi_ram
generic map (
queue_depth => midi_file_rx_bram_depth,
queue_width => queue_width)
port map (
ctrl => ctrl,
enqueue => enqueue,
write_in_data => write_in_data,
read_addr => read_addr,
read_out_data => read_out_data,
empty => empty,
full => full,
contents_count => contents_count);
set_read_en_d1 : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
read_en_d1 <= read_en;
end if;
end process;
go : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
byte_counter <= 0;
state <= idle;
read_addr <= (others => '0');
else
case state is
when idle =>
if read_en = '1' and read_en_d1 = '0' then
read_addr <= read_start_addr;
byte_counter <= read_num_bytes;
state <= read_1;
end if;
when read_1 =>
state <= read_2;
byte_counter <= byte_counter - 1;
when read_2 =>
midi_ram_out_int <= midi_ram_out_int(midi_ram_out'left - 8 downto 0) & read_out_data;
if byte_counter = 0 then
state <= idle;
else
read_addr <= read_addr + 1;
state <= read_1;
end if;
end case;
end if;
end if;
end process;
read_busy <= '0' when state = idle else
'1';
midi_ram_out <= midi_ram_out_int;
end;
| bsd-2-clause | 9df1c25ae9597c70262b9d54060b714b | 0.577689 | 3.458661 | false | false | false | false |
jaruiz/light8080 | src/vhdl/rtl/mcu/mcu80_pkg.vhdl | 1 | 3,231 | --------------------------------------------------------------------------------
-- mcu80_pkg.vhdl -- Support package for Light8080 MCU.
--
-- Contains functions used to initialize internal BRAM with object code.
--
-- This package will be used from the object code package where the program
-- initialized RAM constant is defined. If you use script obj2hdl it will
-- take care of this for you.
-- The package is used in entity mcu80 too, and nowhere else.
--
-- Please see the LICENSE file in the project root for license matters.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu80_pkg is
-- Global signals for the TB to use in lieu of hierarchical names.
signal mon_addr : std_logic_vector(15 downto 0);
signal mon_fetch : std_logic;
signal mon_we : std_logic;
signal mon_wdata : std_logic_vector(7 downto 0);
signal mon_uart_ce : std_logic;
-- Basic array type for the declaration of initialization constants.
-- This type is meant to be used to declare a constant with the object code
-- that is to be preprogrammed in an initialized RAM.
type obj_code_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Basic array type for the definition of initialized RAMs.
type ram_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
--
-- oC: Object code table (as generated by utility script obj2hdl for instance).
-- size: Size of the target memory.
-- Returns ram_t value size-bytes long, suitable for synth-time initialization
-- of a BRAM.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t;
-- Compute log2(A), rounding up.
-- Use this to get the minimum width of the address bus necessary to
-- address A locations.
function log2(A : natural) return natural;
end package;
package body mcu80_pkg is
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t is
variable br : ram_t(integer range 0 to size-1);
variable i : integer;
variable obj_size : integer;
begin
-- If the object code table is longer than the array size, truncate code
if oC'length > size then
obj_size := size;
else
obj_size := oC'length;
end if;
-- Copy object code to start of BRAM...
for i in 0 to obj_size-1 loop
br(i) := oC(oC'low + i);
end loop;
-- ... and fill the rest with zeros
br(obj_size to size-1) := (others => x"00");
return br;
end function objcode_to_bram;
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
end package body;
| lgpl-2.1 | 869f655e88715044d0121432fc40ccae | 0.666667 | 3.911622 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/test_fsm_controller.vhd | 1 | 2,391 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_controller IS
END test_fsm_controller;
ARCHITECTURE behavior OF test_fsm_controller IS
COMPONENT fsm_controller
PORT(
masterReset : IN std_logic;
buttonDown : IN std_logic;
en1 : OUT std_logic;
en2 : OUT std_logic
);
END COMPONENT;
--Inputs
signal masterReset : std_logic := '0';
signal buttonDown : std_logic := '0';
--Outputs
signal en1 : std_logic;
signal en2 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant buttonDown_period : time := 10 ns;
TYPE timer_state_fsm IS (start, stop1, stop2);
signal timer_state : timer_state_fsm := start;
signal counter_state : std_logic_vector(3 downto 0) := (others => '0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fsm_controller PORT MAP (
masterReset => masterReset,
buttonDown => buttonDown,
en1 => en1,
en2 => en2
);
-- Clock process definitions
buttonDown_process :process
begin
buttonDown <= '0';
wait for buttonDown_period/2;
buttonDown <= '1';
wait for buttonDown_period/2;
end process;
-- Stimulus process
process (buttonDown) begin
if (buttonDown'event and buttonDown = '1') then
counter_state <= counter_state + '1';
case timer_state is
when start =>
if counter_state = 1 then
if masterReset = '1' then
counter_state <= (others => '0');
timer_state <= stop1;
masterReset <= '0'
end if;
masterReset <= 1;
counter_staet <= counter_state - '1';
end if;
when stop1 =>
if counter_state = 2 then
if masterReset = '1' then
counter_state <= (others => '0');
timer_state <= stop2;
masterReset <= '0'
end if;
masterReset <= 1;
counter_staet <= counter_state - '1';
end if;
when stop2 =>
if counter_state = 3 then
if masterReset = '1' then
counter_state <= (others => '0');
timer_state <= stop1;
masterReset <= '0'
end if;
masterReset <= 1;
counter_staet <= counter_state - '1';
end if;
end case;
end if;
end process;
END;
| apache-2.0 | 3a4599b65850ea9977999f73bc31d18c | 0.558762 | 3.584708 | false | false | false | false |
zambreno/RCL | parallelCyGraph/coregen/fifo_generator_32_512.vhd | 1 | 106,868 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_32_512.vhd
-- /___/ /\ Timestamp: Thu Jul 25 19:19:26 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_32_512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_32_512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_32_512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end fifo_generator_32_512;
architecture STRUCTURE of fifo_generator_32_512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"F3A2F300FFA2FF00"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP :
RAMB18SDP
generic map(
DO_REG => 0,
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
SRVAL => X"000000000"
)
port map (
RDCLK => clk,
WRCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
REGCE => N0,
SSR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
WRADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDR(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDR(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDR(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDR(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDR(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDR(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM18_TDP_DOP_0_UNCONNECTED
,
WE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 7c6a74d0e3ddc6f47e3b4b626d70ca8d | 0.659711 | 2.613229 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_d32.vhd | 1 | 129,460 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_d32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 14:58:26 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_d32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_d32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_d32;
architecture STRUCTURE of fifo_generator_64_d32 is
signal N0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44;
dout(63) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63);
dout(62) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62);
dout(61) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61);
dout(60) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60);
dout(59) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59);
dout(58) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58);
dout(57) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57);
dout(56) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56);
dout(55) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55);
dout(54) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54);
dout(53) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53);
dout(52) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52);
dout(51) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51);
dout(50) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50);
dout(49) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49);
dout(48) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48);
dout(47) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47);
dout(46) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46);
dout(45) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45);
dout(44) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44);
dout(43) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43);
dout(42) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42);
dout(41) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41);
dout(40) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40);
dout(39) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39);
dout(38) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38);
dout(37) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37);
dout(36) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36);
dout(35) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35);
dout(34) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34);
dout(33) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33);
dout(32) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32);
dout(31) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31);
dout(30) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30);
dout(29) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29);
dout(28) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28);
dout(27) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27);
dout(26) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26);
dout(25) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25);
dout(24) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24);
dout(23) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23);
dout(22) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22);
dout(21) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21);
dout(20) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20);
dout(19) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19);
dout(18) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18);
dout(17) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17);
dout(16) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16);
dout(15) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15);
dout(14) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14);
dout(13) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13);
dout(12) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12);
dout(11) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11);
dout(10) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10);
dout(9) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9);
dout(8) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8);
dout(7) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7);
dout(6) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6);
dout(5) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5);
dout(4) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4);
dout(3) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3);
dout(2) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2);
dout(1) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1);
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(63),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(62),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(61),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(60),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(55),
DIA(0) => din(54),
DIB(1) => din(57),
DIB(0) => din(56),
DIC(1) => din(59),
DIC(0) => din(58),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(43),
DIA(0) => din(42),
DIB(1) => din(45),
DIB(0) => din(44),
DIC(1) => din(47),
DIC(0) => din(46),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(37),
DIA(0) => din(36),
DIB(1) => din(39),
DIB(0) => din(38),
DIC(1) => din(41),
DIC(0) => din(40),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(49),
DIA(0) => din(48),
DIB(1) => din(51),
DIB(0) => din(50),
DIC(1) => din(53),
DIC(0) => din(52),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(25),
DIA(0) => din(24),
DIB(1) => din(27),
DIB(0) => din(26),
DIC(1) => din(29),
DIC(0) => din(28),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(19),
DIA(0) => din(18),
DIB(1) => din(21),
DIB(0) => din(20),
DIC(1) => din(23),
DIC(0) => din(22),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(31),
DIA(0) => din(30),
DIB(1) => din(33),
DIB(0) => din(32),
DIC(1) => din(35),
DIC(0) => din(34),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(7),
DIA(0) => din(6),
DIB(1) => din(9),
DIB(0) => din(8),
DIC(1) => din(11),
DIC(0) => din(10),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(1),
DIA(0) => din(0),
DIB(1) => din(3),
DIB(0) => din(2),
DIC(1) => din(5),
DIC(0) => din(4),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(13),
DIA(0) => din(12),
DIB(1) => din(15),
DIB(0) => din(14),
DIC(1) => din(17),
DIC(0) => din(16),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_63 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_62 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_61 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_60 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_59 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_58 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_57 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_56 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_55 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_54 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_53 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_52 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_51 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_50 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_49 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_48 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_47 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_46 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_45 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_44 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_43 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_42 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_41 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_40 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_39 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_38 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_37 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_36 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_35 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_34 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_33 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_32 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_31 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"7FBFDFEFF7FBFDFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"7BDE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"8008200240041001"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"8E8A8A8AAEAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"7FBFDFEFF7FBFDFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EAEAEAC8AAAAAA88"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"F4F4F0F444440044"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 7d8ab9aad3738778c4c900305ce1a039 | 0.663958 | 2.463418 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/midi/midi_pkg.vhd | 1 | 6,601 | -- Package for helping to implement midi synthesis on an FPGA
-- Midi enumerates musical notes. This package contains functions to help
-- implementation of this on an FPGA.
--
-- To generate notes, we will generate sine waves. this will be implemented
-- using lookup tables which store sin(x).
--
-- the following chart shows the format and scaling of what is stored in the
-- LUT.
--
-- SINE LUT LAYOUT
-- 1.0
-- |
-- s | ---
-- i | / \
-- n | / \
-- e | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
--0.0/0.0 x 1.0
--
-- Note that x and y values are both stored in an arbitrary scaling from 0.0 to
-- 1.0
--
--
--
-- ------------------------------------------------------------------------------
-- The most common audio sampling rate is 44.1 kHz. We will thus perform one
-- LUT lookup every 1/44,100 sec. This time is called the 'audio period'
-- Different frequencies are achieved by indexing through this table
-- faster or slower through time.
--
-- Notes that are low frequency will be sampled far apart in the sine wave LUT,
-- as in the following table where samples are indicated by S:
--
-- LOW FREQ NOTE SINE LOOKUP
-- |
-- | ---
-- | / \
-- | / \
-- | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
-- S S S
-- <----->
--
--
-- Notes that are high frequency are sampled close together in the sine wave LUT:
--
-- HIGH FREQ NOTE SINE LOOKUP
-- |
-- | ---
-- | / \
-- | / \
-- | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
-- S S S S S S
-- <-->
--
-- The distance between audio samples (indicated by arrows in the
-- diagrams above) is called the 'stride'
--
--
--
-- ------------------------------------------------------------------------------
-- We need to consider a few implementation details here:
-- * We want to prevent alisaing in the x axis: Because FPGAs have no
-- multiplier, indexing through the LUTs is achieved by successive addition
-- of the stride once per audio period. Thus we should calculate the number
-- of entries in the sine LUT and the size of the counter which indexes into
-- it differently... The counter may need more precision in order to
-- eliminate cumulative error
--
-- I do not know exactly how much error is permissible. There is a wikipedia
-- article on just-noticeable differences (JND) in pitch which states that
-- minimum JND for two different pitches played independently is 0.6%.
-- However the article says that it is easier to tell the difference for
-- chords but it does not give a minimum JND for it. I will thus treat 0.6%
-- as a upper bound for pitch accuracy.
--
--
-- * We want to prevent aliasing in the Y axis. this is a topic that has been
-- well researched. I will implement 16-bit accuracy.
--
-- * Also the number of LUT entries has an effect on aliasing in both the X and
-- Y axis. I have not reasoned about this yet.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.sine_lut_pkg.all;
package midi_pkg is
constant sample_rate : integer := 44_100;
constant sample_period : time := 1 sec / sample_rate;
-- This is the enumeration of midi notes as defined in some midi spec.
subtype midi_note_t is integer range 21 to 108;
-- For each midi note, holds the number of sample periods that exist in one
-- period of that note.
-- e.g for 440hz, there are 1 sec / 440 * 44100 hz = 100.2 sample periods in
-- one period of that note.
type period_arr_t is array (midi_note_t'low to midi_note_t'high) of real;
function calc_midi_note_periods return period_arr_t;
-- This table holds the rates at which the sine LUTs must be indexed through
-- to output sine waves at the correct frequency.
type stride_arr_t is array (midi_note_t'low to midi_note_t'high) of integer;
function calc_midi_note_strides return stride_arr_t;
-- I can't remember how I derived this exact value. See reasoning in the
-- header for an explanation of the concept.
constant midi_counter_width : integer := 17;
-- A type that allows us to use generate statements to build sine generators.
--
-- TODO: this is very implementation specific. Sounds like it should not
-- beling here.
type midi_note_arr_t is array(0 to num_sines - 1) of midi_note_t;
-----------------------------------------------------------------------------
-- Common midi data typres
type errors_t is record
no_mthd : std_logic;
not_format_1 : std_logic;
end record;
type chunk_data_t is record
base_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
length : unsigned(31 downto 0);
end record;
type chunk_data_t_arr is array(integer range 0 to max_num_tracks - 1) of chunk_data_t;
type midi_pulse_arr is array (1 to max_num_tracks - 1) of std_logic;
end;
package body midi_pkg is
constant midi_counter_max : integer := 2 ** midi_counter_width;
-- There is a direct formula to convert midi numbers and frequencies.
-- Sourced from https://newt.phys.unsw.edu.au/jw/notes.html
function calc_freq_from_midi_no(midi_no : in integer) return real is
begin
return
(2 ** (real(midi_no - 69) /
12.0))
* 440.0;
end;
function calc_midi_note_periods return period_arr_t is
variable freq : real;
variable ret : period_arr_t;
begin
for i in midi_note_t'low to midi_note_t'high loop
freq := calc_freq_from_midi_no(i);
-- the ideal calculation is real(1.0 sec / freq / sample_period), but
-- rounding problems.
ret(i) := 1.0 / freq / (1.0 / real(sample_rate));
end loop;
return ret;
end;
function calc_midi_note_strides return stride_arr_t is
variable freq : real;
variable samples_in_current_note : real;
variable ret : stride_arr_t;
begin
for i in midi_note_t'low to midi_note_t'high loop
freq := calc_freq_from_midi_no(i);
-- the ideal calculation is real(1.0 sec / freq / sample_rate), but that
-- has rounding problems
samples_in_current_note := 1.0 / freq / (1.0 / real(sample_rate));
ret(i) := integer(real(midi_counter_max) / samples_in_current_note);
end loop;
return ret;
end;
end;
| bsd-2-clause | 193e17e887dbafafde42322776d47b6e | 0.603242 | 3.573904 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/uart/uart_rx.vhd | 1 | 5,579 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.uart_constants.all;
use virtual_button_lib.utils.all;
entity uart_rx is
port(
ctrl : in ctrl_t;
uart_rx : in std_logic;
new_data : out std_logic;
framing_error : out std_logic;
data : out std_logic_vector(7 downto 0);
run_counter_dbg : out std_logic
);
end entity;
architecture rtl of uart_rx is
type state_t is (waiting, offset_wait, init_next_bit, wait_next_bit, read_current_bit, set_new_data_flag);
signal state : state_t;
-- We subtract 2 to account for time spent in states init_next_Bit and read_current_bit
constant sampling_bits_count : integer := ((1 sec / baud_rate) / clk_period) - 2;
constant offset_wait_count : integer := sampling_bits_count / 2;
signal counter_max : integer range 0 to sampling_bits_count;
signal counter : integer range 0 to sampling_bits_count;
signal bit_counter : integer range 0 to 9;
signal run_counter : std_logic;
signal sample_data : std_logic;
signal check_framing_error : std_logic;
signal increment_bit_counter : std_logic;
signal reset_bit_counter : std_logic;
signal counter_finished : std_logic;
begin
state_nextstate : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
state <= waiting;
else
case state is
when waiting =>
if uart_rx = '0' then
state <= offset_wait;
end if;
when offset_wait =>
if counter_finished = '1' then
state <= init_next_bit;
end if;
when init_next_bit =>
state <= wait_next_bit;
when wait_next_bit =>
if counter_finished = '1' then
state <= read_current_bit;
end if;
when read_current_bit =>
if bit_counter = 9 then
state <= set_new_data_flag;
else
state <= init_next_bit;
end if;
when set_new_data_flag =>
state <= waiting;
when others =>
state <= waiting;
end case;
end if;
end if;
end process;
fsm_outputs : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
sample_data <= '0';
check_framing_error <= '0';
increment_bit_counter <= '0';
reset_bit_counter <= '0';
else
sample_data <= '0';
check_framing_error <= '0';
increment_bit_counter <= '0';
reset_bit_counter <= '0';
case state is
when waiting =>
null;
when offset_wait =>
null;
when init_next_bit =>
increment_bit_counter <= '1';
when wait_next_bit =>
null;
when read_current_bit =>
if bit_counter >= 1 and bit_counter <= 8 then
sample_data <= '1';
end if;
when set_new_data_flag =>
check_framing_error <= '1';
reset_bit_counter <= '1';
when others => null;
end case;
end if;
end if;
end process;
run_counter <= '1' when state = offset_wait or state = wait_next_bit else '0';
counter_max_select : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
counter_max <= 0;
else
if state = offset_wait then
counter_max <= offset_wait_count;
else
counter_max <= sampling_bits_count;
end if;
end if;
end if;
end process;
counting_process : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
counter <= 0;
else
if counter_finished = '1' then
counter <= 0;
elsif run_counter = '1' and counter < counter_max then
counter <= counter + 1;
end if;
end if;
end if;
end process;
counter_finished <= '1' when counter >= counter_max else '0';
bit_counter_ctrl : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
bit_counter <= 0;
else
if reset_bit_counter = '1' then
bit_counter <= 0;
elsif increment_bit_counter = '1' then
bit_counter <= bit_counter + 1;
end if;
end if;
end if;
end process;
read_data : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
data <= (others => '0');
else
if sample_data = '1' then
data(bit_counter - 1) <= uart_rx;
end if;
end if;
end if;
end process;
detect_framing_error_and_set_new_data : process(ctrl.clk)
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
new_data <= '0';
framing_error <= '0';
else
new_data <= '0';
framing_error <= '0';
if check_framing_error = '1' and uart_rx = '1' then
new_Data <= '1';
elsif check_framing_error = '1' and uart_rx = '0' then
framing_error <= '1';
end if;
end if;
end if;
end process;
run_counter_dbg <= run_counter;
end architecture;
| bsd-2-clause | 264fa9b91839a5f2a1cc11ef125d8c8e | 0.525721 | 3.774696 | false | false | false | false |
jaruiz/light8080 | src/vhdl/rtl/mcu/mcu80.vhdl | 1 | 13,093 | --##############################################################################
-- mcu80_mcu : light8080-based Micro Controller Unit
--##############################################################################
-- This MCU is meant as an usage example for the light8080 core. The code shows
-- how to interface the core to internal BRAM and other modules.
-- This module is not meant to be used in real applications though it can be
-- used as the starting point for one.
--
-- Please see the comments below for usage instructions.
-- Please see the LICENSE file in the project root for license matters.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu80_pkg.all;
--##############################################################################
-- Interface pins:
------------------
-- p1_i : Input port P1.
-- p2_o : Output port P2.
-- rxd_i : UART RxD pin.
-- txd_o : UART TxD pin.
-- extint_i : External interrupt inputs, wired straight to the irq controller.
-- EXCEPT for the one used by the UART -- see generic UART_IRQ_LINE.
-- clk : Master clock, rising edge active.
-- reset : Synchronous reset, 1 cycle active to reset all SoC.
--
--------------------------------------------------------------------------------
-- Generics:
------------
-- OBJ_CODE (mandatory, no default value):
-- Table that will be used to initialize internal BRAM, starting at address 0.
--
-- DEFAULT_RAM_SIZE (default = 0):
-- Internal RAM size. If set to zero, the RAM size will be determined from the
-- size of OBJ_CODE as the smallest power of 2 larger than OBJ_CODE'length.
--
-- UART_IRQ_LINE (defaults to 4):
-- Index of the irq controller input the internal UART is wired to, or >3 to
-- leave the UART unconnected to the IRQ controller.
-- The irq controller input used for the uart will be unconnected to the SoC
-- input port.
--
-- UART_HARDWIRED (defaults to true):
-- True when the UART baud rate is hardwired. the baud rate registers will be
--
-- BAUD_RATE (defaults to 19200):
-- UART default baud rate. When th UART is hardwired, the baud rate can't be
-- changed at run time.
-- Note that you have to set generic z. This value is needed to compute the
-- UART baud rate constants.
--
-- SIMULATION (Defaults to False):
-- When True, a number of internal signals are connected to global package
-- signals.
-- This gives the TB access to those signals without using VHDL2008 features
-- (not yet supported in GHDL) or equivalent proprietary schemes.
-- Set it to True in the TB, ignore it otherwise.
--------------------------------------------------------------------------------
-- I/O port map:
----------------
--
-- 080h..083h UART registers.
-- 084h P1 input port (read only, writes are ignored).
-- 086h P2 output port (write only, reads undefined data).
-- 088h IRQ enable register.
--
-- Please see the comments in the source of the relevant modules for a more
-- detailed explanation of their behavior.
--
-- All i/o ports other than the above read as 00h.
--------------------------------------------------------------------------------
-- Notes:
---------
-- -# If you do not set a default memory size, you then have to take care to
-- control the size of the object code table.
-- -# If you do set the default memory size, the code will not warn you if the
-- object code does not fit inside, it will silentl truncate it.
-- -# The internal memory block is mirrored over the entire address map.
-- -# There is no write protection to any address range: you can overwrite the
-- program. If you do that there's no way to recover it but reloading the
-- FPGA, a reset will not do.
--##############################################################################
entity mcu80 is
generic (
OBJ_CODE : obj_code_t; -- RAM initialization constant
DEFAULT_RAM_SIZE: integer := 0; -- RAM size or 0 to stretch
UART_IRQ_LINE : integer := 4; -- [0..3] or >3 for none
UART_HARDWIRED: boolean := true; -- UART baud rate is hardwired
BAUD_RATE : integer := 19200; -- UART (default) baud rate
CLOCK_FREQ : integer := 50E6; -- Clock frequency in Hz
SIMULATION : boolean := False -- True when instantiated in TB
);
port (
p1_i : in std_logic_vector(7 downto 0);
p2_o : out std_logic_vector(7 downto 0);
rxd_i : in std_logic;
txd_o : out std_logic;
extint_i : in std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic
);
end mcu80;
--##############################################################################
--
--##############################################################################
architecture hardwired of mcu80 is
-- Helper functions ------------------------------------------------------------
-- soc_ram_size: compute size of internal RAM
-- If default_size is /= 0, the size is the default. If it is zero, then the
-- size the smallest power of 2 larger than obj_code_size.
function soc_ram_size(default_size, obj_code_size: integer) return integer is
begin
if default_size=0 then
-- Default is zero: use a RAM as big as necessary for the obj code table
-- rounding to the neares power of 2.
return 2**log2(obj_code_size);
else
-- Default is not zero: use the default and do NOT check to see if the
-- object code fits.
return default_size;
end if;
end function soc_ram_size;
-- Custom types ----------------------------------------------------------------
subtype t_byte is std_logic_vector(7 downto 0);
subtype io_addr_t is unsigned(7 downto 0);
-- CPU signals -----------------------------------------------------------------
signal cpu_vma : std_logic;
signal cpu_rd : std_logic;
signal cpu_wr : std_logic;
signal cpu_io : std_logic;
signal cpu_fetch : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_i : std_logic_vector(7 downto 0);
signal cpu_data_o : std_logic_vector(7 downto 0);
signal cpu_intr : std_logic;
signal cpu_inte : std_logic;
signal cpu_inta : std_logic;
signal cpu_halt : std_logic;
-- Aux CPU signals -------------------------------------------------------------
-- io_wr: asserted in IO write cycles
signal io_wr : std_logic;
-- io_rd: asserted in IO read cycles
signal io_rd : std_logic;
-- io_addr: IO port address, lowest 8 bits of address bus
signal io_addr : unsigned(7 downto 0);
-- io_rd_data: data coming from IO ports (io input mux)
signal io_rd_data : std_logic_vector(7 downto 0);
-- cpu_io_reg: registered cpu_io, used to control mux after cpu_io deasserts
signal cpu_io_reg : std_logic;
-- UART ------------------------------------------------------------------------
signal uart_ce : std_logic;
signal uart_data_rd : std_logic_vector(7 downto 0);
signal uart_irq : std_logic;
-- RAM -------------------------------------------------------------------------
constant RAM_SIZE : integer := soc_ram_size(DEFAULT_RAM_SIZE,OBJ_CODE'length);
constant RAM_ADDR_SIZE : integer := log2(RAM_SIZE);
signal ram_rd_data : std_logic_vector(7 downto 0);
signal ram_we : std_logic;
signal ram : ram_t(0 to RAM_SIZE-1) := objcode_to_bram(OBJ_CODE, RAM_SIZE);
signal ram_addr : unsigned(RAM_ADDR_SIZE-1 downto 0);
-- IRQ controller interface ----------------------------------------------------
signal irqcon_we : std_logic;
signal irqcon_data_rd: std_logic_vector(7 downto 0);
signal irq : std_logic_vector(3 downto 0);
-- IO ports addresses ----------------------------------------------------------
constant ADDR_UART_0 : io_addr_t := X"80"; -- UART registers (80h..83h)
constant ADDR_UART_1 : io_addr_t := X"81"; -- UART registers (80h..83h)
constant ADDR_UART_2 : io_addr_t := X"82"; -- UART registers (80h..83h)
constant ADDR_UART_3 : io_addr_t := X"83"; -- UART registers (80h..83h)
constant P1_DATA_REG : io_addr_t := X"84"; -- port 1 data register
constant P2_DATA_REG : io_addr_t := X"86"; -- port 2 data register
constant INTR_EN_REG : io_addr_t := X"88"; -- interrupts enable register
begin
cpu: entity work.light8080
port map (
clk => clk,
reset => reset,
vma => cpu_vma,
rd => cpu_rd,
wr => cpu_wr,
io => cpu_io,
fetch => cpu_fetch,
addr_out => cpu_addr,
data_in => cpu_data_i,
data_out => cpu_data_o,
intr => cpu_intr,
inte => cpu_inte,
inta => cpu_inta,
halt => cpu_halt
);
io_rd <= cpu_io and cpu_rd;
io_wr <= '1' when cpu_io='1' and cpu_wr='1' else '0';
io_addr <= unsigned(cpu_addr(7 downto 0));
-- Register some control signals that are needed to control multiplexors the
-- cycle after the control signal asserts -- e.g. cpu_io.
control_signal_registers:
process(clk)
begin
if clk'event and clk='1' then
cpu_io_reg <= cpu_io;
end if;
end process control_signal_registers;
-- Input data mux -- remember, no 3-state buses within the FPGA --------------
cpu_data_i <=
irqcon_data_rd when cpu_inta = '1' else
io_rd_data when cpu_io_reg = '1' else
ram_rd_data;
-- BRAM ----------------------------------------------------------------------
ram_we <= '1' when cpu_io='0' and cpu_wr='1' else '0';
ram_addr <= unsigned(cpu_addr(RAM_ADDR_SIZE-1 downto 0));
memory:
process(clk)
begin
if clk'event and clk='1' then
if ram_we = '1' then
ram(to_integer(ram_addr)) <= cpu_data_o;
end if;
ram_rd_data <= ram(to_integer(ram_addr));
end if;
end process memory;
-- Interrupt controller ------------------------------------------------------
-- FIXME interrupts unused in this version
irq_control: entity work.mcu80_irq
port map (
clk => clk,
reset => reset,
irq_i => irq,
data_i => cpu_data_o,
data_o => irqcon_data_rd,
addr_i => cpu_addr(0),
data_we_i => irqcon_we,
cpu_inta_i => cpu_inta,
cpu_intr_o => cpu_intr,
cpu_fetch_i => cpu_fetch
);
irq_line_connections:
for i in 0 to 3 generate
begin
uart_irq_connection:
if i = UART_IRQ_LINE generate
begin
irq(i) <= uart_irq or extint_i(i);
end generate;
other_irq_connections:
if i /= UART_IRQ_LINE generate
irq(i) <= extint_i(i);
end generate;
end generate irq_line_connections;
irqcon_we <= '1' when io_addr=INTR_EN_REG and io_wr='1' else '0';
-- UART -- simple UART with hardwired baud rate ------------------------------
-- NOTE: the serial port does NOT have interrupt capability (yet)
uart : entity work.mcu80_uart
generic map (
BAUD_RATE => BAUD_RATE,
CLOCK_FREQ => CLOCK_FREQ
)
port map (
clk_i => clk,
reset_i => reset,
irq_o => uart_irq,
data_i => cpu_data_o,
data_o => uart_data_rd,
addr_i => cpu_addr(1 downto 0),
ce_i => uart_ce,
wr_i => io_wr,
rd_i => io_rd,
rxd_i => rxd_i,
txd_o => txd_o
);
-- UART write enable
uart_ce <= '1' when
io_addr(7 downto 2) = ADDR_UART_0(7 downto 2)
else '0';
-- IO ports -- Simple IO ports with hardcoded direction ----------------------
-- These are meant as an usage example mostly
output_ports:
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- Reset values for all io ports
p2_o <= (others => '0');
else
if io_wr = '1' then
if to_integer(io_addr) = P2_DATA_REG then
p2_o <= cpu_data_o;
end if;
end if;
end if;
end if;
end process output_ports;
-- Input IO data multiplexor
with io_addr select io_rd_data <=
p1_i when P1_DATA_REG,
uart_data_rd when ADDR_UART_0,
uart_data_rd when ADDR_UART_1,
uart_data_rd when ADDR_UART_2,
uart_data_rd when ADDR_UART_3,
irqcon_data_rd when INTR_EN_REG,
X"00" when others;
-- Simulation support ------------------------------------------------------
Internal_signal_extraction:
if SIMULATION generate
-- 'Connect' all the internal signals we want to watch to members of
-- the info record.
-- This does not require VHDL 2008 support or proprietary tricks.
mon_addr <= cpu_addr;
mon_fetch <= cpu_fetch;
mon_wdata <= cpu_data_o;
mon_we <= cpu_wr;
mon_uart_ce <= uart_ce;
end generate Internal_signal_extraction;
end hardwired;
| lgpl-2.1 | eef1358c25b13a712c5267c07c62839e | 0.535782 | 3.853149 | false | false | false | false |
willtmwu/vhdlExamples | Project/project_nrf_subprog.vhd | 1 | 7,315 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package project_nrf_subprog is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Char HEX constants, must be 0-9 and/or lower case a-f. For internal subprog use for now
constant CHAR_0_i : STD_LOGIC_VECTOR(7 downto 0) := x"30";
constant CHAR_9_i : STD_LOGIC_VECTOR(7 downto 0) := x"39";
constant CHAR_A_i : STD_LOGIC_VECTOR(7 downto 0) := x"61";
constant CHAR_F_i : STD_LOGIC_VECTOR(7 downto 0) := x"66";
subtype nib is std_logic_vector(3 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype half_w is std_logic_vector(15 downto 0);
function Hamming_hByte_encoder ( X : nib ) return byte;
function Hamming_Byte_encoder ( X : byte ) return half_w;
function Hamming_hByte_decoder ( X : byte ) return nib;
function Hamming_Byte_decoder ( X : half_w ) return byte;
function CHAR_TO_HEX ( X : byte ) return nib;
function HEX_TO_CHAR ( X : nib ) return byte;
-- std_logic_vector(4 downto 0) to bcd std_logic_vector(7 downto 0);
subtype input_num is std_logic_vector(4 downto 0); -- 5 bit
subtype BCD_HEX is std_logic_vector(7 downto 0); -- hex
function to_BCD (X: input_num) return BCD_HEX;
end project_nrf_subprog;
package body project_nrf_subprog is
-- Lower (a -> f) and 0->9 ASCII char translated to hex. 0xf on err
function CHAR_TO_HEX (X:byte) return nib is
variable tmpByte : byte := (others => '0');
variable retNib : nib := (others => '0');
begin
if (X>=CHAR_A_i and X<=CHAR_F_i) then
tmpByte := X-CHAR_A_i;
elsif (X>=CHAR_0_i and X<=CHAR_F_i) then
tmpByte := X-CHAR_0_i;
else
tmpByte := (others => '0');
end if;
retNib := tmpByte(3 downto 0);
return retNib;
end CHAR_TO_HEX;
-- Hex 0-F translated to ASCII char. 0x00 on err
function HEX_TO_CHAR (X:nib) return byte is
variable tmpByte : byte := (others => '0');
variable tmpOffset: byte := (others => '0');
begin
tmpOffset(3 downto 0) := X;
if (X>="0000" and X<="1001") then
tmpByte := CHAR_0_i+tmpOffset;
elsif (X>="1010" and X<="1111") then
tmpByte := CHAR_A_i+tmpOffset-"00001010";
else
tmpByte := (others => '0');
end if;
return tmpByte;
end HEX_TO_CHAR;
-- Byte in, 16-bit out
function Hamming_Byte_encoder (X : byte ) return half_w is
variable lowerByte : byte := (others => '0');
variable upperByte : byte := (others => '0');
variable ret_half_w: half_w := (others => '0');
begin
lowerByte := Hamming_hByte_encoder( X(3 downto 0) );
upperByte := Hamming_hByte_encoder( X(7 downto 4) );
ret_half_w(7 downto 0) := lowerByte;
ret_half_w(15 downto 8) := upperByte;
return ret_half_w;
end Hamming_Byte_encoder;
-- 4 bit in, 8 encoded out
function Hamming_hByte_encoder (X : nib) return byte is
variable H0 : std_logic := '0';
variable H1 : std_logic := '0';
variable H2 : std_logic := '0';
variable P : std_logic := '0';
variable encoded : std_logic_vector(7 downto 0) := (others => '0');
begin
H0 := X(1) XOR X(2) XOR X(3);
H1 := X(0) XOR X(2) XOR X(3);
H2 := X(0) XOR X(1) XOR X(3);
P := X(0) XOR X(1) XOR X(2); -- CHECK LOGIC
encoded := X & H2 & H1 & H0 & P;
return encoded;
end Hamming_hByte_encoder;
-- 16 bits in, byte out
function Hamming_Byte_decoder (X : half_w ) return byte is
variable lowerNib : nib := (others => '0');
variable upperNib : nib := (others => '0');
variable retByte : byte := (others => '0');
begin
lowerNib := Hamming_hByte_decoder( X(7 downto 0) );
upperNib := Hamming_hByte_decoder( X(15 downto 8) );
retByte(3 downto 0) := lowerNib;
retByte(7 downto 4) := upperNib;
return retByte;
end Hamming_Byte_decoder;
-- 8 Bits in, 4 bits decoded out
function Hamming_hByte_decoder(X : byte) return nib is
variable S0 : std_logic := '0';
variable S1 : std_logic := '0';
variable S2 : std_logic := '0';
variable P : std_logic := '0';
variable D : std_logic_vector(7 downto 0) := (others => '0');
variable R : std_logic_vector(3 downto 0) := (others => '0');
begin
D := X;
S0 := D(1) XOR D(5) XOR D(6) XOR D(7);
S1 := D(2) XOR D(4) XOR D(6) XOR D(7);
S2 := D(3) XOR D(4) XOR D(5) XOR D(7);
-- Method 1
-- if ( (S0 = '1') and (S1 = '1') and (S2 = '1') ) then
-- D(7) := D(7) XOR '1'; -- Rel D3
-- elsif ( (S0 XOR S1 XOR S2) = '1' ) then
-- D(1) := D(1) XOR S0; -- H0
-- D(2) := D(2) XOR S1; -- H1
-- D(3) := D(3) XOR S2; -- H2
-- else
-- D(4) := D(4) XOR NOT(S0); -- Rel D0
-- D(5) := D(5) XOR NOT(S1); -- Rel D1
-- D(6) := D(6) XOR NOT(S2); -- Rel D2
-- end if;
-- Method 2
D(1) := D(1) XOR (S0 AND NOT(S1) AND NOT(S2));
D(2) := D(2) XOR (NOT(S0) AND S1 AND NOT(S2));
D(3) := D(3) XOR (NOT(S0) AND NOT(S1) AND S2);
D(4) := D(4) XOR (NOT(S0) AND S1 AND S2);
D(5) := D(5) XOR (S0 AND NOT(S1) AND S2);
D(6) := D(6) XOR (S0 AND S1 AND NOT(S2));
D(7) := D(7) XOR (S0 AND S1 AND S2);
R := D(7 downto 4);
return R;
end Hamming_hByte_decoder;
function to_BCD (X: input_num) return BCD_HEX is
variable retHEX : BCD_HEX := (others => '0');
begin
if ( X = "00000") then
retHex := x"00";
elsif (X = "00001") then
retHex := x"01";
elsif (X = "00010") then
retHex := x"02";
elsif (X = "00011") then
retHex := x"03";
elsif (X = "00100") then
retHex := x"04";
elsif (X = "00101") then
retHex := x"05";
elsif (X = "00110") then
retHex := x"06";
elsif (X = "00111") then
retHex := x"07";
elsif (X = "01000") then
retHex := x"08";
elsif (X = "01001") then
retHex := x"09";
elsif (X = "01010") then
retHex := x"10";
elsif (X = "01011") then
retHex := x"11";
elsif (X = "01100") then
retHex := x"12";
elsif (X = "01101") then
retHex := x"13";
elsif (X = "01110") then
retHex := x"14";
elsif (X = "01111") then
retHex := x"15";
elsif (X = "10000") then
retHex := x"16";
elsif (X = "10001") then
retHex := x"17";
elsif (X = "10010") then
retHex := x"18";
elsif (X = "10011") then
retHex := x"19";
elsif (X = "10100") then
retHex := x"20";
elsif (X = "10101") then
retHex := x"21";
elsif (X = "10110") then
retHex := x"22";
elsif (X = "10111") then
retHex := x"23";
elsif (X = "11000") then
retHex := x"24";
elsif (X = "11001") then
retHex := x"25";
elsif (X = "11010") then
retHex := x"26";
elsif (X = "11011") then
retHex := x"27";
elsif (X = "11100") then
retHex := x"28";
elsif (X = "11101") then
retHex := x"29";
elsif (X = "11110") then
retHex := x"30";
elsif (X = "11111") then
retHex := x"31";
end if;
return retHex;
end to_BCD;
end project_nrf_subprog;
| apache-2.0 | e047eb074a302a959bf5272b5f392139 | 0.549692 | 2.635086 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/cygraph_process1.vhd | 2 | 2,767 | -- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 1 of the kernel
-- Request contents of current queue at address (cq_address + kernel_id + offset)
-- NOTE: we can get rid of this process
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process1 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0);
kernels_count : in unsigned(7 downto 0);
cq_count : in unsigned(31 downto 0); -- Number of nodes to visit in the current level
-- Queue pointers
cq_address : in std_logic_vector(63 downto 0);
-- Process 1 signals
p1_done : out std_logic;
p1_count : out unsigned(31 downto 0);
-- Process 1 req queue signals
p1_req_q_almost_full : in std_logic;
p1_req_q_wr_en : out std_logic;
p1_req_q_din : out std_logic_vector(63 downto 0);
p1_req_q_full : in std_logic
);
end entity; -- end of process 1 entity declarion
architecture arch of process1 is
signal p1_offset : unsigned(31 downto 0);
signal count : unsigned(31 downto 0);
begin
p1_count <= count;
p1 : process(clk, rst)
begin
if rising_edge(clk) then
if (rst = '1') then
p1_done <= '0';
count <= (others => '0');
p1_offset <= (others => '0');
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
else
if (started = '0') then
p1_done <= '0';
count <= (others => '0');
p1_offset <= (others => '0');
-- set the p1 request queue signals to default
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
elsif (started = '1') then
if (p1_offset + kernel_id + unsigned(ae_id & "0000") < cq_count and p1_req_q_almost_full = '0') then
-- request current_queue[cq_address + p1_offset + kernel_id]
p1_req_q_wr_en <= '1';
p1_req_q_din <= std_logic_vector(resize(unsigned(cq_address) + 8 * (unsigned(ae_id & "0000") + unsigned(kernel_id) + unsigned(p1_offset)), 64));
-- Increment nodes count and read offset
count <= count + 1;
p1_offset <= p1_offset + kernels_count;
elsif (p1_offset + kernel_id + unsigned(ae_id & "0000") >= cq_count) then
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
p1_done <= '1';
else
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
end if;
else
p1_req_q_wr_en <= '0';
p1_req_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 1
end architecture; -- arch
| apache-2.0 | 289274e1ba695651a93b5d61550ef205 | 0.592338 | 2.630228 | false | false | false | false |
willtmwu/vhdlExamples | Moving Averager/harware_interface.vhd | 1 | 4,727 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0);
JC : out STD_LOGIC_VECTOR (7 downto 0);
JD : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component datapath_averager Port (
mem_addr : in STD_LOGIC_VECTOR(5 downto 0);
window_val : in STD_LOGIC_VECTOR(1 downto 0);
overflow : out STD_LOGIC;
clk : in STD_LOGIC;
masterReset : in STD_LOGIC;
input_val : out STD_LOGIC_VECTOR(7 downto 0);
average_val : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath_controller Port (
window_ctrl : in STD_LOGIC_VECTOR(1 downto 0);
masterReset : in STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR(5 downto 0);
window_val : OUT std_logic_vector(1 downto 0);
overflow : IN std_logic;
clk : in STD_LOGIC
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
--Clock scaled signals
signal clk2Hz : std_logic;
--Bridging Signals
signal window_ctrl : STD_LOGIC_VECTOR(1 downto 0):="01";
signal mem_addr : STD_LOGIC_VECTOR(5 downto 0):=(others => '0');
signal window_val : std_logic_vector(1 downto 0) :=(others => '0');
signal overflow : std_logic := '0';
signal input_val : std_logic_vector (7 downto 0) := (others => '0');
signal average_val : std_logic_vector (7 downto 0) := (others => '0');
begin
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
m1 : datapath_controller port map (window_ctrl, masterReset, mem_addr, window_val, overflow, clk2Hz);
m2 : datapath_averager port map (mem_addr, window_val, overflow, clk2Hz, masterReset, input_val, average_val);
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
clk2Hz <= clockScalers(19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
--Window Ctrl and Debugging
window_ctrl(0) <= slideSwitches(14) when (buttonDown'event and buttonDown = '1') else '0';
window_ctrl(1) <= slideSwitches(15) when (buttonDown'event and buttonDown = '1') else '1';
--window_ctrl <= "01";
--logic_analyzer(6 downto 0) <= average_val (6 downto 0);
--logic_analyzer(7) <= clk2hz;
displayLower(7 downto 0) <= average_val;
displayLower(15 downto 8) <= input_val;
displayUpper(5 downto 0) <= mem_addr;
displayUpper(15 downto 14) <= window_val;
JC <= input_val;
JD <= average_val;
end Behavioral; | apache-2.0 | 14326fc6cd5201719cc340031686c974 | 0.640999 | 3.113966 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/HA/HA_tb.vhd | 1 | 1,654 | library ieee;
use ieee.std_logic_1164.all;
entity HA_tb is
end HA_tb;
architecture tb of HA_tb is
component HA is
port( A, B : in std_logic;
Sout, Cout : out std_logic);
end component;
signal A, B, Sout, Cout: std_logic;
begin
mapping: HA port map(A, B, Sout, Cout);
process
variable errCnt : integer := 0;
begin
--TEST 1
A <= '0';
B <= '1';
wait for 10 ns;
--assert(sum = '1') report "sum error 1" severity error;
--assert(Cout = '0') report "Cout error 1" severity error;
--if(sum /= '1' or Cout /= '0') then
--errCnt := errCnt + 1;
--end if;
--TEST 2
A <= '1';
B <= '1';
wait for 10 ns;
--assert(sum = '0') report "sum error 2" severity error;
--assert(Cout = '1') report "Cout error 2" severity error;
--if(sum /= '0' or Cout /= '1') then
--errCnt := errCnt + 1;
--end if;
--TEST 3
A <= '1';
B <= '0';
wait for 10 ns;
--assert(sum = '1') report "sum error 3" severity error;
--assert(Cout = '0') report "Cout error 3" severity error;
--if(sum /= '1' or Cout /= '0') then
--errCnt := errCnt + 1;
--end if;
---- SUMMARY ----
--if(errCnt = 0) then
--assert false report "Success!" severity note;
--else
--assert false report "Faillure!" severity note;
--end if;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of HA_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END | mit | a801316ff4d5ede799be68b085e0b7f8 | 0.47763 | 3.556989 | false | false | false | false |
SDRG-UCT/RHINO_CALF | ethernet-io/UDP_1GbE.vhd | 1 | 36,040 | ----------------------------------------------------------------------
-- Title : 1 Gbe UDP network implementation with
-- open-cores tri-mac-core on RHINO
----------------------------------------------------------------------
-- Project : RHINO SDR Processing Blocks
----------------------------------------------------------------------
--
-- Author : Lekhobola Tsoeunyane
-- Company : University Of Cape Town
-- Email : [email protected]
----------------------------------------------------------------------
-- Features
-- 1) Marvell 88E1111S initialization
-- 2) UDP packet transmission and reception
-- 2) Adopting the tri-mac-core to work on RHINO board.
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Description:
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2013 Steffen Mauch ----
---- steffen.mauch (at) gmail.com ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity UDP_1GbE is
generic(
UDP_TX_DATA_BYTE_LENGTH : natural := 1;
UDP_RX_DATA_BYTE_LENGTH : natural:= 1
);
port(
-- user logic interface
own_ip_addr : in std_logic_vector (31 downto 0);
own_mac_addr : in std_logic_vector (47 downto 0);
dst_ip_addr : in std_logic_vector (31 downto 0);
dst_mac_addr : out std_logic_vector(47 downto 0);
udp_src_port : in std_logic_vector (15 downto 0);
udp_dst_port : in std_logic_vector (15 downto 0);
udp_tx_pkt_data : in std_logic_vector (8 * UDP_TX_DATA_BYTE_LENGTH - 1 downto 0);
udp_tx_pkt_vld : in std_logic;
udp_tx_rdy : out std_logic;
udp_rx_pkt_data : out std_logic_vector(8 * UDP_RX_DATA_BYTE_LENGTH - 1 downto 0);
udp_rx_pkt_req : in std_logic;
udp_rx_rdy : out std_logic;
mac_init_done : out std_logic;
-- MAC interface
GIGE_COL : in std_logic;
GIGE_CRS : in std_logic;
GIGE_MDC : out std_logic;
GIGE_MDIO : inout std_logic;
GIGE_TX_CLK : in std_logic;
GIGE_nRESET : out std_logic;
GIGE_RXD : in std_logic_vector( 7 downto 0 );
GIGE_RX_CLK : in std_logic;
GIGE_RX_DV : in std_logic;
GIGE_RX_ER : in std_logic;
GIGE_TXD : out std_logic_vector( 7 downto 0 );
GIGE_GTX_CLK : out std_logic;
GIGE_TX_EN : out std_logic;
GIGE_TX_ER : out std_logic;
-- system control
clk_125mhz : in std_logic;
clk_100mhz : in std_logic;
sys_rst_i : in std_logic;
sysclk_locked : in std_logic
);
end UDP_1GbE;
architecture arc of UDP_1GbE is
component MAC_top
port(
--//system signals
Reset : in std_logic;
Clk_125M : in std_logic;
Clk_user : in std_logic;
Clk_reg : in std_logic;
Speed : out std_logic_vector( 2 downto 0);
--//user interface
Rx_mac_ra : out std_logic;
Rx_mac_rd : in std_logic;
Rx_mac_data : out std_logic_vector( 31 downto 0 );
Rx_mac_BE : out std_logic_vector( 1 downto 0 );
Rx_mac_pa : out std_logic;
Rx_mac_sop : out std_logic;
Rx_mac_eop : out std_logic;
--//user interface
Tx_mac_wa : out std_logic;
Tx_mac_wr : in std_logic;
Tx_mac_data : in std_logic_vector( 31 downto 0 );
Tx_mac_BE : in std_logic_vector( 1 downto 0 );--//big endian
Tx_mac_sop : in std_logic;
Tx_mac_eop : in std_logic;
--//pkg_lgth fifo
Pkg_lgth_fifo_rd : in std_logic;
Pkg_lgth_fifo_ra : out std_logic;
Pkg_lgth_fifo_data : out std_logic_vector( 15 downto 0 );
--//Phy interface
--//Phy interface
Gtx_clk : out std_logic;--//used only in GMII mode
Rx_clk : in std_logic;
Tx_clk : in std_logic; --//used only in MII mode
Tx_er : out std_logic;
Tx_en : out std_logic;
Txd : out std_logic_vector( 7 downto 0 );
Rx_er : in std_logic;
Rx_dv : in std_logic;
Rxd : in std_logic_vector( 7 downto 0 );
Crs : in std_logic;
Col : in std_logic;
--//host interface
CSB : in std_logic;
WRB : in std_logic;
CD_in : in std_logic_vector( 15 downto 0 );
CD_out : out std_logic_vector( 15 downto 0 );
CA : in std_logic_vector( 7 downto 0 );
-- mdx
Mdo : out std_logic; --// MII Management Data Output
MdoEn : out std_logic; --// MII Management Data Output Enable
Mdi : in std_logic;
Mdc : out std_logic; --// MII Management Data Clock
-- MII to CPU
Divider : in std_logic_vector(7 downto 0);
CtrlData : in std_logic_vector(15 downto 0);
Rgad : in std_logic_vector(4 downto 0);
Fiad : in std_logic_vector(4 downto 0);
NoPre : in std_logic;
WCtrlData : in std_logic;
RStat : in std_logic;
ScanStat : in std_logic;
Busy : out std_logic;
LinkFail : out std_logic;
Nvalid : out std_logic;
Prsd : out std_logic_vector(15 downto 0);
WCtrlDataStart : out std_logic;
RStatStart : out std_logic;
UpdateMIIRX_DATAReg : out std_logic
);
end component;
component calc_ipv4_checksum
port (
clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (159 downto 0);
ready : out STD_LOGIC;
checksum : out STD_LOGIC_VECTOR (15 downto 0);
reset : in STD_LOGIC);
end component;
---------------------------------------------------------------------------
-- DUBUGGING SECTION
---------------------------------------------------------------------------
component icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
component ila0
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component ila1
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
component vio
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL1 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal CONTROL2 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal ila_data0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal ila_data1 : STD_LOGIC_VECTOR(127 DOWNTO 0);
signal trig0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal trig1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vio_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
---------------------------------------------------------------------------
-- END OF DUBUGGING SECTION
---------------------------------------------------------------------------
attribute S: string;
attribute keep : string;
signal c3_rst0 : std_logic;
signal c3_sys_clk_ibufg : std_logic;
--signal clk_125mhz : std_logic;
--signal clk_100mhz : std_logic;
--signal clk_25mhz : std_logic;
--signal clk_6_25mhz : std_logic;
--signal clk_3_125mhz : std_logic;
signal reset : std_logic;
signal Rx_mac_ra : std_logic;
attribute S of Rx_mac_ra : signal is "TRUE";
signal Rx_mac_rd : std_logic;
attribute S of Rx_mac_rd : signal is "TRUE";
signal Rx_mac_data: std_logic_vector( 31 downto 0 );
attribute S of Rx_mac_data : signal is "TRUE";
signal Rx_mac_BE : std_logic_vector( 1 downto 0 );
attribute S of Rx_mac_BE : signal is "TRUE";
signal Rx_mac_pa : std_logic;
attribute S of Rx_mac_pa : signal is "TRUE";
signal Rx_mac_sop : std_logic;
attribute S of Rx_mac_sop : signal is "TRUE";
signal Rx_mac_eop : std_logic;
attribute S of Rx_mac_eop : signal is "TRUE";
--//user interface
signal Tx_mac_wa : std_logic;
attribute S of Tx_mac_wa : signal is "TRUE";
signal Tx_mac_wr : std_logic;
attribute S of Tx_mac_wr : signal is "TRUE";
signal Tx_mac_data: std_logic_vector( 31 downto 0 );
attribute S of Tx_mac_data : signal is "TRUE";
signal Tx_mac_BE : std_logic_vector( 1 downto 0 );--//big endian
attribute S of Tx_mac_BE : signal is "TRUE";
signal Tx_mac_sop : std_logic;
attribute S of Tx_mac_sop : signal is "TRUE";
signal Tx_mac_eop : std_logic;
attribute S of Tx_mac_eop : signal is "TRUE";
--//pkg_lgth fifo
signal Pkg_lgth_fifo_rd : std_logic;
signal Pkg_lgth_fifo_ra : std_logic;
signal Pkg_lgth_fifo_data : std_logic_vector( 15 downto 0 );
signal CSB : std_logic;
signal WRB : std_logic;
signal CD_in : std_logic_vector( 15 downto 0 );
signal CD_out : std_logic_vector( 15 downto 0 );
signal CA : std_logic_vector( 7 downto 0 );
--//mdx
signal Mdo : std_logic; --// MII Management Data Output
signal MdoEn : std_logic; --// MII Management Data Output Enable
signal Mdi : std_logic;
signal ethernet_speed : std_logic_vector( 2 downto 0);
attribute S of ethernet_speed : signal is "TRUE";
signal GIGE_GTX_CLK_buf : std_logic;
type state_type_ethernet is (arp,arp_wait,idle,wait_state,wait_state1,send_udp,wait_state2); --type of state machine.
signal state_ethernet : state_type_ethernet; --current and next state declaration.
--- transmisssion constants
constant pkt_data_length : integer := 8 * UDP_TX_DATA_BYTE_LENGTH;
constant pkt_byte_mod : integer := (UDP_TX_DATA_BYTE_LENGTH - 2) mod 4;
constant pkt_data_mod : integer := (pkt_data_length - 16) mod 32;
constant pkt_data_word_length : integer := (pkt_data_length - 16) / 32;
constant length_ethernet_frame : integer := integer(ceil(real((UDP_TX_DATA_BYTE_LENGTH) / 4))) + 11;---12;
constant length_ethernet_arp_frame : integer := 11;
constant length_ethernet_arp_request_frame : integer := 11;
-- receiving constants
constant rcv_pkt_data_length : integer := 8 * UDP_RX_DATA_BYTE_LENGTH;
constant rcv_pkt_byte_mod : integer := (UDP_RX_DATA_BYTE_LENGTH - 2) mod 4;
constant rcv_pkt_data_mod : integer := (rcv_pkt_data_length - 16) mod 32;
constant rcv_pkt_data_word_length : integer := (rcv_pkt_data_length - 16) / 32;
constant rcv_length_ethernet_frame : integer := integer(ceil(real((UDP_RX_DATA_BYTE_LENGTH) / 4)));
signal udp_rx_pkt_data_tmp : std_logic_vector(rcv_pkt_data_length - 1 downto 0) := (others => '0');
attribute S of udp_rx_pkt_data_tmp : signal is "TRUE";
type array_network is array (0 to length_ethernet_frame-1) of std_logic_vector(31 downto 0);
type array_network_arp is array (0 to length_ethernet_arp_frame-1) of std_logic_vector(31 downto 0);
type array_network_arp_request is array (0 to length_ethernet_arp_request_frame-1) of std_logic_vector(31 downto 0);
signal eth_array : array_network;
signal arp_array : array_network_arp;
signal arp_request_array : array_network_arp_request;
signal counter_ethernet : integer range 0 to length_ethernet_frame-1;
signal Rx_clk : std_logic;
attribute S of Rx_clk : signal is "TRUE";
signal Tx_clk : std_logic;
attribute S of Tx_clk : signal is "TRUE";
signal Tx_er : std_logic;
attribute S of Tx_er : signal is "TRUE";
signal Tx_en : std_logic;
attribute S of Tx_en : signal is "TRUE";
signal Txd : std_logic_vector( 7 downto 0 );
attribute S of Txd : signal is "TRUE";
signal Rx_er : std_logic;
attribute S of Rx_er : signal is "TRUE";
signal Rx_dv : std_logic;
attribute S of Rx_dv : signal is "TRUE";
signal Rxd : std_logic_vector( 7 downto 0 );
attribute S of Rxd : signal is "TRUE";
signal MDC_sig : std_logic;
signal calc_checksum : std_logic_vector( 15 downto 0);
attribute S of calc_checksum : signal is "TRUE";
signal LED_sig : std_logic;
attribute S of LED_sig : signal is "TRUE";
signal counter_ethernet_delay : integer := 0;
signal counter_ethernet_rec : integer range 0 to 15;
signal packet_valid : std_logic;
attribute S of packet_valid : signal is "TRUE";
signal LED_data : std_logic_vector( 7 downto 0);
attribute S of LED_data : signal is "TRUE";
signal Rx_mac_rd_sig : std_logic;
signal arp_valid_response : std_logic;
signal arp_valid_response_recieved : std_logic;
signal arp_valid : std_logic;
attribute S of arp_valid : signal is "TRUE";
signal arp_mac : std_logic_vector(47 downto 0);
attribute S of arp_mac : signal is "TRUE";
signal arp_ip : std_logic_vector(31 downto 0);
attribute S of arp_ip : signal is "TRUE";
signal arp_send : std_logic;
attribute S of arp_send : signal is "TRUE";
signal arp_clear : std_logic;
attribute S of arp_clear : signal is "TRUE";
-- signal for destination MAC address
signal dst_mac_addr_r : std_logic_vector( 47 downto 0 );
signal gmii_phy_rst_n : std_logic;
-- PHY management
signal config_state : integer range 0 to 31 := 0;
signal config_checked : std_logic := '0';
signal config_delay_count : integer range 0 to 250000000;
signal phy_reg_addr : std_logic_vector(4 downto 0) := (others => '0');
signal Divider : std_logic_vector(7 downto 0) := x"1A";
signal CtrlData : std_logic_vector(15 downto 0);
signal Rgad : std_logic_vector(4 downto 0);
signal Fiad : std_logic_vector(4 downto 0) := "00001";
signal NoPre : std_logic;
signal WCtrlData : std_logic;
signal RStat : std_logic;
signal ScanStat : std_logic;
signal Busy : std_logic;
signal LinkFail : std_logic;
signal Nvalid : std_logic;
signal Prsd : std_logic_vector(15 downto 0);
signal WCtrlDataStart : std_logic;
signal RStatStart : std_logic;
signal UpdateMIIRX_DATAReg : std_logic;
-- Udp transmission
signal udp_counter : integer := 0;
signal udp_rec : std_logic := '0';
signal counter_rx : integer := 0;
signal packet_vld : std_logic := '0';
signal mac_init_ok : std_logic := '0';
-- Debug signals
signal tx_state : std_logic_vector(2 downto 0) := "000";
signal rx_state : std_logic_vector(2 downto 0) := "000";
signal toggle : std_logic := '0'; -- 50 mhz user clock
signal toggle1 : std_logic := '0'; -- 125 mhz
signal toggle2 : std_logic := '0'; -- 125 mhz
begin
reset <= not sysclk_locked;
udp_tx_rdy <= '1' when (Tx_mac_wa = '1' and state_ethernet = wait_state2) else
'0';
dst_mac_addr <= dst_mac_addr_r;
mac_init_done <= mac_init_ok;
-- settings for ethernet MAC
Ethernet_MAC_top : MAC_top
port map(
--//system signals
Reset => reset,
Clk_125M => clk_125mhz,
Clk_user => clk_100mhz,--!!!!!!!!!!!
Clk_reg => clk_100mhz,--!!!!!!!!!!!
-- speed settings after opencore tri-mode (PDF)!
-- b100 : 1000Mbit
-- b010 : 100Mbit
-- b001 : 10Mbit
Speed => ethernet_speed,
--//user interface
Rx_mac_ra => Rx_mac_ra,
Rx_mac_rd => Rx_mac_rd,
Rx_mac_data => Rx_mac_data,
Rx_mac_BE => Rx_mac_BE,
Rx_mac_pa => Rx_mac_pa,
Rx_mac_sop => Rx_mac_sop,
Rx_mac_eop => Rx_mac_eop,
--//user interface
Tx_mac_wa => Tx_mac_wa,
Tx_mac_wr => Tx_mac_wr,
Tx_mac_data => Tx_mac_data,
Tx_mac_BE => Tx_mac_BE, --//big endian
Tx_mac_sop => Tx_mac_sop,
Tx_mac_eop => Tx_mac_eop,
--//pkg_lgth fifo
-- signals for FIFO implementation of RX in core
-- with clock Clk_user!!
Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd,
Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra,
Pkg_lgth_fifo_data => Pkg_lgth_fifo_data,
--//Phy interface
Gtx_clk => GIGE_GTX_CLK_buf,--//used only in GMII mode
Crs => GIGE_CRS,
Col => GIGE_COL,
Rx_clk => Rx_clk,
--Tx_clk => Tx_clk, --//used only in MII mode
Tx_clk => GIGE_TX_CLK, --//used only in MII mode
--Tx_clk => '0',
Tx_er => Tx_er,
Tx_en => Tx_en,
Txd => Txd,
Rx_er => Rx_er,
Rx_dv => Rx_dv,
Rxd => Rxd,
--//host interface
CSB => CSB,
WRB => WRB,
CD_in => CD_in,
CD_out => CD_out,
CA => CA,
--//mdx
Mdo => Mdo, --// MII Management Data Output
MdoEn => MdoEn, --// MII Management Data Output Enable
Mdi => Mdi,
Mdc => MDC_sig, --// MII Management Data Clock
--
Divider => Divider,
CtrlData => CtrlData,
Rgad => Rgad,
Fiad => Fiad,
NoPre => NoPre,
WCtrlData => WCtrlData,
RStat => RStat,
ScanStat => ScanStat,
Busy => Busy,
LinkFail => LinkFail,
Nvalid => Nvalid,
Prsd => Prsd,
WCtrlDataStart => WCtrlDataStart,
RStatStart => RStatStart,
UpdateMIIRX_DATAReg => UpdateMIIRX_DATAReg
);
-- be careful!
GIGE_nRESET <= not reset;
GIGE_TX_ER <= Tx_er;
GIGE_TX_EN <= Tx_en;
GIGE_TXD <= Txd;
Rx_er <= GIGE_RX_ER;
Rx_dv <= GIGE_RX_DV;
Rxd <= GIGE_RXD;
Rx_clk <= GIGE_RX_CLK;
gmii_phy_rst_n <= not reset;
-- MIIM Management
GIGE_MDIO <= Mdo when MdoEn = '1' else
'Z';
Mdi <= GIGE_MDIO when MdoEn = '0' else
'Z';
CSB <= '0';
WRB <= '1';
calc_ipv4_checksum_inst : calc_ipv4_checksum
port map (
clk => clk_100mhz,--!!!!!!!!!!!
data => eth_array(8)(31 downto 16) & eth_array(7) & eth_array(6) &
eth_array(5) & eth_array(4)& eth_array(3)(15 downto 0),
--ready : out STD_LOGIC;
checksum => calc_checksum,
reset => reset
);
Rx_mac_rd <= Rx_mac_rd_sig AND Rx_mac_ra;
ethernet_data_rec_process : process(c3_rst0,clk_100mhz)
begin
if( c3_rst0 = '1' ) then
counter_ethernet_rec <= 0;
packet_valid <= '0';
Rx_mac_rd_sig <= '0';
arp_send <= '0';
arp_mac <= (others => '0');
arp_ip <= (others => '0');
dst_mac_addr_r <= (others => '0');
arp_valid <= '0';
arp_valid_response <= '0';
arp_valid_response_recieved <= '0';
elsif( rising_edge(clk_100mhz) ) then
if( config_checked = '1' ) then
Rx_mac_rd_sig <= '0';
if( arp_clear = '1' ) then
arp_send <= '0';
end if;
if( Rx_mac_ra = '1') then
Rx_mac_rd_sig <= '1';
if( Rx_mac_pa = '1' ) then
counter_ethernet_rec <= counter_ethernet_rec+1;
-- check if dest. is our FPGA device!!
-- when true then packet_valid is high else low
if( counter_ethernet_rec = 0 ) then
if( Rx_mac_data = own_mac_addr(47 downto 16) ) then
packet_valid <= '1';
else
packet_valid <= '0';
end if;
elsif( counter_ethernet_rec = 1 ) then
if( Rx_mac_data(31 downto 16) = own_mac_addr(15 downto 0) ) then
packet_valid <= '1';
else
packet_valid <= '0';
end if;
end if;
-- check if it is an ARP request, then arp_valid = '1'!!
if( counter_ethernet_rec = 3 ) then
--if( Rx_mac_data = ( x"0806" & x"0001" ) AND arp_send = '0' ) then
if( Rx_mac_data = ( x"0806" & x"0001" ) ) then
arp_valid <= '1';
else
arp_valid <= '0';
end if;
end if;
-- if ARP request, process packet further
if( arp_valid = '1' ) then
if( counter_ethernet_rec = 4 ) then
if( Rx_mac_data = ( x"0800" & x"06" & x"04" ) ) then
arp_valid <= '1';
else
arp_valid <= '0';
end if;
elsif( counter_ethernet_rec = 5 ) then
rx_state <= "000";
if( Rx_mac_data(31 downto 16) = x"0001" ) then
arp_valid <= '1';
arp_mac(47 downto 32) <= Rx_mac_data(15 downto 0);
elsif( Rx_mac_data(31 downto 16) = x"0002" ) then
arp_valid_response <= '1';
arp_mac(47 downto 32) <= Rx_mac_data(15 downto 0);
arp_valid <= '1';
else
arp_valid <= '0';
end if;
elsif( counter_ethernet_rec = 6 ) then
rx_state <= "001";
arp_mac(31 downto 0) <= Rx_mac_data;
elsif( counter_ethernet_rec = 7 ) then
rx_state <= "010";
arp_ip <= Rx_mac_data;
arp_valid_response <= '0';
if( Rx_mac_data = dst_ip_addr ) then
arp_valid_response <= '1';
end if;
elsif( counter_ethernet_rec = 8 ) then
rx_state <= "011";
arp_valid_response <= '0';
if( Rx_mac_data = own_mac_addr(47 downto 16) ) then
arp_valid_response <= '1';
end if;
elsif( counter_ethernet_rec = 9 ) then
rx_state <= "100";
if( Rx_mac_data(15 downto 0) = own_ip_addr(31 downto 16) ) then
arp_valid <= '1';
else
arp_valid <= '0';
end if;
arp_valid_response <= '0';
if( Rx_mac_data(31 downto 16) = own_mac_addr(15 downto 0) ) then
arp_valid_response <= '1';
end if;
elsif( counter_ethernet_rec = 10 ) then
rx_state <= "101";
arp_valid <= '0';
arp_valid_response <= '0';
if( Rx_mac_data(31 downto 16) = own_ip_addr(15 downto 0) ) then
if( arp_valid_response = '1' ) then
arp_valid_response_recieved <= '1';
arp_send <= '0';
dst_mac_addr_r <= arp_mac;
else
arp_send <= '1';
arp_valid_response_recieved <= '0';
end if;
end if;
end if;
end if;
end if;
else
counter_ethernet_rec <= 0;
end if;
end if;
end if;
end process;
udp_packet_data_process : process(c3_rst0,clk_100mhz)
begin
if( c3_rst0 = '1' ) then
counter_rx <= 0;
packet_vld <= '0';
elsif( falling_edge(clk_100mhz) ) then
if(packet_valid = '1') then
packet_vld <= '1';
end if;
if(counter_ethernet_rec = 10) then
udp_rx_pkt_data_tmp(rcv_pkt_data_length - 1 downto rcv_pkt_data_length - 16) <= Rx_mac_data(15 downto 0);
counter_rx <= 0;
elsif(counter_rx < rcv_length_ethernet_frame and packet_vld = '1') then
if(counter_rx < rcv_length_ethernet_frame - 1) then
udp_rx_pkt_data_tmp(rcv_pkt_data_length - 17 - (counter_rx * 32) downto rcv_pkt_data_length - 16 - (counter_rx * 32) - 32) <= Rx_mac_data;
else
if(rcv_pkt_byte_mod > 0) then
udp_rx_pkt_data_tmp(rcv_pkt_data_length - 17 - (counter_rx * 32) downto rcv_pkt_data_length - 16 - (counter_rx * 32) - rcv_pkt_data_mod) <= Rx_mac_data(31 downto 32 - rcv_pkt_data_mod);
else
udp_rx_pkt_data_tmp(rcv_pkt_data_length - 17 - (counter_rx * 32) downto rcv_pkt_data_length - 16 - (counter_rx * 32) - 32) <= Rx_mac_data;
end if;
end if;
counter_rx <= counter_rx + 1;
else
counter_rx <= 0;
end if;
if(counter_rx = rcv_length_ethernet_frame) then
packet_vld <= '0';
if(udp_rx_pkt_req = '1') then
udp_rx_pkt_data <= udp_rx_pkt_data_tmp;
udp_rx_rdy <= '1';
end if;
else
udp_rx_pkt_data <= (others => 'Z');
udp_rx_rdy <= '0';
end if;
end if;
end process;
ethernet_data_process : process(c3_rst0,clk_100mhz)
variable counter : integer := 0;
variable ip_header_length : std_logic_vector(15 downto 0);
variable udp_header_length : std_logic_vector(15 downto 0);
begin
Tx_mac_BE <= (others => 'Z');
-- determine ip header and udp header length attributes
if(pkt_byte_mod > 0)then
ip_header_length := conv_std_logic_vector((UDP_TX_DATA_BYTE_LENGTH + 28 + (4 - pkt_byte_mod)), 16);
udp_header_length := conv_std_logic_vector((UDP_TX_DATA_BYTE_LENGTH + 8 + (4 - pkt_byte_mod)), 16);
else
ip_header_length := conv_std_logic_vector((UDP_TX_DATA_BYTE_LENGTH + 28), 16);
udp_header_length := conv_std_logic_vector((UDP_TX_DATA_BYTE_LENGTH + 8), 16);
end if;
-- UDP packet
eth_array(0) <= dst_mac_addr_r(47 downto 16);
eth_array(1) <= dst_mac_addr_r(15 downto 0) & own_mac_addr(47 downto 32);
eth_array(2) <= own_mac_addr(31 downto 0);
-- ethernet type | Version / Header length | diff Services
eth_array(3) <= x"0800" & "0100" & "0101" & "00000000" ;
-- total length | identification
eth_array(4) <= ip_header_length & x"0000";
-- Flags , Fragment Offeset | time to live | protocol
eth_array(5) <= "0100000000000000" & "01000000" & "00010001";
-- header checksum | Source IP:
eth_array(6) <= calc_checksum & own_ip_addr(31 downto 16);
-- | Destin IP:
eth_array(7) <= own_ip_addr(15 downto 0) & dst_ip_addr(31 downto 16);
-- | source port
eth_array(8) <= dst_ip_addr(15 downto 0) & udp_src_port ;
-- dest port | length
eth_array(9) <= udp_dst_port & udp_header_length ;
-- checksum | data
eth_array(10)(31 downto 16) <= x"0000";
-- data
--eth_array(11) <= conv_std_logic_vector(udp_counter, 32);--x"6c6c6f20";
if(pkt_data_length = 8) then
eth_array(10)(15 downto 0) <= (15 downto 8 => '0') & udp_tx_pkt_data;
else
eth_array(10)(15 downto 0) <= udp_tx_pkt_data(pkt_data_length - 1 downto pkt_data_length - 16);
end if;
counter := 0;
for i in 11 to length_ethernet_frame - 2 loop
eth_array(i) <= udp_tx_pkt_data(pkt_data_length - (counter * 32) - 17 downto pkt_data_length - (counter * 32) - 48);
counter := counter + 1;
end loop;
if(pkt_byte_mod > 0) then
eth_array(length_ethernet_frame - 1) <= udp_tx_pkt_data(pkt_data_mod - 1 downto 0) & (32 - pkt_data_mod - 1 downto 0 => '0');
else
eth_array(length_ethernet_frame - 1) <= udp_tx_pkt_data(31 downto 0);
end if;
-- answer to ARP request from any computer
arp_array(0) <= arp_mac(47 downto 16);
arp_array(1) <= arp_mac(15 downto 0) & own_mac_addr(47 downto 32);
arp_array(2) <= own_mac_addr(31 downto 0);
arp_array(3) <= x"0806" & x"0001";
arp_array(4) <= x"0800" & x"06" & x"04";
arp_array(5) <= x"0002" & own_mac_addr(47 downto 32);
arp_array(6) <= own_mac_addr(31 downto 0);
arp_array(7) <= own_ip_addr;
arp_array(8) <= arp_mac(47 downto 16);
arp_array(9) <= arp_mac(15 downto 0) & arp_ip(31 downto 16);
arp_array(10) <= arp_ip(15 downto 0) & x"0000";
-- init ARP request array
arp_request_array(0) <= x"FFFFFFFF";
arp_request_array(1) <= x"FFFF" & own_mac_addr(47 downto 32);
arp_request_array(2) <= own_mac_addr(31 downto 0);
arp_request_array(3) <= x"0806" & x"0001";
arp_request_array(4) <= x"0800" & x"06" & x"04";
arp_request_array(5) <= x"0001" & own_mac_addr(47 downto 32);
arp_request_array(6) <= own_mac_addr(31 downto 0);
arp_request_array(7) <= own_ip_addr;
arp_request_array(8) <= x"00000000";
arp_request_array(9) <= x"0000" & dst_ip_addr(31 downto 16);
arp_request_array(10) <= dst_ip_addr(15 downto 0) & x"0000";
if( c3_rst0 = '1' ) then
Tx_mac_wr <= '0';
Tx_mac_sop <= '0';
Tx_mac_eop <= '0';
counter_ethernet <= 0;
counter_ethernet_delay <= 0;
state_ethernet <= arp;
arp_clear <= '0';
elsif( rising_edge(clk_100mhz) ) then
Tx_mac_sop <= '0';
Tx_mac_eop <= '0';
Tx_mac_wr <= '0';
arp_clear <= '0';
if (config_checked = '1') then
-- signal start of the frame
if( Tx_mac_wa = '1' AND counter_ethernet = 0 AND counter_ethernet_delay = 0) then
Tx_mac_sop <= '1';
end if;
case state_ethernet is
-- send ARP request to recieve the MAC of dst_ip_addr
when arp =>
tx_state <= "000";
if( Tx_mac_wa = '1') then
state_ethernet <= arp;
Tx_mac_wr <= '1';
if( counter_ethernet < length_ethernet_arp_request_frame-1 ) then
counter_ethernet <= counter_ethernet + 1;
else
state_ethernet <= arp_wait;
-- signal end of the frame
Tx_mac_eop <= '1';
Tx_mac_BE <= "00";
end if;
Tx_mac_data <= arp_request_array(counter_ethernet);
else
state_ethernet <= arp_wait;
end if;
-- wait some time to recieve answer to ARP request
when arp_wait =>
tx_state <= "001";
counter_ethernet <= 0;
Tx_mac_data <= (others => '0');
if( counter_ethernet_delay < 2**21-1 ) then
counter_ethernet_delay <= counter_ethernet_delay + 1;
state_ethernet <= arp_wait;
else
state_ethernet <= arp;
counter_ethernet_delay <= 0;
end if;
if( arp_valid_response_recieved = '1' ) then
state_ethernet <= idle;
end if;
-- respond to ARP request
when idle =>
tx_state <= "010";
if( Tx_mac_wa = '1' ) then
state_ethernet <= idle;
Tx_mac_wr <= '1';
if( arp_send = '1' ) then
if( counter_ethernet < length_ethernet_arp_frame-1 ) then
counter_ethernet <= counter_ethernet + 1;
else
--counter_ethernet <= 0;
state_ethernet <= wait_state2;
arp_clear <= '1';
-- signal end of the frame
Tx_mac_BE <= "00";
Tx_mac_eop <= '1';
end if;
Tx_mac_data <= arp_array(counter_ethernet);
else
if( counter_ethernet < length_ethernet_frame-1 ) then
counter_ethernet <= counter_ethernet + 1;
else
--counter_ethernet <= 0;
Tx_mac_eop <= '1';
-- signal end of the frame
Tx_mac_BE <= "00";
state_ethernet <= wait_state2;
end if;
Tx_mac_data <= eth_array(counter_ethernet);
end if;
else
state_ethernet <= wait_state;
end if;
-- wait some time till Tx_mac_wa is high again
when wait_state =>
tx_state <= "101";
if( Tx_mac_wa = '1' ) then
state_ethernet <= idle;
else
state_ethernet <= wait_state;
end if;
-- wait such that throughput is not as high as possible
when wait_state2 =>
tx_state <= "110";
mac_init_ok <= '1';
counter_ethernet <= 0;
counter_ethernet_delay <= 0;
if(udp_tx_pkt_vld = '1' or arp_send = '1') then
state_ethernet <= idle;
else
state_ethernet <= wait_state2;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Marvell 88E1111S initialization
------------------------------------------------------------------------------
phy_config : process(clk_100mhz)
begin
if(rising_edge(clk_100mhz)) then
case config_state is
when 0 =>
if(config_delay_count < 250000000) then
config_delay_count <= config_delay_count + 1;
--else
elsif(config_checked = '0') then
phy_reg_addr <= phy_reg_addr + 1;
config_state <= 1;
end if;
when 1 =>
CtrlData <= x"0C61";
Rgad <= "10100"; -- Register 20
NoPre <= '0';
WCtrlData <= '1';
RStat <= '0';
ScanStat <= '0';
config_state <= 2;
when 2 =>
if(Busy = '1') then
config_state <= 3;
end if;
when 3 =>
if(Busy = '0') then
config_state <= 4;
elsif(MdoEn = '0') then
WCtrlData <= '0';
end if;
when 4 =>
CtrlData <= x"0000";
Rgad <= "10100";
NoPre <= '0';
WCtrlData <= '0';
RStat <= '1';
ScanStat <= '0';
config_state <= 5;
when 5 =>
if(Busy = '1') then
config_state <= 6;
end if;
when 6 =>
if(Busy = '0') then
config_delay_count <= 0;
config_checked <= '1';
config_state <= 0;
elsif(MdoEn = '0') then
RStat <= '0';
end if;
when others =>
null;
end case;
end if;
end process;
-- ODDR2 is needed instead of the following
-- GIGE_GTX_CLK <= GIGE_GTX_CLK_buf;
-- because GIGE_GTX_CLK is dcm_vga_clk_125mhz
-- and limiting in Spartan 6
txclk_ODDR2_inst : ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => GIGE_GTX_CLK, -- 1-bit DDR output data
C0 => GIGE_GTX_CLK_buf, -- clock is your signal from PLL
C1 => not(GIGE_GTX_CLK_buf), -- n
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0' -- 1-bit data input (associated with C1)
);
-- ODDR2 is needed instead of the following
-- GIGE_GTX_CLK <= GIGE_GTX_CLK_buf;
-- because GIGE_GTX_CLK is dcm_vga_clk_125mhz
-- and limiting in Spartan 6
MDC_ODDR2_inst : ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => GIGE_MDC, -- 1-bit DDR output data
C0 => MDC_sig, -- clock is your signal from PLL
C1 => not(MDC_sig), -- n
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0' -- 1-bit data input (associated with C1)
);
-----------------------------------------------------------------------
-- DEBUGGING SECTION
-----------------------------------------------------------------------
--icon_inst : icon
--port map (
--CONTROL0 => CONTROL0,
--CONTROL1 => CONTROL1,
--CONTROL2 => CONTROL2);
--ila0_inst : ila0
--port map (
--CONTROL => CONTROL0,
--CLK => clk_100mhz,
--DATA => ila_data0,
--TRIG0 => TRIG0);
--ila1_inst : ila1
--port map (
--CONTROL => CONTROL1,
--CLK => clk_125mhz,
--DATA => ila_data1,
--TRIG0 => TRIG1);
--vio_inst : vio
--port map (
--CONTROL => CONTROL2,
--ASYNC_OUT => vio_data);
-- ila_data0(31 downto 0) <= Tx_mac_data;
--ila_data0(63 downto 32) <= Rx_mac_data;
--ila_data0(66 downto 64) <= tx_state;
--ila_data0(0) <= Tx_mac_wr;
--ila_data0(1) <= Rx_mac_rd;
--ila_data0(2) <= Tx_mac_sop;
--ila_data0(3) <= Tx_mac_eop;
--ila_data0(4) <= Rx_mac_sop;
--ila_data0(5) <= Rx_mac_eop;
--ila_data0(6) <= Tx_mac_wa;
--ila_data0(9 downto 7) <= tx_state;
--ila_data0(75 downto 74) <= Tx_mac_BE;
--ila_data0(297 downto 74) <= udp_rx_pkt_data_tmp;
--ila_data0(298) <= packet_vld;
--trig0(2 downto 0) <= tx_state; --conv_std_logic_vector(config_state,5); --tx_state;
--trig0(0) <= udp_tx_pkt_vld;
--ila_data1(7 downto 0) <= Txd;
--ila_data1(15 downto 8) <= Rxd;
--ila_data1(18 downto 16) <= ethernet_speed;
--ila_data1(19) <= Tx_mac_wa;
--ila_data1(20) <= Rx_mac_ra;
--ila_data1(21) <= Tx_er;
--ila_data1(22) <= Rx_er;
--ila_data1(23) <= gmii_phy_rst_n;
--ila_data1(24) <= reset;
--ila_data1(25) <= Rx_mac_pa;
--ila_data1(26) <= GIGE_RX_CLK;
end arc; | gpl-3.0 | f0bcf9580356217648d427d7127ddce5 | 0.557769 | 2.957492 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/spi/spi_top.vhd | 1 | 4,202 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity spi_top is
generic(
tx_ram_depth : integer;
tx_max_block_size : integer;
cpol : integer;
cpha : integer
);
port(
ctrl : in ctrl_t;
--hardware interface
cs_n : in std_logic;
sclk : in std_logic;
mosi : in std_logic;
miso : out std_logic;
-- internal receive interface
new_mcu_to_fpga_data : out std_logic;
mcu_to_fpga_data : out std_logic_vector(spi_word_length - 1 downto 0);
-- internal tx interface
enqueue_fpga_to_mcu_data : in std_logic;
fpga_to_mcu_data : in std_logic_vector(15 downto 0);
-- debug from transmitter
full : out std_logic;
contents_count : out integer range 0 to tx_ram_depth
);
end spi_top;
architecture rtl of spi_top is
--signal data_tentatively_latched : std_logic;
signal data_fully_latched : std_logic;
signal header_byte : std_logic_vector(7 downto 0);
signal next_tx_word : std_logic_vector(15 downto 0);
signal tx_header_byte : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
signal latched_data : std_logic_vector(7 downto 0);
signal dequeue : std_logic;
signal empty : std_logic;
signal contents_count_int : integer range 0 to tx_ram_depth;
signal new_mcu_to_fpga_data_from_rx : std_logic;
signal remaining_bytes : integer range 0 to 255;
signal mcu_to_fpga_data_int : std_logic_vector(7 downto 0);
begin
spi_tx_1 : entity virtual_button_lib.spi_tx
generic map (
cpol => cpol,
cpha => cpha)
port map (
ctrl => ctrl,
cs_n => cs_n,
sclk => sclk,
miso => miso,
data => tx_byte,
latched_data => latched_data,
data_fully_latched => data_fully_latched);
tx_fifo : entity work.circular_queue
generic map(
queue_depth => tx_ram_depth,
queue_width => 16
)
port map (
ctrl => ctrl,
enqueue => enqueue_fpga_to_mcu_data,
dequeue => dequeue,
write_in_data => std_logic_vector(fpga_to_mcu_data),
read_out_data => next_tx_word,
empty => empty,
full => full,
contents_count => contents_count_int);
tx_controller : entity virtual_button_lib.spi_tx_ram_controller
generic map(
tx_max_block_size => tx_max_block_size)
port map(
ctrl => ctrl,
contents_count => contents_count_int,
data_fully_latched => data_fully_latched,
next_tx_word => next_tx_word,
latched_data => latched_data,
tx_byte => tx_byte,
dequeue => dequeue
);
contents_count <= contents_count_int;
spi_rx_1 : entity virtual_button_lib.spi_rx
generic map (
cpol => cpol,
cpha => cpha)
port map (
ctrl => ctrl,
sclk => sclk,
cs_n => cs_n,
mosi => mosi,
data => mcu_to_fpga_data_int,
new_data => new_mcu_to_fpga_data_from_rx);
-- spi_rx does not know about data framing. This process does.
-- WOrks out if if a received byte is data or framing-information. If it is
-- data, then flats it to the rest of the fpga through new_mcu_to_fpga_data
decode_rx_frame : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
remaining_bytes <= 0;
new_mcu_to_fpga_data <= '0';
else
new_mcu_to_fpga_data <= '0';
if new_mcu_to_fpga_data_from_rx = '1' and remaining_bytes = 0 then
remaining_bytes <= to_integer(unsigned(mcu_to_fpga_data_int));
elsif new_mcu_to_fpga_data_from_rx = '1' and remaining_bytes > 0 then
remaining_bytes <= remaining_bytes - 1;
new_mcu_to_fpga_data <= '1';
end if;
end if;
end if;
end process;
mcu_to_fpga_data <= mcu_to_fpga_data_int;
end rtl;
| bsd-2-clause | 4a4be7946faeacee6df3de5d21b0353c | 0.569253 | 3.466997 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_512.vhd | 1 | 134,346 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_512.vhd
-- /___/ /\ Timestamp: Wed Aug 13 01:45:08 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_512;
architecture STRUCTURE of fifo_generator_64_512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_171
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_173
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_164,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_169
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_Q : XORCY
port map (
CI => N0,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_0_Q : MUXCY
port map (
CI => N0,
DI => N1,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Result(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_105
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_170,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_174,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_172,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_165,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_163,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_not00001 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_and00001 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or00001 : LUT6
generic map(
INIT => X"F3A2F300FFA2FF00"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_24,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"2F0222022F222222"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp2,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_7_rt_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_6_rt_39
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_5_rt_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_4_rt_35
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_3_rt_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_2_rt_31
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_cy_1_rt_29
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_7_rt_120
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_6_rt_118
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_5_rt_116
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_4_rt_114
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_3_rt_112
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_2_rt_110
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_cy_1_rt_108
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_8_rt_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_8_rt_122
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_104,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_162,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut_0_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(8),
RDADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(7),
RDADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(6),
RDADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(5),
RDADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRL(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRL(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRL(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRL(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(8),
WRADDRU(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(7),
WRADDRU(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(6),
WRADDRU(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(5),
WRADDRU(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 87b25526d77b39a4205b49d88020f12b | 0.689258 | 2.640915 | false | false | false | false |
jhennessy/parallella-hw-old | fpga/projects/vivado_parallella_7010_headless/parallella_7010_headless.srcs/sources_1/ip/processing_system7_0/processing_system7_0_funcsim.vhdl | 1 | 246,108 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
-- Date : Sun Nov 2 20:42:29 2014
-- Host : ubuntu-imac running 64-bit Ubuntu 14.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/john/parallella-hw/fpga/projects/vivado_parallella_7010_headless/parallela_7010_headless/parallela_7010_headless.srcs/sources_1/ip/processing_system7_0/processing_system7_0_funcsim.vhdl
-- Design : processing_system7_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity processing_system7_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute POWER : string;
attribute POWER of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }";
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "true";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "false";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "false";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "true";
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 48;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of processing_system7_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
end processing_system7_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of processing_system7_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 3 downto 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal n_1000_PS7_i : STD_LOGIC;
signal n_701_PS7_i : STD_LOGIC;
signal n_702_PS7_i : STD_LOGIC;
signal n_703_PS7_i : STD_LOGIC;
signal n_704_PS7_i : STD_LOGIC;
signal n_953_PS7_i : STD_LOGIC;
signal n_954_PS7_i : STD_LOGIC;
signal n_955_PS7_i : STD_LOGIC;
signal n_956_PS7_i : STD_LOGIC;
signal n_957_PS7_i : STD_LOGIC;
signal n_958_PS7_i : STD_LOGIC;
signal n_959_PS7_i : STD_LOGIC;
signal n_960_PS7_i : STD_LOGIC;
signal n_961_PS7_i : STD_LOGIC;
signal n_962_PS7_i : STD_LOGIC;
signal n_963_PS7_i : STD_LOGIC;
signal n_964_PS7_i : STD_LOGIC;
signal n_965_PS7_i : STD_LOGIC;
signal n_966_PS7_i : STD_LOGIC;
signal n_967_PS7_i : STD_LOGIC;
signal n_968_PS7_i : STD_LOGIC;
signal n_969_PS7_i : STD_LOGIC;
signal n_970_PS7_i : STD_LOGIC;
signal n_971_PS7_i : STD_LOGIC;
signal n_972_PS7_i : STD_LOGIC;
signal n_973_PS7_i : STD_LOGIC;
signal n_974_PS7_i : STD_LOGIC;
signal n_975_PS7_i : STD_LOGIC;
signal n_976_PS7_i : STD_LOGIC;
signal n_977_PS7_i : STD_LOGIC;
signal n_978_PS7_i : STD_LOGIC;
signal n_979_PS7_i : STD_LOGIC;
signal n_980_PS7_i : STD_LOGIC;
signal n_981_PS7_i : STD_LOGIC;
signal n_982_PS7_i : STD_LOGIC;
signal n_983_PS7_i : STD_LOGIC;
signal n_984_PS7_i : STD_LOGIC;
signal n_985_PS7_i : STD_LOGIC;
signal n_986_PS7_i : STD_LOGIC;
signal n_987_PS7_i : STD_LOGIC;
signal n_988_PS7_i : STD_LOGIC;
signal n_989_PS7_i : STD_LOGIC;
signal n_990_PS7_i : STD_LOGIC;
signal n_991_PS7_i : STD_LOGIC;
signal n_992_PS7_i : STD_LOGIC;
signal n_993_PS7_i : STD_LOGIC;
signal n_994_PS7_i : STD_LOGIC;
signal n_995_PS7_i : STD_LOGIC;
signal n_996_PS7_i : STD_LOGIC;
signal n_997_PS7_i : STD_LOGIC;
signal n_998_PS7_i : STD_LOGIC;
signal n_999_PS7_i : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOGPIOO_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 48 );
signal NLW_PS7_i_EMIOGPIOTN_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 48 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_3.FCLK_CLK_3_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \<const0>\;
TRACE_DATA(1) <= \<const0>\;
TRACE_DATA(0) <= \<const0>\;
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_1000_PS7_i,
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_990_PS7_i,
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_989_PS7_i,
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_988_PS7_i,
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_987_PS7_i,
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_986_PS7_i,
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_985_PS7_i,
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_984_PS7_i,
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_983_PS7_i,
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_982_PS7_i,
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_981_PS7_i,
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_999_PS7_i,
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_980_PS7_i,
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_979_PS7_i,
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_978_PS7_i,
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_977_PS7_i,
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_976_PS7_i,
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_975_PS7_i,
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_974_PS7_i,
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_973_PS7_i,
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_972_PS7_i,
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_971_PS7_i,
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_998_PS7_i,
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_970_PS7_i,
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_969_PS7_i,
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_968_PS7_i,
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_967_PS7_i,
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_966_PS7_i,
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_965_PS7_i,
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_964_PS7_i,
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_963_PS7_i,
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_962_PS7_i,
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_961_PS7_i,
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_997_PS7_i,
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_960_PS7_i,
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_959_PS7_i,
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_958_PS7_i,
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_957_PS7_i,
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_956_PS7_i,
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_955_PS7_i,
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_954_PS7_i,
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_953_PS7_i,
O => GPIO_T(47)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_996_PS7_i,
O => GPIO_T(4)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_995_PS7_i,
O => GPIO_T(5)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_994_PS7_i,
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_993_PS7_i,
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_992_PS7_i,
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_991_PS7_i,
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7) => '0',
EMIOENET0GMIIRXD(6) => '0',
EMIOENET0GMIIRXD(5) => '0',
EMIOENET0GMIIRXD(4) => '0',
EMIOENET0GMIIRXD(3) => '0',
EMIOENET0GMIIRXD(2) => '0',
EMIOENET0GMIIRXD(1) => '0',
EMIOENET0GMIIRXD(0) => '0',
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7) => '0',
EMIOENET1GMIIRXD(6) => '0',
EMIOENET1GMIIRXD(5) => '0',
EMIOENET1GMIIRXD(4) => '0',
EMIOENET1GMIIRXD(3) => '0',
EMIOENET1GMIIRXD(2) => '0',
EMIOENET1GMIIRXD(1) => '0',
EMIOENET1GMIIRXD(0) => '0',
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63) => \<const0>\,
EMIOGPIOI(62) => \<const0>\,
EMIOGPIOI(61) => \<const0>\,
EMIOGPIOI(60) => \<const0>\,
EMIOGPIOI(59) => \<const0>\,
EMIOGPIOI(58) => \<const0>\,
EMIOGPIOI(57) => \<const0>\,
EMIOGPIOI(56) => \<const0>\,
EMIOGPIOI(55) => \<const0>\,
EMIOGPIOI(54) => \<const0>\,
EMIOGPIOI(53) => \<const0>\,
EMIOGPIOI(52) => \<const0>\,
EMIOGPIOI(51) => \<const0>\,
EMIOGPIOI(50) => \<const0>\,
EMIOGPIOI(49) => \<const0>\,
EMIOGPIOI(48) => \<const0>\,
EMIOGPIOI(47 downto 0) => GPIO_I(47 downto 0),
EMIOGPIOO(63 downto 48) => NLW_PS7_i_EMIOGPIOO_UNCONNECTED(63 downto 48),
EMIOGPIOO(47 downto 0) => GPIO_O(47 downto 0),
EMIOGPIOTN(63 downto 48) => NLW_PS7_i_EMIOGPIOTN_UNCONNECTED(63 downto 48),
EMIOGPIOTN(47) => n_953_PS7_i,
EMIOGPIOTN(46) => n_954_PS7_i,
EMIOGPIOTN(45) => n_955_PS7_i,
EMIOGPIOTN(44) => n_956_PS7_i,
EMIOGPIOTN(43) => n_957_PS7_i,
EMIOGPIOTN(42) => n_958_PS7_i,
EMIOGPIOTN(41) => n_959_PS7_i,
EMIOGPIOTN(40) => n_960_PS7_i,
EMIOGPIOTN(39) => n_961_PS7_i,
EMIOGPIOTN(38) => n_962_PS7_i,
EMIOGPIOTN(37) => n_963_PS7_i,
EMIOGPIOTN(36) => n_964_PS7_i,
EMIOGPIOTN(35) => n_965_PS7_i,
EMIOGPIOTN(34) => n_966_PS7_i,
EMIOGPIOTN(33) => n_967_PS7_i,
EMIOGPIOTN(32) => n_968_PS7_i,
EMIOGPIOTN(31) => n_969_PS7_i,
EMIOGPIOTN(30) => n_970_PS7_i,
EMIOGPIOTN(29) => n_971_PS7_i,
EMIOGPIOTN(28) => n_972_PS7_i,
EMIOGPIOTN(27) => n_973_PS7_i,
EMIOGPIOTN(26) => n_974_PS7_i,
EMIOGPIOTN(25) => n_975_PS7_i,
EMIOGPIOTN(24) => n_976_PS7_i,
EMIOGPIOTN(23) => n_977_PS7_i,
EMIOGPIOTN(22) => n_978_PS7_i,
EMIOGPIOTN(21) => n_979_PS7_i,
EMIOGPIOTN(20) => n_980_PS7_i,
EMIOGPIOTN(19) => n_981_PS7_i,
EMIOGPIOTN(18) => n_982_PS7_i,
EMIOGPIOTN(17) => n_983_PS7_i,
EMIOGPIOTN(16) => n_984_PS7_i,
EMIOGPIOTN(15) => n_985_PS7_i,
EMIOGPIOTN(14) => n_986_PS7_i,
EMIOGPIOTN(13) => n_987_PS7_i,
EMIOGPIOTN(12) => n_988_PS7_i,
EMIOGPIOTN(11) => n_989_PS7_i,
EMIOGPIOTN(10) => n_990_PS7_i,
EMIOGPIOTN(9) => n_991_PS7_i,
EMIOGPIOTN(8) => n_992_PS7_i,
EMIOGPIOTN(7) => n_993_PS7_i,
EMIOGPIOTN(6) => n_994_PS7_i,
EMIOGPIOTN(5) => n_995_PS7_i,
EMIOGPIOTN(4) => n_996_PS7_i,
EMIOGPIOTN(3) => n_997_PS7_i,
EMIOGPIOTN(2) => n_998_PS7_i,
EMIOGPIOTN(1) => n_999_PS7_i,
EMIOGPIOTN(0) => n_1000_PS7_i,
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => p_0_in(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3) => n_701_PS7_i,
EMIOSDIO1DATATN(2) => n_702_PS7_i,
EMIOSDIO1DATATN(1) => n_703_PS7_i,
EMIOSDIO1DATATN(0) => n_704_PS7_i,
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK_unbuffered(3),
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3) => \<const0>\,
FCLKCLKTRIGN(2) => \<const0>\,
FCLKCLKTRIGN(1) => \<const0>\,
FCLKCLKTRIGN(0) => \<const0>\,
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3) => '0',
FTMDTRACEINATID(2) => '0',
FTMDTRACEINATID(1) => '0',
FTMDTRACEINATID(0) => '0',
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31) => '0',
FTMDTRACEINDATA(30) => '0',
FTMDTRACEINDATA(29) => '0',
FTMDTRACEINDATA(28) => '0',
FTMDTRACEINDATA(27) => '0',
FTMDTRACEINDATA(26) => '0',
FTMDTRACEINDATA(25) => '0',
FTMDTRACEINDATA(24) => '0',
FTMDTRACEINDATA(23) => '0',
FTMDTRACEINDATA(22) => '0',
FTMDTRACEINDATA(21) => '0',
FTMDTRACEINDATA(20) => '0',
FTMDTRACEINDATA(19) => '0',
FTMDTRACEINDATA(18) => '0',
FTMDTRACEINDATA(17) => '0',
FTMDTRACEINDATA(16) => '0',
FTMDTRACEINDATA(15) => '0',
FTMDTRACEINDATA(14) => '0',
FTMDTRACEINDATA(13) => '0',
FTMDTRACEINDATA(12) => '0',
FTMDTRACEINDATA(11) => '0',
FTMDTRACEINDATA(10) => '0',
FTMDTRACEINDATA(9) => '0',
FTMDTRACEINDATA(8) => '0',
FTMDTRACEINDATA(7) => '0',
FTMDTRACEINDATA(6) => '0',
FTMDTRACEINDATA(5) => '0',
FTMDTRACEINDATA(4) => '0',
FTMDTRACEINDATA(3) => '0',
FTMDTRACEINDATA(2) => '0',
FTMDTRACEINDATA(1) => '0',
FTMDTRACEINDATA(0) => '0',
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15) => \<const0>\,
IRQF2P(14) => \<const0>\,
IRQF2P(13) => \<const0>\,
IRQF2P(12) => \<const0>\,
IRQF2P(11) => \<const0>\,
IRQF2P(10) => \<const0>\,
IRQF2P(9) => \<const0>\,
IRQF2P(8) => \<const0>\,
IRQF2P(7) => \<const0>\,
IRQF2P(6) => \<const0>\,
IRQF2P(5) => \<const0>\,
IRQF2P(4) => \<const0>\,
IRQF2P(3) => \<const0>\,
IRQF2P(2) => \<const0>\,
IRQF2P(1) => \<const0>\,
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 32) => NLW_PS7_i_SAXIHP0RDATA_UNCONNECTED(63 downto 32),
SAXIHP0RDATA(31 downto 0) => S_AXI_HP0_RDATA(31 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63) => \<const0>\,
SAXIHP0WDATA(62) => \<const0>\,
SAXIHP0WDATA(61) => \<const0>\,
SAXIHP0WDATA(60) => \<const0>\,
SAXIHP0WDATA(59) => \<const0>\,
SAXIHP0WDATA(58) => \<const0>\,
SAXIHP0WDATA(57) => \<const0>\,
SAXIHP0WDATA(56) => \<const0>\,
SAXIHP0WDATA(55) => \<const0>\,
SAXIHP0WDATA(54) => \<const0>\,
SAXIHP0WDATA(53) => \<const0>\,
SAXIHP0WDATA(52) => \<const0>\,
SAXIHP0WDATA(51) => \<const0>\,
SAXIHP0WDATA(50) => \<const0>\,
SAXIHP0WDATA(49) => \<const0>\,
SAXIHP0WDATA(48) => \<const0>\,
SAXIHP0WDATA(47) => \<const0>\,
SAXIHP0WDATA(46) => \<const0>\,
SAXIHP0WDATA(45) => \<const0>\,
SAXIHP0WDATA(44) => \<const0>\,
SAXIHP0WDATA(43) => \<const0>\,
SAXIHP0WDATA(42) => \<const0>\,
SAXIHP0WDATA(41) => \<const0>\,
SAXIHP0WDATA(40) => \<const0>\,
SAXIHP0WDATA(39) => \<const0>\,
SAXIHP0WDATA(38) => \<const0>\,
SAXIHP0WDATA(37) => \<const0>\,
SAXIHP0WDATA(36) => \<const0>\,
SAXIHP0WDATA(35) => \<const0>\,
SAXIHP0WDATA(34) => \<const0>\,
SAXIHP0WDATA(33) => \<const0>\,
SAXIHP0WDATA(32) => \<const0>\,
SAXIHP0WDATA(31 downto 0) => S_AXI_HP0_WDATA(31 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7) => \<const0>\,
SAXIHP0WSTRB(6) => \<const0>\,
SAXIHP0WSTRB(5) => \<const0>\,
SAXIHP0WSTRB(4) => \<const0>\,
SAXIHP0WSTRB(3 downto 0) => S_AXI_HP0_WSTRB(3 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_704_PS7_i,
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_703_PS7_i,
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_702_PS7_i,
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => n_701_PS7_i,
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\buffer_fclk_clk_3.FCLK_CLK_3_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(3),
O => FCLK_CLK3
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity processing_system7_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK3 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of processing_system7_0 : entity is true;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of processing_system7_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2014.3";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of processing_system7_0 : entity is "processing_system7_0,processing_system7_v5_5_processing_system7,{}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of processing_system7_0 : entity is "processing_system7_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=48,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=true,C_PACKAGE_NAME=clg400}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of processing_system7_0 : entity is "yes";
end processing_system7_0;
architecture STRUCTURE of processing_system7_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CORE_GENERATION_INFO of inst : label is "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=400, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=9, PCW_UIPARAM_DDR_CWL=9, PCW_UIPARAM_DDR_T_RCD=9, PCW_UIPARAM_DDR_T_RP=9, PCW_UIPARAM_DDR_T_RC=60, PCW_UIPARAM_DDR_T_RAS_MIN=40, PCW_UIPARAM_DDR_T_FAW=50, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.315, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.391, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.374, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.271, PCW_UIPARAM_DDR_BOARD_DELAY0=0.434, PCW_UIPARAM_DDR_BOARD_DELAY1=0.398, PCW_UIPARAM_DDR_BOARD_DELAY2=0.41, PCW_UIPARAM_DDR_BOARD_DELAY3=0.455, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=200.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=40.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=48, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1600.000, PCW_USE_M_AXI_GP0=0, PCW_USE_M_AXI_GP1=1, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=Custom, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=1, PCW_USB1_USB1_IO=MIO 40 .. 51, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=48, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }";
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 48;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "true";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "false";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "false";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "true";
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1600.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={10} usageRate={0.5} /><AXI interface={M_AXI_GP1} dataWidth={32} clockFreq={10} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of inst : label is "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX";
begin
inst: entity work.processing_system7_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3) => '0',
DDR_ARB(2) => '0',
DDR_ARB(1) => '0',
DDR_ARB(0) => '0',
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1) => '0',
DMA0_DRTYPE(0) => '0',
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1) => '0',
DMA1_DRTYPE(0) => '0',
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1) => '0',
DMA2_DRTYPE(0) => '0',
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1) => '0',
DMA3_DRTYPE(0) => '0',
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7) => '0',
ENET0_GMII_RXD(6) => '0',
ENET0_GMII_RXD(5) => '0',
ENET0_GMII_RXD(4) => '0',
ENET0_GMII_RXD(3) => '0',
ENET0_GMII_RXD(2) => '0',
ENET0_GMII_RXD(1) => '0',
ENET0_GMII_RXD(0) => '0',
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX => ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX => ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX => ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX => ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX => ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX => ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX => ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX => ENET0_SOF_RX,
ENET0_SOF_TX => ENET0_SOF_TX,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7) => '0',
ENET1_GMII_RXD(6) => '0',
ENET1_GMII_RXD(5) => '0',
ENET1_GMII_RXD(4) => '0',
ENET1_GMII_RXD(3) => '0',
ENET1_GMII_RXD(2) => '0',
ENET1_GMII_RXD(1) => '0',
ENET1_GMII_RXD(0) => '0',
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => FCLK_CLK3,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3) => '0',
FTMD_TRACEIN_ATID(2) => '0',
FTMD_TRACEIN_ATID(1) => '0',
FTMD_TRACEIN_ATID(0) => '0',
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31) => '0',
FTMD_TRACEIN_DATA(30) => '0',
FTMD_TRACEIN_DATA(29) => '0',
FTMD_TRACEIN_DATA(28) => '0',
FTMD_TRACEIN_DATA(27) => '0',
FTMD_TRACEIN_DATA(26) => '0',
FTMD_TRACEIN_DATA(25) => '0',
FTMD_TRACEIN_DATA(24) => '0',
FTMD_TRACEIN_DATA(23) => '0',
FTMD_TRACEIN_DATA(22) => '0',
FTMD_TRACEIN_DATA(21) => '0',
FTMD_TRACEIN_DATA(20) => '0',
FTMD_TRACEIN_DATA(19) => '0',
FTMD_TRACEIN_DATA(18) => '0',
FTMD_TRACEIN_DATA(17) => '0',
FTMD_TRACEIN_DATA(16) => '0',
FTMD_TRACEIN_DATA(15) => '0',
FTMD_TRACEIN_DATA(14) => '0',
FTMD_TRACEIN_DATA(13) => '0',
FTMD_TRACEIN_DATA(12) => '0',
FTMD_TRACEIN_DATA(11) => '0',
FTMD_TRACEIN_DATA(10) => '0',
FTMD_TRACEIN_DATA(9) => '0',
FTMD_TRACEIN_DATA(8) => '0',
FTMD_TRACEIN_DATA(7) => '0',
FTMD_TRACEIN_DATA(6) => '0',
FTMD_TRACEIN_DATA(5) => '0',
FTMD_TRACEIN_DATA(4) => '0',
FTMD_TRACEIN_DATA(3) => '0',
FTMD_TRACEIN_DATA(2) => '0',
FTMD_TRACEIN_DATA(1) => '0',
FTMD_TRACEIN_DATA(0) => '0',
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31) => '0',
FTMT_F2P_DEBUG(30) => '0',
FTMT_F2P_DEBUG(29) => '0',
FTMT_F2P_DEBUG(28) => '0',
FTMT_F2P_DEBUG(27) => '0',
FTMT_F2P_DEBUG(26) => '0',
FTMT_F2P_DEBUG(25) => '0',
FTMT_F2P_DEBUG(24) => '0',
FTMT_F2P_DEBUG(23) => '0',
FTMT_F2P_DEBUG(22) => '0',
FTMT_F2P_DEBUG(21) => '0',
FTMT_F2P_DEBUG(20) => '0',
FTMT_F2P_DEBUG(19) => '0',
FTMT_F2P_DEBUG(18) => '0',
FTMT_F2P_DEBUG(17) => '0',
FTMT_F2P_DEBUG(16) => '0',
FTMT_F2P_DEBUG(15) => '0',
FTMT_F2P_DEBUG(14) => '0',
FTMT_F2P_DEBUG(13) => '0',
FTMT_F2P_DEBUG(12) => '0',
FTMT_F2P_DEBUG(11) => '0',
FTMT_F2P_DEBUG(10) => '0',
FTMT_F2P_DEBUG(9) => '0',
FTMT_F2P_DEBUG(8) => '0',
FTMT_F2P_DEBUG(7) => '0',
FTMT_F2P_DEBUG(6) => '0',
FTMT_F2P_DEBUG(5) => '0',
FTMT_F2P_DEBUG(4) => '0',
FTMT_F2P_DEBUG(3) => '0',
FTMT_F2P_DEBUG(2) => '0',
FTMT_F2P_DEBUG(1) => '0',
FTMT_F2P_DEBUG(0) => '0',
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(47 downto 0) => GPIO_I(47 downto 0),
GPIO_O(47 downto 0) => GPIO_O(47 downto 0),
GPIO_T(47 downto 0) => GPIO_T(47 downto 0),
I2C0_SCL_I => I2C0_SCL_I,
I2C0_SCL_O => I2C0_SCL_O,
I2C0_SCL_T => I2C0_SCL_T,
I2C0_SDA_I => I2C0_SDA_I,
I2C0_SDA_O => I2C0_SDA_O,
I2C0_SDA_T => I2C0_SDA_T,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => '0',
M_AXI_GP0_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => NLW_inst_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_inst_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11) => '0',
M_AXI_GP0_BID(10) => '0',
M_AXI_GP0_BID(9) => '0',
M_AXI_GP0_BID(8) => '0',
M_AXI_GP0_BID(7) => '0',
M_AXI_GP0_BID(6) => '0',
M_AXI_GP0_BID(5) => '0',
M_AXI_GP0_BID(4) => '0',
M_AXI_GP0_BID(3) => '0',
M_AXI_GP0_BID(2) => '0',
M_AXI_GP0_BID(1) => '0',
M_AXI_GP0_BID(0) => '0',
M_AXI_GP0_BREADY => NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1) => '0',
M_AXI_GP0_BRESP(0) => '0',
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31) => '0',
M_AXI_GP0_RDATA(30) => '0',
M_AXI_GP0_RDATA(29) => '0',
M_AXI_GP0_RDATA(28) => '0',
M_AXI_GP0_RDATA(27) => '0',
M_AXI_GP0_RDATA(26) => '0',
M_AXI_GP0_RDATA(25) => '0',
M_AXI_GP0_RDATA(24) => '0',
M_AXI_GP0_RDATA(23) => '0',
M_AXI_GP0_RDATA(22) => '0',
M_AXI_GP0_RDATA(21) => '0',
M_AXI_GP0_RDATA(20) => '0',
M_AXI_GP0_RDATA(19) => '0',
M_AXI_GP0_RDATA(18) => '0',
M_AXI_GP0_RDATA(17) => '0',
M_AXI_GP0_RDATA(16) => '0',
M_AXI_GP0_RDATA(15) => '0',
M_AXI_GP0_RDATA(14) => '0',
M_AXI_GP0_RDATA(13) => '0',
M_AXI_GP0_RDATA(12) => '0',
M_AXI_GP0_RDATA(11) => '0',
M_AXI_GP0_RDATA(10) => '0',
M_AXI_GP0_RDATA(9) => '0',
M_AXI_GP0_RDATA(8) => '0',
M_AXI_GP0_RDATA(7) => '0',
M_AXI_GP0_RDATA(6) => '0',
M_AXI_GP0_RDATA(5) => '0',
M_AXI_GP0_RDATA(4) => '0',
M_AXI_GP0_RDATA(3) => '0',
M_AXI_GP0_RDATA(2) => '0',
M_AXI_GP0_RDATA(1) => '0',
M_AXI_GP0_RDATA(0) => '0',
M_AXI_GP0_RID(11) => '0',
M_AXI_GP0_RID(10) => '0',
M_AXI_GP0_RID(9) => '0',
M_AXI_GP0_RID(8) => '0',
M_AXI_GP0_RID(7) => '0',
M_AXI_GP0_RID(6) => '0',
M_AXI_GP0_RID(5) => '0',
M_AXI_GP0_RID(4) => '0',
M_AXI_GP0_RID(3) => '0',
M_AXI_GP0_RID(2) => '0',
M_AXI_GP0_RID(1) => '0',
M_AXI_GP0_RID(0) => '0',
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1) => '0',
M_AXI_GP0_RRESP(0) => '0',
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_inst_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED,
M_AXI_GP1_ACLK => M_AXI_GP1_ACLK,
M_AXI_GP1_ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
M_AXI_GP1_ARREADY => M_AXI_GP1_ARREADY,
M_AXI_GP1_ARSIZE(2 downto 0) => M_AXI_GP1_ARSIZE(2 downto 0),
M_AXI_GP1_ARVALID => M_AXI_GP1_ARVALID,
M_AXI_GP1_AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
M_AXI_GP1_AWREADY => M_AXI_GP1_AWREADY,
M_AXI_GP1_AWSIZE(2 downto 0) => M_AXI_GP1_AWSIZE(2 downto 0),
M_AXI_GP1_AWVALID => M_AXI_GP1_AWVALID,
M_AXI_GP1_BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
M_AXI_GP1_BREADY => M_AXI_GP1_BREADY,
M_AXI_GP1_BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
M_AXI_GP1_BVALID => M_AXI_GP1_BVALID,
M_AXI_GP1_RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
M_AXI_GP1_RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
M_AXI_GP1_RLAST => M_AXI_GP1_RLAST,
M_AXI_GP1_RREADY => M_AXI_GP1_RREADY,
M_AXI_GP1_RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
M_AXI_GP1_RVALID => M_AXI_GP1_RVALID,
M_AXI_GP1_WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
M_AXI_GP1_WLAST => M_AXI_GP1_WLAST,
M_AXI_GP1_WREADY => M_AXI_GP1_WREADY,
M_AXI_GP1_WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
M_AXI_GP1_WVALID => M_AXI_GP1_WVALID,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3) => '0',
SDIO0_DATA_I(2) => '0',
SDIO0_DATA_I(1) => '0',
SDIO0_DATA_I(0) => '0',
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3) => '0',
SDIO1_DATA_I(2) => '0',
SDIO1_DATA_I(1) => '0',
SDIO1_DATA_I(0) => '0',
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31) => '0',
S_AXI_ACP_ARADDR(30) => '0',
S_AXI_ACP_ARADDR(29) => '0',
S_AXI_ACP_ARADDR(28) => '0',
S_AXI_ACP_ARADDR(27) => '0',
S_AXI_ACP_ARADDR(26) => '0',
S_AXI_ACP_ARADDR(25) => '0',
S_AXI_ACP_ARADDR(24) => '0',
S_AXI_ACP_ARADDR(23) => '0',
S_AXI_ACP_ARADDR(22) => '0',
S_AXI_ACP_ARADDR(21) => '0',
S_AXI_ACP_ARADDR(20) => '0',
S_AXI_ACP_ARADDR(19) => '0',
S_AXI_ACP_ARADDR(18) => '0',
S_AXI_ACP_ARADDR(17) => '0',
S_AXI_ACP_ARADDR(16) => '0',
S_AXI_ACP_ARADDR(15) => '0',
S_AXI_ACP_ARADDR(14) => '0',
S_AXI_ACP_ARADDR(13) => '0',
S_AXI_ACP_ARADDR(12) => '0',
S_AXI_ACP_ARADDR(11) => '0',
S_AXI_ACP_ARADDR(10) => '0',
S_AXI_ACP_ARADDR(9) => '0',
S_AXI_ACP_ARADDR(8) => '0',
S_AXI_ACP_ARADDR(7) => '0',
S_AXI_ACP_ARADDR(6) => '0',
S_AXI_ACP_ARADDR(5) => '0',
S_AXI_ACP_ARADDR(4) => '0',
S_AXI_ACP_ARADDR(3) => '0',
S_AXI_ACP_ARADDR(2) => '0',
S_AXI_ACP_ARADDR(1) => '0',
S_AXI_ACP_ARADDR(0) => '0',
S_AXI_ACP_ARBURST(1) => '0',
S_AXI_ACP_ARBURST(0) => '0',
S_AXI_ACP_ARCACHE(3) => '0',
S_AXI_ACP_ARCACHE(2) => '0',
S_AXI_ACP_ARCACHE(1) => '0',
S_AXI_ACP_ARCACHE(0) => '0',
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2) => '0',
S_AXI_ACP_ARID(1) => '0',
S_AXI_ACP_ARID(0) => '0',
S_AXI_ACP_ARLEN(3) => '0',
S_AXI_ACP_ARLEN(2) => '0',
S_AXI_ACP_ARLEN(1) => '0',
S_AXI_ACP_ARLEN(0) => '0',
S_AXI_ACP_ARLOCK(1) => '0',
S_AXI_ACP_ARLOCK(0) => '0',
S_AXI_ACP_ARPROT(2) => '0',
S_AXI_ACP_ARPROT(1) => '0',
S_AXI_ACP_ARPROT(0) => '0',
S_AXI_ACP_ARQOS(3) => '0',
S_AXI_ACP_ARQOS(2) => '0',
S_AXI_ACP_ARQOS(1) => '0',
S_AXI_ACP_ARQOS(0) => '0',
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2) => '0',
S_AXI_ACP_ARSIZE(1) => '0',
S_AXI_ACP_ARSIZE(0) => '0',
S_AXI_ACP_ARUSER(4) => '0',
S_AXI_ACP_ARUSER(3) => '0',
S_AXI_ACP_ARUSER(2) => '0',
S_AXI_ACP_ARUSER(1) => '0',
S_AXI_ACP_ARUSER(0) => '0',
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31) => '0',
S_AXI_ACP_AWADDR(30) => '0',
S_AXI_ACP_AWADDR(29) => '0',
S_AXI_ACP_AWADDR(28) => '0',
S_AXI_ACP_AWADDR(27) => '0',
S_AXI_ACP_AWADDR(26) => '0',
S_AXI_ACP_AWADDR(25) => '0',
S_AXI_ACP_AWADDR(24) => '0',
S_AXI_ACP_AWADDR(23) => '0',
S_AXI_ACP_AWADDR(22) => '0',
S_AXI_ACP_AWADDR(21) => '0',
S_AXI_ACP_AWADDR(20) => '0',
S_AXI_ACP_AWADDR(19) => '0',
S_AXI_ACP_AWADDR(18) => '0',
S_AXI_ACP_AWADDR(17) => '0',
S_AXI_ACP_AWADDR(16) => '0',
S_AXI_ACP_AWADDR(15) => '0',
S_AXI_ACP_AWADDR(14) => '0',
S_AXI_ACP_AWADDR(13) => '0',
S_AXI_ACP_AWADDR(12) => '0',
S_AXI_ACP_AWADDR(11) => '0',
S_AXI_ACP_AWADDR(10) => '0',
S_AXI_ACP_AWADDR(9) => '0',
S_AXI_ACP_AWADDR(8) => '0',
S_AXI_ACP_AWADDR(7) => '0',
S_AXI_ACP_AWADDR(6) => '0',
S_AXI_ACP_AWADDR(5) => '0',
S_AXI_ACP_AWADDR(4) => '0',
S_AXI_ACP_AWADDR(3) => '0',
S_AXI_ACP_AWADDR(2) => '0',
S_AXI_ACP_AWADDR(1) => '0',
S_AXI_ACP_AWADDR(0) => '0',
S_AXI_ACP_AWBURST(1) => '0',
S_AXI_ACP_AWBURST(0) => '0',
S_AXI_ACP_AWCACHE(3) => '0',
S_AXI_ACP_AWCACHE(2) => '0',
S_AXI_ACP_AWCACHE(1) => '0',
S_AXI_ACP_AWCACHE(0) => '0',
S_AXI_ACP_AWID(2) => '0',
S_AXI_ACP_AWID(1) => '0',
S_AXI_ACP_AWID(0) => '0',
S_AXI_ACP_AWLEN(3) => '0',
S_AXI_ACP_AWLEN(2) => '0',
S_AXI_ACP_AWLEN(1) => '0',
S_AXI_ACP_AWLEN(0) => '0',
S_AXI_ACP_AWLOCK(1) => '0',
S_AXI_ACP_AWLOCK(0) => '0',
S_AXI_ACP_AWPROT(2) => '0',
S_AXI_ACP_AWPROT(1) => '0',
S_AXI_ACP_AWPROT(0) => '0',
S_AXI_ACP_AWQOS(3) => '0',
S_AXI_ACP_AWQOS(2) => '0',
S_AXI_ACP_AWQOS(1) => '0',
S_AXI_ACP_AWQOS(0) => '0',
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2) => '0',
S_AXI_ACP_AWSIZE(1) => '0',
S_AXI_ACP_AWSIZE(0) => '0',
S_AXI_ACP_AWUSER(4) => '0',
S_AXI_ACP_AWUSER(3) => '0',
S_AXI_ACP_AWUSER(2) => '0',
S_AXI_ACP_AWUSER(1) => '0',
S_AXI_ACP_AWUSER(0) => '0',
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63) => '0',
S_AXI_ACP_WDATA(62) => '0',
S_AXI_ACP_WDATA(61) => '0',
S_AXI_ACP_WDATA(60) => '0',
S_AXI_ACP_WDATA(59) => '0',
S_AXI_ACP_WDATA(58) => '0',
S_AXI_ACP_WDATA(57) => '0',
S_AXI_ACP_WDATA(56) => '0',
S_AXI_ACP_WDATA(55) => '0',
S_AXI_ACP_WDATA(54) => '0',
S_AXI_ACP_WDATA(53) => '0',
S_AXI_ACP_WDATA(52) => '0',
S_AXI_ACP_WDATA(51) => '0',
S_AXI_ACP_WDATA(50) => '0',
S_AXI_ACP_WDATA(49) => '0',
S_AXI_ACP_WDATA(48) => '0',
S_AXI_ACP_WDATA(47) => '0',
S_AXI_ACP_WDATA(46) => '0',
S_AXI_ACP_WDATA(45) => '0',
S_AXI_ACP_WDATA(44) => '0',
S_AXI_ACP_WDATA(43) => '0',
S_AXI_ACP_WDATA(42) => '0',
S_AXI_ACP_WDATA(41) => '0',
S_AXI_ACP_WDATA(40) => '0',
S_AXI_ACP_WDATA(39) => '0',
S_AXI_ACP_WDATA(38) => '0',
S_AXI_ACP_WDATA(37) => '0',
S_AXI_ACP_WDATA(36) => '0',
S_AXI_ACP_WDATA(35) => '0',
S_AXI_ACP_WDATA(34) => '0',
S_AXI_ACP_WDATA(33) => '0',
S_AXI_ACP_WDATA(32) => '0',
S_AXI_ACP_WDATA(31) => '0',
S_AXI_ACP_WDATA(30) => '0',
S_AXI_ACP_WDATA(29) => '0',
S_AXI_ACP_WDATA(28) => '0',
S_AXI_ACP_WDATA(27) => '0',
S_AXI_ACP_WDATA(26) => '0',
S_AXI_ACP_WDATA(25) => '0',
S_AXI_ACP_WDATA(24) => '0',
S_AXI_ACP_WDATA(23) => '0',
S_AXI_ACP_WDATA(22) => '0',
S_AXI_ACP_WDATA(21) => '0',
S_AXI_ACP_WDATA(20) => '0',
S_AXI_ACP_WDATA(19) => '0',
S_AXI_ACP_WDATA(18) => '0',
S_AXI_ACP_WDATA(17) => '0',
S_AXI_ACP_WDATA(16) => '0',
S_AXI_ACP_WDATA(15) => '0',
S_AXI_ACP_WDATA(14) => '0',
S_AXI_ACP_WDATA(13) => '0',
S_AXI_ACP_WDATA(12) => '0',
S_AXI_ACP_WDATA(11) => '0',
S_AXI_ACP_WDATA(10) => '0',
S_AXI_ACP_WDATA(9) => '0',
S_AXI_ACP_WDATA(8) => '0',
S_AXI_ACP_WDATA(7) => '0',
S_AXI_ACP_WDATA(6) => '0',
S_AXI_ACP_WDATA(5) => '0',
S_AXI_ACP_WDATA(4) => '0',
S_AXI_ACP_WDATA(3) => '0',
S_AXI_ACP_WDATA(2) => '0',
S_AXI_ACP_WDATA(1) => '0',
S_AXI_ACP_WDATA(0) => '0',
S_AXI_ACP_WID(2) => '0',
S_AXI_ACP_WID(1) => '0',
S_AXI_ACP_WID(0) => '0',
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7) => '0',
S_AXI_ACP_WSTRB(6) => '0',
S_AXI_ACP_WSTRB(5) => '0',
S_AXI_ACP_WSTRB(4) => '0',
S_AXI_ACP_WSTRB(3) => '0',
S_AXI_ACP_WSTRB(2) => '0',
S_AXI_ACP_WSTRB(1) => '0',
S_AXI_ACP_WSTRB(0) => '0',
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31) => '0',
S_AXI_GP0_ARADDR(30) => '0',
S_AXI_GP0_ARADDR(29) => '0',
S_AXI_GP0_ARADDR(28) => '0',
S_AXI_GP0_ARADDR(27) => '0',
S_AXI_GP0_ARADDR(26) => '0',
S_AXI_GP0_ARADDR(25) => '0',
S_AXI_GP0_ARADDR(24) => '0',
S_AXI_GP0_ARADDR(23) => '0',
S_AXI_GP0_ARADDR(22) => '0',
S_AXI_GP0_ARADDR(21) => '0',
S_AXI_GP0_ARADDR(20) => '0',
S_AXI_GP0_ARADDR(19) => '0',
S_AXI_GP0_ARADDR(18) => '0',
S_AXI_GP0_ARADDR(17) => '0',
S_AXI_GP0_ARADDR(16) => '0',
S_AXI_GP0_ARADDR(15) => '0',
S_AXI_GP0_ARADDR(14) => '0',
S_AXI_GP0_ARADDR(13) => '0',
S_AXI_GP0_ARADDR(12) => '0',
S_AXI_GP0_ARADDR(11) => '0',
S_AXI_GP0_ARADDR(10) => '0',
S_AXI_GP0_ARADDR(9) => '0',
S_AXI_GP0_ARADDR(8) => '0',
S_AXI_GP0_ARADDR(7) => '0',
S_AXI_GP0_ARADDR(6) => '0',
S_AXI_GP0_ARADDR(5) => '0',
S_AXI_GP0_ARADDR(4) => '0',
S_AXI_GP0_ARADDR(3) => '0',
S_AXI_GP0_ARADDR(2) => '0',
S_AXI_GP0_ARADDR(1) => '0',
S_AXI_GP0_ARADDR(0) => '0',
S_AXI_GP0_ARBURST(1) => '0',
S_AXI_GP0_ARBURST(0) => '0',
S_AXI_GP0_ARCACHE(3) => '0',
S_AXI_GP0_ARCACHE(2) => '0',
S_AXI_GP0_ARCACHE(1) => '0',
S_AXI_GP0_ARCACHE(0) => '0',
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5) => '0',
S_AXI_GP0_ARID(4) => '0',
S_AXI_GP0_ARID(3) => '0',
S_AXI_GP0_ARID(2) => '0',
S_AXI_GP0_ARID(1) => '0',
S_AXI_GP0_ARID(0) => '0',
S_AXI_GP0_ARLEN(3) => '0',
S_AXI_GP0_ARLEN(2) => '0',
S_AXI_GP0_ARLEN(1) => '0',
S_AXI_GP0_ARLEN(0) => '0',
S_AXI_GP0_ARLOCK(1) => '0',
S_AXI_GP0_ARLOCK(0) => '0',
S_AXI_GP0_ARPROT(2) => '0',
S_AXI_GP0_ARPROT(1) => '0',
S_AXI_GP0_ARPROT(0) => '0',
S_AXI_GP0_ARQOS(3) => '0',
S_AXI_GP0_ARQOS(2) => '0',
S_AXI_GP0_ARQOS(1) => '0',
S_AXI_GP0_ARQOS(0) => '0',
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2) => '0',
S_AXI_GP0_ARSIZE(1) => '0',
S_AXI_GP0_ARSIZE(0) => '0',
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31) => '0',
S_AXI_GP0_AWADDR(30) => '0',
S_AXI_GP0_AWADDR(29) => '0',
S_AXI_GP0_AWADDR(28) => '0',
S_AXI_GP0_AWADDR(27) => '0',
S_AXI_GP0_AWADDR(26) => '0',
S_AXI_GP0_AWADDR(25) => '0',
S_AXI_GP0_AWADDR(24) => '0',
S_AXI_GP0_AWADDR(23) => '0',
S_AXI_GP0_AWADDR(22) => '0',
S_AXI_GP0_AWADDR(21) => '0',
S_AXI_GP0_AWADDR(20) => '0',
S_AXI_GP0_AWADDR(19) => '0',
S_AXI_GP0_AWADDR(18) => '0',
S_AXI_GP0_AWADDR(17) => '0',
S_AXI_GP0_AWADDR(16) => '0',
S_AXI_GP0_AWADDR(15) => '0',
S_AXI_GP0_AWADDR(14) => '0',
S_AXI_GP0_AWADDR(13) => '0',
S_AXI_GP0_AWADDR(12) => '0',
S_AXI_GP0_AWADDR(11) => '0',
S_AXI_GP0_AWADDR(10) => '0',
S_AXI_GP0_AWADDR(9) => '0',
S_AXI_GP0_AWADDR(8) => '0',
S_AXI_GP0_AWADDR(7) => '0',
S_AXI_GP0_AWADDR(6) => '0',
S_AXI_GP0_AWADDR(5) => '0',
S_AXI_GP0_AWADDR(4) => '0',
S_AXI_GP0_AWADDR(3) => '0',
S_AXI_GP0_AWADDR(2) => '0',
S_AXI_GP0_AWADDR(1) => '0',
S_AXI_GP0_AWADDR(0) => '0',
S_AXI_GP0_AWBURST(1) => '0',
S_AXI_GP0_AWBURST(0) => '0',
S_AXI_GP0_AWCACHE(3) => '0',
S_AXI_GP0_AWCACHE(2) => '0',
S_AXI_GP0_AWCACHE(1) => '0',
S_AXI_GP0_AWCACHE(0) => '0',
S_AXI_GP0_AWID(5) => '0',
S_AXI_GP0_AWID(4) => '0',
S_AXI_GP0_AWID(3) => '0',
S_AXI_GP0_AWID(2) => '0',
S_AXI_GP0_AWID(1) => '0',
S_AXI_GP0_AWID(0) => '0',
S_AXI_GP0_AWLEN(3) => '0',
S_AXI_GP0_AWLEN(2) => '0',
S_AXI_GP0_AWLEN(1) => '0',
S_AXI_GP0_AWLEN(0) => '0',
S_AXI_GP0_AWLOCK(1) => '0',
S_AXI_GP0_AWLOCK(0) => '0',
S_AXI_GP0_AWPROT(2) => '0',
S_AXI_GP0_AWPROT(1) => '0',
S_AXI_GP0_AWPROT(0) => '0',
S_AXI_GP0_AWQOS(3) => '0',
S_AXI_GP0_AWQOS(2) => '0',
S_AXI_GP0_AWQOS(1) => '0',
S_AXI_GP0_AWQOS(0) => '0',
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2) => '0',
S_AXI_GP0_AWSIZE(1) => '0',
S_AXI_GP0_AWSIZE(0) => '0',
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31) => '0',
S_AXI_GP0_WDATA(30) => '0',
S_AXI_GP0_WDATA(29) => '0',
S_AXI_GP0_WDATA(28) => '0',
S_AXI_GP0_WDATA(27) => '0',
S_AXI_GP0_WDATA(26) => '0',
S_AXI_GP0_WDATA(25) => '0',
S_AXI_GP0_WDATA(24) => '0',
S_AXI_GP0_WDATA(23) => '0',
S_AXI_GP0_WDATA(22) => '0',
S_AXI_GP0_WDATA(21) => '0',
S_AXI_GP0_WDATA(20) => '0',
S_AXI_GP0_WDATA(19) => '0',
S_AXI_GP0_WDATA(18) => '0',
S_AXI_GP0_WDATA(17) => '0',
S_AXI_GP0_WDATA(16) => '0',
S_AXI_GP0_WDATA(15) => '0',
S_AXI_GP0_WDATA(14) => '0',
S_AXI_GP0_WDATA(13) => '0',
S_AXI_GP0_WDATA(12) => '0',
S_AXI_GP0_WDATA(11) => '0',
S_AXI_GP0_WDATA(10) => '0',
S_AXI_GP0_WDATA(9) => '0',
S_AXI_GP0_WDATA(8) => '0',
S_AXI_GP0_WDATA(7) => '0',
S_AXI_GP0_WDATA(6) => '0',
S_AXI_GP0_WDATA(5) => '0',
S_AXI_GP0_WDATA(4) => '0',
S_AXI_GP0_WDATA(3) => '0',
S_AXI_GP0_WDATA(2) => '0',
S_AXI_GP0_WDATA(1) => '0',
S_AXI_GP0_WDATA(0) => '0',
S_AXI_GP0_WID(5) => '0',
S_AXI_GP0_WID(4) => '0',
S_AXI_GP0_WID(3) => '0',
S_AXI_GP0_WID(2) => '0',
S_AXI_GP0_WID(1) => '0',
S_AXI_GP0_WID(0) => '0',
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3) => '0',
S_AXI_GP0_WSTRB(2) => '0',
S_AXI_GP0_WSTRB(1) => '0',
S_AXI_GP0_WSTRB(0) => '0',
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31) => '0',
S_AXI_GP1_ARADDR(30) => '0',
S_AXI_GP1_ARADDR(29) => '0',
S_AXI_GP1_ARADDR(28) => '0',
S_AXI_GP1_ARADDR(27) => '0',
S_AXI_GP1_ARADDR(26) => '0',
S_AXI_GP1_ARADDR(25) => '0',
S_AXI_GP1_ARADDR(24) => '0',
S_AXI_GP1_ARADDR(23) => '0',
S_AXI_GP1_ARADDR(22) => '0',
S_AXI_GP1_ARADDR(21) => '0',
S_AXI_GP1_ARADDR(20) => '0',
S_AXI_GP1_ARADDR(19) => '0',
S_AXI_GP1_ARADDR(18) => '0',
S_AXI_GP1_ARADDR(17) => '0',
S_AXI_GP1_ARADDR(16) => '0',
S_AXI_GP1_ARADDR(15) => '0',
S_AXI_GP1_ARADDR(14) => '0',
S_AXI_GP1_ARADDR(13) => '0',
S_AXI_GP1_ARADDR(12) => '0',
S_AXI_GP1_ARADDR(11) => '0',
S_AXI_GP1_ARADDR(10) => '0',
S_AXI_GP1_ARADDR(9) => '0',
S_AXI_GP1_ARADDR(8) => '0',
S_AXI_GP1_ARADDR(7) => '0',
S_AXI_GP1_ARADDR(6) => '0',
S_AXI_GP1_ARADDR(5) => '0',
S_AXI_GP1_ARADDR(4) => '0',
S_AXI_GP1_ARADDR(3) => '0',
S_AXI_GP1_ARADDR(2) => '0',
S_AXI_GP1_ARADDR(1) => '0',
S_AXI_GP1_ARADDR(0) => '0',
S_AXI_GP1_ARBURST(1) => '0',
S_AXI_GP1_ARBURST(0) => '0',
S_AXI_GP1_ARCACHE(3) => '0',
S_AXI_GP1_ARCACHE(2) => '0',
S_AXI_GP1_ARCACHE(1) => '0',
S_AXI_GP1_ARCACHE(0) => '0',
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5) => '0',
S_AXI_GP1_ARID(4) => '0',
S_AXI_GP1_ARID(3) => '0',
S_AXI_GP1_ARID(2) => '0',
S_AXI_GP1_ARID(1) => '0',
S_AXI_GP1_ARID(0) => '0',
S_AXI_GP1_ARLEN(3) => '0',
S_AXI_GP1_ARLEN(2) => '0',
S_AXI_GP1_ARLEN(1) => '0',
S_AXI_GP1_ARLEN(0) => '0',
S_AXI_GP1_ARLOCK(1) => '0',
S_AXI_GP1_ARLOCK(0) => '0',
S_AXI_GP1_ARPROT(2) => '0',
S_AXI_GP1_ARPROT(1) => '0',
S_AXI_GP1_ARPROT(0) => '0',
S_AXI_GP1_ARQOS(3) => '0',
S_AXI_GP1_ARQOS(2) => '0',
S_AXI_GP1_ARQOS(1) => '0',
S_AXI_GP1_ARQOS(0) => '0',
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2) => '0',
S_AXI_GP1_ARSIZE(1) => '0',
S_AXI_GP1_ARSIZE(0) => '0',
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31) => '0',
S_AXI_GP1_AWADDR(30) => '0',
S_AXI_GP1_AWADDR(29) => '0',
S_AXI_GP1_AWADDR(28) => '0',
S_AXI_GP1_AWADDR(27) => '0',
S_AXI_GP1_AWADDR(26) => '0',
S_AXI_GP1_AWADDR(25) => '0',
S_AXI_GP1_AWADDR(24) => '0',
S_AXI_GP1_AWADDR(23) => '0',
S_AXI_GP1_AWADDR(22) => '0',
S_AXI_GP1_AWADDR(21) => '0',
S_AXI_GP1_AWADDR(20) => '0',
S_AXI_GP1_AWADDR(19) => '0',
S_AXI_GP1_AWADDR(18) => '0',
S_AXI_GP1_AWADDR(17) => '0',
S_AXI_GP1_AWADDR(16) => '0',
S_AXI_GP1_AWADDR(15) => '0',
S_AXI_GP1_AWADDR(14) => '0',
S_AXI_GP1_AWADDR(13) => '0',
S_AXI_GP1_AWADDR(12) => '0',
S_AXI_GP1_AWADDR(11) => '0',
S_AXI_GP1_AWADDR(10) => '0',
S_AXI_GP1_AWADDR(9) => '0',
S_AXI_GP1_AWADDR(8) => '0',
S_AXI_GP1_AWADDR(7) => '0',
S_AXI_GP1_AWADDR(6) => '0',
S_AXI_GP1_AWADDR(5) => '0',
S_AXI_GP1_AWADDR(4) => '0',
S_AXI_GP1_AWADDR(3) => '0',
S_AXI_GP1_AWADDR(2) => '0',
S_AXI_GP1_AWADDR(1) => '0',
S_AXI_GP1_AWADDR(0) => '0',
S_AXI_GP1_AWBURST(1) => '0',
S_AXI_GP1_AWBURST(0) => '0',
S_AXI_GP1_AWCACHE(3) => '0',
S_AXI_GP1_AWCACHE(2) => '0',
S_AXI_GP1_AWCACHE(1) => '0',
S_AXI_GP1_AWCACHE(0) => '0',
S_AXI_GP1_AWID(5) => '0',
S_AXI_GP1_AWID(4) => '0',
S_AXI_GP1_AWID(3) => '0',
S_AXI_GP1_AWID(2) => '0',
S_AXI_GP1_AWID(1) => '0',
S_AXI_GP1_AWID(0) => '0',
S_AXI_GP1_AWLEN(3) => '0',
S_AXI_GP1_AWLEN(2) => '0',
S_AXI_GP1_AWLEN(1) => '0',
S_AXI_GP1_AWLEN(0) => '0',
S_AXI_GP1_AWLOCK(1) => '0',
S_AXI_GP1_AWLOCK(0) => '0',
S_AXI_GP1_AWPROT(2) => '0',
S_AXI_GP1_AWPROT(1) => '0',
S_AXI_GP1_AWPROT(0) => '0',
S_AXI_GP1_AWQOS(3) => '0',
S_AXI_GP1_AWQOS(2) => '0',
S_AXI_GP1_AWQOS(1) => '0',
S_AXI_GP1_AWQOS(0) => '0',
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2) => '0',
S_AXI_GP1_AWSIZE(1) => '0',
S_AXI_GP1_AWSIZE(0) => '0',
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31) => '0',
S_AXI_GP1_WDATA(30) => '0',
S_AXI_GP1_WDATA(29) => '0',
S_AXI_GP1_WDATA(28) => '0',
S_AXI_GP1_WDATA(27) => '0',
S_AXI_GP1_WDATA(26) => '0',
S_AXI_GP1_WDATA(25) => '0',
S_AXI_GP1_WDATA(24) => '0',
S_AXI_GP1_WDATA(23) => '0',
S_AXI_GP1_WDATA(22) => '0',
S_AXI_GP1_WDATA(21) => '0',
S_AXI_GP1_WDATA(20) => '0',
S_AXI_GP1_WDATA(19) => '0',
S_AXI_GP1_WDATA(18) => '0',
S_AXI_GP1_WDATA(17) => '0',
S_AXI_GP1_WDATA(16) => '0',
S_AXI_GP1_WDATA(15) => '0',
S_AXI_GP1_WDATA(14) => '0',
S_AXI_GP1_WDATA(13) => '0',
S_AXI_GP1_WDATA(12) => '0',
S_AXI_GP1_WDATA(11) => '0',
S_AXI_GP1_WDATA(10) => '0',
S_AXI_GP1_WDATA(9) => '0',
S_AXI_GP1_WDATA(8) => '0',
S_AXI_GP1_WDATA(7) => '0',
S_AXI_GP1_WDATA(6) => '0',
S_AXI_GP1_WDATA(5) => '0',
S_AXI_GP1_WDATA(4) => '0',
S_AXI_GP1_WDATA(3) => '0',
S_AXI_GP1_WDATA(2) => '0',
S_AXI_GP1_WDATA(1) => '0',
S_AXI_GP1_WDATA(0) => '0',
S_AXI_GP1_WID(5) => '0',
S_AXI_GP1_WID(4) => '0',
S_AXI_GP1_WID(3) => '0',
S_AXI_GP1_WID(2) => '0',
S_AXI_GP1_WID(1) => '0',
S_AXI_GP1_WID(0) => '0',
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3) => '0',
S_AXI_GP1_WSTRB(2) => '0',
S_AXI_GP1_WSTRB(1) => '0',
S_AXI_GP1_WSTRB(0) => '0',
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31) => '0',
S_AXI_HP0_ARADDR(30) => '0',
S_AXI_HP0_ARADDR(29) => '0',
S_AXI_HP0_ARADDR(28) => '0',
S_AXI_HP0_ARADDR(27) => '0',
S_AXI_HP0_ARADDR(26) => '0',
S_AXI_HP0_ARADDR(25) => '0',
S_AXI_HP0_ARADDR(24) => '0',
S_AXI_HP0_ARADDR(23) => '0',
S_AXI_HP0_ARADDR(22) => '0',
S_AXI_HP0_ARADDR(21) => '0',
S_AXI_HP0_ARADDR(20) => '0',
S_AXI_HP0_ARADDR(19) => '0',
S_AXI_HP0_ARADDR(18) => '0',
S_AXI_HP0_ARADDR(17) => '0',
S_AXI_HP0_ARADDR(16) => '0',
S_AXI_HP0_ARADDR(15) => '0',
S_AXI_HP0_ARADDR(14) => '0',
S_AXI_HP0_ARADDR(13) => '0',
S_AXI_HP0_ARADDR(12) => '0',
S_AXI_HP0_ARADDR(11) => '0',
S_AXI_HP0_ARADDR(10) => '0',
S_AXI_HP0_ARADDR(9) => '0',
S_AXI_HP0_ARADDR(8) => '0',
S_AXI_HP0_ARADDR(7) => '0',
S_AXI_HP0_ARADDR(6) => '0',
S_AXI_HP0_ARADDR(5) => '0',
S_AXI_HP0_ARADDR(4) => '0',
S_AXI_HP0_ARADDR(3) => '0',
S_AXI_HP0_ARADDR(2) => '0',
S_AXI_HP0_ARADDR(1) => '0',
S_AXI_HP0_ARADDR(0) => '0',
S_AXI_HP0_ARBURST(1) => '0',
S_AXI_HP0_ARBURST(0) => '0',
S_AXI_HP0_ARCACHE(3) => '0',
S_AXI_HP0_ARCACHE(2) => '0',
S_AXI_HP0_ARCACHE(1) => '0',
S_AXI_HP0_ARCACHE(0) => '0',
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5) => '0',
S_AXI_HP0_ARID(4) => '0',
S_AXI_HP0_ARID(3) => '0',
S_AXI_HP0_ARID(2) => '0',
S_AXI_HP0_ARID(1) => '0',
S_AXI_HP0_ARID(0) => '0',
S_AXI_HP0_ARLEN(3) => '0',
S_AXI_HP0_ARLEN(2) => '0',
S_AXI_HP0_ARLEN(1) => '0',
S_AXI_HP0_ARLEN(0) => '0',
S_AXI_HP0_ARLOCK(1) => '0',
S_AXI_HP0_ARLOCK(0) => '0',
S_AXI_HP0_ARPROT(2) => '0',
S_AXI_HP0_ARPROT(1) => '0',
S_AXI_HP0_ARPROT(0) => '0',
S_AXI_HP0_ARQOS(3) => '0',
S_AXI_HP0_ARQOS(2) => '0',
S_AXI_HP0_ARQOS(1) => '0',
S_AXI_HP0_ARQOS(0) => '0',
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2) => '0',
S_AXI_HP0_ARSIZE(1) => '0',
S_AXI_HP0_ARSIZE(0) => '0',
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31) => '0',
S_AXI_HP0_AWADDR(30) => '0',
S_AXI_HP0_AWADDR(29) => '0',
S_AXI_HP0_AWADDR(28) => '0',
S_AXI_HP0_AWADDR(27) => '0',
S_AXI_HP0_AWADDR(26) => '0',
S_AXI_HP0_AWADDR(25) => '0',
S_AXI_HP0_AWADDR(24) => '0',
S_AXI_HP0_AWADDR(23) => '0',
S_AXI_HP0_AWADDR(22) => '0',
S_AXI_HP0_AWADDR(21) => '0',
S_AXI_HP0_AWADDR(20) => '0',
S_AXI_HP0_AWADDR(19) => '0',
S_AXI_HP0_AWADDR(18) => '0',
S_AXI_HP0_AWADDR(17) => '0',
S_AXI_HP0_AWADDR(16) => '0',
S_AXI_HP0_AWADDR(15) => '0',
S_AXI_HP0_AWADDR(14) => '0',
S_AXI_HP0_AWADDR(13) => '0',
S_AXI_HP0_AWADDR(12) => '0',
S_AXI_HP0_AWADDR(11) => '0',
S_AXI_HP0_AWADDR(10) => '0',
S_AXI_HP0_AWADDR(9) => '0',
S_AXI_HP0_AWADDR(8) => '0',
S_AXI_HP0_AWADDR(7) => '0',
S_AXI_HP0_AWADDR(6) => '0',
S_AXI_HP0_AWADDR(5) => '0',
S_AXI_HP0_AWADDR(4) => '0',
S_AXI_HP0_AWADDR(3) => '0',
S_AXI_HP0_AWADDR(2) => '0',
S_AXI_HP0_AWADDR(1) => '0',
S_AXI_HP0_AWADDR(0) => '0',
S_AXI_HP0_AWBURST(1) => '0',
S_AXI_HP0_AWBURST(0) => '0',
S_AXI_HP0_AWCACHE(3) => '0',
S_AXI_HP0_AWCACHE(2) => '0',
S_AXI_HP0_AWCACHE(1) => '0',
S_AXI_HP0_AWCACHE(0) => '0',
S_AXI_HP0_AWID(5) => '0',
S_AXI_HP0_AWID(4) => '0',
S_AXI_HP0_AWID(3) => '0',
S_AXI_HP0_AWID(2) => '0',
S_AXI_HP0_AWID(1) => '0',
S_AXI_HP0_AWID(0) => '0',
S_AXI_HP0_AWLEN(3) => '0',
S_AXI_HP0_AWLEN(2) => '0',
S_AXI_HP0_AWLEN(1) => '0',
S_AXI_HP0_AWLEN(0) => '0',
S_AXI_HP0_AWLOCK(1) => '0',
S_AXI_HP0_AWLOCK(0) => '0',
S_AXI_HP0_AWPROT(2) => '0',
S_AXI_HP0_AWPROT(1) => '0',
S_AXI_HP0_AWPROT(0) => '0',
S_AXI_HP0_AWQOS(3) => '0',
S_AXI_HP0_AWQOS(2) => '0',
S_AXI_HP0_AWQOS(1) => '0',
S_AXI_HP0_AWQOS(0) => '0',
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2) => '0',
S_AXI_HP0_AWSIZE(1) => '0',
S_AXI_HP0_AWSIZE(0) => '0',
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31) => '0',
S_AXI_HP0_WDATA(30) => '0',
S_AXI_HP0_WDATA(29) => '0',
S_AXI_HP0_WDATA(28) => '0',
S_AXI_HP0_WDATA(27) => '0',
S_AXI_HP0_WDATA(26) => '0',
S_AXI_HP0_WDATA(25) => '0',
S_AXI_HP0_WDATA(24) => '0',
S_AXI_HP0_WDATA(23) => '0',
S_AXI_HP0_WDATA(22) => '0',
S_AXI_HP0_WDATA(21) => '0',
S_AXI_HP0_WDATA(20) => '0',
S_AXI_HP0_WDATA(19) => '0',
S_AXI_HP0_WDATA(18) => '0',
S_AXI_HP0_WDATA(17) => '0',
S_AXI_HP0_WDATA(16) => '0',
S_AXI_HP0_WDATA(15) => '0',
S_AXI_HP0_WDATA(14) => '0',
S_AXI_HP0_WDATA(13) => '0',
S_AXI_HP0_WDATA(12) => '0',
S_AXI_HP0_WDATA(11) => '0',
S_AXI_HP0_WDATA(10) => '0',
S_AXI_HP0_WDATA(9) => '0',
S_AXI_HP0_WDATA(8) => '0',
S_AXI_HP0_WDATA(7) => '0',
S_AXI_HP0_WDATA(6) => '0',
S_AXI_HP0_WDATA(5) => '0',
S_AXI_HP0_WDATA(4) => '0',
S_AXI_HP0_WDATA(3) => '0',
S_AXI_HP0_WDATA(2) => '0',
S_AXI_HP0_WDATA(1) => '0',
S_AXI_HP0_WDATA(0) => '0',
S_AXI_HP0_WID(5) => '0',
S_AXI_HP0_WID(4) => '0',
S_AXI_HP0_WID(3) => '0',
S_AXI_HP0_WID(2) => '0',
S_AXI_HP0_WID(1) => '0',
S_AXI_HP0_WID(0) => '0',
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3) => '0',
S_AXI_HP0_WSTRB(2) => '0',
S_AXI_HP0_WSTRB(1) => '0',
S_AXI_HP0_WSTRB(0) => '0',
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => S_AXI_HP1_ACLK,
S_AXI_HP1_ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
S_AXI_HP1_ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
S_AXI_HP1_ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
S_AXI_HP1_ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
S_AXI_HP1_ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
S_AXI_HP1_ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
S_AXI_HP1_ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
S_AXI_HP1_ARREADY => S_AXI_HP1_ARREADY,
S_AXI_HP1_ARSIZE(2 downto 0) => S_AXI_HP1_ARSIZE(2 downto 0),
S_AXI_HP1_ARVALID => S_AXI_HP1_ARVALID,
S_AXI_HP1_AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
S_AXI_HP1_AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
S_AXI_HP1_AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
S_AXI_HP1_AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
S_AXI_HP1_AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
S_AXI_HP1_AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
S_AXI_HP1_AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
S_AXI_HP1_AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
S_AXI_HP1_AWREADY => S_AXI_HP1_AWREADY,
S_AXI_HP1_AWSIZE(2 downto 0) => S_AXI_HP1_AWSIZE(2 downto 0),
S_AXI_HP1_AWVALID => S_AXI_HP1_AWVALID,
S_AXI_HP1_BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
S_AXI_HP1_BREADY => S_AXI_HP1_BREADY,
S_AXI_HP1_BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
S_AXI_HP1_BVALID => S_AXI_HP1_BVALID,
S_AXI_HP1_RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
S_AXI_HP1_RLAST => S_AXI_HP1_RLAST,
S_AXI_HP1_RREADY => S_AXI_HP1_RREADY,
S_AXI_HP1_RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
S_AXI_HP1_RVALID => S_AXI_HP1_RVALID,
S_AXI_HP1_WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
S_AXI_HP1_WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
S_AXI_HP1_WLAST => S_AXI_HP1_WLAST,
S_AXI_HP1_WREADY => S_AXI_HP1_WREADY,
S_AXI_HP1_WRISSUECAP1_EN => S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
S_AXI_HP1_WVALID => S_AXI_HP1_WVALID,
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31) => '0',
S_AXI_HP2_ARADDR(30) => '0',
S_AXI_HP2_ARADDR(29) => '0',
S_AXI_HP2_ARADDR(28) => '0',
S_AXI_HP2_ARADDR(27) => '0',
S_AXI_HP2_ARADDR(26) => '0',
S_AXI_HP2_ARADDR(25) => '0',
S_AXI_HP2_ARADDR(24) => '0',
S_AXI_HP2_ARADDR(23) => '0',
S_AXI_HP2_ARADDR(22) => '0',
S_AXI_HP2_ARADDR(21) => '0',
S_AXI_HP2_ARADDR(20) => '0',
S_AXI_HP2_ARADDR(19) => '0',
S_AXI_HP2_ARADDR(18) => '0',
S_AXI_HP2_ARADDR(17) => '0',
S_AXI_HP2_ARADDR(16) => '0',
S_AXI_HP2_ARADDR(15) => '0',
S_AXI_HP2_ARADDR(14) => '0',
S_AXI_HP2_ARADDR(13) => '0',
S_AXI_HP2_ARADDR(12) => '0',
S_AXI_HP2_ARADDR(11) => '0',
S_AXI_HP2_ARADDR(10) => '0',
S_AXI_HP2_ARADDR(9) => '0',
S_AXI_HP2_ARADDR(8) => '0',
S_AXI_HP2_ARADDR(7) => '0',
S_AXI_HP2_ARADDR(6) => '0',
S_AXI_HP2_ARADDR(5) => '0',
S_AXI_HP2_ARADDR(4) => '0',
S_AXI_HP2_ARADDR(3) => '0',
S_AXI_HP2_ARADDR(2) => '0',
S_AXI_HP2_ARADDR(1) => '0',
S_AXI_HP2_ARADDR(0) => '0',
S_AXI_HP2_ARBURST(1) => '0',
S_AXI_HP2_ARBURST(0) => '0',
S_AXI_HP2_ARCACHE(3) => '0',
S_AXI_HP2_ARCACHE(2) => '0',
S_AXI_HP2_ARCACHE(1) => '0',
S_AXI_HP2_ARCACHE(0) => '0',
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5) => '0',
S_AXI_HP2_ARID(4) => '0',
S_AXI_HP2_ARID(3) => '0',
S_AXI_HP2_ARID(2) => '0',
S_AXI_HP2_ARID(1) => '0',
S_AXI_HP2_ARID(0) => '0',
S_AXI_HP2_ARLEN(3) => '0',
S_AXI_HP2_ARLEN(2) => '0',
S_AXI_HP2_ARLEN(1) => '0',
S_AXI_HP2_ARLEN(0) => '0',
S_AXI_HP2_ARLOCK(1) => '0',
S_AXI_HP2_ARLOCK(0) => '0',
S_AXI_HP2_ARPROT(2) => '0',
S_AXI_HP2_ARPROT(1) => '0',
S_AXI_HP2_ARPROT(0) => '0',
S_AXI_HP2_ARQOS(3) => '0',
S_AXI_HP2_ARQOS(2) => '0',
S_AXI_HP2_ARQOS(1) => '0',
S_AXI_HP2_ARQOS(0) => '0',
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2) => '0',
S_AXI_HP2_ARSIZE(1) => '0',
S_AXI_HP2_ARSIZE(0) => '0',
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31) => '0',
S_AXI_HP2_AWADDR(30) => '0',
S_AXI_HP2_AWADDR(29) => '0',
S_AXI_HP2_AWADDR(28) => '0',
S_AXI_HP2_AWADDR(27) => '0',
S_AXI_HP2_AWADDR(26) => '0',
S_AXI_HP2_AWADDR(25) => '0',
S_AXI_HP2_AWADDR(24) => '0',
S_AXI_HP2_AWADDR(23) => '0',
S_AXI_HP2_AWADDR(22) => '0',
S_AXI_HP2_AWADDR(21) => '0',
S_AXI_HP2_AWADDR(20) => '0',
S_AXI_HP2_AWADDR(19) => '0',
S_AXI_HP2_AWADDR(18) => '0',
S_AXI_HP2_AWADDR(17) => '0',
S_AXI_HP2_AWADDR(16) => '0',
S_AXI_HP2_AWADDR(15) => '0',
S_AXI_HP2_AWADDR(14) => '0',
S_AXI_HP2_AWADDR(13) => '0',
S_AXI_HP2_AWADDR(12) => '0',
S_AXI_HP2_AWADDR(11) => '0',
S_AXI_HP2_AWADDR(10) => '0',
S_AXI_HP2_AWADDR(9) => '0',
S_AXI_HP2_AWADDR(8) => '0',
S_AXI_HP2_AWADDR(7) => '0',
S_AXI_HP2_AWADDR(6) => '0',
S_AXI_HP2_AWADDR(5) => '0',
S_AXI_HP2_AWADDR(4) => '0',
S_AXI_HP2_AWADDR(3) => '0',
S_AXI_HP2_AWADDR(2) => '0',
S_AXI_HP2_AWADDR(1) => '0',
S_AXI_HP2_AWADDR(0) => '0',
S_AXI_HP2_AWBURST(1) => '0',
S_AXI_HP2_AWBURST(0) => '0',
S_AXI_HP2_AWCACHE(3) => '0',
S_AXI_HP2_AWCACHE(2) => '0',
S_AXI_HP2_AWCACHE(1) => '0',
S_AXI_HP2_AWCACHE(0) => '0',
S_AXI_HP2_AWID(5) => '0',
S_AXI_HP2_AWID(4) => '0',
S_AXI_HP2_AWID(3) => '0',
S_AXI_HP2_AWID(2) => '0',
S_AXI_HP2_AWID(1) => '0',
S_AXI_HP2_AWID(0) => '0',
S_AXI_HP2_AWLEN(3) => '0',
S_AXI_HP2_AWLEN(2) => '0',
S_AXI_HP2_AWLEN(1) => '0',
S_AXI_HP2_AWLEN(0) => '0',
S_AXI_HP2_AWLOCK(1) => '0',
S_AXI_HP2_AWLOCK(0) => '0',
S_AXI_HP2_AWPROT(2) => '0',
S_AXI_HP2_AWPROT(1) => '0',
S_AXI_HP2_AWPROT(0) => '0',
S_AXI_HP2_AWQOS(3) => '0',
S_AXI_HP2_AWQOS(2) => '0',
S_AXI_HP2_AWQOS(1) => '0',
S_AXI_HP2_AWQOS(0) => '0',
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2) => '0',
S_AXI_HP2_AWSIZE(1) => '0',
S_AXI_HP2_AWSIZE(0) => '0',
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63) => '0',
S_AXI_HP2_WDATA(62) => '0',
S_AXI_HP2_WDATA(61) => '0',
S_AXI_HP2_WDATA(60) => '0',
S_AXI_HP2_WDATA(59) => '0',
S_AXI_HP2_WDATA(58) => '0',
S_AXI_HP2_WDATA(57) => '0',
S_AXI_HP2_WDATA(56) => '0',
S_AXI_HP2_WDATA(55) => '0',
S_AXI_HP2_WDATA(54) => '0',
S_AXI_HP2_WDATA(53) => '0',
S_AXI_HP2_WDATA(52) => '0',
S_AXI_HP2_WDATA(51) => '0',
S_AXI_HP2_WDATA(50) => '0',
S_AXI_HP2_WDATA(49) => '0',
S_AXI_HP2_WDATA(48) => '0',
S_AXI_HP2_WDATA(47) => '0',
S_AXI_HP2_WDATA(46) => '0',
S_AXI_HP2_WDATA(45) => '0',
S_AXI_HP2_WDATA(44) => '0',
S_AXI_HP2_WDATA(43) => '0',
S_AXI_HP2_WDATA(42) => '0',
S_AXI_HP2_WDATA(41) => '0',
S_AXI_HP2_WDATA(40) => '0',
S_AXI_HP2_WDATA(39) => '0',
S_AXI_HP2_WDATA(38) => '0',
S_AXI_HP2_WDATA(37) => '0',
S_AXI_HP2_WDATA(36) => '0',
S_AXI_HP2_WDATA(35) => '0',
S_AXI_HP2_WDATA(34) => '0',
S_AXI_HP2_WDATA(33) => '0',
S_AXI_HP2_WDATA(32) => '0',
S_AXI_HP2_WDATA(31) => '0',
S_AXI_HP2_WDATA(30) => '0',
S_AXI_HP2_WDATA(29) => '0',
S_AXI_HP2_WDATA(28) => '0',
S_AXI_HP2_WDATA(27) => '0',
S_AXI_HP2_WDATA(26) => '0',
S_AXI_HP2_WDATA(25) => '0',
S_AXI_HP2_WDATA(24) => '0',
S_AXI_HP2_WDATA(23) => '0',
S_AXI_HP2_WDATA(22) => '0',
S_AXI_HP2_WDATA(21) => '0',
S_AXI_HP2_WDATA(20) => '0',
S_AXI_HP2_WDATA(19) => '0',
S_AXI_HP2_WDATA(18) => '0',
S_AXI_HP2_WDATA(17) => '0',
S_AXI_HP2_WDATA(16) => '0',
S_AXI_HP2_WDATA(15) => '0',
S_AXI_HP2_WDATA(14) => '0',
S_AXI_HP2_WDATA(13) => '0',
S_AXI_HP2_WDATA(12) => '0',
S_AXI_HP2_WDATA(11) => '0',
S_AXI_HP2_WDATA(10) => '0',
S_AXI_HP2_WDATA(9) => '0',
S_AXI_HP2_WDATA(8) => '0',
S_AXI_HP2_WDATA(7) => '0',
S_AXI_HP2_WDATA(6) => '0',
S_AXI_HP2_WDATA(5) => '0',
S_AXI_HP2_WDATA(4) => '0',
S_AXI_HP2_WDATA(3) => '0',
S_AXI_HP2_WDATA(2) => '0',
S_AXI_HP2_WDATA(1) => '0',
S_AXI_HP2_WDATA(0) => '0',
S_AXI_HP2_WID(5) => '0',
S_AXI_HP2_WID(4) => '0',
S_AXI_HP2_WID(3) => '0',
S_AXI_HP2_WID(2) => '0',
S_AXI_HP2_WID(1) => '0',
S_AXI_HP2_WID(0) => '0',
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7) => '0',
S_AXI_HP2_WSTRB(6) => '0',
S_AXI_HP2_WSTRB(5) => '0',
S_AXI_HP2_WSTRB(4) => '0',
S_AXI_HP2_WSTRB(3) => '0',
S_AXI_HP2_WSTRB(2) => '0',
S_AXI_HP2_WSTRB(1) => '0',
S_AXI_HP2_WSTRB(0) => '0',
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31) => '0',
S_AXI_HP3_ARADDR(30) => '0',
S_AXI_HP3_ARADDR(29) => '0',
S_AXI_HP3_ARADDR(28) => '0',
S_AXI_HP3_ARADDR(27) => '0',
S_AXI_HP3_ARADDR(26) => '0',
S_AXI_HP3_ARADDR(25) => '0',
S_AXI_HP3_ARADDR(24) => '0',
S_AXI_HP3_ARADDR(23) => '0',
S_AXI_HP3_ARADDR(22) => '0',
S_AXI_HP3_ARADDR(21) => '0',
S_AXI_HP3_ARADDR(20) => '0',
S_AXI_HP3_ARADDR(19) => '0',
S_AXI_HP3_ARADDR(18) => '0',
S_AXI_HP3_ARADDR(17) => '0',
S_AXI_HP3_ARADDR(16) => '0',
S_AXI_HP3_ARADDR(15) => '0',
S_AXI_HP3_ARADDR(14) => '0',
S_AXI_HP3_ARADDR(13) => '0',
S_AXI_HP3_ARADDR(12) => '0',
S_AXI_HP3_ARADDR(11) => '0',
S_AXI_HP3_ARADDR(10) => '0',
S_AXI_HP3_ARADDR(9) => '0',
S_AXI_HP3_ARADDR(8) => '0',
S_AXI_HP3_ARADDR(7) => '0',
S_AXI_HP3_ARADDR(6) => '0',
S_AXI_HP3_ARADDR(5) => '0',
S_AXI_HP3_ARADDR(4) => '0',
S_AXI_HP3_ARADDR(3) => '0',
S_AXI_HP3_ARADDR(2) => '0',
S_AXI_HP3_ARADDR(1) => '0',
S_AXI_HP3_ARADDR(0) => '0',
S_AXI_HP3_ARBURST(1) => '0',
S_AXI_HP3_ARBURST(0) => '0',
S_AXI_HP3_ARCACHE(3) => '0',
S_AXI_HP3_ARCACHE(2) => '0',
S_AXI_HP3_ARCACHE(1) => '0',
S_AXI_HP3_ARCACHE(0) => '0',
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5) => '0',
S_AXI_HP3_ARID(4) => '0',
S_AXI_HP3_ARID(3) => '0',
S_AXI_HP3_ARID(2) => '0',
S_AXI_HP3_ARID(1) => '0',
S_AXI_HP3_ARID(0) => '0',
S_AXI_HP3_ARLEN(3) => '0',
S_AXI_HP3_ARLEN(2) => '0',
S_AXI_HP3_ARLEN(1) => '0',
S_AXI_HP3_ARLEN(0) => '0',
S_AXI_HP3_ARLOCK(1) => '0',
S_AXI_HP3_ARLOCK(0) => '0',
S_AXI_HP3_ARPROT(2) => '0',
S_AXI_HP3_ARPROT(1) => '0',
S_AXI_HP3_ARPROT(0) => '0',
S_AXI_HP3_ARQOS(3) => '0',
S_AXI_HP3_ARQOS(2) => '0',
S_AXI_HP3_ARQOS(1) => '0',
S_AXI_HP3_ARQOS(0) => '0',
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2) => '0',
S_AXI_HP3_ARSIZE(1) => '0',
S_AXI_HP3_ARSIZE(0) => '0',
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31) => '0',
S_AXI_HP3_AWADDR(30) => '0',
S_AXI_HP3_AWADDR(29) => '0',
S_AXI_HP3_AWADDR(28) => '0',
S_AXI_HP3_AWADDR(27) => '0',
S_AXI_HP3_AWADDR(26) => '0',
S_AXI_HP3_AWADDR(25) => '0',
S_AXI_HP3_AWADDR(24) => '0',
S_AXI_HP3_AWADDR(23) => '0',
S_AXI_HP3_AWADDR(22) => '0',
S_AXI_HP3_AWADDR(21) => '0',
S_AXI_HP3_AWADDR(20) => '0',
S_AXI_HP3_AWADDR(19) => '0',
S_AXI_HP3_AWADDR(18) => '0',
S_AXI_HP3_AWADDR(17) => '0',
S_AXI_HP3_AWADDR(16) => '0',
S_AXI_HP3_AWADDR(15) => '0',
S_AXI_HP3_AWADDR(14) => '0',
S_AXI_HP3_AWADDR(13) => '0',
S_AXI_HP3_AWADDR(12) => '0',
S_AXI_HP3_AWADDR(11) => '0',
S_AXI_HP3_AWADDR(10) => '0',
S_AXI_HP3_AWADDR(9) => '0',
S_AXI_HP3_AWADDR(8) => '0',
S_AXI_HP3_AWADDR(7) => '0',
S_AXI_HP3_AWADDR(6) => '0',
S_AXI_HP3_AWADDR(5) => '0',
S_AXI_HP3_AWADDR(4) => '0',
S_AXI_HP3_AWADDR(3) => '0',
S_AXI_HP3_AWADDR(2) => '0',
S_AXI_HP3_AWADDR(1) => '0',
S_AXI_HP3_AWADDR(0) => '0',
S_AXI_HP3_AWBURST(1) => '0',
S_AXI_HP3_AWBURST(0) => '0',
S_AXI_HP3_AWCACHE(3) => '0',
S_AXI_HP3_AWCACHE(2) => '0',
S_AXI_HP3_AWCACHE(1) => '0',
S_AXI_HP3_AWCACHE(0) => '0',
S_AXI_HP3_AWID(5) => '0',
S_AXI_HP3_AWID(4) => '0',
S_AXI_HP3_AWID(3) => '0',
S_AXI_HP3_AWID(2) => '0',
S_AXI_HP3_AWID(1) => '0',
S_AXI_HP3_AWID(0) => '0',
S_AXI_HP3_AWLEN(3) => '0',
S_AXI_HP3_AWLEN(2) => '0',
S_AXI_HP3_AWLEN(1) => '0',
S_AXI_HP3_AWLEN(0) => '0',
S_AXI_HP3_AWLOCK(1) => '0',
S_AXI_HP3_AWLOCK(0) => '0',
S_AXI_HP3_AWPROT(2) => '0',
S_AXI_HP3_AWPROT(1) => '0',
S_AXI_HP3_AWPROT(0) => '0',
S_AXI_HP3_AWQOS(3) => '0',
S_AXI_HP3_AWQOS(2) => '0',
S_AXI_HP3_AWQOS(1) => '0',
S_AXI_HP3_AWQOS(0) => '0',
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2) => '0',
S_AXI_HP3_AWSIZE(1) => '0',
S_AXI_HP3_AWSIZE(0) => '0',
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63) => '0',
S_AXI_HP3_WDATA(62) => '0',
S_AXI_HP3_WDATA(61) => '0',
S_AXI_HP3_WDATA(60) => '0',
S_AXI_HP3_WDATA(59) => '0',
S_AXI_HP3_WDATA(58) => '0',
S_AXI_HP3_WDATA(57) => '0',
S_AXI_HP3_WDATA(56) => '0',
S_AXI_HP3_WDATA(55) => '0',
S_AXI_HP3_WDATA(54) => '0',
S_AXI_HP3_WDATA(53) => '0',
S_AXI_HP3_WDATA(52) => '0',
S_AXI_HP3_WDATA(51) => '0',
S_AXI_HP3_WDATA(50) => '0',
S_AXI_HP3_WDATA(49) => '0',
S_AXI_HP3_WDATA(48) => '0',
S_AXI_HP3_WDATA(47) => '0',
S_AXI_HP3_WDATA(46) => '0',
S_AXI_HP3_WDATA(45) => '0',
S_AXI_HP3_WDATA(44) => '0',
S_AXI_HP3_WDATA(43) => '0',
S_AXI_HP3_WDATA(42) => '0',
S_AXI_HP3_WDATA(41) => '0',
S_AXI_HP3_WDATA(40) => '0',
S_AXI_HP3_WDATA(39) => '0',
S_AXI_HP3_WDATA(38) => '0',
S_AXI_HP3_WDATA(37) => '0',
S_AXI_HP3_WDATA(36) => '0',
S_AXI_HP3_WDATA(35) => '0',
S_AXI_HP3_WDATA(34) => '0',
S_AXI_HP3_WDATA(33) => '0',
S_AXI_HP3_WDATA(32) => '0',
S_AXI_HP3_WDATA(31) => '0',
S_AXI_HP3_WDATA(30) => '0',
S_AXI_HP3_WDATA(29) => '0',
S_AXI_HP3_WDATA(28) => '0',
S_AXI_HP3_WDATA(27) => '0',
S_AXI_HP3_WDATA(26) => '0',
S_AXI_HP3_WDATA(25) => '0',
S_AXI_HP3_WDATA(24) => '0',
S_AXI_HP3_WDATA(23) => '0',
S_AXI_HP3_WDATA(22) => '0',
S_AXI_HP3_WDATA(21) => '0',
S_AXI_HP3_WDATA(20) => '0',
S_AXI_HP3_WDATA(19) => '0',
S_AXI_HP3_WDATA(18) => '0',
S_AXI_HP3_WDATA(17) => '0',
S_AXI_HP3_WDATA(16) => '0',
S_AXI_HP3_WDATA(15) => '0',
S_AXI_HP3_WDATA(14) => '0',
S_AXI_HP3_WDATA(13) => '0',
S_AXI_HP3_WDATA(12) => '0',
S_AXI_HP3_WDATA(11) => '0',
S_AXI_HP3_WDATA(10) => '0',
S_AXI_HP3_WDATA(9) => '0',
S_AXI_HP3_WDATA(8) => '0',
S_AXI_HP3_WDATA(7) => '0',
S_AXI_HP3_WDATA(6) => '0',
S_AXI_HP3_WDATA(5) => '0',
S_AXI_HP3_WDATA(4) => '0',
S_AXI_HP3_WDATA(3) => '0',
S_AXI_HP3_WDATA(2) => '0',
S_AXI_HP3_WDATA(1) => '0',
S_AXI_HP3_WDATA(0) => '0',
S_AXI_HP3_WID(5) => '0',
S_AXI_HP3_WID(4) => '0',
S_AXI_HP3_WID(3) => '0',
S_AXI_HP3_WID(2) => '0',
S_AXI_HP3_WID(1) => '0',
S_AXI_HP3_WID(0) => '0',
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7) => '0',
S_AXI_HP3_WSTRB(6) => '0',
S_AXI_HP3_WSTRB(5) => '0',
S_AXI_HP3_WSTRB(4) => '0',
S_AXI_HP3_WSTRB(3) => '0',
S_AXI_HP3_WSTRB(2) => '0',
S_AXI_HP3_WSTRB(1) => '0',
S_AXI_HP3_WSTRB(0) => '0',
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
USB1_VBUS_PWRFAULT => USB1_VBUS_PWRFAULT,
USB1_VBUS_PWRSELECT => USB1_VBUS_PWRSELECT,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| gpl-3.0 | 2ed4be848077d38902aff2ea2c518c2b | 0.612654 | 2.54362 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_16.vhd | 1 | 77,708 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_16.vhd
-- /___/ /\ Timestamp: Mon Jul 14 16:27:30 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_16
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_16 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_16;
architecture STRUCTURE of fifo_generator_64_16 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"303A3030003A0030"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => N19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I4 => N19,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000119 : LUT6
generic map(
INIT => X"AE0AAA0AAEAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => N21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031 : LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I4 => N21,
O => N111
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056 : LUT5
generic map(
INIT => X"80082002"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000105 : LUT6
generic map(
INIT => X"BAAAAAAA32222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => N0,
RDADDRL(13) => N0,
RDADDRL(12) => N0,
RDADDRL(11) => N0,
RDADDRL(10) => N0,
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => N0,
RDADDRU(13) => N0,
RDADDRU(12) => N0,
RDADDRU(11) => N0,
RDADDRU(10) => N0,
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => N0,
WRADDRL(13) => N0,
WRADDRL(12) => N0,
WRADDRL(11) => N0,
WRADDRL(10) => N0,
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => N0,
WRADDRU(13) => N0,
WRADDRU(12) => N0,
WRADDRU(11) => N0,
WRADDRU(10) => N0,
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 2bc0564a6204ab84d0f9621c2bf1d381 | 0.696711 | 2.854288 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/single_cycle_add_and_xor.vhd | 1 | 2,483 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000") and (done_aax_int = '0') and (reset_n = '1')) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
| mit | b304c7e107bbe3e208950fe3c26c6259 | 0.482481 | 3.79084 | false | false | false | false |
zambreno/RCL | sccCyGraph/coregen/fifo_generator_64_d16.vhd | 1 | 117,945 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_d16.vhd
-- /___/ /\ Timestamp: Wed Jul 23 15:53:31 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d16.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d16.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d16.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d16.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_d16
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_d16 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_d16;
architecture STRUCTURE of fifo_generator_64_d16 is
signal N0 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_18 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3_1_28 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_180 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_181 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_182 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_183 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_187 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_189 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_190 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_191 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_192 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37;
dout(63) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63);
dout(62) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62);
dout(61) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61);
dout(60) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60);
dout(59) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59);
dout(58) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58);
dout(57) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57);
dout(56) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56);
dout(55) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55);
dout(54) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54);
dout(53) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53);
dout(52) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52);
dout(51) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51);
dout(50) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50);
dout(49) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49);
dout(48) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48);
dout(47) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47);
dout(46) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46);
dout(45) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45);
dout(44) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44);
dout(43) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43);
dout(42) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42);
dout(41) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41);
dout(40) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40);
dout(39) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39);
dout(38) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38);
dout(37) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37);
dout(36) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36);
dout(35) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35);
dout(34) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34);
dout(33) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33);
dout(32) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32);
dout(31) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31);
dout(30) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30);
dout(29) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29);
dout(28) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28);
dout(27) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27);
dout(26) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26);
dout(25) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25);
dout(24) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24);
dout(23) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23);
dout(22) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22);
dout(21) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21);
dout(20) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20);
dout(19) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19);
dout(18) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18);
dout(17) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17);
dout(16) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16);
dout(15) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15);
dout(14) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14);
dout(13) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13);
dout(12) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12);
dout(11) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11);
dout(10) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10);
dout(9) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9);
dout(8) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8);
dout(7) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7);
dout(6) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6);
dout(5) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5);
dout(4) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4);
dout(3) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3);
dout(2) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2);
dout(1) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1);
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_189,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_180
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_189
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_182,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_183
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_191,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_192
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_187,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_188
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_181,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_182
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_191,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_190
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_190,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_191
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_182,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_181
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_187
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => N0,
D => din(63),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => N0,
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => N0,
D => din(62),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => N0,
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => N0,
D => din(61),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => N0,
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => N0,
D => din(60),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => N0,
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(55),
DIA(0) => din(54),
DIB(1) => din(57),
DIB(0) => din(56),
DIC(1) => din(59),
DIC(0) => din(58),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(43),
DIA(0) => din(42),
DIB(1) => din(45),
DIB(0) => din(44),
DIC(1) => din(47),
DIC(0) => din(46),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(37),
DIA(0) => din(36),
DIB(1) => din(39),
DIB(0) => din(38),
DIC(1) => din(41),
DIC(0) => din(40),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(49),
DIA(0) => din(48),
DIB(1) => din(51),
DIB(0) => din(50),
DIC(1) => din(53),
DIC(0) => din(52),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(25),
DIA(0) => din(24),
DIB(1) => din(27),
DIB(0) => din(26),
DIC(1) => din(29),
DIC(0) => din(28),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(19),
DIA(0) => din(18),
DIB(1) => din(21),
DIB(0) => din(20),
DIC(1) => din(23),
DIC(0) => din(22),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(31),
DIA(0) => din(30),
DIB(1) => din(33),
DIB(0) => din(32),
DIC(1) => din(35),
DIC(0) => din(34),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(7),
DIA(0) => din(6),
DIB(1) => din(9),
DIB(0) => din(8),
DIC(1) => din(11),
DIC(0) => din(10),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(1),
DIA(0) => din(0),
DIB(1) => din(3),
DIB(0) => din(2),
DIC(1) => din(5),
DIC(0) => din(4),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(13),
DIA(0) => din(12),
DIB(1) => din(15),
DIB(0) => din(14),
DIC(1) => din(17),
DIC(0) => din(16),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => N0,
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => N0,
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => N0,
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => N0,
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_63 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_62 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_61 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_60 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_59 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_58 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_57 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_56 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_55 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_54 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_53 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_52 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_51 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_50 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_49 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_48 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_47 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_46 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_45 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_44 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_43 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_42 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_41 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_40 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_39 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_38 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_37 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_36 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_35 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_34 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_33 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_32 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_31 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_192,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_190,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_183,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_181,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"303A3030003A0030"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_180,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT4
generic map(
INIT => X"7BDE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3_1_28,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
O => N19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I4 => N19,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_180,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000119 : LUT6
generic map(
INIT => X"A0EAA0AAAAEAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031_SW0 : LUT4
generic map(
INIT => X"7BDE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3_1_28,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
O => N21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031 : LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I4 => N21,
O => N111
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056 : LUT5
generic map(
INIT => X"80082002"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000105 : LUT6
generic map(
INIT => X"BAAAAAAA32222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_16,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_17,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_18,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3_1_28
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
end STRUCTURE;
-- synthesis translate_on
| apache-2.0 | 90b085dbc5d8c890a310b6d895206deb | 0.658909 | 2.473575 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Advanced/test_led_bright.vhd | 1 | 1,783 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_led_bright IS
END test_led_bright;
ARCHITECTURE behavior OF test_led_bright IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT led_bright
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
ready : IN std_logic;
accel_val : IN std_logic_vector(7 downto 0);
pwm_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '0';
signal ready : std_logic := '0';
signal accel_val : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal pwm_out : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: led_bright PORT MAP (
clk => clk,
masterReset => masterReset,
ready => ready,
accel_val => accel_val,
pwm_out => pwm_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ready <= '0';
wait for clk_period*5;
accel_val <= "00011111";
ready <= '1';
wait for clk_period*100;
ready <= '0';
wait for clk_period*5;
accel_val <= "10001000";
ready <= '1';
wait for clk_period*100;
ready <= '0';
wait for clk_period*5;
accel_val <= "11111100";
ready <= '1';
wait for clk_period*100;
ready <= '0';
wait for clk_period*5;
wait;
end process;
END;
| apache-2.0 | 92208827c07ae98c6e57df280381ac08 | 0.545709 | 3.530693 | false | true | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DPU_matrix_multiplication/DPU_matrix_multiplication_tb.vhd | 1 | 1,823 | library ieee;
use ieee.std_logic_1164.all;
entity DPU_matrix_multiplication_tb is
end DPU_matrix_multiplication_tb;
architecture tb of DPU_matrix_multiplication_tb is
Component DPU_matrix_multiplication
port(
Ain : IN std_logic_vector(3 downto 0);
Bin : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
clear: in std_logic;
Aout : OUT std_logic_vector(3 downto 0);
Bout : OUT std_logic_vector(3 downto 0);
Result : OUT std_logic_vector(9 downto 0)
);
end component;
signal Ain : std_logic_vector(3 downto 0) := (others => '0');
signal Bin : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal clear: std_logic :='0';
signal Aout : std_logic_vector(3 downto 0);
signal Bout : std_logic_vector(3 downto 0);
signal Result : std_logic_vector(9 downto 0);
-- constant CLK_period : time := 10 ns;
begin
uut: DPU_matrix_multiplication PORT MAP (
Ain => Ain,
Bin => Bin,
CLK => CLK,
clear => clear,
Aout => Aout,
Bout => Bout,
Result => Result
);
-- Clock process definitions
-- CLK_process :process
-- begin
-- CLK <= '0';
-- wait for CLK_period/2;
-- CLK <= '1';
-- wait for CLK_period/2;
-- end process;
process
begin
clear<='1';
CLK<='0'; wait for 1 ps;
CLK<='1'; wait for 1 ps;
end process;
process
begin
clear<='1';
CLK<='0'; wait for 1 ps;
clear<='1';
Ain<=x"1";
Bin<=x"1";
CLK<='1'; wait for 1 ps;
CLK<='0'; wait for 1 ps;
Ain<=x"1";
Bin<=x"1";
CLK<='1'; wait for 1 ps;
CLK<='0'; wait for 1 ps;
Ain<=x"1";
Bin<=x"1";
-- CLK<='1'; wait for 1 ps;
-- CLK<='0'; wait for 1 ps;
CLK<='1'; wait for 1 ps;
-- wait;
end process;
end tb; | mit | f9f6062bb860a49a7f98422148b12547 | 0.56226 | 2.998355 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_1/counter.vhdl | 1 | 1,562 | -- counter
-- An N-bit counter, with reset functionality.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity counter is
generic(n: integer);
port(
clk, reset: in std_logic;
count: out std_logic_vector(n-1 downto 0)
);
end entity;
architecture behaviorial of counter is
component adder is
generic(n: integer);
port(
x: in std_logic_vector(n-1 downto 0);
y: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic
);
end component;
component register_n is
generic(n: integer);
port(
clk, enable, reset: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0)
);
end component;
signal adder_to_register: std_logic_vector(n-1 downto 0);
signal cout: std_logic;
signal enable: std_logic;
signal temp_count: std_logic_vector(n-1 downto 0);
signal zero: std_logic_vector(n-1 downto 0);
begin
zero <= (n-1 downto 0 => '0');
adder_instance: adder
generic map(n => n)
port map(x => temp_count, y => zero, s => adder_to_register, cin => '1', cout => cout);
register_bits_instance: register_n
generic map(n => n)
port map(clk => clk, enable => '1', reset => reset, d => adder_to_register, q => temp_count);
clock_process: process(clk)
begin
count <= temp_count;
end process;
end;
| unlicense | 7cfad27faea5568d7e1ad6dadbf9be91 | 0.574264 | 3.518018 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_3/processor.vhdl | 1 | 2,594 |
----------------------------------------------------------------------
--- Processor
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity processor is
port (
rst : in std_logic;
ck : in std_logic;
we : out std_logic; -- write enable
address : out std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of processor is
subtype state is std_logic_vector(1 downto 0);
component register_n is
generic(n: integer);
port(
clk, enable, reset: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0)
);
end component;
constant fetch: state := "00";
constant decode: state := "01";
constant goto: state := "10";
constant i_goto: std_logic_vector := "01111111";
signal pcwe: std_logic;
signal irwe: std_logic;
signal pcq_to_adder: std_logic_vector(7 downto 0);
signal adder_to_pcd: std_logic_vector(7 downto 0);
signal instruction: std_logic_vector(7 downto 0);
signal current_state, next_state: state;
begin
pc: register_n
generic map(n => 8)
port map(
clk => ck,
enable => pcwe,
reset => rst,
d => adder_to_pcd,
q => pcq_to_adder
);
ir: register_n
generic map(n => 8)
port map(
clk => ck,
enable => irwe,
reset => rst,
d => datain,
q => instruction
);
next_state <=
goto when current_state = fetch and instruction = i_goto else
decode when current_state = fetch else
fetch when current_state = goto else
fetch when current_state = decode else
fetch;
address <= pcq_to_adder;
pcwe <= '1' when current_state = decode or current_state = goto else '0';
irwe <= '1';
we <= '0';
process (ck)
begin
if (current_state = goto) then
adder_to_pcd <= datain;
else
adder_to_pcd <= std_logic_vector(unsigned(pcq_to_adder) + 1);
end if;
if (rising_edge(ck)) then
if (rst = '1') then
current_state <= fetch;
else
current_state <= next_state;
end if;
end if;
end process;
end architecture rtl;
| unlicense | 64e0df189f902cc9324d6b6b9697321c | 0.5 | 4.021705 | false | false | false | false |
willtmwu/vhdlExamples | BCD Adder/Medium/fsm_controller.vhd | 1 | 1,678 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:27:09 09/04/2014
-- Design Name:
-- Module Name: fsm_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_controller is
Port ( masterReset : in STD_LOGIC;
buttonDown : in STD_LOGIC;
en1 : out STD_LOGIC;
en2 : out STD_LOGIC);
end fsm_controller;
architecture Behavioral of fsm_controller is
TYPE timer_state_fsm IS (start, stop1, stop2);
signal timer_state : timer_state_fsm := stop2;
begin
process (masterReset, buttonDown) begin
if (masterReset = '1') then
timer_state <= stop2;
en1 <= '0';
en2 <= '0';
elsif (buttonDown'event and buttonDown = '1') then
case timer_state is
when stop2 =>
en1 <= '1';
en2 <= '1';
timer_state <= start;
when start =>
en1 <= '0';
timer_state <= stop1;
when stop1 =>
en2 <= '0';
timer_state <= stop2;
end case;
end if;
end process;
end Behavioral;
| apache-2.0 | d6908d7344ad00c8f5f3045e4f60e512 | 0.551251 | 3.632035 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | ISE Design Files/DFF_PC/DFF_PC_tb.vhd | 1 | 936 | library ieee;
use ieee.std_logic_1164.all;
entity DFF_PC_tb is
end DFF_PC_tb;
architecture tb of DFF_PC_tb is
component DFF_PC
port( D, CLK, preset, clear: in std_logic;
Q : out std_logic;
Qnot : out std_logic
);
end component;
signal D : std_logic := '0';
signal CLK : std_logic := '0';
signal Preset : std_logic := '1';
signal Clear : std_logic := '1';
signal Q : std_logic;
signal Qnot : std_logic;
begin
mapping: DFF_PC port map(D,CLK,preset,clear,Q,Qnot);
process
begin
CLK <= '0'; wait for 1 ps;
CLK <= '1'; wait for 1 ps;
end process;
process
begin
D <= '0'; wait for 3 ps;
D <= '1'; wait for 3 ps;
end process;
process
begin
preset <= '0'; wait for 5 ps;
preset <= '1'; wait for 40 ps;
clear <= '0'; wait for 5 ps;
clear <= '1'; wait for 40 ps;
end process;
end tb;
configuration cfg_tb of DFF_PC_tb is
for tb
end for;
end cfg_tb; | mit | ce8a880cb0004c05f1645db9a9b62c6f | 0.594017 | 2.761062 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart.vhd | 3 | 1,641 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart is
PORT( CLK_I : in std_logic;
RST_I : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
end uart;
architecture Behavioral of uart is
COMPONENT uart_tx
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
CE_16 : IN std_logic;
DATA : IN std_logic_vector(7 downto 0);
DATA_FLAG : IN std_logic;
SER_OUT : OUT std_logic;
DATA_FLAGQ : OUT std_logic
);
END COMPONENT;
COMPONENT uart_rx
PORT( CLK_I : IN std_logic;
RST_I : IN std_logic;
CE_16 : IN std_logic;
SER_IN : IN std_logic;
DATA : OUT std_logic_vector(7 downto 0);
DATA_FLAG : OUT std_logic
);
END COMPONENT;
begin
tx: uart_tx
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16,
DATA => TX_DATA,
DATA_FLAG => TX_FLAG,
SER_OUT => TX_SEROUT,
DATA_FLAGQ => TX_FLAGQ
);
rx: uart_rx
PORT MAP( CLK_I => CLK_I,
RST_I => RST_I,
CE_16 => CE_16,
DATA => RX_DATA,
SER_IN => RX_SERIN,
DATA_FLAG => RX_FLAG
);
end Behavioral;
| mit | 7626e12129c23aaa32bde0e24e76cd5a | 0.573431 | 2.690164 | false | false | false | false |
willtmwu/vhdlExamples | Project/SPI_hw_interface_test.vhd | 1 | 9,105 | ----------------------------------------------------------------------------------
-- Company: N/A
-- Engineer: WTMW
-- Create Date: 22:27:15 09/26/2014
-- Design Name:
-- Module Name: SPI_hardware_interface_test.vhd
-- Project Name: project_nrf
-- Target Devices: Nexys 4
-- Tool versions: ISE WEBPACK 64-Bit
-- Description: Testing MOSI and MISO
-- for at edge case of 32byte burst read and write
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY SPI_hw_interface_test IS
END SPI_hw_interface_test;
ARCHITECTURE behavior OF SPI_hw_interface_test IS
COMPONENT SPI_hw_interface
PORT(
clk : IN std_logic;
masterReset : IN std_logic;
en : IN std_logic;
data_byte_in : IN std_logic_vector(7 downto 0);
data_byte_out : OUT std_logic_vector(7 downto 0);
wen : IN std_logic;
ren : IN std_logic;
M_active : OUT std_logic;
M_finished : out std_logic;
regLocation : IN std_logic_vector(7 downto 0);
dataAmount : IN std_logic_vector(5 downto 0);
CS : OUT std_logic;
SCLK : OUT std_logic;
MOSI : OUT std_logic;
MISO : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal masterReset : std_logic := '0';
signal en : std_logic := '0';
signal data_byte_in : std_logic_vector(7 downto 0) := (others => '0');
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal regLocation : std_logic_vector(7 downto 0) := (others => '0');
signal dataAmount : std_logic_vector(5 downto 0) := (others => '0');
signal MISO : std_logic := '0';
--Outputs
signal data_byte_out : std_logic_vector(7 downto 0) := (others => '0');
signal CS : std_logic;
signal SCLK : std_logic;
signal MOSI : std_logic;
signal M_finished : std_logic;
signal M_active : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
--Procedure should mimic NRF, will need to clock out
procedure SPI_MISO (
byte_in : in std_logic_vector(7 downto 0) ;
signal MISO : out std_logic
) is
begin
for i in 7 downto 0 loop
MISO <= byte_in(i);
wait until falling_edge(SCLK);
end loop;
end SPI_MISO;
BEGIN
uut: SPI_hw_interface PORT MAP (
clk => clk,
masterReset => masterReset,
en => en,
data_byte_in => data_byte_in,
data_byte_out => data_byte_out,
wen => wen,
ren => ren,
M_active => M_active,
M_finished => M_finished,
regLocation => regLocation,
dataAmount => dataAmount,
CS => CS,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait until rising_edge(clk);
masterReset <= '1';
wait for clk_period*5;
wait until rising_edge(clk);
masterReset <= '0';
-- PART ONE Retest Sending, 3 Bytes
wait until rising_edge(clk);
en <= '1';
data_byte_in <= "11001001";
wait until rising_edge(clk);
data_byte_in <= "00111001";
wait until rising_edge(clk);
data_byte_in <= "10011011";
wait until rising_edge(clk);
data_byte_in <= (others => '0'); -- Check data is in
en <= '0';
regLocation <= "10001011";
dataAmount <= "000011"; -- 3 bytes to send
wen <= '1'; -- Pulse WEN
wait until rising_edge(clk);
wen <= '0';
wait for clk_period*1000;
wait until M_finished = '1';
wait for clk_period*10;
-- PART TWO Retest Sending, 32 Bytes
wait for clk_period*5;
masterReset <= '0';
wait until rising_edge(clk);
en <= '1';
data_byte_in <= "10000001"; -- 0
wait until rising_edge(clk);
data_byte_in <= "10000011"; -- 1
wait until rising_edge(clk);
data_byte_in <= "10000101"; -- 2
wait until rising_edge(clk);
data_byte_in <= "10000111"; -- 3
wait until rising_edge(clk);
data_byte_in <= "10001001"; -- 4
wait until rising_edge(clk);
data_byte_in <= "10001011"; -- 5
wait until rising_edge(clk);
data_byte_in <= "10001101"; -- 6
wait until rising_edge(clk);
data_byte_in <= "10001111"; -- 7
wait until rising_edge(clk);
data_byte_in <= "10010001"; -- 8
wait until rising_edge(clk);
data_byte_in <= "10010011"; -- 9
wait until rising_edge(clk);
data_byte_in <= "10010101"; -- 10
wait until rising_edge(clk);
data_byte_in <= "10010111"; -- 11
wait until rising_edge(clk);
data_byte_in <= "10011001"; -- 12
wait until rising_edge(clk);
data_byte_in <= "10011011"; -- 13
wait until rising_edge(clk);
data_byte_in <= "10011101"; -- 14
wait until rising_edge(clk);
data_byte_in <= "10011111"; -- 15
wait until rising_edge(clk);
data_byte_in <= "10100001"; -- 16
wait until rising_edge(clk);
data_byte_in <= "10100011"; -- 17
wait until rising_edge(clk);
data_byte_in <= "10100101"; -- 18
wait until rising_edge(clk);
data_byte_in <= "10100111"; -- 19
wait until rising_edge(clk);
data_byte_in <= "10101001"; -- 20
wait until rising_edge(clk);
data_byte_in <= "10101011"; -- 21
wait until rising_edge(clk);
data_byte_in <= "10101101"; -- 22
wait until rising_edge(clk);
data_byte_in <= "10101111"; -- 23
wait until rising_edge(clk);
data_byte_in <= "10110001"; -- 24
wait until rising_edge(clk);
data_byte_in <= "10110011"; -- 25
wait until rising_edge(clk);
data_byte_in <= "10110101"; -- 26
wait until rising_edge(clk);
data_byte_in <= "10110111"; -- 27
wait until rising_edge(clk);
data_byte_in <= "10111001"; -- 28
wait until rising_edge(clk);
data_byte_in <= "10111011"; -- 29
wait until rising_edge(clk);
data_byte_in <= "10111101"; -- 30
wait until rising_edge(clk);
data_byte_in <= "10111111"; -- 31
wait until rising_edge(clk);
data_byte_in <= (others => '0'); -- Check data is in
en <= '0'; -- Data is loaded in properly
regLocation <= "10101011";
dataAmount <= "100000"; -- 32 bytes to send
wen <= '1'; -- Pulse WEN
wait until rising_edge(clk);
wen <= '0';
-- PART 3 Test Reading, 4 Bytes
wait for clk_period*1000;
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk);
regLocation <= "11101011";
dataAmount <= "000100"; -- 4 bytes to read
ren <= '1';
wait until rising_edge(clk);
ren <= '0';
SPI_MISO("11111110", MISO); -- Dummy Shift
SPI_MISO("10110011", MISO); -- Byte 1
SPI_MISO("10011000", MISO); -- Byte 2
SPI_MISO("10101101", MISO); -- Byte 3
SPI_MISO("11101111", MISO); -- Byte 3
-- CLK out the data
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk); -- Clocking out is delayed 1 clk cycle, be careful
en <= '1';
wait for clk_period*6;
wait until rising_edge(clk);
en <= '0';
-- Tested OK , 4 bytes now 32 byte test
-- PART 4 Test Reading, 32 Bytes
wait for clk_period*10;
wait until rising_edge(clk);
regLocation <= "10110111";
dataAmount <= "100000"; -- 4 bytes to read
ren <= '1';
wait until rising_edge(clk);
ren <= '0';
SPI_MISO("11111111", MISO); -- Dummy Shift
SPI_MISO("10000001", MISO); -- Byte 0
SPI_MISO("10000011", MISO); -- Byte 1
SPI_MISO("10000101", MISO); -- Byte 2
SPI_MISO("10000111", MISO); -- Byte 3
SPI_MISO("10001001", MISO); -- Byte 4
SPI_MISO("10001011", MISO); -- Byte 5
SPI_MISO("10001101", MISO); -- Byte 6
SPI_MISO("10001111", MISO); -- Byte 7
SPI_MISO("10010001", MISO); -- Byte 8
SPI_MISO("10010011", MISO); -- Byte 9
SPI_MISO("10010101", MISO); -- Byte 10
SPI_MISO("10010111", MISO); -- Byte 11
SPI_MISO("10011001", MISO); -- Byte 12
SPI_MISO("10011011", MISO); -- Byte 13
SPI_MISO("10011101", MISO); -- Byte 14
SPI_MISO("10011111", MISO); -- Byte 15
SPI_MISO("10100001", MISO); -- Byte 16
SPI_MISO("10100011", MISO); -- Byte 17
SPI_MISO("10100101", MISO); -- Byte 18
SPI_MISO("10100111", MISO); -- Byte 19
SPI_MISO("10101001", MISO); -- Byte 20
SPI_MISO("10101011", MISO); -- Byte 21
SPI_MISO("10101101", MISO); -- Byte 22
SPI_MISO("10101111", MISO); -- Byte 23
SPI_MISO("10110001", MISO); -- Byte 24
SPI_MISO("10110011", MISO); -- Byte 25
SPI_MISO("10110101", MISO); -- Byte 26
SPI_MISO("10110111", MISO); -- Byte 27
SPI_MISO("10111001", MISO); -- Byte 28
SPI_MISO("10111011", MISO); -- Byte 29
SPI_MISO("10111101", MISO); -- Byte 30
SPI_MISO("10111111", MISO); -- Byte 31
-- CLK out the data
wait until M_finished = '1';
wait for clk_period*10;
wait until rising_edge(clk); -- Clocking out is delayed 1 clk cycle, be careful
en <= '1';
wait for clk_period*32; -- Last Clocked byte is also remains for 1 clk cycle
wait until rising_edge(clk);
en <= '0';
-- TEST OK
wait;
end process;
END;
| apache-2.0 | 5aea0706afa412e7f3736facdcb16367 | 0.590555 | 3.100102 | false | false | false | false |
Lyrositor/insa | 3if/ac/tp-ac_2/passage_a_niveau.vhdl | 1 | 2,272 | -- User-Encoded State Machine
library ieee;
use ieee.std_logic_1164.all;
library work;
entity passage_a_niveau is
port(
clock: in std_logic;
reset: in std_logic;
capteur_droite: in std_logic;
capteur_gauche: in std_logic;
ampoule: out std_logic;
alert: out std_logic
);
end entity;
architecture rtl of passage_a_niveau is
-- a type declaration to make the following easier to read
subtype state is std_logic_vector(2 downto 0);
-- State encoding:
constant pdt: state := "000";
constant tvdd: state := "001";
constant tvdd2: state := "010";
constant tvdg: state := "101";
constant tvdg2: state := "110";
constant cata: state := "111";
signal current_state, next_state: state;
begin
-- transition function --
next_state <=
pdt when current_state = pdt and capteur_gauche = '0' and capteur_droite = '0' else
tvdd when current_state = pdt and capteur_gauche = '0' and capteur_droite = '1' else
tvdg when current_state = pdt and capteur_gauche = '1' and capteur_droite = '0' else
tvdd when current_state = tvdd and capteur_gauche = '0' else
tvdd2 when current_state = tvdd and capteur_gauche = '1' else
tvdd2 when current_state = tvdd2 and capteur_gauche = '1' else
pdt when current_state = tvdd2 and capteur_gauche = '0' else
tvdg when current_state = tvdg and capteur_droite = '0' else
tvdg2 when current_state = tvdg and capteur_droite = '1' else
tvdg2 when current_state = tvdg2 and capteur_droite = '1' else
pdt when current_state = tvdg2 and capteur_droite = '0' else
cata; -- all the other cases
-- output function --
ampoule <= '0' when current_state = pdt else '1';
-- the state register --
process (clock)
begin
if (rising_edge(clock)) then
if (current_state = cata) then
alert <= '1';
else
alert <= '0';
end if;
if (reset = '1') then
current_state <= pdt; --initial state
else
current_state <= next_state;
end if;
end if;
end process;
end architecture;
| unlicense | a9a541cd24223bf8443cc4844fdb8e00 | 0.587588 | 3.517028 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/cpu_engine.vhd | 1 | 12,579 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity cpu_engine is
PORT( -- WISHBONE interface
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0);
DAT_O : out std_logic_vector( 7 downto 0);
RST_I : in std_logic;
ACK_I : in std_logic;
ADR_O : out std_logic_vector(15 downto 0);
CYC_O : out std_logic;
STB_O : out std_logic;
TGA_O : out std_logic_vector( 0 downto 0); -- '1' if I/O
WE_O : out std_logic;
INT : in std_logic;
HALT : out std_logic;
-- debug signals
--
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end cpu_engine;
architecture Behavioral of cpu_engine is
-- Unfortunately, the on-chip memory needs a clock to read data.
-- Therefore we cannot make it wishbone compliant without a speed penalty.
-- We avoid this problem by making the on-chip memory part of the CPU.
-- However, as a consequence, you cannot DMA to the on-chip memory.
--
-- The on-chip memory is 8K, so that you can run a test SoC without external
-- memory. For bigger applications, you should use external ROM and RAM and
-- remove the internal memory entirely (setting EXTERN accordingly).
--
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
OP_CAT : out op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_SP : out SP_OP;
D_RD_O : out std_logic;
D_WE_O : out std_logic;
D_LOCK : out std_logic;
-- input/output
D_IO : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- data from memory/IO
ADR : out std_logic_vector(15 downto 0); -- memory/IO address
MQ : out std_logic_vector( 7 downto 0); -- data to memory/IO
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
-- global signals
signal CE : std_logic;
signal T2 : std_logic;
-- memory signals
signal WDAT : std_logic_vector(7 downto 0);
signal RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_RD_O : std_logic;
signal D_WE_O : std_logic;
signal D_LOCK : std_logic; -- first cycle
signal LM_WE : std_logic;
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal XM_RDAT : std_logic_vector(7 downto 0);
signal C_IO : std_logic;
signal C_RD_O : std_logic;
signal C_WE_O : std_logic;
-- signals to remember, whether the previous read cycle
-- addressed internal memory or external memory
--
signal OPCS : std_logic; -- '1' if opcode from external memory
signal RDATS : std_logic; -- '1' if data from external memory
signal EXTERN : std_logic; -- '1' if opcode or data from external memory
begin
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
-- read in T1
PC => M_PC,
OPC => LM_OPC,
-- read or written in T2
ADR => ADR,
WR => LM_WE,
WDAT => WDAT,
RDAT => LM_RDAT
);
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => RDAT,
PC => M_PC
);
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_SP => D_WE_SP,
D_RD_O => D_RD_O,
D_WE_O => D_WE_O,
D_LOCK => D_LOCK,
D_IO => D_IO,
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => RST_I,
CE => CE,
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
IMM => C_IMM,
RDAT => RDAT,
ADR => ADR,
MQ => WDAT,
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
CE <= ACK_I or not EXTERN;
TGA_O(0) <= T2 and C_IO;
WE_O <= T2 and C_WE_O;
STB_O <= EXTERN;
CYC_O <= EXTERN;
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
-- write enable/select signal (debug)
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
DAT_O <= WDAT;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (RST_I = '1') then T2 <= '0';
elsif (CE = '1') then T2 <= not T2;
end if;
end if;
end process;
process(T2, M_PC, ADR, C_IO, C_RD_O, C_WE_O)
begin
if (T2 = '0') then -- opcode fetch
EXTERN <= M_PC(15) or M_PC(14) or M_PC(13); -- 8Kx8 internal memory
-- A EXTERN <= M_PC(15) or M_PC(14) or M_PC(13) or -- 512x8 internal memory
-- A M_PC(12) or M_PC(11) or M_PC(10) or M_PC(9)
-- B EXTERN <= '1'; -- no internal memory
else -- data or I/O
EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 8Kx8 internal memory
-- A EXTERN <= (ADR(15) or ADR(14) or ADR(13) or -- 512x8 internal memory
-- A ADR(12) or ADR(11) or ADR(10) or ADR(9) or
-- B EXTERN <= ('1' or -- no internal memory
C_IO) and (C_RD_O or C_WE_O);
end if;
end process;
-- remember whether access is to internal or to external (incl I/O) memory.
-- clock read data to XM_OPCODE in T1 or to XM_RDAT in T2
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CE = '1') then
if (T2 = '0') then
OPCS <= EXTERN;
XM_OPC <= DAT_I;
else
RDATS <= EXTERN;
XM_RDAT <= DAT_I;
end if;
end if;
end if;
end process;
M_OPC <= LM_OPC when (OPCS = '0') else XM_OPC;
ADR_O <= M_PC when (T2 = '0') else ADR;
RDAT <= LM_RDAT when (RDATS = '0') else XM_RDAT;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
C_IO <= '0';
C_RD_O <= '0';
C_WE_O <= '0';
LM_WE <= '0';
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
C_IO <= D_IO;
C_RD_O <= D_RD_O;
C_WE_O <= D_WE_O;
LM_WE <= D_WE_O and not D_IO;
end if;
end process;
process(CLK_I, RST_I) -- nuovo (thanks to Riccardo Cerulli-Irelli)
begin
if (RST_I = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
C_IMM <= X"FFFF";
elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode... PORTATO FUORI
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end process;
end Behavioral;
| mit | de973bbcb2ed74761a7eba74d6e071fb | 0.551077 | 2.450614 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/buttons/single_button.vhd | 1 | 1,004 | -- Implement pressed/toggled detection for a single button
library ieee;
use ieee.std_logic_1164.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.button_pkg.all;
entity single_button is
generic(
the_char : lowercase_enum
);
port(
ctrl : in ctrl_t;
rx_data : in ascii_vector;
new_data : in std_logic;
pressed : out std_logic;
toggle : out std_logic
);
end;
architecture rtl of single_button is
constant the_char_vec : ascii_vector := to_ascii_vector(the_char);
signal toggle_int : std_logic;
begin
gen_outputs : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
pressed <= '0';
toggle_int <= '0';
else
pressed <= '0';
if new_data = '1' and the_char_vec = rx_data then
pressed <= '1';
toggle_int <= not toggle_int;
end if;
end if;
end if;
end process;
toggle <= toggle_int;
end;
| bsd-2-clause | 7c33c8f36864dff9250949f66df27bde | 0.609562 | 3.313531 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/uart.vhd | 1 | 1,637 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart is
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic;
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
end uart;
architecture Behavioral of uart is
COMPONENT uart_tx
PORT( CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : IN std_logic;
DATA : IN std_logic_vector(7 downto 0);
DATA_FLAG : IN std_logic;
SER_OUT : OUT std_logic;
DATA_FLAGQ : OUT std_logic
);
END COMPONENT;
COMPONENT uart_rx
PORT( CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : IN std_logic;
SER_IN : IN std_logic;
DATA : OUT std_logic_vector(7 downto 0);
DATA_FLAG : OUT std_logic
);
END COMPONENT;
begin
tx: uart_tx
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
DATA => TX_DATA,
DATA_FLAG => TX_FLAG,
SER_OUT => TX_SEROUT,
DATA_FLAGQ => TX_FLAGQ
);
rx: uart_rx
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
DATA => RX_DATA,
SER_IN => RX_SERIN,
DATA_FLAG => RX_FLAG
);
end Behavioral;
| mit | ae7cb4a7a4db7865123de3c93e41626c | 0.570556 | 2.746644 | false | false | false | false |
tommylommykins/logipi-midi-player | tb/spi/spi_tx_ram_controller_tb.vhd | 1 | 3,763 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
entity spi_tx_ram_controller_tb is
end;
architecture behavioural of spi_tx_ram_controller_tb is
signal ctrl : ctrl_t;
signal fpga_to_mcu_data_latched : std_logic := '0';
signal contents_count : integer := 0;
signal tx_header_byte : std_logic;
signal header_byte : std_logic_vector(7 downto 0);
signal dequeue : std_logic;
signal request_more_data : std_logic;
signal tb_location : character;
begin
spi_tx_ram_controller_1 : entity work.spi_tx_ram_controller
generic map (
block_size => 5)
port map (
ctrl => ctrl,
fpga_to_mcu_data_latched => fpga_to_mcu_data_latched,
contents_count => contents_count,
tx_header_byte => tx_header_byte,
header_byte => header_byte,
dequeue => dequeue,
request_more_data => request_more_data);
-- Clock process definitions
clk_process : process
begin
ctrl.clk <= '0';
wait for clk_period/2;
ctrl.clk <= '1';
wait for clk_period/2;
end process;
stim_proc : process
impure function errmsg(instr : in string) return string is
begin
return character'image(tb_location) & " " & instr;
end;
procedure strobe_fpga_to_mcu_data_latched is
begin
wait until falling_edge(ctrl.clk);
fpga_to_mcu_data_latched <= '1';
wait until falling_edge(ctrl.clk);
fpga_to_mcu_data_latched <= '0';
end;
begin
ctrl.reset_n <= '0';
wait for 1 ms;
-- Check reset values
tb_location <= 'a';
assert tx_header_byte = '0' report errmsg("tx_header_byte");
assert header_byte = "00000000" report errmsg("tx_header_byte");
assert dequeue = '0' report errmsg("dequeue");
assert request_more_data = '0' report errmsg ("request_more_data");
ctrl.reset_n <= '1';
wait for 1 us;
tb_location <= 'b';
-- Check transmit zeroes if contents_count is 0.
assert tx_header_byte = '1' report errmsg("tx_header_byte");
assert header_byte = "00000000" report errmsg("header_byte");
wait until falling_edge(ctrl.clk);
strobe_fpga_to_mcu_data_latched;
tb_location <= 'c';
assert tx_header_byte = '1' report errmsg("tx_header_byte");
assert header_byte = "00000000" report errmsg("header_byte");
strobe_fpga_to_mcu_data_latched;
-- Check that if there is one item, then two bytes are transmitted.
tb_location <= 'd';
contents_count <= 1;
wait for 3 * clk_period;
assert tx_header_byte = '1' report errmsg("tx_header_byte");
assert header_byte = "00000001" report errmsg("header_byte");
tb_location <= 'e';
strobe_fpga_to_mcu_data_latched;
assert tx_header_byte = '1' report errmsg("tx_header_byte");
assert header_byte = "00000001" report errmsg("header_byte");
-- Check that the controller is asking for data to be transmitted.
tb_location <= 'f';
strobe_fpga_to_mcu_data_latched;
assert tx_header_byte = '0' report errmsg("tx_header_byte");
-- Check that after the msg is finished transmitting, then it goes back to
-- txing empty headers.
tb_location <= 'g';
contents_count <= 0;
strobe_fpga_to_mcu_data_latched;
assert tx_header_byte = '1' report errmsg("tx_header_byte");
assert header_byte = "00000000" report errmsg("header_byte");
for i in 0 to 20 loop
contents_count <= contents_count + 1;
wait for 150 ns;
strobe_fpga_to_mcu_data_latched;
end loop;
wait;
end process;
end;
| bsd-2-clause | 798d0c533fe7a3b8afec798227abfbbe | 0.622376 | 3.523408 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/clock_multiplier.vhd | 1 | 2,176 | -- In order to avoid compiling simlibs for this device, this file is unused
library ieee;
use ieee.std_logic_1164.all;
--library unisim;
--use unisim.vcomponents.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
entity clock_multiplier is
port(
clk_in : in std_logic;
clk_out : out std_logic
);
end;
architecture rtl of clock_multiplier is
begin
-- DCM_CLKGEN: Digital Clock Manager
-- Spartan-6
-- Xilinx HDL Libraries Guide, version 14.7
--DCM_CLKGEN_inst : DCM_CLKGEN
-- generic map (
-- CLKFXDV_DIVIDE => 2, -- CLKFXDV divide value (2, 4, 8, 16, 32)
-- CLKFX_DIVIDE => 1, -- Divide value - D - (1-256)
-- CLKFX_MD_MAX => 2.0, -- Specify maximum M/D ratio for timing anlysis
-- CLKFX_MULTIPLY => 2, -- Multiply value - M - (2-256)
-- CLKIN_PERIOD => 20.0, -- Input clock period specified in nS
-- SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
-- -- -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
-- STARTUP_WAIT => true -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
-- )
-- port map (
-- CLKFX => clk_out, -- 1-bit output: Generated clock output
-- CLKFX180 => open, -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
-- CLKFXDV => open, -- 1-bit output: Divided clock output
-- LOCKED => open, -- 1-bit output: Locked output
-- PROGDONE => open, -- 1-bit output: Active high output to indicate the successful re-programming
-- STATUS => open, -- 2-bit output: DCM_CLKGEN status
-- CLKIN => clk_in, -- 1-bit input: Input clock
-- FREEZEDCM => '1', -- 1-bit input: Prevents frequency adjustments to input clock
-- PROGCLK => '0', -- 1-bit input: Clock input for M/D reconfiguration
-- PROGDATA => '0', -- 1-bit input: Serial data input for M/D reconfiguration
-- PROGEN => '0', -- 1-bit input: Active high program enable
-- RST => '0' -- 1-bit input: Reset input pin
-- );
end;
| bsd-2-clause | 49b22299ab7b271af89c7eea9f6797ea | 0.594669 | 3.373643 | false | true | false | false |
willtmwu/vhdlExamples | Moving Averager/datapath_controller.vhd | 1 | 894 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity datapath_controller is
Port ( window_ctrl : in STD_LOGIC_VECTOR(1 downto 0);
masterReset : in STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR(5 downto 0);
window_val : OUT std_logic_vector(1 downto 0);
overflow : IN std_logic;
clk : in STD_LOGIC
);
end datapath_controller;
architecture Behavioral of datapath_controller is
signal counter : std_logic_vector (5 downto 0) := (others => '0');
begin
mem_addr <= counter;
process (masterReset, clk ) begin
if (masterReset = '1') then
counter <= (others => '0');
window_val <= "01";
elsif (clk'event and clk = '1') then
counter <= counter + '1';
window_val <= window_ctrl;
end if;
end process;
end Behavioral;
| apache-2.0 | 5d4f83228fa41eaddbbd4b93d37e513e | 0.631991 | 3.104167 | false | false | false | false |
timtian090/Playground | UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/tinyalu.vhd | 1 | 4,337 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity tinyalu is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done : out std_logic;
result : out unsigned ( 15 downto 0 )
);
-- Declarations
end tinyalu;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
architecture rtl of tinyalu is
-- Architecture declarations
-- Internal signal declarations
signal done_aax : std_logic;
signal done_mult : std_logic;
signal result_aax : unsigned(15 downto 0);
signal result_mult : unsigned(15 downto 0);
signal start_single : std_logic; -- Start signal for single cycle ops
signal start_mult : std_logic; -- start signal for multiply
-- Implicit buffer signal declarations
signal done_internal : std_logic;
-- Component Declarations
-- pragma synthesis_off
component assertions
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
done : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic
);
end component;
-- pragma synthesis_on
component single_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
end component;
component three_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
reset_n : in std_logic;
start : in std_logic;
done_mult : out std_logic;
result_mult : out unsigned (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : assertions use entity work.assertions;
for all : single_cycle use entity work.single_cycle;
for all : three_cycle use entity work.three_cycle;
-- pragma synthesis_on
begin
-- purpose: This block shunts the start signal to the correct block.
-- The multiply only sees the start signal when op(2) is '1'
-- type : combinational
-- inputs : op(2),start
-- outputs: start_mult, start_single
start_demux: process (op(2),start)
begin -- process start_demux
case op(2) is
when '0' =>
start_single <= start;
start_mult <= '0';
when '1' =>
start_single <= '0';
start_mult <= start;
when others => null;
end case;
end process start_demux;
result_mux : process(result_aax, result_mult, op)
begin
case op(2) is
when '0'|'L' => result <= result_aax;
when '1'|'H' => result <= result_mult;
when others => result <= (others => 'X');
end case;
end process result_mux;
done_mux : process(done_aax, done_mult, op)
begin
case op(2) is
when '0'|'L' => done_internal <= done_aax;
when '1'|'H' => done_internal <= done_mult;
when others => done_internal <= 'X';
end case;
end process done_mux;
-- Instance port mappings.
-- pragma synthesis_off
firewall : assertions
port map (
A => A,
B => B,
clk => clk,
done => done_internal,
op => op,
reset_n => reset_n,
start => start);
-- pragma synthesis_on
add_and_xor : single_cycle
port map (
A => A,
B => B,
clk => clk,
op => op,
reset_n => reset_n,
start => start_single,
done_aax => done_aax,
result_aax => result_aax
);
mult : three_cycle
port map (
A => A,
B => B,
clk => clk,
reset_n => reset_n,
start => start_mult,
done_mult => done_mult,
result_mult => result_mult
);
-- Implicit buffered output assignments
done <= done_internal;
end rtl;
| mit | 88b033d4a860c8acb46da3cfbe5f3914 | 0.551533 | 3.614167 | false | false | false | false |
tommylommykins/logipi-midi-player | hdl/spi/ram.vhd | 1 | 1,420 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity ram is
generic(
depth : integer;
width : integer
);
port(
ctrl : in ctrl_t;
read_addr : in unsigned(integer(ceil(log2(real(depth)))) -1 downto 0);
next_write_addr : in unsigned(integer(ceil(log2(real(depth)))) -1 downto 0);
write_enable : in std_logic;
write_in : in std_logic_vector(width - 1 downto 0);
read_out : out std_logic_vector(width - 1 downto 0)
);
end;
--synthesize a dual port block ram
architecture rtl of ram is
type ram_type is array (0 to depth - 1) of std_logic_vector (width - 1 downto 0);
-- This signal is preinitialized as zeroes to remove simulation warnings..
-- we don't actually need to zero this.
--
-- also when simulating under xst, if a warning 3035 is generated relating to
-- size mismatch which may cause simulation errors, this is because depth is
-- not a power of 2.
signal ram : ram_type := (others => (others => '0'));
begin
ram_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if write_enable = '1' then
ram(to_integer(next_write_addr)) <= write_in;
end if;
read_out <= ram(to_integer(read_addr));
end if;
end process;
end;
| bsd-2-clause | b18d3279557c45ef866ec4f86ebfcb6f | 0.65 | 3.372922 | false | false | false | false |
Main-Project-MEC/Systolic-Processor-On-FPGA | Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/bin_to_7segment.vhd | 3 | 3,761 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bin_to_7segment is
Port( CLK_I : in std_logic;
PC : in std_logic_vector(15 downto 0);
SEG1 : out std_logic_vector(7 downto 1);
SEG2 : out std_logic_vector(7 downto 0));
end bin_to_7segment;
architecture Behavioral of bin_to_7segment is
-- +------- middle upper
-- |+------- right upper
-- ||+------ right lower
-- |||+----- middle lower
-- ||||+---- left lower
-- |||||+--- left upper
-- ||||||+-- middle middle
-- |||||||
constant LEDV_0 : std_logic_vector(6 downto 0):= "1111110";-- 0
constant LEDV_1 : std_logic_vector(6 downto 0):= "0110000";-- 1
constant LEDV_2 : std_logic_vector(6 downto 0):= "1101101";-- 2
constant LEDV_3 : std_logic_vector(6 downto 0):= "1111001";-- 3
constant LEDV_4 : std_logic_vector(6 downto 0):= "0110011";-- 4
constant LEDV_5 : std_logic_vector(6 downto 0):= "1011011";-- 5
constant LEDV_6 : std_logic_vector(6 downto 0):= "1011111";-- 6
constant LEDV_7 : std_logic_vector(6 downto 0):= "1110000";-- 7
constant LEDV_8 : std_logic_vector(6 downto 0):= "1111111";-- 8
constant LEDV_9 : std_logic_vector(6 downto 0):= "1111011";-- 9
constant LEDV_A : std_logic_vector(6 downto 0):= "1110111";-- A
constant LEDV_b : std_logic_vector(6 downto 0):= "0011111";-- b
constant LEDV_C : std_logic_vector(6 downto 0):= "1001110";-- C
constant LEDV_d : std_logic_vector(6 downto 0):= "0111101";-- d
constant LEDV_E : std_logic_vector(6 downto 0):= "1001111";-- E
constant LEDV_F : std_logic_vector(6 downto 0):= "1000111";-- F
signal LED_CNT : std_logic_vector(25 downto 0);
signal LED_VAL : std_logic_vector(15 downto 0);
begin
process(CLK_I)
variable LED4H, LED4L : std_logic_vector(3 downto 0);
begin
if (rising_edge(CLK_I)) then
if (LED_CNT(25) = '0') then
LED4H := LED_VAL( 7 downto 4);
LED4L := LED_VAL( 3 downto 0);
else
LED4H := LED_VAL(15 downto 12);
LED4L := LED_VAL(11 downto 8);
end if;
if (LED_CNT = 0) then LED_VAL <= PC; end if;
LED_CNT <= LED_CNT + 1;
case LED4H is
when X"0" => SEG1 <= LEDV_0;
when X"1" => SEG1 <= LEDV_1;
when X"2" => SEG1 <= LEDV_2;
when X"3" => SEG1 <= LEDV_3;
when X"4" => SEG1 <= LEDV_4;
when X"5" => SEG1 <= LEDV_5;
when X"6" => SEG1 <= LEDV_6;
when X"7" => SEG1 <= LEDV_7;
when X"8" => SEG1 <= LEDV_8;
when X"9" => SEG1 <= LEDV_9;
when X"A" => SEG1 <= LEDV_A;
when X"B" => SEG1 <= LEDV_b;
when X"C" => SEG1 <= LEDV_c;
when X"D" => SEG1 <= LEDV_d;
when X"E" => SEG1 <= LEDV_E;
when others => SEG1 <= LEDV_F;
end case;
case LED4L is
when X"0" => SEG2(7 downto 1) <= LEDV_0;
when X"1" => SEG2(7 downto 1) <= LEDV_1;
when X"2" => SEG2(7 downto 1) <= LEDV_2;
when X"3" => SEG2(7 downto 1) <= LEDV_3;
when X"4" => SEG2(7 downto 1) <= LEDV_4;
when X"5" => SEG2(7 downto 1) <= LEDV_5;
when X"6" => SEG2(7 downto 1) <= LEDV_6;
when X"7" => SEG2(7 downto 1) <= LEDV_7;
when X"8" => SEG2(7 downto 1) <= LEDV_8;
when X"9" => SEG2(7 downto 1) <= LEDV_9;
when X"A" => SEG2(7 downto 1) <= LEDV_A;
when X"B" => SEG2(7 downto 1) <= LEDV_b;
when X"C" => SEG2(7 downto 1) <= LEDV_c;
when X"D" => SEG2(7 downto 1) <= LEDV_d;
when X"E" => SEG2(7 downto 1) <= LEDV_E;
when others => SEG2(7 downto 1) <= LEDV_F;
end case;
SEG2(0) <= LED_CNT(25);
end if;
end process;
end Behavioral;
| mit | 7e6a2acde7896863bab83be032d53a56 | 0.570327 | 2.519089 | false | false | false | false |
zambreno/RCL | sccCyGraph/vhdl/scc.vhd | 1 | 39,114 | library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
-- use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity scc is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- SCC Parameters
color_in : in std_logic_vector(63 downto 0); -- Color all nodes in the SCC with that color
scc_addr_in : in std_logic_vector(63 downto 0);
nextv_out : out std_logic_vector(63 downto 0); -- Possible start node for next SCC
-- Graph/ReversedGraph Pointers
n_in : in std_logic_vector(63 downto 0);
graph_info_in : in std_logic_vector(63 downto 0);
rgraph_info_in : in std_logic_vector(63 downto 0);
-- Reach queues pointers
fw_addr_in : in std_logic_vector(63 downto 0);
fw_count_in : in std_logic_vector(63 downto 0);
bw_addr_in : in std_logic_vector(63 downto 0);
bw_count_in : in std_logic_vector(63 downto 0);
-- ae-to-ae signals
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
nxtae_rx_data : in std_logic_vector(31 downto 0);
nxtae_rx_vld : in std_logic;
prvae_rx_data : in std_logic_vector(31 downto 0);
prvae_rx_vld : in std_logic;
nxtae_tx_data : out std_logic_vector(31 downto 0);
nxtae_tx_vld : out std_logic;
prvae_tx_data : out std_logic_vector(31 downto 0);
prvae_tx_vld : out std_logic;
-- MC0 port signals
mc0_req_ld : out std_logic;
mc0_req_st : out std_logic;
mc0_req_size : out std_logic_vector(1 downto 0);
mc0_req_vaddr : out std_logic_vector(47 downto 0);
mc0_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc0_req_flush : out std_logic;
mc0_rd_rq_stall : in std_logic;
mc0_wr_rq_stall : in std_logic;
mc0_rsp_push : in std_logic;
mc0_rsp_stall : out std_logic;
mc0_rsp_data : in std_logic_vector(63 downto 0);
mc0_rsp_rdctl : in std_logic_vector(31 downto 0);
mc0_rsp_flush_cmplt : in std_logic;
-- MC1 port signals
mc1_req_ld : out std_logic;
mc1_req_st : out std_logic;
mc1_req_size : out std_logic_vector(1 downto 0);
mc1_req_vaddr : out std_logic_vector(47 downto 0);
mc1_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc1_req_flush : out std_logic;
mc1_rd_rq_stall : in std_logic;
mc1_wr_rq_stall : in std_logic;
mc1_rsp_push : in std_logic;
mc1_rsp_stall : out std_logic;
mc1_rsp_data : in std_logic_vector(63 downto 0);
mc1_rsp_rdctl : in std_logic_vector(31 downto 0);
mc1_rsp_flush_cmplt : in std_logic;
-- MC2 port signals
mc2_req_ld : out std_logic;
mc2_req_st : out std_logic;
mc2_req_size : out std_logic_vector(1 downto 0);
mc2_req_vaddr : out std_logic_vector(47 downto 0);
mc2_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc2_req_flush : out std_logic;
mc2_rd_rq_stall : in std_logic;
mc2_wr_rq_stall : in std_logic;
mc2_rsp_push : in std_logic;
mc2_rsp_stall : out std_logic;
mc2_rsp_data : in std_logic_vector(63 downto 0);
mc2_rsp_rdctl : in std_logic_vector(31 downto 0);
mc2_rsp_flush_cmplt : in std_logic;
-- MC3 port signals
mc3_req_ld : out std_logic;
mc3_req_st : out std_logic;
mc3_req_size : out std_logic_vector(1 downto 0);
mc3_req_vaddr : out std_logic_vector(47 downto 0);
mc3_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc3_req_flush : out std_logic;
mc3_rd_rq_stall : in std_logic;
mc3_wr_rq_stall : in std_logic;
mc3_rsp_push : in std_logic;
mc3_rsp_stall : out std_logic;
mc3_rsp_data : in std_logic_vector(63 downto 0);
mc3_rsp_rdctl : in std_logic_vector(31 downto 0);
mc3_rsp_flush_cmplt : in std_logic;
-- MC4 port signals
mc4_req_ld : out std_logic;
mc4_req_st : out std_logic;
mc4_req_size : out std_logic_vector(1 downto 0);
mc4_req_vaddr : out std_logic_vector(47 downto 0);
mc4_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc4_req_flush : out std_logic;
mc4_rd_rq_stall : in std_logic;
mc4_wr_rq_stall : in std_logic;
mc4_rsp_push : in std_logic;
mc4_rsp_stall : out std_logic;
mc4_rsp_data : in std_logic_vector(63 downto 0);
mc4_rsp_rdctl : in std_logic_vector(31 downto 0);
mc4_rsp_flush_cmplt : in std_logic;
-- MC5 port signals
mc5_req_ld : out std_logic;
mc5_req_st : out std_logic;
mc5_req_size : out std_logic_vector(1 downto 0);
mc5_req_vaddr : out std_logic_vector(47 downto 0);
mc5_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc5_req_flush : out std_logic;
mc5_rd_rq_stall : in std_logic;
mc5_wr_rq_stall : in std_logic;
mc5_rsp_push : in std_logic;
mc5_rsp_stall : out std_logic;
mc5_rsp_data : in std_logic_vector(63 downto 0);
mc5_rsp_rdctl : in std_logic_vector(31 downto 0);
mc5_rsp_flush_cmplt : in std_logic;
-- MC6 port signals
mc6_req_ld : out std_logic;
mc6_req_st : out std_logic;
mc6_req_size : out std_logic_vector(1 downto 0);
mc6_req_vaddr : out std_logic_vector(47 downto 0);
mc6_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc6_req_flush : out std_logic;
mc6_rd_rq_stall : in std_logic;
mc6_wr_rq_stall : in std_logic;
mc6_rsp_push : in std_logic;
mc6_rsp_stall : out std_logic;
mc6_rsp_data : in std_logic_vector(63 downto 0);
mc6_rsp_rdctl : in std_logic_vector(31 downto 0);
mc6_rsp_flush_cmplt : in std_logic;
-- MC7 port signals
mc7_req_ld : out std_logic;
mc7_req_st : out std_logic;
mc7_req_size : out std_logic_vector(1 downto 0);
mc7_req_vaddr : out std_logic_vector(47 downto 0);
mc7_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc7_req_flush : out std_logic;
mc7_rd_rq_stall : in std_logic;
mc7_wr_rq_stall : in std_logic;
mc7_rsp_push : in std_logic;
mc7_rsp_stall : out std_logic;
mc7_rsp_data : in std_logic_vector(63 downto 0);
mc7_rsp_rdctl : in std_logic_vector(31 downto 0);
mc7_rsp_flush_cmplt : in std_logic;
-- MC8 port signals
mc8_req_ld : out std_logic;
mc8_req_st : out std_logic;
mc8_req_size : out std_logic_vector(1 downto 0);
mc8_req_vaddr : out std_logic_vector(47 downto 0);
mc8_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc8_req_flush : out std_logic;
mc8_rd_rq_stall : in std_logic;
mc8_wr_rq_stall : in std_logic;
mc8_rsp_push : in std_logic;
mc8_rsp_stall : out std_logic;
mc8_rsp_data : in std_logic_vector(63 downto 0);
mc8_rsp_rdctl : in std_logic_vector(31 downto 0);
mc8_rsp_flush_cmplt : in std_logic;
-- MC9 port signals
mc9_req_ld : out std_logic;
mc9_req_st : out std_logic;
mc9_req_size : out std_logic_vector(1 downto 0);
mc9_req_vaddr : out std_logic_vector(47 downto 0);
mc9_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc9_req_flush : out std_logic;
mc9_rd_rq_stall : in std_logic;
mc9_wr_rq_stall : in std_logic;
mc9_rsp_push : in std_logic;
mc9_rsp_stall : out std_logic;
mc9_rsp_data : in std_logic_vector(63 downto 0);
mc9_rsp_rdctl : in std_logic_vector(31 downto 0);
mc9_rsp_flush_cmplt : in std_logic;
-- MC10 port signals
mc10_req_ld : out std_logic;
mc10_req_st : out std_logic;
mc10_req_size : out std_logic_vector(1 downto 0);
mc10_req_vaddr : out std_logic_vector(47 downto 0);
mc10_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc10_req_flush : out std_logic;
mc10_rd_rq_stall : in std_logic;
mc10_wr_rq_stall : in std_logic;
mc10_rsp_push : in std_logic;
mc10_rsp_stall : out std_logic;
mc10_rsp_data : in std_logic_vector(63 downto 0);
mc10_rsp_rdctl : in std_logic_vector(31 downto 0);
mc10_rsp_flush_cmplt: in std_logic;
-- MC11 port signals
mc11_req_ld : out std_logic;
mc11_req_st : out std_logic;
mc11_req_size : out std_logic_vector(1 downto 0);
mc11_req_vaddr : out std_logic_vector(47 downto 0);
mc11_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc11_req_flush : out std_logic;
mc11_rd_rq_stall : in std_logic;
mc11_wr_rq_stall : in std_logic;
mc11_rsp_push : in std_logic;
mc11_rsp_stall : out std_logic;
mc11_rsp_data : in std_logic_vector(63 downto 0);
mc11_rsp_rdctl : in std_logic_vector(31 downto 0);
mc11_rsp_flush_cmplt: in std_logic;
-- MC12 port signals
mc12_req_ld : out std_logic;
mc12_req_st : out std_logic;
mc12_req_size : out std_logic_vector(1 downto 0);
mc12_req_vaddr : out std_logic_vector(47 downto 0);
mc12_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc12_req_flush : out std_logic;
mc12_rd_rq_stall : in std_logic;
mc12_wr_rq_stall : in std_logic;
mc12_rsp_push : in std_logic;
mc12_rsp_stall : out std_logic;
mc12_rsp_data : in std_logic_vector(63 downto 0);
mc12_rsp_rdctl : in std_logic_vector(31 downto 0);
mc12_rsp_flush_cmplt: in std_logic;
-- MC13 port signals
mc13_req_ld : out std_logic;
mc13_req_st : out std_logic;
mc13_req_size : out std_logic_vector(1 downto 0);
mc13_req_vaddr : out std_logic_vector(47 downto 0);
mc13_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc13_req_flush : out std_logic;
mc13_rd_rq_stall : in std_logic;
mc13_wr_rq_stall : in std_logic;
mc13_rsp_push : in std_logic;
mc13_rsp_stall : out std_logic;
mc13_rsp_data : in std_logic_vector(63 downto 0);
mc13_rsp_rdctl : in std_logic_vector(31 downto 0);
mc13_rsp_flush_cmplt: in std_logic;
-- MC14 port signals
mc14_req_ld : out std_logic;
mc14_req_st : out std_logic;
mc14_req_size : out std_logic_vector(1 downto 0);
mc14_req_vaddr : out std_logic_vector(47 downto 0);
mc14_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc14_req_flush : out std_logic;
mc14_rd_rq_stall : in std_logic;
mc14_wr_rq_stall : in std_logic;
mc14_rsp_push : in std_logic;
mc14_rsp_stall : out std_logic;
mc14_rsp_data : in std_logic_vector(63 downto 0);
mc14_rsp_rdctl : in std_logic_vector(31 downto 0);
mc14_rsp_flush_cmplt: in std_logic;
-- MC15 port signals
mc15_req_ld : out std_logic;
mc15_req_st : out std_logic;
mc15_req_size : out std_logic_vector(1 downto 0);
mc15_req_vaddr : out std_logic_vector(47 downto 0);
mc15_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc15_req_flush : out std_logic;
mc15_rd_rq_stall : in std_logic;
mc15_wr_rq_stall : in std_logic;
mc15_rsp_push : in std_logic;
mc15_rsp_stall : out std_logic;
mc15_rsp_data : in std_logic_vector(63 downto 0);
mc15_rsp_rdctl : in std_logic_vector(31 downto 0);
mc15_rsp_flush_cmplt: in std_logic
);
end entity;
architecture arch of scc is
component scc_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
-- kernels communication signals
kernel_tx_vld : out std_logic; -- 1 if found nextv
kernel_tx_nextv : out std_logic_vector(63 downto 0);
kernel_rx_vld : in std_logic;
kernel_rx_nextv : in std_logic_vector(63 downto 0);
-- Input Graph Prameters (Represented in Custom CSR)
N : in std_logic_vector(63 downto 0);
graph_info : in std_logic_vector(63 downto 0);
rgraph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0); -- Color to be used to color nodes
fw_queue : in std_logic_vector(63 downto 0); -- FW Reach queue pointer (could be FW or BW reach queue)
fw_count : in std_logic_vector(63 downto 0); -- Number of nodes in FW reach queue
bw_queue : in std_logic_vector(63 downto 0); -- BW Reach queue pointer (could be FW or BW reach queue)
bw_count : in std_logic_vector(63 downto 0); -- Number of nodes in BW reach queue
scc_results : in std_logic_vector(63 downto 0); -- Where we store the color of each node
-- Parameters for next kernel
nxtk_rst : out std_logic;
nxtk_enable : out std_logic;
nextk_busy : in std_logic;
nextk_done : in std_logic;
nxtk_N : out std_logic_vector(63 downto 0);
nxtk_graph_info : out std_logic_vector(63 downto 0);
nxtk_rgraph_info : out std_logic_vector(63 downto 0);
nxtk_color : out std_logic_vector(63 downto 0);
nxtk_fw_queue : out std_logic_vector(63 downto 0);
nxtk_fw_count : out std_logic_vector(63 downto 0);
nxtk_bw_queue : out std_logic_vector(63 downto 0);
nxtk_bw_count : out std_logic_vector(63 downto 0);
nxtk_scc_results : out std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0);
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic
);
end component;
-- Input signals
signal n : std_logic_vector(63 downto 0);
signal color : std_logic_vector(63 downto 0);
signal scc_addr : std_logic_vector(63 downto 0);
signal graph_info : std_logic_vector(63 downto 0);
signal rgraph_info : std_logic_vector(63 downto 0);
signal fw_addr : std_logic_vector(63 downto 0);
signal fw_count : std_logic_vector(63 downto 0);
signal bw_addr : std_logic_vector(63 downto 0);
signal bw_count : std_logic_vector(63 downto 0);
-- Master Process Signals
signal r_rst : std_logic;
signal r_enable : std_logic;
signal kernels_count : unsigned(7 downto 0) := x"20"; -- 64 kernels = 0x40 , 32 kernels = 0x32
type state is (st_idle, st_start, st_wait, st_busy, st_done);
signal scc_state : state;
-- Kernels control signals
signal kernels_enable : std_logic;
signal kernels_done : std_logic;
signal kernels_busy : std_logic;
-- Kernel-to-kernel communication signals
type array_of_slv64 is array (0 to 15) of std_logic_vector(63 downto 0);
signal kernel_tx_vld : std_logic_vector(15 downto 0);
signal kernel_tx_nextv : array_of_slv64;
signal nxtk_rst : std_logic_vector(15 downto 0);
signal nxtk_enable : std_logic_vector(15 downto 0);
signal nextk_busy : std_logic_vector(15 downto 0);
signal nextk_done : std_logic_vector(15 downto 0);
signal nxtk_N : array_of_slv64;
signal nxtk_graph_info : array_of_slv64;
signal nxtk_rgraph_info : array_of_slv64;
signal nxtk_color : array_of_slv64;
signal nxtk_fw_queue : array_of_slv64;
signal nxtk_fw_count : array_of_slv64;
signal nxtk_bw_queue : array_of_slv64;
signal nxtk_bw_count : array_of_slv64;
signal nxtk_scc_results : array_of_slv64;
signal master_tx_vld : std_logic;
signal master_tx_nextv : std_logic_vector(63 downto 0);
signal k2k_start : std_logic;
signal k0_rx_vld : std_logic;
begin
-- CyGraph Kernel 0
k0 : scc_kernel
port map (
-- control signals
clk => clk,
rst => r_rst,
enable => kernels_enable,
busy => kernels_busy,
done => kernels_done,
-- Kernel Parameters
kernel_id => x"00",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(0),
kernel_tx_nextv => kernel_tx_nextv(0),
kernel_rx_vld => k0_rx_vld,
kernel_rx_nextv => master_tx_nextv,
-- Input Graph Prameters (Represented in Custom CSR)
N => n,
graph_info => graph_info,
rgraph_info => rgraph_info,
-- SCC intersection parameters
color => color,
fw_queue => fw_addr,
fw_count => fw_count,
bw_queue => bw_addr,
bw_count => bw_count,
scc_results => scc_addr,
-- Parameters for next kernel
nxtk_rst => nxtk_rst(0),
nxtk_enable => nxtk_enable(0),
nextk_busy => nextk_busy(0),
nextk_done => nextk_done(0),
nxtk_N => nxtk_N(0),
nxtk_graph_info => nxtk_graph_info(0),
nxtk_rgraph_info => nxtk_rgraph_info(0),
nxtk_color => nxtk_color(0),
nxtk_fw_queue => nxtk_fw_queue(0),
nxtk_fw_count => nxtk_fw_count(0),
nxtk_bw_queue => nxtk_bw_queue(0),
nxtk_bw_count => nxtk_bw_count(0),
nxtk_scc_results => nxtk_scc_results(0),
-- MC0 request port signals
mc_req_ld => mc0_req_ld,
mc_req_st => mc0_req_st,
mc_req_size => mc0_req_size,
mc_req_vaddr => mc0_req_vaddr,
mc_req_wrd_rdctl => mc0_req_wrd_rdctl,
mc_rd_rq_stall => mc0_rd_rq_stall,
mc_wr_rq_stall => mc0_wr_rq_stall,
-- MC0 response port signals
mc_rsp_push => mc0_rsp_push,
mc_rsp_stall => mc0_rsp_stall,
mc_rsp_data => mc0_rsp_data,
mc_rsp_rdctl => mc0_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc0_req_flush,
mc_rsp_flush_cmplt => mc0_rsp_flush_cmplt
);
-- CyGraph Kernel 1
k1 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(0),
enable => nxtk_enable(0),
busy => nextk_busy(0),
done => nextk_done(0),
-- Kernel Parameters
kernel_id => x"01",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(1),
kernel_tx_nextv => kernel_tx_nextv(1),
kernel_rx_vld => kernel_tx_vld(0),
kernel_rx_nextv => kernel_tx_nextv(0),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(0),
graph_info => nxtk_graph_info(0),
rgraph_info => nxtk_rgraph_info(0),
-- SCC intersection parameters
color => nxtk_color(0),
fw_queue => nxtk_fw_queue(0),
fw_count => nxtk_fw_count(0),
bw_queue => nxtk_bw_queue(0),
bw_count => nxtk_bw_count(0),
scc_results => nxtk_scc_results(0),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(1),
nxtk_enable => nxtk_enable(1),
nextk_busy => nextk_busy(1),
nextk_done => nextk_done(1),
nxtk_N => nxtk_N(1),
nxtk_graph_info => nxtk_graph_info(1),
nxtk_rgraph_info => nxtk_rgraph_info(1),
nxtk_color => nxtk_color(1),
nxtk_fw_queue => nxtk_fw_queue(1),
nxtk_fw_count => nxtk_fw_count(1),
nxtk_bw_queue => nxtk_bw_queue(1),
nxtk_bw_count => nxtk_bw_count(1),
nxtk_scc_results => nxtk_scc_results(1),
-- MC1 request port signals
mc_req_ld => mc1_req_ld,
mc_req_st => mc1_req_st,
mc_req_size => mc1_req_size,
mc_req_vaddr => mc1_req_vaddr,
mc_req_wrd_rdctl => mc1_req_wrd_rdctl,
mc_rd_rq_stall => mc1_rd_rq_stall,
mc_wr_rq_stall => mc1_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc1_rsp_push,
mc_rsp_stall => mc1_rsp_stall,
mc_rsp_data => mc1_rsp_data,
mc_rsp_rdctl => mc1_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc1_req_flush,
mc_rsp_flush_cmplt => mc1_rsp_flush_cmplt
);
-- CyGraph Kernel 2
k2 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(1),
enable => nxtk_enable(1),
busy => nextk_busy(1),
done => nextk_done(1),
-- Kernel Parameters
kernel_id => x"02",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(2),
kernel_tx_nextv => kernel_tx_nextv(2),
kernel_rx_vld => kernel_tx_vld(1),
kernel_rx_nextv => kernel_tx_nextv(1),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(1),
graph_info => nxtk_graph_info(1),
rgraph_info => nxtk_rgraph_info(1),
-- SCC intersection parameters
color => nxtk_color(1),
fw_queue => nxtk_fw_queue(1),
fw_count => nxtk_fw_count(1),
bw_queue => nxtk_bw_queue(1),
bw_count => nxtk_bw_count(1),
scc_results => nxtk_scc_results(1),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(2),
nxtk_enable => nxtk_enable(2),
nextk_busy => nextk_busy(2),
nextk_done => nextk_done(2),
nxtk_N => nxtk_N(2),
nxtk_graph_info => nxtk_graph_info(2),
nxtk_rgraph_info => nxtk_rgraph_info(2),
nxtk_color => nxtk_color(2),
nxtk_fw_queue => nxtk_fw_queue(2),
nxtk_fw_count => nxtk_fw_count(2),
nxtk_bw_queue => nxtk_bw_queue(2),
nxtk_bw_count => nxtk_bw_count(2),
nxtk_scc_results => nxtk_scc_results(2),
-- MC2 request port signals
mc_req_ld => mc2_req_ld,
mc_req_st => mc2_req_st,
mc_req_size => mc2_req_size,
mc_req_vaddr => mc2_req_vaddr,
mc_req_wrd_rdctl => mc2_req_wrd_rdctl,
mc_rd_rq_stall => mc2_rd_rq_stall,
mc_wr_rq_stall => mc2_wr_rq_stall,
-- MC2 response port signals
mc_rsp_push => mc2_rsp_push,
mc_rsp_stall => mc2_rsp_stall,
mc_rsp_data => mc2_rsp_data,
mc_rsp_rdctl => mc2_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc2_req_flush,
mc_rsp_flush_cmplt => mc2_rsp_flush_cmplt
);
-- CyGraph Kernel 3
k3 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(2),
enable => nxtk_enable(2),
busy => nextk_busy(2),
done => nextk_done(2),
-- Kernel Parameters
kernel_id => x"03",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(3),
kernel_tx_nextv => kernel_tx_nextv(3),
kernel_rx_vld => kernel_tx_vld(2),
kernel_rx_nextv => kernel_tx_nextv(2),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(2),
graph_info => nxtk_graph_info(2),
rgraph_info => nxtk_rgraph_info(2),
-- SCC intersection parameters
color => nxtk_color(2),
fw_queue => nxtk_fw_queue(2),
fw_count => nxtk_fw_count(2),
bw_queue => nxtk_bw_queue(2),
bw_count => nxtk_bw_count(2),
scc_results => nxtk_scc_results(2),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(3),
nxtk_enable => nxtk_enable(3),
nextk_busy => nextk_busy(3),
nextk_done => nextk_done(3),
nxtk_N => nxtk_N(3),
nxtk_graph_info => nxtk_graph_info(3),
nxtk_rgraph_info => nxtk_rgraph_info(3),
nxtk_color => nxtk_color(3),
nxtk_fw_queue => nxtk_fw_queue(3),
nxtk_fw_count => nxtk_fw_count(3),
nxtk_bw_queue => nxtk_bw_queue(3),
nxtk_bw_count => nxtk_bw_count(3),
nxtk_scc_results => nxtk_scc_results(3),
-- MC3 request port signals
mc_req_ld => mc3_req_ld,
mc_req_st => mc3_req_st,
mc_req_size => mc3_req_size,
mc_req_vaddr => mc3_req_vaddr,
mc_req_wrd_rdctl => mc3_req_wrd_rdctl,
mc_rd_rq_stall => mc3_rd_rq_stall,
mc_wr_rq_stall => mc3_wr_rq_stall,
-- MC3 response port signals
mc_rsp_push => mc3_rsp_push,
mc_rsp_stall => mc3_rsp_stall,
mc_rsp_data => mc3_rsp_data,
mc_rsp_rdctl => mc3_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc3_req_flush,
mc_rsp_flush_cmplt => mc3_rsp_flush_cmplt
);
-- CyGraph Kernel 4
k4 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(3),
enable => nxtk_enable(3),
busy => nextk_busy(3),
done => nextk_done(3),
-- Kernel Parameters
kernel_id => x"04",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(4),
kernel_tx_nextv => kernel_tx_nextv(4),
kernel_rx_vld => kernel_tx_vld(3),
kernel_rx_nextv => kernel_tx_nextv(3),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(3),
graph_info => nxtk_graph_info(3),
rgraph_info => nxtk_rgraph_info(3),
-- SCC intersection parameters
color => nxtk_color(3),
fw_queue => nxtk_fw_queue(3),
fw_count => nxtk_fw_count(3),
bw_queue => nxtk_bw_queue(3),
bw_count => nxtk_bw_count(3),
scc_results => nxtk_scc_results(3),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(4),
nxtk_enable => nxtk_enable(4),
nextk_busy => nextk_busy(4),
nextk_done => nextk_done(4),
nxtk_N => nxtk_N(4),
nxtk_graph_info => nxtk_graph_info(4),
nxtk_rgraph_info => nxtk_rgraph_info(4),
nxtk_color => nxtk_color(4),
nxtk_fw_queue => nxtk_fw_queue(4),
nxtk_fw_count => nxtk_fw_count(4),
nxtk_bw_queue => nxtk_bw_queue(4),
nxtk_bw_count => nxtk_bw_count(4),
nxtk_scc_results => nxtk_scc_results(4),
-- MC4 request port signals
mc_req_ld => mc4_req_ld,
mc_req_st => mc4_req_st,
mc_req_size => mc4_req_size,
mc_req_vaddr => mc4_req_vaddr,
mc_req_wrd_rdctl => mc4_req_wrd_rdctl,
mc_rd_rq_stall => mc4_rd_rq_stall,
mc_wr_rq_stall => mc4_wr_rq_stall,
-- MC4 response port signals
mc_rsp_push => mc4_rsp_push,
mc_rsp_stall => mc4_rsp_stall,
mc_rsp_data => mc4_rsp_data,
mc_rsp_rdctl => mc4_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc4_req_flush,
mc_rsp_flush_cmplt => mc4_rsp_flush_cmplt
);
-- CyGraph Kernel 5
k5 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(4),
enable => nxtk_enable(4),
busy => nextk_busy(4),
done => nextk_done(4),
-- Kernel Parameters
kernel_id => x"05",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(5),
kernel_tx_nextv => kernel_tx_nextv(5),
kernel_rx_vld => kernel_tx_vld(4),
kernel_rx_nextv => kernel_tx_nextv(4),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(4),
graph_info => nxtk_graph_info(4),
rgraph_info => nxtk_rgraph_info(4),
-- SCC intersection parameters
color => nxtk_color(4),
fw_queue => nxtk_fw_queue(4),
fw_count => nxtk_fw_count(4),
bw_queue => nxtk_bw_queue(4),
bw_count => nxtk_bw_count(4),
scc_results => nxtk_scc_results(4),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(5),
nxtk_enable => nxtk_enable(5),
nextk_busy => nextk_busy(5),
nextk_done => nextk_done(5),
nxtk_N => nxtk_N(5),
nxtk_graph_info => nxtk_graph_info(5),
nxtk_rgraph_info => nxtk_rgraph_info(5),
nxtk_color => nxtk_color(5),
nxtk_fw_queue => nxtk_fw_queue(5),
nxtk_fw_count => nxtk_fw_count(5),
nxtk_bw_queue => nxtk_bw_queue(5),
nxtk_bw_count => nxtk_bw_count(5),
nxtk_scc_results => nxtk_scc_results(5),
-- MC1 request port signals
mc_req_ld => mc5_req_ld,
mc_req_st => mc5_req_st,
mc_req_size => mc5_req_size,
mc_req_vaddr => mc5_req_vaddr,
mc_req_wrd_rdctl => mc5_req_wrd_rdctl,
mc_rd_rq_stall => mc5_rd_rq_stall,
mc_wr_rq_stall => mc5_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc5_rsp_push,
mc_rsp_stall => mc5_rsp_stall,
mc_rsp_data => mc5_rsp_data,
mc_rsp_rdctl => mc5_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc5_req_flush,
mc_rsp_flush_cmplt => mc5_rsp_flush_cmplt
);
-- CyGraph Kernel 6
k6 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(5),
enable => nxtk_enable(5),
busy => nextk_busy(5),
done => nextk_done(5),
-- Kernel Parameters
kernel_id => x"06",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(6),
kernel_tx_nextv => kernel_tx_nextv(6),
kernel_rx_vld => kernel_tx_vld(5),
kernel_rx_nextv => kernel_tx_nextv(5),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(5),
graph_info => nxtk_graph_info(5),
rgraph_info => nxtk_rgraph_info(5),
-- SCC intersection parameters
color => nxtk_color(5),
fw_queue => nxtk_fw_queue(5),
fw_count => nxtk_fw_count(5),
bw_queue => nxtk_bw_queue(5),
bw_count => nxtk_bw_count(5),
scc_results => nxtk_scc_results(5),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(6),
nxtk_enable => nxtk_enable(6),
nextk_busy => nextk_busy(6),
nextk_done => nextk_done(6),
nxtk_N => nxtk_N(6),
nxtk_graph_info => nxtk_graph_info(6),
nxtk_rgraph_info => nxtk_rgraph_info(6),
nxtk_color => nxtk_color(6),
nxtk_fw_queue => nxtk_fw_queue(6),
nxtk_fw_count => nxtk_fw_count(6),
nxtk_bw_queue => nxtk_bw_queue(6),
nxtk_bw_count => nxtk_bw_count(6),
nxtk_scc_results => nxtk_scc_results(6),
-- MC6 request port signals
mc_req_ld => mc6_req_ld,
mc_req_st => mc6_req_st,
mc_req_size => mc6_req_size,
mc_req_vaddr => mc6_req_vaddr,
mc_req_wrd_rdctl => mc6_req_wrd_rdctl,
mc_rd_rq_stall => mc6_rd_rq_stall,
mc_wr_rq_stall => mc6_wr_rq_stall,
-- MC6 response port signals
mc_rsp_push => mc6_rsp_push,
mc_rsp_stall => mc6_rsp_stall,
mc_rsp_data => mc6_rsp_data,
mc_rsp_rdctl => mc6_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc6_req_flush,
mc_rsp_flush_cmplt => mc6_rsp_flush_cmplt
);
-- CyGraph Kernel 7
k7 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(6),
enable => nxtk_enable(6),
busy => nextk_busy(6),
done => nextk_done(6),
-- Kernel Parameters
kernel_id => x"07",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(7),
kernel_tx_nextv => kernel_tx_nextv(7),
kernel_rx_vld => kernel_tx_vld(6),
kernel_rx_nextv => kernel_tx_nextv(6),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(6),
graph_info => nxtk_graph_info(6),
rgraph_info => nxtk_rgraph_info(6),
-- SCC intersection parameters
color => nxtk_color(6),
fw_queue => nxtk_fw_queue(6),
fw_count => nxtk_fw_count(6),
bw_queue => nxtk_bw_queue(6),
bw_count => nxtk_bw_count(6),
scc_results => nxtk_scc_results(6),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(7),
nxtk_enable => nxtk_enable(7),
nextk_busy => nextk_busy(7),
nextk_done => nextk_done(7),
nxtk_N => nxtk_N(7),
nxtk_graph_info => nxtk_graph_info(7),
nxtk_rgraph_info => nxtk_rgraph_info(7),
nxtk_color => nxtk_color(7),
nxtk_fw_queue => nxtk_fw_queue(7),
nxtk_fw_count => nxtk_fw_count(7),
nxtk_bw_queue => nxtk_bw_queue(7),
nxtk_bw_count => nxtk_bw_count(7),
nxtk_scc_results => nxtk_scc_results(7),
-- MC7 request port signals
mc_req_ld => mc7_req_ld,
mc_req_st => mc7_req_st,
mc_req_size => mc7_req_size,
mc_req_vaddr => mc7_req_vaddr,
mc_req_wrd_rdctl => mc7_req_wrd_rdctl,
mc_rd_rq_stall => mc7_rd_rq_stall,
mc_wr_rq_stall => mc7_wr_rq_stall,
-- MC7 response port signals
mc_rsp_push => mc7_rsp_push,
mc_rsp_stall => mc7_rsp_stall,
mc_rsp_data => mc7_rsp_data,
mc_rsp_rdctl => mc7_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc7_req_flush,
mc_rsp_flush_cmplt => mc7_rsp_flush_cmplt
);
prvae_tx_vld <= '0';
prvae_tx_data <= (others => '0');
nextk_busy(7) <= '0';
nextk_done(7) <= '1';
nextk_busy(15) <= '0';
nextk_done(15) <= '1';
-- Reset unused MC ports
mc8_req_ld <= '0';
mc8_req_st <= '0';
mc8_req_size <= (others => '0');
mc8_req_vaddr <= (others => '0');
mc8_req_wrd_rdctl <= (others => '0');
mc8_req_flush <= '0';
mc8_rsp_stall <= '0';
mc9_req_ld <= '0';
mc9_req_st <= '0';
mc9_req_size <= (others => '0');
mc9_req_vaddr <= (others => '0');
mc9_req_wrd_rdctl <= (others => '0');
mc9_req_flush <= '0';
mc9_rsp_stall <= '0';
mc10_req_ld <= '0';
mc10_req_st <= '0';
mc10_req_size <= (others => '0');
mc10_req_vaddr <= (others => '0');
mc10_req_wrd_rdctl <= (others => '0');
mc10_req_flush <= '0';
mc10_rsp_stall <= '0';
mc11_req_ld <= '0';
mc11_req_st <= '0';
mc11_req_size <= (others => '0');
mc11_req_vaddr <= (others => '0');
mc11_req_wrd_rdctl <= (others => '0');
mc11_req_flush <= '0';
mc11_rsp_stall <= '0';
mc12_req_ld <= '0';
mc12_req_st <= '0';
mc12_req_size <= (others => '0');
mc12_req_vaddr <= (others => '0');
mc12_req_wrd_rdctl <= (others => '0');
mc12_req_flush <= '0';
mc12_rsp_stall <= '0';
mc13_req_ld <= '0';
mc13_req_st <= '0';
mc13_req_size <= (others => '0');
mc13_req_vaddr <= (others => '0');
mc13_req_wrd_rdctl <= (others => '0');
mc13_req_flush <= '0';
mc13_rsp_stall <= '0';
mc14_req_ld <= '0';
mc14_req_st <= '0';
mc14_req_size <= (others => '0');
mc14_req_vaddr <= (others => '0');
mc14_req_wrd_rdctl <= (others => '0');
mc14_req_flush <= '0';
mc14_rsp_stall <= '0';
mc15_req_ld <= '0';
mc15_req_st <= '0';
mc15_req_size <= (others => '0');
mc15_req_vaddr <= (others => '0');
mc15_req_wrd_rdctl <= (others => '0');
mc15_req_flush <= '0';
mc15_rsp_stall <= '0';
rst_control : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- reset data
r_rst <= '1';
r_enable <= '0';
n <= (others => '0');
color <= (others => '0');
scc_addr <= (others => '0');
graph_info <= (others => '0');
rgraph_info <= (others => '0');
fw_addr <= (others => '0');
fw_count <= (others => '0');
bw_addr <= (others => '0');
bw_count <= (others => '0');
else
r_rst <= '0';
if (enable = '1') then
r_enable <= '1';
n <= n_in;
color <= color_in;
scc_addr <= scc_addr_in;
graph_info <= graph_info_in;
rgraph_info <= rgraph_info_in;
fw_addr <= fw_addr_in;
fw_count <= fw_count_in;
bw_addr <= bw_addr_in;
bw_count <= bw_count_in;
else
r_enable <= '0';
end if;
end if;
end if;
end process;
ae_ae : process (clk, r_rst)
begin
if (rising_edge(clk)) then
if (r_rst = '1') then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
master_tx_nextv <= (others => '0');
nextv_out <= (others => '0');
k0_rx_vld <= '0';
else
-- Control output
if (scc_state = st_start) then
nextv_out <= (others => '0');
elsif (kernel_tx_vld(7) = '1') then
nextv_out <= x"00000000" & std_logic_vector(kernel_tx_nextv(7)(31 downto 0));
end if;
-- Control nxtae_tx_vld, nxtae_tx_data
if (scc_state = st_start or scc_state = st_done or scc_state = st_idle) then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
else
nxtae_tx_vld <= kernel_tx_vld(7);
nxtae_tx_data <= kernel_tx_nextv(7)(31 downto 0);
end if;
-- Control k0_rx_vld, master_tx_nextv
if (scc_state = st_start) then
k0_rx_vld <= '0';
master_tx_nextv <= (others => '0');
else
if (ae_id = "00") then
k0_rx_vld <= master_tx_vld;
if (prvae_rx_vld = '1') then
master_tx_nextv <= x"00000000" & prvae_rx_data(31 downto 0);
end if;
elsif (prvae_rx_vld = '1') then
k0_rx_vld <= '1';
master_tx_nextv <= x"00000000" & prvae_rx_data(31 downto 0);
else
k0_rx_vld <= '0';
end if;
end if;
end if;
end if;
end process; -- ae_ae
master : process(clk, r_rst)
begin
if rising_edge(clk) then
if (r_rst = '1') then
busy <= '0';
done <= '0';
scc_state <= st_idle;
kernels_enable <= '0';
else
case (scc_state) is
when st_idle =>
done <= '0';
if (r_enable = '1') then
busy <= '1';
kernels_enable <= '1'; -- set enable early, to allow k2k process in kernel to work
scc_state <= st_start;
else
busy <= '0';
kernels_enable <= '0';
scc_state <= st_idle;
end if ;
when st_start =>
if (kernels_busy = '0') then
kernels_enable <= '0';
scc_state <= st_wait;
else
scc_state <= st_start;
end if;
when st_wait =>
kernels_enable <= '0';
scc_state <= st_busy;
when st_busy =>
if (kernels_busy = '0') then
scc_state <= st_done;
else
scc_state <= st_busy;
end if;
-- Cygraph is done
when st_done =>
done <= '1';
busy <= '0';
scc_state <= st_idle;
when others =>
scc_state <= st_idle;
end case;
end if; -- end if rst
end if; -- end if clk
end process; -- master
-- Kernel-to-kenrel process
--- Start and control the kernel_tx_vld signals
k2k : process (clk, r_rst)
begin
if (rising_edge(clk)) then
if (r_rst = '1') then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If kernel idle, reset signals
if (scc_state = st_start) then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If the start of the level, issue a vld signal
if (k2k_start = '0') then
master_tx_vld <= '0';
k2k_start <= '1';
else
-- if valid signal, pass it to next kernel in the ring
if (prvae_rx_vld = '1') then
master_tx_vld <= '1';
else
master_tx_vld <= '0';
end if;
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
end architecture;
| apache-2.0 | 202d795c8c0ae166c94779b2f530e86d | 0.575421 | 2.498499 | false | false | false | false |
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