repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
ameyagadkari/portfolio | Other Projects Source Code/FPGABasedVideoGame/game.vhd | 1 | 11,009 | --game.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package game is
procedure brick(signal hpos_scr,vpos_scr,xpos,ypos,ball_x,ball_y: in integer; signal draw:out std_logic;signal r,g,b:out std_logic_vector(3 downto 0); signal coll_x,coll_y:out std_logic;signal ball_x_vel:in std_logic;signal ball_y_vel:in std_logic);
procedure bat(signal hpos_scr,vpos_scr, xpos,ypos:in integer; signal draw:out std_logic; signal r,g,b:out std_logic_vector(3 downto 0));
procedure ball(signal hpos_scr,vpos_scr, ball_x,ball_y:in integer; signal ball_row,ball_col:out integer);
procedure gameover(signal hpos_scr,vpos_scr, gameover_x,gameover_y:in integer; signal gameover_row,gameover_col:out integer);
procedure lives(signal hpos_scr,vpos_scr, lives_x,lives_y:in integer; signal lives_row,lives_col:out integer);
procedure welmes(signal hpos_scr,vpos_scr,welmes_x,welmes_y:in integer; signal welmes_row,welmes_col:out integer);
procedure winmes(signal hpos_scr,vpos_scr,winmes_x,winmes_y:in integer; signal winmes_row,winmes_col:out integer);
procedure paused(signal hpos_scr,vpos_scr,paused_x,paused_y:in integer; signal paused_row,paused_col:out integer);
end game;
package body game is
procedure brick(signal hpos_scr,vpos_scr, xpos,ypos,ball_x,ball_y: in integer; signal draw:out std_logic;signal r,g,b:out std_logic_vector(3 downto 0); signal coll_x,coll_y: out std_logic;signal ball_x_vel:in std_logic; signal ball_y_vel:in std_logic) is--Procedure to assign draw,rgb,collision signals of all bricks
begin
if(hpos_scr>=xpos and hpos_scr<xpos+40 and vpos_scr>=ypos and vpos_scr<ypos+20)then
draw<='1';
r<="1001";
g<="0101";
b<="1101";
else
draw<='0';
r<="0000";
g<="0000";
b<="0000";
end if;
if(ypos=ball_y+12) then --top edge collision detection
if(ball_x>=xpos-9 and ball_x<=xpos+36) then--for other top edge pixel collision change velocity in y alone
coll_y<='1';
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_x>=xpos-14 and ball_x<=xpos-10)then
if(ball_y_vel='1' and ball_x_vel='1')then--if ball is coming down and moving right and colliding with top left corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='1' and ball_x_vel='0')then--if ball is coming down and moving left and colliding with top left corner pixel it should change velocity in y alone
coll_y<='1';
elsif(ball_y_vel='0' and ball_x_vel='1')then--if ball is going up and moving right and colliding with top left corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_x>=xpos+37 and ball_x<=xpos+41)then
if(ball_y_vel='1' and ball_x_vel='0')then--if ball is coming down and moving left and colliding with top right corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='1' and ball_x_vel='1')then--if ball is coming down and moving right and colliding with top right corner pixel it should change velocity in y alone
coll_y<='1';
elsif(ball_y_vel='0' and ball_x_vel='0')then--if ball is going up and moving left and colliding with top right corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
else
null;
end if;
else
null;
end if;
if(ypos+19=ball_y) then --bottom edge collision detection
if(ball_x>=xpos-9 and ball_x<=xpos+36) then--for other bottom edge pixel collision change velocity in y alone
coll_y<='1';
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_x>=xpos-14 and ball_x<=xpos-10)then
if(ball_y_vel='0' and ball_x_vel='1')then--if ball is going up and moving right and colliding with bottom left corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='0' and ball_x_vel='0')then--if ball is going up and moving left and colliding with bottom left corner pixel it should change velocity in y alone
coll_y<='1';
elsif(ball_y_vel='1' and ball_x_vel='1')then--if ball is coming down and moving right and colliding with bottom left corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_x>=xpos+37 and ball_x<=xpos+41)then
if(ball_y_vel='0' and ball_x_vel='0')then--if ball is going up and moving left and colliding with bottom right corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='0' and ball_x_vel='1')then--if ball is going up and moving right and colliding with bottom right corner pixel it should change velocity in y alone
coll_y<='1';
elsif(ball_y_vel='1' and ball_x_vel='0')then--if ball is coming down and moving left and colliding with bottom right corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
else
null;
end if;
else
null;
end if;
if(ball_x>=xpos-15 and ball_x<=xpos-11) then --left edge collision detection
if(ball_y>=ypos-9 and ball_y<=ypos+16) then--for other left edge pixel collision change velocity in x alone
coll_x<='1';
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_y>=ypos-11 and ball_y<=ypos-10)then
if(ball_y_vel='0' and ball_x_vel='1')then--if ball is going up and moving right and colliding with left top corner pixel it should change velocity in x alone
coll_x<='1';
elsif(ball_y_vel='1' and ball_x_vel='1')then--if ball is coming down and moving right and colliding with left top corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_y>=ypos+17 and ball_y<=ypos+18)then
if(ball_y_vel='0' and ball_x_vel='1')then--if ball is going up and moving right and colliding with left bottom corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='1' and ball_x_vel='1')then--if ball is coming down and moving right and colliding with left bottom corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
else
null;
end if;
else
null;
end if;
if(ball_x>=xpos+37 and ball_x<=xpos+41) then --right edge collision detection
if(ball_y>=ypos-9 and ball_y<=ypos+16) then--for other right edge pixel collision change velocity in x alone
coll_x<='1';
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_y>=ypos-11 and ball_y<=ypos-10)then
if(ball_y_vel='1' and ball_x_vel='0')then--if ball is coming down and moving left and colliding with right top corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
elsif(ball_y_vel='0' and ball_x_vel='0')then--if ball is going up and moving left and colliding with right top corner pixel it should change velocity in x alone
coll_x<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
elsif(ball_y>=ypos+17 and ball_y<=ypos+18)then
if(ball_y_vel='1' and ball_x_vel='0')then--if ball is coming down and moving left and colliding with right bottom corner pixel it should change velocity in x alone
coll_x<='1';
elsif(ball_y_vel='0' and ball_x_vel='0')then--if ball is going up and moving left and colliding with right bottom corner pixel it should change velocity in both x & y
coll_x<='1';
coll_y<='1';
else
null;
end if;
draw<='0';
r<="0000";
g<="0000";
b<="0000";
else
null;
end if;
else
null;
end if;
end brick;
procedure bat(signal hpos_scr,vpos_scr, xpos,ypos:in integer; signal draw:out std_logic; signal r,g,b:out std_logic_vector(3 downto 0)) is--Procedure to assign draw,rgb signals of the bat
begin
if(hpos_scr>=xpos and hpos_scr<xpos+50 and vpos_scr>=ypos and vpos_scr<ypos+4)then
draw<='1';
r<="1111";
g<="1111";
b<="1111";
else
draw<='0';
r<="0000";
g<="0000";
b<="0000";
end if;
end bat;
procedure ball(signal hpos_scr,vpos_scr, ball_x,ball_y:in integer; signal ball_row,ball_col:out integer) is--Procedure to map current pixel location to BALL_ROM's row/col
begin
if((ball_x<=hpos_scr) and (hpos_scr<ball_x+13) and (ball_y<=vpos_scr) and (vpos_scr<ball_y+13)) then
ball_row <= vpos_scr - ball_y;
ball_col <= hpos_scr - ball_x;
else
null;
end if;
end ball;
procedure gameover(signal hpos_scr,vpos_scr,gameover_x,gameover_y:in integer; signal gameover_row,gameover_col:out integer) is--Procedure to map current pixel location to GAMEOVER_ROM's row/col
begin
if((gameover_x<=hpos_scr) and (hpos_scr<gameover_x+472) and (gameover_y<=vpos_scr) and (vpos_scr<gameover_y+90)) then
gameover_row <= vpos_scr - gameover_y;
gameover_col <= hpos_scr - gameover_x;
else
null;
end if;
end gameover;
procedure lives(signal hpos_scr,vpos_scr,lives_x,lives_y:in integer; signal lives_row,lives_col:out integer) is--Procedure to map current pixel location to LIVES_ROM's row/col
begin
if((lives_x<=hpos_scr) and (hpos_scr<lives_x+92) and (lives_y<=vpos_scr) and (vpos_scr<lives_y+25)) then
lives_row <= vpos_scr - lives_y;
lives_col <= hpos_scr - lives_x;
else
null;
end if;
end lives;
procedure welmes(signal hpos_scr,vpos_scr,welmes_x,welmes_y:in integer; signal welmes_row,welmes_col:out integer) is--Procedure to map current pixel location to WELCOME_ROM's row/col
begin
if((welmes_x<=hpos_scr) and (hpos_scr<welmes_x+496) and (welmes_y<=vpos_scr) and (vpos_scr<welmes_y+390)) then
welmes_row <= vpos_scr - welmes_y;
welmes_col <= hpos_scr - welmes_x;
else
null;
end if;
end welmes;
procedure winmes(signal hpos_scr,vpos_scr,winmes_x,winmes_y:in integer; signal winmes_row,winmes_col:out integer) is--Procedure to map current pixel location to WIN_ROM's row/col
begin
if((winmes_x<=hpos_scr) and (hpos_scr<winmes_x+460) and (winmes_y<=vpos_scr) and (vpos_scr<winmes_y+130)) then
winmes_row <= vpos_scr - winmes_y;
winmes_col <= hpos_scr - winmes_x;
else
null;
end if;
end winmes;
procedure paused(signal hpos_scr,vpos_scr,paused_x,paused_y:in integer; signal paused_row,paused_col:out integer) is--Procedure to map current pixel location to PAUSE_ROM's row/col
begin
if((paused_x<=hpos_scr) and (hpos_scr<paused_x+384) and (paused_y<=vpos_scr) and (vpos_scr<paused_y+76)) then
paused_row <= vpos_scr - paused_y;
paused_col <= hpos_scr - paused_x;
else
null;
end if;
end paused;
end game; | gpl-2.0 | 6e54e28bbf0253c511e9e9e067254bf2 | 0.665183 | 2.897105 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/peripheral_register.vhd | 1 | 3,019 | -------------------------------------------------------------------------------
-- Title : Peripheral Register
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A single 16-bit register that can be read and written to and
-- from the internal parallel bus.
-------------------------------------------------------------------------------
-- Copyright (c) 2011, 2016
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.reset_pkg.all;
entity peripheral_register is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
RESET_IMPL : reset_type := none
);
port (
dout_p : out std_logic_vector(15 downto 0);
din_p : in std_logic_vector(15 downto 0);
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic
);
end peripheral_register;
-------------------------------------------------------------------------------
architecture behavioral of peripheral_register is
type peripheral_register_type is record
dout : std_logic_vector(15 downto 0);
oreg : std_logic_vector(15 downto 0);
end record;
constant peripheral_register_type_initial : peripheral_register_type := (dout => (others => '0'),
oreg => (others => '0'));
signal r, rin : peripheral_register_type := peripheral_register_type_initial;
begin
bus_o.data <= r.dout;
dout_p <= r.oreg;
comb : process(bus_i.addr, bus_i.data, bus_i.re, bus_i.we, din_p, r)
variable v : peripheral_register_type;
begin
v := r;
-- Default value
v.dout := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.oreg := bus_i.data;
elsif bus_i.re = '1' then
v.dout := din_p;
end if;
end if;
-- sync reset
if RESET_IMPL = sync and reset = '1' then
v := peripheral_register_type_initial;
end if;
rin <= v;
end process comb;
async_reset : if RESET_IMPL = async generate
seq : process (clk, reset) is
begin -- process seq
if reset = '0' then -- asynchronous reset (active low)
r <= peripheral_register_type_initial;
elsif clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
sync_reset : if RESET_IMPL /= async generate
seq : process (clk) is
begin -- process seq
if clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
end behavioral;
| bsd-3-clause | db5a2d301afca3f635f5614526d954ec | 0.501491 | 4.036096 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/commutation.vhd | 2 | 4,703 | -------------------------------------------------------------------------------
-- Title : Commutation control via Hall sensors
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
package commutation_pkg is
component commutation is
port (
driver_stage_p : out bldc_driver_stage_type;
hall_p : in hall_sensor_type;
pwm_p : in half_bridge_type;
dir_p : in std_logic;
sd_p : in std_logic;
clk : in std_logic);
end component commutation;
end commutation_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.commutation_pkg.all;
use work.motor_control_pkg.all;
entity commutation is
port (
driver_stage_p : out bldc_driver_stage_type; -- Driver Stage of 3 half bridges
hall_p : in hall_sensor_type; -- Hall Sensors
pwm_p : in half_bridge_type;
dir_p : in std_logic; -- Direction
sd_p : in std_logic; -- Shutdown
clk : in std_logic
);
end commutation;
architecture behavioral of commutation is
type commutation_type is record
hall_1r : std_logic_vector(2 downto 0);
hall_2r : std_logic_vector(2 downto 0);
driver : bldc_driver_stage_type;
end record;
signal r, rin : commutation_type;
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(dir_p, hall_p.a, hall_p.b, hall_p.c,
pwm_p.high, pwm_p.low, r,
r.hall_1r, r.hall_2r,
r.driver.a.high, r.driver.a.low,
r.driver.b.high, r.driver.b.low,
r.driver.c.high, r.driver.c.low,
sd_p)
variable v : commutation_type;
variable index : integer range 0 to 6;
begin
v := r;
-- synchronise Hall sensors inputs
v.hall_1r := hall_p.a & hall_p.b & hall_p.c;
v.hall_2r := r.hall_1r;
if dir_p = '0' then
case r.hall_2r is
when "101" => index := 1;
when "100" => index := 2;
when "110" => index := 3;
when "010" => index := 4;
when "011" => index := 5;
when "001" => index := 6;
when others => index := 0;
end case;
else
case r.hall_2r is
when "101" => index := 4;
when "100" => index := 5;
when "110" => index := 6;
when "010" => index := 1;
when "011" => index := 2;
when "001" => index := 3;
when others => index := 0;
end case;
end if;
case index is
when 1 =>
v.driver := (a => (pwm_p.high, pwm_p.low),
b => ('0', '1'),
c => ('0', '0'));
when 2 =>
v.driver := (a => (pwm_p.high, pwm_p.low),
b => ('0', '0'),
c => ('0', '1'));
when 3 =>
v.driver := (a => ('0', '0'),
b => (pwm_p.high, pwm_p.low),
c => ('0', '1'));
when 4 =>
v.driver := (a => ('0', '1'),
b => (pwm_p.high, pwm_p.low),
c => ('0', '0'));
when 5 =>
v.driver := (a => ('0', '1'),
b => ('0', '0'),
c => (pwm_p.high, pwm_p.low));
when 6 =>
v.driver := (a => ('0', '0'),
b => ('0', '1'),
c => (pwm_p.high, pwm_p.low));
when others =>
-- Error in the readings of the Hall-Sensors => Disable PWM
v.driver := (a => ('0', '0'),
b => ('0', '0'),
c => ('0', '0'));
end case;
if sd_p = '1' then
v.driver :=
(a => ('0', '0'),
b => ('0', '0'),
c => ('0', '0'));
end if;
rin <= v;
end process comb_proc;
driver_stage_p <= r.driver;
end behavioral;
| bsd-3-clause | e4673208395f92a331fcbbe805f11bca | 0.391878 | 3.771451 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0_1/system_zed_vga_0_0_sim_netlist.vhdl | 1 | 2,133 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_zed_vga_0_0 -prefix
-- system_zed_vga_0_0_ system_zed_vga_0_0_sim_netlist.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_vga_0_0 is
port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_vga_0_0 : entity is "system_zed_vga_0_0,zed_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_vga_0_0 : entity is "zed_vga,Vivado 2016.4";
end system_zed_vga_0_0;
architecture STRUCTURE of system_zed_vga_0_0 is
signal \^rgb565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb565\(15 downto 12) <= rgb565(15 downto 12);
\^rgb565\(10 downto 7) <= rgb565(10 downto 7);
\^rgb565\(4 downto 1) <= rgb565(4 downto 1);
vga_b(3 downto 0) <= \^rgb565\(4 downto 1);
vga_g(3 downto 0) <= \^rgb565\(10 downto 7);
vga_r(3 downto 0) <= \^rgb565\(15 downto 12);
end STRUCTURE;
| mit | 91b9bbeb8b92cc9eac8fb1ee1f98abb2 | 0.631505 | 3.560935 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,932 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | fcfcfa47e6971e5c0926e5b5b51fec00 | 0.532707 | 2.812418 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache-rtl.vhdl | 1 | 18,741 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
library mem;
library tech;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_l1mem_data_cache_replace_pkg.all;
architecture rtl of cpu_l1mem_data_cache is
type comb_type is record
cpu_l1mem_data_cache_ctrl_out_vram : cpu_l1mem_data_cache_ctrl_out_vram_type;
cpu_l1mem_data_cache_ctrl_in_vram : cpu_l1mem_data_cache_ctrl_in_vram_type;
cpu_l1mem_data_cache_dp_out_vram : cpu_l1mem_data_cache_dp_out_vram_type;
cpu_l1mem_data_cache_ctrl_out_mram : cpu_l1mem_data_cache_ctrl_out_mram_type;
cpu_l1mem_data_cache_ctrl_in_mram : cpu_l1mem_data_cache_ctrl_in_mram_type;
cpu_l1mem_data_cache_dp_out_mram : cpu_l1mem_data_cache_dp_out_mram_type;
cpu_l1mem_data_cache_ctrl_out_tram : cpu_l1mem_data_cache_ctrl_out_tram_type;
cpu_l1mem_data_cache_dp_in_tram : cpu_l1mem_data_cache_dp_in_tram_type;
cpu_l1mem_data_cache_dp_out_tram : cpu_l1mem_data_cache_dp_out_tram_type;
cpu_l1mem_data_cache_ctrl_out_dram : cpu_l1mem_data_cache_ctrl_out_dram_type;
cpu_l1mem_data_cache_dp_in_dram : cpu_l1mem_data_cache_dp_in_dram_type;
cpu_l1mem_data_cache_dp_out_dram : cpu_l1mem_data_cache_dp_out_dram_type;
cpu_l1mem_data_cache_dp_in_ctrl : cpu_l1mem_data_cache_dp_in_ctrl_type;
cpu_l1mem_data_cache_dp_out_ctrl : cpu_l1mem_data_cache_dp_out_ctrl_type;
cpu_l1mem_data_cache_replace_ctrl_out : cpu_l1mem_data_cache_replace_ctrl_out_type;
cpu_l1mem_data_cache_replace_ctrl_in : cpu_l1mem_data_cache_replace_ctrl_in_type;
cpu_l1mem_data_cache_replace_dp_in : cpu_l1mem_data_cache_replace_dp_in_type;
cpu_l1mem_data_cache_replace_dp_out : cpu_l1mem_data_cache_replace_dp_out_type;
cpu_l1mem_data_cache_ctrl_out : cpu_l1mem_data_cache_ctrl_out_type;
cpu_l1mem_data_cache_dp_out : cpu_l1mem_data_cache_dp_out_type;
sys_master_ctrl_out : sys_master_ctrl_out_type;
sys_master_dp_out : sys_master_dp_out_type;
end record;
signal c : comb_type;
begin
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_none |
cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store |
cpu_l1mem_data_request_code_invalidate |
cpu_l1mem_data_request_code_flush |
cpu_l1mem_data_request_code_writeback |
cpu_l1mem_data_request_code_sync =>
null;
when others =>
assert false
report "cpu_l1mem_data_cache_ctrl_in.request invalid"
severity failure;
end case;
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.cacheen)
report "cpu_l1mem_data_cache_ctrl_in.cacheen invalid"
severity failure;
when others =>
null;
end case;
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store |
cpu_l1mem_data_request_code_invalidate |
cpu_l1mem_data_request_code_flush |
cpu_l1mem_data_request_code_writeback =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.mmuen)
report "cpu_l1mem_data_cache_ctrl_in.mmuen invalid"
severity failure;
when others =>
null;
end case;
if cpu_l1mem_data_cache_ctrl_in.cacheen = '1' then
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.be)
report "cpu_l1mem_data_cache_ctrl_in.alloc invalid"
severity failure;
assert not is_x(cpu_l1mem_data_cache_ctrl_in.alloc)
report "cpu_l1mem_data_cache_ctrl_in.alloc invalid"
severity failure;
assert not is_x(cpu_l1mem_data_cache_ctrl_in.writethrough)
report "cpu_l1mem_data_cache_ctrl_in.writethrough invalid"
severity failure;
when others =>
null;
end case;
end if;
end if;
end process;
-- pragma translate_on
ctrl : entity work.cpu_l1mem_data_cache_ctrl(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_ctrl_in => cpu_mmu_data_ctrl_in,
cpu_mmu_data_ctrl_out => cpu_mmu_data_ctrl_out,
cpu_l1mem_data_cache_ctrl_out => c.cpu_l1mem_data_cache_ctrl_out,
cpu_l1mem_data_cache_ctrl_in => cpu_l1mem_data_cache_ctrl_in,
sys_master_ctrl_out => c.sys_master_ctrl_out,
sys_slave_ctrl_out => sys_slave_ctrl_out,
cpu_l1mem_data_cache_ctrl_out_vram => c.cpu_l1mem_data_cache_ctrl_out_vram,
cpu_l1mem_data_cache_ctrl_in_vram => c.cpu_l1mem_data_cache_ctrl_in_vram,
cpu_l1mem_data_cache_ctrl_out_mram => c.cpu_l1mem_data_cache_ctrl_out_mram,
cpu_l1mem_data_cache_ctrl_in_mram => c.cpu_l1mem_data_cache_ctrl_in_mram,
cpu_l1mem_data_cache_ctrl_out_tram => c.cpu_l1mem_data_cache_ctrl_out_tram,
cpu_l1mem_data_cache_ctrl_out_dram => c.cpu_l1mem_data_cache_ctrl_out_dram,
cpu_l1mem_data_cache_dp_in_ctrl => c.cpu_l1mem_data_cache_dp_in_ctrl,
cpu_l1mem_data_cache_dp_out_ctrl => c.cpu_l1mem_data_cache_dp_out_ctrl,
cpu_l1mem_data_cache_replace_ctrl_in => c.cpu_l1mem_data_cache_replace_ctrl_in,
cpu_l1mem_data_cache_replace_ctrl_out => c.cpu_l1mem_data_cache_replace_ctrl_out
);
cpu_l1mem_data_cache_ctrl_out <= c.cpu_l1mem_data_cache_ctrl_out;
sys_master_ctrl_out <= c.sys_master_ctrl_out;
dp : entity work.cpu_l1mem_data_cache_dp(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_dp_in => cpu_mmu_data_dp_in,
cpu_mmu_data_dp_out => cpu_mmu_data_dp_out,
cpu_l1mem_data_cache_dp_out => c.cpu_l1mem_data_cache_dp_out,
cpu_l1mem_data_cache_dp_in => cpu_l1mem_data_cache_dp_in,
sys_master_dp_out => c.sys_master_dp_out,
sys_slave_dp_out => sys_slave_dp_out,
cpu_l1mem_data_cache_dp_out_vram => c.cpu_l1mem_data_cache_dp_out_vram,
cpu_l1mem_data_cache_dp_out_mram => c.cpu_l1mem_data_cache_dp_out_mram,
cpu_l1mem_data_cache_dp_out_tram => c.cpu_l1mem_data_cache_dp_out_tram,
cpu_l1mem_data_cache_dp_in_tram => c.cpu_l1mem_data_cache_dp_in_tram,
cpu_l1mem_data_cache_dp_out_dram => c.cpu_l1mem_data_cache_dp_out_dram,
cpu_l1mem_data_cache_dp_in_dram => c.cpu_l1mem_data_cache_dp_in_dram,
cpu_l1mem_data_cache_dp_in_ctrl => c.cpu_l1mem_data_cache_dp_in_ctrl,
cpu_l1mem_data_cache_dp_out_ctrl => c.cpu_l1mem_data_cache_dp_out_ctrl,
cpu_l1mem_data_cache_replace_dp_in => c.cpu_l1mem_data_cache_replace_dp_in,
cpu_l1mem_data_cache_replace_dp_out => c.cpu_l1mem_data_cache_replace_dp_out
);
cpu_l1mem_data_cache_dp_out <= c.cpu_l1mem_data_cache_dp_out;
sys_master_dp_out <= c.sys_master_dp_out;
replace : entity work.cpu_l1mem_data_cache_replace(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_l1mem_data_cache_replace_ctrl_out => c.cpu_l1mem_data_cache_replace_ctrl_out,
cpu_l1mem_data_cache_replace_ctrl_in => c.cpu_l1mem_data_cache_replace_ctrl_in,
cpu_l1mem_data_cache_replace_dp_in => c.cpu_l1mem_data_cache_replace_dp_in,
cpu_l1mem_data_cache_replace_dp_out => c.cpu_l1mem_data_cache_replace_dp_out
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_ctrl_in.re)
report "replace re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_replace_ctrl_in.we)
report "replace we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_replace_ctrl_in.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.rindex)
report "replace rindex is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_replace_ctrl_in.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.windex)
report "replace windex is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.wstate)
report "replace wstate is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
vram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
data_bits => cpu_l1mem_data_cache_assoc
)
port map (
clk => clk,
re => c.cpu_l1mem_data_cache_ctrl_out_vram.re,
we => c.cpu_l1mem_data_cache_ctrl_out_vram.we,
raddr => c.cpu_l1mem_data_cache_dp_out_vram.raddr,
rdata => c.cpu_l1mem_data_cache_ctrl_in_vram.rdata,
waddr => c.cpu_l1mem_data_cache_dp_out_vram.waddr,
wdata => c.cpu_l1mem_data_cache_ctrl_out_vram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.re)
report "vram re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.we)
report "vram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_vram.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_vram.raddr)
report "vram raddr is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_ctrl_out_vram.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.wdata)
report "vram wdata is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_vram.waddr)
report "vram waddr is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
mram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
data_bits => cpu_l1mem_data_cache_assoc
)
port map (
clk => clk,
re => c.cpu_l1mem_data_cache_ctrl_out_mram.re,
we => c.cpu_l1mem_data_cache_ctrl_out_mram.we,
raddr => c.cpu_l1mem_data_cache_dp_out_mram.raddr,
rdata => c.cpu_l1mem_data_cache_ctrl_in_mram.rdata,
waddr => c.cpu_l1mem_data_cache_dp_out_mram.waddr,
wdata => c.cpu_l1mem_data_cache_ctrl_out_mram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.re)
report "mram re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.we)
report "mram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_mram.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_mram.raddr)
report "mram raddr is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_ctrl_out_mram.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.wdata)
report "mram wdata is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_mram.waddr)
report "mram waddr is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
tram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
word_bits => cpu_l1mem_data_cache_tag_bits,
log2_banks => cpu_l1mem_data_cache_log2_assoc
)
port map (
clk => clk,
en => c.cpu_l1mem_data_cache_ctrl_out_tram.en,
we => c.cpu_l1mem_data_cache_ctrl_out_tram.we,
banken => c.cpu_l1mem_data_cache_ctrl_out_tram.banken,
addr => c.cpu_l1mem_data_cache_dp_out_tram.addr,
rdata => c.cpu_l1mem_data_cache_dp_in_tram.rdata,
wdata => c.cpu_l1mem_data_cache_dp_out_tram.wdata
);
-- pragma translate_on
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.en)
report "tram en is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_tram.en = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_tram.addr)
report "tram addr is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.banken)
report "tram banken is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.we)
report "tram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_tram.we = '1' then
for n in cpu_l1mem_data_cache_assoc-1 downto 0 loop
if c.cpu_l1mem_data_cache_ctrl_out_tram.banken(n) = '1' then
assert not is_x(std_ulogic_vector2_slice2(c.cpu_l1mem_data_cache_dp_out_tram.wdata, n))
report "tram wdata " & integer'image(n) & " is invalid"
severity failure;
end if;
end loop;
end if;
end if;
end if;
end process;
-- pragma translate_on
dram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits + cpu_l1mem_data_cache_offset_bits - cpu_log2_word_bytes,
word_bits => byte_bits,
log2_banks => cpu_l1mem_data_cache_log2_assoc + cpu_log2_word_bytes
)
port map (
clk => clk,
en => c.cpu_l1mem_data_cache_ctrl_out_dram.en,
we => c.cpu_l1mem_data_cache_ctrl_out_dram.we,
banken => c.cpu_l1mem_data_cache_dp_out_dram.banken,
addr => c.cpu_l1mem_data_cache_dp_out_dram.addr,
rdata => c.cpu_l1mem_data_cache_dp_in_dram.rdata,
wdata => c.cpu_l1mem_data_cache_dp_out_dram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_dram.en)
report "dram en is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_dram.en = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_dram.addr)
report "dram addr is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_dram.banken)
report "dram banken is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_dram.we)
report "dram we is invalid"
severity failure;
--if c.cpu_l1mem_data_cache_ctrl_out_dram.we = '1' then
-- for n in cpu_l1mem_data_cache_assoc-1 downto 0 loop
-- if c.cpu_l1mem_data_cache_ctrl_out_tram.banken(n) = '1' then
-- assert not is_x(std_ulogic_vector2_slice2(c.cpu_l1mem_data_cache_dp_out_dram.wdata, n))
-- report "dram wdata " & integer'image(n) & " is invalid"
-- severity failure;
-- end if;
-- end loop;
--end if;
end if;
end if;
end process;
-- pragma translate_on
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(sys_slave_ctrl_out.ready)
report "sys_slave_ctrl_out.ready invalid"
severity failure;
if sys_slave_ctrl_out.ready = '1' then
assert not is_x(sys_slave_ctrl_out.error)
report "sys_slave_ctrl_out.error invalid"
severity failure;
end if;
assert not is_x(c.sys_master_ctrl_out.request)
report "sys_master_ctrl_out.request invalid"
severity failure;
if c.sys_master_ctrl_out.request = '1' then
assert not is_x(c.sys_master_ctrl_out.be)
report "sys_master_ctrl_out.be invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.write)
report "sys_master_ctrl_out.write invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.cacheable)
report "sys_master_ctrl_out.cacheable invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.inst)
report "sys_master_ctrl_out.inst invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.burst)
report "sys_master_ctrl_out.burst invalid"
severity failure;
if c.sys_master_ctrl_out.burst = '1' then
assert not is_x(c.sys_master_ctrl_out.bwrap)
report "sys_master_ctrl_out.bwrap invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.bcycles)
report "sys_master_ctrl_out.bcycles invalid"
severity failure;
end if;
assert not is_x(c.sys_master_dp_out.paddr)
report "sys_master_dp_out.paddr invalid"
severity failure;
assert not is_x(c.sys_master_dp_out.size)
report "sys_master_dp_out.size invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
end;
| apache-2.0 | 660c1890f60fcd5bf87fe86e04af6fb5 | 0.614855 | 2.957393 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/test_cdma/test_cdma.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 21,231 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 02:21:04 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
M_AXIS_MM2S_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_MM2S_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_MM2S_STS_tlast : out STD_LOGIC;
M_AXIS_MM2S_STS_tready : in STD_LOGIC;
M_AXIS_MM2S_STS_tvalid : out STD_LOGIC;
M_AXIS_MM2S_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_MM2S_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIS_MM2S_tlast : out STD_LOGIC;
M_AXIS_MM2S_tready : in STD_LOGIC;
M_AXIS_MM2S_tvalid : out STD_LOGIC;
M_AXIS_S2MM_STS_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_S2MM_STS_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXIS_S2MM_STS_tlast : out STD_LOGIC;
M_AXIS_S2MM_STS_tready : in STD_LOGIC;
M_AXIS_S2MM_STS_tvalid : out STD_LOGIC;
M_AXI_MM2S_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_MM2S_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_arready : in STD_LOGIC;
M_AXI_MM2S_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_MM2S_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_MM2S_arvalid : out STD_LOGIC;
M_AXI_MM2S_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_MM2S_rlast : in STD_LOGIC;
M_AXI_MM2S_rready : out STD_LOGIC;
M_AXI_MM2S_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_MM2S_rvalid : in STD_LOGIC;
M_AXI_S2MM_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_S2MM_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awready : in STD_LOGIC;
M_AXI_S2MM_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_S2MM_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_awvalid : out STD_LOGIC;
M_AXI_S2MM_bready : out STD_LOGIC;
M_AXI_S2MM_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_S2MM_bvalid : in STD_LOGIC;
M_AXI_S2MM_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_S2MM_wlast : out STD_LOGIC;
M_AXI_S2MM_wready : in STD_LOGIC;
M_AXI_S2MM_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_S2MM_wvalid : out STD_LOGIC;
S_AXIS_MM2S_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_MM2S_CMD_tready : out STD_LOGIC;
S_AXIS_MM2S_CMD_tvalid : in STD_LOGIC;
S_AXIS_S2MM_CMD_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
S_AXIS_S2MM_CMD_tready : out STD_LOGIC;
S_AXIS_S2MM_CMD_tvalid : in STD_LOGIC;
S_AXIS_S2MM_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_S2MM_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIS_S2MM_tlast : in STD_LOGIC;
S_AXIS_S2MM_tready : out STD_LOGIC;
S_AXIS_S2MM_tvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
mm2s_err : out STD_LOGIC;
s2mm_err : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=2,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_axi_datamover_0_0 is
port (
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_mm2s_aresetn : in STD_LOGIC;
mm2s_err : out STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : in STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : in STD_LOGIC;
s_axis_mm2s_cmd_tvalid : in STD_LOGIC;
s_axis_mm2s_cmd_tready : out STD_LOGIC;
s_axis_mm2s_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
m_axis_mm2s_sts_tvalid : out STD_LOGIC;
m_axis_mm2s_sts_tready : in STD_LOGIC;
m_axis_mm2s_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_mm2s_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_sts_tlast : out STD_LOGIC;
m_axi_mm2s_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tlast : out STD_LOGIC;
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
m_axi_s2mm_aresetn : in STD_LOGIC;
s2mm_err : out STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : in STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : in STD_LOGIC;
s_axis_s2mm_cmd_tvalid : in STD_LOGIC;
s_axis_s2mm_cmd_tready : out STD_LOGIC;
s_axis_s2mm_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
m_axis_s2mm_sts_tvalid : out STD_LOGIC;
m_axis_s2mm_sts_tready : in STD_LOGIC;
m_axis_s2mm_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_s2mm_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_s2mm_sts_tlast : out STD_LOGIC;
m_axi_s2mm_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tlast : in STD_LOGIC;
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC
);
end component system_axi_datamover_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_0;
signal S_AXIS_MM2S_CMD_1_TDATA : STD_LOGIC_VECTOR ( 71 downto 0 );
signal S_AXIS_MM2S_CMD_1_TREADY : STD_LOGIC;
signal S_AXIS_MM2S_CMD_1_TVALID : STD_LOGIC;
signal S_AXIS_S2MM_1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXIS_S2MM_1_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXIS_S2MM_1_TLAST : STD_LOGIC;
signal S_AXIS_S2MM_1_TREADY : STD_LOGIC;
signal S_AXIS_S2MM_1_TVALID : STD_LOGIC;
signal S_AXIS_S2MM_CMD_1_TDATA : STD_LOGIC_VECTOR ( 71 downto 0 );
signal S_AXIS_S2MM_CMD_1_TREADY : STD_LOGIC;
signal S_AXIS_S2MM_CMD_1_TVALID : STD_LOGIC;
signal aclk_1 : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_STS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_datamover_0_M_AXIS_MM2S_STS_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_datamover_0_M_AXIS_MM2S_STS_TLAST : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_STS_TREADY : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_STS_TVALID : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_datamover_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_datamover_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_datamover_0_M_AXIS_S2MM_STS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_datamover_0_M_AXIS_S2MM_STS_TKEEP : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_datamover_0_M_AXIS_S2MM_STS_TLAST : STD_LOGIC;
signal axi_datamover_0_M_AXIS_S2MM_STS_TREADY : STD_LOGIC;
signal axi_datamover_0_M_AXIS_S2MM_STS_TVALID : STD_LOGIC;
signal axi_datamover_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_datamover_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARUSER : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_datamover_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_datamover_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_datamover_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_datamover_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWUSER : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_datamover_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_datamover_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_datamover_0_mm2s_err : STD_LOGIC;
signal axi_datamover_0_s2mm_err : STD_LOGIC;
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXIS_MM2S_STS_tdata(7 downto 0) <= axi_datamover_0_M_AXIS_MM2S_STS_TDATA(7 downto 0);
M_AXIS_MM2S_STS_tkeep(0) <= axi_datamover_0_M_AXIS_MM2S_STS_TKEEP(0);
M_AXIS_MM2S_STS_tlast <= axi_datamover_0_M_AXIS_MM2S_STS_TLAST;
M_AXIS_MM2S_STS_tvalid <= axi_datamover_0_M_AXIS_MM2S_STS_TVALID;
M_AXIS_MM2S_tdata(31 downto 0) <= axi_datamover_0_M_AXIS_MM2S_TDATA(31 downto 0);
M_AXIS_MM2S_tkeep(3 downto 0) <= axi_datamover_0_M_AXIS_MM2S_TKEEP(3 downto 0);
M_AXIS_MM2S_tlast <= axi_datamover_0_M_AXIS_MM2S_TLAST;
M_AXIS_MM2S_tvalid <= axi_datamover_0_M_AXIS_MM2S_TVALID;
M_AXIS_S2MM_STS_tdata(7 downto 0) <= axi_datamover_0_M_AXIS_S2MM_STS_TDATA(7 downto 0);
M_AXIS_S2MM_STS_tkeep(0) <= axi_datamover_0_M_AXIS_S2MM_STS_TKEEP(0);
M_AXIS_S2MM_STS_tlast <= axi_datamover_0_M_AXIS_S2MM_STS_TLAST;
M_AXIS_S2MM_STS_tvalid <= axi_datamover_0_M_AXIS_S2MM_STS_TVALID;
M_AXI_MM2S_araddr(31 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARADDR(31 downto 0);
M_AXI_MM2S_arburst(1 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARBURST(1 downto 0);
M_AXI_MM2S_arcache(3 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARCACHE(3 downto 0);
M_AXI_MM2S_arid(3 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARID(3 downto 0);
M_AXI_MM2S_arlen(7 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARLEN(7 downto 0);
M_AXI_MM2S_arprot(2 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARPROT(2 downto 0);
M_AXI_MM2S_arsize(2 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARSIZE(2 downto 0);
M_AXI_MM2S_aruser(3 downto 0) <= axi_datamover_0_M_AXI_MM2S_ARUSER(3 downto 0);
M_AXI_MM2S_arvalid <= axi_datamover_0_M_AXI_MM2S_ARVALID;
M_AXI_MM2S_rready <= axi_datamover_0_M_AXI_MM2S_RREADY;
M_AXI_S2MM_awaddr(31 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWADDR(31 downto 0);
M_AXI_S2MM_awburst(1 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWBURST(1 downto 0);
M_AXI_S2MM_awcache(3 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWCACHE(3 downto 0);
M_AXI_S2MM_awid(3 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWID(3 downto 0);
M_AXI_S2MM_awlen(7 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWLEN(7 downto 0);
M_AXI_S2MM_awprot(2 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWPROT(2 downto 0);
M_AXI_S2MM_awsize(2 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWSIZE(2 downto 0);
M_AXI_S2MM_awuser(3 downto 0) <= axi_datamover_0_M_AXI_S2MM_AWUSER(3 downto 0);
M_AXI_S2MM_awvalid <= axi_datamover_0_M_AXI_S2MM_AWVALID;
M_AXI_S2MM_bready <= axi_datamover_0_M_AXI_S2MM_BREADY;
M_AXI_S2MM_wdata(31 downto 0) <= axi_datamover_0_M_AXI_S2MM_WDATA(31 downto 0);
M_AXI_S2MM_wlast <= axi_datamover_0_M_AXI_S2MM_WLAST;
M_AXI_S2MM_wstrb(3 downto 0) <= axi_datamover_0_M_AXI_S2MM_WSTRB(3 downto 0);
M_AXI_S2MM_wvalid <= axi_datamover_0_M_AXI_S2MM_WVALID;
S_AXIS_MM2S_CMD_1_TDATA(71 downto 0) <= S_AXIS_MM2S_CMD_tdata(71 downto 0);
S_AXIS_MM2S_CMD_1_TVALID <= S_AXIS_MM2S_CMD_tvalid;
S_AXIS_MM2S_CMD_tready <= S_AXIS_MM2S_CMD_1_TREADY;
S_AXIS_S2MM_1_TDATA(31 downto 0) <= S_AXIS_S2MM_tdata(31 downto 0);
S_AXIS_S2MM_1_TKEEP(3 downto 0) <= S_AXIS_S2MM_tkeep(3 downto 0);
S_AXIS_S2MM_1_TLAST <= S_AXIS_S2MM_tlast;
S_AXIS_S2MM_1_TVALID <= S_AXIS_S2MM_tvalid;
S_AXIS_S2MM_CMD_1_TDATA(71 downto 0) <= S_AXIS_S2MM_CMD_tdata(71 downto 0);
S_AXIS_S2MM_CMD_1_TVALID <= S_AXIS_S2MM_CMD_tvalid;
S_AXIS_S2MM_CMD_tready <= S_AXIS_S2MM_CMD_1_TREADY;
S_AXIS_S2MM_tready <= S_AXIS_S2MM_1_TREADY;
aclk_1 <= aclk;
axi_datamover_0_M_AXIS_MM2S_STS_TREADY <= M_AXIS_MM2S_STS_tready;
axi_datamover_0_M_AXIS_MM2S_TREADY <= M_AXIS_MM2S_tready;
axi_datamover_0_M_AXIS_S2MM_STS_TREADY <= M_AXIS_S2MM_STS_tready;
axi_datamover_0_M_AXI_MM2S_ARREADY <= M_AXI_MM2S_arready;
axi_datamover_0_M_AXI_MM2S_RDATA(31 downto 0) <= M_AXI_MM2S_rdata(31 downto 0);
axi_datamover_0_M_AXI_MM2S_RLAST <= M_AXI_MM2S_rlast;
axi_datamover_0_M_AXI_MM2S_RRESP(1 downto 0) <= M_AXI_MM2S_rresp(1 downto 0);
axi_datamover_0_M_AXI_MM2S_RVALID <= M_AXI_MM2S_rvalid;
axi_datamover_0_M_AXI_S2MM_AWREADY <= M_AXI_S2MM_awready;
axi_datamover_0_M_AXI_S2MM_BRESP(1 downto 0) <= M_AXI_S2MM_bresp(1 downto 0);
axi_datamover_0_M_AXI_S2MM_BVALID <= M_AXI_S2MM_bvalid;
axi_datamover_0_M_AXI_S2MM_WREADY <= M_AXI_S2MM_wready;
mm2s_err <= axi_datamover_0_mm2s_err;
s2mm_err <= axi_datamover_0_s2mm_err;
axi_datamover_0: component system_axi_datamover_0_0
port map (
m_axi_mm2s_aclk => aclk_1,
m_axi_mm2s_araddr(31 downto 0) => axi_datamover_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_datamover_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_datamover_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_aresetn => vdd_dout(0),
m_axi_mm2s_arid(3 downto 0) => axi_datamover_0_M_AXI_MM2S_ARID(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_datamover_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_datamover_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_datamover_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_datamover_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_aruser(3 downto 0) => axi_datamover_0_M_AXI_MM2S_ARUSER(3 downto 0),
m_axi_mm2s_arvalid => axi_datamover_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_datamover_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_datamover_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_datamover_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_datamover_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_datamover_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => aclk_1,
m_axi_s2mm_aresetn => vdd_dout(0),
m_axi_s2mm_awaddr(31 downto 0) => axi_datamover_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_datamover_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_datamover_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awid(3 downto 0) => axi_datamover_0_M_AXI_S2MM_AWID(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_datamover_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_datamover_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_datamover_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_datamover_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awuser(3 downto 0) => axi_datamover_0_M_AXI_S2MM_AWUSER(3 downto 0),
m_axi_s2mm_awvalid => axi_datamover_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_datamover_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_datamover_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_datamover_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_datamover_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_datamover_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_datamover_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_datamover_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_datamover_0_M_AXI_S2MM_WVALID,
m_axis_mm2s_cmdsts_aclk => aclk_1,
m_axis_mm2s_cmdsts_aresetn => vdd_dout(0),
m_axis_mm2s_sts_tdata(7 downto 0) => axi_datamover_0_M_AXIS_MM2S_STS_TDATA(7 downto 0),
m_axis_mm2s_sts_tkeep(0) => axi_datamover_0_M_AXIS_MM2S_STS_TKEEP(0),
m_axis_mm2s_sts_tlast => axi_datamover_0_M_AXIS_MM2S_STS_TLAST,
m_axis_mm2s_sts_tready => axi_datamover_0_M_AXIS_MM2S_STS_TREADY,
m_axis_mm2s_sts_tvalid => axi_datamover_0_M_AXIS_MM2S_STS_TVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_datamover_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_datamover_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_datamover_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_datamover_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_datamover_0_M_AXIS_MM2S_TVALID,
m_axis_s2mm_cmdsts_aresetn => vdd_dout(0),
m_axis_s2mm_cmdsts_awclk => aclk_1,
m_axis_s2mm_sts_tdata(7 downto 0) => axi_datamover_0_M_AXIS_S2MM_STS_TDATA(7 downto 0),
m_axis_s2mm_sts_tkeep(0) => axi_datamover_0_M_AXIS_S2MM_STS_TKEEP(0),
m_axis_s2mm_sts_tlast => axi_datamover_0_M_AXIS_S2MM_STS_TLAST,
m_axis_s2mm_sts_tready => axi_datamover_0_M_AXIS_S2MM_STS_TREADY,
m_axis_s2mm_sts_tvalid => axi_datamover_0_M_AXIS_S2MM_STS_TVALID,
mm2s_err => axi_datamover_0_mm2s_err,
s2mm_err => axi_datamover_0_s2mm_err,
s_axis_mm2s_cmd_tdata(71 downto 0) => S_AXIS_MM2S_CMD_1_TDATA(71 downto 0),
s_axis_mm2s_cmd_tready => S_AXIS_MM2S_CMD_1_TREADY,
s_axis_mm2s_cmd_tvalid => S_AXIS_MM2S_CMD_1_TVALID,
s_axis_s2mm_cmd_tdata(71 downto 0) => S_AXIS_S2MM_CMD_1_TDATA(71 downto 0),
s_axis_s2mm_cmd_tready => S_AXIS_S2MM_CMD_1_TREADY,
s_axis_s2mm_cmd_tvalid => S_AXIS_S2MM_CMD_1_TVALID,
s_axis_s2mm_tdata(31 downto 0) => S_AXIS_S2MM_1_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => S_AXIS_S2MM_1_TKEEP(3 downto 0),
s_axis_s2mm_tlast => S_AXIS_S2MM_1_TLAST,
s_axis_s2mm_tready => S_AXIS_S2MM_1_TREADY,
s_axis_s2mm_tvalid => S_AXIS_S2MM_1_TVALID
);
vdd: component system_xlconstant_0_0
port map (
dout(0) => vdd_dout(0)
);
end STRUCTURE;
| mit | d2794ee89a1b80214c88a2afa5769b2c | 0.668033 | 2.508981 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_1rw-rtl.vhdl | 1 | 3,510 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_1rw is
constant assoc : natural := 2**log2_assoc;
type comb_type is record
tag_en : std_ulogic;
tag_we : std_ulogic;
tag_banken : std_ulogic_vector(assoc-1 downto 0);
tag_addr : std_ulogic_vector(index_bits-1 downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
data_en : std_ulogic;
data_we : std_ulogic;
data_banken : std_ulogic_vector(assoc-1 downto 0);
data_addr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_en <= en and tagen;
c.tag_we <= we;
c.tag_banken <= way;
c.tag_addr <= index;
c.data_en <= en and dataen;
c.data_we <= we;
c.data_addr <= index & offset;
c.data_banken <= way;
way_loop : for n in assoc-1 downto 0 generate
tag_bit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
end generate;
data_bit_loop : for m in word_bits-1 downto 0 generate
c.data_wdata(n, m) <= wdata(m);
end generate;
end generate;
rtag <= c.tag_rdata;
rdata <= c.data_rdata;
tag_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
en => c.tag_en,
we => c.tag_we,
banken => c.tag_banken,
addr => c.tag_addr,
wdata => c.tag_wdata,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits + offset_bits,
word_bits => word_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
en => c.data_en,
we => c.data_we,
banken => c.data_banken,
addr => c.data_addr,
wdata => c.data_wdata,
rdata => c.data_rdata
);
end;
| apache-2.0 | dceca22812a1f4281a13305485f135b5 | 0.548148 | 3.6074 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_uart_tx_tb.vhd | 2 | 2,203 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_uart_tx"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_tx_tb is
end entity imotor_uart_tx_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_uart_tx_tb is
-- component generics
-- Component ports
-- clock
signal clk : std_logic := '1';
signal start : std_logic := '0'; -- Start signal for transmission
signal imotor_clock : imotor_timer_type;
begin -- architecture behavourial
-- component instantiation
imotor_timer : entity work.imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 1E6,
SEND_FREQUENCY => 1E3)
port map (
clock_out_p => imotor_clock,
clk => clk);
DUT : entity work.imotor_uart_tx
generic map (
START_BITS => 1,
DATA_BITS => 8,
STOP_BITS => 1,
PARITY => Odd)
port map (
data_in_p => "00101100",
start_in_p => start,
clock_tx_in_p => imotor_clock.tx,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
wait for 0.5 us;
start <= '1';
wait until clk = '1';
start <= '0';
wait for 10 us;
start <= '1';
wait until false;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | 198d594a94d88042c04ec988136ee05e | 0.415797 | 4.961712 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_1r1w.vhdl | 1 | 2,454 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Core (SRAMs), 1 read port, 1 write port
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity cache_core_1r1w is
generic (
log2_assoc : natural := 0;
word_bits : natural := 1;
index_bits : natural := 1;
offset_bits : natural := 0;
tag_bits : natural := 1;
write_first : boolean := true
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
we : in std_ulogic;
wway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
wtagen : in std_ulogic;
wdataen : in std_ulogic;
windex : in std_ulogic_vector(index_bits-1 downto 0);
woffset : in std_ulogic_vector(offset_bits-1 downto 0);
wtag : in std_ulogic_vector(tag_bits-1 downto 0);
wdata : in std_ulogic_vector(word_bits-1 downto 0);
re : in std_ulogic;
rway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
rtagen : in std_ulogic;
rdataen : in std_ulogic;
rindex : in std_ulogic_vector(index_bits-1 downto 0);
roffset : in std_ulogic_vector(offset_bits-1 downto 0);
rtag : out std_ulogic_vector2(2**log2_assoc-1 downto 0, tag_bits-1 downto 0);
rdata : out std_ulogic_vector2(2**log2_assoc-1 downto 0, word_bits-1 downto 0)
);
end;
| apache-2.0 | 2862828b9c300a42f40bb8082cf14350 | 0.55216 | 3.964459 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/goertzel_muxes.vhd | 2 | 2,107 | -------------------------------------------------------------------------------
-- Title : Goertel Muxes
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Selects one data word, one coefficient and one input from the
-- arrays of different channels/frequencies. Truely combinatorial.
-- goertzel_pipeline has registers at its inputs.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
entity goertzel_muxes is
generic (
CHANNELS : positive := 12;
FREQUENCIES : positive);
port (
-- control pins of the muxes, from control unit
mux_delay1_p : in std_logic;
mux_delay2_p : in std_logic;
mux_coef : in natural range FREQUENCIES-1 downto 0;
mux_input : in natural range CHANNELS-1 downto 0;
-- data to mux
bram_data : in goertzel_result_type;
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
-- outputs of the mux
delay1_p : out goertzel_data_type;
delay2_p : out goertzel_data_type;
coef_p : out goertzel_coef_type;
input_p : out goertzel_input_type);
end entity goertzel_muxes;
architecture behavourial of goertzel_muxes is
begin -- architecture behavourial
-- be able to blank the input. This is necessary at the beginning of a
-- cycle.
delay1_p <= bram_data(0) when (mux_delay1_p = '1') else (others => '0');
delay2_p <= bram_data(1) when (mux_delay2_p = '1') else (others => '0');
-- select one coefficient from all coefficients
coef_p <= coefs_p(mux_coef);
-- select one input from all inputs
input_p <= inputs_p(mux_input);
end architecture behavourial;
| bsd-3-clause | 29bd63a0c8bd85c50141228244f53868 | 0.524917 | 4.036398 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/synth/system_vga_buffer_0_0.vhd | 1 | 4,630 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "vga_buffer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_buffer_0_0_arch : ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_buffer,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE_POW2=12}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 12
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
| mit | f08c6562136e094abc2f3a22ca37a32a | 0.707127 | 3.58082 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_byte_align.vhd | 1 | 4,108 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 byte aligner
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives raw, unaligned bytes (which could contain part of two actual bytes)
--from the SERDES and aligns them by looking for the D-PHY sync pattern
--When wait_for_sync is high the entity will wait until it sees the valid header at some alignment,
--at which point the found alignment is locked until packet_done is asserted
--valid_data is asserted as soon as the sync pattern is found, so the next byte
--contains the CSI packet header
--In reality to avoid false triggers we must look for a valid sync pattern on all 4 lanes,
--if this does not occur the word aligner (a seperate entity) will assert packet_done immediately
entity csi_rx_byte_align is
port ( clock : in STD_LOGIC; --byte clock in
reset : in STD_LOGIC; --synchronous active high reset
enable : in STD_LOGIC; --active high enable
deser_in : in STD_LOGIC_VECTOR (7 downto 0); --raw data from ISERDES
wait_for_sync : in STD_LOGIC; --when high will look for a sync pattern if sync not already found
packet_done : in STD_LOGIC; --assert to reset synchronisation status
valid_data : out STD_LOGIC; --goes high as soon as sync pattern is found (so data out on next cycle contains header)
data_out : out STD_LOGIC_VECTOR (7 downto 0)); --aligned data out, typically delayed by 2 cycles
end csi_rx_byte_align;
architecture Behavioral of csi_rx_byte_align is
signal curr_byte : std_logic_vector(7 downto 0);
signal last_byte : std_logic_vector(7 downto 0);
signal shifted_byte : std_logic_vector(7 downto 0);
signal found_hdr : std_logic;
signal valid_data_int : std_logic;
signal hdr_offs : unsigned(2 downto 0);
signal data_offs : unsigned(2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
valid_data_int <= '0';
elsif enable = '1' then
last_byte <= curr_byte;
curr_byte <= deser_in;
data_out <= shifted_byte;
if packet_done = '1' then
valid_data_int <= found_hdr;
elsif wait_for_sync = '1' and found_hdr = '1' and valid_data_int = '0' then
valid_data_int <= '1';
data_offs <= hdr_offs;
end if;
end if;
end if;
end process;
valid_data <= valid_data_int;
--This assumes that data is arranged correctly (chronologically last bit in MSB)
--and looks for the "10111000" sync sequence
process(curr_byte, last_byte)
constant sync : std_logic_vector(7 downto 0) := "10111000";
variable was_found : boolean := false;
variable offset : integer range 0 to 7;
begin
offset := 0;
was_found := false;
for i in 0 to 7 loop
if (curr_byte(i downto 0) & last_byte(7 downto i + 1) = sync) and (unsigned(last_byte(i downto 0)) = 0) then
was_found := true;
offset := i;
end if;
end loop;
if was_found then
found_hdr <= '1';
hdr_offs <= to_unsigned(offset, 3);
else
found_hdr <= '0';
hdr_offs <= "000";
end if;
end process;
--This aligns the data correctly
shifted_byte <= curr_byte when data_offs = 7 else
curr_byte(6 downto 0) & last_byte(7 downto 7) when data_offs = 6 else
curr_byte(5 downto 0) & last_byte(7 downto 6) when data_offs = 5 else
curr_byte(4 downto 0) & last_byte(7 downto 5) when data_offs = 4 else
curr_byte(3 downto 0) & last_byte(7 downto 4) when data_offs = 3 else
curr_byte(2 downto 0) & last_byte(7 downto 3) when data_offs = 2 else
curr_byte(1 downto 0) & last_byte(7 downto 2) when data_offs = 1 else
curr_byte(0 downto 0) & last_byte(7 downto 1);
end Behavioral;
| mit | 60673a41353a12ae0f20d310677a8939 | 0.607352 | 3.835668 | false | false | false | false |
sbourdeauducq/dspunit | sim/bench_cpcomplex.vhd | 2 | 12,144 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_cpcomplex is
end bench_cpcomplex;
--=----------------------------------------------------------------------------
architecture archi_bench_cpcomplex of bench_cpcomplex is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_cpcomplex
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
-- init_file => "exsig.mif")
init_file => "exsig_fft.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "exsig_fft.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
s_data_in_cmdreg <= x"0000", x"003F" after 141 ns, x"003F" after 151 ns, x"0464" after 161 ns, x"0002" after 171 ns, -- cp m0->m1
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 141 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_cpcomplex;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=debugfft.sav
-------------------------------------------------------------------------------
| gpl-3.0 | 12802891fb073021a0290b14157a942b | 0.480731 | 3.420845 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_sim_netlist.vhdl | 1 | 30,710 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_sim_netlist.vhdl
-- Design : affine_block_uint_to_ieee754_fp_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
port (
\y[13]\ : out STD_LOGIC;
\y[23]\ : out STD_LOGIC;
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y[22]\ : out STD_LOGIC;
\y[20]\ : out STD_LOGIC;
\y[18]\ : out STD_LOGIC;
\y[22]_0\ : out STD_LOGIC;
\y[22]_1\ : out STD_LOGIC;
\y[21]\ : out STD_LOGIC;
\y[20]_0\ : out STD_LOGIC;
\x_9__s_port_]\ : in STD_LOGIC;
\x[9]_0\ : in STD_LOGIC;
\x[9]_1\ : in STD_LOGIC;
\x[9]_2\ : in STD_LOGIC;
\x[9]_3\ : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
\x[9]_4\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\x[9]_5\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp : entity is "uint_to_ieee754_fp";
end affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
signal mantissa2_carry_i_1_n_0 : STD_LOGIC;
signal mantissa2_carry_i_2_n_0 : STD_LOGIC;
signal mantissa2_carry_i_3_n_0 : STD_LOGIC;
signal mantissa2_carry_i_4_n_0 : STD_LOGIC;
signal mantissa2_carry_n_2 : STD_LOGIC;
signal mantissa2_carry_n_3 : STD_LOGIC;
signal \x_9__s_net_1\ : STD_LOGIC;
signal \^y[13]\ : STD_LOGIC;
signal \y[13]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^y[18]\ : STD_LOGIC;
signal \y[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^y[20]\ : STD_LOGIC;
signal \^y[20]_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \^y[21]\ : STD_LOGIC;
signal \y[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \^y[22]\ : STD_LOGIC;
signal \^y[22]_0\ : STD_LOGIC;
signal \^y[22]_1\ : STD_LOGIC;
signal \^y[23]\ : STD_LOGIC;
signal \y[23]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[27]_INST_0_i_4_n_0\ : STD_LOGIC;
signal NLW_mantissa2_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_mantissa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[14]_INST_0_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[14]_INST_0_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[15]_INST_0_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[16]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_6\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[23]_INST_0_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[30]_INST_0_i_2\ : label is "soft_lutpair1";
begin
\x_9__s_net_1\ <= \x_9__s_port_]\;
\y[13]\ <= \^y[13]\;
\y[18]\ <= \^y[18]\;
\y[20]\ <= \^y[20]\;
\y[20]_0\ <= \^y[20]_0\;
\y[21]\ <= \^y[21]\;
\y[22]\ <= \^y[22]\;
\y[22]_0\ <= \^y[22]_0\;
\y[22]_1\ <= \^y[22]_1\;
\y[23]\ <= \^y[23]\;
mantissa2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => NLW_mantissa2_carry_CO_UNCONNECTED(3 downto 2),
CO(1) => mantissa2_carry_n_2,
CO(0) => mantissa2_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1) => mantissa2_carry_i_1_n_0,
DI(0) => mantissa2_carry_i_2_n_0,
O(3 downto 0) => NLW_mantissa2_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => mantissa2_carry_i_3_n_0,
S(0) => mantissa2_carry_i_4_n_0
);
mantissa2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^y[22]\,
I1 => \^y[20]\,
O => mantissa2_carry_i_1_n_0
);
mantissa2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^y[13]\,
I1 => \^y[23]\,
O => mantissa2_carry_i_2_n_0
);
mantissa2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^y[20]\,
I1 => \^y[22]\,
O => mantissa2_carry_i_3_n_0
);
mantissa2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^y[23]\,
I1 => \^y[13]\,
O => mantissa2_carry_i_4_n_0
);
\y[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888C888888BF"
)
port map (
I0 => \y[14]_INST_0_i_3_n_0\,
I1 => \^y[23]\,
I2 => \y[13]_INST_0_i_1_n_0\,
I3 => \y[14]_INST_0_i_1_n_0\,
I4 => \x[9]_4\,
I5 => \y[14]_INST_0_i_2_n_0\,
O => y(0)
);
\y[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[13]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(6),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[13]_INST_0_i_1_n_0\
);
\y[13]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(4),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(8),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(0),
O => \y[13]_INST_0_i_2_n_0\
);
\y[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFFAB00ABFFABFF"
)
port map (
I0 => \y[15]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_1_n_0\,
I2 => \y[14]_INST_0_i_2_n_0\,
I3 => \^y[23]\,
I4 => \y[14]_INST_0_i_3_n_0\,
I5 => \y[15]_INST_0_i_1_n_0\,
O => y(1)
);
\y[14]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mantissa2_carry_n_2,
I1 => CO(0),
O => \y[14]_INST_0_i_1_n_0\
);
\y[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[14]_INST_0_i_4_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(7),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[14]_INST_0_i_2_n_0\
);
\y[14]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(0),
I3 => \^y[22]\,
O => \y[14]_INST_0_i_3_n_0\
);
\y[14]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(5),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(1),
O => \y[14]_INST_0_i_4_n_0\
);
\y[14]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => O(0),
I2 => mantissa2_carry_n_2,
O => \y[14]_INST_0_i_5_n_0\
);
\y[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[16]_INST_0_i_2_n_0\,
I3 => \y[15]_INST_0_i_1_n_0\,
I4 => \y[16]_INST_0_i_1_n_0\,
I5 => \y[15]_INST_0_i_2_n_0\,
O => y(2)
);
\y[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[15]_INST_0_i_3_n_0\,
I1 => \y[17]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[15]_INST_0_i_1_n_0\
);
\y[15]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(1),
I3 => \^y[22]\,
O => \y[15]_INST_0_i_2_n_0\
);
\y[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(6),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[15]_INST_0_i_3_n_0\
);
\y[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[17]_INST_0_i_2_n_0\,
I3 => \y[16]_INST_0_i_1_n_0\,
I4 => \y[17]_INST_0_i_1_n_0\,
I5 => \y[16]_INST_0_i_2_n_0\,
O => y(3)
);
\y[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[16]_INST_0_i_3_n_0\,
I1 => \y[18]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_1_n_0\
);
\y[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(0),
I1 => \^y[22]\,
I2 => x(2),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_2_n_0\
);
\y[16]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(7),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[16]_INST_0_i_3_n_0\
);
\y[16]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_4_n_0\
);
\y[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[18]_INST_0_i_2_n_0\,
I3 => \y[17]_INST_0_i_1_n_0\,
I4 => \y[18]_INST_0_i_1_n_0\,
I5 => \y[17]_INST_0_i_2_n_0\,
O => y(4)
);
\y[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFBFFFB"
)
port map (
I0 => \y[20]_INST_0_i_4_n_0\,
I1 => x(6),
I2 => \y[21]_INST_0_i_4_n_0\,
I3 => \y[20]_INST_0_i_3_n_0\,
I4 => \y[17]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[17]_INST_0_i_1_n_0\
);
\y[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(1),
I1 => \^y[22]\,
I2 => x(3),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[17]_INST_0_i_2_n_0\
);
\y[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(8),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(4),
O => \y[17]_INST_0_i_3_n_0\
);
\y[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0BFBFBF"
)
port map (
I0 => \y[19]_INST_0_i_2_n_0\,
I1 => \y[18]_INST_0_i_1_n_0\,
I2 => \^y[23]\,
I3 => \y[18]_INST_0_i_2_n_0\,
I4 => \y[19]_INST_0_i_1_n_0\,
O => y(5)
);
\y[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEF0000FFEFFFEF"
)
port map (
I0 => \y[20]_INST_0_i_3_n_0\,
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(7),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => \y[18]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[18]_INST_0_i_1_n_0\
);
\y[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00BFBFFFFFFFFF"
)
port map (
I0 => \^y[22]\,
I1 => x(2),
I2 => \^y[20]\,
I3 => \x[9]_2\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[18]_INST_0_i_2_n_0\
);
\y[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(9),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(5),
O => \y[18]_INST_0_i_3_n_0\
);
\y[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[20]_INST_0_i_2_n_0\,
I3 => \y[19]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_1_n_0\,
I5 => \y[19]_INST_0_i_2_n_0\,
O => y(6)
);
\y[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(6),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(8),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[19]_INST_0_i_1_n_0\
);
\y[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF404000000000"
)
port map (
I0 => \^y[22]\,
I1 => x(3),
I2 => \^y[20]\,
I3 => \x[9]_0\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[19]_INST_0_i_2_n_0\
);
\y[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[21]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_1_n_0\,
O => y(7)
);
\y[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(7),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(9),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[20]_INST_0_i_1_n_0\
);
\y[20]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_2\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_3\,
O => \y[20]_INST_0_i_2_n_0\
);
\y[20]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[20]_INST_0_i_3_n_0\
);
\y[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
O => \y[20]_INST_0_i_4_n_0\
);
\y[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAFFEA00EAFFEAFF"
)
port map (
I0 => \y[21]_INST_0_i_1_n_0\,
I1 => \x_9__s_net_1\,
I2 => mantissa2_carry_n_2,
I3 => \^y[23]\,
I4 => \y[21]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_3_n_0\,
O => y(8)
);
\y[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400044400000000"
)
port map (
I0 => \y[21]_INST_0_i_4_n_0\,
I1 => x(8),
I2 => \^y[22]\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[21]_INST_0_i_1_n_0\
);
\y[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000202020"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => \y[21]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \^y[22]\,
I4 => mantissa2_carry_n_2,
I5 => O(1),
O => \y[21]_INST_0_i_2_n_0\
);
\y[21]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_0\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_1\,
O => \y[21]_INST_0_i_3_n_0\
);
\y[21]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55A9FFFF55A90000"
)
port map (
I0 => p_1_out(0),
I1 => \^y[23]\,
I2 => \^y[18]\,
I3 => \^y[22]_0\,
I4 => mantissa2_carry_n_2,
I5 => O(2),
O => \y[21]_INST_0_i_4_n_0\
);
\y[21]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[21]_INST_0_i_6_n_0\
);
\y[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE222E200000000"
)
port map (
I0 => \x_9__s_net_1\,
I1 => \^y[23]\,
I2 => \x[9]_1\,
I3 => \^y[13]\,
I4 => \x[9]_5\,
I5 => mantissa2_carry_n_2,
O => y(9)
);
\y[22]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
O => \^y[13]\
);
\y[22]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
O => \^y[22]\
);
\y[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => \^y[20]_0\,
I3 => \^y[21]\,
I4 => x(8),
I5 => x(9),
O => \^y[20]\
);
\y[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00005504"
)
port map (
I0 => x(3),
I1 => x(0),
I2 => x(1),
I3 => x(2),
I4 => \y[23]_INST_0_i_1_n_0\,
I5 => \y[23]_INST_0_i_2_n_0\,
O => \^y[23]\
);
\y[23]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => x(5),
I1 => x(9),
I2 => x(7),
O => \y[23]_INST_0_i_1_n_0\
);
\y[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0FFF0F4"
)
port map (
I0 => x(5),
I1 => x(4),
I2 => x(8),
I3 => x(7),
I4 => x(6),
I5 => x(9),
O => \y[23]_INST_0_i_2_n_0\
);
\y[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => \^y[22]_1\,
I1 => \^y[21]\,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => \^y[22]_0\
);
\y[27]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF01"
)
port map (
I0 => \y[27]_INST_0_i_4_n_0\,
I1 => x(7),
I2 => x(6),
I3 => x(9),
I4 => x(8),
O => \^y[18]\
);
\y[27]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(6),
I3 => x(7),
O => \^y[21]\
);
\y[27]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(1),
I1 => x(0),
I2 => x(2),
I3 => x(3),
O => \^y[20]_0\
);
\y[27]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(3),
I3 => x(2),
I4 => x(0),
I5 => x(1),
O => \y[27]_INST_0_i_4_n_0\
);
\y[30]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => x(8),
I1 => x(9),
O => \^y[22]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_uint_to_ieee754_fp_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_uint_to_ieee754_fp_0_1 : entity is "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_uint_to_ieee754_fp_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_uint_to_ieee754_fp_0_1 : entity is "uint_to_ieee754_fp,Vivado 2016.4";
end affine_block_uint_to_ieee754_fp_0_1;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_0 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^y\ : STD_LOGIC_VECTOR ( 30 downto 13 );
signal \y[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[21]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[20]_INST_0_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_5\ : label is "soft_lutpair8";
begin
y(31) <= \<const0>\;
y(30) <= \^y\(30);
y(29) <= \^y\(27);
y(28) <= \^y\(27);
y(27 downto 13) <= \^y\(27 downto 13);
y(12) <= \<const0>\;
y(11) <= \<const0>\;
y(10) <= \<const0>\;
y(9) <= \<const0>\;
y(8) <= \<const0>\;
y(7) <= \<const0>\;
y(6) <= \<const0>\;
y(5) <= \<const0>\;
y(4) <= \<const0>\;
y(3) <= \<const0>\;
y(2) <= \<const0>\;
y(1) <= \<const0>\;
y(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp
port map (
CO(0) => \y[21]_INST_0_i_5_n_0\,
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
p_1_out(0) => p_1_out(3),
x(9 downto 0) => x(9 downto 0),
\x[9]_0\ => \y[21]_INST_0_i_7_n_0\,
\x[9]_1\ => \y[22]_INST_0_i_2_n_0\,
\x[9]_2\ => \y[20]_INST_0_i_5_n_0\,
\x[9]_3\ => \y[20]_INST_0_i_6_n_0\,
\x[9]_4\ => \y[30]_INST_0_i_1_n_0\,
\x[9]_5\ => \y[22]_INST_0_i_4_n_0\,
\x_9__s_port_]\ => \y[22]_INST_0_i_1_n_0\,
y(9 downto 0) => \^y\(22 downto 13),
\y[13]\ => U0_n_0,
\y[18]\ => U0_n_14,
\y[20]\ => U0_n_13,
\y[20]_0\ => U0_n_18,
\y[21]\ => U0_n_17,
\y[22]\ => U0_n_12,
\y[22]_0\ => U0_n_15,
\y[22]_1\ => U0_n_16,
\y[23]\ => \^y\(23)
);
\y[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(0),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(4),
O => \y[20]_INST_0_i_5_n_0\
);
\y[20]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => x(2),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(6),
O => \y[20]_INST_0_i_6_n_0\
);
\y[21]_INST_0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \y[21]_INST_0_i_10_n_0\
);
\y[21]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y\(23),
I1 => U0_n_14,
O => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[21]_INST_0_i_5_n_0\,
CO(2) => \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\(2),
CO(1) => \y[21]_INST_0_i_5_n_2\,
CO(0) => \y[21]_INST_0_i_5_n_3\,
CYINIT => \^y\(23),
DI(3 downto 0) => B"0000",
O(3) => \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\(3),
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
S(3) => '1',
S(2) => \y[21]_INST_0_i_9_n_0\,
S(1) => \y[21]_INST_0_i_10_n_0\,
S(0) => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(1),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(5),
O => \y[21]_INST_0_i_7_n_0\
);
\y[21]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => U0_n_16,
I1 => U0_n_17,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => p_1_out(3)
);
\y[21]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_18,
I3 => U0_n_17,
I4 => x(8),
I5 => x(9),
O => \y[21]_INST_0_i_9_n_0\
);
\y[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[22]_INST_0_i_5_n_0\,
I1 => U0_n_0,
I2 => x(2),
I3 => U0_n_12,
I4 => U0_n_13,
I5 => x(6),
O => \y[22]_INST_0_i_1_n_0\
);
\y[22]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => x(7),
I1 => U0_n_13,
I2 => x(3),
I3 => U0_n_12,
O => \y[22]_INST_0_i_2_n_0\
);
\y[22]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(5),
I1 => U0_n_12,
I2 => x(9),
I3 => U0_n_13,
I4 => x(1),
O => \y[22]_INST_0_i_4_n_0\
);
\y[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(4),
I1 => U0_n_12,
I2 => x(8),
I3 => U0_n_13,
I4 => x(0),
O => \y[22]_INST_0_i_5_n_0\
);
\y[24]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(23),
I2 => U0_n_14,
O => \^y\(24)
);
\y[25]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_15,
I3 => \y[30]_INST_0_i_1_n_0\,
O => \^y\(25)
);
\y[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => x(9),
I1 => \^y\(27),
O => \^y\(26)
);
\y[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => x(9),
I3 => x(8),
I4 => U0_n_17,
I5 => U0_n_18,
O => \^y\(27)
);
\y[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(27),
O => \^y\(30)
);
\y[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => U0_n_17,
I1 => x(1),
I2 => x(0),
I3 => x(2),
I4 => x(3),
I5 => U0_n_16,
O => \y[30]_INST_0_i_1_n_0\
);
end STRUCTURE;
| mit | 30f3457074356db1c72d7697d7301061 | 0.472745 | 2.339275 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/system_ov7670_vga_0_1_sim_netlist.vhdl | 1 | 5,321 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:46:53 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/system_ov7670_vga_0_1_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_1_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_1_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_1_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_1_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_1 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_1 : entity is "system_ov7670_vga_0_1,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_1 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_1;
architecture STRUCTURE of system_ov7670_vga_0_1 is
begin
U0: entity work.system_ov7670_vga_0_1_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | fd5e65d5df4a0ffcdd8f08a1c952ffc0 | 0.52415 | 3.186228 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/ov7670_controller/ov7670_controller.srcs/sources_1/imports/new/i2c_sender.vhd | 8 | 4,935 | ----------------------------------------------------------------------------------
-- Engineer: <[email protected]
--
-- Description: Send the commands to the OV7670 over an I2C-like interface
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end i2c_sender;
architecture Structural of i2c_sender is
-- this value gives a 254 cycle pause before the initial frame is sent
signal divider : unsigned (7 downto 0) := "00000001";
signal busy_sr : std_logic_vector(31 downto 0) := (others => '0');
signal data_sr : std_logic_vector(31 downto 0) := (others => '1');
begin
process(busy_sr, data_sr(31))
begin
if busy_sr(11 downto 10) = "10" or
busy_sr(20 downto 19) = "10" or
busy_sr(29 downto 28) = "10" then
siod <= 'Z';
else
siod <= data_sr(31);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
taken <= '0';
if busy_sr(31) = '0' then
SIOC <= '1';
if send = '1' then
if divider = "00000000" then
data_sr <= "100" & id & '0' & reg & '0' & value & '0' & "01";
busy_sr <= "111" & "111111111" & "111111111" & "111111111" & "11";
taken <= '1';
else
divider <= divider+1; -- this only happens on powerup
end if;
end if;
else
case busy_sr(32-1 downto 32-3) & busy_sr(2 downto 0) is
when "111"&"111" => -- start seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"110" => -- start seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"100" => -- start seq #3
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '0';
when "10" => SIOC <= '0';
when others => SIOC <= '0';
end case;
when "110"&"000" => -- end seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "100"&"000" => -- end seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "000"&"000" => -- Idle
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when others =>
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '0';
end case;
end case;
if divider = "11111111" then
busy_sr <= busy_sr(32-2 downto 0) & '0';
data_sr <= data_sr(32-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end Structural; | mit | d778cb5d072343c8dcfd14618f5a56cd | 0.347923 | 4.523373 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dotdiv.vhd | 2 | 9,900 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
use work.dsputil_pac.all;
-------------------------------------------------------------------------------
entity dotdiv is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
num_shift : in std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
div_q : in std_logic_vector((sig_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end dotdiv;
--=----------------------------------------------------------------------------
architecture archi_dotdiv of dotdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_dotdiv_pipe_length : integer := div_pipe_length + 4;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_dotdiv_state is (st_init, st_load_divpipe, st_store_divres);
signal s_state : t_dotdiv_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w_offs : unsigned((cmdreg_width - 1) downto 0);
signal s_wr_en : std_logic;
signal s_data_a : std_logic_vector((sig_width - 1) downto 0);
signal s_data_b : std_logic_vector((sig_width - 1) downto 0);
signal s_div_num : std_logic_vector((sig_width - 1) downto 0);
signal s_num_shift : unsigned(2 downto 0);
signal s_div_den_next : std_logic_vector((sig_width - 1) downto 0);
signal s_div_num_next : std_logic_vector((2*sig_width - 1) downto 0);
signal s_num_sign : std_logic;
begin -- archs_dotdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_dotdiv : process (clk)
begin -- process p_dotdiv
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
s_dsp_bus.op_done <= '0';
s_addr_r <= (others => '0');
s_addr_w <= (others => '0');
s_wr_en <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_addr_w <= (others => '0');
s_addr_r <= (others => '0');
s_wr_en <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_load_divpipe;
s_addr_r <= (others => '0');
end if;
when st_load_divpipe =>
s_addr_r <= s_addr_r + 1;
if(s_addr_r = c_dotdiv_pipe_length) then
s_wr_en <= '1';
s_state <= st_store_divres;
end if;
when st_store_divres =>
s_addr_r <= s_addr_r + 1;
s_addr_w <= s_addr_w + 1;
if s_addr_w = s_length then
-- end of operation
s_wr_en <= '0';
s_state <= st_init;
s_dsp_bus.op_done <= '1';
end if;
when others => null;
end case;
end if;
end if;
end process p_dotdiv;
p_data_select : process (clk)
begin -- process p_data_select
if rising_edge(clk) then -- rising clock edge
case opflag_select(opflagbit_srcm2 downto opflagbit_srcm0) is
when "011" =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m1;
when "101" =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m2;
when "110" =>
s_data_a <= data_in_m1;
s_data_b <= data_in_m2;
when others =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m1;
end case;
s_dsp_bus.div_num <= s_div_num_next;
s_dsp_bus.div_den <= s_div_den_next;
s_num_shift <= unsigned(num_shift(2 downto 0));
end if;
end process p_data_select;
p_out_select : process (clk)
begin -- process p_out_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m0) = '1' then
s_dsp_bus.wr_en_m0 <= s_wr_en;
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m1) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= s_wr_en;
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m2) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= s_wr_en;
end if;
s_dsp_bus.data_out_m0 <= div_q;
s_dsp_bus.data_out_m1 <= div_q;
s_dsp_bus.data_out_m2 <= div_q;
end if;
end process p_out_select;
p_adr_select : process (clk)
begin -- process p_adr_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_w_m0 <= (others => '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.c_en_m0 <= '0';
s_dsp_bus.c_en_m1 <= '0';
s_dsp_bus.c_en_m2 <= '0';
else
s_dsp_bus.addr_w_m0 <= s_addr_w_offs;
s_dsp_bus.addr_r_m0 <= s_addr_r;
if opflag_select(opflagbit_srcm1) = '1' then
s_dsp_bus.addr_m1 <= s_addr_r;
else
s_dsp_bus.addr_m1 <= s_addr_w_offs;
end if;
if opflag_select(opflagbit_srcm2) = '1' then
s_dsp_bus.addr_m2 <= s_addr_r;
else
s_dsp_bus.addr_m2 <= s_addr_w_offs;
end if;
s_dsp_bus.c_en_m0 <= opflag_select(opflagbit_srcm0) or opflag_select(opflagbit_m0);
s_dsp_bus.c_en_m1 <= opflag_select(opflagbit_srcm1) or opflag_select(opflagbit_m1);
s_dsp_bus.c_en_m2 <= opflag_select(opflagbit_srcm2) or opflag_select(opflagbit_m2);
end if;
end if;
end process p_adr_select;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-- Divider input signals
s_div_num <= s_data_a when opflag_select(opflagbit_srcswap) = '0' else s_data_b;
s_div_den_next <= s_data_a when opflag_select(opflagbit_srcswap) = '1' else s_data_b;
s_div_num_next <= s_div_num & zeros(sig_width) when to_integer(s_num_shift) = 0 else
bit_extent(s_num_sign, 2) & s_div_num & zeros(sig_width - 2) when to_integer(s_num_shift) = 1 else
bit_extent(s_num_sign, 4) & s_div_num & zeros(sig_width - 4) when to_integer(s_num_shift) = 2 else
bit_extent(s_num_sign, 6) & s_div_num & zeros(sig_width - 6) when to_integer(s_num_shift) = 3 else
bit_extent(s_num_sign, 8) & s_div_num & zeros(sig_width - 8) when to_integer(s_num_shift) = 4 else
bit_extent(s_num_sign, 10) & s_div_num & zeros(sig_width - 10) when to_integer(s_num_shift) = 5 else
bit_extent(s_num_sign, 12) & s_div_num & zeros(sig_width - 12) when to_integer(s_num_shift) = 6 else
bit_extent(s_num_sign, 14) & s_div_num & zeros(sig_width - 14);-- when s_num_shift = x"7";
s_num_sign <= s_div_num(sig_width - 1);
dsp_bus <= s_dsp_bus;
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_dsp_bus.alu_select <= alu_mul;
s_addr_w_offs <= s_addr_w + unsigned(offset_result);
end archi_dotdiv;
| gpl-3.0 | ab5523298142087dd4a99474a13878fd | 0.477677 | 3.350254 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s1.vhd | 2 | 3,979 | library ieee;
use ieee.std_logic_1164.all;
entity s1 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s1;
architecture behaviour of s1 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end; | mit | a7b2a84e30c3ee8840bb4dc933c57a82 | 0.673536 | 3.030465 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_sim_netlist.vhdl | 1 | 2,227 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_rgb565_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_rgb565_0_0 : entity is "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_rgb565_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_rgb565_0_0 : entity is "rgb888_to_rgb565,Vivado 2016.4";
end system_rgb888_to_rgb565_0_0;
architecture STRUCTURE of system_rgb888_to_rgb565_0_0 is
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\^rgb_888\(23 downto 19) <= rgb_888(23 downto 19);
\^rgb_888\(15 downto 10) <= rgb_888(15 downto 10);
\^rgb_888\(7 downto 3) <= rgb_888(7 downto 3);
rgb_565(15 downto 11) <= \^rgb_888\(23 downto 19);
rgb_565(10 downto 5) <= \^rgb_888\(15 downto 10);
rgb_565(4 downto 0) <= \^rgb_888\(7 downto 3);
end STRUCTURE;
| mit | e1b8b85d81fb223b1a77cbfdd0058d62 | 0.651998 | 3.420891 | false | false | false | false |
sbourdeauducq/dspunit | rtl/conv_circ.vhd | 2 | 8,325 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity conv_circ is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
alu_result1 : in std_logic_vector((sig_width - 1) downto 0);
alu_result_acc1 : in std_logic_vector((acc_width - 1) downto 0);
alu_result2 : in std_logic_vector((sig_width - 1) downto 0);
alu_result_acc2 : in std_logic_vector((acc_width - 1) downto 0);
gcount : in unsigned(15 downto 0);
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus;
test : out std_logic_vector((sig_width - 1) downto 0)
);
end conv_circ;
--=----------------------------------------------------------------------------
architecture archi_conv_circ of conv_circ is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_conv_circ_state is (st_init, st_integral, st_store, st_waitpipe, st_startpipe);
signal s_state : t_conv_circ_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_conv_res : std_logic_vector((sig_width - 1) downto 0);
begin -- archs_conv_circ
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_conv_circ : process (clk)
begin -- process p_conv_circ
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_w_m0 <= (others => '0');
s_dsp_bus.wr_en_m0 <= '0';
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
--s_dsp_bus.c_en_m2 <= '0';
-- alu
--s_dsp_bus.mul_in_a1 <= (others <= '0');
--s_dsp_bus.mul_in_b1 <= (others <= '0');
--s_dsp_bus.mul_in_a2 <= (others <= '0');
--s_dsp_bus.mul_in_b2 <= (others <= '0');
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-- global counter
--s_dsp_bus.gcounter_reset <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_m1 <= s_length;
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_startpipe;
end if;
when st_startpipe =>
if s_dsp_bus.addr_r_m0 = 1 then
s_state <= st_integral;
-- s_dsp_bus.acc_mode1 <= acc_add;
end if;
-- index increment
s_dsp_bus.addr_r_m0 <= s_dsp_bus.addr_r_m0 + 1;
s_dsp_bus.addr_m1 <= (s_dsp_bus.addr_m1 - 1) and s_length;
-- accumulator init
s_dsp_bus.acc_mode1 <= acc_store;
when st_waitpipe =>
if s_dsp_bus.addr_r_m0 = 1 then
s_state <= st_store;
s_dsp_bus.acc_mode1 <= acc_store;
-- s_dsp_bus.wr_en_m2 <= '1';
end if;
-- index increment
s_dsp_bus.addr_r_m0 <= s_dsp_bus.addr_r_m0 + 1;
s_dsp_bus.addr_m1 <= (s_dsp_bus.addr_m1 - 1) and s_length;
when st_store =>
-- save accumulator result in memory
s_dsp_bus.wr_en_m2 <= '1';
if(s_dsp_bus.addr_m2 = s_length) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
else
s_dsp_bus.acc_mode1 <= acc_add;
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m2 + 1;
s_state <= st_integral;
end if;
-- index increment
s_dsp_bus.addr_r_m0 <= s_dsp_bus.addr_r_m0 + 1;
s_dsp_bus.addr_m1 <= (s_dsp_bus.addr_m1 - 1) and s_length;
when st_integral =>
s_dsp_bus.wr_en_m2 <= '0';
-- perform mac operation
s_dsp_bus.acc_mode1 <= acc_add;
-- end of integration
if s_dsp_bus.addr_r_m0 = s_length then
s_state <= st_waitpipe;
s_dsp_bus.addr_r_m0 <= (others => '0');
else
-- index increment
s_dsp_bus.addr_r_m0 <= s_dsp_bus.addr_r_m0 + 1;
s_dsp_bus.addr_m1 <= (s_dsp_bus.addr_m1 - 1) and s_length;
end if;
when others => null;
end case;
end if;
end if;
end process p_conv_circ;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
-- multiplication of signals is made before accumulation
s_dsp_bus.mul_in_a1 <= data_in_m0;
s_dsp_bus.mul_in_b1 <= data_in_m1;
s_conv_res <= std_logic_vector(alu_result_acc1((sig_width - 1) downto 0));
s_dsp_bus.data_out_m2 <= s_conv_res;
s_dsp_bus.data_out_m0 <= s_conv_res;
s_dsp_bus.data_out_m1 <= s_conv_res;
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
test <= s_conv_res;
end archi_conv_circ;
-------------------------------------------------------------------------------
| gpl-3.0 | 4ef40163fbea51986c50d4fa249e7ce0 | 0.421021 | 3.600779 | false | false | false | false |
loa-org/loa-hdl | modules/uart/tb/uart_tb.vhd | 2 | 2,788 | -------------------------------------------------------------------------------
-- Title : Testbench for design "uart"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_tb is
end entity uart_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tb is
-- component ports
signal txd : std_logic := '1';
signal rxd : std_logic := '1';
signal rxd_combined : std_logic := '1';
signal din : std_logic_vector(7 downto 0) := (others => '0');
signal dout : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal error : std_logic := '0';
signal full : std_logic := '0';
signal clk_en : std_logic := '0';
signal clk : std_logic := '0';
begin
rxd_combined <= rxd and txd;
-- component instantiation
dut : uart
port map (
txd_p => txd,
rxd_p => rxd_combined,
din_p => din,
empty_p => empty,
re_p => re,
dout_p => dout,
we_p => we,
error_p => error,
full_p => full,
clk_en => clk_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_en <= '1';
wait until rising_edge(clk);
clk_en <= '0';
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
-- transmission from extern
uart_transmit(rxd, "001111100", 5000000);
wait for 10 us;
uart_transmit(rxd, "101011100", 5000000);
wait for 1 us;
uart_transmit(rxd, "101011101", 5000000);
wait;
end process waveform;
fifo : process
begin
wait for 3 us;
empty <= '0';
din <= "00000000";
wait until falling_edge(re);
din <= "11001010";
wait until falling_edge(re);
din <= "00001011";
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
wait;
end process fifo;
end architecture behavourial;
| bsd-3-clause | 3818e154cf7bade41f7c598a52e5f886 | 0.436514 | 4.376766 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/1e84/hdl/vhdl/util_ds_buf.vhd | 1 | 13,877 | -------------------------------------------------------------------------------
-- util_ds_buf.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2007 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_ds_buf.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_ds_buf.vhd
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity util_ds_buf is
generic (
C_BUF_TYPE : string := "IBUFDS";
C_SIZE : integer := 1
);
port (
-- ports for differential signaling input buffer
IBUF_DS_P : in std_logic_vector(C_SIZE-1 downto 0);
IBUF_DS_N : in std_logic_vector(C_SIZE-1 downto 0);
IBUF_OUT : out std_logic_vector(C_SIZE-1 downto 0);
IBUF_DS_ODIV2 : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for differential signaling output buffer
OBUF_IN : in std_logic_vector(C_SIZE-1 downto 0);
OBUF_DS_P : out std_logic_vector(C_SIZE-1 downto 0);
OBUF_DS_N : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for tri-state differential signaling io buffer
IOBUF_DS_P : inout std_logic_vector(C_SIZE-1 downto 0);
IOBUF_DS_N : inout std_logic_vector(C_SIZE-1 downto 0);
IOBUF_IO_T : in std_logic_vector(C_SIZE-1 downto 0);
IOBUF_IO_I : in std_logic_vector(C_SIZE-1 downto 0);
IOBUF_IO_O : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for BUFG
BUFG_I : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_O : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for BUFGCE
BUFGCE_I : in std_logic_vector(C_SIZE-1 downto 0);
BUFGCE_CE : in std_logic_vector(C_SIZE-1 downto 0);
BUFGCE_O : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for BUFH
BUFH_I : in std_logic_vector(C_SIZE-1 downto 0);
BUFH_O : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for BUFHCE
BUFHCE_I : in std_logic_vector(C_SIZE-1 downto 0);
BUFHCE_CE : in std_logic_vector(C_SIZE-1 downto 0);
BUFHCE_O : out std_logic_vector(C_SIZE-1 downto 0);
-- ports for BUFG_GT
BUFG_GT_I : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_GT_CE : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_GT_CEMASK : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_GT_CLR : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_GT_CLRMASK : in std_logic_vector(C_SIZE-1 downto 0);
BUFG_GT_DIV : in std_logic_vector((3 * C_SIZE) - 1 downto 0);
BUFG_GT_O : out std_logic_vector(C_SIZE-1 downto 0)
);
end util_ds_buf;
architecture IMP of util_ds_buf is
-- function to return lower case character
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- function to return lower case string
function LowerCase_String (s : string) return string is
variable res : string(s'range);
begin
for I in s'range loop
res(I) := LowerCase_Char(s(I));
end loop;
return res;
end function LowerCase_String;
constant BUFFER_TYPE : string := LowerCase_String(C_BUF_TYPE);
begin
-- instantiate IBUFDS_GTE2
USE_IBUFDS_GTE2 : if (BUFFER_TYPE = "ibufdsgte2") generate
signal IBUF_OUT_P : std_logic_vector(C_SIZE-1 downto 0);
signal IBUF_OUT_N : std_logic_vector(C_SIZE-1 downto 0);
begin
GEN_IBUFDS_GTE2 : for i in 0 to C_SIZE-1 generate
IBUF_P_I : IBUF
port map (O => IBUF_OUT_P(i), I => IBUF_DS_P(i));
IBUF_N_I : IBUF
port map (O => IBUF_OUT_N(i), I => IBUF_DS_N(i));
IBUFDS_GTE2_I : IBUFDS_GTE2
port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_OUT_P(i), IB => IBUF_OUT_N(i), CEB => '0');
end generate GEN_IBUFDS_GTE2;
-- tie-off other non-used outputs
OBUF_DS_P <= (others => '0');
OBUF_DS_N <= (others => '0');
IOBUF_IO_O <= (others => '0');
IOBUF_DS_P <= (others => '0');
IOBUF_DS_N <= (others => '0');
end generate USE_IBUFDS_GTE2;
-- instantiate IBUFDS_GTE3
USE_IBUFDS_GTE3 : if (BUFFER_TYPE = "ibufdsgte3") generate
GEN_IBUFDS_GTE3 : for i in 0 to C_SIZE-1 generate
IBUFDS_GTE3_I : IBUFDS_GTE3
port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i), CEB => '0');
end generate GEN_IBUFDS_GTE3;
-- tie-off other non-used outputs
OBUF_DS_P <= (others => '0');
OBUF_DS_N <= (others => '0');
IOBUF_IO_O <= (others => '0');
IOBUF_DS_P <= (others => '0');
IOBUF_DS_N <= (others => '0');
end generate USE_IBUFDS_GTE3;
-- instantiate IBUFDS_GTE4
USE_IBUFDS_GTE4 : if (BUFFER_TYPE = "ibufdsgte4") generate
GEN_IBUFDS_GTE4 : for i in 0 to C_SIZE-1 generate
IBUFDS_GTE4_I : IBUFDS_GTE4
port map (O => IBUF_OUT(i), ODIV2 => IBUF_DS_ODIV2(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i), CEB => '0');
end generate GEN_IBUFDS_GTE4;
-- tie-off other non-used outputs
OBUF_DS_P <= (others => '0');
OBUF_DS_N <= (others => '0');
IOBUF_IO_O <= (others => '0');
IOBUF_DS_P <= (others => '0');
IOBUF_DS_N <= (others => '0');
end generate USE_IBUFDS_GTE4;
-- instantiate IBUFDS
USE_IBUFDS : if (BUFFER_TYPE = "ibufds") generate
GEN_IBUFDS : for i in 0 to C_SIZE-1 generate
IBUFDS_I : IBUFDS
port map (O => IBUF_OUT(i), I => IBUF_DS_P(i), IB => IBUF_DS_N(i));
end generate GEN_IBUFDS;
-- tie-off other non-used outputs
IBUF_DS_ODIV2 <= (others => '0');
OBUF_DS_P <= (others => '0');
OBUF_DS_N <= (others => '0');
IOBUF_IO_O <= (others => '0');
IOBUF_DS_P <= (others => '0');
IOBUF_DS_N <= (others => '0');
end generate USE_IBUFDS;
-- instantiate OBUFDS
USE_OBUFDS : if (BUFFER_TYPE = "obufds") generate
GEN_OBUFDS : for i in 0 to C_SIZE-1 generate
OBUFDS_I : OBUFDS
port map (O => OBUF_DS_P(i), OB => OBUF_DS_N(i), I => OBUF_IN(i));
end generate GEN_OBUFDS;
-- tie-off other non-used outputs
IBUF_OUT <= (others => '0');
IBUF_DS_ODIV2 <= (others => '0');
IOBUF_IO_O <= (others => '0');
IOBUF_DS_P <= (others => '0');
IOBUF_DS_N <= (others => '0');
end generate USE_OBUFDS;
-- instantiate IOBUFDS
USE_IOBUFDS : if (BUFFER_TYPE = "iobufds") generate
GEN_IOBUFDS : for i in 0 to C_SIZE-1 generate
IOBUFDS_I : IOBUFDS
port map (
O => IOBUF_IO_O(i),
IO => IOBUF_DS_P(i),
IOB => IOBUF_DS_N(i),
I => IOBUF_IO_I(i),
T => IOBUF_IO_T(i)
);
end generate GEN_IOBUFDS;
-- tie-off other non-used outputs
IBUF_OUT <= (others => '0');
IBUF_DS_ODIV2 <= (others => '0');
OBUF_DS_P <= (others => '0');
OBUF_DS_N <= (others => '0');
end generate USE_IOBUFDS;
-- instantiate BUFG
USE_BUFG : if (BUFFER_TYPE = "bufg") generate
GEN_BUFG : for i in 0 to C_SIZE-1 generate
BUFG_U : BUFG
port map (
O => BUFG_O(i),
I => BUFG_I(i)
);
end generate GEN_BUFG;
end generate USE_BUFG;
-- instantiate BUFGCE
USE_BUFGCE : if (BUFFER_TYPE = "bufgce") generate
GEN_BUFGCE : for i in 0 to C_SIZE-1 generate
BUFGCE_U : BUFGCE
port map (
O => BUFGCE_O(i),
I => BUFGCE_I(i),
CE => BUFGCE_CE(i)
);
end generate GEN_BUFGCE;
end generate USE_BUFGCE;
-- instantiate BUFH
USE_BUFH : if (BUFFER_TYPE = "bufh") generate
GEN_BUFH : for i in 0 to C_SIZE-1 generate
BUFH_U : BUFH
port map (
O => BUFH_O(i),
I => BUFH_I(i)
);
end generate GEN_BUFH;
end generate USE_BUFH;
-- instantiate BUFHCE
USE_BUFHCE : if (BUFFER_TYPE = "bufhce") generate
GEN_BUFHCE : for i in 0 to C_SIZE-1 generate
BUFHCE_U : BUFHCE
port map (
O => BUFHCE_O(i),
I => BUFHCE_I(i),
CE => BUFHCE_CE(i)
);
end generate GEN_BUFHCE;
end generate USE_BUFHCE;
-- instantiate BUFG
USE_BUFG_GT : if (BUFFER_TYPE = "bufg_gt") generate
GEN_BUFG_GT : for i in 0 to C_SIZE-1 generate
BUFG_GT_U : BUFG_GT
port map (
O => BUFG_GT_O(i),
CE => BUFG_GT_CE(i),
CEMASK => BUFG_GT_CEMASK(i),
CLR => BUFG_GT_CLR(i),
CLRMASK => BUFG_GT_CLRMASK(i),
DIV => BUFG_GT_DIV((3*i)+2 downto 3*i),
I => BUFG_GT_I(i)
);
end generate GEN_BUFG_GT;
end generate USE_BUFG_GT;
end IMP;
| mit | b875b814b32c61f19575ece71dbad7c5 | 0.468761 | 3.708445 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div_pipe_inferred-rtl.vhdl | 1 | 3,273 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
architecture rtl of div_pipe_inferred is
type comb_type is record
dbz : std_ulogic;
overflow : std_ulogic;
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
end record;
signal c : comb_type;
type stage_type is record
dbz : std_ulogic;
overflow : std_ulogic;
result : std_ulogic_vector(src1_bits downto 0);
end record;
type reg_type is array(0 to stages-1) of stage_type;
signal r, r_next : reg_type;
pure function div(src1, src2 : std_ulogic_vector(src1_bits downto 0)) return std_ulogic_vector is
variable ret : std_ulogic_vector(src1_bits downto 0);
begin
-- pragma translate_off
if is_x(src1) or is_x(src2) or src2 = (src1_bits downto 0 => '0') then
ret := (others => 'X');
else
-- pragma translate_on
ret := std_ulogic_vector(signed(src1) / signed(src2));
-- pragma translate_off
end if;
-- pragma translate_on
return ret;
end function;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src1(src2_bits-1) and not unsgnd) & src2;
c.dbz <= all_zeros(src2);
c.overflow <= (not unsgnd and
-- e.g. (signed) 0x80000000 / 0xffffffff = 0x80000000
-- so result is not representable
src1(src1_bits-1) and all_zeros(src1(src1_bits-2 downto 0)) and
all_ones(src2)
);
r_next(0).dbz <= c.dbz;
r_next(0).overflow <= c.overflow;
r_next(0).result <= div(c.src1_tmp, c.src2_tmp);
stages_gt_1 : if stages > 1 generate
pipeline_loop : for n in 1 to stages-1 generate
r_next(n) <= r(n-1);
end generate;
end generate;
dbz <= r(stages-1).dbz;
overflow <= r(stages-1).overflow;
result <= r(stages-1).result(src1_bits-1 downto 0);
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | a754cf13409c55e9ec5ddeb4cb734a02 | 0.55912 | 3.740571 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl | 1 | 2,376 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:17 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb565_to_rgb888_0_0 -prefix
-- system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_1_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb_565\(15 downto 0) <= rgb_565(15 downto 0);
rgb_888(23 downto 19) <= \^rgb_565\(15 downto 11);
rgb_888(18 downto 16) <= \^rgb_565\(15 downto 13);
rgb_888(15 downto 10) <= \^rgb_565\(10 downto 5);
rgb_888(9 downto 8) <= \^rgb_565\(10 downto 9);
rgb_888(7 downto 3) <= \^rgb_565\(4 downto 0);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
| mit | c3d0dc684bc67edfaf526533080788a7 | 0.635943 | 3.384615 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zybo_hdmi/zybo_hdmi.srcs/sources_1/new/dvid.vhd | 6 | 3,920 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; | mit | 91b4125808c18eac542e272b207f7b48 | 0.522449 | 3.450704 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/zed_hdmi.vhd | 7 | 6,019 | ----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; | mit | 45fe007000789bfc5ab40e48f9108509 | 0.435787 | 3.895793 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/mmu/inst/pass/cpu_or1knd_i5_mmu_inst_pass-rtl.vhdl | 1 | 1,736 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_mmu_inst_types_pkg.all;
architecture rtl of cpu_or1knd_i5_mmu_inst_pass is
begin
mmu : entity work.cpu_mmu_inst_pass(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_inst_pass_ctrl_in => cpu_or1knd_i5_mmu_inst_pass_ctrl_in,
cpu_mmu_inst_pass_ctrl_out => cpu_or1knd_i5_mmu_inst_pass_ctrl_out,
cpu_mmu_inst_pass_dp_in => cpu_or1knd_i5_mmu_inst_pass_dp_in,
cpu_mmu_inst_pass_dp_out => cpu_or1knd_i5_mmu_inst_pass_dp_out
);
end;
| apache-2.0 | 716fff74b573d726e5ffa62552e0416f | 0.520161 | 4.16307 | false | false | false | false |
loa-org/loa-hdl | modules/ir_tx/hdl/ir_tx_module.vhd | 2 | 4,326 | -------------------------------------------------------------------------------
-- Title : Transmitter for infrared beacons
-- Project :
-------------------------------------------------------------------------------
-- File : uss_tx_module.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Register description
--
-- offset | Meaning
-- -------+---------
-- 0x00 | Fractional Clock Divider MUL value
-- 0x01 | Fractional Clock Divider DIV value
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.reg_file_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity ir_tx_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF# -- Base address at the internal data bus
);
port (
-- Ports to the ultrasonic transmitters
ir_tx_p : out std_logic;
-- Modulation input for one infrared transmitter
modulation_p : in std_logic;
-- Output of the clock enable signal
clk_ir_enable_p : out std_logic;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end ir_tx_module;
-------------------------------------------------------------------------------
architecture behavioral of ir_tx_module is
-- types for states
-- none
-- record for internal states
-- none
-----------------------------------------------------------------------------
-- internal signals
-----------------------------------------------------------------------------
-- access to the internal register
constant REG_ADDR_BIT : natural := 1; -- 2**1 = 2 registers for mul and div value
signal reg_o : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal reg_i : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal clk_mul : std_logic_vector(15 downto 0);
signal clk_div : std_logic_vector(15 downto 0);
signal clk_ir_enable : std_logic := '0';
signal clk_ir : std_logic := '0'; -- Clock signal with 50% duty cycle
begin -- behavioral
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- register for access to and from STM
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk
);
-- clock generation of clk_uss_tx
fractional_clock_divider_variable_1 : fractional_clock_divider_variable
generic map (
WIDTH => 16)
port map (
div => clk_div,
mul => clk_mul,
clk_out_p => clk_ir_enable,
clk => clk);
-- generate a signal with a 50% duty-cycle from the enable signal
process (clk, clk_ir_enable)
begin
if rising_edge(clk) then
if clk_ir_enable = '1' then
clk_ir <= not clk_ir;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Mapping of signals between components and module ports
-----------------------------------------------------------------------------
clk_mul <= reg_o(0);
clk_div <= reg_o(1);
-- read back
reg_i <= reg_o;
clk_ir_enable_p <= clk_ir_enable;
-----------------------------------------------------------------------------
-- Drive Infrared Transmitters
-----------------------------------------------------------------------------
ir_tx_p <= clk_ir and modulation_p;
end behavioral;
| bsd-3-clause | f2e50fd391fdaa6d5326ee78416c91bc | 0.420943 | 4.631692 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_or1knd_i5_core-rtl.vhdl | 1 | 12,482 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_or1knd_i5_mmu_inst_pkg.all;
use work.cpu_or1knd_i5_mmu_data_pkg.all;
use work.cpu_l1mem_inst_pkg.all;
use work.cpu_l1mem_data_pkg.all;
use work.cpu_or1knd_i5_pipe_pkg.all;
architecture rtl of cpu_or1knd_i5_core is
type comb_type is record
sys_master_ctrl_out_master : sys_master_ctrl_out_vector_type(1 downto 0);
sys_master_dp_out_master : sys_master_dp_out_vector_type(1 downto 0);
sys_slave_ctrl_out_master : sys_slave_ctrl_out_vector_type(1 downto 0);
sys_master_ctrl_out : sys_master_ctrl_out_type;
sys_master_dp_out : sys_master_dp_out_type;
cpu_l1mem_inst_ctrl_in : cpu_l1mem_inst_ctrl_in_type;
cpu_l1mem_inst_dp_in : cpu_l1mem_inst_dp_in_type;
cpu_l1mem_inst_ctrl_out : cpu_l1mem_inst_ctrl_out_type;
cpu_l1mem_inst_dp_out : cpu_l1mem_inst_dp_out_type;
cpu_l1mem_data_ctrl_in : cpu_l1mem_data_ctrl_in_type;
cpu_l1mem_data_dp_in : cpu_l1mem_data_dp_in_type;
cpu_l1mem_data_ctrl_out : cpu_l1mem_data_ctrl_out_type;
cpu_l1mem_data_dp_out : cpu_l1mem_data_dp_out_type;
cpu_or1knd_i5_mmu_inst_ctrl_in : cpu_or1knd_i5_mmu_inst_ctrl_in_type;
cpu_or1knd_i5_mmu_inst_dp_in : cpu_or1knd_i5_mmu_inst_dp_in_type;
cpu_or1knd_i5_mmu_inst_ctrl_out : cpu_or1knd_i5_mmu_inst_ctrl_out_type;
cpu_or1knd_i5_mmu_inst_dp_out : cpu_or1knd_i5_mmu_inst_dp_out_type;
cpu_or1knd_i5_mmu_data_ctrl_in : cpu_or1knd_i5_mmu_data_ctrl_in_type;
cpu_or1knd_i5_mmu_data_dp_in : cpu_or1knd_i5_mmu_data_dp_in_type;
cpu_or1knd_i5_mmu_data_ctrl_out : cpu_or1knd_i5_mmu_data_ctrl_out_type;
cpu_or1knd_i5_mmu_data_dp_out : cpu_or1knd_i5_mmu_data_dp_out_type;
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe : cpu_or1knd_i5_mmu_inst_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_inst_dp_in_pipe : cpu_or1knd_i5_mmu_inst_dp_in_pipe_type;
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe : cpu_or1knd_i5_mmu_inst_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_inst_dp_out_pipe : cpu_or1knd_i5_mmu_inst_dp_out_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_in_pipe : cpu_or1knd_i5_mmu_data_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_data_dp_in_pipe : cpu_or1knd_i5_mmu_data_dp_in_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_out_pipe : cpu_or1knd_i5_mmu_data_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_data_dp_out_pipe : cpu_or1knd_i5_mmu_data_dp_out_pipe_type;
end record;
signal c : comb_type;
begin
pipe : entity work.cpu_or1knd_i5_pipe(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_l1mem_inst_ctrl_out => c.cpu_l1mem_inst_ctrl_out,
cpu_l1mem_data_ctrl_out => c.cpu_l1mem_data_ctrl_out,
cpu_l1mem_inst_dp_out => c.cpu_l1mem_inst_dp_out,
cpu_l1mem_data_dp_out => c.cpu_l1mem_data_dp_out,
cpu_l1mem_inst_ctrl_in => c.cpu_l1mem_inst_ctrl_in,
cpu_l1mem_data_ctrl_in => c.cpu_l1mem_data_ctrl_in,
cpu_l1mem_inst_dp_in => c.cpu_l1mem_inst_dp_in,
cpu_l1mem_data_dp_in => c.cpu_l1mem_data_dp_in,
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_in_pipe,
cpu_or1knd_i5_mmu_inst_dp_in_pipe => c.cpu_or1knd_i5_mmu_inst_dp_in_pipe,
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_out_pipe,
cpu_or1knd_i5_mmu_inst_dp_out_pipe => c.cpu_or1knd_i5_mmu_inst_dp_out_pipe,
cpu_or1knd_i5_mmu_data_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_in_pipe,
cpu_or1knd_i5_mmu_data_dp_in_pipe => c.cpu_or1knd_i5_mmu_data_dp_in_pipe,
cpu_or1knd_i5_mmu_data_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_out_pipe,
cpu_or1knd_i5_mmu_data_dp_out_pipe => c.cpu_or1knd_i5_mmu_data_dp_out_pipe
);
l1mem_inst : entity work.cpu_l1mem_inst(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_inst_ctrl_in => c.cpu_or1knd_i5_mmu_inst_ctrl_in,
cpu_mmu_inst_dp_in => c.cpu_or1knd_i5_mmu_inst_dp_in,
cpu_mmu_inst_ctrl_out => c.cpu_or1knd_i5_mmu_inst_ctrl_out,
cpu_mmu_inst_dp_out => c.cpu_or1knd_i5_mmu_inst_dp_out,
cpu_l1mem_inst_ctrl_in => c.cpu_l1mem_inst_ctrl_in,
cpu_l1mem_inst_dp_in => c.cpu_l1mem_inst_dp_in,
cpu_l1mem_inst_ctrl_out => c.cpu_l1mem_inst_ctrl_out,
cpu_l1mem_inst_dp_out => c.cpu_l1mem_inst_dp_out,
sys_master_ctrl_out => c.sys_master_ctrl_out_master(0),
sys_master_dp_out => c.sys_master_dp_out_master(0),
sys_slave_ctrl_out => c.sys_slave_ctrl_out_master(0),
sys_slave_dp_out => sys_slave_dp_out
);
l1mem_data : entity work.cpu_l1mem_data(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_ctrl_in => c.cpu_or1knd_i5_mmu_data_ctrl_in,
cpu_mmu_data_dp_in => c.cpu_or1knd_i5_mmu_data_dp_in,
cpu_mmu_data_ctrl_out => c.cpu_or1knd_i5_mmu_data_ctrl_out,
cpu_mmu_data_dp_out => c.cpu_or1knd_i5_mmu_data_dp_out,
cpu_l1mem_data_ctrl_in => c.cpu_l1mem_data_ctrl_in,
cpu_l1mem_data_dp_in => c.cpu_l1mem_data_dp_in,
cpu_l1mem_data_ctrl_out => c.cpu_l1mem_data_ctrl_out,
cpu_l1mem_data_dp_out => c.cpu_l1mem_data_dp_out,
sys_master_ctrl_out => c.sys_master_ctrl_out_master(1),
sys_master_dp_out => c.sys_master_dp_out_master(1),
sys_slave_ctrl_out => c.sys_slave_ctrl_out_master(1),
sys_slave_dp_out => sys_slave_dp_out
);
mmu_inst : entity work.cpu_or1knd_i5_mmu_inst(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_or1knd_i5_mmu_inst_ctrl_in => c.cpu_or1knd_i5_mmu_inst_ctrl_in,
cpu_or1knd_i5_mmu_inst_dp_in => c.cpu_or1knd_i5_mmu_inst_dp_in,
cpu_or1knd_i5_mmu_inst_ctrl_out => c.cpu_or1knd_i5_mmu_inst_ctrl_out,
cpu_or1knd_i5_mmu_inst_dp_out => c.cpu_or1knd_i5_mmu_inst_dp_out,
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_in_pipe,
cpu_or1knd_i5_mmu_inst_dp_in_pipe => c.cpu_or1knd_i5_mmu_inst_dp_in_pipe,
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_inst_ctrl_out_pipe,
cpu_or1knd_i5_mmu_inst_dp_out_pipe => c.cpu_or1knd_i5_mmu_inst_dp_out_pipe
);
mmu_data : entity work.cpu_or1knd_i5_mmu_data(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_or1knd_i5_mmu_data_ctrl_in => c.cpu_or1knd_i5_mmu_data_ctrl_in,
cpu_or1knd_i5_mmu_data_dp_in => c.cpu_or1knd_i5_mmu_data_dp_in,
cpu_or1knd_i5_mmu_data_ctrl_out => c.cpu_or1knd_i5_mmu_data_ctrl_out,
cpu_or1knd_i5_mmu_data_dp_out => c.cpu_or1knd_i5_mmu_data_dp_out,
cpu_or1knd_i5_mmu_data_ctrl_in_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_in_pipe,
cpu_or1knd_i5_mmu_data_dp_in_pipe => c.cpu_or1knd_i5_mmu_data_dp_in_pipe,
cpu_or1knd_i5_mmu_data_ctrl_out_pipe => c.cpu_or1knd_i5_mmu_data_ctrl_out_pipe,
cpu_or1knd_i5_mmu_data_dp_out_pipe => c.cpu_or1knd_i5_mmu_data_dp_out_pipe
);
arb : entity sys.sys_master_arb(rtl)
generic map (
masters => 2
)
port map (
clk => clk,
rstn => rstn,
sys_master_ctrl_out_master => c.sys_master_ctrl_out_master,
sys_master_dp_out_master => c.sys_master_dp_out_master,
sys_slave_ctrl_out_master => c.sys_slave_ctrl_out_master,
sys_slave_ctrl_out_sys => sys_slave_ctrl_out,
sys_master_ctrl_out_sys => c.sys_master_ctrl_out,
sys_master_dp_out_sys => c.sys_master_dp_out
);
sys_master_ctrl_out <= c.sys_master_ctrl_out;
sys_master_dp_out <= c.sys_master_dp_out;
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(sys_slave_ctrl_out.ready)
report "sys_slave_ctrl_out.ready invalid"
severity failure;
if sys_slave_ctrl_out.ready = '1' then
assert not is_x(sys_slave_ctrl_out.error)
report "sys_slave_ctrl_out.error invalid"
severity failure;
end if;
assert not is_x(c.sys_master_ctrl_out.request)
report "sys_master_ctrl_out.request invalid"
severity failure;
if c.sys_master_ctrl_out.request = '1' then
assert not is_x(c.sys_master_ctrl_out.be)
report "sys_master_ctrl_out.be invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.write)
report "sys_master_ctrl_out.write invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.cacheable)
report "sys_master_ctrl_out.cacheable invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.inst)
report "sys_master_ctrl_out.inst invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.burst)
report "sys_master_ctrl_out.burst invalid"
severity failure;
if c.sys_master_ctrl_out.burst = '1' then
assert not is_x(c.sys_master_ctrl_out.bwrap)
report "sys_master_ctrl_out.bwrap invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.bcycles)
report "sys_master_ctrl_out.bcycles invalid"
severity failure;
end if;
assert not is_x(c.sys_master_dp_out.paddr)
report "sys_master_dp_out.paddr invalid"
severity failure;
for n in sys_transfer_size_bits-1 downto 2 loop
assert c.sys_master_dp_out.size(n) = '0'
report "sys_master_dp_out.size invalid"
severity failure;
end loop;
--case c.sys_master_dp_out.size(1 downto 0) is
-- when "00" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(7 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when "01" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(15 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when "10" =>
-- if c.sys_master_ctrl_out.write = '1' then
-- assert not is_x(c.sys_master_dp_out.data(31 downto 0))
-- report "sys_master_dp_out.data invalid"
-- severity failure;
-- end if;
-- when others =>
-- assert not false
-- report "sys_master_dp_out.size invalid"
-- severity failure;
--end case;
end if;
end if;
end process;
-- pragma translate_on
end;
| apache-2.0 | 81f8eb8730d8f2c0655b93debe456f0f | 0.566736 | 2.785539 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_1_0/system_rgb888_to_g8_1_0_sim_netlist.vhdl | 1 | 157,944 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 23:06:45 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_g8_1_0 -prefix
-- system_rgb888_to_g8_1_0_ system_rgb888_to_g8_1_0_sim_netlist.vhdl
-- Design : system_rgb888_to_g8_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_1_0_rgb888_to_g8 is
port (
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb888_to_g8_1_0_rgb888_to_g8;
architecture STRUCTURE of system_rgb888_to_g8_1_0_rgb888_to_g8 is
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal g810_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g81__120_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_1\ : STD_LOGIC;
signal \g81__120_carry__0_n_2\ : STD_LOGIC;
signal \g81__120_carry__0_n_3\ : STD_LOGIC;
signal \g81__120_carry__0_n_4\ : STD_LOGIC;
signal \g81__120_carry__0_n_5\ : STD_LOGIC;
signal \g81__120_carry__0_n_6\ : STD_LOGIC;
signal \g81__120_carry__0_n_7\ : STD_LOGIC;
signal \g81__120_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_1\ : STD_LOGIC;
signal \g81__120_carry__1_n_2\ : STD_LOGIC;
signal \g81__120_carry__1_n_3\ : STD_LOGIC;
signal \g81__120_carry__1_n_4\ : STD_LOGIC;
signal \g81__120_carry__1_n_5\ : STD_LOGIC;
signal \g81__120_carry__1_n_6\ : STD_LOGIC;
signal \g81__120_carry__1_n_7\ : STD_LOGIC;
signal \g81__120_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_n_1\ : STD_LOGIC;
signal \g81__120_carry__2_n_3\ : STD_LOGIC;
signal \g81__120_carry__2_n_6\ : STD_LOGIC;
signal \g81__120_carry__2_n_7\ : STD_LOGIC;
signal \g81__120_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_1\ : STD_LOGIC;
signal \g81__120_carry_n_2\ : STD_LOGIC;
signal \g81__120_carry_n_3\ : STD_LOGIC;
signal \g81__120_carry_n_4\ : STD_LOGIC;
signal \g81__120_carry_n_5\ : STD_LOGIC;
signal \g81__120_carry_n_6\ : STD_LOGIC;
signal \g81__149_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_1\ : STD_LOGIC;
signal \g81__149_carry__0_n_2\ : STD_LOGIC;
signal \g81__149_carry__0_n_3\ : STD_LOGIC;
signal \g81__149_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_1\ : STD_LOGIC;
signal \g81__149_carry__1_n_2\ : STD_LOGIC;
signal \g81__149_carry__1_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_1\ : STD_LOGIC;
signal \g81__149_carry__2_n_2\ : STD_LOGIC;
signal \g81__149_carry__2_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_n_4\ : STD_LOGIC;
signal \g81__149_carry__2_n_5\ : STD_LOGIC;
signal \g81__149_carry__2_n_6\ : STD_LOGIC;
signal \g81__149_carry__2_n_7\ : STD_LOGIC;
signal \g81__149_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_1\ : STD_LOGIC;
signal \g81__149_carry__3_n_2\ : STD_LOGIC;
signal \g81__149_carry__3_n_3\ : STD_LOGIC;
signal \g81__149_carry__3_n_4\ : STD_LOGIC;
signal \g81__149_carry__3_n_5\ : STD_LOGIC;
signal \g81__149_carry__3_n_6\ : STD_LOGIC;
signal \g81__149_carry__3_n_7\ : STD_LOGIC;
signal \g81__149_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_2\ : STD_LOGIC;
signal \g81__149_carry__4_n_3\ : STD_LOGIC;
signal \g81__149_carry__4_n_5\ : STD_LOGIC;
signal \g81__149_carry__4_n_6\ : STD_LOGIC;
signal \g81__149_carry__4_n_7\ : STD_LOGIC;
signal \g81__149_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_1\ : STD_LOGIC;
signal \g81__149_carry_n_2\ : STD_LOGIC;
signal \g81__149_carry_n_3\ : STD_LOGIC;
signal \g81__206_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_1\ : STD_LOGIC;
signal \g81__206_carry__0_n_2\ : STD_LOGIC;
signal \g81__206_carry__0_n_3\ : STD_LOGIC;
signal \g81__206_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_1\ : STD_LOGIC;
signal \g81__206_carry__1_n_2\ : STD_LOGIC;
signal \g81__206_carry__1_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_1\ : STD_LOGIC;
signal \g81__206_carry__2_n_2\ : STD_LOGIC;
signal \g81__206_carry__2_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_n_4\ : STD_LOGIC;
signal \g81__206_carry__2_n_5\ : STD_LOGIC;
signal \g81__206_carry__2_n_6\ : STD_LOGIC;
signal \g81__206_carry__2_n_7\ : STD_LOGIC;
signal \g81__206_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_1\ : STD_LOGIC;
signal \g81__206_carry__3_n_2\ : STD_LOGIC;
signal \g81__206_carry__3_n_3\ : STD_LOGIC;
signal \g81__206_carry__3_n_4\ : STD_LOGIC;
signal \g81__206_carry__3_n_5\ : STD_LOGIC;
signal \g81__206_carry__3_n_6\ : STD_LOGIC;
signal \g81__206_carry__3_n_7\ : STD_LOGIC;
signal \g81__206_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_2\ : STD_LOGIC;
signal \g81__206_carry__4_n_3\ : STD_LOGIC;
signal \g81__206_carry__4_n_5\ : STD_LOGIC;
signal \g81__206_carry__4_n_6\ : STD_LOGIC;
signal \g81__206_carry__4_n_7\ : STD_LOGIC;
signal \g81__206_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_1\ : STD_LOGIC;
signal \g81__206_carry_n_2\ : STD_LOGIC;
signal \g81__206_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_1\ : STD_LOGIC;
signal \g81__22_carry__0_n_2\ : STD_LOGIC;
signal \g81__22_carry__0_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_n_4\ : STD_LOGIC;
signal \g81__22_carry__0_n_5\ : STD_LOGIC;
signal \g81__22_carry__0_n_6\ : STD_LOGIC;
signal \g81__22_carry__0_n_7\ : STD_LOGIC;
signal \g81__22_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_1\ : STD_LOGIC;
signal \g81__22_carry__1_n_2\ : STD_LOGIC;
signal \g81__22_carry__1_n_3\ : STD_LOGIC;
signal \g81__22_carry__1_n_4\ : STD_LOGIC;
signal \g81__22_carry__1_n_5\ : STD_LOGIC;
signal \g81__22_carry__1_n_6\ : STD_LOGIC;
signal \g81__22_carry__1_n_7\ : STD_LOGIC;
signal \g81__22_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_n_1\ : STD_LOGIC;
signal \g81__22_carry__2_n_3\ : STD_LOGIC;
signal \g81__22_carry__2_n_6\ : STD_LOGIC;
signal \g81__22_carry__2_n_7\ : STD_LOGIC;
signal \g81__22_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_1\ : STD_LOGIC;
signal \g81__22_carry_n_2\ : STD_LOGIC;
signal \g81__22_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry_n_4\ : STD_LOGIC;
signal \g81__22_carry_n_5\ : STD_LOGIC;
signal \g81__22_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_1\ : STD_LOGIC;
signal \g81__261_carry__0_n_2\ : STD_LOGIC;
signal \g81__261_carry__0_n_3\ : STD_LOGIC;
signal \g81__261_carry__0_n_4\ : STD_LOGIC;
signal \g81__261_carry__0_n_5\ : STD_LOGIC;
signal \g81__261_carry__0_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_n_7\ : STD_LOGIC;
signal \g81__261_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_1\ : STD_LOGIC;
signal \g81__261_carry__1_n_2\ : STD_LOGIC;
signal \g81__261_carry__1_n_3\ : STD_LOGIC;
signal \g81__261_carry__1_n_4\ : STD_LOGIC;
signal \g81__261_carry__1_n_5\ : STD_LOGIC;
signal \g81__261_carry__1_n_6\ : STD_LOGIC;
signal \g81__261_carry__1_n_7\ : STD_LOGIC;
signal \g81__261_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_n_1\ : STD_LOGIC;
signal \g81__261_carry__2_n_3\ : STD_LOGIC;
signal \g81__261_carry__2_n_6\ : STD_LOGIC;
signal \g81__261_carry__2_n_7\ : STD_LOGIC;
signal \g81__261_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_1\ : STD_LOGIC;
signal \g81__261_carry_n_2\ : STD_LOGIC;
signal \g81__261_carry_n_3\ : STD_LOGIC;
signal \g81__261_carry_n_4\ : STD_LOGIC;
signal \g81__261_carry_n_5\ : STD_LOGIC;
signal \g81__261_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry_n_7\ : STD_LOGIC;
signal \g81__301_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_1\ : STD_LOGIC;
signal \g81__301_carry__0_n_2\ : STD_LOGIC;
signal \g81__301_carry__0_n_3\ : STD_LOGIC;
signal \g81__301_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_1\ : STD_LOGIC;
signal \g81__301_carry__1_n_2\ : STD_LOGIC;
signal \g81__301_carry__1_n_3\ : STD_LOGIC;
signal \g81__301_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_1\ : STD_LOGIC;
signal \g81__301_carry__2_n_2\ : STD_LOGIC;
signal \g81__301_carry__2_n_3\ : STD_LOGIC;
signal \g81__301_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_1\ : STD_LOGIC;
signal \g81__301_carry__3_n_2\ : STD_LOGIC;
signal \g81__301_carry__3_n_3\ : STD_LOGIC;
signal \g81__301_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_1\ : STD_LOGIC;
signal \g81__301_carry__4_n_2\ : STD_LOGIC;
signal \g81__301_carry__4_n_3\ : STD_LOGIC;
signal \g81__301_carry__5_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_1\ : STD_LOGIC;
signal \g81__301_carry__5_n_2\ : STD_LOGIC;
signal \g81__301_carry__5_n_3\ : STD_LOGIC;
signal \g81__301_carry__6_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_n_1\ : STD_LOGIC;
signal \g81__301_carry__6_n_2\ : STD_LOGIC;
signal \g81__301_carry__6_n_3\ : STD_LOGIC;
signal \g81__301_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_1\ : STD_LOGIC;
signal \g81__301_carry_n_2\ : STD_LOGIC;
signal \g81__301_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_n_1\ : STD_LOGIC;
signal \g81__347_carry__0_n_2\ : STD_LOGIC;
signal \g81__347_carry__0_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_n_4\ : STD_LOGIC;
signal \g81__347_carry__0_n_5\ : STD_LOGIC;
signal \g81__347_carry__0_n_6\ : STD_LOGIC;
signal \g81__347_carry__0_n_7\ : STD_LOGIC;
signal \g81__347_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_1\ : STD_LOGIC;
signal \g81__347_carry_n_2\ : STD_LOGIC;
signal \g81__347_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry_n_4\ : STD_LOGIC;
signal \g81__347_carry_n_5\ : STD_LOGIC;
signal \g81__347_carry_n_6\ : STD_LOGIC;
signal \g81__347_carry_n_7\ : STD_LOGIC;
signal \g81__53_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_1\ : STD_LOGIC;
signal \g81__53_carry__0_n_2\ : STD_LOGIC;
signal \g81__53_carry__0_n_3\ : STD_LOGIC;
signal \g81__53_carry__0_n_4\ : STD_LOGIC;
signal \g81__53_carry__0_n_5\ : STD_LOGIC;
signal \g81__53_carry__0_n_6\ : STD_LOGIC;
signal \g81__53_carry__0_n_7\ : STD_LOGIC;
signal \g81__53_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_1\ : STD_LOGIC;
signal \g81__53_carry__1_n_2\ : STD_LOGIC;
signal \g81__53_carry__1_n_3\ : STD_LOGIC;
signal \g81__53_carry__1_n_4\ : STD_LOGIC;
signal \g81__53_carry__1_n_5\ : STD_LOGIC;
signal \g81__53_carry__1_n_6\ : STD_LOGIC;
signal \g81__53_carry__1_n_7\ : STD_LOGIC;
signal \g81__53_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_n_1\ : STD_LOGIC;
signal \g81__53_carry__2_n_3\ : STD_LOGIC;
signal \g81__53_carry__2_n_6\ : STD_LOGIC;
signal \g81__53_carry__2_n_7\ : STD_LOGIC;
signal \g81__53_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_1\ : STD_LOGIC;
signal \g81__53_carry_n_2\ : STD_LOGIC;
signal \g81__53_carry_n_3\ : STD_LOGIC;
signal \g81__53_carry_n_4\ : STD_LOGIC;
signal \g81__53_carry_n_5\ : STD_LOGIC;
signal \g81__53_carry_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_1\ : STD_LOGIC;
signal \g81__92_carry__0_n_2\ : STD_LOGIC;
signal \g81__92_carry__0_n_3\ : STD_LOGIC;
signal \g81__92_carry__0_n_4\ : STD_LOGIC;
signal \g81__92_carry__0_n_5\ : STD_LOGIC;
signal \g81__92_carry__0_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_n_7\ : STD_LOGIC;
signal \g81__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_1\ : STD_LOGIC;
signal \g81__92_carry__1_n_2\ : STD_LOGIC;
signal \g81__92_carry__1_n_3\ : STD_LOGIC;
signal \g81__92_carry__1_n_4\ : STD_LOGIC;
signal \g81__92_carry__1_n_5\ : STD_LOGIC;
signal \g81__92_carry__1_n_6\ : STD_LOGIC;
signal \g81__92_carry__1_n_7\ : STD_LOGIC;
signal \g81__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_n_1\ : STD_LOGIC;
signal \g81__92_carry__2_n_3\ : STD_LOGIC;
signal \g81__92_carry__2_n_6\ : STD_LOGIC;
signal \g81__92_carry__2_n_7\ : STD_LOGIC;
signal \g81__92_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_1\ : STD_LOGIC;
signal \g81__92_carry_n_2\ : STD_LOGIC;
signal \g81__92_carry_n_3\ : STD_LOGIC;
signal \g81__92_carry_n_4\ : STD_LOGIC;
signal \g81__92_carry_n_5\ : STD_LOGIC;
signal \g81__92_carry_n_6\ : STD_LOGIC;
signal \g81_carry__0_i_10_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_11_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_12_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_13_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_14_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_15_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_1\ : STD_LOGIC;
signal \g81_carry__0_n_2\ : STD_LOGIC;
signal \g81_carry__0_n_3\ : STD_LOGIC;
signal \g81_carry__0_n_4\ : STD_LOGIC;
signal \g81_carry__0_n_5\ : STD_LOGIC;
signal \g81_carry__0_n_6\ : STD_LOGIC;
signal \g81_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_1\ : STD_LOGIC;
signal \g81_carry__1_n_2\ : STD_LOGIC;
signal \g81_carry__1_n_3\ : STD_LOGIC;
signal \g81_carry__1_n_4\ : STD_LOGIC;
signal \g81_carry__1_n_5\ : STD_LOGIC;
signal \g81_carry__1_n_6\ : STD_LOGIC;
signal \g81_carry__1_n_7\ : STD_LOGIC;
signal \g81_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__2_n_1\ : STD_LOGIC;
signal \g81_carry__2_n_3\ : STD_LOGIC;
signal \g81_carry__2_n_6\ : STD_LOGIC;
signal \g81_carry__2_n_7\ : STD_LOGIC;
signal g81_carry_i_1_n_0 : STD_LOGIC;
signal g81_carry_i_2_n_0 : STD_LOGIC;
signal g81_carry_i_3_n_0 : STD_LOGIC;
signal g81_carry_i_4_n_0 : STD_LOGIC;
signal g81_carry_i_5_n_0 : STD_LOGIC;
signal g81_carry_i_6_n_0 : STD_LOGIC;
signal g81_carry_i_7_n_0 : STD_LOGIC;
signal g81_carry_n_0 : STD_LOGIC;
signal g81_carry_n_1 : STD_LOGIC;
signal g81_carry_n_2 : STD_LOGIC;
signal g81_carry_n_3 : STD_LOGIC;
signal g81_carry_n_7 : STD_LOGIC;
signal g83 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \g83__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_1\ : STD_LOGIC;
signal \g83__0_carry__0_n_2\ : STD_LOGIC;
signal \g83__0_carry__0_n_3\ : STD_LOGIC;
signal \g83__0_carry__0_n_4\ : STD_LOGIC;
signal \g83__0_carry__0_n_5\ : STD_LOGIC;
signal \g83__0_carry__0_n_6\ : STD_LOGIC;
signal \g83__0_carry__0_n_7\ : STD_LOGIC;
signal \g83__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__1_n_2\ : STD_LOGIC;
signal \g83__0_carry__1_n_7\ : STD_LOGIC;
signal \g83__0_carry_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_1\ : STD_LOGIC;
signal \g83__0_carry_n_2\ : STD_LOGIC;
signal \g83__0_carry_n_3\ : STD_LOGIC;
signal \g83__0_carry_n_4\ : STD_LOGIC;
signal \g83__0_carry_n_5\ : STD_LOGIC;
signal \g83__0_carry_n_6\ : STD_LOGIC;
signal \g83__0_carry_n_7\ : STD_LOGIC;
signal g84 : STD_LOGIC;
signal \g84_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g84_carry__0_i_2_n_0\ : STD_LOGIC;
signal g84_carry_i_1_n_0 : STD_LOGIC;
signal g84_carry_i_2_n_0 : STD_LOGIC;
signal g84_carry_i_3_n_0 : STD_LOGIC;
signal g84_carry_i_4_n_0 : STD_LOGIC;
signal g84_carry_i_5_n_0 : STD_LOGIC;
signal g84_carry_i_6_n_0 : STD_LOGIC;
signal g84_carry_i_7_n_0 : STD_LOGIC;
signal g84_carry_i_8_n_0 : STD_LOGIC;
signal g84_carry_n_0 : STD_LOGIC;
signal g84_carry_n_1 : STD_LOGIC;
signal g84_carry_n_2 : STD_LOGIC;
signal g84_carry_n_3 : STD_LOGIC;
signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__120_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__149_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__149_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__206_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__206_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__22_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__22_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__22_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__261_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__261_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__301_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__301_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__347_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__53_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__53_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__53_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__92_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__92_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_g81_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g83__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g83__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_g84_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g84_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g84_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute HLUTNM : string;
attribute HLUTNM of \g81__120_carry__1_i_1\ : label is "lutpair7";
attribute HLUTNM of \g81__149_carry__0_i_1\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_2\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__0_i_5\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__0_i_6\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_7\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__1_i_1\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_2\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_3\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__1_i_4\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__1_i_5\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__1_i_6\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_7\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_8\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__2_i_1\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_2\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_3\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__2_i_4\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__2_i_5\ : label is "lutpair17";
attribute HLUTNM of \g81__149_carry__2_i_6\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_7\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_8\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__3_i_1\ : label is "lutpair17";
attribute HLUTNM of \g81__206_carry__0_i_1\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_2\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__0_i_5\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__0_i_6\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_7\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__1_i_1\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_2\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_3\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__1_i_4\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__1_i_5\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__1_i_6\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_7\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_8\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__2_i_1\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__2_i_4\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__2_i_6\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__3_i_1\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_3\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__3_i_6\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_8\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__4_i_2\ : label is "lutpair26";
attribute HLUTNM of \g81__206_carry__4_i_6\ : label is "lutpair26";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \g81_carry__0_i_10\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_11\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \g81_carry__0_i_13\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_14\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_15\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__0_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__1_i_9\ : label is "soft_lutpair3";
attribute HLUTNM of \g81_carry__2_i_2\ : label is "lutpair7";
attribute HLUTNM of \g83__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \g83__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_7\ : label is "lutpair0";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(4 downto 1),
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => \_carry_i_5_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_4\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_6\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3 downto 2) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \_carry__1_n_2\,
CO(0) => \NLW__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => g83(9),
S(3 downto 1) => B"001",
S(0) => \_carry__1_i_1_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_2\,
O => \_carry__1_i_1_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
O => \_carry_i_1_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_4\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_6\,
O => \_carry_i_5_n_0\
);
\g81__120_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__120_carry_n_0\,
CO(2) => \g81__120_carry_n_1\,
CO(1) => \g81__120_carry_n_2\,
CO(0) => \g81__120_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__120_carry_i_1_n_0\,
DI(1) => \g81__120_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__120_carry_n_4\,
O(2) => \g81__120_carry_n_5\,
O(1) => \g81__120_carry_n_6\,
O(0) => \NLW_g81__120_carry_O_UNCONNECTED\(0),
S(3) => \g81__120_carry_i_3_n_0\,
S(2) => \g81__120_carry_i_4_n_0\,
S(1) => \g81__120_carry_i_5_n_0\,
S(0) => \g81__120_carry_i_6_n_0\
);
\g81__120_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry_n_0\,
CO(3) => \g81__120_carry__0_n_0\,
CO(2) => \g81__120_carry__0_n_1\,
CO(1) => \g81__120_carry__0_n_2\,
CO(0) => \g81__120_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__120_carry__0_n_4\,
O(2) => \g81__120_carry__0_n_5\,
O(1) => \g81__120_carry__0_n_6\,
O(0) => \g81__120_carry__0_n_7\,
S(3) => \g81__120_carry__0_i_1_n_0\,
S(2) => \g81__120_carry__0_i_2_n_0\,
S(1) => \g81__120_carry__0_i_3_n_0\,
S(0) => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__120_carry__0_i_1_n_0\
);
\g81__120_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__120_carry__0_i_2_n_0\
);
\g81__120_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__120_carry__0_i_3_n_0\
);
\g81__120_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__0_n_0\,
CO(3) => \g81__120_carry__1_n_0\,
CO(2) => \g81__120_carry__1_n_1\,
CO(1) => \g81__120_carry__1_n_2\,
CO(0) => \g81__120_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__120_carry__1_n_4\,
O(2) => \g81__120_carry__1_n_5\,
O(1) => \g81__120_carry__1_n_6\,
O(0) => \g81__120_carry__1_n_7\,
S(3) => \g81__120_carry__1_i_1_n_0\,
S(2) => \g81__120_carry__1_i_2_n_0\,
S(1) => \g81__120_carry__1_i_3_n_0\,
S(0) => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"369C"
)
port map (
I0 => g84,
I1 => \g81_carry__1_i_1_n_0\,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__120_carry__1_i_1_n_0\
);
\g81__120_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_2_n_0\
);
\g81__120_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_3_n_0\
);
\g81__120_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__1_n_0\,
CO(3) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__120_carry__2_n_1\,
CO(1) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__120_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__120_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__120_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__120_carry__2_n_6\,
O(0) => \g81__120_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__120_carry__2_i_1_n_0\
);
\g81__120_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__120_carry_i_1_n_0\
);
\g81__120_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__120_carry_i_2_n_0\
);
\g81__120_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__120_carry_i_3_n_0\
);
\g81__120_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__120_carry_i_4_n_0\
);
\g81__120_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__120_carry_i_5_n_0\
);
\g81__120_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__120_carry_i_6_n_0\
);
\g81__149_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__149_carry_n_0\,
CO(2) => \g81__149_carry_n_1\,
CO(1) => \g81__149_carry_n_2\,
CO(0) => \g81__149_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry_i_1_n_0\,
DI(2) => \g81__149_carry_i_2_n_0\,
DI(1) => \g81__149_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__149_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry_i_4_n_0\,
S(2) => \g81__149_carry_i_5_n_0\,
S(1) => \g81__149_carry_i_6_n_0\,
S(0) => \g81__149_carry_i_7_n_0\
);
\g81__149_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry_n_0\,
CO(3) => \g81__149_carry__0_n_0\,
CO(2) => \g81__149_carry__0_n_1\,
CO(1) => \g81__149_carry__0_n_2\,
CO(0) => \g81__149_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__0_i_1_n_0\,
DI(2) => \g81__149_carry__0_i_2_n_0\,
DI(1) => \g81__149_carry__0_i_3_n_0\,
DI(0) => \g81__149_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__0_i_5_n_0\,
S(2) => \g81__149_carry__0_i_6_n_0\,
S(1) => \g81__149_carry__0_i_7_n_0\,
S(0) => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
O => \g81__149_carry__0_i_1_n_0\
);
\g81__149_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
O => \g81__149_carry__0_i_2_n_0\
);
\g81__149_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_6\,
I1 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_3_n_0\
);
\g81__149_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
O => \g81__149_carry__0_i_4_n_0\
);
\g81__149_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
I3 => \g81__149_carry__0_i_1_n_0\,
O => \g81__149_carry__0_i_5_n_0\
);
\g81__149_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
I3 => \g81__149_carry__0_i_2_n_0\,
O => \g81__149_carry__0_i_6_n_0\
);
\g81__149_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
I2 => \g81_carry__1_n_6\,
I3 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_7_n_0\
);
\g81__149_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
I2 => \g81__22_carry_n_4\,
I3 => \g81_carry__1_n_6\,
O => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__0_n_0\,
CO(3) => \g81__149_carry__1_n_0\,
CO(2) => \g81__149_carry__1_n_1\,
CO(1) => \g81__149_carry__1_n_2\,
CO(0) => \g81__149_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__1_i_1_n_0\,
DI(2) => \g81__149_carry__1_i_2_n_0\,
DI(1) => \g81__149_carry__1_i_3_n_0\,
DI(0) => \g81__149_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__1_i_5_n_0\,
S(2) => \g81__149_carry__1_i_6_n_0\,
S(1) => \g81__149_carry__1_i_7_n_0\,
S(0) => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__1_i_1_n_0\
);
\g81__149_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
O => \g81__149_carry__1_i_2_n_0\
);
\g81__149_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
O => \g81__149_carry__1_i_3_n_0\
);
\g81__149_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
O => \g81__149_carry__1_i_4_n_0\
);
\g81__149_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_1_n_0\,
O => \g81__149_carry__1_i_5_n_0\
);
\g81__149_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_2_n_0\,
O => \g81__149_carry__1_i_6_n_0\
);
\g81__149_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
I3 => \g81__149_carry__1_i_3_n_0\,
O => \g81__149_carry__1_i_7_n_0\
);
\g81__149_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
I3 => \g81__149_carry__1_i_4_n_0\,
O => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__1_n_0\,
CO(3) => \g81__149_carry__2_n_0\,
CO(2) => \g81__149_carry__2_n_1\,
CO(1) => \g81__149_carry__2_n_2\,
CO(0) => \g81__149_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__2_i_1_n_0\,
DI(2) => \g81__149_carry__2_i_2_n_0\,
DI(1) => \g81__149_carry__2_i_3_n_0\,
DI(0) => \g81__149_carry__2_i_4_n_0\,
O(3) => \g81__149_carry__2_n_4\,
O(2) => \g81__149_carry__2_n_5\,
O(1) => \g81__149_carry__2_n_6\,
O(0) => \g81__149_carry__2_n_7\,
S(3) => \g81__149_carry__2_i_5_n_0\,
S(2) => \g81__149_carry__2_i_6_n_0\,
S(1) => \g81__149_carry__2_i_7_n_0\,
S(0) => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_1_n_0\
);
\g81__149_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_2_n_0\
);
\g81__149_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_3_n_0\
);
\g81__149_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_4_n_0\
);
\g81__149_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_1_n_0\,
O => \g81__149_carry__2_i_5_n_0\
);
\g81__149_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_2_n_0\,
O => \g81__149_carry__2_i_6_n_0\
);
\g81__149_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_3_n_0\,
O => \g81__149_carry__2_i_7_n_0\
);
\g81__149_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_4_n_0\,
O => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__2_n_0\,
CO(3) => \g81__149_carry__3_n_0\,
CO(2) => \g81__149_carry__3_n_1\,
CO(1) => \g81__149_carry__3_n_2\,
CO(0) => \g81__149_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__2_i_2_n_0\,
DI(2) => \g81_carry__2_i_2_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81__149_carry__3_i_1_n_0\,
O(3) => \g81__149_carry__3_n_4\,
O(2) => \g81__149_carry__3_n_5\,
O(1) => \g81__149_carry__3_n_6\,
O(0) => \g81__149_carry__3_n_7\,
S(3) => \g81__149_carry__3_i_2_n_0\,
S(2) => \g81__149_carry__3_i_3_n_0\,
S(1) => \g81__149_carry__3_i_4_n_0\,
S(0) => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__3_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__3_i_1_n_0\
);
\g81__149_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_7\,
O => \g81__149_carry__3_i_2_n_0\
);
\g81__149_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_4\,
O => \g81__149_carry__3_i_3_n_0\
);
\g81__149_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_5\,
O => \g81__149_carry__3_i_4_n_0\
);
\g81__149_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__149_carry__3_i_1_n_0\,
I1 => \g81__53_carry__1_n_6\,
O => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__3_n_0\,
CO(3) => \g81__149_carry__4_n_0\,
CO(2) => \NLW_g81__149_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__149_carry__4_n_2\,
CO(0) => \g81__149_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__149_carry__4_i_1_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3) => \NLW_g81__149_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__149_carry__4_n_5\,
O(1) => \g81__149_carry__4_n_6\,
O(0) => \g81__149_carry__4_n_7\,
S(3 downto 2) => B"10",
S(1) => \g81__149_carry__4_i_2_n_0\,
S(0) => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__149_carry__4_i_1_n_0\
);
\g81__149_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_1\,
O => \g81__149_carry__4_i_2_n_0\
);
\g81__149_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_6\,
O => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
O => \g81__149_carry_i_1_n_0\
);
\g81__149_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
O => \g81__149_carry_i_2_n_0\
);
\g81__149_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_3_n_0\
);
\g81__149_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
I2 => \g81__22_carry_n_5\,
I3 => \g81_carry__1_n_7\,
O => \g81__149_carry_i_4_n_0\
);
\g81__149_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__22_carry_n_6\,
I3 => \g81_carry__0_n_4\,
O => \g81__149_carry_i_5_n_0\
);
\g81__149_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g81_carry__0_n_5\,
O => \g81__149_carry_i_6_n_0\
);
\g81__149_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_7_n_0\
);
\g81__206_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__206_carry_n_0\,
CO(2) => \g81__206_carry_n_1\,
CO(1) => \g81__206_carry_n_2\,
CO(0) => \g81__206_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry_i_1_n_0\,
DI(2) => \g81__206_carry_i_2_n_0\,
DI(1) => \g81__206_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__206_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry_i_4_n_0\,
S(2) => \g81__206_carry_i_5_n_0\,
S(1) => \g81__206_carry_i_6_n_0\,
S(0) => \g81__206_carry_i_7_n_0\
);
\g81__206_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry_n_0\,
CO(3) => \g81__206_carry__0_n_0\,
CO(2) => \g81__206_carry__0_n_1\,
CO(1) => \g81__206_carry__0_n_2\,
CO(0) => \g81__206_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__0_i_1_n_0\,
DI(2) => \g81__206_carry__0_i_2_n_0\,
DI(1) => \g81__206_carry__0_i_3_n_0\,
DI(0) => \g81__206_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__0_i_5_n_0\,
S(2) => \g81__206_carry__0_i_6_n_0\,
S(1) => \g81__206_carry__0_i_7_n_0\,
S(0) => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
O => \g81__206_carry__0_i_1_n_0\
);
\g81__206_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
O => \g81__206_carry__0_i_2_n_0\
);
\g81__206_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_4\,
I1 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_3_n_0\
);
\g81__206_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
O => \g81__206_carry__0_i_4_n_0\
);
\g81__206_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
I3 => \g81__206_carry__0_i_1_n_0\,
O => \g81__206_carry__0_i_5_n_0\
);
\g81__206_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
I3 => \g81__206_carry__0_i_2_n_0\,
O => \g81__206_carry__0_i_6_n_0\
);
\g81__206_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
I2 => \g81__92_carry_n_4\,
I3 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_7_n_0\
);
\g81__206_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
I2 => \g81__149_carry__3_n_7\,
I3 => \g81__92_carry_n_4\,
O => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__0_n_0\,
CO(3) => \g81__206_carry__1_n_0\,
CO(2) => \g81__206_carry__1_n_1\,
CO(1) => \g81__206_carry__1_n_2\,
CO(0) => \g81__206_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__1_i_1_n_0\,
DI(2) => \g81__206_carry__1_i_2_n_0\,
DI(1) => \g81__206_carry__1_i_3_n_0\,
DI(0) => \g81__206_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__1_i_5_n_0\,
S(2) => \g81__206_carry__1_i_6_n_0\,
S(1) => \g81__206_carry__1_i_7_n_0\,
S(0) => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
O => \g81__206_carry__1_i_1_n_0\
);
\g81__206_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
O => \g81__206_carry__1_i_2_n_0\
);
\g81__206_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
O => \g81__206_carry__1_i_3_n_0\
);
\g81__206_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
O => \g81__206_carry__1_i_4_n_0\
);
\g81__206_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
I3 => \g81__206_carry__1_i_1_n_0\,
O => \g81__206_carry__1_i_5_n_0\
);
\g81__206_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
I3 => \g81__206_carry__1_i_2_n_0\,
O => \g81__206_carry__1_i_6_n_0\
);
\g81__206_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
I3 => \g81__206_carry__1_i_3_n_0\,
O => \g81__206_carry__1_i_7_n_0\
);
\g81__206_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
I3 => \g81__206_carry__1_i_4_n_0\,
O => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__1_n_0\,
CO(3) => \g81__206_carry__2_n_0\,
CO(2) => \g81__206_carry__2_n_1\,
CO(1) => \g81__206_carry__2_n_2\,
CO(0) => \g81__206_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_i_1_n_0\,
DI(2) => \g81__206_carry__2_i_2_n_0\,
DI(1) => \g81__206_carry__2_i_3_n_0\,
DI(0) => \g81__206_carry__2_i_4_n_0\,
O(3) => \g81__206_carry__2_n_4\,
O(2) => \g81__206_carry__2_n_5\,
O(1) => \g81__206_carry__2_n_6\,
O(0) => \g81__206_carry__2_n_7\,
S(3) => \g81__206_carry__2_i_5_n_0\,
S(2) => \g81__206_carry__2_i_6_n_0\,
S(1) => \g81__206_carry__2_i_7_n_0\,
S(0) => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
O => \g81__206_carry__2_i_1_n_0\
);
\g81__206_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry__2_n_7\,
I1 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_2_n_0\
);
\g81__206_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__0_n_6\,
I3 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_3_n_0\
);
\g81__206_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
O => \g81__206_carry__2_i_4_n_0\
);
\g81__206_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_1_n_0\,
I1 => \g81__120_carry__1_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__2_i_5_n_0\
);
\g81__206_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
I2 => \g81__92_carry__2_n_7\,
I3 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_6_n_0\
);
\g81__206_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"888E77717771888E"
)
port map (
I0 => \g81__92_carry__1_n_4\,
I1 => \g81__120_carry__0_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
I4 => \g81__120_carry__0_n_5\,
I5 => \g81__92_carry__2_n_7\,
O => \g81__206_carry__2_i_7_n_0\
);
\g81__206_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_4_n_0\,
I1 => \g81__120_carry__0_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__2_n_0\,
CO(3) => \g81__206_carry__3_n_0\,
CO(2) => \g81__206_carry__3_n_1\,
CO(1) => \g81__206_carry__3_n_2\,
CO(0) => \g81__206_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_i_1_n_0\,
DI(2) => \g81__206_carry__3_i_2_n_0\,
DI(1) => \g81__206_carry__3_i_3_n_0\,
DI(0) => \g81__206_carry__3_i_4_n_0\,
O(3) => \g81__206_carry__3_n_4\,
O(2) => \g81__206_carry__3_n_5\,
O(1) => \g81__206_carry__3_n_6\,
O(0) => \g81__206_carry__3_n_7\,
S(3) => \g81__206_carry__3_i_5_n_0\,
S(2) => \g81__206_carry__3_i_6_n_0\,
S(1) => \g81__206_carry__3_i_7_n_0\,
S(0) => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_1_n_0\
);
\g81__206_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__3_i_2_n_0\
);
\g81__206_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_3_n_0\
);
\g81__206_carry__3_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__1_n_7\,
I3 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__3_i_4_n_0\
);
\g81__206_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_1_n_0\,
I1 => \g81__120_carry__2_n_7\,
O => \g81__206_carry__3_i_5_n_0\
);
\g81__206_carry__3_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__1_n_4\,
O => \g81__206_carry__3_i_6_n_0\
);
\g81__206_carry__3_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_3_n_0\,
I1 => \g81__120_carry__1_n_5\,
O => \g81__206_carry__3_i_7_n_0\
);
\g81__206_carry__3_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"56AAAAA9"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
I3 => \g81__92_carry__2_n_1\,
I4 => \g81__120_carry__1_n_7\,
O => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__3_n_0\,
CO(3) => \g81__206_carry__4_n_0\,
CO(2) => \NLW_g81__206_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__206_carry__4_n_2\,
CO(0) => \g81__206_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__206_carry__4_i_1_n_0\,
DI(1) => \g81__206_carry__4_i_2_n_0\,
DI(0) => \g81__206_carry__4_i_3_n_0\,
O(3) => \NLW_g81__206_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__206_carry__4_n_5\,
O(1) => \g81__206_carry__4_n_6\,
O(0) => \g81__206_carry__4_n_7\,
S(3) => '1',
S(2) => \g81__206_carry__4_i_4_n_0\,
S(1) => \g81__206_carry__4_i_5_n_0\,
S(0) => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_1_n_0\
);
\g81__206_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__4_i_2_n_0\
);
\g81__206_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_3_n_0\
);
\g81__206_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_4_n_0\
);
\g81__206_carry__4_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__4_i_2_n_0\,
I1 => \g81__120_carry__2_n_1\,
O => \g81__206_carry__4_i_5_n_0\
);
\g81__206_carry__4_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__2_n_6\,
O => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
O => \g81__206_carry_i_1_n_0\
);
\g81__206_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
O => \g81__206_carry_i_2_n_0\
);
\g81__206_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_3_n_0\
);
\g81__206_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
I2 => \g81__149_carry__2_n_4\,
I3 => \g81__92_carry_n_5\,
O => \g81__206_carry_i_4_n_0\
);
\g81__206_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
I2 => \g81__149_carry__2_n_5\,
I3 => \g81__92_carry_n_6\,
O => \g81__206_carry_i_5_n_0\
);
\g81__206_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
I2 => \g81__149_carry__2_n_6\,
I3 => g81_carry_n_7,
O => \g81__206_carry_i_6_n_0\
);
\g81__206_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_7_n_0\
);
\g81__22_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__22_carry_n_0\,
CO(2) => \g81__22_carry_n_1\,
CO(1) => \g81__22_carry_n_2\,
CO(0) => \g81__22_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__22_carry_i_1_n_0\,
DI(1) => \g81__22_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__22_carry_n_4\,
O(2) => \g81__22_carry_n_5\,
O(1) => \g81__22_carry_n_6\,
O(0) => \NLW_g81__22_carry_O_UNCONNECTED\(0),
S(3) => \g81__22_carry_i_3_n_0\,
S(2) => \g81__22_carry_i_4_n_0\,
S(1) => \g81__22_carry_i_5_n_0\,
S(0) => \g81__22_carry_i_6_n_0\
);
\g81__22_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry_n_0\,
CO(3) => \g81__22_carry__0_n_0\,
CO(2) => \g81__22_carry__0_n_1\,
CO(1) => \g81__22_carry__0_n_2\,
CO(0) => \g81__22_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__22_carry__0_n_4\,
O(2) => \g81__22_carry__0_n_5\,
O(1) => \g81__22_carry__0_n_6\,
O(0) => \g81__22_carry__0_n_7\,
S(3) => \g81__22_carry__0_i_1_n_0\,
S(2) => \g81__22_carry__0_i_2_n_0\,
S(1) => \g81__22_carry__0_i_3_n_0\,
S(0) => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__22_carry__0_i_1_n_0\
);
\g81__22_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__22_carry__0_i_2_n_0\
);
\g81__22_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__22_carry__0_i_3_n_0\
);
\g81__22_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__0_n_0\,
CO(3) => \g81__22_carry__1_n_0\,
CO(2) => \g81__22_carry__1_n_1\,
CO(1) => \g81__22_carry__1_n_2\,
CO(0) => \g81__22_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__22_carry__1_n_4\,
O(2) => \g81__22_carry__1_n_5\,
O(1) => \g81__22_carry__1_n_6\,
O(0) => \g81__22_carry__1_n_7\,
S(3) => \g81__22_carry__1_i_1_n_0\,
S(2) => \g81__22_carry__1_i_2_n_0\,
S(1) => \g81__22_carry__1_i_3_n_0\,
S(0) => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__22_carry__1_i_1_n_0\
);
\g81__22_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_2_n_0\
);
\g81__22_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_3_n_0\
);
\g81__22_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__1_n_0\,
CO(3) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__22_carry__2_n_1\,
CO(1) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__22_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__22_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__22_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__22_carry__2_n_6\,
O(0) => \g81__22_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__22_carry__2_i_1_n_0\
);
\g81__22_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__22_carry_i_1_n_0\
);
\g81__22_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__22_carry_i_2_n_0\
);
\g81__22_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__22_carry_i_3_n_0\
);
\g81__22_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__22_carry_i_4_n_0\
);
\g81__22_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__22_carry_i_5_n_0\
);
\g81__22_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__22_carry_i_6_n_0\
);
\g81__261_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__261_carry_n_0\,
CO(2) => \g81__261_carry_n_1\,
CO(1) => \g81__261_carry_n_2\,
CO(0) => \g81__261_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_n_6\,
DI(2) => \g81__206_carry__2_n_7\,
DI(1 downto 0) => B"01",
O(3) => \g81__261_carry_n_4\,
O(2) => \g81__261_carry_n_5\,
O(1) => \g81__261_carry_n_6\,
O(0) => \g81__261_carry_n_7\,
S(3) => \g81__261_carry_i_1_n_0\,
S(2) => \g81__261_carry_i_2_n_0\,
S(1) => \g81__261_carry_i_3_n_0\,
S(0) => \g81__261_carry_i_4_n_0\
);
\g81__261_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry_n_0\,
CO(3) => \g81__261_carry__0_n_0\,
CO(2) => \g81__261_carry__0_n_1\,
CO(1) => \g81__261_carry__0_n_2\,
CO(0) => \g81__261_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_n_6\,
DI(2) => \g81__206_carry__3_n_7\,
DI(1) => \g81__206_carry__2_n_4\,
DI(0) => \g81__206_carry__2_n_5\,
O(3) => \g81__261_carry__0_n_4\,
O(2) => \g81__261_carry__0_n_5\,
O(1) => \g81__261_carry__0_n_6\,
O(0) => \g81__261_carry__0_n_7\,
S(3) => \g81__261_carry__0_i_1_n_0\,
S(2) => \g81__261_carry__0_i_2_n_0\,
S(1) => \g81__261_carry__0_i_3_n_0\,
S(0) => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__206_carry__3_n_4\,
O => \g81__261_carry__0_i_1_n_0\
);
\g81__261_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__206_carry__3_n_5\,
O => \g81__261_carry__0_i_2_n_0\
);
\g81__261_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__206_carry__3_n_6\,
O => \g81__261_carry__0_i_3_n_0\
);
\g81__261_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__206_carry__3_n_7\,
O => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__0_n_0\,
CO(3) => \g81__261_carry__1_n_0\,
CO(2) => \g81__261_carry__1_n_1\,
CO(1) => \g81__261_carry__1_n_2\,
CO(0) => \g81__261_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__4_n_6\,
DI(2) => \g81__206_carry__4_n_7\,
DI(1) => \g81__206_carry__3_n_4\,
DI(0) => \g81__206_carry__3_n_5\,
O(3) => \g81__261_carry__1_n_4\,
O(2) => \g81__261_carry__1_n_5\,
O(1) => \g81__261_carry__1_n_6\,
O(0) => \g81__261_carry__1_n_7\,
S(3) => \g81__261_carry__1_i_1_n_0\,
S(2) => \g81__261_carry__1_i_2_n_0\,
S(1) => \g81__261_carry__1_i_3_n_0\,
S(0) => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_6\,
I1 => \g81__206_carry__4_n_0\,
O => \g81__261_carry__1_i_1_n_0\
);
\g81__261_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_7\,
I1 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__1_i_2_n_0\
);
\g81__261_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__206_carry__4_n_6\,
O => \g81__261_carry__1_i_3_n_0\
);
\g81__261_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__206_carry__4_n_7\,
O => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__1_n_0\,
CO(3) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__261_carry__2_n_1\,
CO(1) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__261_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__206_carry__4_n_0\,
DI(0) => \g81__206_carry__4_n_5\,
O(3 downto 2) => \NLW_g81__261_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__261_carry__2_n_6\,
O(0) => \g81__261_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \g81__261_carry__2_i_1_n_0\,
S(0) => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \g81__206_carry__4_n_0\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__261_carry__2_i_1_n_0\
);
\g81__261_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__206_carry__2_n_4\,
O => \g81__261_carry_i_1_n_0\
);
\g81__261_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__206_carry__2_n_5\,
O => \g81__261_carry_i_2_n_0\
);
\g81__261_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__261_carry_i_3_n_0\
);
\g81__261_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__261_carry_i_4_n_0\
);
\g81__301_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__301_carry_n_0\,
CO(2) => \g81__301_carry_n_1\,
CO(1) => \g81__301_carry_n_2\,
CO(0) => \g81__301_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry_i_1_n_0\,
DI(2) => \g81__301_carry_i_2_n_0\,
DI(1) => \g81__301_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__301_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry_i_4_n_0\,
S(2) => \g81__301_carry_i_5_n_0\,
S(1) => \g81__301_carry_i_6_n_0\,
S(0) => \g81__301_carry_i_7_n_0\
);
\g81__301_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry_n_0\,
CO(3) => \g81__301_carry__0_n_0\,
CO(2) => \g81__301_carry__0_n_1\,
CO(1) => \g81__301_carry__0_n_2\,
CO(0) => \g81__301_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__0_i_1_n_0\,
DI(2) => \g81__301_carry__0_i_2_n_0\,
DI(1) => \g81__301_carry__0_i_3_n_0\,
DI(0) => \g81__301_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__0_i_5_n_0\,
S(2) => \g81__301_carry__0_i_6_n_0\,
S(1) => \g81__301_carry__0_i_7_n_0\,
S(0) => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_5\,
I1 => g84,
I2 => g83(6),
I3 => \g83__0_carry__0_n_5\,
O => \g81__301_carry__0_i_1_n_0\
);
\g81__301_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_6\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
O => \g81__301_carry__0_i_2_n_0\
);
\g81__301_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_7\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
O => \g81__301_carry__0_i_3_n_0\
);
\g81__301_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_4\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
O => \g81__301_carry__0_i_4_n_0\
);
\g81__301_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
I3 => \g81__261_carry__0_n_5\,
I4 => \g81__261_carry__0_n_4\,
I5 => \g81_carry__1_i_9_n_0\,
O => \g81__301_carry__0_i_5_n_0\
);
\g81__301_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
I3 => \g81__261_carry__0_n_6\,
I4 => \g81__261_carry__0_n_5\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__301_carry__0_i_6_n_0\
);
\g81__301_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
I3 => \g81__261_carry__0_n_7\,
I4 => \g81__261_carry__0_n_6\,
I5 => \g81_carry__0_i_14_n_0\,
O => \g81__301_carry__0_i_7_n_0\
);
\g81__301_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => \g81__261_carry_n_4\,
I2 => \g81__261_carry__0_n_7\,
I3 => \g83__0_carry__0_n_7\,
I4 => g83(4),
I5 => g84,
O => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__0_n_0\,
CO(3) => \g81__301_carry__1_n_0\,
CO(2) => \g81__301_carry__1_n_1\,
CO(1) => \g81__301_carry__1_n_2\,
CO(0) => \g81__301_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__1_i_1_n_0\,
DI(2) => \g81__301_carry__1_i_2_n_0\,
DI(1) => \g81__301_carry__1_i_3_n_0\,
DI(0) => \g81__301_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__1_i_5_n_0\,
S(2) => \g81__301_carry__1_i_6_n_0\,
S(1) => \g81__301_carry__1_i_7_n_0\,
S(0) => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__1_i_1_n_0\
);
\g81__301_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_6\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__301_carry__1_i_2_n_0\
);
\g81__301_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_7\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__301_carry__1_i_3_n_0\
);
\g81__301_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_4\,
I1 => g84,
I2 => g83(7),
I3 => \g83__0_carry__0_n_4\,
O => \g81__301_carry__1_i_4_n_0\
);
\g81__301_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \g81__261_carry__1_n_4\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_5_n_0\
);
\g81__301_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"50AF30CF50AFCF30"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => \g81__261_carry__1_n_6\,
I3 => \g81__261_carry__1_n_5\,
I4 => g84,
I5 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_6_n_0\
);
\g81__301_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => g83(8),
I2 => g84,
I3 => \g81__261_carry__1_n_7\,
I4 => \g81__261_carry__1_n_6\,
I5 => \g81__301_carry__1_i_9_n_0\,
O => \g81__301_carry__1_i_7_n_0\
);
\g81__301_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__1_i_9_n_0\,
I1 => \g81__261_carry__0_n_4\,
I2 => \g81__261_carry__1_n_7\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => g84,
O => \g81__301_carry__1_i_9_n_0\
);
\g81__301_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__1_n_0\,
CO(3) => \g81__301_carry__2_n_0\,
CO(2) => \g81__301_carry__2_n_1\,
CO(1) => \g81__301_carry__2_n_2\,
CO(0) => \g81__301_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__2_i_1_n_0\,
DI(2) => \g81__301_carry__2_i_2_n_0\,
DI(1) => \g81__301_carry__2_i_3_n_0\,
DI(0) => \g81__301_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__2_i_5_n_0\,
S(2) => \g81__301_carry__2_i_6_n_0\,
S(1) => \g81__301_carry__2_i_7_n_0\,
S(0) => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__2_i_1_n_0\
);
\g81__301_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_2_n_0\
);
\g81__301_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_3_n_0\
);
\g81__301_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_4_n_0\
);
\g81__301_carry__2_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_5_n_0\
);
\g81__301_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6663"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \g81__261_carry__2_n_1\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_6_n_0\
);
\g81__301_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \g81__261_carry__2_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_7_n_0\
);
\g81__301_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \g81__261_carry__2_n_7\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__2_n_0\,
CO(3) => \g81__301_carry__3_n_0\,
CO(2) => \g81__301_carry__3_n_1\,
CO(1) => \g81__301_carry__3_n_2\,
CO(0) => \g81__301_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__3_i_1_n_0\,
DI(2) => \g81__301_carry__3_i_2_n_0\,
DI(1) => \g81__301_carry__3_i_3_n_0\,
DI(0) => \g81__301_carry__3_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__3_i_5_n_0\,
S(2) => \g81__301_carry__3_i_6_n_0\,
S(1) => \g81__301_carry__3_i_7_n_0\,
S(0) => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_1_n_0\
);
\g81__301_carry__3_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_2_n_0\
);
\g81__301_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_3_n_0\
);
\g81__301_carry__3_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_4_n_0\
);
\g81__301_carry__3_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_5_n_0\
);
\g81__301_carry__3_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_6_n_0\
);
\g81__301_carry__3_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_7_n_0\
);
\g81__301_carry__3_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__3_n_0\,
CO(3) => \g81__301_carry__4_n_0\,
CO(2) => \g81__301_carry__4_n_1\,
CO(1) => \g81__301_carry__4_n_2\,
CO(0) => \g81__301_carry__4_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__4_i_1_n_0\,
DI(2) => \g81__301_carry__4_i_2_n_0\,
DI(1) => \g81__301_carry__4_i_3_n_0\,
DI(0) => \g81__301_carry__4_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__4_i_5_n_0\,
S(2) => \g81__301_carry__4_i_6_n_0\,
S(1) => \g81__301_carry__4_i_7_n_0\,
S(0) => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__4_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_1_n_0\
);
\g81__301_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_2_n_0\
);
\g81__301_carry__4_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_3_n_0\
);
\g81__301_carry__4_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_4_n_0\
);
\g81__301_carry__4_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_5_n_0\
);
\g81__301_carry__4_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_6_n_0\
);
\g81__301_carry__4_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_7_n_0\
);
\g81__301_carry__4_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__4_n_0\,
CO(3) => \g81__301_carry__5_n_0\,
CO(2) => \g81__301_carry__5_n_1\,
CO(1) => \g81__301_carry__5_n_2\,
CO(0) => \g81__301_carry__5_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__5_i_1_n_0\,
DI(2) => \g81__301_carry__5_i_2_n_0\,
DI(1) => \g81__301_carry__5_i_3_n_0\,
DI(0) => \g81__301_carry__5_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__5_i_5_n_0\,
S(2) => \g81__301_carry__5_i_6_n_0\,
S(1) => \g81__301_carry__5_i_7_n_0\,
S(0) => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__5_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_1_n_0\
);
\g81__301_carry__5_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_2_n_0\
);
\g81__301_carry__5_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_3_n_0\
);
\g81__301_carry__5_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_4_n_0\
);
\g81__301_carry__5_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_5_n_0\
);
\g81__301_carry__5_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_6_n_0\
);
\g81__301_carry__5_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_7_n_0\
);
\g81__301_carry__5_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__5_n_0\,
CO(3) => \NLW_g81__301_carry__6_CO_UNCONNECTED\(3),
CO(2) => \g81__301_carry__6_n_1\,
CO(1) => \g81__301_carry__6_n_2\,
CO(0) => \g81__301_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__301_carry__6_i_1_n_0\,
DI(1) => \g81__301_carry__6_i_2_n_0\,
DI(0) => \g81__301_carry__6_i_3_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__6_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \g81__301_carry__6_i_4_n_0\,
S(1) => \g81__301_carry__6_i_5_n_0\,
S(0) => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry__6_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_1_n_0\
);
\g81__301_carry__6_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_2_n_0\
);
\g81__301_carry__6_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_3_n_0\
);
\g81__301_carry__6_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_4_n_0\
);
\g81__301_carry__6_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_5_n_0\
);
\g81__301_carry__6_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_5\,
I1 => g84,
I2 => g83(2),
I3 => \g83__0_carry_n_5\,
O => \g81__301_carry_i_1_n_0\
);
\g81__301_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABEF"
)
port map (
I0 => \g81__261_carry_n_6\,
I1 => g84,
I2 => g83(1),
I3 => \g83__0_carry_n_6\,
O => \g81__301_carry_i_2_n_0\
);
\g81__301_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g81__261_carry_n_7\,
I1 => \g83__0_carry_n_7\,
O => \g81__301_carry_i_3_n_0\
);
\g81__301_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
I3 => \g81__261_carry_n_5\,
I4 => \g81__261_carry_n_4\,
I5 => \g81_carry__0_i_9_n_0\,
O => \g81__301_carry_i_4_n_0\
);
\g81__301_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DD22DD22D2DD2D2"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__261_carry_n_6\,
I2 => \g81__261_carry_n_5\,
I3 => \g83__0_carry_n_5\,
I4 => g83(2),
I5 => g84,
O => \g81__301_carry_i_5_n_0\
);
\g81__301_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22DD22DD2D22D2D"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
I2 => \g81__261_carry_n_6\,
I3 => \g83__0_carry_n_6\,
I4 => g83(1),
I5 => g84,
O => \g81__301_carry_i_6_n_0\
);
\g81__301_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
O => \g81__301_carry_i_7_n_0\
);
\g81__347_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__347_carry_n_0\,
CO(2) => \g81__347_carry_n_1\,
CO(1) => \g81__347_carry_n_2\,
CO(0) => \g81__347_carry_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \g81__347_carry_n_4\,
O(2) => \g81__347_carry_n_5\,
O(1) => \g81__347_carry_n_6\,
O(0) => \g81__347_carry_n_7\,
S(3) => \g81__347_carry_i_1_n_0\,
S(2) => \g81__347_carry_i_2_n_0\,
S(1) => \g81__347_carry_i_3_n_0\,
S(0) => \g81__347_carry_i_4_n_0\
);
\g81__347_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__347_carry_n_0\,
CO(3) => \NLW_g81__347_carry__0_CO_UNCONNECTED\(3),
CO(2) => \g81__347_carry__0_n_1\,
CO(1) => \g81__347_carry__0_n_2\,
CO(0) => \g81__347_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \g81__347_carry__0_n_4\,
O(2) => \g81__347_carry__0_n_5\,
O(1) => \g81__347_carry__0_n_6\,
O(0) => \g81__347_carry__0_n_7\,
S(3) => \g81__347_carry__0_i_1_n_0\,
S(2) => \g81__347_carry__0_i_2_n_0\,
S(1) => \g81__347_carry__0_i_3_n_0\,
S(0) => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_4\,
O => \g81__347_carry__0_i_1_n_0\
);
\g81__347_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_5\,
O => \g81__347_carry__0_i_2_n_0\
);
\g81__347_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_6\,
O => \g81__347_carry__0_i_3_n_0\
);
\g81__347_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_7\,
O => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_4\,
O => \g81__347_carry_i_1_n_0\
);
\g81__347_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_5\,
O => \g81__347_carry_i_2_n_0\
);
\g81__347_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__347_carry_i_3_n_0\
);
\g81__347_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__347_carry_i_4_n_0\
);
\g81__53_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__53_carry_n_0\,
CO(2) => \g81__53_carry_n_1\,
CO(1) => \g81__53_carry_n_2\,
CO(0) => \g81__53_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__53_carry_i_1_n_0\,
DI(1) => \g81__53_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__53_carry_n_4\,
O(2) => \g81__53_carry_n_5\,
O(1) => \g81__53_carry_n_6\,
O(0) => \NLW_g81__53_carry_O_UNCONNECTED\(0),
S(3) => \g81__53_carry_i_3_n_0\,
S(2) => \g81__53_carry_i_4_n_0\,
S(1) => \g81__53_carry_i_5_n_0\,
S(0) => \g81__53_carry_i_6_n_0\
);
\g81__53_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry_n_0\,
CO(3) => \g81__53_carry__0_n_0\,
CO(2) => \g81__53_carry__0_n_1\,
CO(1) => \g81__53_carry__0_n_2\,
CO(0) => \g81__53_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__53_carry__0_n_4\,
O(2) => \g81__53_carry__0_n_5\,
O(1) => \g81__53_carry__0_n_6\,
O(0) => \g81__53_carry__0_n_7\,
S(3) => \g81__53_carry__0_i_1_n_0\,
S(2) => \g81__53_carry__0_i_2_n_0\,
S(1) => \g81__53_carry__0_i_3_n_0\,
S(0) => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__53_carry__0_i_1_n_0\
);
\g81__53_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__53_carry__0_i_2_n_0\
);
\g81__53_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__53_carry__0_i_3_n_0\
);
\g81__53_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__0_n_0\,
CO(3) => \g81__53_carry__1_n_0\,
CO(2) => \g81__53_carry__1_n_1\,
CO(1) => \g81__53_carry__1_n_2\,
CO(0) => \g81__53_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__53_carry__1_n_4\,
O(2) => \g81__53_carry__1_n_5\,
O(1) => \g81__53_carry__1_n_6\,
O(0) => \g81__53_carry__1_n_7\,
S(3) => \g81__53_carry__1_i_1_n_0\,
S(2) => \g81__53_carry__1_i_2_n_0\,
S(1) => \g81__53_carry__1_i_3_n_0\,
S(0) => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__53_carry__1_i_1_n_0\
);
\g81__53_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_2_n_0\
);
\g81__53_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_3_n_0\
);
\g81__53_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__1_n_0\,
CO(3) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__53_carry__2_n_1\,
CO(1) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__53_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__53_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__53_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__53_carry__2_n_6\,
O(0) => \g81__53_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__53_carry__2_i_1_n_0\
);
\g81__53_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__53_carry_i_1_n_0\
);
\g81__53_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__53_carry_i_2_n_0\
);
\g81__53_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__53_carry_i_3_n_0\
);
\g81__53_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__53_carry_i_4_n_0\
);
\g81__53_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__53_carry_i_5_n_0\
);
\g81__53_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__53_carry_i_6_n_0\
);
\g81__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__92_carry_n_0\,
CO(2) => \g81__92_carry_n_1\,
CO(1) => \g81__92_carry_n_2\,
CO(0) => \g81__92_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__92_carry_i_1_n_0\,
DI(1) => \g81__92_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__92_carry_n_4\,
O(2) => \g81__92_carry_n_5\,
O(1) => \g81__92_carry_n_6\,
O(0) => \NLW_g81__92_carry_O_UNCONNECTED\(0),
S(3) => \g81__92_carry_i_3_n_0\,
S(2) => \g81__92_carry_i_4_n_0\,
S(1) => \g81__92_carry_i_5_n_0\,
S(0) => \g81__92_carry_i_6_n_0\
);
\g81__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry_n_0\,
CO(3) => \g81__92_carry__0_n_0\,
CO(2) => \g81__92_carry__0_n_1\,
CO(1) => \g81__92_carry__0_n_2\,
CO(0) => \g81__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__92_carry__0_n_4\,
O(2) => \g81__92_carry__0_n_5\,
O(1) => \g81__92_carry__0_n_6\,
O(0) => \g81__92_carry__0_n_7\,
S(3) => \g81__92_carry__0_i_1_n_0\,
S(2) => \g81__92_carry__0_i_2_n_0\,
S(1) => \g81__92_carry__0_i_3_n_0\,
S(0) => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__92_carry__0_i_1_n_0\
);
\g81__92_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__92_carry__0_i_2_n_0\
);
\g81__92_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__92_carry__0_i_3_n_0\
);
\g81__92_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__0_n_0\,
CO(3) => \g81__92_carry__1_n_0\,
CO(2) => \g81__92_carry__1_n_1\,
CO(1) => \g81__92_carry__1_n_2\,
CO(0) => \g81__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__92_carry__1_n_4\,
O(2) => \g81__92_carry__1_n_5\,
O(1) => \g81__92_carry__1_n_6\,
O(0) => \g81__92_carry__1_n_7\,
S(3) => \g81__92_carry__1_i_1_n_0\,
S(2) => \g81__92_carry__1_i_2_n_0\,
S(1) => \g81__92_carry__1_i_3_n_0\,
S(0) => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__92_carry__1_i_1_n_0\
);
\g81__92_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_2_n_0\
);
\g81__92_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_3_n_0\
);
\g81__92_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__1_n_0\,
CO(3) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__92_carry__2_n_1\,
CO(1) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__92_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__92_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__92_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__92_carry__2_n_6\,
O(0) => \g81__92_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__92_carry__2_i_1_n_0\
);
\g81__92_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__92_carry_i_1_n_0\
);
\g81__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__92_carry_i_2_n_0\
);
\g81__92_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__92_carry_i_3_n_0\
);
\g81__92_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__92_carry_i_4_n_0\
);
\g81__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__92_carry_i_5_n_0\
);
\g81__92_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__92_carry_i_6_n_0\
);
g81_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g81_carry_n_0,
CO(2) => g81_carry_n_1,
CO(1) => g81_carry_n_2,
CO(0) => g81_carry_n_3,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => g81_carry_i_2_n_0,
DI(1) => g81_carry_i_3_n_0,
DI(0) => '0',
O(3 downto 1) => NLW_g81_carry_O_UNCONNECTED(3 downto 1),
O(0) => g81_carry_n_7,
S(3) => g81_carry_i_4_n_0,
S(2) => g81_carry_i_5_n_0,
S(1) => g81_carry_i_6_n_0,
S(0) => g81_carry_i_7_n_0
);
\g81_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g81_carry_n_0,
CO(3) => \g81_carry__0_n_0\,
CO(2) => \g81_carry__0_n_1\,
CO(1) => \g81_carry__0_n_2\,
CO(0) => \g81_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81_carry__0_n_4\,
O(2) => \g81_carry__0_n_5\,
O(1) => \g81_carry__0_n_6\,
O(0) => \NLW_g81_carry__0_O_UNCONNECTED\(0),
S(3) => \g81_carry__0_i_5_n_0\,
S(2) => \g81_carry__0_i_6_n_0\,
S(1) => \g81_carry__0_i_7_n_0\,
S(0) => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
I4 => g83(7),
I5 => \g83__0_carry__0_n_4\,
O => \g81_carry__0_i_1_n_0\
);
\g81_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81_carry__0_i_10_n_0\
);
\g81_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81_carry__0_i_11_n_0\
);
\g81_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
O => \g81_carry__0_i_12_n_0\
);
\g81_carry__0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
O => \g81_carry__0_i_13_n_0\
);
\g81_carry__0_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
O => \g81_carry__0_i_14_n_0\
);
\g81_carry__0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81_carry__0_i_15_n_0\
);
\g81_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_10_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => g83(6),
I5 => \g83__0_carry__0_n_5\,
O => \g81_carry__0_i_2_n_0\
);
\g81_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
I4 => g83(5),
I5 => \g83__0_carry__0_n_6\,
O => \g81_carry__0_i_3_n_0\
);
\g81_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C33CC33CA5A55A5A"
)
port map (
I0 => g83(5),
I1 => \g83__0_carry__0_n_6\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g83__0_carry_n_4\,
I4 => g83(3),
I5 => g84,
O => \g81_carry__0_i_4_n_0\
);
\g81_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81_carry__0_i_5_n_0\
);
\g81_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81_carry__0_i_6_n_0\
);
\g81_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81_carry__0_i_7_n_0\
);
\g81_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81_carry__0_i_9_n_0\
);
\g81_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__0_n_0\,
CO(3) => \g81_carry__1_n_0\,
CO(2) => \g81_carry__1_n_1\,
CO(1) => \g81_carry__1_n_2\,
CO(0) => \g81_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81_carry__1_n_4\,
O(2) => \g81_carry__1_n_5\,
O(1) => \g81_carry__1_n_6\,
O(0) => \g81_carry__1_n_7\,
S(3) => \g81_carry__1_i_5_n_0\,
S(2) => \g81_carry__1_i_6_n_0\,
S(1) => \g81_carry__1_i_7_n_0\,
S(0) => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(7),
I1 => \g83__0_carry__0_n_4\,
I2 => g84,
I3 => g83(9),
I4 => \g83__0_carry__1_n_2\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_1_n_0\
);
\g81_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(6),
I1 => \g83__0_carry__0_n_5\,
I2 => g84,
I3 => g83(8),
I4 => \g83__0_carry__1_n_7\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_2_n_0\
);
\g81_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(5),
I2 => \g83__0_carry__0_n_6\,
I3 => \g81_carry__1_i_9_n_0\,
I4 => g83(9),
I5 => \g83__0_carry__1_n_2\,
O => \g81_carry__1_i_3_n_0\
);
\g81_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(4),
I2 => \g83__0_carry__0_n_7\,
I3 => \g81_carry__0_i_12_n_0\,
I4 => g83(8),
I5 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_4_n_0\
);
\g81_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_5_n_0\
);
\g81_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_6_n_0\
);
\g81_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_7_n_0\
);
\g81_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_4\,
I1 => g83(7),
I2 => g84,
O => \g81_carry__1_i_9_n_0\
);
\g81_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__1_n_0\,
CO(3) => \NLW_g81_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81_carry__2_n_1\,
CO(1) => \NLW_g81_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81_carry__2_n_6\,
O(0) => \g81_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81_carry__2_i_3_n_0\
);
\g81_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_1_n_0\
);
\g81_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_2_n_0\
);
\g81_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81_carry__2_i_3_n_0\
);
g81_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_1_n_0
);
g81_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => g81_carry_i_2_n_0
);
g81_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => g81_carry_i_3_n_0
);
g81_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => g81_carry_i_4_n_0
);
g81_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => g81_carry_i_5_n_0
);
g81_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_6_n_0
);
g81_carry_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => g81_carry_i_7_n_0
);
\g83__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g83__0_carry_n_0\,
CO(2) => \g83__0_carry_n_1\,
CO(1) => \g83__0_carry_n_2\,
CO(0) => \g83__0_carry_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry_i_1_n_0\,
DI(2) => \g83__0_carry_i_2_n_0\,
DI(1) => \g83__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \g83__0_carry_n_4\,
O(2) => \g83__0_carry_n_5\,
O(1) => \g83__0_carry_n_6\,
O(0) => \g83__0_carry_n_7\,
S(3) => \g83__0_carry_i_4_n_0\,
S(2) => \g83__0_carry_i_5_n_0\,
S(1) => \g83__0_carry_i_6_n_0\,
S(0) => \g83__0_carry_i_7_n_0\
);
\g83__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry_n_0\,
CO(3) => \g83__0_carry__0_n_0\,
CO(2) => \g83__0_carry__0_n_1\,
CO(1) => \g83__0_carry__0_n_2\,
CO(0) => \g83__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry__0_i_1_n_0\,
DI(2) => \g83__0_carry__0_i_2_n_0\,
DI(1) => \g83__0_carry__0_i_3_n_0\,
DI(0) => \g83__0_carry__0_i_4_n_0\,
O(3) => \g83__0_carry__0_n_4\,
O(2) => \g83__0_carry__0_n_5\,
O(1) => \g83__0_carry__0_n_6\,
O(0) => \g83__0_carry__0_n_7\,
S(3) => \g83__0_carry__0_i_5_n_0\,
S(2) => \g83__0_carry__0_i_6_n_0\,
S(1) => \g83__0_carry__0_i_7_n_0\,
S(0) => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
O => \g83__0_carry__0_i_1_n_0\
);
\g83__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
O => \g83__0_carry__0_i_2_n_0\
);
\g83__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
O => \g83__0_carry__0_i_3_n_0\
);
\g83__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
O => \g83__0_carry__0_i_4_n_0\
);
\g83__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry__0_i_1_n_0\,
I1 => rgb888(7),
I2 => rgb888(15),
I3 => rgb888(23),
O => \g83__0_carry__0_i_5_n_0\
);
\g83__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
I3 => \g83__0_carry__0_i_2_n_0\,
O => \g83__0_carry__0_i_6_n_0\
);
\g83__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
I3 => \g83__0_carry__0_i_3_n_0\,
O => \g83__0_carry__0_i_7_n_0\
);
\g83__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
I3 => \g83__0_carry__0_i_4_n_0\,
O => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry__0_n_0\,
CO(3 downto 2) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \g83__0_carry__1_n_2\,
CO(0) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_g83__0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \g83__0_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(15),
I1 => rgb888(7),
I2 => rgb888(23),
O => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
O => \g83__0_carry_i_1_n_0\
);
\g83__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
O => \g83__0_carry_i_2_n_0\
);
\g83__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_3_n_0\
);
\g83__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
I3 => \g83__0_carry_i_1_n_0\,
O => \g83__0_carry_i_4_n_0\
);
\g83__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
I3 => \g83__0_carry_i_2_n_0\,
O => \g83__0_carry_i_5_n_0\
);
\g83__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
I3 => \g83__0_carry_i_3_n_0\,
O => \g83__0_carry_i_6_n_0\
);
\g83__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_7_n_0\
);
g84_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g84_carry_n_0,
CO(2) => g84_carry_n_1,
CO(1) => g84_carry_n_2,
CO(0) => g84_carry_n_3,
CYINIT => '1',
DI(3) => g84_carry_i_1_n_0,
DI(2) => g84_carry_i_2_n_0,
DI(1) => g84_carry_i_3_n_0,
DI(0) => g84_carry_i_4_n_0,
O(3 downto 0) => NLW_g84_carry_O_UNCONNECTED(3 downto 0),
S(3) => g84_carry_i_5_n_0,
S(2) => g84_carry_i_6_n_0,
S(1) => g84_carry_i_7_n_0,
S(0) => g84_carry_i_8_n_0
);
\g84_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g84_carry_n_0,
CO(3 downto 1) => \NLW_g84_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => g84,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \g84_carry__0_i_1_n_0\,
O(3 downto 0) => \NLW_g84_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \g84_carry__0_i_2_n_0\
);
\g84_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_1_n_0\
);
\g84_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_2_n_0\
);
g84_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_1_n_0
);
g84_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_2_n_0
);
g84_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_3_n_0
);
g84_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_4_n_0
);
g84_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_5_n_0
);
g84_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_6_n_0
);
g84_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_7_n_0
);
g84_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_8_n_0
);
\g8[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_7\,
O => g810_in(0)
);
\g8[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_6\,
O => g810_in(1)
);
\g8[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_5\,
O => g810_in(2)
);
\g8[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_4\,
O => g810_in(3)
);
\g8[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_7\,
O => g810_in(4)
);
\g8[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_6\,
O => g810_in(5)
);
\g8[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_5\,
O => g810_in(6)
);
\g8[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_4\,
O => g810_in(7)
);
\g8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(0),
Q => g8(0),
R => '0'
);
\g8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(1),
Q => g8(1),
R => '0'
);
\g8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(2),
Q => g8(2),
R => '0'
);
\g8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(3),
Q => g8(3),
R => '0'
);
\g8_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(4),
Q => g8(4),
R => '0'
);
\g8_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(5),
Q => g8(5),
R => '0'
);
\g8_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(6),
Q => g8(6),
R => '0'
);
\g8_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(7),
Q => g8(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_1_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_g8_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_g8_1_0 : entity is "system_rgb888_to_g8_1_0,rgb888_to_g8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_g8_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_g8_1_0 : entity is "rgb888_to_g8,Vivado 2016.4";
end system_rgb888_to_g8_1_0;
architecture STRUCTURE of system_rgb888_to_g8_1_0 is
begin
U0: entity work.system_rgb888_to_g8_1_0_rgb888_to_g8
port map (
clk => clk,
g8(7 downto 0) => g8(7 downto 0),
rgb888(23 downto 0) => rgb888(23 downto 0)
);
end STRUCTURE;
| mit | 08eaa64f0aa81019afe5c9a5b8042a89 | 0.49156 | 2.24905 | false | false | false | false |
loa-org/loa-hdl | modules/spislave/hdl/spislave_pkg.vhd | 2 | 3,786 | -------------------------------------------------------------------------------
-- Title : SPI Slave Package Definition
-- Project :
-------------------------------------------------------------------------------
-- File : spislave_pkg.vhd
-- Author : [email protected]
-- Company :
-- Created : 2011-08-27
-- Platform :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
package spislave_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component spi_slave
port (
miso_p : out std_logic;
mosi_p : in std_logic;
sck_p : in std_logic;
csn_p : in std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic);
end component;
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic);
end spislave_pkg;
-------------------------------------------------------------------------------
package body spislave_pkg is
procedure spiReadWord (
constant addr : in natural range 0 to 2**15-1;
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31 downto 16) := std_logic_vector(to_unsigned(addr, 16));
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
procedure spiWriteWord (
signal addr : in std_logic_vector(14 downto 0);
signal data : in std_logic_vector(15 downto 0);
signal sck : out std_logic;
signal mosi : out std_logic;
signal cs_n : out std_logic;
signal clk : in std_logic) is
variable d : std_logic_vector(31 downto 0) := (others => '0');
begin
d(31) := '1'; -- MSB = '1' <=> write
d(30 downto 16) := addr(14 downto 0);
d(15 downto 0) := data;
-- start
cs_n <= '1';
sck <= '0';
mosi <= '0';
wait for 50 ns;
cs_n <= '0';
wait for 100 ns;
-- 32 data bits
for ii in 31 downto 0 loop
sck <= '0';
mosi <= d(ii);
wait for 50 ns;
sck <= '1';
wait for 50 ns;
end loop; -- ii
-- end
sck <= '0';
wait for 50 ns;
cs_n <= '1';
sck <= '0';
mosi <= 'Z';
wait for 100 ns;
end procedure;
end package body spislave_pkg;
| bsd-3-clause | cff3492ddd5fcf7fdc8db4138a40cc34 | 0.426572 | 3.964398 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_sim_netlist.vhdl | 1 | 2,182 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_sim_netlist.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_vga_0_0 is
port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_vga_0_0 : entity is "system_zed_vga_0_0,zed_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_vga_0_0 : entity is "zed_vga,Vivado 2016.4";
end system_zed_vga_0_0;
architecture STRUCTURE of system_zed_vga_0_0 is
signal \^rgb565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb565\(15 downto 12) <= rgb565(15 downto 12);
\^rgb565\(10 downto 7) <= rgb565(10 downto 7);
\^rgb565\(4 downto 1) <= rgb565(4 downto 1);
vga_b(3 downto 0) <= \^rgb565\(4 downto 1);
vga_g(3 downto 0) <= \^rgb565\(10 downto 7);
vga_r(3 downto 0) <= \^rgb565\(15 downto 12);
end STRUCTURE;
| mit | 8ce8e3429c25a2908ba90ab6615ca3b4 | 0.637489 | 3.519355 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_rst_controller.vhd | 1 | 3,700 | -- niosii_system_rst_controller.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0'
);
end entity niosii_system_rst_controller;
architecture rtl of niosii_system_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_rst_controller
| apache-2.0 | 6b87e194eb692da5fbc416ca6425a125 | 0.548919 | 2.746845 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_hs_lane_phy.vhd | 1 | 7,915 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--High-Speed D-PHY lane RX PHY for MIPI CSI-2 Rx core
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This entity handles input skew compensation and deserialisation for the
--CSI data input lanes. Output is has arbitrary alignment which must be fixed later on
--in the processing chain
entity csi_rx_hs_lane_phy is
generic(
series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6
invert : boolean := false; --Whether or not to invert output (i.e. if pairs are swapped)
term_en : boolean := true; --Whether or not to enable internal input termination
delay : natural --IDELAY delay value for skew compensation
);
port (
ddr_bit_clock : in STD_LOGIC; --true and complement DDR bit clocks, buffered from D-PHY clock
ddr_bit_clock_b : in STD_LOGIC;
byte_clock : in STD_LOGIC; --byte clock; i.e. input clock /4
enable : in STD_LOGIC; --active high enable for SERDES
reset : in STD_LOGIC; --reset, latched internally to byte clock
dphy_hs : in STD_LOGIC_VECTOR (1 downto 0); --lane input, 1 is P, 0 is N
deser_out : out STD_LOGIC_VECTOR (7 downto 0) --deserialised byte output
);
end csi_rx_hs_lane_phy;
architecture Behavioral of csi_rx_hs_lane_phy is
signal reset_lat : std_logic; --reset synchronised to byte clock
signal in_se : std_logic; --input after differential buffer
signal in_delayed : std_logic; --input after deskew
--for Virtex-6 devices where we cascade two ISERDESs
signal shift_1 : std_logic;
signal shift_2 : std_logic;
signal serdes_out_int : std_logic_vector(7 downto 0);
begin
process(byte_clock)
begin
if rising_edge(byte_clock) then
reset_lat <= reset;
end if;
end process;
inbuf : IBUFDS
generic map(
DIFF_TERM => term_en,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT")
port map(
O => in_se,
I => dphy_hs(1),
IB => dphy_hs(0));
--7 series specific blocks
gen_7s : if series = "7SERIES" generate
indelay : IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "TRUE",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => delay,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA",
PIPE_SEL => "FALSE"
)
port map (
DATAOUT => in_delayed,
DATAIN => '0',
C => byte_clock,
CE => '0',
INC => '0',
IDATAIN => in_se,
CNTVALUEIN => "00000",
CNTVALUEOUT => open,
CINVCTRL => '0',
LD => '0',
LDPIPEEN => '0',
REGRST => '0'
);
ideser : ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 1,
OFB_USED => "FALSE",
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
--In the ISERDESE2, Q8 is the oldest bit but in the CSI spec
--the MSB is the most recent bit. So we mirror the output
Q1 => serdes_out_int(7),
Q2 => serdes_out_int(6),
Q3 => serdes_out_int(5),
Q4 => serdes_out_int(4),
Q5 => serdes_out_int(3),
Q6 => serdes_out_int(2),
Q7 => serdes_out_int(1),
Q8 => serdes_out_int(0),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => enable,
CE2 => '1',
CLKDIVP => '0',
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
OCLK => '0',
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
D => '0',
DDLY => in_delayed,
OFB => '0',
OCLKB => '0',
RST => reset_lat,
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
end generate;
--Legacy Virtex-6 specific blocks
gen_v6 : if series = "VIRTEX6" generate
--Input delay for skew compensation
indelay : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "I",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => delay,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => in_delayed,
DATAIN => '0',
C => byte_clock,
CE => '0',
INC => '0',
IDATAIN => in_se,
ODATAIN => '0',
RST => '0',
T => '1',
CNTVALUEIN => "00000",
CNTVALUEOUT => open,
CLKIN => '0',
CINVCTRL => '0'
);
--Input deserialisation
ideser1 : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => FALSE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 2,
OFB_USED => FALSE,
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map(
O => open,
Q1 => serdes_out_int(7),
Q2 => serdes_out_int(6),
Q3 => serdes_out_int(5),
Q4 => serdes_out_int(4),
Q5 => serdes_out_int(3),
Q6 => serdes_out_int(2),
SHIFTOUT1 => shift_1,
SHIFTOUT2 => shift_2,
BITSLIP => '0',
CE1 => enable,
CE2 => enable,
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
D => '0',
DDLY => in_delayed,
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OCLK => '0',
OFB => '0',
RST => reset_lat,
SHIFTIN1 => '0',
SHIFTIN2 => '0');
ideser2 : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => FALSE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 2,
OFB_USED => FALSE,
SERDES_MODE => "SLAVE",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map(
O => open,
Q1 => open,
Q2 => open,
Q3 => serdes_out_int(1),
Q4 => serdes_out_int(0),
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => enable,
CE2 => enable,
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
D => '0',
DDLY => '0',
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OCLK => '0',
OFB => '0',
RST => reset_lat,
SHIFTIN1 => shift_1,
SHIFTIN2 => shift_2);
end generate;
--Inversion of output based on generic
gen_true : if not invert generate
deser_out <= serdes_out_int;
end generate;
gen_inv : if invert generate
deser_out <= not serdes_out_int;
end generate;
end architecture;
| mit | 890447515ea52089a45c5b1bdbdc2656 | 0.484397 | 3.655889 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ipshared/0b3c/vga_sync.vhd | 1 | 2,792 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture Structural of vga_sync is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk,rst)
begin
if rst='0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '0';
hsync <= '0';
active <= '0';
elsif rising_edge(clk) then
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
| mit | bf9a25031e16291d093ab680e4c621a6 | 0.459169 | 3.872399 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_timer_tb.vhd | 2 | 1,502 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_timer_tb"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_timer_tb is
end entity imotor_timer_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_timer_tb is
-- component generics
-- component ports
-- clock
signal clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT : imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 1E6,
SEND_FREQUENCY => 1E5)
port map (
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | ef85a22d21f8ed8d8ffcbe4570b56d60 | 0.387483 | 5.913386 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/lfsr_inferred-rtl.vhdl | 1 | 2,497 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.logic_pkg.all;
architecture rtl of lfsr_inferred is
subtype state_type is std_ulogic_vector(state_bits-1 downto 0);
constant taps : state_type := lfsr_taps(state_bits);
type comb_type is record
state_next : state_type;
end record;
signal c : comb_type;
type reg_type is record
state : state_type;
end record;
signal r, r_next : reg_type;
begin
-- Galois style
state_next_gen : for n in state_bits-2 downto 0 generate
tap : if taps(n) = '1' generate
c.state_next(n) <= r.state(n+1) xor r.state(0);
end generate;
no_tap : if taps(n) = '0' generate
c.state_next(n) <= r.state(n+1);
end generate;
end generate;
c.state_next(state_bits-1) <= r.state(0);
with en select
r_next.state <= c.state_next when '1',
r.state when '0',
(others => 'X') when others;
output <= r.state(0);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r.state(0) <= '1';
r.state(state_bits-1 downto 1) <= (others => '0');
when others =>
r <= (state => (others => 'X'));
end case;
end if;
end process;
end;
| apache-2.0 | 813b276cbaf1739f20af8b18a6ca5be3 | 0.509812 | 4.140962 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_pll/vga_pll.srcs/sources_1/new/vga_pll.vhd | 7 | 1,175 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_pll is
port (
clk_100 : in std_logic;
clk_50 : out std_logic;
clk_25 : out std_logic;
clk_12_5 : out std_logic;
clk_6_25 : out std_logic
);
end vga_pll;
architecture Behavioral of vga_pll is
signal clk_50_s : std_logic := '0';
signal clk_25_s : std_logic := '0';
signal clk_12_5_s : std_logic := '0';
signal clk_6_25_s : std_logic := '0';
begin
clk_50 <= clk_50_s;
clk_25 <= clk_25_s;
clk_12_5 <= clk_12_5_s;
clk_6_25 <= clk_6_25_s;
process(clk_100)
begin
if rising_edge(clk_100) then
clk_50_s <= not clk_50_s;
end if;
end process;
process(clk_50_s)
begin
if rising_edge(clk_50_s) then
clk_25_s <= not clk_25_s;
end if;
end process;
process(clk_25_s)
begin
if rising_edge(clk_25_s) then
clk_12_5_s <= not clk_12_5_s;
end if;
end process;
process(clk_6_25_s)
begin
if rising_edge(clk_6_25_s) then
clk_6_25_s <= not clk_6_25_s;
end if;
end process;
end Behavioral;
| mit | d656a0caa6cd497db317f100b0d170c8 | 0.520851 | 2.865854 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/sim/system_vga_transform_0_0.vhd | 1 | 4,361 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_transform:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_transform_0_0;
ARCHITECTURE system_vga_transform_0_0_arch OF system_vga_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_transform IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_transform;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_transform
PORT MAP (
clk => clk,
enable => enable,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out
);
END system_vga_transform_0_0_arch;
| mit | 2c4ddad46f7b4000b6959e09f7f034c3 | 0.698234 | 3.607113 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/synth/system_vga_hessian_0_0.vhd | 1 | 4,405 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=640}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | f731ba46d82c6e7e0ac1dc294dc6979f | 0.719637 | 3.680033 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1r1w_inferred-rtl.vhdl | 1 | 2,933 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
signal memory : memory_type
-- pragma translate_off
:= (others => (others => '0'));
-- pragma translate_on
;
type reg_type is record
raddr : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
begin
write_first_true_gen: if write_first generate
rdata <= memory(conv_addr(r.raddr));
main : process(clk)
begin
if rising_edge(clk) then
if re = '1' then
r.raddr <= raddr;
end if;
if we = '1' then
if addr_bits > 0 then
memory(conv_addr(waddr)) <= wdata;
else
memory(0) <= wdata;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
if re = '1' then
if addr_bits > 0 then
r.rdata <= memory(conv_addr(raddr));
else
r.rdata <= memory(0);
end if;
end if;
if we = '1' then
if addr_bits > 0 then
memory(conv_addr(waddr)) <= wdata;
else
memory(0) <= wdata;
end if
end if;
end if;
end generate;
end;
| apache-2.0 | 263b80d5d5309e6fed6e54b6eebf90b9 | 0.519605 | 4.332349 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/2e76/rgb565_to_rgb888.vhd | 2 | 1,391 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: rgb565_to_rgb888 - Structural
-- Description: Convert 16-bit rgb565 to 24-bit rgb888
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb565_to_rgb888 is
port(
rgb_565: in std_logic_vector(15 downto 0);
rgb_888: out std_logic_vector(23 downto 0)
);
end rgb565_to_rgb888;
architecture Structural of rgb565_to_rgb888 is
signal red, green, blue: std_logic_vector(7 downto 0) := "00000000";
begin
red(4 downto 0) <= rgb_565(15 downto 11);
green(5 downto 0) <= rgb_565(10 downto 5);
blue(4 downto 0) <= rgb_565(4 downto 0);
process(red, green, blue)
variable r_1, r_2, g_1, g_2, b_1, b_2: unsigned(7 downto 0);
begin
r_1 := unsigned(red) sll 3;
r_2 := unsigned(red) srl 2;
g_1 := unsigned(green) sll 2;
g_2 := unsigned(green) srl 4;
b_1 := unsigned(blue) sll 3;
b_2 := unsigned(blue) sll 2;
rgb_888(23 downto 16) <= std_logic_vector(r_1 or r_2);
rgb_888(15 downto 8) <= std_logic_vector(g_1 or g_2);
rgb_888(7 downto 0) <= std_logic_vector(b_1 or b_1);
end process;
end Structural;
| mit | c71d29dd57a7da142fa6e0a46f331555 | 0.536305 | 3.327751 | false | false | false | false |
loa-org/loa-hdl | modules/fifo_sync/tb/fifo_sync_tb.vhd | 2 | 2,816 | -------------------------------------------------------------------------------
-- Title : Synchronous FIFO Testbench
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fifo_sync_pkg.all;
-------------------------------------------------------------------------------
entity fifo_sync_tb is
end entity fifo_sync_tb;
-------------------------------------------------------------------------------
architecture tb of fifo_sync_tb is
use work.fifo_sync_pkg.all;
-- component ports
constant data_width : natural := 8;
constant address_width : natural := 4;
signal di : std_logic_vector(data_width -1 downto 0);
signal wr : std_logic := '0';
signal full : std_logic;
signal do : std_logic_vector(data_width -1 downto 0);
signal rd : std_logic := '0';
signal empty : std_logic;
signal r : std_logic := '0';
signal w : std_logic := '0';
-- clock
signal Clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT : fifo_sync
generic map (
data_width => data_width,
address_width => address_width)
port map (
di => di,
wr => wr,
full => full,
do => do,
rd => rd,
empty => empty,
valid => open,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
process
variable n : integer := 0;
begin
wait until Clk = '1';
if w = '1' and full = '0' then
wr <= '1';
di <= std_logic_vector(to_unsigned(n, 8));
n := n+1;
else
wr <= '0';
end if;
end process;
process
variable n : integer := 0;
begin
wait until Clk = '1';
if empty = '0' and r = '1' then
rd <= '1';
else
rd <= '0';
end if;
end process;
process
begin
w <= '1';
wait for 300 ns;
w <= '0';
wait for 100 ns;
r <= '1';
wait for 50 ns;
r <= '0';
wait for 100 ns;
end process;
end architecture tb;
configuration fifo_sync_tb_cfg of fifo_sync_tb is
for tb
end for;
end fifo_sync_tb_cfg;
| bsd-3-clause | 085439756ed7b5aac926d95a3558d6ed | 0.466264 | 4.093023 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent.vhd | 1 | 17,848 | -- niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 7;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 53;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 8;
PKT_BYTEEN_L : integer := 8;
PKT_ADDR_H : integer := 33;
PKT_ADDR_L : integer := 9;
PKT_TRANS_COMPRESSED_READ : integer := 34;
PKT_TRANS_POSTED : integer := 35;
PKT_TRANS_WRITE : integer := 36;
PKT_TRANS_READ : integer := 37;
PKT_TRANS_LOCK : integer := 38;
PKT_SRC_ID_H : integer := 58;
PKT_SRC_ID_L : integer := 55;
PKT_DEST_ID_H : integer := 62;
PKT_DEST_ID_L : integer := 59;
PKT_BURSTWRAP_H : integer := 45;
PKT_BURSTWRAP_L : integer := 43;
PKT_BYTE_CNT_H : integer := 42;
PKT_BYTE_CNT_L : integer := 40;
PKT_PROTECTION_H : integer := 66;
PKT_PROTECTION_L : integer := 64;
PKT_RESPONSE_STATUS_H : integer := 72;
PKT_RESPONSE_STATUS_L : integer := 71;
PKT_BURST_SIZE_H : integer := 48;
PKT_BURST_SIZE_L : integer := 46;
ST_CHANNEL_W : integer := 13;
ST_DATA_W : integer := 73;
AVS_BURSTCOUNT_W : integer := 1;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
m0_address : out std_logic_vector(24 downto 0); -- m0.address
m0_burstcount : out std_logic_vector(0 downto 0); -- .burstcount
m0_byteenable : out std_logic_vector(0 downto 0); -- .byteenable
m0_debugaccess : out std_logic; -- .debugaccess
m0_lock : out std_logic; -- .lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .readdata
m0_readdatavalid : in std_logic := '0'; -- .readdatavalid
m0_read : out std_logic; -- .read
m0_waitrequest : in std_logic := '0'; -- .waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- .writedata
m0_write : out std_logic; -- .write
rp_endofpacket : out std_logic; -- rp.endofpacket
rp_ready : in std_logic := '0'; -- .ready
rp_valid : out std_logic; -- .valid
rp_data : out std_logic_vector(72 downto 0); -- .data
rp_startofpacket : out std_logic; -- .startofpacket
cp_ready : out std_logic; -- cp.ready
cp_valid : in std_logic := '0'; -- .valid
cp_data : in std_logic_vector(72 downto 0) := (others => '0'); -- .data
cp_startofpacket : in std_logic := '0'; -- .startofpacket
cp_endofpacket : in std_logic := '0'; -- .endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
rf_sink_ready : out std_logic; -- rf_sink.ready
rf_sink_valid : in std_logic := '0'; -- .valid
rf_sink_startofpacket : in std_logic := '0'; -- .startofpacket
rf_sink_endofpacket : in std_logic := '0'; -- .endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => '0'); -- .data
rf_source_ready : in std_logic := '0'; -- rf_source.ready
rf_source_valid : out std_logic; -- .valid
rf_source_startofpacket : out std_logic; -- .startofpacket
rf_source_endofpacket : out std_logic; -- .endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- .data
rdata_fifo_sink_ready : out std_logic; -- rdata_fifo_sink.ready
rdata_fifo_sink_valid : in std_logic := '0'; -- .valid
rdata_fifo_sink_data : in std_logic_vector(9 downto 0) := (others => '0'); -- .data
rdata_fifo_src_ready : in std_logic := '0'; -- rdata_fifo_src.ready
rdata_fifo_src_valid : out std_logic; -- .valid
rdata_fifo_src_data : out std_logic_vector(9 downto 0); -- .data
m0_response : in std_logic_vector(1 downto 0) := (others => '0');
m0_writeresponserequest : out std_logic;
m0_writeresponsevalid : in std_logic := '0'
);
end entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent;
architecture rtl of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent is
component altera_merlin_slave_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(0 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(9 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_agent;
begin
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => PKT_DATA_H,
PKT_DATA_L => PKT_DATA_L,
PKT_BEGIN_BURST => PKT_BEGIN_BURST,
PKT_SYMBOL_W => PKT_SYMBOL_W,
PKT_BYTEEN_H => PKT_BYTEEN_H,
PKT_BYTEEN_L => PKT_BYTEEN_L,
PKT_ADDR_H => PKT_ADDR_H,
PKT_ADDR_L => PKT_ADDR_L,
PKT_TRANS_COMPRESSED_READ => PKT_TRANS_COMPRESSED_READ,
PKT_TRANS_POSTED => PKT_TRANS_POSTED,
PKT_TRANS_WRITE => PKT_TRANS_WRITE,
PKT_TRANS_READ => PKT_TRANS_READ,
PKT_TRANS_LOCK => PKT_TRANS_LOCK,
PKT_SRC_ID_H => PKT_SRC_ID_H,
PKT_SRC_ID_L => PKT_SRC_ID_L,
PKT_DEST_ID_H => PKT_DEST_ID_H,
PKT_DEST_ID_L => PKT_DEST_ID_L,
PKT_BURSTWRAP_H => PKT_BURSTWRAP_H,
PKT_BURSTWRAP_L => PKT_BURSTWRAP_L,
PKT_BYTE_CNT_H => PKT_BYTE_CNT_H,
PKT_BYTE_CNT_L => PKT_BYTE_CNT_L,
PKT_PROTECTION_H => PKT_PROTECTION_H,
PKT_PROTECTION_L => PKT_PROTECTION_L,
PKT_RESPONSE_STATUS_H => PKT_RESPONSE_STATUS_H,
PKT_RESPONSE_STATUS_L => PKT_RESPONSE_STATUS_L,
PKT_BURST_SIZE_H => PKT_BURST_SIZE_H,
PKT_BURST_SIZE_L => PKT_BURST_SIZE_L,
ST_CHANNEL_W => ST_CHANNEL_W,
ST_DATA_W => ST_DATA_W,
AVS_BURSTCOUNT_W => AVS_BURSTCOUNT_W,
SUPPRESS_0_BYTEEN_CMD => SUPPRESS_0_BYTEEN_CMD,
PREVENT_FIFO_OVERFLOW => PREVENT_FIFO_OVERFLOW,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
m0_address => m0_address, -- m0.address
m0_burstcount => m0_burstcount, -- .burstcount
m0_byteenable => m0_byteenable, -- .byteenable
m0_debugaccess => m0_debugaccess, -- .debugaccess
m0_lock => m0_lock, -- .lock
m0_readdata => m0_readdata, -- .readdata
m0_readdatavalid => m0_readdatavalid, -- .readdatavalid
m0_read => m0_read, -- .read
m0_waitrequest => m0_waitrequest, -- .waitrequest
m0_writedata => m0_writedata, -- .writedata
m0_write => m0_write, -- .write
rp_endofpacket => rp_endofpacket, -- rp.endofpacket
rp_ready => rp_ready, -- .ready
rp_valid => rp_valid, -- .valid
rp_data => rp_data, -- .data
rp_startofpacket => rp_startofpacket, -- .startofpacket
cp_ready => cp_ready, -- cp.ready
cp_valid => cp_valid, -- .valid
cp_data => cp_data, -- .data
cp_startofpacket => cp_startofpacket, -- .startofpacket
cp_endofpacket => cp_endofpacket, -- .endofpacket
cp_channel => cp_channel, -- .channel
rf_sink_ready => rf_sink_ready, -- rf_sink.ready
rf_sink_valid => rf_sink_valid, -- .valid
rf_sink_startofpacket => rf_sink_startofpacket, -- .startofpacket
rf_sink_endofpacket => rf_sink_endofpacket, -- .endofpacket
rf_sink_data => rf_sink_data, -- .data
rf_source_ready => rf_source_ready, -- rf_source.ready
rf_source_valid => rf_source_valid, -- .valid
rf_source_startofpacket => rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => rf_source_endofpacket, -- .endofpacket
rf_source_data => rf_source_data, -- .data
rdata_fifo_sink_ready => rdata_fifo_sink_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => rdata_fifo_sink_valid, -- .valid
rdata_fifo_sink_data => rdata_fifo_sink_data, -- .data
rdata_fifo_src_ready => rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent
| apache-2.0 | 478471e4f430aab5d0e3d19bfd5047a2 | 0.422961 | 3.965341 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/synth/system_rst_ps7_0_100M_0.vhd | 1 | 6,572 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_ps7_0_100M_0;
ARCHITECTURE system_rst_ps7_0_100M_0_arch OF system_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "system_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "system_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_ps7_0_100M_0_arch;
| mit | 1df97c519543b3eac13cf5d5baaf72a2 | 0.712568 | 3.440838 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl | 1 | 2,175 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:26:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl
-- Design : system_xlconstant_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_0 : entity is "yes";
end system_xlconstant_0_0;
architecture STRUCTURE of system_xlconstant_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
dout(23) <= \<const1>\;
dout(22) <= \<const1>\;
dout(21) <= \<const1>\;
dout(20) <= \<const1>\;
dout(19) <= \<const1>\;
dout(18) <= \<const1>\;
dout(17) <= \<const1>\;
dout(16) <= \<const1>\;
dout(15) <= \<const1>\;
dout(14) <= \<const1>\;
dout(13) <= \<const1>\;
dout(12) <= \<const1>\;
dout(11) <= \<const1>\;
dout(10) <= \<const1>\;
dout(9) <= \<const1>\;
dout(8) <= \<const1>\;
dout(7) <= \<const1>\;
dout(6) <= \<const1>\;
dout(5) <= \<const1>\;
dout(4) <= \<const1>\;
dout(3) <= \<const1>\;
dout(2) <= \<const1>\;
dout(1) <= \<const1>\;
dout(0) <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 033f1228fd23e4d1c320145561724dec | 0.587126 | 3.519417 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_sim_netlist.vhdl | 1 | 10,123 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
active : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_1_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal \data_pair[15]_i_1_n_0\ : STD_LOGIC;
signal \data_pair[7]_i_1_n_0\ : STD_LOGIC;
signal \data_pair_reg_n_0_[0]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[10]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[11]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[12]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[13]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[14]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[15]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[1]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[2]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[3]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[4]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[5]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[6]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[7]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[8]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[9]\ : STD_LOGIC;
signal rgb_regn_0_0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => \data_pair[7]_i_1_n_0\,
Q => cycle,
R => '0'
);
\data_pair[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle,
I1 => active,
O => \data_pair[15]_i_1_n_0\
);
\data_pair[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => active,
I1 => cycle,
O => \data_pair[7]_i_1_n_0\
);
\data_pair_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[0]\,
R => '0'
);
\data_pair_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[10]\,
R => '0'
);
\data_pair_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[11]\,
R => '0'
);
\data_pair_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[12]\,
R => '0'
);
\data_pair_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[13]\,
R => '0'
);
\data_pair_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[14]\,
R => '0'
);
\data_pair_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[15]\,
R => '0'
);
\data_pair_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[1]\,
R => '0'
);
\data_pair_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[2]\,
R => '0'
);
\data_pair_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[3]\,
R => '0'
);
\data_pair_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[4]\,
R => '0'
);
\data_pair_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[5]\,
R => '0'
);
\data_pair_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[6]\,
R => '0'
);
\data_pair_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[7]\,
R => '0'
);
\data_pair_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[8]\,
R => '0'
);
\data_pair_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[9]\,
R => '0'
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[0]\,
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[10]\,
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[11]\,
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[12]\,
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[13]\,
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[14]\,
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[15]\,
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[1]\,
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[2]\,
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[3]\,
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[4]\,
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[5]\,
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[6]\,
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[7]\,
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[8]\,
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[9]\,
Q => rgb(9),
R => '0'
);
rgb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_x2,
O => rgb_regn_0_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_1_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
active => active,
clk_x2 => clk_x2,
data(7 downto 0) => data(7 downto 0),
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | e311fa7d5b1747371a8264b258d1f815 | 0.506569 | 2.785636 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_laplacian_fusion_0_0/synth/system_vga_laplacian_fusion_0_0.vhd | 1 | 4,371 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_laplacian_fusion:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_laplacian_fusion_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rgb_blur_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_blur_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_laplacian_fusion_0_0;
ARCHITECTURE system_vga_laplacian_fusion_0_0_arch OF system_vga_laplacian_fusion_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_laplacian_fusion_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_laplacian_fusion IS
PORT (
clk_25 : IN STD_LOGIC;
rgb_blur_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_blur_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_laplacian_fusion;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_laplacian_fusion_0_0_arch: ARCHITECTURE IS "vga_laplacian_fusion,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_laplacian_fusion_0_0_arch : ARCHITECTURE IS "system_vga_laplacian_fusion_0_0,vga_laplacian_fusion,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_laplacian_fusion_0_0_arch: ARCHITECTURE IS "system_vga_laplacian_fusion_0_0,vga_laplacian_fusion,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_laplacian_fusion,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : vga_laplacian_fusion
PORT MAP (
clk_25 => clk_25,
rgb_blur_0 => rgb_blur_0,
rgb_pass_0 => rgb_pass_0,
rgb_blur_1 => rgb_blur_1,
rgb_pass_1 => rgb_pass_1,
rgb_out => rgb_out
);
END system_vga_laplacian_fusion_0_0_arch;
| mit | eedd2b8f4b0f09a6c735b30f3696d70c | 0.734157 | 3.597531 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_hs_clk_phy.vhd | 1 | 1,755 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--High-Speed D-PHY clock RX PHY for MIPI CSI-2 Rx core
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
-- This receives the input clock and produces both real and complement DDR bit
-- clocks and an SDR (i.e. in/4) byte clock for the SERDES and other downstream devices
entity csi_rx_hs_clk_phy is
generic (
series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6
term_en : boolean := true
);
port (
dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --D-PHY clock input; 1 is P, 0 is N
reset : in STD_LOGIC; --reset input for BUFR
ddr_bit_clock : out STD_LOGIC; --DDR bit clock (i.e. input clock buffered) out
ddr_bit_clock_b : out STD_LOGIC; --Inverted DDR bit clock out
byte_clock : out STD_LOGIC --SDR byte clock (i.e. input clock / 4) out
);
end csi_rx_hs_clk_phy;
architecture Behavioral of csi_rx_hs_clk_phy is
signal bit_clock_int_pre : std_logic;
signal bit_clock_int : std_logic;
signal bit_clock_b_int : std_logic;
signal byte_clock_int : std_logic;
begin
iclkdbuf : IBUFDS
generic map (
DIFF_TERM => term_en,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT"
)
port map(
O => bit_clock_int_pre,
I => dphy_clk(1),
IB => dphy_clk(0)
);
iclkbufio: BUFIO
port map (
O => bit_clock_int,
I => bit_clock_int_pre
);
bit_clock_b_int <= NOT bit_clock_int;
clkdiv : BUFR
generic map (
BUFR_DIVIDE => "4",
SIM_DEVICE => series
)
port map (
O => byte_clock_int,
CE => '1',
CLR => reset,
I => bit_clock_int_pre
);
ddr_bit_clock <= bit_clock_int;
ddr_bit_clock_b <= bit_clock_b_int;
byte_clock <= byte_clock_int;
end Behavioral;
| mit | faeecdb9ab6b2aa740895f65d583022c | 0.647293 | 2.94958 | false | false | false | false |
pgavin/carpe | hdl/cpu/bpb/bimod/cpu_bpb_bimod-rtl.vhdl | 1 | 4,142 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
library tech;
use work.cpu_bpb_bimod_pkg.all;
use work.cpu_bpb_bimod_config_pkg.all;
architecture rtl of cpu_bpb_bimod is
-- weakly not taken. 0xxx is not taken, 1xxx is taken
constant wnt : cpu_bpb_bimod_state_type := (cpu_bpb_bimod_state_bits-1 => '0', others => '1');
type comb_type is record
syncram_we : std_ulogic;
syncram_waddr : std_ulogic_vector(cpu_bpb_bimod_index_bits-1 downto 0);
syncram_wdata : cpu_bpb_bimod_state_type;
syncram_re : std_ulogic;
syncram_raddr : std_ulogic_vector(cpu_bpb_bimod_index_bits-1 downto 0);
syncram_rdata : cpu_bpb_bimod_state_type;
wstate_sat0 : std_ulogic;
wstate_sat1 : std_ulogic;
wstate_sel : std_ulogic_vector(2 downto 0);
wstate : cpu_bpb_bimod_state_type;
end record;
signal c : comb_type;
begin
-- saturating counter increment
c.wstate_sat0 <= all_zeros(cpu_bpb_bimod_dp_in.wstate);
c.wstate_sat1 <= all_ones(cpu_bpb_bimod_dp_in.wstate);
c.wstate_sel <= (
2 => cpu_bpb_bimod_ctrl_in.wtaken,
1 => c.wstate_sat1,
0 => c.wstate_sat0
);
with c.wstate_sel select
c.wstate <= std_ulogic_vector(unsigned(cpu_bpb_bimod_dp_in.wstate) + to_unsigned(1, cpu_bpb_bimod_state_bits)) when "100" | "101", -- taken, not saturated
(others => '1') when "110", -- taken, saturated
std_ulogic_vector(unsigned(cpu_bpb_bimod_dp_in.wstate) - to_unsigned(1, cpu_bpb_bimod_state_bits)) when "000" | "010", -- not taken, not saturated
(others => '0') when "001", -- not taken, saturated
(others => 'X') when others;
c.syncram_we <= cpu_bpb_bimod_ctrl_in.wen;
c.syncram_waddr <= cpu_bpb_bimod_dp_in.waddr(cpu_bpb_bimod_index_bits-1 downto 0);
c.syncram_wdata <= c.wstate;
c.syncram_re <= cpu_bpb_bimod_ctrl_in.ren;
c.syncram_raddr <= cpu_bpb_bimod_dp_in.raddr(cpu_bpb_bimod_index_bits-1 downto 0);
-- bpb outputs
cpu_bpb_bimod_ctrl_out <= (
rtaken => c.syncram_rdata(cpu_bpb_bimod_state_bits-1)
);
cpu_bpb_bimod_dp_out <= (
rstate => c.syncram_rdata
);
sram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => cpu_bpb_bimod_index_bits,
data_bits => cpu_bpb_bimod_state_bits,
write_first => true
)
port map (
clk => clk,
we => c.syncram_we,
waddr => c.syncram_waddr,
wdata => c.syncram_wdata,
re => c.syncram_re,
raddr => c.syncram_raddr,
rdata => c.syncram_rdata
);
end;
| apache-2.0 | 4f8768103c70437ade8ba8b9a64771cf | 0.529937 | 3.694915 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/prioritizer_inferred-rtl.vhdl | 1 | 19,302 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of prioritizer_inferred is
begin
input_bits_1 : if input_bits = 1 generate
dataout <= datain;
end generate;
input_bits_2 : if input_bits = 2 generate
dataout <= (others => 'X') when is_x(datain(1)) else
"10" when datain(1) = '1' else
"0X" when is_x(datain(0)) else
"01" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_3 : if input_bits = 3 generate
dataout <= (others => 'X') when is_x(datain(2)) else
"100" when datain(2) = '1' else
"0XX" when is_x(datain(1)) else
"010" when datain(1) = '1' else
"00X" when is_x(datain(0)) else
"001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_4 : if input_bits = 4 generate
dataout <= (others => 'X') when is_x(datain(3)) else
"1000" when datain(3) = '1' else
"0XXX" when is_x(datain(2)) else
"0100" when datain(2) = '1' else
"00XX" when is_x(datain(1)) else
"0010" when datain(1) = '1' else
"000X" when is_x(datain(0)) else
"0001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_5 : if input_bits = 5 generate
dataout <= (others => 'X') when is_x(datain(4)) else
"10000" when datain(4) = '1' else
"0XXXX" when is_x(datain(3)) else
"01000" when datain(3) = '1' else
"00XXX" when is_x(datain(2)) else
"00100" when datain(2) = '1' else
"000XX" when is_x(datain(1)) else
"00010" when datain(1) = '1' else
"0000X" when is_x(datain(0)) else
"00001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_6 : if input_bits = 6 generate
dataout <= (others => 'X') when is_x(datain(5)) else
"100000" when datain(5) = '1' else
"0XXXXX" when is_x(datain(4)) else
"010000" when datain(4) = '1' else
"00XXXX" when is_x(datain(3)) else
"001000" when datain(3) = '1' else
"000XXX" when is_x(datain(2)) else
"000100" when datain(2) = '1' else
"0000XX" when is_x(datain(1)) else
"000010" when datain(1) = '1' else
"00000X" when is_x(datain(0)) else
"000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_7 : if input_bits = 7 generate
dataout <= (others => 'X') when is_x(datain(6)) else
"1000000" when datain(6) = '1' else
"0XXXXXX" when is_x(datain(5)) else
"0100000" when datain(5) = '1' else
"00XXXXX" when is_x(datain(4)) else
"0010000" when datain(4) = '1' else
"000XXXX" when is_x(datain(3)) else
"0001000" when datain(3) = '1' else
"0000XXX" when is_x(datain(2)) else
"0000100" when datain(2) = '1' else
"00000XX" when is_x(datain(1)) else
"0000010" when datain(1) = '1' else
"000000X" when is_x(datain(0)) else
"0000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_8 : if input_bits = 8 generate
dataout <= (others => 'X') when is_x(datain(7)) else
"10000000" when datain(7) = '1' else
"0XXXXXXX" when is_x(datain(6)) else
"01000000" when datain(6) = '1' else
"00XXXXXX" when is_x(datain(5)) else
"00100000" when datain(5) = '1' else
"000XXXXX" when is_x(datain(4)) else
"00010000" when datain(4) = '1' else
"0000XXXX" when is_x(datain(3)) else
"00001000" when datain(3) = '1' else
"00000XXX" when is_x(datain(2)) else
"00000100" when datain(2) = '1' else
"000000XX" when is_x(datain(1)) else
"00000010" when datain(1) = '1' else
"0000000X" when is_x(datain(0)) else
"00000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_9 : if input_bits = 9 generate
dataout <= (others => 'X') when is_x(datain(8)) else
"100000000" when datain(8) = '1' else
"0XXXXXXXX" when is_x(datain(7)) else
"010000000" when datain(7) = '1' else
"00XXXXXXX" when is_x(datain(6)) else
"001000000" when datain(6) = '1' else
"000XXXXXX" when is_x(datain(5)) else
"000100000" when datain(5) = '1' else
"0000XXXXX" when is_x(datain(4)) else
"000010000" when datain(4) = '1' else
"00000XXXX" when is_x(datain(3)) else
"000001000" when datain(3) = '1' else
"000000XXX" when is_x(datain(2)) else
"000000100" when datain(2) = '1' else
"0000000XX" when is_x(datain(1)) else
"000000010" when datain(1) = '1' else
"00000000X" when is_x(datain(0)) else
"000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_10 : if input_bits = 10 generate
dataout <= (others => 'X') when is_x(datain(9)) else
"1000000000" when datain(9) = '1' else
"0XXXXXXXXX" when is_x(datain(8)) else
"0100000000" when datain(8) = '1' else
"00XXXXXXXX" when is_x(datain(7)) else
"0010000000" when datain(7) = '1' else
"000XXXXXXX" when is_x(datain(6)) else
"0001000000" when datain(6) = '1' else
"0000XXXXXX" when is_x(datain(5)) else
"0000100000" when datain(5) = '1' else
"00000XXXXX" when is_x(datain(4)) else
"0000010000" when datain(4) = '1' else
"000000XXXX" when is_x(datain(3)) else
"0000001000" when datain(3) = '1' else
"0000000XXX" when is_x(datain(2)) else
"0000000100" when datain(2) = '1' else
"00000000XX" when is_x(datain(1)) else
"0000000010" when datain(1) = '1' else
"000000000X" when is_x(datain(0)) else
"0000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_11 : if input_bits = 11 generate
dataout <= (others => 'X') when is_x(datain(10)) else
"10000000000" when datain(10) = '1' else
"0XXXXXXXXXX" when is_x(datain(9)) else
"01000000000" when datain(9) = '1' else
"00XXXXXXXXX" when is_x(datain(8)) else
"00100000000" when datain(8) = '1' else
"000XXXXXXXX" when is_x(datain(7)) else
"00010000000" when datain(7) = '1' else
"0000XXXXXXX" when is_x(datain(6)) else
"00001000000" when datain(6) = '1' else
"00000XXXXXX" when is_x(datain(5)) else
"00000100000" when datain(5) = '1' else
"000000XXXXX" when is_x(datain(4)) else
"00000010000" when datain(4) = '1' else
"0000000XXXX" when is_x(datain(3)) else
"00000001000" when datain(3) = '1' else
"00000000XXX" when is_x(datain(2)) else
"00000000100" when datain(2) = '1' else
"000000000XX" when is_x(datain(1)) else
"00000000010" when datain(1) = '1' else
"0000000000X" when is_x(datain(0)) else
"00000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_12 : if input_bits = 12 generate
dataout <= (others => 'X') when is_x(datain(11)) else
"100000000000" when datain(11) = '1' else
"0XXXXXXXXXXX" when is_x(datain(10)) else
"010000000000" when datain(10) = '1' else
"00XXXXXXXXXX" when is_x(datain(9)) else
"001000000000" when datain(9) = '1' else
"000XXXXXXXXX" when is_x(datain(8)) else
"000100000000" when datain(8) = '1' else
"0000XXXXXXXX" when is_x(datain(7)) else
"000010000000" when datain(7) = '1' else
"00000XXXXXXX" when is_x(datain(6)) else
"000001000000" when datain(6) = '1' else
"000000XXXXXX" when is_x(datain(5)) else
"000000100000" when datain(5) = '1' else
"0000000XXXXX" when is_x(datain(4)) else
"000000010000" when datain(4) = '1' else
"00000000XXXX" when is_x(datain(3)) else
"000000001000" when datain(3) = '1' else
"000000000XXX" when is_x(datain(2)) else
"000000000100" when datain(2) = '1' else
"0000000000XX" when is_x(datain(1)) else
"000000000010" when datain(1) = '1' else
"00000000000X" when is_x(datain(0)) else
"000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_13 : if input_bits = 13 generate
dataout <= (others => 'X') when is_x(datain(12)) else
"1000000000000" when datain(12) = '1' else
"0XXXXXXXXXXXX" when is_x(datain(11)) else
"0100000000000" when datain(11) = '1' else
"00XXXXXXXXXXX" when is_x(datain(10)) else
"0010000000000" when datain(10) = '1' else
"000XXXXXXXXXX" when is_x(datain(9)) else
"0001000000000" when datain(9) = '1' else
"0000XXXXXXXXX" when is_x(datain(8)) else
"0000100000000" when datain(8) = '1' else
"00000XXXXXXXX" when is_x(datain(7)) else
"0000010000000" when datain(7) = '1' else
"000000XXXXXXX" when is_x(datain(6)) else
"0000001000000" when datain(6) = '1' else
"0000000XXXXXX" when is_x(datain(5)) else
"0000000100000" when datain(5) = '1' else
"00000000XXXXX" when is_x(datain(4)) else
"0000000010000" when datain(4) = '1' else
"000000000XXXX" when is_x(datain(3)) else
"0000000001000" when datain(3) = '1' else
"0000000000XXX" when is_x(datain(2)) else
"0000000000100" when datain(2) = '1' else
"00000000000XX" when is_x(datain(1)) else
"0000000000010" when datain(1) = '1' else
"000000000000X" when is_x(datain(0)) else
"0000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_14 : if input_bits = 14 generate
dataout <= (others => 'X') when is_x(datain(13)) else
"10000000000000" when datain(13) = '1' else
"0XXXXXXXXXXXXX" when is_x(datain(12)) else
"01000000000000" when datain(12) = '1' else
"00XXXXXXXXXXXX" when is_x(datain(11)) else
"00100000000000" when datain(11) = '1' else
"000XXXXXXXXXXX" when is_x(datain(10)) else
"00010000000000" when datain(10) = '1' else
"0000XXXXXXXXXX" when is_x(datain(9)) else
"00001000000000" when datain(9) = '1' else
"00000XXXXXXXXX" when is_x(datain(8)) else
"00000100000000" when datain(8) = '1' else
"000000XXXXXXXX" when is_x(datain(7)) else
"00000010000000" when datain(7) = '1' else
"0000000XXXXXXX" when is_x(datain(6)) else
"00000001000000" when datain(6) = '1' else
"00000000XXXXXX" when is_x(datain(5)) else
"00000000100000" when datain(5) = '1' else
"000000000XXXXX" when is_x(datain(4)) else
"00000000010000" when datain(4) = '1' else
"0000000000XXXX" when is_x(datain(3)) else
"00000000001000" when datain(3) = '1' else
"00000000000XXX" when is_x(datain(2)) else
"00000000000100" when datain(2) = '1' else
"000000000000XX" when is_x(datain(1)) else
"00000000000010" when datain(1) = '1' else
"0000000000000X" when is_x(datain(0)) else
"00000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_15 : if input_bits = 15 generate
dataout <= (others => 'X') when is_x(datain(14)) else
"100000000000000" when datain(14) = '1' else
"0XXXXXXXXXXXXXX" when is_x(datain(13)) else
"010000000000000" when datain(13) = '1' else
"00XXXXXXXXXXXXX" when is_x(datain(12)) else
"001000000000000" when datain(12) = '1' else
"000XXXXXXXXXXXX" when is_x(datain(11)) else
"000100000000000" when datain(11) = '1' else
"0000XXXXXXXXXXX" when is_x(datain(10)) else
"000010000000000" when datain(10) = '1' else
"00000XXXXXXXXXX" when is_x(datain(9)) else
"000001000000000" when datain(9) = '1' else
"000000XXXXXXXXX" when is_x(datain(8)) else
"000000100000000" when datain(8) = '1' else
"0000000XXXXXXXX" when is_x(datain(7)) else
"000000010000000" when datain(7) = '1' else
"00000000XXXXXXX" when is_x(datain(6)) else
"000000001000000" when datain(6) = '1' else
"000000000XXXXXX" when is_x(datain(5)) else
"000000000100000" when datain(5) = '1' else
"0000000000XXXXX" when is_x(datain(4)) else
"000000000010000" when datain(4) = '1' else
"00000000000XXXX" when is_x(datain(3)) else
"000000000001000" when datain(3) = '1' else
"000000000000XXX" when is_x(datain(2)) else
"000000000000100" when datain(2) = '1' else
"0000000000000XX" when is_x(datain(1)) else
"000000000000010" when datain(1) = '1' else
"00000000000000X" when is_x(datain(0)) else
"000000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_16 : if input_bits = 16 generate
dataout <= (others => 'X') when is_x(datain(15)) else
"1000000000000000" when datain(15) = '1' else
"0XXXXXXXXXXXXXXX" when is_x(datain(14)) else
"0100000000000000" when datain(14) = '1' else
"00XXXXXXXXXXXXXX" when is_x(datain(13)) else
"0010000000000000" when datain(13) = '1' else
"000XXXXXXXXXXXXX" when is_x(datain(12)) else
"0001000000000000" when datain(12) = '1' else
"0000XXXXXXXXXXXX" when is_x(datain(11)) else
"0000100000000000" when datain(11) = '1' else
"00000XXXXXXXXXXX" when is_x(datain(10)) else
"0000010000000000" when datain(10) = '1' else
"000000XXXXXXXXXX" when is_x(datain(9)) else
"0000001000000000" when datain(9) = '1' else
"0000000XXXXXXXXX" when is_x(datain(8)) else
"0000000100000000" when datain(8) = '1' else
"00000000XXXXXXXX" when is_x(datain(7)) else
"0000000010000000" when datain(7) = '1' else
"000000000XXXXXXX" when is_x(datain(6)) else
"0000000001000000" when datain(6) = '1' else
"0000000000XXXXXX" when is_x(datain(5)) else
"0000000000100000" when datain(5) = '1' else
"00000000000XXXXX" when is_x(datain(4)) else
"0000000000010000" when datain(4) = '1' else
"000000000000XXXX" when is_x(datain(3)) else
"0000000000001000" when datain(3) = '1' else
"0000000000000XXX" when is_x(datain(2)) else
"0000000000000100" when datain(2) = '1' else
"00000000000000XX" when is_x(datain(1)) else
"0000000000000010" when datain(1) = '1' else
"000000000000000X" when is_x(datain(0)) else
"0000000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_out_of_range : if input_bits > 16 generate
input_bits_out_of_rance_proc : process is
begin
assert input_bits > 16 report "input_bits is out of range" severity failure;
wait;
end process;
end generate;
end;
| apache-2.0 | f19388478a518fdb1b468c50f5587b3a | 0.481349 | 3.923171 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_2_0/synth/system_vga_gaussian_blur_2_0.vhd | 1 | 5,235 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_2_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_2_0;
ARCHITECTURE system_vga_gaussian_blur_2_0_arch OF system_vga_gaussian_blur_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_2_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_2_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_2_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_2_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_2_0,vga_gaussian_blur,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_2_0_arch;
| mit | 93aa186cb4f1e4434a466ae329289c1a | 0.698185 | 3.487675 | false | false | false | false |
loa-org/loa-hdl | modules/uart/hdl/uart_rx.vhd | 1 | 6,593 | -------------------------------------------------------------------------------
-- Title : UART Receiver (Odd-Parity)
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-- Data is received with LSB (Least Significat Bit) first.
-- The receiver uses 5x oversampling, therefore clk_rx_en needs to be five times
-- higher than the desired bitrate.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx is
generic (
RESET_IMPL : reset_type := none
);
port (
rxd_p : in std_logic;
disable_p : in std_logic;
data_p : out std_logic_vector(7 downto 0);
we_p : out std_logic;
error_p : out std_logic;
full_p : in std_logic;
clk_rx_en : in std_logic;
reset : in std_logic;
clk : in std_logic);
end uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of uart_rx is
type receive_states is (IDLE, START, DATA);
type uart_rx_type is record
state : receive_states;
bitcount : integer range 0 to 10;
samplecount : integer range 0 to 4;
samples : std_logic_vector(4 downto 0);
parity : std_logic;
-- is set when the reception has been
-- disabled during the last byte
disabled : std_logic;
shift_reg : std_logic_vector(9 downto 0);
-- Output FIFO
fifo_data : std_logic_vector(7 downto 0);
fifo_we : std_logic;
fifo_error : std_logic; -- parity of framing error
end record;
constant uart_rx_type_initial : uart_rx_type := (
state => IDLE,
bitcount => 0,
samplecount => 0,
samples => (others => '0'),
parity => '0',
disabled => '0',
shift_reg => (others => '0'),
fifo_data => (others => '0'),
fifo_we => '0',
fifo_error => '0');
signal r, rin : uart_rx_type := uart_rx_type_initial;
signal voter_output : std_logic := '0';
-- Five bit majority voter.
--
-- Returns '1' if more than two bits in the input vector are set, and
-- '0' otherwise.
function voter(samples : in std_logic_vector(4 downto 0)) return std_logic is
variable cnt : integer range 0 to 5 := 0;
begin
for c in 1 to 3 loop
if samples(c) = '1' then
cnt := cnt + 1;
end if;
end loop;
if cnt >= 2 then
return '1';
else
return '0';
end if;
end voter;
begin
-- Connections between ports and signals
data_p <= r.fifo_data;
we_p <= r.fifo_we;
error_p <= r.fifo_error;
-- Combinatorial part of FSM
comb_proc : process(clk_rx_en, disable_p, r, rxd_p, voter_output, reset)
variable v : uart_rx_type;
begin
v := r;
v.fifo_we := '0';
v.fifo_error := '0';
v.fifo_data := (others => '0');
-- RXD line is constantly sampled.
if clk_rx_en = '1' then
v.samples := r.samples(3 downto 0) & rxd_p;
voter_output <= voter(r.samples);
end if;
if disable_p = '1' then
v.disabled := '1';
end if;
case r.state is
when IDLE =>
if clk_rx_en = '1' then
if rxd_p = '0' then
v.state := START;
v.samplecount := 0;
end if;
end if;
when START =>
if clk_rx_en = '1' then
if r.samplecount = 3 then
if voter_output = '0' then
v.state := DATA;
v.samplecount := 0;
v.bitcount := 0;
v.parity := '0';
else
v.state := IDLE;
end if;
else
v.samplecount := r.samplecount + 1;
end if;
end if;
when DATA =>
if clk_rx_en = '1' then
if r.samplecount = 4 then
v.samplecount := 0;
v.shift_reg := voter_output & r.shift_reg(9 downto 1);
v.parity := r.parity xor voter_output;
if r.bitcount = 9 then
v.state := IDLE;
v.disabled := '0';
-- Only forward the received data if the receiver
-- wasn't disabled during the receiption.
if r.disabled = '0' then
v.fifo_we := '1';
end if;
-- Check for framing errors (= no stop bit) or parity errors
if v.shift_reg(9) = '0' or v.parity = '1' then
v.fifo_error := '1';
end if;
v.fifo_data := v.shift_reg(7 downto 0);
else
v.bitcount := r.bitcount + 1;
end if;
else
v.samplecount := r.samplecount + 1;
end if;
end if;
end case;
-- sync reset
if RESET_IMPL = sync then
if reset = '1' then
v := uart_rx_type_initial;
end if;
end if;
rin <= v;
end process comb_proc;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
reset_async : if RESET_IMPL = async generate
seq_proc : process(clk, reset)
begin
if reset = '1' then
r <= uart_rx_type_initial; -- async reset
elsif rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_async;
reset_sync : if not (RESET_IMPL = async) generate
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_sync;
-- Component instantiations
end behavioural;
| bsd-3-clause | 064f7ae2e85a8223f5a322f1942c0329 | 0.433642 | 4.261797 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/sim/system_vga_sync_ref_0_0.vhd | 5 | 3,959 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_ref:1.0
-- IP Revision: 65
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_ref_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_ref_0_0;
ARCHITECTURE system_vga_sync_ref_0_0_arch OF system_vga_sync_ref_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_ref IS
GENERIC (
H_SIZE : INTEGER;
H_SYNC_SIZE : INTEGER;
V_SIZE : INTEGER;
DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_ref;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_ref
GENERIC MAP (
H_SIZE => 640,
H_SYNC_SIZE => 144,
V_SIZE => 480,
DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
hsync => hsync,
vsync => vsync,
start => start,
active => active,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_ref_0_0_arch;
| mit | 30afb5680219b55e50bea61d2ccd9fea | 0.698409 | 3.892822 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_width_adapter_001.vhd | 1 | 10,501 | -- niosii_system_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 42;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 51;
IN_PKT_BYTE_CNT_L : integer := 49;
IN_PKT_TRANS_COMPRESSED_READ : integer := 43;
IN_PKT_BURSTWRAP_H : integer := 54;
IN_PKT_BURSTWRAP_L : integer := 52;
IN_PKT_BURST_SIZE_H : integer := 57;
IN_PKT_BURST_SIZE_L : integer := 55;
IN_PKT_RESPONSE_STATUS_H : integer := 81;
IN_PKT_RESPONSE_STATUS_L : integer := 80;
IN_PKT_TRANS_EXCLUSIVE : integer := 48;
IN_PKT_BURST_TYPE_H : integer := 59;
IN_PKT_BURST_TYPE_L : integer := 58;
IN_ST_DATA_W : integer := 82;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 69;
OUT_PKT_BYTE_CNT_L : integer := 67;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 61;
OUT_PKT_BURST_SIZE_H : integer := 75;
OUT_PKT_BURST_SIZE_L : integer := 73;
OUT_PKT_RESPONSE_STATUS_H : integer := 99;
OUT_PKT_RESPONSE_STATUS_L : integer := 98;
OUT_PKT_TRANS_EXCLUSIVE : integer := 66;
OUT_PKT_BURST_TYPE_H : integer := 77;
OUT_PKT_BURST_TYPE_L : integer := 76;
OUT_ST_DATA_W : integer := 100;
ST_CHANNEL_W : integer := 13;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(81 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(99 downto 0); -- .data
out_channel : out std_logic_vector(12 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity niosii_system_width_adapter_001;
architecture rtl of niosii_system_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of niosii_system_width_adapter_001
| apache-2.0 | c9bcf079c2cfc11c91eb83b3530bfb7e | 0.461575 | 3.373273 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_control_unit_tb.vhd | 2 | 2,850 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_control_unit"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_control_unit_tb is
end entity goertzel_control_unit_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_control_unit_tb is
-- component generics
constant SAMPLES : positive := 5;
constant FREQUENCIES : positive := 2;
constant CHANNELS : positive := 3;
-- component ports
signal start_p : std_logic := '0';
signal ready_p : std_logic := '0';
signal bram_addr : std_logic_vector(7 downto 0) := (others => '0');
signal bram_we : std_logic := '0';
signal mux_delay1 : std_logic := '0';
signal mux_delay2 : std_logic := '0';
signal mux_coef : natural range FREQUENCIES-1 downto 0;
signal mux_input : natural range CHANNELS-1 downto 0;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_control_unit
generic map (
SAMPLES => SAMPLES,
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS)
port map (
start_p => start_p,
ready_p => ready_p,
bram_addr_p => bram_addr,
bram_we_p => bram_we,
mux_delay1_p => mux_delay1,
mux_delay2_p => mux_delay2,
mux_coef_p => mux_coef,
mux_input_p => mux_input,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- some delay
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- New 12 new samples from ADCs received: start control unit!
start_p <= '1';
wait until clk = '0';
start_p <= '0';
-- wait until all samples for all frequencies are processed and the
-- address counter was reset to 0
wait until bram_addr = "00000000";
-- restart
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause | 75c3e7f1eb667f8084d99f7f8affb171 | 0.454035 | 4.531002 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ipshared/20d6/zed_vga.vhd | 1 | 1,034 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: zed_vga - Structural
-- Description: Output rgb-565 pixel data to zedboard vga
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity zed_vga is
port(
rgb565: in std_logic_vector(15 downto 0);
vga_r: out std_logic_vector(3 downto 0);
vga_g: out std_logic_vector(3 downto 0);
vga_b: out std_logic_vector(3 downto 0)
);
end zed_vga;
architecture Structural of zed_vga is
signal red: std_logic_vector(4 downto 0);
signal green: std_logic_vector(5 downto 0);
signal blue: std_logic_vector(4 downto 0);
begin
red <= rgb565(15 downto 11);
green <= rgb565(10 downto 5);
blue <= rgb565(4 downto 0);
vga_r <= red(4 downto 1);
vga_g <= green(5 downto 2);
vga_b <= blue(4 downto 1);
end Structural;
| mit | 81b36ea746a9765d1604acb85eaf9f04 | 0.542553 | 3.773723 | false | false | false | false |
sbourdeauducq/dspunit | sim/bench_dotdiv.vhd | 2 | 12,301 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dotdiv is
end bench_dotdiv;
--=----------------------------------------------------------------------------
architecture archi_bench_dotdiv of bench_dotdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dotdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "divden.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "divnum.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000110" after 131 ns, "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
--s_data_in_cmdreg <= x"0000", x"004F" after 141 ns, x"0040" after 151 ns, x"02D7" after 161 ns, x"0002" after 171 ns, -- dotdiv, muladd m0,1>m0
s_data_in_cmdreg <= x"0000", x"0003" after 131 ns, x"004F" after 141 ns, x"0040" after 151 ns, x"08C8" after 161 ns, x"0002" after 171 ns, -- dotdiv,m1 / m0 => m2.
-- num shift : 3
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 131 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_dotdiv;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=dotdiv.sav
-------------------------------------------------------------------------------
| gpl-3.0 | 06416c29f26ae11904f0a7d3603457bc | 0.481587 | 3.407479 | false | false | false | false |
loa-org/loa-hdl | modules/spislave/tb/spi_slave_tb.vhd | 2 | 3,411 | -------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave_tb is
end spi_slave_tb;
-------------------------------------------------------------------------------
architecture tb of spi_slave_tb is
-- component ports
signal mosi : std_logic;
signal miso : std_logic;
signal sck : std_logic;
signal csn : std_logic;
signal clk : std_logic := '1';
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
signal bus_data : unsigned(15 downto 0) := (others => '0');
signal debug_addr : std_logic_vector(14 downto 0);
signal debug_data : std_logic_vector(15 downto 0);
begin -- tb
DUT : spi_slave port map (
--ireg => open,
--bit_cnt => open,
miso_p => miso,
mosi_p => mosi,
sck_p => sck,
csn_p => csn,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
Clk <= not Clk after 5.0 ns;
-- Change the bus data to find out when exactly the bus is sampled
process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
bus_i.data <= std_logic_vector(bus_data);
bus_data <= bus_data + 1;
end if;
end process;
process
variable d : std_logic_vector(31 downto 0);
begin
debug_addr <= std_logic_vector(to_unsigned(16#0ff#, 15));
debug_data <= x"fe35";
-- read access to addr 0x7000 with 0x0000 as dummy data.
spiReadWord(addr => 16#7000#, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
-- write access to addr 0x00ff with data 0xfe35
spiWriteWord(addr => debug_addr, data => debug_data, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
--
wait for 1 us;
d := X"8209" & X"cd43";
-- start
csn <= '1';
sck <= '0';
mosi <= '0';
wait for 250 ns;
csn <= '0';
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
-- no pause between two transfers:
if false then
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
wait for 250 ns;
csn <= '0';
wait for 250 ns;
end if;
-- write access to addr 0xf0f with data 0x1234
d := X"8f0f" & X"1234";
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
end process;
end tb;
| bsd-3-clause | 129f2572c4cd3857d3ab7315a38ceaf5 | 0.4292 | 3.952491 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 2,852 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
apply : in STD_LOGIC;
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 );
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
trigger : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
trigger : in STD_LOGIC;
apply : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC;
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system;
begin
system_i: component system
port map (
apply => apply,
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
state(1 downto 0) => state(1 downto 0),
transform => transform,
transform_led => transform_led,
trigger => trigger,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
| mit | d6d4fe14fb71f0bbdd07cc371fb54dfb | 0.571178 | 3.587421 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/synth/system_vga_overlay_0_0.vhd | 3 | 3,985 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_overlay:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_overlay_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_overlay_0_0;
ARCHITECTURE system_vga_overlay_0_0_arch OF system_vga_overlay_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_overlay IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_overlay;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "vga_overlay,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_overlay_0_0_arch : ARCHITECTURE IS "system_vga_overlay_0_0,vga_overlay,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "system_vga_overlay_0_0,vga_overlay,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_overlay,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_overlay
PORT MAP (
clk => clk,
rgb_0 => rgb_0,
rgb_1 => rgb_1,
rgb => rgb
);
END system_vga_overlay_0_0_arch;
| mit | b5b5f2163a33b4b966d90e0308cb80b0 | 0.736261 | 3.770104 | false | false | false | false |
loa-org/loa-hdl | modules/pwm/tb/pwm_tb.vhd | 2 | 1,011 | library ieee;
use ieee.std_logic_1164.all;
entity pwm_tb is
end pwm_tb;
architecture behavior of pwm_tb is
use work.pwm_pkg.all;
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(11 downto 0) := (others => '0');
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal: --__
tb : process
begin
value <= x"7FF";
wait for 200 us;
value <= x"001";
wait for 200 us;
value <= x"FFE";
wait for 200 us;
value <= x"000";
wait for 200 us;
value <= x"FFF";
wait for 200 us;
end process;
uut : pwm
generic map (width => 12)
port map(
clk => clk,
clk_en_p => clk_en,
reset => reset,
value_p => value,
output_p => output);
end;
| bsd-3-clause | 81d33d7c99d8557290cd03311d43189f | 0.492582 | 3.462329 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/desxor1.vhd | 2 | 475 | library ieee;
use ieee.std_logic_1164.all;
entity desxor1 is port
(
e : in std_logic_vector(1 TO 48);
b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: out std_logic_vector (1 TO 6);
k : in std_logic_vector (1 TO 48)
);
end desxor1;
architecture behavior of desxor1 is
signal XX : std_logic_vector( 1 to 48);
begin
XX<=k xor e;
b1x<=XX(1 to 6);
b2x<=XX(7 to 12);
b3x<=XX(13 to 18);
b4x<=XX(19 to 24);
b5x<=XX(25 to 30);
b6x<=XX(31 to 36);
b7x<=XX(37 to 42);
b8x<=XX(43 to 48);
end behavior;
| mit | 8005d355b85376182ddc98c14bdac48c | 0.667368 | 2.074236 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache_pkg.vhdl | 1 | 14,834 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_types_pkg.all;
package cpu_l1mem_data_cache_pkg is
constant cpu_l1mem_data_cache_assoc : natural := 2**cpu_l1mem_data_cache_log2_assoc;
type cpu_l1mem_data_cache_ctrl_in_type is record
-- when '1' indicates a new request, must be '0' while
-- waiting for a miss return, otherwise '1' will cancel
-- a pending request
request : cpu_l1mem_data_request_code_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
alloc : std_ulogic;
writethrough : std_ulogic;
priv : std_ulogic;
be : std_ulogic;
end record;
type cpu_l1mem_data_cache_dp_in_type is record
size : cpu_data_size_type;
vaddr : cpu_vaddr_type;
data : cpu_word_type;
end record;
type cpu_l1mem_data_cache_ctrl_out_type is record
ready : std_ulogic;
result : cpu_l1mem_data_result_code_type;
end record;
type cpu_l1mem_data_cache_dp_out_type is record
paddr : cpu_paddr_type;
data : cpu_word_type;
end record;
constant cpu_l1mem_data_cache_block_bytes : natural := 2**cpu_l1mem_data_cache_offset_bits;
constant cpu_l1mem_data_cache_log2_block_words : natural := cpu_l1mem_data_cache_offset_bits - cpu_log2_word_bytes;
constant cpu_l1mem_data_cache_block_words : natural := 2**cpu_l1mem_data_cache_log2_block_words;
constant cpu_l1mem_data_cache_tag_bits : natural := cpu_paddr_bits - cpu_l1mem_data_cache_index_bits - cpu_l1mem_data_cache_offset_bits;
type cpu_l1mem_data_cache_owner_index_type is (
cpu_l1mem_data_cache_owner_index_none,
cpu_l1mem_data_cache_owner_index_request,
cpu_l1mem_data_cache_owner_index_stb,
cpu_l1mem_data_cache_owner_index_bus_op
);
type cpu_l1mem_data_cache_owner_type is
array (cpu_l1mem_data_cache_owner_index_type range
cpu_l1mem_data_cache_owner_index_type'high downto
cpu_l1mem_data_cache_owner_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_owner_none : cpu_l1mem_data_cache_owner_type := "0001";
constant cpu_l1mem_data_cache_owner_request : cpu_l1mem_data_cache_owner_type := "0010";
constant cpu_l1mem_data_cache_owner_stb : cpu_l1mem_data_cache_owner_type := "0100";
constant cpu_l1mem_data_cache_owner_bus_op : cpu_l1mem_data_cache_owner_type := "1000";
type cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_stb,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_replace
);
type cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0100";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "1000";
type cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_stb
);
type cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "100";
type cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_next_word,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_request_word,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_stb,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_stb_word
);
type cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000100";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "001000";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "010000";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "100000";
type cpu_l1mem_data_cache_a_bus_op_size_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_size_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_word,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_stb
);
type cpu_l1mem_data_cache_a_bus_op_size_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_size_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_size_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_size_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_size_sel_old : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0001";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_word : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0010";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_request : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0100";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_stb : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "1000";
type cpu_l1mem_data_cache_b_result_data_sel_index_type is (
cpu_l1mem_data_cache_b_result_data_sel_index_cache,
cpu_l1mem_data_cache_b_result_data_sel_index_bus,
cpu_l1mem_data_cache_b_result_data_sel_index_bus_shifted,
cpu_l1mem_data_cache_b_result_data_sel_index_stb
);
type cpu_l1mem_data_cache_b_result_data_sel_type is
array (cpu_l1mem_data_cache_b_result_data_sel_index_type range
cpu_l1mem_data_cache_b_result_data_sel_index_type'high downto
cpu_l1mem_data_cache_b_result_data_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_b_result_data_sel_cache : cpu_l1mem_data_cache_b_result_data_sel_type := "0001";
constant cpu_l1mem_data_cache_b_result_data_sel_bus : cpu_l1mem_data_cache_b_result_data_sel_type := "0010";
constant cpu_l1mem_data_cache_b_result_data_sel_bus_shifted : cpu_l1mem_data_cache_b_result_data_sel_type := "0100";
constant cpu_l1mem_data_cache_b_result_data_sel_stb : cpu_l1mem_data_cache_b_result_data_sel_type := "1000";
type cpu_l1mem_data_cache_dp_in_ctrl_type is record
a_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_head_be : std_ulogic;
a_stb_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_paddr_tag_sel : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_bus_op_paddr_index_sel : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_bus_op_paddr_offset_sel : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_bus_op_size_sel : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_bus_op_cache_paddr_sel_old : std_ulogic;
a_bus_op_sys_paddr_sel_old : std_ulogic;
a_bus_op_sys_data_sel_cache : std_ulogic;
a_vtram_owner : cpu_l1mem_data_cache_owner_type;
a_rmdram_owner : cpu_l1mem_data_cache_owner_type;
a_bus_op_owner : cpu_l1mem_data_cache_owner_type;
a_dram_wdata_be : std_ulogic;
b_vtram_owner : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner : cpu_l1mem_data_cache_owner_type;
b_replace_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_read_data_be : std_ulogic;
b_cache_read_data_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_be : std_ulogic;
b_request_stb_array_hit : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_complete : std_ulogic;
b_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_push_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_combine_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_result_data_sel : cpu_l1mem_data_cache_b_result_data_sel_type;
end record;
type cpu_l1mem_data_cache_dp_out_ctrl_type is record
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_stb_array_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_size_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_block_word_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_word_byte_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_in_vram_type is record
rdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_vram_type is record
re : std_ulogic;
we : std_ulogic;
wdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_vram_type is record
raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_in_mram_type is record
rdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_mram_type is record
re : std_ulogic;
we : std_ulogic;
wdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_mram_type is record
raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_tram_type is record
en : std_ulogic;
we : std_ulogic;
banken : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_in_tram_type is record
rdata : std_ulogic_vector2(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_tram_type is record
addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
wdata : std_ulogic_vector2(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_dram_type is record
en : std_ulogic;
we : std_ulogic;
end record;
type cpu_l1mem_data_cache_dp_in_dram_type is record
rdata : std_ulogic_vector2(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_dram_type is record
banken : std_ulogic_vector(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0);
addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
wdata : std_ulogic_vector2(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
end record;
end package;
| apache-2.0 | a6e05467578d6a95cc377700f81f3583 | 0.676352 | 2.735891 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0_1/synth/system_vga_sync_0_0.vhd | 3 | 4,745 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | 98aa65f0975c5e35a7cdc1e95ece11f7 | 0.702213 | 3.661265 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_sim_netlist.vhdl | 1 | 3,203 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_sim_netlist.vhdl
-- Design : system_clock_splitter_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_1_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_1_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_1_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_1_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_1_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_1_0 : entity is "system_clock_splitter_1_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_1_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_1_0;
architecture STRUCTURE of system_clock_splitter_1_0 is
begin
U0: entity work.system_clock_splitter_1_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
| mit | e4bca34b244a460540a79c9fa9412532 | 0.622854 | 3.48531 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/hdl/hdlc_crc_pkg.vhd | 2 | 3,099 | -------------------------------------------------------------------------------
-- Title : HDLC async Encoder & Decoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- CRC-8 for HDLC, x^8 + x^2 + x^1 + 1
-------------------------------------------------------------------------------
-- Package:
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
-- CRC function:
-- Copyright (C) 1999-2008 Easics NV. (see disclaimer over function)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hdlc_crc_pkg is
function calc_crc_8210(Data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0)) return std_logic_vector;
end package hdlc_crc_pkg;
package body hdlc_crc_pkg is
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Info : [email protected] / http://www.easics.com
--------------------------------------------------------------------------------
-- polynomial: (0 1 2 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function calc_crc_8210(Data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0)) return std_logic_vector is
variable d : std_logic_vector(7 downto 0);
variable c : std_logic_vector(7 downto 0);
variable newcrc : std_logic_vector(7 downto 0);
begin
d := Data;
c := crc;
newcrc(0) := d(7) xor d(6) xor d(0) xor c(0) xor c(6) xor c(7);
newcrc(1) := d(6) xor d(1) xor d(0) xor c(0) xor c(1) xor c(6);
newcrc(2) := d(6) xor d(2) xor d(1) xor d(0) xor c(0) xor c(1) xor c(2) xor c(6);
newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(1) xor c(2) xor c(3) xor c(7);
newcrc(4) := d(4) xor d(3) xor d(2) xor c(2) xor c(3) xor c(4);
newcrc(5) := d(5) xor d(4) xor d(3) xor c(3) xor c(4) xor c(5);
newcrc(6) := d(6) xor d(5) xor d(4) xor c(4) xor c(5) xor c(6);
newcrc(7) := d(7) xor d(6) xor d(5) xor c(5) xor c(6) xor c(7);
return newcrc;
end calc_crc_8210;
end hdlc_crc_pkg;
| bsd-3-clause | 164da6e5773be1e33110f54900446acf | 0.501452 | 3.720288 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/hdl/input_capture.vhd | 2 | 3,017 | -------------------------------------------------------------------------------
-- Title : Input Capture Counter
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package input_capture_pkg is
component input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic;
dir_p : in std_logic;
clk_en_p : in std_logic;
clk : in std_logic);
end component input_capture;
end package input_capture_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_capture is
port (
value_p : out std_logic_vector(15 downto 0);
step_p : in std_logic; -- Encoder Step
dir_p : in std_logic; -- Encoder Direction
clk_en_p : in std_logic; -- Clock enable
clk : in std_logic
);
end entity input_capture;
architecture behavioral of input_capture is
type input_capture_type is record
dir : std_logic;
value : std_logic_vector(15 downto 0);
invalid : std_logic;
cnt : unsigned(15 downto 0); -- Counter value
end record;
signal r, rin : input_capture_type := (
dir => '0',
value => (others => '1'),
invalid => '1',
cnt => (others => '0')
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(clk_en_p, dir_p, r, r.cnt, step_p)
variable v : input_capture_type;
begin
v := r;
if clk_en_p = '1' then
v.cnt := r.cnt + 1;
end if;
-- Check for overflows
if r.cnt = (r.cnt'range => '1') then
v.value := std_logic_vector(r.cnt);
v.invalid := '1';
end if;
-- Next value will bigger, preadjust the output value
if std_logic_vector(r.cnt) >= r.value then
v.value := std_logic_vector(r.cnt);
end if;
if step_p = '1' then
if v.dir = dir_p and r.invalid = '0' then
-- Step is in the same direction as the one before
-- => correct measurement
v.value := std_logic_vector(r.cnt);
else
-- Step in the other direction => invalid value
v.value := (others => '1');
end if;
v.dir := dir_p;
v.cnt := (others => '0');
v.invalid := '0';
end if;
rin <= v;
end process comb_proc;
value_p <= r.value;
end architecture behavioral;
| bsd-3-clause | 51b94962bf15340d2484bdaa02f342a2 | 0.463374 | 3.943791 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.vhdl | 1 | 13,896 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 24 17:28:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_buffer_1_0 -prefix
-- system_vga_buffer_1_0_ system_vga_buffer_1_0_sim_netlist.vhdl
-- Design : system_vga_buffer_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_buffer_1_0_vga_buffer;
architecture STRUCTURE of system_vga_buffer_1_0_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_data_reg_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 24 );
signal NLW_data_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg : label is 24576;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(9),
Q => c_addr_w(9),
R => '0'
);
data_reg: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addr_w(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addr_r(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_DBITERR_UNCONNECTED,
DIADI(31 downto 24) => B"00000000",
DIADI(23 downto 0) => data_w(23 downto 0),
DIBDI(31 downto 0) => B"00000000111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 24) => NLW_data_reg_DOBDO_UNCONNECTED(31 downto 24),
DOBDO(23 downto 0) => data_r(23 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_1_0 : entity is "system_vga_buffer_1_0,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_1_0 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_1_0;
architecture STRUCTURE of system_vga_buffer_1_0 is
begin
U0: entity work.system_vga_buffer_1_0_vga_buffer
port map (
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
x_addr_r(9 downto 0) => x_addr_r(9 downto 0),
x_addr_w(9 downto 0) => x_addr_w(9 downto 0)
);
end STRUCTURE;
| mit | 1ad92b6f845cb420f22045fdef9371fc | 0.526554 | 3.014317 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/sim/system_affine_rotation_generator_0_0.vhd | 1 | 3,693 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:affine_rotation_generator:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_affine_rotation_generator_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
reset : IN STD_LOGIC;
a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_affine_rotation_generator_0_0;
ARCHITECTURE system_affine_rotation_generator_0_0_arch OF system_affine_rotation_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_affine_rotation_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT affine_rotation_generator IS
PORT (
clk_25 : IN STD_LOGIC;
reset : IN STD_LOGIC;
a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT affine_rotation_generator;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : affine_rotation_generator
PORT MAP (
clk_25 => clk_25,
reset => reset,
a00 => a00,
a01 => a01,
a10 => a10,
a11 => a11
);
END system_affine_rotation_generator_0_0_arch;
| mit | d87075a1b7e48a6b6236fa2b2870f959 | 0.729759 | 3.899683 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/sim/system_vga_gaussian_blur_1_0.vhd | 1 | 4,527 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_1_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_1_0;
ARCHITECTURE system_vga_gaussian_blur_1_0_arch OF system_vga_gaussian_blur_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_1_0_arch;
| mit | d0b8f1fdb21998f62c8ed43dc869d48b | 0.685885 | 3.630313 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/e67f/ov7670_controller.vhd | 2 | 2,552 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Structural; | mit | 07a2fb02f42fdbf16d9735233db83646 | 0.51489 | 4.044374 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 4,096 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue May 09 02:12:18 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
gclk : in STD_LOGIC;
hsync : out STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
gclk : in STD_LOGIC;
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
gclk => gclk,
hsync => hsync,
vga_b(3 downto 0) => vga_b(3 downto 0),
vga_g(3 downto 0) => vga_g(3 downto 0),
vga_r(3 downto 0) => vga_r(3 downto 0),
vsync => vsync
);
end STRUCTURE;
| mit | d1a07cbb119b77a9acce1b7285d0b8f5 | 0.584717 | 3.098336 | false | false | false | false |
olofk/libstorage | rtl/vhdl/generic/fifo_generic.vhd | 1 | 2,630 | --
-- FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library libstorage_1;
use libstorage_1.libstorage_pkg.all;
entity fifo_generic is
generic (
type data_type;
DEPTH : positive);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in data_type;
empty_o : out std_ulogic);
end entity fifo_generic;
architecture rtl of fifo_generic is
constant ADDR_WIDTH : natural := clog2(DEPTH);
signal wr_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal rd_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal full_or_empty : std_ulogic;
signal empty_not_full : std_ulogic;
begin
full_o <= full_or_empty and not empty_not_full;
empty_o <= full_or_empty and empty_not_full;
empty_not_full <= (wr_addr(ADDR_WIDTH) ?= rd_addr(ADDR_WIDTH));
full_or_empty <= (wr_addr(ADDR_WIDTH-1 downto 0) ?= rd_addr(ADDR_WIDTH-1 downto 0));
p_main: process (clk) is
begin
if rising_edge(clk) then
if wr_en_i then
wr_addr <= wr_addr + 1;
end if;
if rd_en_i then
rd_addr <= rd_addr + 1;
end if;
if rst then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
end if;
end if;
end process p_main;
dpram: entity libstorage_1.dpram_generic
generic map (
data_type => data_type,
DEPTH => DEPTH)
port map (
clk => clk,
rd_en_i => rd_en_i,
rd_addr_i => rd_addr(ADDR_WIDTH-1 downto 0),
rd_data_o => rd_data_o,
wr_en_i => wr_en_i,
wr_addr_i => wr_addr(ADDR_WIDTH-1 downto 0),
wr_data_i => wr_data_i);
end architecture rtl;
| isc | cd97083da1f5b5b0609d7bd25f8010bf | 0.639163 | 3.275218 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/hdl/imotor_uart_rx.vhd | 2 | 4,215 | -------------------------------------------------------------------------------
-- Title : iMotor UART receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that receives serial data.
--
-- This implementation does not have a baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_rx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_out_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data out
rxd_in_p : in std_logic; -- Serial in
deaf_in_p : in std_logic; -- Ignore rxd_in_p when high.
ready_out_p : out std_logic; -- High for one clock when new data
-- received
parity_error_out_p : out std_logic; -- High when the frame had a parity
-- error
clock_rx_in_p : in std_logic; -- Bit clock for receiver
clk : in std_logic
);
end imotor_uart_rx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_rx is
type imotor_uart_rx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1:
STATE2 -- State 2:
);
type imotor_uart_rx_type is record
state : imotor_uart_rx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_rx_type := (state => IDLE);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
parity_error_out_p <= '0';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r)
variable v : imotor_uart_rx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
v := r;
case r.state is
when IDLE => null;
when STATE1 => null;
when STATE2 => null;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | c931e64c104af642015be8b0f8f43509 | 0.341637 | 6.004274 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/synth/system_vga_gaussian_blur_0_0.vhd | 1 | 4,598 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_0_0;
ARCHITECTURE system_vga_gaussian_blur_0_0_arch OF system_vga_gaussian_blur_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_0_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
clk_25 => clk_25,
hsync_in => hsync_in,
vsync_in => vsync_in,
rgb_in => rgb_in,
hsync_out => hsync_out,
vsync_out => vsync_out,
rgb_blur => rgb_blur,
rgb_pass => rgb_pass
);
END system_vga_gaussian_blur_0_0_arch;
| mit | f149a7fc68901c85e54eb648cf4ab9eb | 0.714441 | 3.550579 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/timestamp_tb.vhd | 2 | 3,656 | -------------------------------------------------------------------------------
-- Title : Testbench for design "timestamp"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: The timestamp generator creates a global timestamp. The
-- timestamp takers sample these timestamps when triggered. The
-- timestamp takers are readable by the bus and maintain
-- consistency by double buffering the timestamp.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
use work.spislave_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity timestamp_tb is
end timestamp_tb;
-------------------------------------------------------------------------------
architecture tb of timestamp_tb is
-- component generics
constant WIDTH : positive := 8;
constant BASE_ADDR_TIMESTAMP_TAKER_1 : positive := 16#0100#;
-- component ports
signal timestamp : timestamp_type := (others => '0');
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal bus_to_stm : busdevice_out_type;
signal trigger_s : std_logic := '0';
signal bank_x_s : std_logic := '0';
signal bank_y_s : std_logic := '1';
signal clk : std_logic := '0';
begin
-- component instantiation
timestamp_generator_1 : entity work.timestamp_generator
port map (
timestamp_o_p => timestamp,
clk => clk);
timestamp_taker_1 : entity work.timestamp_taker
generic map (
BASE_ADDRESS => BASE_ADDR_TIMESTAMP_TAKER_1)
port map (
timestamp_i_p => timestamp,
trigger_i_p => trigger_s,
bank_x_i_p => bank_x_s,
bank_y_i_p => bank_y_s,
bus_o => bus_to_stm,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 20 ns;
waveform : process
begin
wait for 20 ns;
wait for 200 ns;
-- Trigger
wait until rising_edge(clk);
trigger_s <= '1';
wait until rising_edge(clk);
trigger_s <= '0';
wait for 20 ns;
bank_x_s <= '1';
bank_y_s <= '0';
wait for 200 ns;
-- Trigger
wait until rising_edge(clk);
trigger_s <= '1';
wait until rising_edge(clk);
trigger_s <= '0';
wait for 20 ns;
bank_x_s <= '0';
bank_y_s <= '1';
-- do not repeat
wait;
end process waveform;
-- purpose: Read access to the timestamp register from the bus
-- type : combinational
-- inputs :
-- outputs:
bus_read : process
variable timestamp : std_logic_vector(15 downto 0) := (others => '0');
begin -- process bus_read
wait for 400 ns;
readWord(addr => 16#0100#, bus_i => bus_i, clk => clk);
timestamp := bus_to_stm.data;
-- read again after next trigger
wait for 400 ns;
readWord(addr => 16#0100#, bus_i => bus_i, clk => clk);
timestamp := bus_to_stm.data;
wait; -- do not repeat
end process bus_read;
end tb;
| bsd-3-clause | c4d52b5509b4f0274c1d4576825f46ce | 0.470186 | 4.301176 | false | false | false | false |
loa-org/loa-hdl | modules/adc_mcp3008/tb/adc_mcp3008_module_tb.vhd | 2 | 6,210 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_mcp3008_module"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_mcp3008_module_tb is
end adc_mcp3008_module_tb;
-------------------------------------------------------------------------------
architecture tb of adc_mcp3008_module_tb is
use work.adc_mcp3008_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal adc_out_p : adc_mcp3008_spi_out_type;
signal adc_in_p : adc_mcp3008_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal miso_p : std_logic;
signal mosi_p : std_logic;
signal cs_np : std_logic;
signal sck_p : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_mcp3008_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
clk => clk);
-- clock generation
Clk <= not Clk after 10 NS;
adc_in_p.miso <= miso_p;
mosi_p <= adc_out_p.mosi;
cs_np <= adc_out_p.cs_n;
sck_p <= adc_out_P.sck;
-- waveform generation
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 NS;
end process bus_stimulus_proc;
-----------------------------------------------------------------------------
-- ADC side stimulus
-----------------------------------------------------------------------------
process
begin
miso_p <= 'Z';
wait until cs_np = '0';
wait until sck_p = '1';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
-- leading zero of mcp3008
miso_p <= '0';
wait until sck_p = '0';
-- actual MSB of conversion
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= 'Z';
miso_p <= 'Z';
wait until cs_np = '0';
wait until sck_p = '1';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
-- leading zero of mcp3008
miso_p <= '0';
wait until sck_p = '0';
-- actual MSB of conversion
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= 'Z';
end process;
end tb;
-------------------------------------------------------------------------------
configuration adc_mcp3008_module_tb_tb_cfg of adc_mcp3008_module_tb is
for tb
end for;
end adc_mcp3008_module_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | c23fa6705d47627d4cac879190a0db91 | 0.38905 | 3.548571 | false | false | false | false |
cakesmith/Firefly | VHDL/PixelClockGenerator.vhd | 1 | 3,145 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : PixelClockGenerator.vhd
-- /___/ /\ Timestamp : 01/02/2014 12:18:56
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/nick/Jarvis/ipcore_dir/PixelClockGenerator.xaw -st PixelClockGenerator.vhd
--Design Name: PixelClockGenerator
--Device: xc3s250e-4vq100
--
-- Module PixelClockGenerator
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity PixelClockGenerator is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end PixelClockGenerator;
architecture BEHAVIORAL of PixelClockGenerator is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | e435e294ad1bab8a69a495eed5525bf5 | 0.48744 | 3.844743 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_hessian/vga_hessian.srcs/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_3.vhd | 45 | 8,325 | library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
| mit | a1439dfb298ffa4f345aaf0fa598f699 | 0.42967 | 3.611714 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/cache/replace/lru/cpu_l1mem_inst_cache_replace_lru-rtl.vhdl | 1 | 2,122 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_l1mem_inst_cache_replace_lru_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_replace_lru is
begin
lru : entity mem.cache_replace_lru(rtl)
generic map (
log2_assoc => cpu_l1mem_inst_cache_log2_assoc,
index_bits => cpu_l1mem_inst_cache_index_bits
)
port map (
clk => clk,
rstn => rstn,
re => cpu_l1mem_inst_cache_replace_lru_ctrl_in.re,
rindex => cpu_l1mem_inst_cache_replace_lru_dp_in.rindex,
rway => cpu_l1mem_inst_cache_replace_lru_ctrl_out.rway,
rstate => cpu_l1mem_inst_cache_replace_lru_dp_out.rstate,
we => cpu_l1mem_inst_cache_replace_lru_ctrl_in.we,
windex => cpu_l1mem_inst_cache_replace_lru_dp_in.windex,
wway => cpu_l1mem_inst_cache_replace_lru_ctrl_in.wway,
wstate => cpu_l1mem_inst_cache_replace_lru_dp_in.wstate
);
end;
| apache-2.0 | 738204c284a40d60cd809c1faeec7c7f | 0.549953 | 3.915129 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_sim_netlist.vhdl | 1 | 760,084 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:47:09 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_sim_netlist.vhdl
-- Design : system_vga_hessian_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_bindec : entity is "bindec";
end system_vga_hessian_1_0_bindec;
architecture STRUCTURE of system_vga_hessian_1_0_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => ena,
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => addra(1),
O => ena_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_bindec_0 is
port (
enb_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_bindec_0 : entity is "bindec";
end system_vga_hessian_1_0_bindec_0;
architecture STRUCTURE of system_vga_hessian_1_0_bindec_0 is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => enb,
I1 => addrb(0),
I2 => addrb(1),
O => enb_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(1),
I1 => addrb(0),
I2 => enb,
O => enb_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(0),
I1 => enb,
I2 => addrb(1),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end system_vga_hessian_1_0_blk_mem_gen_mux;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\douta[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 8 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
clkb : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
begin
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(3)
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(4)
);
\doutb[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(5)
);
\doutb[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(6)
);
\doutb[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(7)
);
\doutb[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(8)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(0)
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(1)
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_vga_hessian_1_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 1) => B"000000000000000",
DIBDI(0) => dinb(0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => doutb(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => ena,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
I2 => enb,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_vga_hessian_1_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.system_vga_hessian_1_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(0) => DOPBDOP(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_vga_hessian_1_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal enb_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_9\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.system_vga_hessian_1_0_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena => ena,
ena_array(2 downto 0) => ena_array(2 downto 0)
);
\bindec_b.bindec_inst_b\: entity work.system_vga_hessian_1_0_bindec_0
port map (
addrb(1 downto 0) => addrb(13 downto 12),
enb => enb,
enb_array(2 downto 0) => enb_array(2 downto 0)
);
\has_mux_a.A\: entity work.system_vga_hessian_1_0_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_16\,
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(15 downto 7),
ena => ena
);
\has_mux_b.B\: entity work.\system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_17\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addrb(1 downto 0) => addrb(13 downto 12),
clkb => clkb,
doutb(8 downto 0) => doutb(15 downto 7),
enb => enb
);
\ramloop[0].ram.r\: entity work.system_vga_hessian_1_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
dinb(1 downto 0) => dinb(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
doutb(1 downto 0) => doutb(2 downto 1),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(4 downto 3),
dinb(1 downto 0) => dinb(4 downto 3),
douta(1 downto 0) => douta(4 downto 3),
doutb(1 downto 0) => doutb(4 downto 3),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(6 downto 5),
dinb(1 downto 0) => dinb(6 downto 5),
douta(1 downto 0) => douta(6 downto 5),
doutb(1 downto 0) => doutb(6 downto 5),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[4].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[4].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[4].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[4].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[4].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[4].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[4].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[4].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[4].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7) => \ramloop[4].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[4].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[4].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[4].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[4].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[4].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[4].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[4].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[4].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[5].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[5].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[5].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[5].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[5].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[5].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[5].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[5].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[5].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[5].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(1),
enb => enb,
enb_array(0) => enb_array(1),
\top_right_1_reg[14]\(7) => \ramloop[5].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[5].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[5].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[5].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[5].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[5].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[5].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[5].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[5].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[6].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[6].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[6].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[6].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[6].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[6].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[6].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[6].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[6].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[6].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(2),
enb => enb,
enb_array(0) => enb_array(2),
\top_right_1_reg[14]\(7) => \ramloop[6].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[6].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[6].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[6].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[6].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[6].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[6].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[6].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[6].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[7].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\
port map (
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_vga_hessian_1_0_blk_mem_gen_top;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.system_vga_hessian_1_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.system_vga_hessian_1_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 22.148499999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "yes";
end system_vga_hessian_1_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_0";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end system_vga_hessian_1_0_blk_mem_gen_0;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 22.148499999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_vga_hessian_1_0_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15 downto 0) => B"0000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_vga_hessian is
port (
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
clk_x16 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_vga_hessian : entity is "vga_hessian";
end system_vga_hessian_1_0_vga_hessian;
architecture STRUCTURE of system_vga_hessian_1_0_vga_hessian is
signal A : STD_LOGIC_VECTOR ( 15 downto 0 );
signal B : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx : STD_LOGIC;
signal \Lxx0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_1\ : STD_LOGIC;
signal \Lxx0_carry__0_n_2\ : STD_LOGIC;
signal \Lxx0_carry__0_n_3\ : STD_LOGIC;
signal \Lxx0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_1\ : STD_LOGIC;
signal \Lxx0_carry__1_n_2\ : STD_LOGIC;
signal \Lxx0_carry__1_n_3\ : STD_LOGIC;
signal \Lxx0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_n_1\ : STD_LOGIC;
signal \Lxx0_carry__2_n_2\ : STD_LOGIC;
signal \Lxx0_carry__2_n_3\ : STD_LOGIC;
signal Lxx0_carry_i_1_n_0 : STD_LOGIC;
signal Lxx0_carry_i_2_n_0 : STD_LOGIC;
signal Lxx0_carry_i_3_n_0 : STD_LOGIC;
signal Lxx0_carry_i_4_n_0 : STD_LOGIC;
signal Lxx0_carry_i_5_n_0 : STD_LOGIC;
signal Lxx0_carry_i_6_n_0 : STD_LOGIC;
signal Lxx0_carry_n_0 : STD_LOGIC;
signal Lxx0_carry_n_1 : STD_LOGIC;
signal Lxx0_carry_n_2 : STD_LOGIC;
signal Lxx0_carry_n_3 : STD_LOGIC;
signal Lxx_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx_00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_00__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_3\ : STD_LOGIC;
signal Lxx_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lxx_11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_11__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_3\ : STD_LOGIC;
signal \Lxx_2[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[9]\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry_n_7\ : STD_LOGIC;
signal \Lxy_0[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_1 : STD_LOGIC;
signal \Lxy_1_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_2 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxy_3 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy0_carry__2_n_3\ : STD_LOGIC;
signal Lyy0_carry_i_1_n_0 : STD_LOGIC;
signal Lyy0_carry_i_2_n_0 : STD_LOGIC;
signal Lyy0_carry_i_3_n_0 : STD_LOGIC;
signal Lyy0_carry_i_4_n_0 : STD_LOGIC;
signal Lyy0_carry_i_5_n_0 : STD_LOGIC;
signal Lyy0_carry_i_6_n_0 : STD_LOGIC;
signal Lyy0_carry_n_0 : STD_LOGIC;
signal Lyy0_carry_n_1 : STD_LOGIC;
signal Lyy0_carry_n_2 : STD_LOGIC;
signal Lyy0_carry_n_3 : STD_LOGIC;
signal Lyy_0 : STD_LOGIC;
signal \Lyy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lyy_20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_20__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_3\ : STD_LOGIC;
signal \Lyy_2[15]_i_1_n_0\ : STD_LOGIC;
signal Lyy_2_bottom_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right01_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_3\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_2_top_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_top_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal addr_0 : STD_LOGIC;
signal \addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal bottom_left_0 : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \bottom_right_0[0]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[10]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[11]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[12]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[13]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[14]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_3_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_4_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_5_n_0\ : STD_LOGIC;
signal \bottom_right_0[1]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[2]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[3]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[4]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[5]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[6]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[7]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[8]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[9]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_right_1 : STD_LOGIC;
signal \bottom_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \cache[10]_5\ : STD_LOGIC;
signal \cache[9][15]_i_1_n_0\ : STD_LOGIC;
signal \cache_reg[0]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[10]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[3][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[4]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[7][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[8]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[9]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg_gate__0_n_0\ : STD_LOGIC;
signal \cache_reg_gate__10_n_0\ : STD_LOGIC;
signal \cache_reg_gate__11_n_0\ : STD_LOGIC;
signal \cache_reg_gate__12_n_0\ : STD_LOGIC;
signal \cache_reg_gate__13_n_0\ : STD_LOGIC;
signal \cache_reg_gate__14_n_0\ : STD_LOGIC;
signal \cache_reg_gate__15_n_0\ : STD_LOGIC;
signal \cache_reg_gate__16_n_0\ : STD_LOGIC;
signal \cache_reg_gate__17_n_0\ : STD_LOGIC;
signal \cache_reg_gate__18_n_0\ : STD_LOGIC;
signal \cache_reg_gate__19_n_0\ : STD_LOGIC;
signal \cache_reg_gate__1_n_0\ : STD_LOGIC;
signal \cache_reg_gate__20_n_0\ : STD_LOGIC;
signal \cache_reg_gate__21_n_0\ : STD_LOGIC;
signal \cache_reg_gate__22_n_0\ : STD_LOGIC;
signal \cache_reg_gate__23_n_0\ : STD_LOGIC;
signal \cache_reg_gate__24_n_0\ : STD_LOGIC;
signal \cache_reg_gate__25_n_0\ : STD_LOGIC;
signal \cache_reg_gate__26_n_0\ : STD_LOGIC;
signal \cache_reg_gate__27_n_0\ : STD_LOGIC;
signal \cache_reg_gate__28_n_0\ : STD_LOGIC;
signal \cache_reg_gate__29_n_0\ : STD_LOGIC;
signal \cache_reg_gate__2_n_0\ : STD_LOGIC;
signal \cache_reg_gate__30_n_0\ : STD_LOGIC;
signal \cache_reg_gate__3_n_0\ : STD_LOGIC;
signal \cache_reg_gate__4_n_0\ : STD_LOGIC;
signal \cache_reg_gate__5_n_0\ : STD_LOGIC;
signal \cache_reg_gate__6_n_0\ : STD_LOGIC;
signal \cache_reg_gate__7_n_0\ : STD_LOGIC;
signal \cache_reg_gate__8_n_0\ : STD_LOGIC;
signal \cache_reg_gate__9_n_0\ : STD_LOGIC;
signal cache_reg_gate_n_0 : STD_LOGIC;
signal cache_reg_r_0_n_0 : STD_LOGIC;
signal cache_reg_r_1_n_0 : STD_LOGIC;
signal cache_reg_r_n_0 : STD_LOGIC;
signal compute_addr_0 : STD_LOGIC;
signal \compute_addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal compute_addr_2 : STD_LOGIC;
signal \compute_addr_2[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_4_n_0\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_3 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_3[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[9]_i_1_n_0\ : STD_LOGIC;
signal corner : STD_LOGIC;
signal \corner_reg_n_0_[0]\ : STD_LOGIC;
signal \corner_reg_n_0_[10]\ : STD_LOGIC;
signal \corner_reg_n_0_[11]\ : STD_LOGIC;
signal \corner_reg_n_0_[12]\ : STD_LOGIC;
signal \corner_reg_n_0_[13]\ : STD_LOGIC;
signal \corner_reg_n_0_[14]\ : STD_LOGIC;
signal \corner_reg_n_0_[15]\ : STD_LOGIC;
signal \corner_reg_n_0_[1]\ : STD_LOGIC;
signal \corner_reg_n_0_[2]\ : STD_LOGIC;
signal \corner_reg_n_0_[3]\ : STD_LOGIC;
signal \corner_reg_n_0_[4]\ : STD_LOGIC;
signal \corner_reg_n_0_[5]\ : STD_LOGIC;
signal \corner_reg_n_0_[6]\ : STD_LOGIC;
signal \corner_reg_n_0_[7]\ : STD_LOGIC;
signal \corner_reg_n_0_[8]\ : STD_LOGIC;
signal \corner_reg_n_0_[9]\ : STD_LOGIC;
signal cycle : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cycle[0]_i_1_n_0\ : STD_LOGIC;
signal \cycle[0]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1__0_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_2_n_0\ : STD_LOGIC;
signal \cycle_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[2]_rep_n_0\ : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data2 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data5 : STD_LOGIC_VECTOR ( 13 downto 10 );
signal det_0 : STD_LOGIC;
signal det_0_reg_i_2_n_0 : STD_LOGIC;
signal det_0_reg_n_106 : STD_LOGIC;
signal det_0_reg_n_107 : STD_LOGIC;
signal det_0_reg_n_108 : STD_LOGIC;
signal det_0_reg_n_109 : STD_LOGIC;
signal det_0_reg_n_110 : STD_LOGIC;
signal det_0_reg_n_111 : STD_LOGIC;
signal det_0_reg_n_112 : STD_LOGIC;
signal det_0_reg_n_113 : STD_LOGIC;
signal det_0_reg_n_114 : STD_LOGIC;
signal det_0_reg_n_115 : STD_LOGIC;
signal det_0_reg_n_116 : STD_LOGIC;
signal det_0_reg_n_117 : STD_LOGIC;
signal det_0_reg_n_118 : STD_LOGIC;
signal det_0_reg_n_119 : STD_LOGIC;
signal det_0_reg_n_120 : STD_LOGIC;
signal det_0_reg_n_121 : STD_LOGIC;
signal det_0_reg_n_122 : STD_LOGIC;
signal det_0_reg_n_123 : STD_LOGIC;
signal det_0_reg_n_124 : STD_LOGIC;
signal det_0_reg_n_125 : STD_LOGIC;
signal det_0_reg_n_126 : STD_LOGIC;
signal det_0_reg_n_127 : STD_LOGIC;
signal det_0_reg_n_128 : STD_LOGIC;
signal det_0_reg_n_129 : STD_LOGIC;
signal det_0_reg_n_130 : STD_LOGIC;
signal det_0_reg_n_131 : STD_LOGIC;
signal det_0_reg_n_132 : STD_LOGIC;
signal det_0_reg_n_133 : STD_LOGIC;
signal det_0_reg_n_134 : STD_LOGIC;
signal det_0_reg_n_135 : STD_LOGIC;
signal det_0_reg_n_136 : STD_LOGIC;
signal det_0_reg_n_137 : STD_LOGIC;
signal det_0_reg_n_138 : STD_LOGIC;
signal det_0_reg_n_139 : STD_LOGIC;
signal det_0_reg_n_140 : STD_LOGIC;
signal det_0_reg_n_141 : STD_LOGIC;
signal det_0_reg_n_142 : STD_LOGIC;
signal det_0_reg_n_143 : STD_LOGIC;
signal det_0_reg_n_144 : STD_LOGIC;
signal det_0_reg_n_145 : STD_LOGIC;
signal det_0_reg_n_146 : STD_LOGIC;
signal det_0_reg_n_147 : STD_LOGIC;
signal det_0_reg_n_148 : STD_LOGIC;
signal det_0_reg_n_149 : STD_LOGIC;
signal det_0_reg_n_150 : STD_LOGIC;
signal det_0_reg_n_151 : STD_LOGIC;
signal det_0_reg_n_152 : STD_LOGIC;
signal det_0_reg_n_153 : STD_LOGIC;
signal det_abs : STD_LOGIC_VECTOR ( 31 downto 0 );
signal det_abs0 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \det_abs[10]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[11]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[13]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[14]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[15]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[17]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[18]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[19]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[1]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[21]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[22]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[23]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[25]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[26]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[27]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[29]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[2]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[30]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[3]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_7_n_0\ : STD_LOGIC;
signal \det_abs[5]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[6]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[7]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[9]_i_1_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_3\ : STD_LOGIC;
signal det_reg_n_100 : STD_LOGIC;
signal det_reg_n_101 : STD_LOGIC;
signal det_reg_n_102 : STD_LOGIC;
signal det_reg_n_103 : STD_LOGIC;
signal det_reg_n_104 : STD_LOGIC;
signal det_reg_n_105 : STD_LOGIC;
signal det_reg_n_74 : STD_LOGIC;
signal det_reg_n_75 : STD_LOGIC;
signal det_reg_n_76 : STD_LOGIC;
signal det_reg_n_77 : STD_LOGIC;
signal det_reg_n_78 : STD_LOGIC;
signal det_reg_n_79 : STD_LOGIC;
signal det_reg_n_80 : STD_LOGIC;
signal det_reg_n_81 : STD_LOGIC;
signal det_reg_n_82 : STD_LOGIC;
signal det_reg_n_83 : STD_LOGIC;
signal det_reg_n_84 : STD_LOGIC;
signal det_reg_n_85 : STD_LOGIC;
signal det_reg_n_86 : STD_LOGIC;
signal det_reg_n_87 : STD_LOGIC;
signal det_reg_n_88 : STD_LOGIC;
signal det_reg_n_89 : STD_LOGIC;
signal det_reg_n_90 : STD_LOGIC;
signal det_reg_n_91 : STD_LOGIC;
signal det_reg_n_92 : STD_LOGIC;
signal det_reg_n_93 : STD_LOGIC;
signal det_reg_n_94 : STD_LOGIC;
signal det_reg_n_95 : STD_LOGIC;
signal det_reg_n_96 : STD_LOGIC;
signal det_reg_n_97 : STD_LOGIC;
signal det_reg_n_98 : STD_LOGIC;
signal det_reg_n_99 : STD_LOGIC;
signal \din_reg_n_0_[0]\ : STD_LOGIC;
signal \din_reg_n_0_[10]\ : STD_LOGIC;
signal \din_reg_n_0_[11]\ : STD_LOGIC;
signal \din_reg_n_0_[12]\ : STD_LOGIC;
signal \din_reg_n_0_[13]\ : STD_LOGIC;
signal \din_reg_n_0_[14]\ : STD_LOGIC;
signal \din_reg_n_0_[15]\ : STD_LOGIC;
signal \din_reg_n_0_[1]\ : STD_LOGIC;
signal \din_reg_n_0_[2]\ : STD_LOGIC;
signal \din_reg_n_0_[3]\ : STD_LOGIC;
signal \din_reg_n_0_[4]\ : STD_LOGIC;
signal \din_reg_n_0_[5]\ : STD_LOGIC;
signal \din_reg_n_0_[6]\ : STD_LOGIC;
signal \din_reg_n_0_[7]\ : STD_LOGIC;
signal \din_reg_n_0_[8]\ : STD_LOGIC;
signal \din_reg_n_0_[9]\ : STD_LOGIC;
signal dout_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal dout_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal last_value : STD_LOGIC_VECTOR ( 7 downto 0 );
signal left : STD_LOGIC;
signal \left[15]_i_2_n_0\ : STD_LOGIC;
signal \left[15]_i_3_n_0\ : STD_LOGIC;
signal \left_reg_n_0_[0]\ : STD_LOGIC;
signal \left_reg_n_0_[10]\ : STD_LOGIC;
signal \left_reg_n_0_[11]\ : STD_LOGIC;
signal \left_reg_n_0_[12]\ : STD_LOGIC;
signal \left_reg_n_0_[13]\ : STD_LOGIC;
signal \left_reg_n_0_[14]\ : STD_LOGIC;
signal \left_reg_n_0_[15]\ : STD_LOGIC;
signal \left_reg_n_0_[1]\ : STD_LOGIC;
signal \left_reg_n_0_[2]\ : STD_LOGIC;
signal \left_reg_n_0_[3]\ : STD_LOGIC;
signal \left_reg_n_0_[4]\ : STD_LOGIC;
signal \left_reg_n_0_[5]\ : STD_LOGIC;
signal \left_reg_n_0_[6]\ : STD_LOGIC;
signal \left_reg_n_0_[7]\ : STD_LOGIC;
signal \left_reg_n_0_[8]\ : STD_LOGIC;
signal \left_reg_n_0_[9]\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \plusOp_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_7\ : STD_LOGIC;
signal top : STD_LOGIC;
signal \top[15]_i_2_n_0\ : STD_LOGIC;
signal top_left_0 : STD_LOGIC;
signal \top_left_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \top_left_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_reg_n_0_[0]\ : STD_LOGIC;
signal \top_reg_n_0_[10]\ : STD_LOGIC;
signal \top_reg_n_0_[11]\ : STD_LOGIC;
signal \top_reg_n_0_[12]\ : STD_LOGIC;
signal \top_reg_n_0_[13]\ : STD_LOGIC;
signal \top_reg_n_0_[14]\ : STD_LOGIC;
signal \top_reg_n_0_[15]\ : STD_LOGIC;
signal \top_reg_n_0_[1]\ : STD_LOGIC;
signal \top_reg_n_0_[2]\ : STD_LOGIC;
signal \top_reg_n_0_[3]\ : STD_LOGIC;
signal \top_reg_n_0_[4]\ : STD_LOGIC;
signal \top_reg_n_0_[5]\ : STD_LOGIC;
signal \top_reg_n_0_[6]\ : STD_LOGIC;
signal \top_reg_n_0_[7]\ : STD_LOGIC;
signal \top_reg_n_0_[8]\ : STD_LOGIC;
signal \top_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_0 : STD_LOGIC;
signal \top_right_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_1 : STD_LOGIC;
signal \top_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \value_reg_n_0_[0]\ : STD_LOGIC;
signal \value_reg_n_0_[1]\ : STD_LOGIC;
signal \value_reg_n_0_[2]\ : STD_LOGIC;
signal \value_reg_n_0_[3]\ : STD_LOGIC;
signal \value_reg_n_0_[4]\ : STD_LOGIC;
signal \value_reg_n_0_[5]\ : STD_LOGIC;
signal \value_reg_n_0_[6]\ : STD_LOGIC;
signal \value_reg_n_0_[7]\ : STD_LOGIC;
signal wen_i_1_n_0 : STD_LOGIC;
signal wen_i_2_n_0 : STD_LOGIC;
signal wen_reg_n_0 : STD_LOGIC;
signal x : STD_LOGIC;
signal \x0[0]_i_2_n_0\ : STD_LOGIC;
signal \x0[0]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_2_n_0\ : STD_LOGIC;
signal \x0[1]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_1_n_0\ : STD_LOGIC;
signal \x0[2]_i_2_n_0\ : STD_LOGIC;
signal \x0[2]_i_3_n_0\ : STD_LOGIC;
signal \x0[2]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_1_n_0\ : STD_LOGIC;
signal \x0[3]_i_2_n_0\ : STD_LOGIC;
signal \x0[3]_i_3_n_0\ : STD_LOGIC;
signal \x0[3]_i_4_n_0\ : STD_LOGIC;
signal \x0[3]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_6_n_0\ : STD_LOGIC;
signal \x0[4]_i_1_n_0\ : STD_LOGIC;
signal \x0[4]_i_2_n_0\ : STD_LOGIC;
signal \x0[4]_i_3_n_0\ : STD_LOGIC;
signal \x0[4]_i_4_n_0\ : STD_LOGIC;
signal \x0[4]_i_5_n_0\ : STD_LOGIC;
signal \x0[5]_i_1_n_0\ : STD_LOGIC;
signal \x0[5]_i_2_n_0\ : STD_LOGIC;
signal \x0[5]_i_3_n_0\ : STD_LOGIC;
signal \x0[5]_i_4_n_0\ : STD_LOGIC;
signal \x0[5]_i_5_n_0\ : STD_LOGIC;
signal \x0[6]_i_1_n_0\ : STD_LOGIC;
signal \x0[6]_i_2_n_0\ : STD_LOGIC;
signal \x0[6]_i_3_n_0\ : STD_LOGIC;
signal \x0[6]_i_4_n_0\ : STD_LOGIC;
signal \x0[6]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_1_n_0\ : STD_LOGIC;
signal \x0[7]_i_2_n_0\ : STD_LOGIC;
signal \x0[7]_i_3_n_0\ : STD_LOGIC;
signal \x0[7]_i_4_n_0\ : STD_LOGIC;
signal \x0[7]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_6_n_0\ : STD_LOGIC;
signal \x0[7]_i_7_n_0\ : STD_LOGIC;
signal \x0[8]_i_1_n_0\ : STD_LOGIC;
signal \x0[8]_i_2_n_0\ : STD_LOGIC;
signal \x0[8]_i_3_n_0\ : STD_LOGIC;
signal \x0[8]_i_4_n_0\ : STD_LOGIC;
signal \x0[8]_i_5_n_0\ : STD_LOGIC;
signal \x0[8]_i_6_n_0\ : STD_LOGIC;
signal \x0[8]_i_7_n_0\ : STD_LOGIC;
signal \x0[9]_i_1_n_0\ : STD_LOGIC;
signal \x0[9]_i_2_n_0\ : STD_LOGIC;
signal \x0[9]_i_3_n_0\ : STD_LOGIC;
signal \x0[9]_i_4_n_0\ : STD_LOGIC;
signal \x0[9]_i_5_n_0\ : STD_LOGIC;
signal \x0[9]_i_6_n_0\ : STD_LOGIC;
signal \x0[9]_i_7_n_0\ : STD_LOGIC;
signal \x0_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \x0_reg[1]_i_1_n_0\ : STD_LOGIC;
signal x1 : STD_LOGIC;
signal \x1[0]_i_1_n_0\ : STD_LOGIC;
signal \x1[1]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_2_n_0\ : STD_LOGIC;
signal \x1[2]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_1_n_0\ : STD_LOGIC;
signal \x1[3]_i_2_n_0\ : STD_LOGIC;
signal \x1[3]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_1_n_0\ : STD_LOGIC;
signal \x1[4]_i_2_n_0\ : STD_LOGIC;
signal \x1[4]_i_3_n_0\ : STD_LOGIC;
signal \x1[4]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_5_n_0\ : STD_LOGIC;
signal \x1[5]_i_1_n_0\ : STD_LOGIC;
signal \x1[5]_i_2_n_0\ : STD_LOGIC;
signal \x1[5]_i_3_n_0\ : STD_LOGIC;
signal \x1[5]_i_4_n_0\ : STD_LOGIC;
signal \x1[5]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_1_n_0\ : STD_LOGIC;
signal \x1[6]_i_2_n_0\ : STD_LOGIC;
signal \x1[6]_i_3_n_0\ : STD_LOGIC;
signal \x1[6]_i_4_n_0\ : STD_LOGIC;
signal \x1[6]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_6_n_0\ : STD_LOGIC;
signal \x1[6]_i_7_n_0\ : STD_LOGIC;
signal \x1[6]_i_8_n_0\ : STD_LOGIC;
signal \x1[7]_i_1_n_0\ : STD_LOGIC;
signal \x1[7]_i_2_n_0\ : STD_LOGIC;
signal \x1[7]_i_3_n_0\ : STD_LOGIC;
signal \x1[7]_i_4_n_0\ : STD_LOGIC;
signal \x1[7]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_1_n_0\ : STD_LOGIC;
signal \x1[8]_i_2_n_0\ : STD_LOGIC;
signal \x1[8]_i_3_n_0\ : STD_LOGIC;
signal \x1[8]_i_4_n_0\ : STD_LOGIC;
signal \x1[8]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_2_n_0\ : STD_LOGIC;
signal \x1[9]_i_3_n_0\ : STD_LOGIC;
signal \x1[9]_i_4_n_0\ : STD_LOGIC;
signal \x1[9]_i_5_n_0\ : STD_LOGIC;
signal \x1[9]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_7_n_0\ : STD_LOGIC;
signal \x1[9]_i_8_n_0\ : STD_LOGIC;
signal \x_reg_n_0_[0]\ : STD_LOGIC;
signal \x_reg_n_0_[1]\ : STD_LOGIC;
signal \x_reg_n_0_[2]\ : STD_LOGIC;
signal \x_reg_n_0_[3]\ : STD_LOGIC;
signal \x_reg_n_0_[4]\ : STD_LOGIC;
signal \x_reg_n_0_[5]\ : STD_LOGIC;
signal \x_reg_n_0_[6]\ : STD_LOGIC;
signal \x_reg_n_0_[7]\ : STD_LOGIC;
signal \x_reg_n_0_[8]\ : STD_LOGIC;
signal \x_reg_n_0_[9]\ : STD_LOGIC;
signal y1 : STD_LOGIC;
signal \y1[2]_i_1_n_0\ : STD_LOGIC;
signal \y1[3]_i_1_n_0\ : STD_LOGIC;
signal \y1_reg_n_0_[0]\ : STD_LOGIC;
signal \y1_reg_n_0_[1]\ : STD_LOGIC;
signal \y1_reg_n_0_[2]\ : STD_LOGIC;
signal \y1_reg_n_0_[3]\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2[1]_i_1_n_0\ : STD_LOGIC;
signal \y2[2]_i_1_n_0\ : STD_LOGIC;
signal \y2[3]_i_1_n_0\ : STD_LOGIC;
signal \y2_reg_n_0_[0]\ : STD_LOGIC;
signal \y2_reg_n_0_[1]\ : STD_LOGIC;
signal \y2_reg_n_0_[2]\ : STD_LOGIC;
signal \y2_reg_n_0_[3]\ : STD_LOGIC;
signal y3 : STD_LOGIC;
signal \y3[1]_i_1_n_0\ : STD_LOGIC;
signal \y3[2]_i_1_n_0\ : STD_LOGIC;
signal \y3[3]_i_1_n_0\ : STD_LOGIC;
signal \y3_reg_n_0_[0]\ : STD_LOGIC;
signal \y3_reg_n_0_[1]\ : STD_LOGIC;
signal \y3_reg_n_0_[2]\ : STD_LOGIC;
signal \y3_reg_n_0_[3]\ : STD_LOGIC;
signal \y4[2]_i_1_n_0\ : STD_LOGIC;
signal \y4[3]_i_1_n_0\ : STD_LOGIC;
signal y5 : STD_LOGIC;
signal \y5[0]_i_1_n_0\ : STD_LOGIC;
signal \y5[1]_i_1_n_0\ : STD_LOGIC;
signal \y5[2]_i_1_n_0\ : STD_LOGIC;
signal \y5[3]_i_1_n_0\ : STD_LOGIC;
signal y6 : STD_LOGIC;
signal \y6[2]_i_1_n_0\ : STD_LOGIC;
signal \y6[3]_i_1_n_0\ : STD_LOGIC;
signal \y6_reg_n_0_[0]\ : STD_LOGIC;
signal \y6_reg_n_0_[1]\ : STD_LOGIC;
signal \y6_reg_n_0_[2]\ : STD_LOGIC;
signal \y6_reg_n_0_[3]\ : STD_LOGIC;
signal y7 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y7[2]_i_1_n_0\ : STD_LOGIC;
signal \y7[3]_i_1_n_0\ : STD_LOGIC;
signal y8 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y8[3]_i_1_n_0\ : STD_LOGIC;
signal y9 : STD_LOGIC;
signal \y9[3]_i_1_n_0\ : STD_LOGIC;
signal \y_actual_reg_n_0_[0]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[1]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[2]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[3]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[4]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[5]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[6]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[7]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[8]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[9]\ : STD_LOGIC;
signal \NLW_Lxx0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_0_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_0_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_0_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_det_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute HLUTNM : string;
attribute HLUTNM of \Lxx0_carry__0_i_1\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_2\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_3\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__0_i_4\ : label is "lutpair1";
attribute HLUTNM of \Lxx0_carry__0_i_5\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__0_i_6\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_7\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_8\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__1_i_1\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_2\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_3\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__1_i_4\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__1_i_5\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__1_i_6\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_7\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_8\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__2_i_1\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_2\ : label is "lutpair10";
attribute HLUTNM of \Lxx0_carry__2_i_3\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__2_i_6\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_7\ : label is "lutpair10";
attribute HLUTNM of Lxx0_carry_i_1 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_2 : label is "lutpair24";
attribute HLUTNM of Lxx0_carry_i_3 : label is "lutpair1";
attribute HLUTNM of Lxx0_carry_i_4 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_5 : label is "lutpair24";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_10\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_8\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_8\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_10\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_8\ : label is "soft_lutpair32";
attribute HLUTNM of \Lyy0_carry__0_i_1\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_2\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_3\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__0_i_4\ : label is "lutpair13";
attribute HLUTNM of \Lyy0_carry__0_i_5\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__0_i_6\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_7\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_8\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__1_i_1\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_2\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_3\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__1_i_4\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__1_i_5\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__1_i_6\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_7\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_8\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__2_i_1\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_2\ : label is "lutpair22";
attribute HLUTNM of \Lyy0_carry__2_i_3\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__2_i_6\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_7\ : label is "lutpair22";
attribute HLUTNM of Lyy0_carry_i_1 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_2 : label is "lutpair25";
attribute HLUTNM of Lyy0_carry_i_3 : label is "lutpair13";
attribute HLUTNM of Lyy0_carry_i_4 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_5 : label is "lutpair25";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_10\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_11\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_9\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_10\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_9\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_8\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry_i_8\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_11\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \addr_0[0]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[11]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[12]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[13]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_0[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[5]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[6]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[8]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[9]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_1[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \addr_1[10]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[12]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[13]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[3]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[5]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[6]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[7]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[8]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[9]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \bottom_right_0[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bottom_right_0[14]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_5\ : label is "soft_lutpair12";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_0 : label is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_0 : label is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_0 : label is "blk_mem_gen_v8_3_5,Vivado 2016.4";
attribute srl_bus_name : string;
attribute srl_bus_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name : string;
attribute srl_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 ";
attribute SOFT_HLUTNM of cache_reg_gate : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__10\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \cache_reg_gate__11\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__12\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__13\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__14\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__15\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__16\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__17\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__18\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__19\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__20\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__21\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__22\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__23\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__24\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__25\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__26\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__27\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__28\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__29\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__3\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__30\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__4\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__6\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__7\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__8\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__9\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \compute_addr_0[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \compute_addr_2[10]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[11]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[12]_i_2\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_3[10]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[11]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[12]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \compute_addr_3[13]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \cycle[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cycle[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[3]_i_2\ : label is "soft_lutpair15";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cycle_reg[0]\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[0]_rep\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[1]\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep__0\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[2]\ : label is "cycle_reg[2]";
attribute ORIG_CELL_NAME of \cycle_reg[2]_rep\ : label is "cycle_reg[2]";
attribute SOFT_HLUTNM of \det_abs[10]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[11]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[12]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[13]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[14]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[15]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[16]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[17]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[18]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[19]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \det_abs[1]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[21]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[22]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[24]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[25]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[26]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[27]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[28]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[30]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[6]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[8]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[9]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \left[15]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \left[15]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x0[1]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x0[2]_i_4\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[2]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x0[3]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \x0[3]_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[4]_i_4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[4]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[5]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x0[5]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[7]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x0[7]_i_6\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \x0[8]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[8]_i_5\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x0[8]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x0[8]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[9]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x1[3]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_5\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[5]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[5]_i_5\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x1[6]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x1[6]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[6]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[6]_i_8\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x1[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x1[7]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x1[8]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x1[9]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x1[9]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y1[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \y1[3]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y2[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y3[1]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y3[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y3[3]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y4[2]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y4[3]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y5[0]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y5[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y5[2]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y5[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y6[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y6[3]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y7[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y7[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y9[3]_i_1\ : label is "soft_lutpair20";
begin
Lxx0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lxx0_carry_n_0,
CO(2) => Lxx0_carry_n_1,
CO(1) => Lxx0_carry_n_2,
CO(0) => Lxx0_carry_n_3,
CYINIT => '0',
DI(3) => Lxx0_carry_i_1_n_0,
DI(2) => Lxx0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lxx_2_reg_n_0_[0]\,
O(3 downto 0) => A(3 downto 0),
S(3) => Lxx0_carry_i_3_n_0,
S(2) => Lxx0_carry_i_4_n_0,
S(1) => Lxx0_carry_i_5_n_0,
S(0) => Lxx0_carry_i_6_n_0
);
\Lxx0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lxx0_carry_n_0,
CO(3) => \Lxx0_carry__0_n_0\,
CO(2) => \Lxx0_carry__0_n_1\,
CO(1) => \Lxx0_carry__0_n_2\,
CO(0) => \Lxx0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__0_i_1_n_0\,
DI(2) => \Lxx0_carry__0_i_2_n_0\,
DI(1) => \Lxx0_carry__0_i_3_n_0\,
DI(0) => \Lxx0_carry__0_i_4_n_0\,
O(3 downto 0) => A(7 downto 4),
S(3) => \Lxx0_carry__0_i_5_n_0\,
S(2) => \Lxx0_carry__0_i_6_n_0\,
S(1) => \Lxx0_carry__0_i_7_n_0\,
S(0) => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
O => \Lxx0_carry__0_i_1_n_0\
);
\Lxx0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
O => \Lxx0_carry__0_i_2_n_0\
);
\Lxx0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
O => \Lxx0_carry__0_i_3_n_0\
);
\Lxx0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
O => \Lxx0_carry__0_i_4_n_0\
);
\Lxx0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
I3 => \Lxx0_carry__0_i_1_n_0\,
O => \Lxx0_carry__0_i_5_n_0\
);
\Lxx0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
I3 => \Lxx0_carry__0_i_2_n_0\,
O => \Lxx0_carry__0_i_6_n_0\
);
\Lxx0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
I3 => \Lxx0_carry__0_i_3_n_0\,
O => \Lxx0_carry__0_i_7_n_0\
);
\Lxx0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
I3 => \Lxx0_carry__0_i_4_n_0\,
O => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__0_n_0\,
CO(3) => \Lxx0_carry__1_n_0\,
CO(2) => \Lxx0_carry__1_n_1\,
CO(1) => \Lxx0_carry__1_n_2\,
CO(0) => \Lxx0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__1_i_1_n_0\,
DI(2) => \Lxx0_carry__1_i_2_n_0\,
DI(1) => \Lxx0_carry__1_i_3_n_0\,
DI(0) => \Lxx0_carry__1_i_4_n_0\,
O(3 downto 0) => A(11 downto 8),
S(3) => \Lxx0_carry__1_i_5_n_0\,
S(2) => \Lxx0_carry__1_i_6_n_0\,
S(1) => \Lxx0_carry__1_i_7_n_0\,
S(0) => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
O => \Lxx0_carry__1_i_1_n_0\
);
\Lxx0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
O => \Lxx0_carry__1_i_2_n_0\
);
\Lxx0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
O => \Lxx0_carry__1_i_3_n_0\
);
\Lxx0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
O => \Lxx0_carry__1_i_4_n_0\
);
\Lxx0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
I3 => \Lxx0_carry__1_i_1_n_0\,
O => \Lxx0_carry__1_i_5_n_0\
);
\Lxx0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
I3 => \Lxx0_carry__1_i_2_n_0\,
O => \Lxx0_carry__1_i_6_n_0\
);
\Lxx0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
I3 => \Lxx0_carry__1_i_3_n_0\,
O => \Lxx0_carry__1_i_7_n_0\
);
\Lxx0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
I3 => \Lxx0_carry__1_i_4_n_0\,
O => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__1_n_0\,
CO(3) => \NLW_Lxx0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx0_carry__2_n_1\,
CO(1) => \Lxx0_carry__2_n_2\,
CO(0) => \Lxx0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx0_carry__2_i_1_n_0\,
DI(1) => \Lxx0_carry__2_i_2_n_0\,
DI(0) => \Lxx0_carry__2_i_3_n_0\,
O(3 downto 0) => A(15 downto 12),
S(3) => \Lxx0_carry__2_i_4_n_0\,
S(2) => \Lxx0_carry__2_i_5_n_0\,
S(1) => \Lxx0_carry__2_i_6_n_0\,
S(0) => \Lxx0_carry__2_i_7_n_0\
);
\Lxx0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
O => \Lxx0_carry__2_i_1_n_0\
);
\Lxx0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
O => \Lxx0_carry__2_i_2_n_0\
);
\Lxx0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
O => \Lxx0_carry__2_i_3_n_0\
);
\Lxx0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => Lxx_0(14),
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => \Lxx_2_reg_n_0_[15]\,
I4 => Lxx_1(15),
I5 => Lxx_0(15),
O => \Lxx0_carry__2_i_4_n_0\
);
\Lxx0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxx0_carry__2_i_1_n_0\,
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => Lxx_0(14),
O => \Lxx0_carry__2_i_5_n_0\
);
\Lxx0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
I3 => \Lxx0_carry__2_i_2_n_0\,
O => \Lxx0_carry__2_i_6_n_0\
);
\Lxx0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
I3 => \Lxx0_carry__2_i_3_n_0\,
O => \Lxx0_carry__2_i_7_n_0\
);
Lxx0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
O => Lxx0_carry_i_1_n_0
);
Lxx0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_2_n_0
);
Lxx0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
I3 => Lxx0_carry_i_1_n_0,
O => Lxx0_carry_i_3_n_0
);
Lxx0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
I3 => Lxx0_carry_i_2_n_0,
O => Lxx0_carry_i_4_n_0
);
Lxx0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_5_n_0
);
Lxx0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lxx_2_reg_n_0_[0]\,
I1 => Lxx_0(0),
O => Lxx0_carry_i_6_n_0
);
\Lxx_00__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_00__1_carry_n_0\,
CO(2) => \Lxx_00__1_carry_n_1\,
CO(1) => \Lxx_00__1_carry_n_2\,
CO(0) => \Lxx_00__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry_i_1_n_0\,
DI(2) => \Lxx_00__1_carry_i_2_n_0\,
DI(1) => \Lxx_00__1_carry_i_3_n_0\,
DI(0) => \bottom_right_0_reg_n_0_[0]\,
O(3 downto 0) => Lxx_00(3 downto 0),
S(3) => \Lxx_00__1_carry_i_4_n_0\,
S(2) => \Lxx_00__1_carry_i_5_n_0\,
S(1) => \Lxx_00__1_carry_i_6_n_0\,
S(0) => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry_n_0\,
CO(3) => \Lxx_00__1_carry__0_n_0\,
CO(2) => \Lxx_00__1_carry__0_n_1\,
CO(1) => \Lxx_00__1_carry__0_n_2\,
CO(0) => \Lxx_00__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_00(7 downto 4),
S(3) => \Lxx_00__1_carry__0_i_5_n_0\,
S(2) => \Lxx_00__1_carry__0_i_6_n_0\,
S(1) => \Lxx_00__1_carry__0_i_7_n_0\,
S(0) => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[6]\,
I1 => \Lxx_00__1_carry__0_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[5]\,
I3 => \top_right_0_reg_n_0_[5]\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_1_n_0\
);
\Lxx_00__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[5]\,
I1 => \top_right_0_reg_n_0_[5]\,
I2 => \top_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_10_n_0\
);
\Lxx_00__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[4]\,
I1 => \top_right_0_reg_n_0_[4]\,
I2 => \top_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_11_n_0\
);
\Lxx_00__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[7]\,
I1 => \top_right_0_reg_n_0_[7]\,
I2 => \top_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__0_i_12_n_0\
);
\Lxx_00__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[5]\,
I1 => \Lxx_00__1_carry__0_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[4]\,
I3 => \top_right_0_reg_n_0_[4]\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_2_n_0\
);
\Lxx_00__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[4]\,
I1 => \Lxx_00__1_carry__0_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[3]\,
I3 => \top_right_0_reg_n_0_[3]\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry__0_i_3_n_0\
);
\Lxx_00__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[3]\,
I1 => \Lxx_00__1_carry_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[2]\,
I3 => \top_right_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry__0_i_4_n_0\
);
\Lxx_00__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[6]\,
I2 => \top_right_0_reg_n_0_[6]\,
I3 => \bottom_left_0_reg_n_0_[6]\,
I4 => \bottom_right_0_reg_n_0_[7]\,
I5 => \Lxx_00__1_carry__0_i_12_n_0\,
O => \Lxx_00__1_carry__0_i_5_n_0\
);
\Lxx_00__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[5]\,
I2 => \top_right_0_reg_n_0_[5]\,
I3 => \bottom_left_0_reg_n_0_[5]\,
I4 => \bottom_right_0_reg_n_0_[6]\,
I5 => \Lxx_00__1_carry__0_i_9_n_0\,
O => \Lxx_00__1_carry__0_i_6_n_0\
);
\Lxx_00__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[4]\,
I2 => \top_right_0_reg_n_0_[4]\,
I3 => \bottom_left_0_reg_n_0_[4]\,
I4 => \bottom_right_0_reg_n_0_[5]\,
I5 => \Lxx_00__1_carry__0_i_10_n_0\,
O => \Lxx_00__1_carry__0_i_7_n_0\
);
\Lxx_00__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[3]\,
I2 => \top_right_0_reg_n_0_[3]\,
I3 => \bottom_left_0_reg_n_0_[3]\,
I4 => \bottom_right_0_reg_n_0_[4]\,
I5 => \Lxx_00__1_carry__0_i_11_n_0\,
O => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[6]\,
I1 => \top_right_0_reg_n_0_[6]\,
I2 => \top_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__0_i_9_n_0\
);
\Lxx_00__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__0_n_0\,
CO(3) => \Lxx_00__1_carry__1_n_0\,
CO(2) => \Lxx_00__1_carry__1_n_1\,
CO(1) => \Lxx_00__1_carry__1_n_2\,
CO(0) => \Lxx_00__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_00(11 downto 8),
S(3) => \Lxx_00__1_carry__1_i_5_n_0\,
S(2) => \Lxx_00__1_carry__1_i_6_n_0\,
S(1) => \Lxx_00__1_carry__1_i_7_n_0\,
S(0) => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[10]\,
I1 => \Lxx_00__1_carry__1_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[9]\,
I3 => \top_right_0_reg_n_0_[9]\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_1_n_0\
);
\Lxx_00__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[9]\,
I1 => \top_right_0_reg_n_0_[9]\,
I2 => \top_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_10_n_0\
);
\Lxx_00__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[8]\,
I1 => \top_right_0_reg_n_0_[8]\,
I2 => \top_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_11_n_0\
);
\Lxx_00__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[11]\,
I1 => \top_right_0_reg_n_0_[11]\,
I2 => \top_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__1_i_12_n_0\
);
\Lxx_00__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[9]\,
I1 => \Lxx_00__1_carry__1_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[8]\,
I3 => \top_right_0_reg_n_0_[8]\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_2_n_0\
);
\Lxx_00__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[8]\,
I1 => \Lxx_00__1_carry__1_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[7]\,
I3 => \top_right_0_reg_n_0_[7]\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__1_i_3_n_0\
);
\Lxx_00__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[7]\,
I1 => \Lxx_00__1_carry__0_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[6]\,
I3 => \top_right_0_reg_n_0_[6]\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__1_i_4_n_0\
);
\Lxx_00__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[10]\,
I2 => \top_right_0_reg_n_0_[10]\,
I3 => \bottom_left_0_reg_n_0_[10]\,
I4 => \bottom_right_0_reg_n_0_[11]\,
I5 => \Lxx_00__1_carry__1_i_12_n_0\,
O => \Lxx_00__1_carry__1_i_5_n_0\
);
\Lxx_00__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[9]\,
I2 => \top_right_0_reg_n_0_[9]\,
I3 => \bottom_left_0_reg_n_0_[9]\,
I4 => \bottom_right_0_reg_n_0_[10]\,
I5 => \Lxx_00__1_carry__1_i_9_n_0\,
O => \Lxx_00__1_carry__1_i_6_n_0\
);
\Lxx_00__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[8]\,
I2 => \top_right_0_reg_n_0_[8]\,
I3 => \bottom_left_0_reg_n_0_[8]\,
I4 => \bottom_right_0_reg_n_0_[9]\,
I5 => \Lxx_00__1_carry__1_i_10_n_0\,
O => \Lxx_00__1_carry__1_i_7_n_0\
);
\Lxx_00__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[7]\,
I2 => \top_right_0_reg_n_0_[7]\,
I3 => \bottom_left_0_reg_n_0_[7]\,
I4 => \bottom_right_0_reg_n_0_[8]\,
I5 => \Lxx_00__1_carry__1_i_11_n_0\,
O => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[10]\,
I1 => \top_right_0_reg_n_0_[10]\,
I2 => \top_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__1_i_9_n_0\
);
\Lxx_00__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_00__1_carry__2_n_1\,
CO(1) => \Lxx_00__1_carry__2_n_2\,
CO(0) => \Lxx_00__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_00__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_00__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_00__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_00(15 downto 12),
S(3) => \Lxx_00__1_carry__2_i_4_n_0\,
S(2) => \Lxx_00__1_carry__2_i_5_n_0\,
S(1) => \Lxx_00__1_carry__2_i_6_n_0\,
S(0) => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[13]\,
I1 => \Lxx_00__1_carry__2_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[12]\,
I3 => \top_right_0_reg_n_0_[12]\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_1_n_0\
);
\Lxx_00__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => \top_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \bottom_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_10_n_0\
);
\Lxx_00__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_0_reg_n_0_[15]\,
I1 => \bottom_left_0_reg_n_0_[15]\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \top_left_0_reg_n_0_[15]\,
O => \Lxx_00__1_carry__2_i_11_n_0\
);
\Lxx_00__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[14]\,
I1 => \top_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
O => \Lxx_00__1_carry__2_i_12_n_0\
);
\Lxx_00__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[12]\,
I1 => \Lxx_00__1_carry__2_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[11]\,
I3 => \top_right_0_reg_n_0_[11]\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__2_i_2_n_0\
);
\Lxx_00__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[11]\,
I1 => \Lxx_00__1_carry__1_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[10]\,
I3 => \top_right_0_reg_n_0_[10]\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__2_i_3_n_0\
);
\Lxx_00__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_00__1_carry__2_i_10_n_0\,
I1 => \bottom_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
I3 => \top_right_0_reg_n_0_[14]\,
I4 => \bottom_left_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_11_n_0\,
O => \Lxx_00__1_carry__2_i_4_n_0\
);
\Lxx_00__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[13]\,
I2 => \top_right_0_reg_n_0_[13]\,
I3 => \bottom_left_0_reg_n_0_[13]\,
I4 => \bottom_right_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_12_n_0\,
O => \Lxx_00__1_carry__2_i_5_n_0\
);
\Lxx_00__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[12]\,
I2 => \top_right_0_reg_n_0_[12]\,
I3 => \bottom_left_0_reg_n_0_[12]\,
I4 => \bottom_right_0_reg_n_0_[13]\,
I5 => \Lxx_00__1_carry__2_i_8_n_0\,
O => \Lxx_00__1_carry__2_i_6_n_0\
);
\Lxx_00__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[11]\,
I2 => \top_right_0_reg_n_0_[11]\,
I3 => \bottom_left_0_reg_n_0_[11]\,
I4 => \bottom_right_0_reg_n_0_[12]\,
I5 => \Lxx_00__1_carry__2_i_9_n_0\,
O => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \top_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_8_n_0\
);
\Lxx_00__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[12]\,
I1 => \top_right_0_reg_n_0_[12]\,
I2 => \top_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_9_n_0\
);
\Lxx_00__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[2]\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[1]\,
I5 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_1_n_0\
);
\Lxx_00__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => \bottom_left_0_reg_n_0_[1]\,
I1 => \top_right_0_reg_n_0_[1]\,
I2 => \top_left_0_reg_n_0_[1]\,
I3 => \bottom_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_2_n_0\
);
\Lxx_00__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_0_reg_n_0_[1]\,
I1 => \bottom_left_0_reg_n_0_[1]\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \top_left_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_3_n_0\
);
\Lxx_00__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_right_0_reg_n_0_[3]\,
I5 => \Lxx_00__1_carry_i_8_n_0\,
O => \Lxx_00__1_carry_i_4_n_0\
);
\Lxx_00__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_00__1_carry_i_2_n_0\,
I1 => \bottom_right_0_reg_n_0_[2]\,
I2 => \Lxx_00__1_carry_i_9_n_0\,
I3 => \bottom_left_0_reg_n_0_[1]\,
I4 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_5_n_0\
);
\Lxx_00__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_00__1_carry_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[0]\,
I2 => \top_right_0_reg_n_0_[0]\,
I3 => \bottom_left_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_6_n_0\
);
\Lxx_00__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \bottom_left_0_reg_n_0_[0]\,
I1 => \top_right_0_reg_n_0_[0]\,
I2 => \top_left_0_reg_n_0_[0]\,
I3 => \bottom_right_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[3]\,
I1 => \top_right_0_reg_n_0_[3]\,
I2 => \top_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry_i_8_n_0\
);
\Lxx_00__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[2]\,
I1 => \top_right_0_reg_n_0_[2]\,
I2 => \top_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry_i_9_n_0\
);
\Lxx_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(0),
Q => Lxx_0(0),
R => '0'
);
\Lxx_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(10),
Q => Lxx_0(10),
R => '0'
);
\Lxx_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(11),
Q => Lxx_0(11),
R => '0'
);
\Lxx_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(12),
Q => Lxx_0(12),
R => '0'
);
\Lxx_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(13),
Q => Lxx_0(13),
R => '0'
);
\Lxx_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(14),
Q => Lxx_0(14),
R => '0'
);
\Lxx_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(15),
Q => Lxx_0(15),
R => '0'
);
\Lxx_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(1),
Q => Lxx_0(1),
R => '0'
);
\Lxx_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(2),
Q => Lxx_0(2),
R => '0'
);
\Lxx_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(3),
Q => Lxx_0(3),
R => '0'
);
\Lxx_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(4),
Q => Lxx_0(4),
R => '0'
);
\Lxx_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(5),
Q => Lxx_0(5),
R => '0'
);
\Lxx_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(6),
Q => Lxx_0(6),
R => '0'
);
\Lxx_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(7),
Q => Lxx_0(7),
R => '0'
);
\Lxx_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(8),
Q => Lxx_0(8),
R => '0'
);
\Lxx_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(9),
Q => Lxx_0(9),
R => '0'
);
\Lxx_11__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_11__1_carry_n_0\,
CO(2) => \Lxx_11__1_carry_n_1\,
CO(1) => \Lxx_11__1_carry_n_2\,
CO(0) => \Lxx_11__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry_i_1_n_0\,
DI(2) => \Lxx_11__1_carry_i_2_n_0\,
DI(1) => \Lxx_11__1_carry_i_3_n_0\,
DI(0) => \bottom_right_1_reg_n_0_[0]\,
O(3 downto 0) => Lxx_11(3 downto 0),
S(3) => \Lxx_11__1_carry_i_4_n_0\,
S(2) => \Lxx_11__1_carry_i_5_n_0\,
S(1) => \Lxx_11__1_carry_i_6_n_0\,
S(0) => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry_n_0\,
CO(3) => \Lxx_11__1_carry__0_n_0\,
CO(2) => \Lxx_11__1_carry__0_n_1\,
CO(1) => \Lxx_11__1_carry__0_n_2\,
CO(0) => \Lxx_11__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_11(7 downto 4),
S(3) => \Lxx_11__1_carry__0_i_5_n_0\,
S(2) => \Lxx_11__1_carry__0_i_6_n_0\,
S(1) => \Lxx_11__1_carry__0_i_7_n_0\,
S(0) => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[6]\,
I1 => \Lxx_11__1_carry__0_i_9_n_0\,
I2 => top_left_1(5),
I3 => \top_right_1_reg_n_0_[5]\,
I4 => bottom_left_1(5),
O => \Lxx_11__1_carry__0_i_1_n_0\
);
\Lxx_11__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(5),
I1 => \top_right_1_reg_n_0_[5]\,
I2 => top_left_1(5),
O => \Lxx_11__1_carry__0_i_10_n_0\
);
\Lxx_11__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(4),
I1 => \top_right_1_reg_n_0_[4]\,
I2 => top_left_1(4),
O => \Lxx_11__1_carry__0_i_11_n_0\
);
\Lxx_11__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(7),
I1 => \top_right_1_reg_n_0_[7]\,
I2 => top_left_1(7),
O => \Lxx_11__1_carry__0_i_12_n_0\
);
\Lxx_11__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[5]\,
I1 => \Lxx_11__1_carry__0_i_10_n_0\,
I2 => top_left_1(4),
I3 => \top_right_1_reg_n_0_[4]\,
I4 => bottom_left_1(4),
O => \Lxx_11__1_carry__0_i_2_n_0\
);
\Lxx_11__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[4]\,
I1 => \Lxx_11__1_carry__0_i_11_n_0\,
I2 => top_left_1(3),
I3 => \top_right_1_reg_n_0_[3]\,
I4 => bottom_left_1(3),
O => \Lxx_11__1_carry__0_i_3_n_0\
);
\Lxx_11__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[3]\,
I1 => \Lxx_11__1_carry_i_8_n_0\,
I2 => top_left_1(2),
I3 => \top_right_1_reg_n_0_[2]\,
I4 => bottom_left_1(2),
O => \Lxx_11__1_carry__0_i_4_n_0\
);
\Lxx_11__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_1_n_0\,
I1 => top_left_1(6),
I2 => \top_right_1_reg_n_0_[6]\,
I3 => bottom_left_1(6),
I4 => \bottom_right_1_reg_n_0_[7]\,
I5 => \Lxx_11__1_carry__0_i_12_n_0\,
O => \Lxx_11__1_carry__0_i_5_n_0\
);
\Lxx_11__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_2_n_0\,
I1 => top_left_1(5),
I2 => \top_right_1_reg_n_0_[5]\,
I3 => bottom_left_1(5),
I4 => \bottom_right_1_reg_n_0_[6]\,
I5 => \Lxx_11__1_carry__0_i_9_n_0\,
O => \Lxx_11__1_carry__0_i_6_n_0\
);
\Lxx_11__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_3_n_0\,
I1 => top_left_1(4),
I2 => \top_right_1_reg_n_0_[4]\,
I3 => bottom_left_1(4),
I4 => \bottom_right_1_reg_n_0_[5]\,
I5 => \Lxx_11__1_carry__0_i_10_n_0\,
O => \Lxx_11__1_carry__0_i_7_n_0\
);
\Lxx_11__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_4_n_0\,
I1 => top_left_1(3),
I2 => \top_right_1_reg_n_0_[3]\,
I3 => bottom_left_1(3),
I4 => \bottom_right_1_reg_n_0_[4]\,
I5 => \Lxx_11__1_carry__0_i_11_n_0\,
O => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(6),
I1 => \top_right_1_reg_n_0_[6]\,
I2 => top_left_1(6),
O => \Lxx_11__1_carry__0_i_9_n_0\
);
\Lxx_11__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__0_n_0\,
CO(3) => \Lxx_11__1_carry__1_n_0\,
CO(2) => \Lxx_11__1_carry__1_n_1\,
CO(1) => \Lxx_11__1_carry__1_n_2\,
CO(0) => \Lxx_11__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_11(11 downto 8),
S(3) => \Lxx_11__1_carry__1_i_5_n_0\,
S(2) => \Lxx_11__1_carry__1_i_6_n_0\,
S(1) => \Lxx_11__1_carry__1_i_7_n_0\,
S(0) => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[10]\,
I1 => \Lxx_11__1_carry__1_i_9_n_0\,
I2 => top_left_1(9),
I3 => \top_right_1_reg_n_0_[9]\,
I4 => bottom_left_1(9),
O => \Lxx_11__1_carry__1_i_1_n_0\
);
\Lxx_11__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(9),
I1 => \top_right_1_reg_n_0_[9]\,
I2 => top_left_1(9),
O => \Lxx_11__1_carry__1_i_10_n_0\
);
\Lxx_11__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(8),
I1 => \top_right_1_reg_n_0_[8]\,
I2 => top_left_1(8),
O => \Lxx_11__1_carry__1_i_11_n_0\
);
\Lxx_11__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(11),
I1 => \top_right_1_reg_n_0_[11]\,
I2 => top_left_1(11),
O => \Lxx_11__1_carry__1_i_12_n_0\
);
\Lxx_11__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[9]\,
I1 => \Lxx_11__1_carry__1_i_10_n_0\,
I2 => top_left_1(8),
I3 => \top_right_1_reg_n_0_[8]\,
I4 => bottom_left_1(8),
O => \Lxx_11__1_carry__1_i_2_n_0\
);
\Lxx_11__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[8]\,
I1 => \Lxx_11__1_carry__1_i_11_n_0\,
I2 => top_left_1(7),
I3 => \top_right_1_reg_n_0_[7]\,
I4 => bottom_left_1(7),
O => \Lxx_11__1_carry__1_i_3_n_0\
);
\Lxx_11__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[7]\,
I1 => \Lxx_11__1_carry__0_i_12_n_0\,
I2 => top_left_1(6),
I3 => \top_right_1_reg_n_0_[6]\,
I4 => bottom_left_1(6),
O => \Lxx_11__1_carry__1_i_4_n_0\
);
\Lxx_11__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_1_n_0\,
I1 => top_left_1(10),
I2 => \top_right_1_reg_n_0_[10]\,
I3 => bottom_left_1(10),
I4 => \bottom_right_1_reg_n_0_[11]\,
I5 => \Lxx_11__1_carry__1_i_12_n_0\,
O => \Lxx_11__1_carry__1_i_5_n_0\
);
\Lxx_11__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_2_n_0\,
I1 => top_left_1(9),
I2 => \top_right_1_reg_n_0_[9]\,
I3 => bottom_left_1(9),
I4 => \bottom_right_1_reg_n_0_[10]\,
I5 => \Lxx_11__1_carry__1_i_9_n_0\,
O => \Lxx_11__1_carry__1_i_6_n_0\
);
\Lxx_11__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_3_n_0\,
I1 => top_left_1(8),
I2 => \top_right_1_reg_n_0_[8]\,
I3 => bottom_left_1(8),
I4 => \bottom_right_1_reg_n_0_[9]\,
I5 => \Lxx_11__1_carry__1_i_10_n_0\,
O => \Lxx_11__1_carry__1_i_7_n_0\
);
\Lxx_11__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_4_n_0\,
I1 => top_left_1(7),
I2 => \top_right_1_reg_n_0_[7]\,
I3 => bottom_left_1(7),
I4 => \bottom_right_1_reg_n_0_[8]\,
I5 => \Lxx_11__1_carry__1_i_11_n_0\,
O => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(10),
I1 => \top_right_1_reg_n_0_[10]\,
I2 => top_left_1(10),
O => \Lxx_11__1_carry__1_i_9_n_0\
);
\Lxx_11__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_11__1_carry__2_n_1\,
CO(1) => \Lxx_11__1_carry__2_n_2\,
CO(0) => \Lxx_11__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_11__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_11__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_11__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_11(15 downto 12),
S(3) => \Lxx_11__1_carry__2_i_4_n_0\,
S(2) => \Lxx_11__1_carry__2_i_5_n_0\,
S(1) => \Lxx_11__1_carry__2_i_6_n_0\,
S(0) => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[13]\,
I1 => \Lxx_11__1_carry__2_i_8_n_0\,
I2 => top_left_1(12),
I3 => \top_right_1_reg_n_0_[12]\,
I4 => bottom_left_1(12),
O => \Lxx_11__1_carry__2_i_1_n_0\
);
\Lxx_11__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => top_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => bottom_left_1(13),
O => \Lxx_11__1_carry__2_i_10_n_0\
);
\Lxx_11__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_1_reg_n_0_[15]\,
I1 => bottom_left_1(15),
I2 => \bottom_right_1_reg_n_0_[15]\,
I3 => top_left_1(15),
O => \Lxx_11__1_carry__2_i_11_n_0\
);
\Lxx_11__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(14),
I1 => \top_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
O => \Lxx_11__1_carry__2_i_12_n_0\
);
\Lxx_11__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[12]\,
I1 => \Lxx_11__1_carry__2_i_9_n_0\,
I2 => top_left_1(11),
I3 => \top_right_1_reg_n_0_[11]\,
I4 => bottom_left_1(11),
O => \Lxx_11__1_carry__2_i_2_n_0\
);
\Lxx_11__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[11]\,
I1 => \Lxx_11__1_carry__1_i_12_n_0\,
I2 => top_left_1(10),
I3 => \top_right_1_reg_n_0_[10]\,
I4 => bottom_left_1(10),
O => \Lxx_11__1_carry__2_i_3_n_0\
);
\Lxx_11__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_11__1_carry__2_i_10_n_0\,
I1 => \bottom_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
I3 => \top_right_1_reg_n_0_[14]\,
I4 => bottom_left_1(14),
I5 => \Lxx_11__1_carry__2_i_11_n_0\,
O => \Lxx_11__1_carry__2_i_4_n_0\
);
\Lxx_11__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_1_n_0\,
I1 => top_left_1(13),
I2 => \top_right_1_reg_n_0_[13]\,
I3 => bottom_left_1(13),
I4 => \bottom_right_1_reg_n_0_[14]\,
I5 => \Lxx_11__1_carry__2_i_12_n_0\,
O => \Lxx_11__1_carry__2_i_5_n_0\
);
\Lxx_11__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_2_n_0\,
I1 => top_left_1(12),
I2 => \top_right_1_reg_n_0_[12]\,
I3 => bottom_left_1(12),
I4 => \bottom_right_1_reg_n_0_[13]\,
I5 => \Lxx_11__1_carry__2_i_8_n_0\,
O => \Lxx_11__1_carry__2_i_6_n_0\
);
\Lxx_11__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_3_n_0\,
I1 => top_left_1(11),
I2 => \top_right_1_reg_n_0_[11]\,
I3 => bottom_left_1(11),
I4 => \bottom_right_1_reg_n_0_[12]\,
I5 => \Lxx_11__1_carry__2_i_9_n_0\,
O => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => top_left_1(13),
O => \Lxx_11__1_carry__2_i_8_n_0\
);
\Lxx_11__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(12),
I1 => \top_right_1_reg_n_0_[12]\,
I2 => top_left_1(12),
O => \Lxx_11__1_carry__2_i_9_n_0\
);
\Lxx_11__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[2]\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => bottom_left_1(1),
I5 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_1_n_0\
);
\Lxx_11__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => bottom_left_1(1),
I1 => \top_right_1_reg_n_0_[1]\,
I2 => top_left_1(1),
I3 => \bottom_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_2_n_0\
);
\Lxx_11__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_1_reg_n_0_[1]\,
I1 => bottom_left_1(1),
I2 => \bottom_right_1_reg_n_0_[1]\,
I3 => top_left_1(1),
O => \Lxx_11__1_carry_i_3_n_0\
);
\Lxx_11__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry_i_1_n_0\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => \bottom_right_1_reg_n_0_[3]\,
I5 => \Lxx_11__1_carry_i_8_n_0\,
O => \Lxx_11__1_carry_i_4_n_0\
);
\Lxx_11__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_11__1_carry_i_2_n_0\,
I1 => \bottom_right_1_reg_n_0_[2]\,
I2 => \Lxx_11__1_carry_i_9_n_0\,
I3 => bottom_left_1(1),
I4 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_5_n_0\
);
\Lxx_11__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_11__1_carry_i_3_n_0\,
I1 => top_left_1(0),
I2 => \top_right_1_reg_n_0_[0]\,
I3 => bottom_left_1(0),
O => \Lxx_11__1_carry_i_6_n_0\
);
\Lxx_11__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => bottom_left_1(0),
I1 => \top_right_1_reg_n_0_[0]\,
I2 => top_left_1(0),
I3 => \bottom_right_1_reg_n_0_[0]\,
O => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(3),
I1 => \top_right_1_reg_n_0_[3]\,
I2 => top_left_1(3),
O => \Lxx_11__1_carry_i_8_n_0\
);
\Lxx_11__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(2),
I1 => \top_right_1_reg_n_0_[2]\,
I2 => top_left_1(2),
O => \Lxx_11__1_carry_i_9_n_0\
);
\Lxx_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(9),
Q => Lxx_1(10),
R => '0'
);
\Lxx_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(10),
Q => Lxx_1(11),
R => '0'
);
\Lxx_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(11),
Q => Lxx_1(12),
R => '0'
);
\Lxx_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(12),
Q => Lxx_1(13),
R => '0'
);
\Lxx_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(13),
Q => Lxx_1(14),
R => '0'
);
\Lxx_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(14),
Q => Lxx_1(15),
R => '0'
);
\Lxx_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(0),
Q => Lxx_1(1),
R => '0'
);
\Lxx_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(1),
Q => Lxx_1(2),
R => '0'
);
\Lxx_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(2),
Q => Lxx_1(3),
R => '0'
);
\Lxx_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(3),
Q => Lxx_1(4),
R => '0'
);
\Lxx_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(4),
Q => Lxx_1(5),
R => '0'
);
\Lxx_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(5),
Q => Lxx_1(6),
R => '0'
);
\Lxx_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(6),
Q => Lxx_1(7),
R => '0'
);
\Lxx_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(7),
Q => Lxx_1(8),
R => '0'
);
\Lxx_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(8),
Q => Lxx_1(9),
R => '0'
);
\Lxx_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => cycle(2),
I4 => rst,
I5 => active,
O => \Lxx_2[15]_i_1_n_0\
);
\Lxx_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxx_2_reg_n_0_[0]\,
R => '0'
);
\Lxx_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxx_2_reg_n_0_[10]\,
R => '0'
);
\Lxx_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxx_2_reg_n_0_[11]\,
R => '0'
);
\Lxx_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxx_2_reg_n_0_[12]\,
R => '0'
);
\Lxx_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxx_2_reg_n_0_[13]\,
R => '0'
);
\Lxx_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxx_2_reg_n_0_[14]\,
R => '0'
);
\Lxx_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxx_2_reg_n_0_[15]\,
R => '0'
);
\Lxx_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxx_2_reg_n_0_[1]\,
R => '0'
);
\Lxx_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxx_2_reg_n_0_[2]\,
R => '0'
);
\Lxx_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxx_2_reg_n_0_[3]\,
R => '0'
);
\Lxx_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxx_2_reg_n_0_[4]\,
R => '0'
);
\Lxx_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxx_2_reg_n_0_[5]\,
R => '0'
);
\Lxx_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxx_2_reg_n_0_[6]\,
R => '0'
);
\Lxx_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxx_2_reg_n_0_[7]\,
R => '0'
);
\Lxx_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxx_2_reg_n_0_[8]\,
R => '0'
);
\Lxx_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxx_2_reg_n_0_[9]\,
R => '0'
);
\Lxy0__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxy0__1_carry_n_0\,
CO(2) => \Lxy0__1_carry_n_1\,
CO(1) => \Lxy0__1_carry_n_2\,
CO(0) => \Lxy0__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry_i_1_n_0\,
DI(2) => \Lxy0__1_carry_i_2_n_0\,
DI(1) => \Lxy0__1_carry_i_3_n_0\,
DI(0) => \Lxy_0_reg_n_0_[0]\,
O(3) => \Lxy0__1_carry_n_4\,
O(2) => \Lxy0__1_carry_n_5\,
O(1) => \Lxy0__1_carry_n_6\,
O(0) => \Lxy0__1_carry_n_7\,
S(3) => \Lxy0__1_carry_i_4_n_0\,
S(2) => \Lxy0__1_carry_i_5_n_0\,
S(1) => \Lxy0__1_carry_i_6_n_0\,
S(0) => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry_n_0\,
CO(3) => \Lxy0__1_carry__0_n_0\,
CO(2) => \Lxy0__1_carry__0_n_1\,
CO(1) => \Lxy0__1_carry__0_n_2\,
CO(0) => \Lxy0__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__0_i_1_n_0\,
DI(2) => \Lxy0__1_carry__0_i_2_n_0\,
DI(1) => \Lxy0__1_carry__0_i_3_n_0\,
DI(0) => \Lxy0__1_carry__0_i_4_n_0\,
O(3) => \Lxy0__1_carry__0_n_4\,
O(2) => \Lxy0__1_carry__0_n_5\,
O(1) => \Lxy0__1_carry__0_n_6\,
O(0) => \Lxy0__1_carry__0_n_7\,
S(3) => \Lxy0__1_carry__0_i_5_n_0\,
S(2) => \Lxy0__1_carry__0_i_6_n_0\,
S(1) => \Lxy0__1_carry__0_i_7_n_0\,
S(0) => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[6]\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => Lxy_3(5),
I3 => Lxy_2(5),
I4 => \Lxy_1_reg_n_0_[5]\,
O => \Lxy0__1_carry__0_i_1_n_0\
);
\Lxy0__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(5),
I1 => \Lxy_1_reg_n_0_[5]\,
I2 => Lxy_2(5),
O => \Lxy0__1_carry__0_i_10_n_0\
);
\Lxy0__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(4),
I1 => \Lxy_1_reg_n_0_[4]\,
I2 => Lxy_2(4),
O => \Lxy0__1_carry__0_i_11_n_0\
);
\Lxy0__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(7),
I1 => \Lxy_1_reg_n_0_[7]\,
I2 => Lxy_2(7),
O => \Lxy0__1_carry__0_i_12_n_0\
);
\Lxy0__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[5]\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => Lxy_3(4),
I3 => Lxy_2(4),
I4 => \Lxy_1_reg_n_0_[4]\,
O => \Lxy0__1_carry__0_i_2_n_0\
);
\Lxy0__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[4]\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => Lxy_3(3),
I3 => Lxy_2(3),
I4 => \Lxy_1_reg_n_0_[3]\,
O => \Lxy0__1_carry__0_i_3_n_0\
);
\Lxy0__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[3]\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => Lxy_3(2),
I3 => Lxy_2(2),
I4 => \Lxy_1_reg_n_0_[2]\,
O => \Lxy0__1_carry__0_i_4_n_0\
);
\Lxy0__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_1_n_0\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[7]\,
I3 => \Lxy_1_reg_n_0_[6]\,
I4 => Lxy_2(6),
I5 => Lxy_3(6),
O => \Lxy0__1_carry__0_i_5_n_0\
);
\Lxy0__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_2_n_0\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[6]\,
I3 => \Lxy_1_reg_n_0_[5]\,
I4 => Lxy_2(5),
I5 => Lxy_3(5),
O => \Lxy0__1_carry__0_i_6_n_0\
);
\Lxy0__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_3_n_0\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[5]\,
I3 => \Lxy_1_reg_n_0_[4]\,
I4 => Lxy_2(4),
I5 => Lxy_3(4),
O => \Lxy0__1_carry__0_i_7_n_0\
);
\Lxy0__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_4_n_0\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[4]\,
I3 => \Lxy_1_reg_n_0_[3]\,
I4 => Lxy_2(3),
I5 => Lxy_3(3),
O => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(6),
I1 => \Lxy_1_reg_n_0_[6]\,
I2 => Lxy_2(6),
O => \Lxy0__1_carry__0_i_9_n_0\
);
\Lxy0__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__0_n_0\,
CO(3) => \Lxy0__1_carry__1_n_0\,
CO(2) => \Lxy0__1_carry__1_n_1\,
CO(1) => \Lxy0__1_carry__1_n_2\,
CO(0) => \Lxy0__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__1_i_1_n_0\,
DI(2) => \Lxy0__1_carry__1_i_2_n_0\,
DI(1) => \Lxy0__1_carry__1_i_3_n_0\,
DI(0) => \Lxy0__1_carry__1_i_4_n_0\,
O(3) => \Lxy0__1_carry__1_n_4\,
O(2) => \Lxy0__1_carry__1_n_5\,
O(1) => \Lxy0__1_carry__1_n_6\,
O(0) => \Lxy0__1_carry__1_n_7\,
S(3) => \Lxy0__1_carry__1_i_5_n_0\,
S(2) => \Lxy0__1_carry__1_i_6_n_0\,
S(1) => \Lxy0__1_carry__1_i_7_n_0\,
S(0) => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[10]\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => Lxy_3(9),
I3 => Lxy_2(9),
I4 => \Lxy_1_reg_n_0_[9]\,
O => \Lxy0__1_carry__1_i_1_n_0\
);
\Lxy0__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(9),
I1 => \Lxy_1_reg_n_0_[9]\,
I2 => Lxy_2(9),
O => \Lxy0__1_carry__1_i_10_n_0\
);
\Lxy0__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(8),
I1 => \Lxy_1_reg_n_0_[8]\,
I2 => Lxy_2(8),
O => \Lxy0__1_carry__1_i_11_n_0\
);
\Lxy0__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(11),
I1 => \Lxy_1_reg_n_0_[11]\,
I2 => Lxy_2(11),
O => \Lxy0__1_carry__1_i_12_n_0\
);
\Lxy0__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[9]\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => Lxy_3(8),
I3 => Lxy_2(8),
I4 => \Lxy_1_reg_n_0_[8]\,
O => \Lxy0__1_carry__1_i_2_n_0\
);
\Lxy0__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[8]\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => Lxy_3(7),
I3 => Lxy_2(7),
I4 => \Lxy_1_reg_n_0_[7]\,
O => \Lxy0__1_carry__1_i_3_n_0\
);
\Lxy0__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[7]\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => Lxy_3(6),
I3 => Lxy_2(6),
I4 => \Lxy_1_reg_n_0_[6]\,
O => \Lxy0__1_carry__1_i_4_n_0\
);
\Lxy0__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_1_n_0\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[11]\,
I3 => \Lxy_1_reg_n_0_[10]\,
I4 => Lxy_2(10),
I5 => Lxy_3(10),
O => \Lxy0__1_carry__1_i_5_n_0\
);
\Lxy0__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_2_n_0\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[10]\,
I3 => \Lxy_1_reg_n_0_[9]\,
I4 => Lxy_2(9),
I5 => Lxy_3(9),
O => \Lxy0__1_carry__1_i_6_n_0\
);
\Lxy0__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_3_n_0\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[9]\,
I3 => \Lxy_1_reg_n_0_[8]\,
I4 => Lxy_2(8),
I5 => Lxy_3(8),
O => \Lxy0__1_carry__1_i_7_n_0\
);
\Lxy0__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_4_n_0\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[8]\,
I3 => \Lxy_1_reg_n_0_[7]\,
I4 => Lxy_2(7),
I5 => Lxy_3(7),
O => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(10),
I1 => \Lxy_1_reg_n_0_[10]\,
I2 => Lxy_2(10),
O => \Lxy0__1_carry__1_i_9_n_0\
);
\Lxy0__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__1_n_0\,
CO(3) => \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxy0__1_carry__2_n_1\,
CO(1) => \Lxy0__1_carry__2_n_2\,
CO(0) => \Lxy0__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxy0__1_carry__2_i_1_n_0\,
DI(1) => \Lxy0__1_carry__2_i_2_n_0\,
DI(0) => \Lxy0__1_carry__2_i_3_n_0\,
O(3) => \Lxy0__1_carry__2_n_4\,
O(2) => \Lxy0__1_carry__2_n_5\,
O(1) => \Lxy0__1_carry__2_n_6\,
O(0) => \Lxy0__1_carry__2_n_7\,
S(3) => \Lxy0__1_carry__2_i_4_n_0\,
S(2) => \Lxy0__1_carry__2_i_5_n_0\,
S(1) => \Lxy0__1_carry__2_i_6_n_0\,
S(0) => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[13]\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => Lxy_3(12),
I3 => Lxy_2(12),
I4 => \Lxy_1_reg_n_0_[12]\,
O => \Lxy0__1_carry__2_i_1_n_0\
);
\Lxy0__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => \Lxy_1_reg_n_0_[13]\,
I1 => Lxy_2(13),
I2 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_10_n_0\
);
\Lxy0__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(15),
I1 => \Lxy_1_reg_n_0_[15]\,
I2 => Lxy_3(15),
I3 => \Lxy_0_reg_n_0_[15]\,
O => \Lxy0__1_carry__2_i_11_n_0\
);
\Lxy0__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(14),
I1 => \Lxy_1_reg_n_0_[14]\,
I2 => Lxy_2(14),
O => \Lxy0__1_carry__2_i_12_n_0\
);
\Lxy0__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[12]\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => Lxy_3(11),
I3 => Lxy_2(11),
I4 => \Lxy_1_reg_n_0_[11]\,
O => \Lxy0__1_carry__2_i_2_n_0\
);
\Lxy0__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[11]\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => Lxy_3(10),
I3 => Lxy_2(10),
I4 => \Lxy_1_reg_n_0_[10]\,
O => \Lxy0__1_carry__2_i_3_n_0\
);
\Lxy0__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E87781E87E11E87"
)
port map (
I0 => \Lxy0__1_carry__2_i_10_n_0\,
I1 => \Lxy_0_reg_n_0_[14]\,
I2 => \Lxy0__1_carry__2_i_11_n_0\,
I3 => \Lxy_1_reg_n_0_[14]\,
I4 => Lxy_2(14),
I5 => Lxy_3(14),
O => \Lxy0__1_carry__2_i_4_n_0\
);
\Lxy0__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_1_n_0\,
I1 => \Lxy0__1_carry__2_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[14]\,
I3 => \Lxy_1_reg_n_0_[13]\,
I4 => Lxy_2(13),
I5 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_5_n_0\
);
\Lxy0__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_2_n_0\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[13]\,
I3 => \Lxy_1_reg_n_0_[12]\,
I4 => Lxy_2(12),
I5 => Lxy_3(12),
O => \Lxy0__1_carry__2_i_6_n_0\
);
\Lxy0__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_3_n_0\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[12]\,
I3 => \Lxy_1_reg_n_0_[11]\,
I4 => Lxy_2(11),
I5 => Lxy_3(11),
O => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(13),
I1 => \Lxy_1_reg_n_0_[13]\,
I2 => Lxy_2(13),
O => \Lxy0__1_carry__2_i_8_n_0\
);
\Lxy0__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(12),
I1 => \Lxy_1_reg_n_0_[12]\,
I2 => Lxy_2(12),
O => \Lxy0__1_carry__2_i_9_n_0\
);
\Lxy0__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBEEBBE8228EBBE"
)
port map (
I0 => \Lxy_0_reg_n_0_[2]\,
I1 => Lxy_2(2),
I2 => \Lxy_1_reg_n_0_[2]\,
I3 => Lxy_3(2),
I4 => \Lxy_1_reg_n_0_[1]\,
I5 => Lxy_2(1),
O => \Lxy0__1_carry_i_1_n_0\
);
\Lxy0__1_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => Lxy_2(1),
I1 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_10_n_0\
);
\Lxy0__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4DD4"
)
port map (
I0 => Lxy_3(1),
I1 => \Lxy_0_reg_n_0_[1]\,
I2 => \Lxy_1_reg_n_0_[1]\,
I3 => Lxy_2(1),
O => \Lxy0__1_carry_i_2_n_0\
);
\Lxy0__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxy_1_reg_n_0_[1]\,
I1 => Lxy_2(1),
I2 => Lxy_3(1),
I3 => \Lxy_0_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_3_n_0\
);
\Lxy0__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry_i_1_n_0\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[3]\,
I3 => \Lxy_1_reg_n_0_[2]\,
I4 => Lxy_2(2),
I5 => Lxy_3(2),
O => \Lxy0__1_carry_i_4_n_0\
);
\Lxy0__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"69966969"
)
port map (
I0 => \Lxy0__1_carry_i_2_n_0\,
I1 => \Lxy0__1_carry_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[2]\,
I3 => Lxy_2(1),
I4 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_5_n_0\
);
\Lxy0__1_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy_0_reg_n_0_[1]\,
I1 => Lxy_3(1),
I2 => \Lxy0__1_carry_i_10_n_0\,
I3 => Lxy_3(0),
I4 => Lxy_2(0),
I5 => \Lxy_1_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_6_n_0\
);
\Lxy0__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(0),
I1 => \Lxy_1_reg_n_0_[0]\,
I2 => Lxy_3(0),
I3 => \Lxy_0_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(3),
I1 => \Lxy_1_reg_n_0_[3]\,
I2 => Lxy_2(3),
O => \Lxy0__1_carry_i_8_n_0\
);
\Lxy0__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(2),
I1 => \Lxy_1_reg_n_0_[2]\,
I2 => Lxy_2(2),
O => \Lxy0__1_carry_i_9_n_0\
);
\Lxy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => \Lxy_0[15]_i_1_n_0\
);
\Lxy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxy_0_reg_n_0_[0]\,
R => '0'
);
\Lxy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxy_0_reg_n_0_[10]\,
R => '0'
);
\Lxy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxy_0_reg_n_0_[11]\,
R => '0'
);
\Lxy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxy_0_reg_n_0_[12]\,
R => '0'
);
\Lxy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxy_0_reg_n_0_[13]\,
R => '0'
);
\Lxy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxy_0_reg_n_0_[14]\,
R => '0'
);
\Lxy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxy_0_reg_n_0_[15]\,
R => '0'
);
\Lxy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxy_0_reg_n_0_[1]\,
R => '0'
);
\Lxy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxy_0_reg_n_0_[2]\,
R => '0'
);
\Lxy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxy_0_reg_n_0_[3]\,
R => '0'
);
\Lxy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxy_0_reg_n_0_[4]\,
R => '0'
);
\Lxy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxy_0_reg_n_0_[5]\,
R => '0'
);
\Lxy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxy_0_reg_n_0_[6]\,
R => '0'
);
\Lxy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxy_0_reg_n_0_[7]\,
R => '0'
);
\Lxy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxy_0_reg_n_0_[8]\,
R => '0'
);
\Lxy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxy_0_reg_n_0_[9]\,
R => '0'
);
\Lxy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => Lxy_1
);
\Lxy_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(0),
Q => \Lxy_1_reg_n_0_[0]\,
R => '0'
);
\Lxy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(10),
Q => \Lxy_1_reg_n_0_[10]\,
R => '0'
);
\Lxy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(11),
Q => \Lxy_1_reg_n_0_[11]\,
R => '0'
);
\Lxy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(12),
Q => \Lxy_1_reg_n_0_[12]\,
R => '0'
);
\Lxy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(13),
Q => \Lxy_1_reg_n_0_[13]\,
R => '0'
);
\Lxy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(14),
Q => \Lxy_1_reg_n_0_[14]\,
R => '0'
);
\Lxy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(15),
Q => \Lxy_1_reg_n_0_[15]\,
R => '0'
);
\Lxy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(1),
Q => \Lxy_1_reg_n_0_[1]\,
R => '0'
);
\Lxy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(2),
Q => \Lxy_1_reg_n_0_[2]\,
R => '0'
);
\Lxy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(3),
Q => \Lxy_1_reg_n_0_[3]\,
R => '0'
);
\Lxy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(4),
Q => \Lxy_1_reg_n_0_[4]\,
R => '0'
);
\Lxy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(5),
Q => \Lxy_1_reg_n_0_[5]\,
R => '0'
);
\Lxy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(6),
Q => \Lxy_1_reg_n_0_[6]\,
R => '0'
);
\Lxy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(7),
Q => \Lxy_1_reg_n_0_[7]\,
R => '0'
);
\Lxy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(8),
Q => \Lxy_1_reg_n_0_[8]\,
R => '0'
);
\Lxy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(9),
Q => \Lxy_1_reg_n_0_[9]\,
R => '0'
);
\Lxy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(0),
Q => Lxy_2(0),
R => '0'
);
\Lxy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(10),
Q => Lxy_2(10),
R => '0'
);
\Lxy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(11),
Q => Lxy_2(11),
R => '0'
);
\Lxy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(12),
Q => Lxy_2(12),
R => '0'
);
\Lxy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(13),
Q => Lxy_2(13),
R => '0'
);
\Lxy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(14),
Q => Lxy_2(14),
R => '0'
);
\Lxy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(15),
Q => Lxy_2(15),
R => '0'
);
\Lxy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(1),
Q => Lxy_2(1),
R => '0'
);
\Lxy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(2),
Q => Lxy_2(2),
R => '0'
);
\Lxy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(3),
Q => Lxy_2(3),
R => '0'
);
\Lxy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(4),
Q => Lxy_2(4),
R => '0'
);
\Lxy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(5),
Q => Lxy_2(5),
R => '0'
);
\Lxy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(6),
Q => Lxy_2(6),
R => '0'
);
\Lxy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(7),
Q => Lxy_2(7),
R => '0'
);
\Lxy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(8),
Q => Lxy_2(8),
R => '0'
);
\Lxy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(9),
Q => Lxy_2(9),
R => '0'
);
\Lxy_3[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => cycle(3),
O => y6
);
\Lxy_3_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(0),
Q => Lxy_3(0),
R => '0'
);
\Lxy_3_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(10),
Q => Lxy_3(10),
R => '0'
);
\Lxy_3_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(11),
Q => Lxy_3(11),
R => '0'
);
\Lxy_3_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(12),
Q => Lxy_3(12),
R => '0'
);
\Lxy_3_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(13),
Q => Lxy_3(13),
R => '0'
);
\Lxy_3_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(14),
Q => Lxy_3(14),
R => '0'
);
\Lxy_3_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(15),
Q => Lxy_3(15),
R => '0'
);
\Lxy_3_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(1),
Q => Lxy_3(1),
R => '0'
);
\Lxy_3_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(2),
Q => Lxy_3(2),
R => '0'
);
\Lxy_3_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(3),
Q => Lxy_3(3),
R => '0'
);
\Lxy_3_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(4),
Q => Lxy_3(4),
R => '0'
);
\Lxy_3_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(5),
Q => Lxy_3(5),
R => '0'
);
\Lxy_3_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(6),
Q => Lxy_3(6),
R => '0'
);
\Lxy_3_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(7),
Q => Lxy_3(7),
R => '0'
);
\Lxy_3_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(8),
Q => Lxy_3(8),
R => '0'
);
\Lxy_3_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(9),
Q => Lxy_3(9),
R => '0'
);
Lyy0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lyy0_carry_n_0,
CO(2) => Lyy0_carry_n_1,
CO(1) => Lyy0_carry_n_2,
CO(0) => Lyy0_carry_n_3,
CYINIT => '0',
DI(3) => Lyy0_carry_i_1_n_0,
DI(2) => Lyy0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lyy_2_reg_n_0_[0]\,
O(3 downto 0) => B(3 downto 0),
S(3) => Lyy0_carry_i_3_n_0,
S(2) => Lyy0_carry_i_4_n_0,
S(1) => Lyy0_carry_i_5_n_0,
S(0) => Lyy0_carry_i_6_n_0
);
\Lyy0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lyy0_carry_n_0,
CO(3) => \Lyy0_carry__0_n_0\,
CO(2) => \Lyy0_carry__0_n_1\,
CO(1) => \Lyy0_carry__0_n_2\,
CO(0) => \Lyy0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__0_i_1_n_0\,
DI(2) => \Lyy0_carry__0_i_2_n_0\,
DI(1) => \Lyy0_carry__0_i_3_n_0\,
DI(0) => \Lyy0_carry__0_i_4_n_0\,
O(3 downto 0) => B(7 downto 4),
S(3) => \Lyy0_carry__0_i_5_n_0\,
S(2) => \Lyy0_carry__0_i_6_n_0\,
S(1) => \Lyy0_carry__0_i_7_n_0\,
S(0) => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
O => \Lyy0_carry__0_i_1_n_0\
);
\Lyy0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
O => \Lyy0_carry__0_i_2_n_0\
);
\Lyy0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
O => \Lyy0_carry__0_i_3_n_0\
);
\Lyy0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
O => \Lyy0_carry__0_i_4_n_0\
);
\Lyy0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
I3 => \Lyy0_carry__0_i_1_n_0\,
O => \Lyy0_carry__0_i_5_n_0\
);
\Lyy0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
I3 => \Lyy0_carry__0_i_2_n_0\,
O => \Lyy0_carry__0_i_6_n_0\
);
\Lyy0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
I3 => \Lyy0_carry__0_i_3_n_0\,
O => \Lyy0_carry__0_i_7_n_0\
);
\Lyy0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
I3 => \Lyy0_carry__0_i_4_n_0\,
O => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__0_n_0\,
CO(3) => \Lyy0_carry__1_n_0\,
CO(2) => \Lyy0_carry__1_n_1\,
CO(1) => \Lyy0_carry__1_n_2\,
CO(0) => \Lyy0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__1_i_1_n_0\,
DI(2) => \Lyy0_carry__1_i_2_n_0\,
DI(1) => \Lyy0_carry__1_i_3_n_0\,
DI(0) => \Lyy0_carry__1_i_4_n_0\,
O(3 downto 0) => B(11 downto 8),
S(3) => \Lyy0_carry__1_i_5_n_0\,
S(2) => \Lyy0_carry__1_i_6_n_0\,
S(1) => \Lyy0_carry__1_i_7_n_0\,
S(0) => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
O => \Lyy0_carry__1_i_1_n_0\
);
\Lyy0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
O => \Lyy0_carry__1_i_2_n_0\
);
\Lyy0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
O => \Lyy0_carry__1_i_3_n_0\
);
\Lyy0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
O => \Lyy0_carry__1_i_4_n_0\
);
\Lyy0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
I3 => \Lyy0_carry__1_i_1_n_0\,
O => \Lyy0_carry__1_i_5_n_0\
);
\Lyy0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
I3 => \Lyy0_carry__1_i_2_n_0\,
O => \Lyy0_carry__1_i_6_n_0\
);
\Lyy0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
I3 => \Lyy0_carry__1_i_3_n_0\,
O => \Lyy0_carry__1_i_7_n_0\
);
\Lyy0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
I3 => \Lyy0_carry__1_i_4_n_0\,
O => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__1_n_0\,
CO(3) => \NLW_Lyy0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy0_carry__2_n_1\,
CO(1) => \Lyy0_carry__2_n_2\,
CO(0) => \Lyy0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy0_carry__2_i_1_n_0\,
DI(1) => \Lyy0_carry__2_i_2_n_0\,
DI(0) => \Lyy0_carry__2_i_3_n_0\,
O(3 downto 0) => B(15 downto 12),
S(3) => \Lyy0_carry__2_i_4_n_0\,
S(2) => \Lyy0_carry__2_i_5_n_0\,
S(1) => \Lyy0_carry__2_i_6_n_0\,
S(0) => \Lyy0_carry__2_i_7_n_0\
);
\Lyy0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
O => \Lyy0_carry__2_i_1_n_0\
);
\Lyy0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
O => \Lyy0_carry__2_i_2_n_0\
);
\Lyy0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
O => \Lyy0_carry__2_i_3_n_0\
);
\Lyy0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \Lyy_0_reg_n_0_[14]\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_2_reg_n_0_[15]\,
I4 => Lyy_1(15),
I5 => \Lyy_0_reg_n_0_[15]\,
O => \Lyy0_carry__2_i_4_n_0\
);
\Lyy0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lyy0_carry__2_i_1_n_0\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_0_reg_n_0_[14]\,
O => \Lyy0_carry__2_i_5_n_0\
);
\Lyy0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
I3 => \Lyy0_carry__2_i_2_n_0\,
O => \Lyy0_carry__2_i_6_n_0\
);
\Lyy0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
I3 => \Lyy0_carry__2_i_3_n_0\,
O => \Lyy0_carry__2_i_7_n_0\
);
Lyy0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
O => Lyy0_carry_i_1_n_0
);
Lyy0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_2_n_0
);
Lyy0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
I3 => Lyy0_carry_i_1_n_0,
O => Lyy0_carry_i_3_n_0
);
Lyy0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
I3 => Lyy0_carry_i_2_n_0,
O => Lyy0_carry_i_4_n_0
);
Lyy0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_5_n_0
);
Lyy0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lyy_2_reg_n_0_[0]\,
I1 => \Lyy_0_reg_n_0_[0]\,
O => Lyy0_carry_i_6_n_0
);
\Lyy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[0]_rep_n_0\,
O => Lyy_0
);
\Lyy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(0),
Q => \Lyy_0_reg_n_0_[0]\,
R => '0'
);
\Lyy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(10),
Q => \Lyy_0_reg_n_0_[10]\,
R => '0'
);
\Lyy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(11),
Q => \Lyy_0_reg_n_0_[11]\,
R => '0'
);
\Lyy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(12),
Q => \Lyy_0_reg_n_0_[12]\,
R => '0'
);
\Lyy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(13),
Q => \Lyy_0_reg_n_0_[13]\,
R => '0'
);
\Lyy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(14),
Q => \Lyy_0_reg_n_0_[14]\,
R => '0'
);
\Lyy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(15),
Q => \Lyy_0_reg_n_0_[15]\,
R => '0'
);
\Lyy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(1),
Q => \Lyy_0_reg_n_0_[1]\,
R => '0'
);
\Lyy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(2),
Q => \Lyy_0_reg_n_0_[2]\,
R => '0'
);
\Lyy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(3),
Q => \Lyy_0_reg_n_0_[3]\,
R => '0'
);
\Lyy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(4),
Q => \Lyy_0_reg_n_0_[4]\,
R => '0'
);
\Lyy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(5),
Q => \Lyy_0_reg_n_0_[5]\,
R => '0'
);
\Lyy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(6),
Q => \Lyy_0_reg_n_0_[6]\,
R => '0'
);
\Lyy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(7),
Q => \Lyy_0_reg_n_0_[7]\,
R => '0'
);
\Lyy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(8),
Q => \Lyy_0_reg_n_0_[8]\,
R => '0'
);
\Lyy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(9),
Q => \Lyy_0_reg_n_0_[9]\,
R => '0'
);
\Lyy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => rst,
I3 => active,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y1
);
\Lyy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(9),
Q => Lyy_1(10),
R => '0'
);
\Lyy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(10),
Q => Lyy_1(11),
R => '0'
);
\Lyy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(11),
Q => Lyy_1(12),
R => '0'
);
\Lyy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(12),
Q => Lyy_1(13),
R => '0'
);
\Lyy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(13),
Q => Lyy_1(14),
R => '0'
);
\Lyy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(14),
Q => Lyy_1(15),
R => '0'
);
\Lyy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(0),
Q => Lyy_1(1),
R => '0'
);
\Lyy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(1),
Q => Lyy_1(2),
R => '0'
);
\Lyy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(2),
Q => Lyy_1(3),
R => '0'
);
\Lyy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(3),
Q => Lyy_1(4),
R => '0'
);
\Lyy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(4),
Q => Lyy_1(5),
R => '0'
);
\Lyy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(5),
Q => Lyy_1(6),
R => '0'
);
\Lyy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(6),
Q => Lyy_1(7),
R => '0'
);
\Lyy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(7),
Q => Lyy_1(8),
R => '0'
);
\Lyy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(8),
Q => Lyy_1(9),
R => '0'
);
\Lyy_20__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_20__1_carry_n_0\,
CO(2) => \Lyy_20__1_carry_n_1\,
CO(1) => \Lyy_20__1_carry_n_2\,
CO(0) => \Lyy_20__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry_i_1_n_0\,
DI(2) => \Lyy_20__1_carry_i_2_n_0\,
DI(1) => \Lyy_20__1_carry_i_3_n_0\,
DI(0) => Lyy_2_bottom_right(0),
O(3 downto 0) => Lyy_20(3 downto 0),
S(3) => \Lyy_20__1_carry_i_4_n_0\,
S(2) => \Lyy_20__1_carry_i_5_n_0\,
S(1) => \Lyy_20__1_carry_i_6_n_0\,
S(0) => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry_n_0\,
CO(3) => \Lyy_20__1_carry__0_n_0\,
CO(2) => \Lyy_20__1_carry__0_n_1\,
CO(1) => \Lyy_20__1_carry__0_n_2\,
CO(0) => \Lyy_20__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__0_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__0_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__0_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_20(7 downto 4),
S(3) => \Lyy_20__1_carry__0_i_5_n_0\,
S(2) => \Lyy_20__1_carry__0_i_6_n_0\,
S(1) => \Lyy_20__1_carry__0_i_7_n_0\,
S(0) => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(6),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_right(6),
I3 => \Lyy_20__1_carry__0_i_9_n_0\,
I4 => Lyy_2_bottom_right(6),
O => \Lyy_20__1_carry__0_i_1_n_0\
);
\Lyy_20__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(5),
I1 => Lyy_2_bottom_left(5),
I2 => Lyy_2_top_right(5),
O => \Lyy_20__1_carry__0_i_10_n_0\
);
\Lyy_20__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(3),
I1 => Lyy_2_top_left(3),
I2 => Lyy_2_bottom_left(3),
O => \Lyy_20__1_carry__0_i_11_n_0\
);
\Lyy_20__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(7),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_right(7),
O => \Lyy_20__1_carry__0_i_12_n_0\
);
\Lyy_20__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(5),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_left(4),
I3 => Lyy_2_top_right(4),
I4 => \Lyy_20__1_carry__0_i_10_n_0\,
O => \Lyy_20__1_carry__0_i_2_n_0\
);
\Lyy_20__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(4),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_right(4),
I3 => \Lyy_20__1_carry__0_i_11_n_0\,
I4 => Lyy_2_bottom_right(4),
O => \Lyy_20__1_carry__0_i_3_n_0\
);
\Lyy_20__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(3),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_left(2),
I3 => Lyy_2_top_right(2),
I4 => \Lyy_20__1_carry_i_8_n_0\,
O => \Lyy_20__1_carry__0_i_4_n_0\
);
\Lyy_20__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_1_n_0\,
I1 => \Lyy_20__1_carry__0_i_12_n_0\,
I2 => Lyy_2_bottom_right(7),
I3 => Lyy_2_top_right(6),
I4 => Lyy_2_top_left(6),
I5 => Lyy_2_bottom_left(6),
O => \Lyy_20__1_carry__0_i_5_n_0\
);
\Lyy_20__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_2_n_0\,
I1 => Lyy_2_top_right(6),
I2 => Lyy_2_bottom_left(6),
I3 => Lyy_2_top_left(6),
I4 => Lyy_2_bottom_right(6),
I5 => \Lyy_20__1_carry__0_i_9_n_0\,
O => \Lyy_20__1_carry__0_i_6_n_0\
);
\Lyy_20__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_3_n_0\,
I1 => \Lyy_20__1_carry__0_i_10_n_0\,
I2 => Lyy_2_bottom_right(5),
I3 => Lyy_2_top_right(4),
I4 => Lyy_2_top_left(4),
I5 => Lyy_2_bottom_left(4),
O => \Lyy_20__1_carry__0_i_7_n_0\
);
\Lyy_20__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_4_n_0\,
I1 => Lyy_2_top_right(4),
I2 => Lyy_2_bottom_left(4),
I3 => Lyy_2_top_left(4),
I4 => Lyy_2_bottom_right(4),
I5 => \Lyy_20__1_carry__0_i_11_n_0\,
O => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(5),
I1 => Lyy_2_top_left(5),
I2 => Lyy_2_bottom_left(5),
O => \Lyy_20__1_carry__0_i_9_n_0\
);
\Lyy_20__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__0_n_0\,
CO(3) => \Lyy_20__1_carry__1_n_0\,
CO(2) => \Lyy_20__1_carry__1_n_1\,
CO(1) => \Lyy_20__1_carry__1_n_2\,
CO(0) => \Lyy_20__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__1_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__1_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__1_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_20(11 downto 8),
S(3) => \Lyy_20__1_carry__1_i_5_n_0\,
S(2) => \Lyy_20__1_carry__1_i_6_n_0\,
S(1) => \Lyy_20__1_carry__1_i_7_n_0\,
S(0) => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(10),
I1 => Lyy_2_bottom_left(10),
I2 => Lyy_2_top_right(10),
I3 => \Lyy_20__1_carry__1_i_9_n_0\,
I4 => Lyy_2_bottom_right(10),
O => \Lyy_20__1_carry__1_i_1_n_0\
);
\Lyy_20__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(9),
I1 => Lyy_2_bottom_left(9),
I2 => Lyy_2_top_right(9),
O => \Lyy_20__1_carry__1_i_10_n_0\
);
\Lyy_20__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(8),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_right(8),
O => \Lyy_20__1_carry__1_i_11_n_0\
);
\Lyy_20__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(10),
I1 => Lyy_2_top_left(10),
I2 => Lyy_2_bottom_left(10),
O => \Lyy_20__1_carry__1_i_12_n_0\
);
\Lyy_20__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(9),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_left(8),
I3 => Lyy_2_top_right(8),
I4 => \Lyy_20__1_carry__1_i_10_n_0\,
O => \Lyy_20__1_carry__1_i_2_n_0\
);
\Lyy_20__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(8),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_left(7),
I3 => Lyy_2_top_right(7),
I4 => \Lyy_20__1_carry__1_i_11_n_0\,
O => \Lyy_20__1_carry__1_i_3_n_0\
);
\Lyy_20__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(7),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_left(6),
I3 => Lyy_2_top_right(6),
I4 => \Lyy_20__1_carry__0_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_4_n_0\
);
\Lyy_20__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_1_n_0\,
I1 => Lyy_2_top_right(11),
I2 => Lyy_2_bottom_left(11),
I3 => Lyy_2_top_left(11),
I4 => Lyy_2_bottom_right(11),
I5 => \Lyy_20__1_carry__1_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_5_n_0\
);
\Lyy_20__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_2_n_0\,
I1 => Lyy_2_top_right(10),
I2 => Lyy_2_bottom_left(10),
I3 => Lyy_2_top_left(10),
I4 => Lyy_2_bottom_right(10),
I5 => \Lyy_20__1_carry__1_i_9_n_0\,
O => \Lyy_20__1_carry__1_i_6_n_0\
);
\Lyy_20__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_3_n_0\,
I1 => \Lyy_20__1_carry__1_i_10_n_0\,
I2 => Lyy_2_bottom_right(9),
I3 => Lyy_2_top_right(8),
I4 => Lyy_2_top_left(8),
I5 => Lyy_2_bottom_left(8),
O => \Lyy_20__1_carry__1_i_7_n_0\
);
\Lyy_20__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_4_n_0\,
I1 => \Lyy_20__1_carry__1_i_11_n_0\,
I2 => Lyy_2_bottom_right(8),
I3 => Lyy_2_top_right(7),
I4 => Lyy_2_top_left(7),
I5 => Lyy_2_bottom_left(7),
O => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(9),
I1 => Lyy_2_top_left(9),
I2 => Lyy_2_bottom_left(9),
O => \Lyy_20__1_carry__1_i_9_n_0\
);
\Lyy_20__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__1_n_0\,
CO(3) => \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_20__1_carry__2_n_1\,
CO(1) => \Lyy_20__1_carry__2_n_2\,
CO(0) => \Lyy_20__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_20__1_carry__2_i_1_n_0\,
DI(1) => \Lyy_20__1_carry__2_i_2_n_0\,
DI(0) => \Lyy_20__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_20(15 downto 12),
S(3) => \Lyy_20__1_carry__2_i_4_n_0\,
S(2) => \Lyy_20__1_carry__2_i_5_n_0\,
S(1) => \Lyy_20__1_carry__2_i_6_n_0\,
S(0) => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(13),
I1 => Lyy_2_top_right(12),
I2 => Lyy_2_top_left(12),
I3 => Lyy_2_bottom_left(12),
I4 => \Lyy_20__1_carry__2_i_8_n_0\,
O => \Lyy_20__1_carry__2_i_1_n_0\
);
\Lyy_20__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_10_n_0\
);
\Lyy_20__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(15),
I1 => Lyy_2_bottom_left(15),
I2 => Lyy_2_top_left(15),
I3 => Lyy_2_bottom_right(15),
O => \Lyy_20__1_carry__2_i_11_n_0\
);
\Lyy_20__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(12),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_left(11),
I3 => Lyy_2_top_right(11),
I4 => \Lyy_20__1_carry__2_i_9_n_0\,
O => \Lyy_20__1_carry__2_i_2_n_0\
);
\Lyy_20__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(11),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_right(11),
I3 => \Lyy_20__1_carry__1_i_12_n_0\,
I4 => Lyy_2_bottom_right(11),
O => \Lyy_20__1_carry__2_i_3_n_0\
);
\Lyy_20__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E78871E871EE187"
)
port map (
I0 => Lyy_2_bottom_right(14),
I1 => \Lyy_20__1_carry__2_i_10_n_0\,
I2 => \Lyy_20__1_carry__2_i_11_n_0\,
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_left(14),
I5 => Lyy_2_top_right(14),
O => \Lyy_20__1_carry__2_i_4_n_0\
);
\Lyy_20__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__2_i_1_n_0\,
I1 => Lyy_2_top_right(14),
I2 => Lyy_2_bottom_left(14),
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_right(14),
I5 => \Lyy_20__1_carry__2_i_10_n_0\,
O => \Lyy_20__1_carry__2_i_5_n_0\
);
\Lyy_20__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_2_n_0\,
I1 => \Lyy_20__1_carry__2_i_8_n_0\,
I2 => Lyy_2_bottom_right(13),
I3 => Lyy_2_bottom_left(12),
I4 => Lyy_2_top_left(12),
I5 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_6_n_0\
);
\Lyy_20__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_3_n_0\,
I1 => \Lyy_20__1_carry__2_i_9_n_0\,
I2 => Lyy_2_bottom_right(12),
I3 => Lyy_2_top_right(11),
I4 => Lyy_2_top_left(11),
I5 => Lyy_2_bottom_left(11),
O => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_8_n_0\
);
\Lyy_20__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(12),
I1 => Lyy_2_bottom_left(12),
I2 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_9_n_0\
);
\Lyy_20__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FFFFFF00969696"
)
port map (
I0 => Lyy_2_top_left(2),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_right(2),
I3 => Lyy_2_top_right(1),
I4 => Lyy_2_bottom_left(1),
I5 => Lyy_2_bottom_right(2),
O => \Lyy_20__1_carry_i_1_n_0\
);
\Lyy_20__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => Lyy_2_top_right(1),
I1 => Lyy_2_bottom_left(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_2_n_0\
);
\Lyy_20__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_3_n_0\
);
\Lyy_20__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry_i_1_n_0\,
I1 => \Lyy_20__1_carry_i_8_n_0\,
I2 => Lyy_2_bottom_right(3),
I3 => Lyy_2_top_right(2),
I4 => Lyy_2_top_left(2),
I5 => Lyy_2_bottom_left(2),
O => \Lyy_20__1_carry_i_4_n_0\
);
\Lyy_20__1_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry_i_2_n_0\,
I1 => Lyy_2_top_right(2),
I2 => Lyy_2_bottom_left(2),
I3 => Lyy_2_top_left(2),
I4 => Lyy_2_bottom_right(2),
I5 => \Lyy_20__1_carry_i_9_n_0\,
O => \Lyy_20__1_carry_i_5_n_0\
);
\Lyy_20__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A59"
)
port map (
I0 => \Lyy_20__1_carry_i_3_n_0\,
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_top_right(0),
O => \Lyy_20__1_carry_i_6_n_0\
);
\Lyy_20__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(0),
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_bottom_right(0),
O => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(3),
I1 => Lyy_2_bottom_left(3),
I2 => Lyy_2_top_right(3),
O => \Lyy_20__1_carry_i_8_n_0\
);
\Lyy_20__1_carry_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
O => \Lyy_20__1_carry_i_9_n_0\
);
\Lyy_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \Lyy_2[15]_i_1_n_0\
);
\Lyy_2_bottom_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(0),
Q => Lyy_2_bottom_left(0),
R => '0'
);
\Lyy_2_bottom_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(10),
Q => Lyy_2_bottom_left(10),
R => '0'
);
\Lyy_2_bottom_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(11),
Q => Lyy_2_bottom_left(11),
R => '0'
);
\Lyy_2_bottom_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(12),
Q => Lyy_2_bottom_left(12),
R => '0'
);
\Lyy_2_bottom_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(13),
Q => Lyy_2_bottom_left(13),
R => '0'
);
\Lyy_2_bottom_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(14),
Q => Lyy_2_bottom_left(14),
R => '0'
);
\Lyy_2_bottom_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(15),
Q => Lyy_2_bottom_left(15),
R => '0'
);
\Lyy_2_bottom_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(1),
Q => Lyy_2_bottom_left(1),
R => '0'
);
\Lyy_2_bottom_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(2),
Q => Lyy_2_bottom_left(2),
R => '0'
);
\Lyy_2_bottom_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(3),
Q => Lyy_2_bottom_left(3),
R => '0'
);
\Lyy_2_bottom_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(4),
Q => Lyy_2_bottom_left(4),
R => '0'
);
\Lyy_2_bottom_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(5),
Q => Lyy_2_bottom_left(5),
R => '0'
);
\Lyy_2_bottom_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(6),
Q => Lyy_2_bottom_left(6),
R => '0'
);
\Lyy_2_bottom_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(7),
Q => Lyy_2_bottom_left(7),
R => '0'
);
\Lyy_2_bottom_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(8),
Q => Lyy_2_bottom_left(8),
R => '0'
);
\Lyy_2_bottom_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(9),
Q => Lyy_2_bottom_left(9),
R => '0'
);
\Lyy_2_bottom_right0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(3 downto 0),
S(3) => \Lyy_2_bottom_right0__0_carry_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__0_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__0_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(7 downto 4),
S(3) => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(6),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => \corner_reg_n_0_[5]\,
I3 => \top_reg_n_0_[5]\,
I4 => \left_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[5]\,
I1 => \left_reg_n_0_[5]\,
I2 => \top_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[4]\,
I1 => \left_reg_n_0_[4]\,
I2 => \top_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[7]\,
I1 => \left_reg_n_0_[7]\,
I2 => \top_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(5),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => \corner_reg_n_0_[4]\,
I3 => \top_reg_n_0_[4]\,
I4 => \left_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(4),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => \corner_reg_n_0_[3]\,
I3 => \top_reg_n_0_[3]\,
I4 => \left_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(3),
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => \corner_reg_n_0_[2]\,
I3 => \top_reg_n_0_[2]\,
I4 => \left_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => last_value(7),
I3 => \left_reg_n_0_[6]\,
I4 => \top_reg_n_0_[6]\,
I5 => \corner_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => last_value(6),
I3 => \left_reg_n_0_[5]\,
I4 => \top_reg_n_0_[5]\,
I5 => \corner_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => last_value(5),
I3 => \left_reg_n_0_[4]\,
I4 => \top_reg_n_0_[4]\,
I5 => \corner_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => last_value(4),
I3 => \left_reg_n_0_[3]\,
I4 => \top_reg_n_0_[3]\,
I5 => \corner_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[6]\,
I1 => \left_reg_n_0_[6]\,
I2 => \top_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__1_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__1_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(11 downto 8),
S(3) => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \corner_reg_n_0_[10]\,
I3 => \corner_reg_n_0_[9]\,
I4 => \top_reg_n_0_[9]\,
I5 => \left_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \top_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \top_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \top_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \corner_reg_n_0_[9]\,
I3 => \corner_reg_n_0_[8]\,
I4 => \top_reg_n_0_[8]\,
I5 => \left_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \corner_reg_n_0_[8]\,
I3 => \corner_reg_n_0_[7]\,
I4 => \top_reg_n_0_[7]\,
I5 => \left_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(7),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => \corner_reg_n_0_[6]\,
I3 => \top_reg_n_0_[6]\,
I4 => \left_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\,
I2 => \left_reg_n_0_[10]\,
I3 => \top_reg_n_0_[10]\,
I4 => \corner_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\,
I2 => \left_reg_n_0_[9]\,
I3 => \top_reg_n_0_[9]\,
I4 => \corner_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\,
I2 => \left_reg_n_0_[8]\,
I3 => \top_reg_n_0_[8]\,
I4 => \corner_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\,
I2 => \left_reg_n_0_[7]\,
I3 => \top_reg_n_0_[7]\,
I4 => \corner_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \top_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(3) => \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_2_bottom_right0__0_carry__2_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__2_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(15 downto 12),
S(3) => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
I3 => \corner_reg_n_0_[12]\,
I4 => \top_reg_n_0_[12]\,
I5 => \left_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \left_reg_n_0_[14]\,
I2 => \top_reg_n_0_[14]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \top_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \top_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \corner_reg_n_0_[12]\,
I3 => \corner_reg_n_0_[11]\,
I4 => \top_reg_n_0_[11]\,
I5 => \left_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \corner_reg_n_0_[11]\,
I3 => \corner_reg_n_0_[10]\,
I4 => \top_reg_n_0_[10]\,
I5 => \left_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D2882"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\,
I1 => \corner_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[14]\,
I4 => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\,
O => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\,
I2 => \left_reg_n_0_[13]\,
I3 => \top_reg_n_0_[13]\,
I4 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\,
I2 => \left_reg_n_0_[12]\,
I3 => \top_reg_n_0_[12]\,
I4 => \corner_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\,
I2 => \left_reg_n_0_[11]\,
I3 => \top_reg_n_0_[11]\,
I4 => \corner_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \left_reg_n_0_[13]\,
I1 => \top_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"D42B2BD42BD4D42B"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \top_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[15]\,
I4 => \left_reg_n_0_[15]\,
I5 => \corner_reg_n_0_[15]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(2),
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => \corner_reg_n_0_[1]\,
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[3]\,
I1 => \left_reg_n_0_[3]\,
I2 => \top_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \top_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"20BABA20BA2020BA"
)
port map (
I0 => last_value(1),
I1 => \corner_reg_n_0_[0]\,
I2 => last_value(0),
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669966969969669"
)
port map (
I0 => \top_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \corner_reg_n_0_[1]\,
I3 => last_value(1),
I4 => last_value(0),
I5 => \corner_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => last_value(3),
I3 => \left_reg_n_0_[2]\,
I4 => \top_reg_n_0_[2]\,
I5 => \corner_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => last_value(2),
I3 => \left_reg_n_0_[1]\,
I4 => \top_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB44B4BB4"
)
port map (
I0 => \corner_reg_n_0_[0]\,
I1 => last_value(0),
I2 => last_value(1),
I3 => \Lyy_2_bottom_right0__0_carry_i_11_n_0\,
I4 => \left_reg_n_0_[0]\,
I5 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
I2 => \corner_reg_n_0_[0]\,
I3 => last_value(0),
O => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[2]\,
I1 => \left_reg_n_0_[2]\,
I2 => \top_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_9_n_0\
);
\Lyy_2_bottom_right[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => y5
);
\Lyy_2_bottom_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(0),
Q => Lyy_2_bottom_right(0),
R => '0'
);
\Lyy_2_bottom_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(10),
Q => Lyy_2_bottom_right(10),
R => '0'
);
\Lyy_2_bottom_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(11),
Q => Lyy_2_bottom_right(11),
R => '0'
);
\Lyy_2_bottom_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(12),
Q => Lyy_2_bottom_right(12),
R => '0'
);
\Lyy_2_bottom_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(13),
Q => Lyy_2_bottom_right(13),
R => '0'
);
\Lyy_2_bottom_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(14),
Q => Lyy_2_bottom_right(14),
R => '0'
);
\Lyy_2_bottom_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(15),
Q => Lyy_2_bottom_right(15),
R => '0'
);
\Lyy_2_bottom_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(1),
Q => Lyy_2_bottom_right(1),
R => '0'
);
\Lyy_2_bottom_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(2),
Q => Lyy_2_bottom_right(2),
R => '0'
);
\Lyy_2_bottom_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(3),
Q => Lyy_2_bottom_right(3),
R => '0'
);
\Lyy_2_bottom_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(4),
Q => Lyy_2_bottom_right(4),
R => '0'
);
\Lyy_2_bottom_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(5),
Q => Lyy_2_bottom_right(5),
R => '0'
);
\Lyy_2_bottom_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(6),
Q => Lyy_2_bottom_right(6),
R => '0'
);
\Lyy_2_bottom_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(7),
Q => Lyy_2_bottom_right(7),
R => '0'
);
\Lyy_2_bottom_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(8),
Q => Lyy_2_bottom_right(8),
R => '0'
);
\Lyy_2_bottom_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(9),
Q => Lyy_2_bottom_right(9),
R => '0'
);
\Lyy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(0),
Q => \Lyy_2_reg_n_0_[0]\,
R => '0'
);
\Lyy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(10),
Q => \Lyy_2_reg_n_0_[10]\,
R => '0'
);
\Lyy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(11),
Q => \Lyy_2_reg_n_0_[11]\,
R => '0'
);
\Lyy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(12),
Q => \Lyy_2_reg_n_0_[12]\,
R => '0'
);
\Lyy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(13),
Q => \Lyy_2_reg_n_0_[13]\,
R => '0'
);
\Lyy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(14),
Q => \Lyy_2_reg_n_0_[14]\,
R => '0'
);
\Lyy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(15),
Q => \Lyy_2_reg_n_0_[15]\,
R => '0'
);
\Lyy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(1),
Q => \Lyy_2_reg_n_0_[1]\,
R => '0'
);
\Lyy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(2),
Q => \Lyy_2_reg_n_0_[2]\,
R => '0'
);
\Lyy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(3),
Q => \Lyy_2_reg_n_0_[3]\,
R => '0'
);
\Lyy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(4),
Q => \Lyy_2_reg_n_0_[4]\,
R => '0'
);
\Lyy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(5),
Q => \Lyy_2_reg_n_0_[5]\,
R => '0'
);
\Lyy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(6),
Q => \Lyy_2_reg_n_0_[6]\,
R => '0'
);
\Lyy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(7),
Q => \Lyy_2_reg_n_0_[7]\,
R => '0'
);
\Lyy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(8),
Q => \Lyy_2_reg_n_0_[8]\,
R => '0'
);
\Lyy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(9),
Q => \Lyy_2_reg_n_0_[9]\,
R => '0'
);
\Lyy_2_top_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(0),
Q => Lyy_2_top_left(0),
R => '0'
);
\Lyy_2_top_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(10),
Q => Lyy_2_top_left(10),
R => '0'
);
\Lyy_2_top_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(11),
Q => Lyy_2_top_left(11),
R => '0'
);
\Lyy_2_top_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(12),
Q => Lyy_2_top_left(12),
R => '0'
);
\Lyy_2_top_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(13),
Q => Lyy_2_top_left(13),
R => '0'
);
\Lyy_2_top_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(14),
Q => Lyy_2_top_left(14),
R => '0'
);
\Lyy_2_top_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(15),
Q => Lyy_2_top_left(15),
R => '0'
);
\Lyy_2_top_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(1),
Q => Lyy_2_top_left(1),
R => '0'
);
\Lyy_2_top_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(2),
Q => Lyy_2_top_left(2),
R => '0'
);
\Lyy_2_top_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(3),
Q => Lyy_2_top_left(3),
R => '0'
);
\Lyy_2_top_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(4),
Q => Lyy_2_top_left(4),
R => '0'
);
\Lyy_2_top_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(5),
Q => Lyy_2_top_left(5),
R => '0'
);
\Lyy_2_top_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(6),
Q => Lyy_2_top_left(6),
R => '0'
);
\Lyy_2_top_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(7),
Q => Lyy_2_top_left(7),
R => '0'
);
\Lyy_2_top_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(8),
Q => Lyy_2_top_left(8),
R => '0'
);
\Lyy_2_top_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(9),
Q => Lyy_2_top_left(9),
R => '0'
);
\Lyy_2_top_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[0]\,
Q => Lyy_2_top_right(0),
R => '0'
);
\Lyy_2_top_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[10]\,
Q => Lyy_2_top_right(10),
R => '0'
);
\Lyy_2_top_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[11]\,
Q => Lyy_2_top_right(11),
R => '0'
);
\Lyy_2_top_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[12]\,
Q => Lyy_2_top_right(12),
R => '0'
);
\Lyy_2_top_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[13]\,
Q => Lyy_2_top_right(13),
R => '0'
);
\Lyy_2_top_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[14]\,
Q => Lyy_2_top_right(14),
R => '0'
);
\Lyy_2_top_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[15]\,
Q => Lyy_2_top_right(15),
R => '0'
);
\Lyy_2_top_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[1]\,
Q => Lyy_2_top_right(1),
R => '0'
);
\Lyy_2_top_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[2]\,
Q => Lyy_2_top_right(2),
R => '0'
);
\Lyy_2_top_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[3]\,
Q => Lyy_2_top_right(3),
R => '0'
);
\Lyy_2_top_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[4]\,
Q => Lyy_2_top_right(4),
R => '0'
);
\Lyy_2_top_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[5]\,
Q => Lyy_2_top_right(5),
R => '0'
);
\Lyy_2_top_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[6]\,
Q => Lyy_2_top_right(6),
R => '0'
);
\Lyy_2_top_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[7]\,
Q => Lyy_2_top_right(7),
R => '0'
);
\Lyy_2_top_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[8]\,
Q => Lyy_2_top_right(8),
R => '0'
);
\Lyy_2_top_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[9]\,
Q => Lyy_2_top_right(9),
R => '0'
);
\addr_0[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[0]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[0]\,
O => \addr_0[0]_i_1_n_0\
);
\addr_0[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[10]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[10]\,
O => \addr_0[10]_i_1_n_0\
);
\addr_0[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[11]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[11]\,
O => \addr_0[11]_i_1_n_0\
);
\addr_0[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[12]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[12]\,
O => \addr_0[12]_i_1_n_0\
);
\addr_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => addr_0
);
\addr_0[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[13]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[13]\,
O => \addr_0[13]_i_2_n_0\
);
\addr_0[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[1]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[1]\,
O => \addr_0[1]_i_1_n_0\
);
\addr_0[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[2]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[2]\,
O => \addr_0[2]_i_1_n_0\
);
\addr_0[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[3]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[3]\,
O => \addr_0[3]_i_1_n_0\
);
\addr_0[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[4]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[4]\,
O => \addr_0[4]_i_1_n_0\
);
\addr_0[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[5]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[5]\,
O => \addr_0[5]_i_1_n_0\
);
\addr_0[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[6]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[6]\,
O => \addr_0[6]_i_1_n_0\
);
\addr_0[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[7]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[7]\,
O => \addr_0[7]_i_1_n_0\
);
\addr_0[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[8]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[8]\,
O => \addr_0[8]_i_1_n_0\
);
\addr_0[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[9]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[9]\,
O => \addr_0[9]_i_1_n_0\
);
\addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[0]_i_1_n_0\,
Q => \addr_0_reg_n_0_[0]\,
R => '0'
);
\addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[10]_i_1_n_0\,
Q => \addr_0_reg_n_0_[10]\,
R => '0'
);
\addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[11]_i_1_n_0\,
Q => \addr_0_reg_n_0_[11]\,
R => '0'
);
\addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[12]_i_1_n_0\,
Q => \addr_0_reg_n_0_[12]\,
R => '0'
);
\addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[13]_i_2_n_0\,
Q => \addr_0_reg_n_0_[13]\,
R => '0'
);
\addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[1]_i_1_n_0\,
Q => \addr_0_reg_n_0_[1]\,
R => '0'
);
\addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[2]_i_1_n_0\,
Q => \addr_0_reg_n_0_[2]\,
R => '0'
);
\addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[3]_i_1_n_0\,
Q => \addr_0_reg_n_0_[3]\,
R => '0'
);
\addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[4]_i_1_n_0\,
Q => \addr_0_reg_n_0_[4]\,
R => '0'
);
\addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[5]_i_1_n_0\,
Q => \addr_0_reg_n_0_[5]\,
R => '0'
);
\addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[6]_i_1_n_0\,
Q => \addr_0_reg_n_0_[6]\,
R => '0'
);
\addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[7]_i_1_n_0\,
Q => \addr_0_reg_n_0_[7]\,
R => '0'
);
\addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[8]_i_1_n_0\,
Q => \addr_0_reg_n_0_[8]\,
R => '0'
);
\addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[9]_i_1_n_0\,
Q => \addr_0_reg_n_0_[9]\,
R => '0'
);
\addr_1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(0),
O => \addr_1[0]_i_1_n_0\
);
\addr_1[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(10),
O => \addr_1[10]_i_1_n_0\
);
\addr_1[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(11),
O => \addr_1[11]_i_1_n_0\
);
\addr_1[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(12),
O => \addr_1[12]_i_1_n_0\
);
\addr_1[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(13),
O => \addr_1[13]_i_1_n_0\
);
\addr_1[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(1),
O => \addr_1[1]_i_1_n_0\
);
\addr_1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(2),
O => \addr_1[2]_i_1_n_0\
);
\addr_1[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(3),
O => \addr_1[3]_i_1_n_0\
);
\addr_1[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(4),
O => \addr_1[4]_i_1_n_0\
);
\addr_1[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(5),
O => \addr_1[5]_i_1_n_0\
);
\addr_1[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(6),
O => \addr_1[6]_i_1_n_0\
);
\addr_1[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(7),
O => \addr_1[7]_i_1_n_0\
);
\addr_1[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(8),
O => \addr_1[8]_i_1_n_0\
);
\addr_1[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(9),
O => \addr_1[9]_i_1_n_0\
);
\addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[0]_i_1_n_0\,
Q => addr_1(0),
R => '0'
);
\addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[10]_i_1_n_0\,
Q => addr_1(10),
R => '0'
);
\addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[11]_i_1_n_0\,
Q => addr_1(11),
R => '0'
);
\addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[12]_i_1_n_0\,
Q => addr_1(12),
R => '0'
);
\addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[13]_i_1_n_0\,
Q => addr_1(13),
R => '0'
);
\addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[1]_i_1_n_0\,
Q => addr_1(1),
R => '0'
);
\addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[2]_i_1_n_0\,
Q => addr_1(2),
R => '0'
);
\addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[3]_i_1_n_0\,
Q => addr_1(3),
R => '0'
);
\addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[4]_i_1_n_0\,
Q => addr_1(4),
R => '0'
);
\addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[5]_i_1_n_0\,
Q => addr_1(5),
R => '0'
);
\addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[6]_i_1_n_0\,
Q => addr_1(6),
R => '0'
);
\addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[7]_i_1_n_0\,
Q => addr_1(7),
R => '0'
);
\addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[8]_i_1_n_0\,
Q => addr_1(8),
R => '0'
);
\addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[9]_i_1_n_0\,
Q => addr_1(9),
R => '0'
);
\bottom_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8800880000000800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[1]_rep_n_0\,
O => bottom_left_0
);
\bottom_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(0),
Q => \bottom_left_0_reg_n_0_[0]\,
R => '0'
);
\bottom_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(10),
Q => \bottom_left_0_reg_n_0_[10]\,
R => '0'
);
\bottom_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(11),
Q => \bottom_left_0_reg_n_0_[11]\,
R => '0'
);
\bottom_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(12),
Q => \bottom_left_0_reg_n_0_[12]\,
R => '0'
);
\bottom_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(13),
Q => \bottom_left_0_reg_n_0_[13]\,
R => '0'
);
\bottom_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(14),
Q => \bottom_left_0_reg_n_0_[14]\,
R => '0'
);
\bottom_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(15),
Q => \bottom_left_0_reg_n_0_[15]\,
R => '0'
);
\bottom_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(1),
Q => \bottom_left_0_reg_n_0_[1]\,
R => '0'
);
\bottom_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(2),
Q => \bottom_left_0_reg_n_0_[2]\,
R => '0'
);
\bottom_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(3),
Q => \bottom_left_0_reg_n_0_[3]\,
R => '0'
);
\bottom_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(4),
Q => \bottom_left_0_reg_n_0_[4]\,
R => '0'
);
\bottom_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(5),
Q => \bottom_left_0_reg_n_0_[5]\,
R => '0'
);
\bottom_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(6),
Q => \bottom_left_0_reg_n_0_[6]\,
R => '0'
);
\bottom_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(7),
Q => \bottom_left_0_reg_n_0_[7]\,
R => '0'
);
\bottom_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(8),
Q => \bottom_left_0_reg_n_0_[8]\,
R => '0'
);
\bottom_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(9),
Q => \bottom_left_0_reg_n_0_[9]\,
R => '0'
);
\bottom_left_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000040"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
O => top_right_1
);
\bottom_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(0),
Q => bottom_left_1(0),
R => '0'
);
\bottom_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(10),
Q => bottom_left_1(10),
R => '0'
);
\bottom_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(11),
Q => bottom_left_1(11),
R => '0'
);
\bottom_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(12),
Q => bottom_left_1(12),
R => '0'
);
\bottom_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(13),
Q => bottom_left_1(13),
R => '0'
);
\bottom_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(14),
Q => bottom_left_1(14),
R => '0'
);
\bottom_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(15),
Q => bottom_left_1(15),
R => '0'
);
\bottom_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(1),
Q => bottom_left_1(1),
R => '0'
);
\bottom_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(2),
Q => bottom_left_1(2),
R => '0'
);
\bottom_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(3),
Q => bottom_left_1(3),
R => '0'
);
\bottom_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(4),
Q => bottom_left_1(4),
R => '0'
);
\bottom_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(5),
Q => bottom_left_1(5),
R => '0'
);
\bottom_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(6),
Q => bottom_left_1(6),
R => '0'
);
\bottom_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(7),
Q => bottom_left_1(7),
R => '0'
);
\bottom_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(8),
Q => bottom_left_1(8),
R => '0'
);
\bottom_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(9),
Q => bottom_left_1(9),
R => '0'
);
\bottom_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[0]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(0),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(0),
O => p_0_out(0)
);
\bottom_right_0[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(0),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[0]_i_2_n_0\
);
\bottom_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[10]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(10),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(10),
O => p_0_out(10)
);
\bottom_right_0[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(10),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(10),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[10]_i_2_n_0\
);
\bottom_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[11]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(11),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(11),
O => p_0_out(11)
);
\bottom_right_0[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(11),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(11),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[11]_i_2_n_0\
);
\bottom_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[12]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(12),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(12),
O => p_0_out(12)
);
\bottom_right_0[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(12),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(12),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[12]_i_2_n_0\
);
\bottom_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[13]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(13),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(13),
O => p_0_out(13)
);
\bottom_right_0[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(13),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(13),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[13]_i_2_n_0\
);
\bottom_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[14]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(14),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(14),
O => p_0_out(14)
);
\bottom_right_0[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(14),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(14),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[14]_i_2_n_0\
);
\bottom_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"444A000000000000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \bottom_right_0[15]_i_1_n_0\
);
\bottom_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[15]_i_4_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(15),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(15),
O => p_0_out(15)
);
\bottom_right_0[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(2),
O => \bottom_right_0[15]_i_3_n_0\
);
\bottom_right_0[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(15),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(15),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[15]_i_4_n_0\
);
\bottom_right_0[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(0),
O => \bottom_right_0[15]_i_5_n_0\
);
\bottom_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[1]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(1),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(1),
O => p_0_out(1)
);
\bottom_right_0[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(1),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[1]_i_2_n_0\
);
\bottom_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[2]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(2),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(2),
O => p_0_out(2)
);
\bottom_right_0[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(2),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[2]_i_2_n_0\
);
\bottom_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[3]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(3),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(3),
O => p_0_out(3)
);
\bottom_right_0[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(3),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[3]_i_2_n_0\
);
\bottom_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[4]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(4),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(4),
O => p_0_out(4)
);
\bottom_right_0[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(4),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[4]_i_2_n_0\
);
\bottom_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[5]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(5),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(5),
O => p_0_out(5)
);
\bottom_right_0[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(5),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[5]_i_2_n_0\
);
\bottom_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[6]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(6),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(6),
O => p_0_out(6)
);
\bottom_right_0[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(6),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[6]_i_2_n_0\
);
\bottom_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[7]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(7),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(7),
O => p_0_out(7)
);
\bottom_right_0[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(7),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[7]_i_2_n_0\
);
\bottom_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[8]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(8),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(8),
O => p_0_out(8)
);
\bottom_right_0[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(8),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[8]_i_2_n_0\
);
\bottom_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[9]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(9),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(9),
O => p_0_out(9)
);
\bottom_right_0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(9),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[9]_i_2_n_0\
);
\bottom_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(0),
Q => \bottom_right_0_reg_n_0_[0]\,
R => '0'
);
\bottom_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(10),
Q => \bottom_right_0_reg_n_0_[10]\,
R => '0'
);
\bottom_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(11),
Q => \bottom_right_0_reg_n_0_[11]\,
R => '0'
);
\bottom_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(12),
Q => \bottom_right_0_reg_n_0_[12]\,
R => '0'
);
\bottom_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(13),
Q => \bottom_right_0_reg_n_0_[13]\,
R => '0'
);
\bottom_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(14),
Q => \bottom_right_0_reg_n_0_[14]\,
R => '0'
);
\bottom_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(15),
Q => \bottom_right_0_reg_n_0_[15]\,
R => '0'
);
\bottom_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(1),
Q => \bottom_right_0_reg_n_0_[1]\,
R => '0'
);
\bottom_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(2),
Q => \bottom_right_0_reg_n_0_[2]\,
R => '0'
);
\bottom_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(3),
Q => \bottom_right_0_reg_n_0_[3]\,
R => '0'
);
\bottom_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(4),
Q => \bottom_right_0_reg_n_0_[4]\,
R => '0'
);
\bottom_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(5),
Q => \bottom_right_0_reg_n_0_[5]\,
R => '0'
);
\bottom_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(6),
Q => \bottom_right_0_reg_n_0_[6]\,
R => '0'
);
\bottom_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(7),
Q => \bottom_right_0_reg_n_0_[7]\,
R => '0'
);
\bottom_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(8),
Q => \bottom_right_0_reg_n_0_[8]\,
R => '0'
);
\bottom_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(9),
Q => \bottom_right_0_reg_n_0_[9]\,
R => '0'
);
\bottom_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[0]\,
O => \bottom_right_1[0]_i_1_n_0\
);
\bottom_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(10),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \bottom_right_1[10]_i_1_n_0\
);
\bottom_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(11),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \bottom_right_1[11]_i_1_n_0\
);
\bottom_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(12),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \bottom_right_1[12]_i_1_n_0\
);
\bottom_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(13),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[13]\,
O => \bottom_right_1[13]_i_1_n_0\
);
\bottom_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(14),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[14]\,
O => \bottom_right_1[14]_i_1_n_0\
);
\bottom_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(15),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[15]\,
O => \bottom_right_1[15]_i_1_n_0\
);
\bottom_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(1),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[1]\,
O => \bottom_right_1[1]_i_1_n_0\
);
\bottom_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(2),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \bottom_right_1[2]_i_1_n_0\
);
\bottom_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(3),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \bottom_right_1[3]_i_1_n_0\
);
\bottom_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(4),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \bottom_right_1[4]_i_1_n_0\
);
\bottom_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(5),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \bottom_right_1[5]_i_1_n_0\
);
\bottom_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(6),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \bottom_right_1[6]_i_1_n_0\
);
\bottom_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(7),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \bottom_right_1[7]_i_1_n_0\
);
\bottom_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \bottom_right_1[8]_i_1_n_0\
);
\bottom_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(9),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \bottom_right_1[9]_i_1_n_0\
);
\bottom_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[0]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[0]\,
R => '0'
);
\bottom_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[10]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[10]\,
R => '0'
);
\bottom_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[11]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[11]\,
R => '0'
);
\bottom_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[12]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[12]\,
R => '0'
);
\bottom_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[13]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[13]\,
R => '0'
);
\bottom_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[14]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[14]\,
R => '0'
);
\bottom_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[15]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[15]\,
R => '0'
);
\bottom_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[1]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[1]\,
R => '0'
);
\bottom_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[2]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[2]\,
R => '0'
);
\bottom_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[3]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[3]\,
R => '0'
);
\bottom_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[4]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[4]\,
R => '0'
);
\bottom_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[5]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[5]\,
R => '0'
);
\bottom_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[6]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[6]\,
R => '0'
);
\bottom_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[7]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[7]\,
R => '0'
);
\bottom_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[8]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[8]\,
R => '0'
);
\bottom_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[9]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[9]\,
R => '0'
);
bram_0: entity work.system_vga_hessian_1_0_blk_mem_gen_0
port map (
addra(13) => \addr_0_reg_n_0_[13]\,
addra(12) => \addr_0_reg_n_0_[12]\,
addra(11) => \addr_0_reg_n_0_[11]\,
addra(10) => \addr_0_reg_n_0_[10]\,
addra(9) => \addr_0_reg_n_0_[9]\,
addra(8) => \addr_0_reg_n_0_[8]\,
addra(7) => \addr_0_reg_n_0_[7]\,
addra(6) => \addr_0_reg_n_0_[6]\,
addra(5) => \addr_0_reg_n_0_[5]\,
addra(4) => \addr_0_reg_n_0_[4]\,
addra(3) => \addr_0_reg_n_0_[3]\,
addra(2) => \addr_0_reg_n_0_[2]\,
addra(1) => \addr_0_reg_n_0_[1]\,
addra(0) => \addr_0_reg_n_0_[0]\,
addrb(13 downto 0) => addr_1(13 downto 0),
clka => clk_x16,
clkb => clk_x16,
dina(15) => \din_reg_n_0_[15]\,
dina(14) => \din_reg_n_0_[14]\,
dina(13) => \din_reg_n_0_[13]\,
dina(12) => \din_reg_n_0_[12]\,
dina(11) => \din_reg_n_0_[11]\,
dina(10) => \din_reg_n_0_[10]\,
dina(9) => \din_reg_n_0_[9]\,
dina(8) => \din_reg_n_0_[8]\,
dina(7) => \din_reg_n_0_[7]\,
dina(6) => \din_reg_n_0_[6]\,
dina(5) => \din_reg_n_0_[5]\,
dina(4) => \din_reg_n_0_[4]\,
dina(3) => \din_reg_n_0_[3]\,
dina(2) => \din_reg_n_0_[2]\,
dina(1) => \din_reg_n_0_[1]\,
dina(0) => \din_reg_n_0_[0]\,
dinb(15 downto 0) => B"0000000000000000",
douta(15 downto 0) => dout_0(15 downto 0),
doutb(15 downto 0) => dout_1(15 downto 0),
ena => '1',
enb => '1',
wea(0) => wen_reg_n_0,
web(0) => '0'
);
\cache[9][15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => \cache[9][15]_i_1_n_0\
);
\cache[9][15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => active,
I1 => cycle(2),
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => \cycle_reg[0]_rep_n_0\,
O => \cache[10]_5\
);
\cache_reg[0][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(0),
Q => \cache_reg[0]_4\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(10),
Q => \cache_reg[0]_4\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(11),
Q => \cache_reg[0]_4\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(12),
Q => \cache_reg[0]_4\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(13),
Q => \cache_reg[0]_4\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(14),
Q => \cache_reg[0]_4\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(15),
Q => \cache_reg[0]_4\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(1),
Q => \cache_reg[0]_4\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(2),
Q => \cache_reg[0]_4\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(3),
Q => \cache_reg[0]_4\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(4),
Q => \cache_reg[0]_4\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(5),
Q => \cache_reg[0]_4\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(6),
Q => \cache_reg[0]_4\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(7),
Q => \cache_reg[0]_4\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(8),
Q => \cache_reg[0]_4\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(9),
Q => \cache_reg[0]_4\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(0),
Q => \cache_reg[10]_3\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(10),
Q => \cache_reg[10]_3\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(11),
Q => \cache_reg[10]_3\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(12),
Q => \cache_reg[10]_3\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(13),
Q => \cache_reg[10]_3\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(14),
Q => \cache_reg[10]_3\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(15),
Q => \cache_reg[10]_3\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(1),
Q => \cache_reg[10]_3\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(2),
Q => \cache_reg[10]_3\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(3),
Q => \cache_reg[10]_3\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(4),
Q => \cache_reg[10]_3\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(5),
Q => \cache_reg[10]_3\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(6),
Q => \cache_reg[10]_3\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(7),
Q => \cache_reg[10]_3\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(8),
Q => \cache_reg[10]_3\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(9),
Q => \cache_reg[10]_3\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[2][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(0),
Q => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(10),
Q => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(11),
Q => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(12),
Q => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(13),
Q => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(14),
Q => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(15),
Q => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(1),
Q => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(2),
Q => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(3),
Q => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(4),
Q => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(5),
Q => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(6),
Q => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(7),
Q => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(8),
Q => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(9),
Q => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[3][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[4][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__14_n_0\,
Q => \cache_reg[4]_0\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__4_n_0\,
Q => \cache_reg[4]_0\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__3_n_0\,
Q => \cache_reg[4]_0\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__2_n_0\,
Q => \cache_reg[4]_0\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__1_n_0\,
Q => \cache_reg[4]_0\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__0_n_0\,
Q => \cache_reg[4]_0\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_gate_n_0,
Q => \cache_reg[4]_0\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__13_n_0\,
Q => \cache_reg[4]_0\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__12_n_0\,
Q => \cache_reg[4]_0\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__11_n_0\,
Q => \cache_reg[4]_0\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__10_n_0\,
Q => \cache_reg[4]_0\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__9_n_0\,
Q => \cache_reg[4]_0\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__8_n_0\,
Q => \cache_reg[4]_0\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__7_n_0\,
Q => \cache_reg[4]_0\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__6_n_0\,
Q => \cache_reg[4]_0\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__5_n_0\,
Q => \cache_reg[4]_0\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[6][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(0),
Q => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(10),
Q => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(11),
Q => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(12),
Q => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(13),
Q => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(14),
Q => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(15),
Q => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(1),
Q => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(2),
Q => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(3),
Q => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(4),
Q => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(5),
Q => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(6),
Q => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(7),
Q => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(8),
Q => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(9),
Q => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[7][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__30_n_0\,
Q => \cache_reg[8]_1\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__20_n_0\,
Q => \cache_reg[8]_1\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__19_n_0\,
Q => \cache_reg[8]_1\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__18_n_0\,
Q => \cache_reg[8]_1\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__17_n_0\,
Q => \cache_reg[8]_1\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__16_n_0\,
Q => \cache_reg[8]_1\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__15_n_0\,
Q => \cache_reg[8]_1\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__29_n_0\,
Q => \cache_reg[8]_1\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__28_n_0\,
Q => \cache_reg[8]_1\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__27_n_0\,
Q => \cache_reg[8]_1\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__26_n_0\,
Q => \cache_reg[8]_1\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__25_n_0\,
Q => \cache_reg[8]_1\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__24_n_0\,
Q => \cache_reg[8]_1\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__23_n_0\,
Q => \cache_reg[8]_1\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__22_n_0\,
Q => \cache_reg[8]_1\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__21_n_0\,
Q => \cache_reg[8]_1\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(0),
Q => \cache_reg[9]_2\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(10),
Q => \cache_reg[9]_2\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(11),
Q => \cache_reg[9]_2\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(12),
Q => \cache_reg[9]_2\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(13),
Q => \cache_reg[9]_2\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(14),
Q => \cache_reg[9]_2\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(15),
Q => \cache_reg[9]_2\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(1),
Q => \cache_reg[9]_2\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(2),
Q => \cache_reg[9]_2\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(3),
Q => \cache_reg[9]_2\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(4),
Q => \cache_reg[9]_2\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(5),
Q => \cache_reg[9]_2\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(6),
Q => \cache_reg[9]_2\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(7),
Q => \cache_reg[9]_2\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(8),
Q => \cache_reg[9]_2\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(9),
Q => \cache_reg[9]_2\(9),
R => \cache[9][15]_i_1_n_0\
);
cache_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => cache_reg_gate_n_0
);
\cache_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__0_n_0\
);
\cache_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__1_n_0\
);
\cache_reg_gate__10\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__10_n_0\
);
\cache_reg_gate__11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__11_n_0\
);
\cache_reg_gate__12\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__12_n_0\
);
\cache_reg_gate__13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__13_n_0\
);
\cache_reg_gate__14\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__14_n_0\
);
\cache_reg_gate__15\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__15_n_0\
);
\cache_reg_gate__16\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__16_n_0\
);
\cache_reg_gate__17\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__17_n_0\
);
\cache_reg_gate__18\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__18_n_0\
);
\cache_reg_gate__19\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__19_n_0\
);
\cache_reg_gate__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__2_n_0\
);
\cache_reg_gate__20\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__20_n_0\
);
\cache_reg_gate__21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__21_n_0\
);
\cache_reg_gate__22\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__22_n_0\
);
\cache_reg_gate__23\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__23_n_0\
);
\cache_reg_gate__24\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__24_n_0\
);
\cache_reg_gate__25\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__25_n_0\
);
\cache_reg_gate__26\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__26_n_0\
);
\cache_reg_gate__27\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__27_n_0\
);
\cache_reg_gate__28\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__28_n_0\
);
\cache_reg_gate__29\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__29_n_0\
);
\cache_reg_gate__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__3_n_0\
);
\cache_reg_gate__30\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__30_n_0\
);
\cache_reg_gate__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__4_n_0\
);
\cache_reg_gate__5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__5_n_0\
);
\cache_reg_gate__6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__6_n_0\
);
\cache_reg_gate__7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__7_n_0\
);
\cache_reg_gate__8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__8_n_0\
);
\cache_reg_gate__9\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__9_n_0\
);
cache_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => '1',
Q => cache_reg_r_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_n_0,
Q => cache_reg_r_0_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_0_n_0,
Q => cache_reg_r_1_n_0,
R => \cache[9][15]_i_1_n_0\
);
\compute_addr_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(0),
O => \compute_addr_0[0]_i_1_n_0\
);
\compute_addr_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[10]_i_2_n_0\,
O => \compute_addr_0[10]_i_1_n_0\
);
\compute_addr_0[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[0]\,
I1 => data5(10),
I2 => cycle(3),
I3 => \y1_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[10]_i_2_n_0\
);
\compute_addr_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDCDC88888"
)
port map (
I0 => cycle(0),
I1 => data5(11),
I2 => cycle(3),
I3 => \y1_reg_n_0_[1]\,
I4 => \compute_addr_0[11]_i_2_n_0\,
I5 => \compute_addr_0[11]_i_3_n_0\,
O => \compute_addr_0[11]_i_1_n_0\
);
\compute_addr_0[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_2_n_0\
);
\compute_addr_0[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAAAAAACFC0"
)
port map (
I0 => \compute_addr_2[11]_i_2_n_0\,
I1 => \y1_reg_n_0_[1]\,
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_3_n_0\
);
\compute_addr_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[12]_i_2_n_0\,
O => \compute_addr_0[12]_i_1_n_0\
);
\compute_addr_0[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[2]\,
I1 => data5(12),
I2 => cycle(3),
I3 => \y1_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[12]_i_2_n_0\
);
\compute_addr_0[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(0),
O => compute_addr_0
);
\compute_addr_0[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[13]_i_3_n_0\,
O => \compute_addr_0[13]_i_2_n_0\
);
\compute_addr_0[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => \y1_reg_n_0_[3]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[13]_i_3_n_0\
);
\compute_addr_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(1),
O => \compute_addr_0[1]_i_1_n_0\
);
\compute_addr_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \compute_addr_0[2]_i_1_n_0\
);
\compute_addr_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(3),
O => \compute_addr_0[3]_i_1_n_0\
);
\compute_addr_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(4),
O => \compute_addr_0[4]_i_1_n_0\
);
\compute_addr_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(5),
O => \compute_addr_0[5]_i_1_n_0\
);
\compute_addr_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(6),
O => \compute_addr_0[6]_i_1_n_0\
);
\compute_addr_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \compute_addr_0[7]_i_1_n_0\
);
\compute_addr_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(8),
O => \compute_addr_0[8]_i_1_n_0\
);
\compute_addr_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data1(9),
O => \compute_addr_0[9]_i_1_n_0\
);
\compute_addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[0]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[0]\,
R => '0'
);
\compute_addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[10]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[10]\,
R => '0'
);
\compute_addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[11]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[11]\,
R => '0'
);
\compute_addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[12]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[12]\,
R => '0'
);
\compute_addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[13]_i_2_n_0\,
Q => \compute_addr_0_reg_n_0_[13]\,
R => '0'
);
\compute_addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[1]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[1]\,
R => '0'
);
\compute_addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[2]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[2]\,
R => '0'
);
\compute_addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[3]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[3]\,
R => '0'
);
\compute_addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[4]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[4]\,
R => '0'
);
\compute_addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[5]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[5]\,
R => '0'
);
\compute_addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[6]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[6]\,
R => '0'
);
\compute_addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[7]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[7]\,
R => '0'
);
\compute_addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[8]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[8]\,
R => '0'
);
\compute_addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[9]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[9]\,
R => '0'
);
\compute_addr_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(0),
O => \compute_addr_1[0]_i_1_n_0\
);
\compute_addr_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[10]_i_2_n_0\,
O => \compute_addr_1[10]_i_1_n_0\
);
\compute_addr_1[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(10),
I1 => data2(10),
I2 => cycle(3),
I3 => \y3_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[10]_i_2_n_0\
);
\compute_addr_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(11),
I1 => cycle(0),
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[11]_i_2_n_0\,
O => \compute_addr_1[11]_i_1_n_0\
);
\compute_addr_1[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(11),
I1 => data2(11),
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[11]_i_2_n_0\
);
\compute_addr_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[12]_i_2_n_0\,
O => \compute_addr_1[12]_i_1_n_0\
);
\compute_addr_1[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(12),
I1 => data2(12),
I2 => cycle(3),
I3 => \y3_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[12]_i_2_n_0\
);
\compute_addr_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[13]_i_2_n_0\,
O => \compute_addr_1[13]_i_1_n_0\
);
\compute_addr_1[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => data2(13),
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[13]_i_2_n_0\
);
\compute_addr_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(1),
O => \compute_addr_1[1]_i_1_n_0\
);
\compute_addr_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(2),
O => \compute_addr_1[2]_i_1_n_0\
);
\compute_addr_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(3),
O => \compute_addr_1[3]_i_1_n_0\
);
\compute_addr_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(4),
O => \compute_addr_1[4]_i_1_n_0\
);
\compute_addr_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(5),
O => \compute_addr_1[5]_i_1_n_0\
);
\compute_addr_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(6),
O => \compute_addr_1[6]_i_1_n_0\
);
\compute_addr_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(7),
O => \compute_addr_1[7]_i_1_n_0\
);
\compute_addr_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(8),
O => \compute_addr_1[8]_i_1_n_0\
);
\compute_addr_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(9),
O => \compute_addr_1[9]_i_1_n_0\
);
\compute_addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[0]_i_1_n_0\,
Q => compute_addr_1(0),
R => '0'
);
\compute_addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[10]_i_1_n_0\,
Q => compute_addr_1(10),
R => '0'
);
\compute_addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[11]_i_1_n_0\,
Q => compute_addr_1(11),
R => '0'
);
\compute_addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[12]_i_1_n_0\,
Q => compute_addr_1(12),
R => '0'
);
\compute_addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[13]_i_1_n_0\,
Q => compute_addr_1(13),
R => '0'
);
\compute_addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[1]_i_1_n_0\,
Q => compute_addr_1(1),
R => '0'
);
\compute_addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[2]_i_1_n_0\,
Q => compute_addr_1(2),
R => '0'
);
\compute_addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[3]_i_1_n_0\,
Q => compute_addr_1(3),
R => '0'
);
\compute_addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[4]_i_1_n_0\,
Q => compute_addr_1(4),
R => '0'
);
\compute_addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[5]_i_1_n_0\,
Q => compute_addr_1(5),
R => '0'
);
\compute_addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[6]_i_1_n_0\,
Q => compute_addr_1(6),
R => '0'
);
\compute_addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[7]_i_1_n_0\,
Q => compute_addr_1(7),
R => '0'
);
\compute_addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[8]_i_1_n_0\,
Q => compute_addr_1(8),
R => '0'
);
\compute_addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[9]_i_1_n_0\,
Q => compute_addr_1(9),
R => '0'
);
\compute_addr_2[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[0]\,
O => \compute_addr_2[10]_i_1_n_0\
);
\compute_addr_2[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[0]\,
I1 => cycle(3),
I2 => data1(10),
O => \compute_addr_2[10]_i_2_n_0\
);
\compute_addr_2[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[1]\,
O => \compute_addr_2[11]_i_1_n_0\
);
\compute_addr_2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[1]\,
I1 => cycle(3),
I2 => data1(11),
O => \compute_addr_2[11]_i_2_n_0\
);
\compute_addr_2[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[2]\,
O => \compute_addr_2[12]_i_1_n_0\
);
\compute_addr_2[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[2]\,
I1 => cycle(3),
I2 => data1(12),
O => \compute_addr_2[12]_i_2_n_0\
);
\compute_addr_2[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080808000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => compute_addr_2
);
\compute_addr_2[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[3]\,
O => \compute_addr_2[13]_i_2_n_0\
);
\compute_addr_2[13]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"81FF"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
O => \compute_addr_2[13]_i_3_n_0\
);
\compute_addr_2[13]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[3]\,
I1 => cycle(3),
I2 => data1(13),
O => \compute_addr_2[13]_i_4_n_0\
);
\compute_addr_2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(0),
Q => \compute_addr_2_reg_n_0_[0]\,
R => '0'
);
\compute_addr_2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[10]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[10]\,
R => '0'
);
\compute_addr_2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[11]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[11]\,
R => '0'
);
\compute_addr_2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[12]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[12]\,
R => '0'
);
\compute_addr_2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[13]_i_2_n_0\,
Q => \compute_addr_2_reg_n_0_[13]\,
R => '0'
);
\compute_addr_2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(1),
Q => \compute_addr_2_reg_n_0_[1]\,
R => '0'
);
\compute_addr_2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(2),
Q => \compute_addr_2_reg_n_0_[2]\,
R => '0'
);
\compute_addr_2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(3),
Q => \compute_addr_2_reg_n_0_[3]\,
R => '0'
);
\compute_addr_2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(4),
Q => \compute_addr_2_reg_n_0_[4]\,
R => '0'
);
\compute_addr_2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(5),
Q => \compute_addr_2_reg_n_0_[5]\,
R => '0'
);
\compute_addr_2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(6),
Q => \compute_addr_2_reg_n_0_[6]\,
R => '0'
);
\compute_addr_2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(7),
Q => \compute_addr_2_reg_n_0_[7]\,
R => '0'
);
\compute_addr_2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(8),
Q => \compute_addr_2_reg_n_0_[8]\,
R => '0'
);
\compute_addr_2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(9),
Q => \compute_addr_2_reg_n_0_[9]\,
R => '0'
);
\compute_addr_3[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(0),
O => \compute_addr_3[0]_i_1_n_0\
);
\compute_addr_3[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(10),
O => \compute_addr_3[10]_i_1_n_0\
);
\compute_addr_3[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(0),
I1 => cycle(3),
I2 => y8(0),
O => \compute_addr_3[10]_i_2_n_0\
);
\compute_addr_3[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(11),
O => \compute_addr_3[11]_i_1_n_0\
);
\compute_addr_3[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(1),
I1 => cycle(3),
I2 => y8(1),
O => \compute_addr_3[11]_i_2_n_0\
);
\compute_addr_3[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(12),
O => \compute_addr_3[12]_i_1_n_0\
);
\compute_addr_3[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(2),
I1 => cycle(3),
I2 => y8(2),
O => \compute_addr_3[12]_i_2_n_0\
);
\compute_addr_3[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(13),
O => \compute_addr_3[13]_i_1_n_0\
);
\compute_addr_3[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(3),
I1 => cycle(3),
I2 => y8(3),
O => \compute_addr_3[13]_i_2_n_0\
);
\compute_addr_3[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(1),
O => \compute_addr_3[1]_i_1_n_0\
);
\compute_addr_3[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(2),
O => \compute_addr_3[2]_i_1_n_0\
);
\compute_addr_3[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(3),
O => \compute_addr_3[3]_i_1_n_0\
);
\compute_addr_3[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(4),
O => \compute_addr_3[4]_i_1_n_0\
);
\compute_addr_3[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(5),
O => \compute_addr_3[5]_i_1_n_0\
);
\compute_addr_3[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(6),
O => \compute_addr_3[6]_i_1_n_0\
);
\compute_addr_3[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(7),
O => \compute_addr_3[7]_i_1_n_0\
);
\compute_addr_3[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(8),
O => \compute_addr_3[8]_i_1_n_0\
);
\compute_addr_3[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(9),
O => \compute_addr_3[9]_i_1_n_0\
);
\compute_addr_3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[0]_i_1_n_0\,
Q => compute_addr_3(0),
R => '0'
);
\compute_addr_3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[10]_i_1_n_0\,
Q => compute_addr_3(10),
R => '0'
);
\compute_addr_3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[11]_i_1_n_0\,
Q => compute_addr_3(11),
R => '0'
);
\compute_addr_3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[12]_i_1_n_0\,
Q => compute_addr_3(12),
R => '0'
);
\compute_addr_3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[13]_i_1_n_0\,
Q => compute_addr_3(13),
R => '0'
);
\compute_addr_3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[1]_i_1_n_0\,
Q => compute_addr_3(1),
R => '0'
);
\compute_addr_3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[2]_i_1_n_0\,
Q => compute_addr_3(2),
R => '0'
);
\compute_addr_3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[3]_i_1_n_0\,
Q => compute_addr_3(3),
R => '0'
);
\compute_addr_3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[4]_i_1_n_0\,
Q => compute_addr_3(4),
R => '0'
);
\compute_addr_3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[5]_i_1_n_0\,
Q => compute_addr_3(5),
R => '0'
);
\compute_addr_3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[6]_i_1_n_0\,
Q => compute_addr_3(6),
R => '0'
);
\compute_addr_3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[7]_i_1_n_0\,
Q => compute_addr_3(7),
R => '0'
);
\compute_addr_3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[8]_i_1_n_0\,
Q => compute_addr_3(8),
R => '0'
);
\compute_addr_3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[9]_i_1_n_0\,
Q => compute_addr_3(9),
R => '0'
);
\corner[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
I5 => top,
O => corner
);
\corner_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(0),
Q => \corner_reg_n_0_[0]\,
R => corner
);
\corner_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(10),
Q => \corner_reg_n_0_[10]\,
R => corner
);
\corner_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(11),
Q => \corner_reg_n_0_[11]\,
R => corner
);
\corner_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(12),
Q => \corner_reg_n_0_[12]\,
R => corner
);
\corner_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(13),
Q => \corner_reg_n_0_[13]\,
R => corner
);
\corner_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(14),
Q => \corner_reg_n_0_[14]\,
R => corner
);
\corner_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(15),
Q => \corner_reg_n_0_[15]\,
R => corner
);
\corner_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(1),
Q => \corner_reg_n_0_[1]\,
R => corner
);
\corner_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(2),
Q => \corner_reg_n_0_[2]\,
R => corner
);
\corner_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(3),
Q => \corner_reg_n_0_[3]\,
R => corner
);
\corner_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(4),
Q => \corner_reg_n_0_[4]\,
R => corner
);
\corner_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(5),
Q => \corner_reg_n_0_[5]\,
R => corner
);
\corner_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(6),
Q => \corner_reg_n_0_[6]\,
R => corner
);
\corner_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(7),
Q => \corner_reg_n_0_[7]\,
R => corner
);
\corner_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(8),
Q => \corner_reg_n_0_[8]\,
R => corner
);
\corner_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(9),
Q => \corner_reg_n_0_[9]\,
R => corner
);
\cycle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_i_1_n_0\
);
\cycle[0]_rep_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_rep_i_1_n_0\
);
\cycle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_i_1_n_0\
);
\cycle[1]_rep_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1_n_0\
);
\cycle[1]_rep_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1__0_n_0\
);
\cycle[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => cycle(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
O => \cycle[2]_i_1_n_0\
);
\cycle[2]_rep_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => cycle(0),
I2 => cycle(2),
O => \cycle[2]_rep_i_1_n_0\
);
\cycle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => active,
O => \cycle[3]_i_1_n_0\
);
\cycle[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => cycle(1),
I3 => \cycle_reg[0]_rep_n_0\,
O => \cycle[3]_i_2_n_0\
);
\cycle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_i_1_n_0\,
Q => cycle(0),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_rep_i_1_n_0\,
Q => \cycle_reg[0]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_i_1_n_0\,
Q => cycle(1),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1_n_0\,
Q => \cycle_reg[1]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1__0_n_0\,
Q => \cycle_reg[1]_rep__0_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_i_1_n_0\,
Q => cycle(2),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_rep_i_1_n_0\,
Q => \cycle_reg[2]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[3]_i_2_n_0\,
Q => cycle(3),
R => \cycle[3]_i_1_n_0\
);
det_0_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => A(15),
A(28) => A(15),
A(27) => A(15),
A(26) => A(15),
A(25) => A(15),
A(24) => A(15),
A(23) => A(15),
A(22) => A(15),
A(21) => A(15),
A(20) => A(15),
A(19) => A(15),
A(18) => A(15),
A(17) => A(15),
A(16) => A(15),
A(15 downto 0) => A(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_0_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => B(15),
B(16) => B(15),
B(15 downto 0) => B(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_0_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_0_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => Lxx,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => det_0_reg_i_2_n_0,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => det_0,
CEP => '0',
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_det_0_reg_OVERFLOW_UNCONNECTED,
P(47 downto 0) => NLW_det_0_reg_P_UNCONNECTED(47 downto 0),
PATTERNBDETECT => NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_0_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => det_0_reg_n_106,
PCOUT(46) => det_0_reg_n_107,
PCOUT(45) => det_0_reg_n_108,
PCOUT(44) => det_0_reg_n_109,
PCOUT(43) => det_0_reg_n_110,
PCOUT(42) => det_0_reg_n_111,
PCOUT(41) => det_0_reg_n_112,
PCOUT(40) => det_0_reg_n_113,
PCOUT(39) => det_0_reg_n_114,
PCOUT(38) => det_0_reg_n_115,
PCOUT(37) => det_0_reg_n_116,
PCOUT(36) => det_0_reg_n_117,
PCOUT(35) => det_0_reg_n_118,
PCOUT(34) => det_0_reg_n_119,
PCOUT(33) => det_0_reg_n_120,
PCOUT(32) => det_0_reg_n_121,
PCOUT(31) => det_0_reg_n_122,
PCOUT(30) => det_0_reg_n_123,
PCOUT(29) => det_0_reg_n_124,
PCOUT(28) => det_0_reg_n_125,
PCOUT(27) => det_0_reg_n_126,
PCOUT(26) => det_0_reg_n_127,
PCOUT(25) => det_0_reg_n_128,
PCOUT(24) => det_0_reg_n_129,
PCOUT(23) => det_0_reg_n_130,
PCOUT(22) => det_0_reg_n_131,
PCOUT(21) => det_0_reg_n_132,
PCOUT(20) => det_0_reg_n_133,
PCOUT(19) => det_0_reg_n_134,
PCOUT(18) => det_0_reg_n_135,
PCOUT(17) => det_0_reg_n_136,
PCOUT(16) => det_0_reg_n_137,
PCOUT(15) => det_0_reg_n_138,
PCOUT(14) => det_0_reg_n_139,
PCOUT(13) => det_0_reg_n_140,
PCOUT(12) => det_0_reg_n_141,
PCOUT(11) => det_0_reg_n_142,
PCOUT(10) => det_0_reg_n_143,
PCOUT(9) => det_0_reg_n_144,
PCOUT(8) => det_0_reg_n_145,
PCOUT(7) => det_0_reg_n_146,
PCOUT(6) => det_0_reg_n_147,
PCOUT(5) => det_0_reg_n_148,
PCOUT(4) => det_0_reg_n_149,
PCOUT(3) => det_0_reg_n_150,
PCOUT(2) => det_0_reg_n_151,
PCOUT(1) => det_0_reg_n_152,
PCOUT(0) => det_0_reg_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_0_reg_UNDERFLOW_UNCONNECTED
);
det_0_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => Lxx
);
det_0_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => rst,
I5 => active,
O => det_0_reg_i_2_n_0
);
det_0_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => cycle(1),
I3 => rst,
I4 => active,
I5 => \cycle_reg[0]_rep_n_0\,
O => det_0
);
\det_abs[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(10),
I1 => det_reg_n_95,
I2 => det_reg_n_74,
O => \det_abs[10]_i_1_n_0\
);
\det_abs[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(11),
I1 => det_reg_n_94,
I2 => det_reg_n_74,
O => \det_abs[11]_i_1_n_0\
);
\det_abs[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(12),
I1 => det_reg_n_93,
I2 => det_reg_n_74,
O => \det_abs[12]_i_1_n_0\
);
\det_abs[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_93,
O => \det_abs[12]_i_3_n_0\
);
\det_abs[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_94,
O => \det_abs[12]_i_4_n_0\
);
\det_abs[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_95,
O => \det_abs[12]_i_5_n_0\
);
\det_abs[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_96,
O => \det_abs[12]_i_6_n_0\
);
\det_abs[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(13),
I1 => det_reg_n_92,
I2 => det_reg_n_74,
O => \det_abs[13]_i_1_n_0\
);
\det_abs[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(14),
I1 => det_reg_n_91,
I2 => det_reg_n_74,
O => \det_abs[14]_i_1_n_0\
);
\det_abs[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(15),
I1 => det_reg_n_90,
I2 => det_reg_n_74,
O => \det_abs[15]_i_1_n_0\
);
\det_abs[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(16),
I1 => det_reg_n_89,
I2 => det_reg_n_74,
O => \det_abs[16]_i_1_n_0\
);
\det_abs[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_89,
O => \det_abs[16]_i_3_n_0\
);
\det_abs[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_90,
O => \det_abs[16]_i_4_n_0\
);
\det_abs[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_91,
O => \det_abs[16]_i_5_n_0\
);
\det_abs[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_92,
O => \det_abs[16]_i_6_n_0\
);
\det_abs[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(17),
I1 => det_reg_n_88,
I2 => det_reg_n_74,
O => \det_abs[17]_i_1_n_0\
);
\det_abs[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(18),
I1 => det_reg_n_87,
I2 => det_reg_n_74,
O => \det_abs[18]_i_1_n_0\
);
\det_abs[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(19),
I1 => det_reg_n_86,
I2 => det_reg_n_74,
O => \det_abs[19]_i_1_n_0\
);
\det_abs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(1),
I1 => det_reg_n_104,
I2 => det_reg_n_74,
O => \det_abs[1]_i_1_n_0\
);
\det_abs[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(20),
I1 => det_reg_n_85,
I2 => det_reg_n_74,
O => \det_abs[20]_i_1_n_0\
);
\det_abs[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_85,
O => \det_abs[20]_i_3_n_0\
);
\det_abs[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_86,
O => \det_abs[20]_i_4_n_0\
);
\det_abs[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_87,
O => \det_abs[20]_i_5_n_0\
);
\det_abs[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_88,
O => \det_abs[20]_i_6_n_0\
);
\det_abs[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(21),
I1 => det_reg_n_84,
I2 => det_reg_n_74,
O => \det_abs[21]_i_1_n_0\
);
\det_abs[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(22),
I1 => det_reg_n_83,
I2 => det_reg_n_74,
O => \det_abs[22]_i_1_n_0\
);
\det_abs[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(23),
I1 => det_reg_n_82,
I2 => det_reg_n_74,
O => \det_abs[23]_i_1_n_0\
);
\det_abs[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(24),
I1 => det_reg_n_81,
I2 => det_reg_n_74,
O => \det_abs[24]_i_1_n_0\
);
\det_abs[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_81,
O => \det_abs[24]_i_3_n_0\
);
\det_abs[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_82,
O => \det_abs[24]_i_4_n_0\
);
\det_abs[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_83,
O => \det_abs[24]_i_5_n_0\
);
\det_abs[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_84,
O => \det_abs[24]_i_6_n_0\
);
\det_abs[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(25),
I1 => det_reg_n_80,
I2 => det_reg_n_74,
O => \det_abs[25]_i_1_n_0\
);
\det_abs[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(26),
I1 => det_reg_n_79,
I2 => det_reg_n_74,
O => \det_abs[26]_i_1_n_0\
);
\det_abs[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(27),
I1 => det_reg_n_78,
I2 => det_reg_n_74,
O => \det_abs[27]_i_1_n_0\
);
\det_abs[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(28),
I1 => det_reg_n_77,
I2 => det_reg_n_74,
O => \det_abs[28]_i_1_n_0\
);
\det_abs[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_77,
O => \det_abs[28]_i_3_n_0\
);
\det_abs[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_78,
O => \det_abs[28]_i_4_n_0\
);
\det_abs[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_79,
O => \det_abs[28]_i_5_n_0\
);
\det_abs[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_80,
O => \det_abs[28]_i_6_n_0\
);
\det_abs[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(29),
I1 => det_reg_n_76,
I2 => det_reg_n_74,
O => \det_abs[29]_i_1_n_0\
);
\det_abs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(2),
I1 => det_reg_n_103,
I2 => det_reg_n_74,
O => \det_abs[2]_i_1_n_0\
);
\det_abs[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(30),
I1 => det_reg_n_75,
I2 => det_reg_n_74,
O => \det_abs[30]_i_1_n_0\
);
\det_abs[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => det_abs0(31),
I1 => det_reg_n_74,
O => \det_abs[31]_i_1_n_0\
);
\det_abs[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_74,
O => \det_abs[31]_i_3_n_0\
);
\det_abs[31]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_75,
O => \det_abs[31]_i_4_n_0\
);
\det_abs[31]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_76,
O => \det_abs[31]_i_5_n_0\
);
\det_abs[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(3),
I1 => det_reg_n_102,
I2 => det_reg_n_74,
O => \det_abs[3]_i_1_n_0\
);
\det_abs[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(4),
I1 => det_reg_n_101,
I2 => det_reg_n_74,
O => \det_abs[4]_i_1_n_0\
);
\det_abs[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_105,
O => \det_abs[4]_i_3_n_0\
);
\det_abs[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_101,
O => \det_abs[4]_i_4_n_0\
);
\det_abs[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_102,
O => \det_abs[4]_i_5_n_0\
);
\det_abs[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_103,
O => \det_abs[4]_i_6_n_0\
);
\det_abs[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_104,
O => \det_abs[4]_i_7_n_0\
);
\det_abs[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(5),
I1 => det_reg_n_100,
I2 => det_reg_n_74,
O => \det_abs[5]_i_1_n_0\
);
\det_abs[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(6),
I1 => det_reg_n_99,
I2 => det_reg_n_74,
O => \det_abs[6]_i_1_n_0\
);
\det_abs[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(7),
I1 => det_reg_n_98,
I2 => det_reg_n_74,
O => \det_abs[7]_i_1_n_0\
);
\det_abs[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(8),
I1 => det_reg_n_97,
I2 => det_reg_n_74,
O => \det_abs[8]_i_1_n_0\
);
\det_abs[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_97,
O => \det_abs[8]_i_3_n_0\
);
\det_abs[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_98,
O => \det_abs[8]_i_4_n_0\
);
\det_abs[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_99,
O => \det_abs[8]_i_5_n_0\
);
\det_abs[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_100,
O => \det_abs[8]_i_6_n_0\
);
\det_abs[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(9),
I1 => det_reg_n_96,
I2 => det_reg_n_74,
O => \det_abs[9]_i_1_n_0\
);
\det_abs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => det_reg_n_105,
Q => det_abs(0),
R => '0'
);
\det_abs_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[10]_i_1_n_0\,
Q => det_abs(10),
R => '0'
);
\det_abs_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[11]_i_1_n_0\,
Q => det_abs(11),
R => '0'
);
\det_abs_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[12]_i_1_n_0\,
Q => det_abs(12),
R => '0'
);
\det_abs_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[8]_i_2_n_0\,
CO(3) => \det_abs_reg[12]_i_2_n_0\,
CO(2) => \det_abs_reg[12]_i_2_n_1\,
CO(1) => \det_abs_reg[12]_i_2_n_2\,
CO(0) => \det_abs_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(12 downto 9),
S(3) => \det_abs[12]_i_3_n_0\,
S(2) => \det_abs[12]_i_4_n_0\,
S(1) => \det_abs[12]_i_5_n_0\,
S(0) => \det_abs[12]_i_6_n_0\
);
\det_abs_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[13]_i_1_n_0\,
Q => det_abs(13),
R => '0'
);
\det_abs_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[14]_i_1_n_0\,
Q => det_abs(14),
R => '0'
);
\det_abs_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[15]_i_1_n_0\,
Q => det_abs(15),
R => '0'
);
\det_abs_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[16]_i_1_n_0\,
Q => det_abs(16),
R => '0'
);
\det_abs_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[12]_i_2_n_0\,
CO(3) => \det_abs_reg[16]_i_2_n_0\,
CO(2) => \det_abs_reg[16]_i_2_n_1\,
CO(1) => \det_abs_reg[16]_i_2_n_2\,
CO(0) => \det_abs_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(16 downto 13),
S(3) => \det_abs[16]_i_3_n_0\,
S(2) => \det_abs[16]_i_4_n_0\,
S(1) => \det_abs[16]_i_5_n_0\,
S(0) => \det_abs[16]_i_6_n_0\
);
\det_abs_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[17]_i_1_n_0\,
Q => det_abs(17),
R => '0'
);
\det_abs_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[18]_i_1_n_0\,
Q => det_abs(18),
R => '0'
);
\det_abs_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[19]_i_1_n_0\,
Q => det_abs(19),
R => '0'
);
\det_abs_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[1]_i_1_n_0\,
Q => det_abs(1),
R => '0'
);
\det_abs_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[20]_i_1_n_0\,
Q => det_abs(20),
R => '0'
);
\det_abs_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[16]_i_2_n_0\,
CO(3) => \det_abs_reg[20]_i_2_n_0\,
CO(2) => \det_abs_reg[20]_i_2_n_1\,
CO(1) => \det_abs_reg[20]_i_2_n_2\,
CO(0) => \det_abs_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(20 downto 17),
S(3) => \det_abs[20]_i_3_n_0\,
S(2) => \det_abs[20]_i_4_n_0\,
S(1) => \det_abs[20]_i_5_n_0\,
S(0) => \det_abs[20]_i_6_n_0\
);
\det_abs_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[21]_i_1_n_0\,
Q => det_abs(21),
R => '0'
);
\det_abs_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[22]_i_1_n_0\,
Q => det_abs(22),
R => '0'
);
\det_abs_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[23]_i_1_n_0\,
Q => det_abs(23),
R => '0'
);
\det_abs_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[24]_i_1_n_0\,
Q => det_abs(24),
R => '0'
);
\det_abs_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[20]_i_2_n_0\,
CO(3) => \det_abs_reg[24]_i_2_n_0\,
CO(2) => \det_abs_reg[24]_i_2_n_1\,
CO(1) => \det_abs_reg[24]_i_2_n_2\,
CO(0) => \det_abs_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(24 downto 21),
S(3) => \det_abs[24]_i_3_n_0\,
S(2) => \det_abs[24]_i_4_n_0\,
S(1) => \det_abs[24]_i_5_n_0\,
S(0) => \det_abs[24]_i_6_n_0\
);
\det_abs_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[25]_i_1_n_0\,
Q => det_abs(25),
R => '0'
);
\det_abs_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[26]_i_1_n_0\,
Q => det_abs(26),
R => '0'
);
\det_abs_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[27]_i_1_n_0\,
Q => det_abs(27),
R => '0'
);
\det_abs_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[28]_i_1_n_0\,
Q => det_abs(28),
R => '0'
);
\det_abs_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[24]_i_2_n_0\,
CO(3) => \det_abs_reg[28]_i_2_n_0\,
CO(2) => \det_abs_reg[28]_i_2_n_1\,
CO(1) => \det_abs_reg[28]_i_2_n_2\,
CO(0) => \det_abs_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(28 downto 25),
S(3) => \det_abs[28]_i_3_n_0\,
S(2) => \det_abs[28]_i_4_n_0\,
S(1) => \det_abs[28]_i_5_n_0\,
S(0) => \det_abs[28]_i_6_n_0\
);
\det_abs_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[29]_i_1_n_0\,
Q => det_abs(29),
R => '0'
);
\det_abs_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[2]_i_1_n_0\,
Q => det_abs(2),
R => '0'
);
\det_abs_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[30]_i_1_n_0\,
Q => det_abs(30),
R => '0'
);
\det_abs_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[31]_i_1_n_0\,
Q => det_abs(31),
R => '0'
);
\det_abs_reg[31]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \det_abs_reg[31]_i_2_n_2\,
CO(0) => \det_abs_reg[31]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\(3),
O(2 downto 0) => det_abs0(31 downto 29),
S(3) => '0',
S(2) => \det_abs[31]_i_3_n_0\,
S(1) => \det_abs[31]_i_4_n_0\,
S(0) => \det_abs[31]_i_5_n_0\
);
\det_abs_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[3]_i_1_n_0\,
Q => det_abs(3),
R => '0'
);
\det_abs_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[4]_i_1_n_0\,
Q => det_abs(4),
R => '0'
);
\det_abs_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \det_abs_reg[4]_i_2_n_0\,
CO(2) => \det_abs_reg[4]_i_2_n_1\,
CO(1) => \det_abs_reg[4]_i_2_n_2\,
CO(0) => \det_abs_reg[4]_i_2_n_3\,
CYINIT => \det_abs[4]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(4 downto 1),
S(3) => \det_abs[4]_i_4_n_0\,
S(2) => \det_abs[4]_i_5_n_0\,
S(1) => \det_abs[4]_i_6_n_0\,
S(0) => \det_abs[4]_i_7_n_0\
);
\det_abs_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[5]_i_1_n_0\,
Q => det_abs(5),
R => '0'
);
\det_abs_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[6]_i_1_n_0\,
Q => det_abs(6),
R => '0'
);
\det_abs_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[7]_i_1_n_0\,
Q => det_abs(7),
R => '0'
);
\det_abs_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[8]_i_1_n_0\,
Q => det_abs(8),
R => '0'
);
\det_abs_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[4]_i_2_n_0\,
CO(3) => \det_abs_reg[8]_i_2_n_0\,
CO(2) => \det_abs_reg[8]_i_2_n_1\,
CO(1) => \det_abs_reg[8]_i_2_n_2\,
CO(0) => \det_abs_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(8 downto 5),
S(3) => \det_abs[8]_i_3_n_0\,
S(2) => \det_abs[8]_i_4_n_0\,
S(1) => \det_abs[8]_i_5_n_0\,
S(0) => \det_abs[8]_i_6_n_0\
);
\det_abs_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[9]_i_1_n_0\,
Q => det_abs(9),
R => '0'
);
det_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \Lxy0__1_carry__2_n_4\,
A(28) => \Lxy0__1_carry__2_n_4\,
A(27) => \Lxy0__1_carry__2_n_4\,
A(26) => \Lxy0__1_carry__2_n_4\,
A(25) => \Lxy0__1_carry__2_n_4\,
A(24) => \Lxy0__1_carry__2_n_4\,
A(23) => \Lxy0__1_carry__2_n_4\,
A(22) => \Lxy0__1_carry__2_n_4\,
A(21) => \Lxy0__1_carry__2_n_4\,
A(20) => \Lxy0__1_carry__2_n_4\,
A(19) => \Lxy0__1_carry__2_n_4\,
A(18) => \Lxy0__1_carry__2_n_4\,
A(17) => \Lxy0__1_carry__2_n_4\,
A(16) => \Lxy0__1_carry__2_n_4\,
A(15) => \Lxy0__1_carry__2_n_4\,
A(14) => \Lxy0__1_carry__2_n_5\,
A(13) => \Lxy0__1_carry__2_n_6\,
A(12) => \Lxy0__1_carry__2_n_7\,
A(11) => \Lxy0__1_carry__1_n_4\,
A(10) => \Lxy0__1_carry__1_n_5\,
A(9) => \Lxy0__1_carry__1_n_6\,
A(8) => \Lxy0__1_carry__1_n_7\,
A(7) => \Lxy0__1_carry__0_n_4\,
A(6) => \Lxy0__1_carry__0_n_5\,
A(5) => \Lxy0__1_carry__0_n_6\,
A(4) => \Lxy0__1_carry__0_n_7\,
A(3) => \Lxy0__1_carry_n_4\,
A(2) => \Lxy0__1_carry_n_5\,
A(1) => \Lxy0__1_carry_n_6\,
A(0) => \Lxy0__1_carry_n_7\,
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0011",
B(17) => \Lxy0__1_carry__2_n_4\,
B(16) => \Lxy0__1_carry__2_n_4\,
B(15) => \Lxy0__1_carry__2_n_4\,
B(14) => \Lxy0__1_carry__2_n_5\,
B(13) => \Lxy0__1_carry__2_n_6\,
B(12) => \Lxy0__1_carry__2_n_7\,
B(11) => \Lxy0__1_carry__1_n_4\,
B(10) => \Lxy0__1_carry__1_n_5\,
B(9) => \Lxy0__1_carry__1_n_6\,
B(8) => \Lxy0__1_carry__1_n_7\,
B(7) => \Lxy0__1_carry__0_n_4\,
B(6) => \Lxy0__1_carry__0_n_5\,
B(5) => \Lxy0__1_carry__0_n_6\,
B(4) => \Lxy0__1_carry__0_n_7\,
B(3) => \Lxy0__1_carry_n_4\,
B(2) => \Lxy0__1_carry_n_5\,
B(1) => \Lxy0__1_carry_n_6\,
B(0) => \Lxy0__1_carry_n_7\,
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => y3,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => y3,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => y2,
CEP => y9,
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0010101",
OVERFLOW => NLW_det_reg_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_det_reg_P_UNCONNECTED(47 downto 32),
P(31) => det_reg_n_74,
P(30) => det_reg_n_75,
P(29) => det_reg_n_76,
P(28) => det_reg_n_77,
P(27) => det_reg_n_78,
P(26) => det_reg_n_79,
P(25) => det_reg_n_80,
P(24) => det_reg_n_81,
P(23) => det_reg_n_82,
P(22) => det_reg_n_83,
P(21) => det_reg_n_84,
P(20) => det_reg_n_85,
P(19) => det_reg_n_86,
P(18) => det_reg_n_87,
P(17) => det_reg_n_88,
P(16) => det_reg_n_89,
P(15) => det_reg_n_90,
P(14) => det_reg_n_91,
P(13) => det_reg_n_92,
P(12) => det_reg_n_93,
P(11) => det_reg_n_94,
P(10) => det_reg_n_95,
P(9) => det_reg_n_96,
P(8) => det_reg_n_97,
P(7) => det_reg_n_98,
P(6) => det_reg_n_99,
P(5) => det_reg_n_100,
P(4) => det_reg_n_101,
P(3) => det_reg_n_102,
P(2) => det_reg_n_103,
P(1) => det_reg_n_104,
P(0) => det_reg_n_105,
PATTERNBDETECT => NLW_det_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47) => det_0_reg_n_106,
PCIN(46) => det_0_reg_n_107,
PCIN(45) => det_0_reg_n_108,
PCIN(44) => det_0_reg_n_109,
PCIN(43) => det_0_reg_n_110,
PCIN(42) => det_0_reg_n_111,
PCIN(41) => det_0_reg_n_112,
PCIN(40) => det_0_reg_n_113,
PCIN(39) => det_0_reg_n_114,
PCIN(38) => det_0_reg_n_115,
PCIN(37) => det_0_reg_n_116,
PCIN(36) => det_0_reg_n_117,
PCIN(35) => det_0_reg_n_118,
PCIN(34) => det_0_reg_n_119,
PCIN(33) => det_0_reg_n_120,
PCIN(32) => det_0_reg_n_121,
PCIN(31) => det_0_reg_n_122,
PCIN(30) => det_0_reg_n_123,
PCIN(29) => det_0_reg_n_124,
PCIN(28) => det_0_reg_n_125,
PCIN(27) => det_0_reg_n_126,
PCIN(26) => det_0_reg_n_127,
PCIN(25) => det_0_reg_n_128,
PCIN(24) => det_0_reg_n_129,
PCIN(23) => det_0_reg_n_130,
PCIN(22) => det_0_reg_n_131,
PCIN(21) => det_0_reg_n_132,
PCIN(20) => det_0_reg_n_133,
PCIN(19) => det_0_reg_n_134,
PCIN(18) => det_0_reg_n_135,
PCIN(17) => det_0_reg_n_136,
PCIN(16) => det_0_reg_n_137,
PCIN(15) => det_0_reg_n_138,
PCIN(14) => det_0_reg_n_139,
PCIN(13) => det_0_reg_n_140,
PCIN(12) => det_0_reg_n_141,
PCIN(11) => det_0_reg_n_142,
PCIN(10) => det_0_reg_n_143,
PCIN(9) => det_0_reg_n_144,
PCIN(8) => det_0_reg_n_145,
PCIN(7) => det_0_reg_n_146,
PCIN(6) => det_0_reg_n_147,
PCIN(5) => det_0_reg_n_148,
PCIN(4) => det_0_reg_n_149,
PCIN(3) => det_0_reg_n_150,
PCIN(2) => det_0_reg_n_151,
PCIN(1) => det_0_reg_n_152,
PCIN(0) => det_0_reg_n_153,
PCOUT(47 downto 0) => NLW_det_reg_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_reg_UNDERFLOW_UNCONNECTED
);
det_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y2
);
det_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y9
);
\din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(0),
Q => \din_reg_n_0_[0]\,
R => '0'
);
\din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(10),
Q => \din_reg_n_0_[10]\,
R => '0'
);
\din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(11),
Q => \din_reg_n_0_[11]\,
R => '0'
);
\din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(12),
Q => \din_reg_n_0_[12]\,
R => '0'
);
\din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(13),
Q => \din_reg_n_0_[13]\,
R => '0'
);
\din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(14),
Q => \din_reg_n_0_[14]\,
R => '0'
);
\din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(15),
Q => \din_reg_n_0_[15]\,
R => '0'
);
\din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(1),
Q => \din_reg_n_0_[1]\,
R => '0'
);
\din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(2),
Q => \din_reg_n_0_[2]\,
R => '0'
);
\din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(3),
Q => \din_reg_n_0_[3]\,
R => '0'
);
\din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(4),
Q => \din_reg_n_0_[4]\,
R => '0'
);
\din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(5),
Q => \din_reg_n_0_[5]\,
R => '0'
);
\din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(6),
Q => \din_reg_n_0_[6]\,
R => '0'
);
\din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(7),
Q => \din_reg_n_0_[7]\,
R => '0'
);
\din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(8),
Q => \din_reg_n_0_[8]\,
R => '0'
);
\din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(9),
Q => \din_reg_n_0_[9]\,
R => '0'
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y3
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(0),
Q => hessian_out(0),
R => '0'
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(10),
Q => hessian_out(10),
R => '0'
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(11),
Q => hessian_out(11),
R => '0'
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(12),
Q => hessian_out(12),
R => '0'
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(13),
Q => hessian_out(13),
R => '0'
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(14),
Q => hessian_out(14),
R => '0'
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(15),
Q => hessian_out(15),
R => '0'
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(16),
Q => hessian_out(16),
R => '0'
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(17),
Q => hessian_out(17),
R => '0'
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(18),
Q => hessian_out(18),
R => '0'
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(19),
Q => hessian_out(19),
R => '0'
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(1),
Q => hessian_out(1),
R => '0'
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(20),
Q => hessian_out(20),
R => '0'
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(21),
Q => hessian_out(21),
R => '0'
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(22),
Q => hessian_out(22),
R => '0'
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(23),
Q => hessian_out(23),
R => '0'
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(24),
Q => hessian_out(24),
R => '0'
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(25),
Q => hessian_out(25),
R => '0'
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(26),
Q => hessian_out(26),
R => '0'
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(27),
Q => hessian_out(27),
R => '0'
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(28),
Q => hessian_out(28),
R => '0'
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(29),
Q => hessian_out(29),
R => '0'
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(2),
Q => hessian_out(2),
R => '0'
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(30),
Q => hessian_out(30),
R => '0'
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(31),
Q => hessian_out(31),
R => '0'
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(3),
Q => hessian_out(3),
R => '0'
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(4),
Q => hessian_out(4),
R => '0'
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(5),
Q => hessian_out(5),
R => '0'
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(6),
Q => hessian_out(6),
R => '0'
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(7),
Q => hessian_out(7),
R => '0'
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(8),
Q => hessian_out(8),
R => '0'
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(9),
Q => hessian_out(9),
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[7]\,
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[6]\,
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[5]\,
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[4]\,
O => \i__carry__0_i_5_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[9]\,
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[8]\,
O => \i__carry__1_i_2_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[3]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55599555"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"5595"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_4_n_0\
);
\last_value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[0]\,
Q => last_value(0),
R => '0'
);
\last_value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[1]\,
Q => last_value(1),
R => '0'
);
\last_value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[2]\,
Q => last_value(2),
R => '0'
);
\last_value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[3]\,
Q => last_value(3),
R => '0'
);
\last_value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[4]\,
Q => last_value(4),
R => '0'
);
\last_value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[5]\,
Q => last_value(5),
R => '0'
);
\last_value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[6]\,
Q => last_value(6),
R => '0'
);
\last_value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[7]\,
Q => last_value(7),
R => '0'
);
\left[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
O => left
);
\left[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[6]\,
I3 => \left[15]_i_3_n_0\,
O => \left[15]_i_2_n_0\
);
\left[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \left[15]_i_3_n_0\
);
\left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(0),
Q => \left_reg_n_0_[0]\,
R => left
);
\left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(10),
Q => \left_reg_n_0_[10]\,
R => left
);
\left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(11),
Q => \left_reg_n_0_[11]\,
R => left
);
\left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(12),
Q => \left_reg_n_0_[12]\,
R => left
);
\left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(13),
Q => \left_reg_n_0_[13]\,
R => left
);
\left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(14),
Q => \left_reg_n_0_[14]\,
R => left
);
\left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(15),
Q => \left_reg_n_0_[15]\,
R => left
);
\left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(1),
Q => \left_reg_n_0_[1]\,
R => left
);
\left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(2),
Q => \left_reg_n_0_[2]\,
R => left
);
\left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(3),
Q => \left_reg_n_0_[3]\,
R => left
);
\left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(4),
Q => \left_reg_n_0_[4]\,
R => left
);
\left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(5),
Q => \left_reg_n_0_[5]\,
R => left
);
\left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(6),
Q => \left_reg_n_0_[6]\,
R => left
);
\left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(7),
Q => \left_reg_n_0_[7]\,
R => left
);
\left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(8),
Q => \left_reg_n_0_[8]\,
R => left
);
\left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(9),
Q => \left_reg_n_0_[9]\,
R => left
);
\plusOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \plusOp_inferred__0/i__carry_n_0\,
CO(2) => \plusOp_inferred__0/i__carry_n_1\,
CO(1) => \plusOp_inferred__0/i__carry_n_2\,
CO(0) => \plusOp_inferred__0/i__carry_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[3]\,
DI(2) => \x_reg_n_0_[2]\,
DI(1) => \x_reg_n_0_[1]\,
DI(0) => \x_reg_n_0_[0]\,
O(3) => \plusOp_inferred__0/i__carry_n_4\,
O(2) => \plusOp_inferred__0/i__carry_n_5\,
O(1) => \plusOp_inferred__0/i__carry_n_6\,
O(0) => \plusOp_inferred__0/i__carry_n_7\,
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\plusOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry_n_0\,
CO(3) => \plusOp_inferred__0/i__carry__0_n_0\,
CO(2) => \plusOp_inferred__0/i__carry__0_n_1\,
CO(1) => \plusOp_inferred__0/i__carry__0_n_2\,
CO(0) => \plusOp_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[6]\,
DI(2) => \x_reg_n_0_[5]\,
DI(1) => \x_reg_n_0_[4]\,
DI(0) => \i__carry__0_i_1_n_0\,
O(3) => \plusOp_inferred__0/i__carry__0_n_4\,
O(2) => \plusOp_inferred__0/i__carry__0_n_5\,
O(1) => \plusOp_inferred__0/i__carry__0_n_6\,
O(0) => \plusOp_inferred__0/i__carry__0_n_7\,
S(3) => \i__carry__0_i_2_n_0\,
S(2) => \i__carry__0_i_3_n_0\,
S(1) => \i__carry__0_i_4_n_0\,
S(0) => \i__carry__0_i_5_n_0\
);
\plusOp_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_reg_n_0_[7]\,
O(3 downto 2) => \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_inferred__0/i__carry__1_n_6\,
O(0) => \plusOp_inferred__0/i__carry__1_n_7\,
S(3 downto 2) => B"00",
S(1) => \i__carry__1_i_1_n_0\,
S(0) => \i__carry__1_i_2_n_0\
);
\top[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => x,
I1 => \top[15]_i_2_n_0\,
I2 => \y_actual_reg_n_0_[3]\,
I3 => \y_actual_reg_n_0_[0]\,
I4 => \y_actual_reg_n_0_[1]\,
I5 => \y_actual_reg_n_0_[2]\,
O => top
);
\top[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \y_actual_reg_n_0_[8]\,
I1 => \y_actual_reg_n_0_[9]\,
I2 => \y_actual_reg_n_0_[6]\,
I3 => \y_actual_reg_n_0_[7]\,
I4 => \y_actual_reg_n_0_[4]\,
I5 => \y_actual_reg_n_0_[5]\,
O => \top[15]_i_2_n_0\
);
\top_left_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(0),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_left_0[0]_i_1_n_0\
);
\top_left_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(10),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_left_0[10]_i_1_n_0\
);
\top_left_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(11),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_left_0[11]_i_1_n_0\
);
\top_left_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(12),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_left_0[12]_i_1_n_0\
);
\top_left_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(13),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_left_0[13]_i_1_n_0\
);
\top_left_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(14),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_left_0[14]_i_1_n_0\
);
\top_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000700010000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep_n_0\,
O => top_left_0
);
\top_left_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(15),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_left_0[15]_i_2_n_0\
);
\top_left_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(1),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_left_0[1]_i_1_n_0\
);
\top_left_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(2),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_left_0[2]_i_1_n_0\
);
\top_left_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_left_0[3]_i_1_n_0\
);
\top_left_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(4),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_left_0[4]_i_1_n_0\
);
\top_left_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(5),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_left_0[5]_i_1_n_0\
);
\top_left_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(6),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_left_0[6]_i_1_n_0\
);
\top_left_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(7),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_left_0[7]_i_1_n_0\
);
\top_left_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(8),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_left_0[8]_i_1_n_0\
);
\top_left_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(9),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_left_0[9]_i_1_n_0\
);
\top_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[0]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[0]\,
R => '0'
);
\top_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[10]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[10]\,
R => '0'
);
\top_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[11]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[11]\,
R => '0'
);
\top_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[12]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[12]\,
R => '0'
);
\top_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[13]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[13]\,
R => '0'
);
\top_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[14]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[14]\,
R => '0'
);
\top_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[15]_i_2_n_0\,
Q => \top_left_0_reg_n_0_[15]\,
R => '0'
);
\top_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[1]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[1]\,
R => '0'
);
\top_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[2]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[2]\,
R => '0'
);
\top_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[3]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[3]\,
R => '0'
);
\top_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[4]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[4]\,
R => '0'
);
\top_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[5]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[5]\,
R => '0'
);
\top_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[6]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[6]\,
R => '0'
);
\top_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[7]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[7]\,
R => '0'
);
\top_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[8]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[8]\,
R => '0'
);
\top_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[9]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[9]\,
R => '0'
);
\top_left_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[0]\,
O => \top_left_1[0]_i_1_n_0\
);
\top_left_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[10]\,
O => \top_left_1[10]_i_1_n_0\
);
\top_left_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[11]\,
O => \top_left_1[11]_i_1_n_0\
);
\top_left_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[12]\,
O => \top_left_1[12]_i_1_n_0\
);
\top_left_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[13]\,
O => \top_left_1[13]_i_1_n_0\
);
\top_left_1[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(14),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[14]\,
O => \top_left_1[14]_i_1_n_0\
);
\top_left_1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
O => bottom_right_1
);
\top_left_1[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(15),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[15]\,
O => \top_left_1[15]_i_2_n_0\
);
\top_left_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[1]\,
O => \top_left_1[1]_i_1_n_0\
);
\top_left_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[2]\,
O => \top_left_1[2]_i_1_n_0\
);
\top_left_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[3]\,
O => \top_left_1[3]_i_1_n_0\
);
\top_left_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[4]\,
O => \top_left_1[4]_i_1_n_0\
);
\top_left_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[5]\,
O => \top_left_1[5]_i_1_n_0\
);
\top_left_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[6]\,
O => \top_left_1[6]_i_1_n_0\
);
\top_left_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[7]\,
O => \top_left_1[7]_i_1_n_0\
);
\top_left_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[8]\,
O => \top_left_1[8]_i_1_n_0\
);
\top_left_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[9]\,
O => \top_left_1[9]_i_1_n_0\
);
\top_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[0]_i_1_n_0\,
Q => top_left_1(0),
R => '0'
);
\top_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[10]_i_1_n_0\,
Q => top_left_1(10),
R => '0'
);
\top_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[11]_i_1_n_0\,
Q => top_left_1(11),
R => '0'
);
\top_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[12]_i_1_n_0\,
Q => top_left_1(12),
R => '0'
);
\top_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[13]_i_1_n_0\,
Q => top_left_1(13),
R => '0'
);
\top_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[14]_i_1_n_0\,
Q => top_left_1(14),
R => '0'
);
\top_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[15]_i_2_n_0\,
Q => top_left_1(15),
R => '0'
);
\top_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[1]_i_1_n_0\,
Q => top_left_1(1),
R => '0'
);
\top_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[2]_i_1_n_0\,
Q => top_left_1(2),
R => '0'
);
\top_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[3]_i_1_n_0\,
Q => top_left_1(3),
R => '0'
);
\top_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[4]_i_1_n_0\,
Q => top_left_1(4),
R => '0'
);
\top_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[5]_i_1_n_0\,
Q => top_left_1(5),
R => '0'
);
\top_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[6]_i_1_n_0\,
Q => top_left_1(6),
R => '0'
);
\top_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[7]_i_1_n_0\,
Q => top_left_1(7),
R => '0'
);
\top_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[8]_i_1_n_0\,
Q => top_left_1(8),
R => '0'
);
\top_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[9]_i_1_n_0\,
Q => top_left_1(9),
R => '0'
);
\top_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(0),
Q => \top_reg_n_0_[0]\,
R => top
);
\top_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(10),
Q => \top_reg_n_0_[10]\,
R => top
);
\top_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(11),
Q => \top_reg_n_0_[11]\,
R => top
);
\top_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(12),
Q => \top_reg_n_0_[12]\,
R => top
);
\top_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(13),
Q => \top_reg_n_0_[13]\,
R => top
);
\top_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(14),
Q => \top_reg_n_0_[14]\,
R => top
);
\top_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(15),
Q => \top_reg_n_0_[15]\,
R => top
);
\top_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(1),
Q => \top_reg_n_0_[1]\,
R => top
);
\top_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(2),
Q => \top_reg_n_0_[2]\,
R => top
);
\top_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(3),
Q => \top_reg_n_0_[3]\,
R => top
);
\top_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(4),
Q => \top_reg_n_0_[4]\,
R => top
);
\top_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(5),
Q => \top_reg_n_0_[5]\,
R => top
);
\top_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(6),
Q => \top_reg_n_0_[6]\,
R => top
);
\top_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(7),
Q => \top_reg_n_0_[7]\,
R => top
);
\top_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(8),
Q => \top_reg_n_0_[8]\,
R => top
);
\top_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(9),
Q => \top_reg_n_0_[9]\,
R => top
);
\top_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_right_0[0]_i_1_n_0\
);
\top_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(10),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_right_0[10]_i_1_n_0\
);
\top_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(11),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_right_0[11]_i_1_n_0\
);
\top_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(12),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_right_0[12]_i_1_n_0\
);
\top_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(13),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_right_0[13]_i_1_n_0\
);
\top_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(14),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_right_0[14]_i_1_n_0\
);
\top_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0880000080080800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => top_right_0
);
\top_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(15),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_right_0[15]_i_2_n_0\
);
\top_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(1),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_right_0[1]_i_1_n_0\
);
\top_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(2),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_right_0[2]_i_1_n_0\
);
\top_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(3),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_right_0[3]_i_1_n_0\
);
\top_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(4),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_right_0[4]_i_1_n_0\
);
\top_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(5),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_right_0[5]_i_1_n_0\
);
\top_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(6),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_right_0[6]_i_1_n_0\
);
\top_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(7),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_right_0[7]_i_1_n_0\
);
\top_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(8),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_right_0[8]_i_1_n_0\
);
\top_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(9),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_right_0[9]_i_1_n_0\
);
\top_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[0]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[0]\,
R => '0'
);
\top_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[10]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[10]\,
R => '0'
);
\top_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[11]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[11]\,
R => '0'
);
\top_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[12]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[12]\,
R => '0'
);
\top_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[13]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[13]\,
R => '0'
);
\top_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[14]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[14]\,
R => '0'
);
\top_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[15]_i_2_n_0\,
Q => \top_right_0_reg_n_0_[15]\,
R => '0'
);
\top_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[1]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[1]\,
R => '0'
);
\top_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[2]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[2]\,
R => '0'
);
\top_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[3]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[3]\,
R => '0'
);
\top_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[4]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[4]\,
R => '0'
);
\top_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[5]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[5]\,
R => '0'
);
\top_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[6]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[6]\,
R => '0'
);
\top_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[7]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[7]\,
R => '0'
);
\top_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[8]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[8]\,
R => '0'
);
\top_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[9]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[9]\,
R => '0'
);
\top_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[0]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[0]\,
O => \top_right_1[0]_i_1_n_0\
);
\top_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[10]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[10]\,
O => \top_right_1[10]_i_1_n_0\
);
\top_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[11]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[11]\,
O => \top_right_1[11]_i_1_n_0\
);
\top_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[12]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[12]\,
O => \top_right_1[12]_i_1_n_0\
);
\top_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[13]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[13]\,
O => \top_right_1[13]_i_1_n_0\
);
\top_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[14]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[14]\,
O => \top_right_1[14]_i_1_n_0\
);
\top_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[15]\,
O => \top_right_1[15]_i_1_n_0\
);
\top_right_1[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => cycle(3),
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \top_right_1[15]_i_2_n_0\
);
\top_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[1]\,
O => \top_right_1[1]_i_1_n_0\
);
\top_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[2]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[2]\,
O => \top_right_1[2]_i_1_n_0\
);
\top_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[3]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[3]\,
O => \top_right_1[3]_i_1_n_0\
);
\top_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[4]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[4]\,
O => \top_right_1[4]_i_1_n_0\
);
\top_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[5]\,
O => \top_right_1[5]_i_1_n_0\
);
\top_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[6]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[6]\,
O => \top_right_1[6]_i_1_n_0\
);
\top_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[7]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[7]\,
O => \top_right_1[7]_i_1_n_0\
);
\top_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[8]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[8]\,
O => \top_right_1[8]_i_1_n_0\
);
\top_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[9]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[9]\,
O => \top_right_1[9]_i_1_n_0\
);
\top_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[0]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[0]\,
R => '0'
);
\top_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[10]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[10]\,
R => '0'
);
\top_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[11]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[11]\,
R => '0'
);
\top_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[12]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[12]\,
R => '0'
);
\top_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[13]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[13]\,
R => '0'
);
\top_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[14]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[14]\,
R => '0'
);
\top_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[15]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[15]\,
R => '0'
);
\top_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[1]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[1]\,
R => '0'
);
\top_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[2]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[2]\,
R => '0'
);
\top_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[3]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[3]\,
R => '0'
);
\top_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[4]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[4]\,
R => '0'
);
\top_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[5]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[5]\,
R => '0'
);
\top_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[6]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[6]\,
R => '0'
);
\top_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[7]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[7]\,
R => '0'
);
\top_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[8]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[8]\,
R => '0'
);
\top_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[9]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[9]\,
R => '0'
);
\value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(0),
Q => \value_reg_n_0_[0]\,
R => '0'
);
\value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(1),
Q => \value_reg_n_0_[1]\,
R => '0'
);
\value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(2),
Q => \value_reg_n_0_[2]\,
R => '0'
);
\value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(3),
Q => \value_reg_n_0_[3]\,
R => '0'
);
\value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(4),
Q => \value_reg_n_0_[4]\,
R => '0'
);
\value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(5),
Q => \value_reg_n_0_[5]\,
R => '0'
);
\value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(6),
Q => \value_reg_n_0_[6]\,
R => '0'
);
\value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(7),
Q => \value_reg_n_0_[7]\,
R => '0'
);
wen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAAA2AAAA"
)
port map (
I0 => wen_reg_n_0,
I1 => wen_i_2_n_0,
I2 => \cycle_reg[0]_rep_n_0\,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => wen_i_1_n_0
);
wen_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => active,
I1 => rst,
O => wen_i_2_n_0
);
wen_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => wen_i_1_n_0,
Q => wen_reg_n_0,
R => '0'
);
\x0[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3B01FFC53A00FEC4"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => data2(0),
I4 => \x_reg_n_0_[0]\,
I5 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_2_n_0\
);
\x0[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(0),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_3_n_0\
);
\x0[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCEECCEEEEEECCFC"
)
port map (
I0 => data2(1),
I1 => \x0[1]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_6\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_2_n_0\
);
\x0[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(1),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_6\,
O => \x0[1]_i_3_n_0\
);
\x0[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"60600060"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[0]\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_4_n_0\
);
\x0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBFBBBFFBBBBBB"
)
port map (
I0 => \x0[2]_i_2_n_0\,
I1 => \x0[2]_i_3_n_0\,
I2 => data2(2),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry_n_5\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[2]_i_1_n_0\
);
\x0[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88AA22A0880022A0"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x0[2]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(2),
O => \x0[2]_i_2_n_0\
);
\x0[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FF3F3F377777777"
)
port map (
I0 => data2(2),
I1 => \x0[2]_i_5_n_0\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
I5 => \x1[6]_i_8_n_0\,
O => \x0[2]_i_3_n_0\
);
\x0[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[2]_i_4_n_0\
);
\x0[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
O => \x0[2]_i_5_n_0\
);
\x0[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x0[3]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[3]_i_3_n_0\,
I3 => cycle(3),
I4 => \x0[3]_i_4_n_0\,
O => \x0[3]_i_1_n_0\
);
\x0[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"660FFF00660FFFFF"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_5_n_0\,
I2 => data2(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_2_n_0\
);
\x0[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F9F090000900"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(3),
O => \x0[3]_i_3_n_0\
);
\x0[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(3),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_4_n_0\
);
\x0[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_5_n_0\
);
\x0[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_6_n_0\
);
\x0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[4]_i_2_n_0\,
I1 => \x0[4]_i_3_n_0\,
I2 => data2(4),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[4]_i_1_n_0\
);
\x0[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x0[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[4]_i_2_n_0\
);
\x0[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"008A0080A08AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data2(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x0[4]_i_5_n_0\,
O => \x0[4]_i_3_n_0\
);
\x0[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
O => \x0[4]_i_4_n_0\
);
\x0[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"95555555"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
O => \x0[4]_i_5_n_0\
);
\x0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[5]_i_2_n_0\,
I1 => \x0[5]_i_3_n_0\,
I2 => data2(5),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_6\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[5]_i_1_n_0\
);
\x0[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(5),
I1 => \x_reg_n_0_[5]\,
I2 => \x0[8]_i_7_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[5]_i_2_n_0\
);
\x0[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A80008AAAAAAAA"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \plusOp_inferred__0/i__carry__0_n_6\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => data2(5),
I5 => \x0[5]_i_4_n_0\,
O => \x0[5]_i_3_n_0\
);
\x0[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x0[5]_i_5_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(0),
O => \x0[5]_i_4_n_0\
);
\x0[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x0[5]_i_5_n_0\
);
\x0[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0507"
)
port map (
I0 => \x0[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(3),
I3 => \x0[6]_i_3_n_0\,
I4 => \x0[6]_i_4_n_0\,
O => \x0[6]_i_1_n_0\
);
\x0[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0707077077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data2(6),
I2 => \x_reg_n_0_[6]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x0[8]_i_5_n_0\,
O => \x0[6]_i_2_n_0\
);
\x0[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6600FF0F66FFFF0F"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x0[6]_i_5_n_0\,
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(6),
O => \x0[6]_i_3_n_0\
);
\x0[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C0C0C0C0C0C088"
)
port map (
I0 => data2(6),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[6]_i_4_n_0\
);
\x0[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x0[6]_i_5_n_0\
);
\x0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF020000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x0[7]_i_2_n_0\,
I3 => \x0[7]_i_3_n_0\,
I4 => \x0[7]_i_4_n_0\,
I5 => \x0[7]_i_5_n_0\,
O => \x0[7]_i_1_n_0\
);
\x0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[8]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \x_reg_n_0_[6]\,
O => \x0[7]_i_2_n_0\
);
\x0[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99F000FF99F00000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[7]_i_6_n_0\,
I2 => data2(7),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_3_n_0\
);
\x0[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
O => \x0[7]_i_4_n_0\
);
\x0[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x0[7]_i_7_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data2(7),
I4 => cycle(3),
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_5_n_0\
);
\x0[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x0[6]_i_5_n_0\,
I1 => \x_reg_n_0_[6]\,
O => \x0[7]_i_6_n_0\
);
\x0[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x_reg_n_0_[6]\,
I3 => \x_reg_n_0_[5]\,
I4 => \x0[8]_i_7_n_0\,
I5 => \x_reg_n_0_[7]\,
O => \x0[7]_i_7_n_0\
);
\x0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0FFF1F1F1"
)
port map (
I0 => \x0[8]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[8]_i_3_n_0\,
I3 => \x0[8]_i_4_n_0\,
I4 => \x0[8]_i_5_n_0\,
I5 => cycle(3),
O => \x0[8]_i_1_n_0\
);
\x0[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"990FFF00990FFFFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x0[8]_i_6_n_0\,
I2 => data2(8),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__1_n_7\,
O => \x0[8]_i_2_n_0\
);
\x0[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888B888B888B8C0"
)
port map (
I0 => \plusOp_inferred__0/i__carry__1_n_7\,
I1 => cycle(3),
I2 => data2(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[8]_i_3_n_0\
);
\x0[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x0[8]_i_4_n_0\
);
\x0[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x0[8]_i_5_n_0\
);
\x0[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x0[6]_i_5_n_0\,
O => \x0[8]_i_6_n_0\
);
\x0[8]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[0]\,
I4 => \x_reg_n_0_[3]\,
O => \x0[8]_i_7_n_0\
);
\x0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"77FE000000000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => active,
I5 => rst,
O => \x0[9]_i_1_n_0\
);
\x0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0101"
)
port map (
I0 => \x0[9]_i_3_n_0\,
I1 => cycle(3),
I2 => cycle(2),
I3 => \x0[9]_i_4_n_0\,
I4 => \x0[9]_i_5_n_0\,
O => \x0[9]_i_2_n_0\
);
\x0[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF03AFF3A003A0F3"
)
port map (
I0 => \x0[9]_i_6_n_0\,
I1 => \plusOp_inferred__0/i__carry__1_n_6\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => data2(9),
I5 => \x0[9]_i_7_n_0\,
O => \x0[9]_i_3_n_0\
);
\x0[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C0C0C0C0C44"
)
port map (
I0 => data2(9),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__1_n_6\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \x0[9]_i_4_n_0\
);
\x0[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5CCC0000"
)
port map (
I0 => \x0[9]_i_7_n_0\,
I1 => data2(9),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => \x0[9]_i_5_n_0\
);
\x0[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"55559555"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x_reg_n_0_[6]\,
I4 => \x0[6]_i_5_n_0\,
O => \x0[9]_i_6_n_0\
);
\x0[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x_reg_n_0_[6]\,
O => \x0[9]_i_7_n_0\
);
\x0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[0]_i_1_n_0\,
Q => data1(0),
R => '0'
);
\x0_reg[0]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[0]_i_2_n_0\,
I1 => \x0[0]_i_3_n_0\,
O => \x0_reg[0]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[1]_i_1_n_0\,
Q => data1(1),
R => '0'
);
\x0_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[1]_i_2_n_0\,
I1 => \x0[1]_i_3_n_0\,
O => \x0_reg[1]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[2]_i_1_n_0\,
Q => data1(2),
R => '0'
);
\x0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[3]_i_1_n_0\,
Q => data1(3),
R => '0'
);
\x0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[4]_i_1_n_0\,
Q => data1(4),
R => '0'
);
\x0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[5]_i_1_n_0\,
Q => data1(5),
R => '0'
);
\x0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[6]_i_1_n_0\,
Q => data1(6),
R => '0'
);
\x0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[7]_i_1_n_0\,
Q => data1(7),
R => '0'
);
\x0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[8]_i_1_n_0\,
Q => data1(8),
R => '0'
);
\x0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[9]_i_2_n_0\,
Q => data1(9),
R => '0'
);
\x1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF01FF4EFE00B100"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \x_reg_n_0_[0]\,
I4 => cycle(3),
I5 => data1(0),
O => \x1[0]_i_1_n_0\
);
\x1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFEFAAA955565010"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => data1(1),
I5 => \x_reg_n_0_[1]\,
O => \x1[1]_i_1_n_0\
);
\x1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEAEAEAEFEAE"
)
port map (
I0 => \x1[2]_i_2_n_0\,
I1 => \x1[2]_i_3_n_0\,
I2 => cycle(3),
I3 => \x_reg_n_0_[2]\,
I4 => \x1[5]_i_3_n_0\,
I5 => data1(2),
O => \x1[2]_i_1_n_0\
);
\x1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A2A288880202888"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x_reg_n_0_[2]\,
I2 => cycle(0),
I3 => \x_reg_n_0_[1]\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \x1[2]_i_2_n_0\
);
\x1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3CAAAAAA00000000"
)
port map (
I0 => data1(2),
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[2]_i_3_n_0\
);
\x1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[3]_i_2_n_0\,
I1 => \x1[3]_i_3_n_0\,
I2 => data1(3),
I3 => cycle(3),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[3]_i_1_n_0\
);
\x1[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0770707077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data1(3),
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x0[8]_i_5_n_0\,
O => \x1[3]_i_2_n_0\
);
\x1[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[3]_i_4_n_0\,
O => \x1[3]_i_3_n_0\
);
\x1[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[2]\,
O => \x1[3]_i_4_n_0\
);
\x1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[4]_i_2_n_0\,
I1 => \x1[4]_i_3_n_0\,
I2 => data1(4),
I3 => cycle(3),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[4]_i_1_n_0\
);
\x1[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data1(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x1[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[4]_i_2_n_0\
);
\x1[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[4]_i_5_n_0\,
O => \x1[4]_i_3_n_0\
);
\x1[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_4_n_0\
);
\x1[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_5_n_0\
);
\x1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => \x1[5]_i_2_n_0\,
I1 => data1(5),
I2 => \x1[5]_i_3_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => cycle(3),
O => \x1[5]_i_1_n_0\
);
\x1[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDFDCDCDFDFDFDCD"
)
port map (
I0 => \x1[5]_i_4_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[6]_i_8_n_0\,
I4 => data1(5),
I5 => \x1[5]_i_5_n_0\,
O => \x1[5]_i_2_n_0\
);
\x1[5]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
O => \x1[5]_i_3_n_0\
);
\x1[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0530FA3FF5300A3F"
)
port map (
I0 => \x1[6]_i_7_n_0\,
I1 => data1(5),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[5]\,
I5 => \left[15]_i_3_n_0\,
O => \x1[5]_i_4_n_0\
);
\x1[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555666"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[4]\,
O => \x1[5]_i_5_n_0\
);
\x1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[6]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[6]_i_4_n_0\,
O => \x1[6]_i_1_n_0\
);
\x1[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05050CFC05F5F"
)
port map (
I0 => data1(6),
I1 => \x1[6]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[6]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[6]\,
O => \x1[6]_i_2_n_0\
);
\x1[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A900FF00A9000000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x1[6]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \x1[6]_i_8_n_0\,
I5 => data1(6),
O => \x1[6]_i_3_n_0\
);
\x1[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(6),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[6]\,
O => \x1[6]_i_4_n_0\
);
\x1[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_5_n_0\
);
\x1[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555666"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_6_n_0\
);
\x1[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x1[6]_i_7_n_0\
);
\x1[6]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
O => \x1[6]_i_8_n_0\
);
\x1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[7]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[7]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[7]_i_4_n_0\,
O => \x1[7]_i_1_n_0\
);
\x1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"303F5050CFC05F5F"
)
port map (
I0 => data1(7),
I1 => \x1[7]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[9]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[7]\,
O => \x1[7]_i_2_n_0\
);
\x1[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F0F090000000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x1[9]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \x1[7]_i_3_n_0\
);
\x1[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(7),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[7]_i_4_n_0\
);
\x1[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[4]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[7]_i_5_n_0\
);
\x1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => \x1[8]_i_2_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[8]_i_3_n_0\,
O => \x1[8]_i_1_n_0\
);
\x1[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA300A3F0A30FA3F"
)
port map (
I0 => \x1[8]_i_4_n_0\,
I1 => data1(8),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[8]\,
I5 => \left[15]_i_2_n_0\,
O => \x1[8]_i_2_n_0\
);
\x1[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[8]_i_5_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(8),
I4 => cycle(3),
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_3_n_0\
);
\x1[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555556"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x1[6]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[8]_i_4_n_0\
);
\x1[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000002"
)
port map (
I0 => \x1[8]_i_6_n_0\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[6]_i_7_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_5_n_0\
);
\x1[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x1[8]_i_6_n_0\
);
\x1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008880880880"
)
port map (
I0 => active,
I1 => rst,
I2 => cycle(0),
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => x1
);
\x1[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000047"
)
port map (
I0 => \x1[9]_i_3_n_0\,
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x1[9]_i_4_n_0\,
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \x1[9]_i_5_n_0\,
O => \x1[9]_i_2_n_0\
);
\x1[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C335555"
)
port map (
I0 => data1(9),
I1 => \x_reg_n_0_[9]\,
I2 => \x_reg_n_0_[8]\,
I3 => \left[15]_i_2_n_0\,
I4 => cycle(0),
O => \x1[9]_i_3_n_0\
);
\x1[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0100FEFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[9]_i_6_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[9]\,
O => \x1[9]_i_4_n_0\
);
\x1[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[9]_i_8_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(9),
I4 => cycle(3),
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_5_n_0\
);
\x1[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFE"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x_reg_n_0_[4]\,
O => \x1[9]_i_6_n_0\
);
\x1[9]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \x1[9]_i_7_n_0\
);
\x1[9]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x1[9]_i_6_n_0\,
I3 => \x_reg_n_0_[7]\,
I4 => \x_reg_n_0_[8]\,
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_8_n_0\
);
\x1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[0]_i_1_n_0\,
Q => data2(0),
R => '0'
);
\x1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[1]_i_1_n_0\,
Q => data2(1),
R => '0'
);
\x1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[2]_i_1_n_0\,
Q => data2(2),
R => '0'
);
\x1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[3]_i_1_n_0\,
Q => data2(3),
R => '0'
);
\x1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[4]_i_1_n_0\,
Q => data2(4),
R => '0'
);
\x1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[5]_i_1_n_0\,
Q => data2(5),
R => '0'
);
\x1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[6]_i_1_n_0\,
Q => data2(6),
R => '0'
);
\x1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[7]_i_1_n_0\,
Q => data2(7),
R => '0'
);
\x1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[8]_i_1_n_0\,
Q => data2(8),
R => '0'
);
\x1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[9]_i_2_n_0\,
Q => data2(9),
R => '0'
);
\x[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => x
);
\x_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(0),
Q => \x_reg_n_0_[0]\,
R => '0'
);
\x_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(1),
Q => \x_reg_n_0_[1]\,
R => '0'
);
\x_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(2),
Q => \x_reg_n_0_[2]\,
R => '0'
);
\x_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(3),
Q => \x_reg_n_0_[3]\,
R => '0'
);
\x_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(4),
Q => \x_reg_n_0_[4]\,
R => '0'
);
\x_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(5),
Q => \x_reg_n_0_[5]\,
R => '0'
);
\x_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(6),
Q => \x_reg_n_0_[6]\,
R => '0'
);
\x_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(7),
Q => \x_reg_n_0_[7]\,
R => '0'
);
\x_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(8),
Q => \x_reg_n_0_[8]\,
R => '0'
);
\x_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(9),
Q => \x_reg_n_0_[9]\,
R => '0'
);
\y1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y1[2]_i_1_n_0\
);
\y1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
I3 => \y_actual_reg_n_0_[3]\,
O => \y1[3]_i_1_n_0\
);
\y1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[0]_i_1_n_0\,
Q => \y1_reg_n_0_[0]\,
R => '0'
);
\y1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[1]_i_1_n_0\,
Q => \y1_reg_n_0_[1]\,
R => '0'
);
\y1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[2]_i_1_n_0\,
Q => \y1_reg_n_0_[2]\,
R => '0'
);
\y1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[3]_i_1_n_0\,
Q => \y1_reg_n_0_[3]\,
R => '0'
);
\y2[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
O => \y2[1]_i_1_n_0\
);
\y2[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y2[2]_i_1_n_0\
);
\y2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y2[3]_i_1_n_0\
);
\y2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y_actual_reg_n_0_[0]\,
Q => \y2_reg_n_0_[0]\,
R => '0'
);
\y2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[1]_i_1_n_0\,
Q => \y2_reg_n_0_[1]\,
R => '0'
);
\y2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[2]_i_1_n_0\,
Q => \y2_reg_n_0_[2]\,
R => '0'
);
\y2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[3]_i_1_n_0\,
Q => \y2_reg_n_0_[3]\,
R => '0'
);
\y3[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y3[1]_i_1_n_0\
);
\y3[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"87"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y3[2]_i_1_n_0\
);
\y3[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y3[3]_i_1_n_0\
);
\y3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y5[0]_i_1_n_0\,
Q => \y3_reg_n_0_[0]\,
R => '0'
);
\y3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[1]_i_1_n_0\,
Q => \y3_reg_n_0_[1]\,
R => '0'
);
\y3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[2]_i_1_n_0\,
Q => \y3_reg_n_0_[2]\,
R => '0'
);
\y3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[3]_i_1_n_0\,
Q => \y3_reg_n_0_[3]\,
R => '0'
);
\y4[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
O => \y4[2]_i_1_n_0\
);
\y4[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y4[3]_i_1_n_0\
);
\y4_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[0]\,
Q => data2(10),
R => '0'
);
\y4_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[1]\,
Q => data2(11),
R => '0'
);
\y4_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[2]_i_1_n_0\,
Q => data2(12),
R => '0'
);
\y4_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[3]_i_1_n_0\,
Q => data2(13),
R => '0'
);
\y5[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
O => \y5[0]_i_1_n_0\
);
\y5[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[0]\,
O => \y5[1]_i_1_n_0\
);
\y5[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y5[2]_i_1_n_0\
);
\y5[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A955"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y5[3]_i_1_n_0\
);
\y5_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[0]_i_1_n_0\,
Q => data1(10),
R => '0'
);
\y5_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[1]_i_1_n_0\,
Q => data1(11),
R => '0'
);
\y5_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[2]_i_1_n_0\,
Q => data1(12),
R => '0'
);
\y5_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[3]_i_1_n_0\,
Q => data1(13),
R => '0'
);
\y6[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y6[2]_i_1_n_0\
);
\y6[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y6[3]_i_1_n_0\
);
\y6_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y_actual_reg_n_0_[0]\,
Q => \y6_reg_n_0_[0]\,
R => '0'
);
\y6_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y2[1]_i_1_n_0\,
Q => \y6_reg_n_0_[1]\,
R => '0'
);
\y6_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[2]_i_1_n_0\,
Q => \y6_reg_n_0_[2]\,
R => '0'
);
\y6_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[3]_i_1_n_0\,
Q => \y6_reg_n_0_[3]\,
R => '0'
);
\y7[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y7[2]_i_1_n_0\
);
\y7[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y7[3]_i_1_n_0\
);
\y7_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y5[0]_i_1_n_0\,
Q => y7(0),
R => '0'
);
\y7_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y3[1]_i_1_n_0\,
Q => y7(1),
R => '0'
);
\y7_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[2]_i_1_n_0\,
Q => y7(2),
R => '0'
);
\y7_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[3]_i_1_n_0\,
Q => y7(3),
R => '0'
);
\y8[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
O => \y8[3]_i_1_n_0\
);
\y8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[0]\,
Q => y8(0),
R => '0'
);
\y8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[1]\,
Q => y8(1),
R => '0'
);
\y8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[2]\,
Q => y8(2),
R => '0'
);
\y8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y8[3]_i_1_n_0\,
Q => y8(3),
R => '0'
);
\y9[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y9[3]_i_1_n_0\
);
\y9_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[0]_i_1_n_0\,
Q => data5(10),
R => '0'
);
\y9_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[1]_i_1_n_0\,
Q => data5(11),
R => '0'
);
\y9_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y1[2]_i_1_n_0\,
Q => data5(12),
R => '0'
);
\y9_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y9[3]_i_1_n_0\,
Q => data5(13),
R => '0'
);
\y_actual_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(0),
Q => \y_actual_reg_n_0_[0]\,
R => '0'
);
\y_actual_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(1),
Q => \y_actual_reg_n_0_[1]\,
R => '0'
);
\y_actual_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(2),
Q => \y_actual_reg_n_0_[2]\,
R => '0'
);
\y_actual_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(3),
Q => \y_actual_reg_n_0_[3]\,
R => '0'
);
\y_actual_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(4),
Q => \y_actual_reg_n_0_[4]\,
R => '0'
);
\y_actual_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(5),
Q => \y_actual_reg_n_0_[5]\,
R => '0'
);
\y_actual_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(6),
Q => \y_actual_reg_n_0_[6]\,
R => '0'
);
\y_actual_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(7),
Q => \y_actual_reg_n_0_[7]\,
R => '0'
);
\y_actual_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(8),
Q => \y_actual_reg_n_0_[8]\,
R => '0'
);
\y_actual_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(9),
Q => \y_actual_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_hessian_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_1_0 : entity is "system_vga_hessian_1_0,vga_hessian,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_1_0 : entity is "vga_hessian,Vivado 2016.4";
end system_vga_hessian_1_0;
architecture STRUCTURE of system_vga_hessian_1_0 is
begin
U0: entity work.system_vga_hessian_1_0_vga_hessian
port map (
active => active,
clk_x16 => clk_x16,
g_in(7 downto 0) => g_in(7 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
rst => rst,
x_addr(9 downto 0) => x_addr(9 downto 0),
y_addr(9 downto 0) => y_addr(9 downto 0)
);
end STRUCTURE;
| mit | f01a003a0ad371074187807558094103 | 0.546382 | 2.727816 | false | false | false | false |
loa-org/loa-hdl | modules/ds18b20/tb/ds18b20_tb.vhd | 1 | 2,728 | -------------------------------------------------------------------------------
-- Title : DS18b20 Reader Testbench
-------------------------------------------------------------------------------
-- Note: Sorry, only poor visual wavwform inspection for now.
--
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-14
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.onewire_pkg.all;
use work.onewire_cfg_pkg.all;
use work.ds18b20_pkg.all;
-------------------------------------------------------------------------------
entity ds18b20_tb is
end ds18b20_tb;
-------------------------------------------------------------------------------
architecture tb of ds18b20_tb is
component ds18b20
port (
ow_out : in onewire_out_type;
ow_in : out onewire_in_type;
ds18b20_in : in ds18b20_in_type;
ds18b20_out : out ds18b20_out_type;
clk : in std_logic);
end component;
-- component ports
signal ow_out : onewire_out_type := (d => (others => '0'), busy => '0', err => '0');
signal ow_in : onewire_in_type;
signal ds18b20_in : ds18b20_in_type := (refresh => '0');
signal ds18b20_out : ds18b20_out_type;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : ds18b20
port map (
ow_out => ow_out,
ow_in => ow_in,
ds18b20_in => ds18b20_in,
ds18b20_out => ds18b20_out,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk = '1';
ds18b20_in.refresh <= '1';
wait until Clk = '1';
ds18b20_in.refresh <= '0';
wait until Clk = '1';
ow_out.busy <= '1';
wait for 100 ns;
ow_out.busy <= '0';
wait until Clk = '1';
ow_out.busy <= '1';
wait for 100 ns;
ow_out.busy <= '0';
wait until Clk = '1';
ow_out.busy <= '1';
wait for 100 ns;
ow_out.busy <= '0';
wait until Clk = '1';
ow_out.busy <= '1';
wait for 100 ns;
ow_out.busy <= '0';
wait until Clk = '1';
wait for 20 ms;
end process WaveGen_Proc;
process
begin
wait for 1 us;
ow_out.d <= x"ff";
end process;
end tb;
| bsd-3-clause | 3ed60bc59bfc23dcc43a7aeeeb4490cb | 0.46151 | 3.647059 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl | 1 | 589,114 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:15:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl
-- Design : system_auto_us_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_mi_word_q : out STD_LOGIC;
first_word : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
wrap_buffer_available : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
use_wrap_buffer_reg_0 : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : out STD_LOGIC;
\current_word_1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_1\ : out STD_LOGIC;
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
pop_mi_data : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
\current_word_1_reg[2]_1\ : in STD_LOGIC;
\current_word_1_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
signal M_AXI_RDATA_I : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \USE_RTL_ADDR.addr_q[4]_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_7_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal \^first_word_reg_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_3_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_2_n_0 : STD_LOGIC;
signal \^use_wrap_buffer_reg_0\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal \wrap_buffer_available_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_buffer_available_i_2__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_5\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_6\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_7\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair38";
begin
\current_word_1_reg[2]_0\(2 downto 0) <= \^current_word_1_reg[2]_0\(2 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
first_word_reg_0(2 downto 0) <= \^first_word_reg_0\(2 downto 0);
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
use_wrap_buffer_reg_0 <= \^use_wrap_buffer_reg_0\;
wrap_buffer_available <= \^wrap_buffer_available\;
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(0),
Q => M_AXI_RDATA_I(0),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(10),
Q => M_AXI_RDATA_I(10),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(11),
Q => M_AXI_RDATA_I(11),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(12),
Q => M_AXI_RDATA_I(12),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(13),
Q => M_AXI_RDATA_I(13),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(14),
Q => M_AXI_RDATA_I(14),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(15),
Q => M_AXI_RDATA_I(15),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(16),
Q => M_AXI_RDATA_I(16),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(17),
Q => M_AXI_RDATA_I(17),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(18),
Q => M_AXI_RDATA_I(18),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(19),
Q => M_AXI_RDATA_I(19),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(1),
Q => M_AXI_RDATA_I(1),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(20),
Q => M_AXI_RDATA_I(20),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(21),
Q => M_AXI_RDATA_I(21),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(22),
Q => M_AXI_RDATA_I(22),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(23),
Q => M_AXI_RDATA_I(23),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(24),
Q => M_AXI_RDATA_I(24),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(25),
Q => M_AXI_RDATA_I(25),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(26),
Q => M_AXI_RDATA_I(26),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(27),
Q => M_AXI_RDATA_I(27),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(28),
Q => M_AXI_RDATA_I(28),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(29),
Q => M_AXI_RDATA_I(29),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(2),
Q => M_AXI_RDATA_I(2),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(30),
Q => M_AXI_RDATA_I(30),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(31),
Q => M_AXI_RDATA_I(31),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(32),
Q => M_AXI_RDATA_I(32),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(33),
Q => M_AXI_RDATA_I(33),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(34),
Q => M_AXI_RDATA_I(34),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(35),
Q => M_AXI_RDATA_I(35),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(36),
Q => M_AXI_RDATA_I(36),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(37),
Q => M_AXI_RDATA_I(37),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(38),
Q => M_AXI_RDATA_I(38),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(39),
Q => M_AXI_RDATA_I(39),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(3),
Q => M_AXI_RDATA_I(3),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(40),
Q => M_AXI_RDATA_I(40),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(41),
Q => M_AXI_RDATA_I(41),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(42),
Q => M_AXI_RDATA_I(42),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(43),
Q => M_AXI_RDATA_I(43),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(44),
Q => M_AXI_RDATA_I(44),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(45),
Q => M_AXI_RDATA_I(45),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(46),
Q => M_AXI_RDATA_I(46),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(47),
Q => M_AXI_RDATA_I(47),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(48),
Q => M_AXI_RDATA_I(48),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(49),
Q => M_AXI_RDATA_I(49),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(4),
Q => M_AXI_RDATA_I(4),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(50),
Q => M_AXI_RDATA_I(50),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(51),
Q => M_AXI_RDATA_I(51),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(52),
Q => M_AXI_RDATA_I(52),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(53),
Q => M_AXI_RDATA_I(53),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(54),
Q => M_AXI_RDATA_I(54),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(55),
Q => M_AXI_RDATA_I(55),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(56),
Q => M_AXI_RDATA_I(56),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(57),
Q => M_AXI_RDATA_I(57),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(58),
Q => M_AXI_RDATA_I(58),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(59),
Q => M_AXI_RDATA_I(59),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(5),
Q => M_AXI_RDATA_I(5),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(60),
Q => M_AXI_RDATA_I(60),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(61),
Q => M_AXI_RDATA_I(61),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(62),
Q => M_AXI_RDATA_I(62),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(63),
Q => M_AXI_RDATA_I(63),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(6),
Q => M_AXI_RDATA_I(6),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(7),
Q => M_AXI_RDATA_I(7),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(8),
Q => M_AXI_RDATA_I(8),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(9),
Q => M_AXI_RDATA_I(9),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => s_axi_rlast_INST_0_i_6_n_0,
I2 => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\,
I3 => s_axi_rlast_INST_0_i_5_n_0,
I4 => \USE_RTL_ADDR.addr_q[4]_i_6_n_0\,
I5 => \USE_RTL_ADDR.addr_q[4]_i_7_n_0\,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
\USE_RTL_ADDR.addr_q[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_6_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \USE_RTL_ADDR.addr_q[4]_i_7_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => Q(66),
Q => \^first_mi_word_q\,
S => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFA051111FA05"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => s_axi_rlast_INST_0_i_6_n_0,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => s_axi_rlast_INST_0_i_6_n_0,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1DE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I3 => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050500030"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => s_axi_rlast_INST_0_i_6_n_0,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => s_axi_aresetn
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \^first_word_reg_0\(0),
R => s_axi_aresetn
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \^first_word_reg_0\(1),
R => s_axi_aresetn
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \^first_word_reg_0\(2),
R => s_axi_aresetn
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^s_axi_rlast\,
Q => \^first_word\,
S => s_axi_aresetn
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F2000000FFFFFFFF"
)
port map (
I0 => \^s_axi_rlast\,
I1 => \^use_wrap_buffer\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I3 => s_axi_rready,
I4 => rd_cmd_valid,
I5 => mr_rvalid,
O => \m_payload_i_reg[0]\(0)
);
\pre_next_word_1[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^current_word_1_reg[2]_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10),
O => \pre_next_word_1_reg[2]_0\
);
\pre_next_word_1[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[2]_0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(9),
O => \pre_next_word_1_reg[2]_1\
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^current_word_1_reg[2]_0\(0),
R => s_axi_aresetn
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^current_word_1_reg[2]_0\(1),
R => s_axi_aresetn
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => \^current_word_1_reg[2]_0\(2),
R => s_axi_aresetn
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(64),
Q => rresp_wrap_buffer(0),
R => s_axi_aresetn
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(65),
Q => rresp_wrap_buffer(1),
R => s_axi_aresetn
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(0),
I1 => M_AXI_RDATA_I(32),
I2 => \^use_wrap_buffer\,
I3 => Q(0),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(32),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(10),
I1 => M_AXI_RDATA_I(42),
I2 => \^use_wrap_buffer\,
I3 => Q(10),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(42),
O => s_axi_rdata(10)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(11),
I1 => M_AXI_RDATA_I(43),
I2 => \^use_wrap_buffer\,
I3 => Q(11),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(43),
O => s_axi_rdata(11)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(12),
I1 => M_AXI_RDATA_I(44),
I2 => \^use_wrap_buffer\,
I3 => Q(12),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(44),
O => s_axi_rdata(12)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(13),
I1 => M_AXI_RDATA_I(45),
I2 => \^use_wrap_buffer\,
I3 => Q(13),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(45),
O => s_axi_rdata(13)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(14),
I1 => M_AXI_RDATA_I(46),
I2 => \^use_wrap_buffer\,
I3 => Q(14),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(46),
O => s_axi_rdata(14)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(15),
I1 => M_AXI_RDATA_I(47),
I2 => \^use_wrap_buffer\,
I3 => Q(15),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(47),
O => s_axi_rdata(15)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(16),
I1 => M_AXI_RDATA_I(48),
I2 => \^use_wrap_buffer\,
I3 => Q(16),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(48),
O => s_axi_rdata(16)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(17),
I1 => M_AXI_RDATA_I(49),
I2 => \^use_wrap_buffer\,
I3 => Q(17),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(49),
O => s_axi_rdata(17)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(18),
I1 => M_AXI_RDATA_I(50),
I2 => \^use_wrap_buffer\,
I3 => Q(18),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(50),
O => s_axi_rdata(18)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(19),
I1 => M_AXI_RDATA_I(51),
I2 => \^use_wrap_buffer\,
I3 => Q(19),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(51),
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(1),
I1 => M_AXI_RDATA_I(33),
I2 => \^use_wrap_buffer\,
I3 => Q(1),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(33),
O => s_axi_rdata(1)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(20),
I1 => M_AXI_RDATA_I(52),
I2 => \^use_wrap_buffer\,
I3 => Q(20),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(52),
O => s_axi_rdata(20)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(21),
I1 => M_AXI_RDATA_I(53),
I2 => \^use_wrap_buffer\,
I3 => Q(21),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(53),
O => s_axi_rdata(21)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(22),
I1 => M_AXI_RDATA_I(54),
I2 => \^use_wrap_buffer\,
I3 => Q(22),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(54),
O => s_axi_rdata(22)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(23),
I1 => M_AXI_RDATA_I(55),
I2 => \^use_wrap_buffer\,
I3 => Q(23),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(55),
O => s_axi_rdata(23)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(24),
I1 => M_AXI_RDATA_I(56),
I2 => \^use_wrap_buffer\,
I3 => Q(24),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(56),
O => s_axi_rdata(24)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(25),
I1 => M_AXI_RDATA_I(57),
I2 => \^use_wrap_buffer\,
I3 => Q(25),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(57),
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(26),
I1 => M_AXI_RDATA_I(58),
I2 => \^use_wrap_buffer\,
I3 => Q(26),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(58),
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(27),
I1 => M_AXI_RDATA_I(59),
I2 => \^use_wrap_buffer\,
I3 => Q(27),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(59),
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(28),
I1 => M_AXI_RDATA_I(60),
I2 => \^use_wrap_buffer\,
I3 => Q(28),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(60),
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(29),
I1 => M_AXI_RDATA_I(61),
I2 => \^use_wrap_buffer\,
I3 => Q(29),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(61),
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(2),
I1 => M_AXI_RDATA_I(34),
I2 => \^use_wrap_buffer\,
I3 => Q(2),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(34),
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(30),
I1 => M_AXI_RDATA_I(62),
I2 => \^use_wrap_buffer\,
I3 => Q(30),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(62),
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(31),
I1 => M_AXI_RDATA_I(63),
I2 => \^use_wrap_buffer\,
I3 => Q(31),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(63),
O => s_axi_rdata(31)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(3),
I1 => M_AXI_RDATA_I(35),
I2 => \^use_wrap_buffer\,
I3 => Q(3),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(35),
O => s_axi_rdata(3)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(4),
I1 => M_AXI_RDATA_I(36),
I2 => \^use_wrap_buffer\,
I3 => Q(4),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(36),
O => s_axi_rdata(4)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(5),
I1 => M_AXI_RDATA_I(37),
I2 => \^use_wrap_buffer\,
I3 => Q(5),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(37),
O => s_axi_rdata(5)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(6),
I1 => M_AXI_RDATA_I(38),
I2 => \^use_wrap_buffer\,
I3 => Q(6),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(38),
O => s_axi_rdata(6)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(7),
I1 => M_AXI_RDATA_I(39),
I2 => \^use_wrap_buffer\,
I3 => Q(7),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(39),
O => s_axi_rdata(7)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(8),
I1 => M_AXI_RDATA_I(40),
I2 => \^use_wrap_buffer\,
I3 => Q(8),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(40),
O => s_axi_rdata(8)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(9),
I1 => M_AXI_RDATA_I(41),
I2 => \^use_wrap_buffer\,
I3 => Q(9),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(41),
O => s_axi_rdata(9)
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F100F1000000"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^use_wrap_buffer_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[0]_0\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8),
I5 => s_axi_rlast_INST_0_i_3_n_0,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEEEFEFFFFFFFF"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => s_axi_rlast_INST_0_i_5_n_0,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I5 => s_axi_rlast_INST_0_i_6_n_0,
O => \^use_wrap_buffer_reg_0\
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11),
O => s_axi_rlast_INST_0_i_3_n_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050500030"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3),
O => s_axi_rlast_INST_0_i_6_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => Q(64),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => Q(65),
O => s_axi_rresp(1)
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => s_axi_rready,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I2 => \current_word_1_reg[2]_1\,
I3 => \^use_wrap_buffer\,
I4 => \^use_wrap_buffer_reg_0\,
I5 => \^wrap_buffer_available\,
O => s_ready_i_reg
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCCBECC0CCC0C"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I1 => \^use_wrap_buffer\,
I2 => \^s_axi_rlast\,
I3 => use_wrap_buffer_i_2_n_0,
I4 => \^use_wrap_buffer_reg_0\,
I5 => \^wrap_buffer_available\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => mr_rvalid,
I2 => rd_cmd_valid,
I3 => s_axi_rready,
O => use_wrap_buffer_i_2_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => s_axi_aresetn
);
\wrap_buffer_available_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF800008888"
)
port map (
I0 => m_valid_i_reg(0),
I1 => s_axi_rready,
I2 => \^use_wrap_buffer_reg_0\,
I3 => use_wrap_buffer_i_2_n_0,
I4 => \wrap_buffer_available_i_2__0_n_0\,
I5 => \^wrap_buffer_available\,
O => \wrap_buffer_available_i_1__0_n_0\
);
\wrap_buffer_available_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^use_wrap_buffer_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
O => \wrap_buffer_available_i_2__0_n_0\
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \wrap_buffer_available_i_1__0_n_0\,
Q => \^wrap_buffer_available\,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
port (
first_word_q : out STD_LOGIC;
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ : out STD_LOGIC;
p_251_in : out STD_LOGIC;
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wrap_buffer_available : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wr_cmd_valid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer : entity is "axi_dwidth_converter_v2_1_11_w_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\ : STD_LOGIC;
signal \^use_register.m_axi_wlast_q_reg_0\ : STD_LOGIC;
signal \^use_rtl_curr_word.current_word_q_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_1\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_2\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^use_rtl_length.length_counter_q_reg[3]_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[7]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\ : STD_LOGIC;
signal first_mi_word_q : STD_LOGIC;
signal \^first_word_q\ : STD_LOGIC;
signal \^m_axi_wlast\ : STD_LOGIC;
signal \^m_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_251_in\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal wstrb_wrap_buffer_1 : STD_LOGIC;
signal wstrb_wrap_buffer_2 : STD_LOGIC;
signal wstrb_wrap_buffer_3 : STD_LOGIC;
signal wstrb_wrap_buffer_4 : STD_LOGIC;
signal wstrb_wrap_buffer_5 : STD_LOGIC;
signal wstrb_wrap_buffer_6 : STD_LOGIC;
signal wstrb_wrap_buffer_7 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_7\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_6\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_7\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9\ : label is "soft_lutpair47";
begin
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ <= \^use_register.m_axi_wlast_q_reg_0\;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) <= \^use_rtl_curr_word.current_word_q_reg[2]_0\(2 downto 0);
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ <= \^use_rtl_length.first_mi_word_q_reg_0\;
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ <= \^use_rtl_length.first_mi_word_q_reg_1\;
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ <= \^use_rtl_length.first_mi_word_q_reg_2\;
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ <= \^use_rtl_length.length_counter_q_reg[3]_0\;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ <= \^use_rtl_length.length_counter_q_reg[7]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0) <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0);
first_word_q <= \^first_word_q\;
m_axi_wlast <= \^m_axi_wlast\;
m_axi_wstrb(7 downto 0) <= \^m_axi_wstrb\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
p_251_in <= \^p_251_in\;
wrap_buffer_available <= \^wrap_buffer_available\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000B847"
)
port map (
I0 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(0),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\,
I2 => Q(11),
I3 => Q(8),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\,
I5 => \^use_rtl_length.length_counter_q_reg[3]_0\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D000D0D000000000"
)
port map (
I0 => \^m_axi_wvalid\,
I1 => m_axi_wready,
I2 => s_axi_wvalid,
I3 => \^wrap_buffer_available\,
I4 => Q(12),
I5 => wr_cmd_valid,
O => \^use_rtl_length.first_mi_word_q_reg_2\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => Q(3),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => first_mi_word_q,
I4 => Q(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\
);
\USE_REGISTER.M_AXI_WLAST_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wlast,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \^m_axi_wlast\,
O => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\
);
\USE_REGISTER.M_AXI_WLAST_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\,
Q => \^m_axi_wlast\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_REGISTER.M_AXI_WVALID_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\,
Q => \^m_axi_wvalid\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.first_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wlast,
Q => \^first_word_q\,
S => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]_0\(2),
I1 => Q(14),
I2 => \^first_word_q\,
I3 => Q(10),
O => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]_0\(1),
I1 => Q(14),
I2 => \^first_word_q\,
I3 => Q(9),
O => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000400000000"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\,
I2 => \^use_rtl_length.first_mi_word_q_reg_1\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\,
I5 => \^use_rtl_length.first_mi_word_q_reg_2\,
O => \^p_251_in\
);
\USE_RTL_LENGTH.first_mi_word_q_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => first_mi_word_q,
I3 => Q(2),
O => \^use_rtl_length.first_mi_word_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\,
I1 => Q(13),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I3 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
I5 => \^use_rtl_length.length_counter_q_reg[7]_0\,
O => \^use_rtl_length.first_mi_word_q_reg_1\
);
\USE_RTL_LENGTH.first_mi_word_q_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => s_axi_wlast,
Q => first_mi_word_q,
S => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => first_mi_word_q,
I2 => Q(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => Q(0),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => first_mi_word_q,
I4 => Q(1),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B847"
)
port map (
I0 => Q(2),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^use_rtl_length.length_counter_q_reg[3]_0\,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB874B847"
)
port map (
I0 => Q(3),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => Q(2),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => Q(0),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => first_mi_word_q,
I4 => Q(1),
O => \^use_rtl_length.length_counter_q_reg[3]_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCAACCAAC3AAC355"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => Q(4),
I2 => Q(3),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => \^use_rtl_length.first_mi_word_q_reg_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => Q(5),
I2 => Q(4),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => first_mi_word_q,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => Q(6),
I2 => Q(5),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21DE2E2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => first_mi_word_q,
I2 => Q(7),
I3 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I4 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => Q(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => first_mi_word_q,
I4 => Q(6),
O => \^use_rtl_length.length_counter_q_reg[7]_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(3),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I2 => \^use_rtl_length.first_mi_word_q_reg_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I4 => first_mi_word_q,
I5 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(0),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => p_1_in(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(1),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => p_1_in(1)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => p_1_in(2)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(3),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => p_1_in(3)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(4),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => p_1_in(4)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(5),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => p_1_in(5)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(6),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => p_1_in(6)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(7),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => p_1_in(7)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(0),
Q => m_axi_wdata(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(1),
Q => m_axi_wdata(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(2),
Q => m_axi_wdata(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(3),
Q => m_axi_wdata(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(4),
Q => m_axi_wdata(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(5),
Q => m_axi_wdata(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(6),
Q => m_axi_wdata(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(7),
Q => m_axi_wdata(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => \^m_axi_wstrb\(0),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\,
Q => \^m_axi_wstrb\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\,
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(10),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(11),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(12),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(13),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(14),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_1,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(15),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(8),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(9),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\,
Q => m_axi_wdata(10),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\,
Q => m_axi_wdata(11),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\,
Q => m_axi_wdata(12),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\,
Q => m_axi_wdata(13),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\,
Q => m_axi_wdata(14),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\,
Q => m_axi_wdata(15),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\,
Q => m_axi_wdata(8),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\,
Q => m_axi_wdata(9),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => \^m_axi_wstrb\(1),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\,
Q => \^m_axi_wstrb\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_1,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\,
Q => wstrb_wrap_buffer_1,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(16),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(17),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(18),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(19),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(20),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(21),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(22),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_2,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(23),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\,
Q => m_axi_wdata(16),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\,
Q => m_axi_wdata(17),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\,
Q => m_axi_wdata(18),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\,
Q => m_axi_wdata(19),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\,
Q => m_axi_wdata(20),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\,
Q => m_axi_wdata(21),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\,
Q => m_axi_wdata(22),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\,
Q => m_axi_wdata(23),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => \^m_axi_wstrb\(2),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\,
Q => \^m_axi_wstrb\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_2,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\,
Q => wstrb_wrap_buffer_2,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(24),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(25),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(26),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(27),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(28),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(29),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(30),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_3,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(31),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\,
Q => m_axi_wdata(24),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\,
Q => m_axi_wdata(25),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\,
Q => m_axi_wdata(26),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\,
Q => m_axi_wdata(27),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\,
Q => m_axi_wdata(28),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\,
Q => m_axi_wdata(29),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\,
Q => m_axi_wdata(30),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\,
Q => m_axi_wdata(31),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => \^m_axi_wstrb\(3),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\,
Q => \^m_axi_wstrb\(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_3,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\,
Q => wstrb_wrap_buffer_3,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(0),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(1),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(3),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(4),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(5),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(6),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_4,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(7),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\,
Q => m_axi_wdata(32),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\,
Q => m_axi_wdata(33),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\,
Q => m_axi_wdata(34),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\,
Q => m_axi_wdata(35),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\,
Q => m_axi_wdata(36),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\,
Q => m_axi_wdata(37),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\,
Q => m_axi_wdata(38),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\,
Q => m_axi_wdata(39),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => \^m_axi_wstrb\(4),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\,
Q => \^m_axi_wstrb\(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_4,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\,
Q => wstrb_wrap_buffer_4,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(8),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(9),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(10),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(11),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(12),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(13),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(14),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_5,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(15),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\,
Q => m_axi_wdata(40),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\,
Q => m_axi_wdata(41),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\,
Q => m_axi_wdata(42),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\,
Q => m_axi_wdata(43),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\,
Q => m_axi_wdata(44),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\,
Q => m_axi_wdata(45),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\,
Q => m_axi_wdata(46),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\,
Q => m_axi_wdata(47),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => \^m_axi_wstrb\(5),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\,
Q => \^m_axi_wstrb\(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_5,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\,
Q => wstrb_wrap_buffer_5,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(16),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(17),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(18),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(19),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(20),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(21),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(22),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_6,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(23),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\,
Q => m_axi_wdata(48),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\,
Q => m_axi_wdata(49),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\,
Q => m_axi_wdata(50),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\,
Q => m_axi_wdata(51),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\,
Q => m_axi_wdata(52),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\,
Q => m_axi_wdata(53),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\,
Q => m_axi_wdata(54),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\,
Q => m_axi_wdata(55),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => \^m_axi_wstrb\(6),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\,
Q => \^m_axi_wstrb\(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_6,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\,
Q => wstrb_wrap_buffer_6,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(24),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(25),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(26),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(27),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(28),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(29),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(30),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \out\,
O => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFEA"
)
port map (
I0 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
I1 => Q(2),
I2 => first_mi_word_q,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I5 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFDFD5"
)
port map (
I0 => Q(13),
I1 => Q(7),
I2 => first_mi_word_q,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I5 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_7,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(31),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\,
I1 => \^wrap_buffer_available\,
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\,
I4 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\,
Q => m_axi_wdata(56),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\,
Q => m_axi_wdata(57),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\,
Q => m_axi_wdata(58),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\,
Q => m_axi_wdata(59),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\,
Q => m_axi_wdata(60),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\,
Q => m_axi_wdata(61),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\,
Q => m_axi_wdata(62),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\,
Q => m_axi_wdata(63),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => \^m_axi_wstrb\(7),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\,
Q => \^m_axi_wstrb\(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_7,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\,
Q => wstrb_wrap_buffer_7,
R => SR(0)
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
Q => \^wrap_buffer_available\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
port (
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 44 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\ : STD_LOGIC_VECTOR ( 27 downto 0 );
signal \USE_READ.read_addr_inst/access_need_extra_word__3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst/cmd_next_word_ii__10\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_axi_araddr[2]_INST_0_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0_i_2\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_3\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_6\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_6\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0_i_2\ : label is "soft_lutpair72";
begin
Q(44 downto 0) <= \^q\(44 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0) <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(27 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAAAE"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCECFEAAFCA8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFEEFFFEEEEE"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000022202AA"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414144414141044"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8848488848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFC0000EEFC"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2228282828282828"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I5 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7888788877887888"
)
port map (
I0 => sr_araddr(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I2 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF08088888080"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_arburst(1),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => sr_araddr(0),
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000100010000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888882288888828"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I1 => sr_araddr(1),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF5FF07000A00F8"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_araddr(2),
O => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100010001000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I1 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => sr_araddr(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554555455540000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"13100000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(2),
I3 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I4 => \^q\(33),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFE0000000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \^q\(33),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(9)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => s_axi_aresetn
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEFCCCCCCCC"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000040400"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFA0A0A0B0"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \m_axi_araddr[1]_INST_0_i_3_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(4),
O => \m_axi_araddr[1]_INST_0_i_2_n_0\
);
\m_axi_araddr[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400044444"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(1),
I2 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I5 => s_axi_arlen_ii(0),
O => \m_axi_araddr[1]_INST_0_i_3_n_0\
);
\m_axi_araddr[1]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_araddr[1]_INST_0_i_4_n_0\
);
\m_axi_araddr[1]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_5_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABABAB00000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I2 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => sr_araddr(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_2_n_0\
);
\m_axi_araddr[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_araddr[2]_INST_0_i_3_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00004000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => \^q\(33),
I2 => s_axi_arlen_ii(2),
I3 => sr_arburst(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_arburst[0]_INST_0_i_1_n_0\,
O => m_axi_arburst(0)
);
\m_axi_arburst[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(1),
I4 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I5 => sr_arburst(0),
O => \m_axi_arburst[0]_INST_0_i_1_n_0\
);
\m_axi_arburst[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03030700"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
O => \m_axi_arburst[0]_INST_0_i_2_n_0\
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFF00FF00"
)
port map (
I0 => \^q\(33),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arburst[1]_INST_0_i_1_n_0\,
I3 => \m_axi_arburst[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => m_axi_arburst(1)
);
\m_axi_arburst[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(0),
I2 => sr_arsize(2),
O => \m_axi_arburst[1]_INST_0_i_1_n_0\
);
\m_axi_arburst[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00A000BB00B100"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arburst(1),
I4 => sr_arsize(1),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arburst[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00151515FFEAEAEA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_READ.read_addr_inst/access_need_extra_word__3\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_1_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F800000000"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
O => \USE_READ.read_addr_inst/access_need_extra_word__3\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030202"
)
port map (
I0 => sr_araddr(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFAAEAAA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_araddr(0),
I3 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I4 => sr_araddr(2),
I5 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_araddr(0),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_10_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E888"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F4000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_10_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000A800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A800A800A800"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(0),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAAAEAAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00003777FFFFC888"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5540400000000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_7_n_0\,
O => \m_axi_arlen[3]_INST_0_i_3_n_0\
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => \^q\(33),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_7_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(4),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F0800000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07070F0F07F8F0F0"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[5]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A0C00"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[5]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"556A6A6A"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(6),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000100010000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => \^q\(33),
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(4),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(7),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(7)
);
\m_axi_arlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => s_axi_arlen_ii(3),
O => \m_axi_arlen[7]_INST_0_i_1_n_0\
);
\m_axi_arlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[7]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => sr_arsize(1),
O => \m_axi_arlen[7]_INST_0_i_3_n_0\
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(0),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(1),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(1)
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000100000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(10),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(11),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(12),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(13),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(14),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(15),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(16),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(17),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(18),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(19),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(20),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(21),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(22),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(23),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(24),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(25),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(26),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(27),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(28),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(29),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(30),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(31),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(32),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(33),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(34),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(3),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(40),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(41),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(42),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(43),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(4),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(52),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(53),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(54),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(55),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(56),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(57),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(58),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(5),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(59),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(60),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(6),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(7),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(8),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(9),
Q => \^q\(6),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_arready\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^sr_arvalid\,
I4 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
sr_awvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 24 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 24 downto 0 );
signal \m_axi_awaddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \^m_axi_awregion[3]\ : STD_LOGIC_VECTOR ( 41 downto 0 );
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[3]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[4]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[5]\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal s_axi_awlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal sr_awaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_awvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_axi_awaddr[0]_INST_0_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_3\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_4\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_3\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_4\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_8\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_axi_awburst[0]_INST_0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_awburst[1]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_3\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_awlen[2]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_awlen[5]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_3\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_4\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_10\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_13\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_14\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_2\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_4\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_awsize[0]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_awsize[1]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_awsize[2]_INST_0\ : label is "soft_lutpair93";
begin
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\;
\aresetn_d_reg[1]\ <= \^aresetn_d_reg[1]\;
\in\(24 downto 0) <= \^in\(24 downto 0);
\m_axi_awregion[3]\(41 downto 0) <= \^m_axi_awregion[3]\(41 downto 0);
s_axi_awready <= \^s_axi_awready\;
sr_awvalid <= \^sr_awvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAE"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => sr_awsize(2),
I4 => sr_awsize(1),
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAFEBA"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => sr_awsize(1),
I5 => sr_awsize(2),
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"380038003800C800"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awaddr(0),
I2 => s_axi_awlen_ii(0),
I3 => \^in\(8),
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414141141414144"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I2 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I3 => sr_awburst(1),
I4 => sr_awburst(0),
I5 => sr_awaddr(1),
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00100000FFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000E00000000000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => sr_awaddr(0),
I3 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"03EFFC00FC0003EF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\,
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001010100"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I5 => sr_awaddr(0),
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4441444144414444"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_awaddr(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => sr_awaddr(0),
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4015151515404040"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\,
I2 => sr_awaddr(1),
I3 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I4 => sr_awsize(1),
I5 => sr_awaddr(2),
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"000E"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000200020000"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(0),
I5 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(2),
I1 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]\,
R => s_axi_aresetn
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A2AAAAAA"
)
port map (
I0 => sr_awaddr(0),
I1 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(0)
);
\m_axi_awaddr[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
O => \m_axi_awaddr[0]_INST_0_i_1_n_0\
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"008A"
)
port map (
I0 => sr_awaddr(1),
I1 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF1B"
)
port map (
I0 => sr_awsize(0),
I1 => s_axi_awlen_ii(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[1]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88008F00"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I3 => sr_awaddr(2),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
O => \m_axi_awaddr[2]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\
);
\m_axi_awaddr[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0033557F"
)
port map (
I0 => sr_awsize(1),
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[2]_INST_0_i_3_n_0\
);
\m_axi_awaddr[2]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awaddr[2]_INST_0_i_4_n_0\
);
\m_axi_awaddr[2]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0A0C00000A0C"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(2),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[2]_INST_0_i_5_n_0\
);
\m_axi_awaddr[2]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAEFFFFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => \^in\(8),
I3 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \m_axi_awaddr[2]_INST_0_i_6_n_0\
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9AAAAAA999AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[3]\,
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I5 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(3),
O => \m_axi_awaddr[3]_INST_0_i_1_n_0\
);
\m_axi_awaddr[3]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"53"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(0),
O => \m_axi_awaddr[3]_INST_0_i_2_n_0\
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[4]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_payload_i_reg_n_0_[3]\,
I3 => \m_axi_awaddr[4]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(4)
);
\m_axi_awaddr[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAA2A28AAAAAAA"
)
port map (
I0 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[4]_INST_0_i_1_n_0\
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[5]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => \m_payload_i_reg_n_0_[3]\,
I4 => \m_payload_i_reg_n_0_[4]\,
I5 => \m_axi_awaddr[5]_INST_0_i_3_n_0\,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010101000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I3 => sr_awaddr(2),
I4 => sr_awaddr(1),
I5 => sr_awaddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\
);
\m_axi_awaddr[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => \^m_axi_awregion[3]\(30),
I1 => s_axi_awlen_ii(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \^in\(24),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\
);
\m_axi_awaddr[5]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"30233323"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => sr_awsize(2),
I3 => sr_awsize(1),
I4 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_3_n_0\
);
\m_axi_awaddr[5]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \m_axi_awaddr[5]_INST_0_i_4_n_0\
);
\m_axi_awaddr[5]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => \^m_axi_awregion[3]\(30),
O => \m_axi_awaddr[5]_INST_0_i_5_n_0\
);
\m_axi_awaddr[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => s_axi_awlen_ii(5),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(7),
I5 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_6_n_0\
);
\m_axi_awaddr[5]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(7),
I2 => s_axi_awlen_ii(6),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(5),
O => \m_axi_awaddr[5]_INST_0_i_7_n_0\
);
\m_axi_awaddr[5]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000A000C"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
O => \m_axi_awaddr[5]_INST_0_i_8_n_0\
);
\m_axi_awaddr[5]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFAFAEECCEA88"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(1),
I5 => sr_awsize(2),
O => \m_axi_awaddr[5]_INST_0_i_9_n_0\
);
\m_axi_awburst[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awburst(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(0)
);
\m_axi_awburst[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awburst(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(1)
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9599"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[0]_INST_0_i_2_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(0),
O => \^in\(0)
);
\m_axi_awlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
I4 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
O => \m_axi_awlen[0]_INST_0_i_1_n_0\
);
\m_axi_awlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"575F5757575F5F5F"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[0]_INST_0_i_3_n_0\,
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[0]_INST_0_i_2_n_0\
);
\m_axi_awlen[0]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awlen[0]_INST_0_i_3_n_0\
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"959A"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(1),
O => \^in\(1)
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1FF2E00"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I4 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \^in\(2)
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08880800F777F7FF"
)
port map (
I0 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I4 => s_axi_awlen_ii(1),
I5 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
O => \^in\(3)
);
\m_axi_awlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCDFCFDFFCDFFFD"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => s_axi_awlen_ii(3),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[3]_INST_0_i_1_n_0\
);
\m_axi_awlen[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
O => \^in\(4)
);
\m_axi_awlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFF00008000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
O => \^in\(5)
);
\m_axi_awlen[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003222"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
O => \m_axi_awlen[5]_INST_0_i_1_n_0\
);
\m_axi_awlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"2E"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
O => \m_axi_awlen[5]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000DFFFFFFF"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
O => \^in\(6)
);
\m_axi_awlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055004000000000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
O => \m_axi_awlen[6]_INST_0_i_1_n_0\
);
\m_axi_awlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACACACACACACACA"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => sr_awsize(1),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[6]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I1 => sr_awburst(1),
I2 => sr_awburst(0),
O => \m_axi_awlen[6]_INST_0_i_3_n_0\
);
\m_axi_awlen[6]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
O => \m_axi_awlen[6]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_3_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_6_n_0\,
O => \^in\(7)
);
\m_axi_awlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF3FFFF55555555"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(7),
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_1_n_0\
);
\m_axi_awlen[7]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_10_n_0\
);
\m_axi_awlen[7]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDD1111D1DD"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_15_n_0\,
O => \m_axi_awlen[7]_INST_0_i_11_n_0\
);
\m_axi_awlen[7]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF3F3F5F5F0FF"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(2),
I3 => s_axi_awlen_ii(6),
I4 => sr_awsize(1),
I5 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_12_n_0\
);
\m_axi_awlen[7]_INST_0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_13_n_0\
);
\m_axi_awlen[7]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"03080008"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(6),
O => \m_axi_awlen[7]_INST_0_i_14_n_0\
);
\m_axi_awlen[7]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"3530353535353535"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[7]_INST_0_i_15_n_0\
);
\m_axi_awlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_7_n_0\,
O => \m_axi_awlen[7]_INST_0_i_2_n_0\
);
\m_axi_awlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF5F7FFFFFFFF"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_10_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I5 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \m_axi_awlen[7]_INST_0_i_3_n_0\
);
\m_axi_awlen[7]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_12_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => s_axi_awlen_ii(3),
O => \m_axi_awlen[7]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E222EEEEE222E222"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^in\(10),
I3 => s_axi_awlen_ii(6),
I4 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I5 => s_axi_awlen_ii(7),
O => \m_axi_awlen[7]_INST_0_i_5_n_0\
);
\m_axi_awlen[7]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_6_n_0\
);
\m_axi_awlen[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBFBB"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_14_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => sr_awsize(1),
I3 => s_axi_awlen_ii(7),
I4 => sr_awsize(0),
I5 => sr_awsize(2),
O => \m_axi_awlen[7]_INST_0_i_7_n_0\
);
\m_axi_awlen[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"08AE08AE08AE0808"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I1 => sr_awaddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I3 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I4 => sr_awburst(1),
I5 => sr_awburst(0),
O => \m_axi_awlen[7]_INST_0_i_8_n_0\
);
\m_axi_awlen[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFAFFFBFFFBFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I2 => sr_awburst(1),
I3 => sr_awburst(0),
I4 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I5 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_9_n_0\
);
\m_axi_awsize[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(0)
);
\m_axi_awsize[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(1)
);
\m_axi_awsize[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awsize(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(2)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_awvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_awaddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^m_axi_awregion[3]\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^m_axi_awregion[3]\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^m_axi_awregion[3]\(6),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^m_axi_awregion[3]\(7),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^m_axi_awregion[3]\(8),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^m_axi_awregion[3]\(9),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^m_axi_awregion[3]\(10),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^m_axi_awregion[3]\(11),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^m_axi_awregion[3]\(12),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^m_axi_awregion[3]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_awaddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^m_axi_awregion[3]\(14),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^m_axi_awregion[3]\(15),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^m_axi_awregion[3]\(16),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^m_axi_awregion[3]\(17),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^m_axi_awregion[3]\(18),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^m_axi_awregion[3]\(19),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^m_axi_awregion[3]\(20),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^m_axi_awregion[3]\(21),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^m_axi_awregion[3]\(22),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^m_axi_awregion[3]\(23),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_awaddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^m_axi_awregion[3]\(24),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^m_axi_awregion[3]\(25),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^m_axi_awregion[3]\(26),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^m_axi_awregion[3]\(27),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^m_axi_awregion[3]\(28),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_awsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_awsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_awsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_awburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_awburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => \m_payload_i_reg_n_0_[3]\,
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^m_axi_awregion[3]\(29),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^m_axi_awregion[3]\(30),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^m_axi_awregion[3]\(31),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^m_axi_awregion[3]\(32),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_awlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_awlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_awlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_awlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_awlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_awlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \m_payload_i_reg_n_0_[4]\,
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_awlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_awlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^m_axi_awregion[3]\(33),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^m_axi_awregion[3]\(34),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^m_axi_awregion[3]\(35),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^m_axi_awregion[3]\(36),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^m_axi_awregion[3]\(37),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^m_axi_awregion[3]\(38),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^m_axi_awregion[3]\(39),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \m_payload_i_reg_n_0_[5]\,
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^m_axi_awregion[3]\(40),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^m_axi_awregion[3]\(41),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^m_axi_awregion[3]\(0),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^m_axi_awregion[3]\(1),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^m_axi_awregion[3]\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^m_axi_awregion[3]\(3),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_awready\,
I1 => cmd_push_block_reg,
I2 => s_axi_awvalid,
I3 => \aresetn_d_reg[1]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^sr_awvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \aresetn_d_reg[1]_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_awvalid,
I3 => \^sr_awvalid\,
I4 => \^aresetn_d_reg[1]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_awready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^mr_rvalid\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair28";
begin
m_axi_rready <= \^m_axi_rready\;
mr_rvalid <= \^mr_rvalid\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(0),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(10),
Q => Q(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(11),
Q => Q(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(12),
Q => Q(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(13),
Q => Q(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(14),
Q => Q(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(15),
Q => Q(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(16),
Q => Q(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(17),
Q => Q(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(18),
Q => Q(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(19),
Q => Q(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(1),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(20),
Q => Q(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(21),
Q => Q(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(22),
Q => Q(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(23),
Q => Q(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(24),
Q => Q(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(25),
Q => Q(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(26),
Q => Q(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(27),
Q => Q(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(28),
Q => Q(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(29),
Q => Q(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(2),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(30),
Q => Q(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(31),
Q => Q(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(32),
Q => Q(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(33),
Q => Q(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(34),
Q => Q(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(35),
Q => Q(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(36),
Q => Q(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(37),
Q => Q(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(38),
Q => Q(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(39),
Q => Q(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(3),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(40),
Q => Q(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(41),
Q => Q(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(42),
Q => Q(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(43),
Q => Q(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(44),
Q => Q(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(45),
Q => Q(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(46),
Q => Q(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(47),
Q => Q(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(48),
Q => Q(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(49),
Q => Q(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(4),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(50),
Q => Q(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(51),
Q => Q(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(52),
Q => Q(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(53),
Q => Q(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(54),
Q => Q(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(55),
Q => Q(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(56),
Q => Q(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(57),
Q => Q(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(58),
Q => Q(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(59),
Q => Q(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(5),
Q => Q(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(60),
Q => Q(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(61),
Q => Q(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(62),
Q => Q(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(63),
Q => Q(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(64),
Q => Q(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(65),
Q => Q(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(66),
Q => Q(66),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(6),
Q => Q(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(7),
Q => Q(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(8),
Q => Q(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(9),
Q => Q(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDFDFDFD00000000"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => \^mr_rvalid\,
I3 => rd_cmd_valid,
I4 => use_wrap_buffer_reg,
I5 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^mr_rvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5FFD500000000"
)
port map (
I0 => \^mr_rvalid\,
I1 => rd_cmd_valid,
I2 => use_wrap_buffer_reg,
I3 => \^m_axi_rready\,
I4 => m_axi_rvalid,
I5 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
port (
\USE_RTL_CURR_WORD.first_word_q_reg\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
p_251_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
cmd_push_block : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[5]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^use_rtl_curr_word.current_word_q_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^use_rtl_curr_word.first_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\ : STD_LOGIC;
signal \^use_rtl_curr_word.pre_next_word_q_reg[1]\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal wr_cmd_complete_wrap : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal wr_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_3\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\ : label is "soft_lutpair51";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair55";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair54";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair53";
begin
Q(14 downto 0) <= \^q\(14 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\;
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) <= \^use_rtl_curr_word.current_word_q_reg[2]\(2 downto 0);
\USE_RTL_CURR_WORD.first_word_q_reg\ <= \^use_rtl_curr_word.first_word_q_reg\;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ <= \^use_rtl_curr_word.pre_next_word_q_reg[1]\;
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ <= \^use_rtl_length.first_mi_word_q_reg_0\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA080000FFFFFFFF"
)
port map (
I0 => s_axi_wlast,
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[0]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I4 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I5 => \^use_rtl_curr_word.first_word_q_reg\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg[5]\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[3]\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\,
I4 => \^q\(13),
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0001FFFF"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]\(2),
I1 => \^use_rtl_curr_word.current_word_q_reg[2]\(1),
I2 => wr_cmd_complete_wrap,
I3 => \^use_rtl_curr_word.current_word_q_reg[2]\(0),
I4 => \^q\(13),
I5 => \^q\(14),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(2),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => wr_cmd_mask(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => wr_cmd_mask(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => wr_cmd_mask(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => wr_cmd_offset(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => \^q\(8),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => cmd_last_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => wr_cmd_next_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(9),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => \^q\(10),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => \^q\(11),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => wr_cmd_first_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => wr_cmd_first_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(12),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => wr_cmd_complete_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => \^q\(13),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(14),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => data_Exists_I,
Q => \^use_rtl_curr_word.first_word_q_reg\,
R => s_axi_aresetn
);
\USE_REGISTER.M_AXI_WVALID_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FFFF00800080"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\,
I2 => s_axi_wvalid,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
O => \USE_REGISTER.M_AXI_WVALID_q_reg\
);
\USE_REGISTER.M_AXI_WVALID_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAABAA"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I1 => \^use_rtl_length.first_mi_word_q_reg\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I3 => \^use_rtl_length.first_mi_word_q_reg_0\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
O => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => wrap_buffer_available,
I1 => \^q\(12),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
O => \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_awvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFF2000FFBA0045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => data_Exists_I_i_2_n_0,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => buffer_Full_q,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => s_axi_aresetn
);
\USE_RTL_CURR_WORD.current_word_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(0),
I1 => wr_cmd_next_word(0),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(0)
);
\USE_RTL_CURR_WORD.current_word_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(1),
I1 => \^q\(9),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(1)
);
\USE_RTL_CURR_WORD.current_word_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(2),
I1 => \^q\(10),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(2)
);
\USE_RTL_CURR_WORD.first_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA08AA00000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(12),
I2 => wrap_buffer_available,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I4 => m_axi_wready,
I5 => \^use_rtl_curr_word.first_word_q_reg\,
O => E(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => wr_cmd_mask(0),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
I2 => \^q\(14),
I3 => first_word_q,
I4 => wr_cmd_next_word(0),
I5 => cmd_step(0),
O => D(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => wr_cmd_mask(1),
I1 => cmd_step(1),
I2 => \^q\(9),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
I5 => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\,
O => D(1)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(14),
I1 => first_word_q,
O => \^use_rtl_curr_word.pre_next_word_q_reg[1]\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882828228282882"
)
port map (
I0 => wr_cmd_mask(2),
I1 => cmd_step(2),
I2 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\,
I3 => cmd_step(1),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\,
I5 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\,
O => D(2)
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => cmd_step(0),
I1 => wr_cmd_next_word(0),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
O => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_awvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"999A9995"
)
port map (
I0 => \^q\(8),
I1 => \^q\(11),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(0),
O => \^use_rtl_length.first_mi_word_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(1),
I1 => wr_cmd_first_word(1),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(1),
O => \^use_rtl_length.first_mi_word_q_reg\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => s_axi_aresetn
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F00"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => \^q\(13),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => s_axi_wlast,
I2 => p_251_in,
I3 => \out\,
O => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => wr_cmd_first_word(2),
I1 => first_word_q,
I2 => \^q\(14),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(0),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(0),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[39]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(1),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(1),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[47]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(2),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(2),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[55]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFBF"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
I1 => \^q\(13),
I2 => \^use_rtl_length.first_mi_word_q_reg_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\,
I4 => \^use_rtl_length.first_mi_word_q_reg\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(3),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"75557575FFFFFFFF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wrap_buffer_available,
I4 => \^q\(12),
I5 => s_axi_wvalid,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(3),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[63]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_awvalid,
I3 => m_axi_awready,
O => cmd_push_block0
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I1 => data_Exists_I,
I2 => data_Exists_I_i_2_n_0,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => s_axi_aresetn
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_awvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_awvalid
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAA8A8A"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wrap_buffer_available,
I4 => \^q\(12),
O => s_axi_wready
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_awready,
I3 => \out\,
O => s_ready_i_reg
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFAAAA"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => s_axi_wlast,
I3 => p_251_in,
I4 => wrap_buffer_available,
O => wrap_buffer_available_reg
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\,
I1 => wrap_buffer_available,
I2 => \^q\(12),
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => s_axi_wvalid,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
port (
\M_AXI_RDATA_I_reg[63]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
pop_mi_data : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
first_word_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[63]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
first_word : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : in STD_LOGIC;
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
\out\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rdata_i_reg[63]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal \^current_word_1_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal \data_Exists_I_i_2__0_n_0\ : STD_LOGIC;
signal \^first_word_reg\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[2]_i_5_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \M_AXI_RDATA_I[63]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1__0\ : label is "soft_lutpair39";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_push_block_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \data_Exists_I_i_2__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \pre_next_word_1[1]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \s_ready_i_i_2__1\ : label is "soft_lutpair43";
begin
E(0) <= \^e\(0);
\M_AXI_RDATA_I_reg[63]\ <= \^m_axi_rdata_i_reg[63]\;
Q(12 downto 0) <= \^q\(12 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\;
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
\current_word_1_reg[2]\(2 downto 0) <= \^current_word_1_reg[2]\(2 downto 0);
first_word_reg <= \^first_word_reg\;
\M_AXI_RDATA_I[63]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => first_mi_word_q,
I3 => use_wrap_buffer,
I4 => rd_cmd_packed_wrap,
O => \M_AXI_RDATA_I_reg[63]_0\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AA02FFFFFFFF"
)
port map (
I0 => \^e\(0),
I1 => wrap_buffer_available,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
I3 => use_wrap_buffer,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I5 => \^m_axi_rdata_i_reg[63]\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01FDFE02FFFFFFFF"
)
port map (
I0 => \current_word_1_reg[2]_0\(2),
I1 => \^q\(12),
I2 => first_word,
I3 => \^q\(11),
I4 => \^q\(8),
I5 => \^first_word_reg\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => \^q\(8),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(9),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => \^q\(10),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => \^q\(11),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => rd_cmd_packed_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_modified,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(12),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => data_Exists_I,
Q => \^m_axi_rdata_i_reg[63]\,
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFF4000FFF4000B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => \data_Exists_I_i_2__0_n_0\,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808888888888"
)
port map (
I0 => valid_Write,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I3 => use_wrap_buffer,
I4 => wrap_buffer_available_reg_0,
I5 => \^e\(0),
O => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => s_axi_aresetn
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000808080008000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => s_axi_rready,
I3 => \^use_rtl_length.first_mi_word_q_reg\,
I4 => use_wrap_buffer,
I5 => wrap_buffer_available_reg,
O => pop_mi_data
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_arvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\,
Q => buffer_Full_q,
R => s_axi_aresetn
);
\cmd_push_block_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(0),
O => \^current_word_1_reg[2]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \^q\(9),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(1),
O => \^current_word_1_reg[2]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \^q\(10),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(2),
O => \^current_word_1_reg[2]\(2)
);
\data_Exists_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => data_Exists_I,
I2 => \data_Exists_I_i_2__0_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
\data_Exists_I_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => \data_Exists_I_i_2__0_n_0\
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => s_axi_aresetn
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[66]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDDDDDDDDF"
)
port map (
I0 => rd_cmd_modified,
I1 => \^q\(12),
I2 => \^current_word_1_reg[2]\(2),
I3 => \^current_word_1_reg[2]\(1),
I4 => rd_cmd_complete_wrap,
I5 => \^current_word_1_reg[2]\(0),
O => \^use_rtl_length.first_mi_word_q_reg\
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => \^q\(12),
I3 => first_word,
I4 => rd_cmd_next_word(0),
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
I2 => \^q\(9),
I3 => \pre_next_word_1[1]_i_2_n_0\,
I4 => \pre_next_word_1_reg[2]\(1),
I5 => \pre_next_word_1[2]_i_5_n_0\,
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(12),
I1 => first_word,
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => s_axi_rready,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => mr_rvalid,
I3 => use_wrap_buffer,
O => \^e\(0)
);
\pre_next_word_1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2828288228828282"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\,
I2 => \pre_next_word_1_reg[2]_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
I4 => \pre_next_word_1_reg[1]\,
I5 => \pre_next_word_1[2]_i_5_n_0\,
O => D(2)
);
\pre_next_word_1[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(0),
O => \pre_next_word_1[2]_i_5_n_0\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(11),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[2]_0\(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE0201FD"
)
port map (
I0 => \current_word_1_reg[2]_0\(0),
I1 => \^q\(12),
I2 => first_word,
I3 => rd_cmd_first_word(0),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\,
I5 => s_axi_rlast_INST_0_i_7_n_0,
O => \^first_word_reg\
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\,
I1 => rd_cmd_first_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[2]_0\(1),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^m_axi_rdata_i_reg[63]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
O => s_axi_rvalid
);
\s_ready_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_arready,
I3 => \out\,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
wr_cmd_valid : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
p_251_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
sr_awvalid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[5]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
Q(14 downto 0) => Q(14 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_REGISTER.M_AXI_WVALID_q_reg\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ => \USE_RTL_CURR_WORD.current_word_q_reg[0]\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0),
\USE_RTL_CURR_WORD.first_word_q_reg\ => wr_cmd_valid,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_RTL_LENGTH.first_mi_word_q_reg_0\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
\USE_RTL_LENGTH.length_counter_q_reg[3]\ => \USE_RTL_LENGTH.length_counter_q_reg[3]\,
\USE_RTL_LENGTH.length_counter_q_reg[5]\ => \USE_RTL_LENGTH.length_counter_q_reg[5]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0),
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
first_word_q => first_word_q,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => s_ready_i_reg,
sr_awvalid => sr_awvalid,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
pop_mi_data : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
first_word_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
first_word : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : in STD_LOGIC;
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
\out\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
\M_AXI_RDATA_I_reg[63]\ => rd_cmd_valid,
\M_AXI_RDATA_I_reg[63]_0\(0) => \M_AXI_RDATA_I_reg[63]\(0),
Q(12 downto 0) => Q(12 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\(2 downto 0) => \current_word_1_reg[2]\(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => \current_word_1_reg[2]_0\(2 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => first_word_reg,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[1]\ => \pre_next_word_1_reg[1]\,
\pre_next_word_1_reg[2]\(2 downto 0) => \pre_next_word_1_reg[2]\(2 downto 0),
\pre_next_word_1_reg[2]_0\ => \pre_next_word_1_reg[2]_0\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg,
wrap_buffer_available_reg_0 => wrap_buffer_available_reg_0
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(66 downto 0) => Q(66 downto 0),
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
use_wrap_buffer_reg => use_wrap_buffer_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
s_ready_i_reg : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
sr_awvalid : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
signal \^aresetn_d_reg[1]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
begin
\aresetn_d_reg[1]\ <= \^aresetn_d_reg[1]\;
s_ready_i_reg <= \^s_ready_i_reg\;
ar_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice
port map (
Q(44 downto 0) => Q(44 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0),
\aresetn_d_reg[0]\ => \^aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => \^s_ready_i_reg\,
sr_arvalid => sr_arvalid
);
aw_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0
port map (
D(60 downto 0) => D(60 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ => \in\(24),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ => \in\(25),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \in\(26),
\aresetn_d_reg[1]\ => \^aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \^s_ready_i_reg\,
cmd_push_block_reg => cmd_push_block_reg_0,
\in\(24) => \in\(27),
\in\(23 downto 0) => \in\(23 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
\m_axi_awregion[3]\(41 downto 0) => \m_axi_awregion[3]\(41 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_10\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_11\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_12\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_13\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_14\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_15\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_16\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_18\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_19\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_2\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_28\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_8\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_9\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_11\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_12\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_13\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_14\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_15\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_16\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_17\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_18\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_19\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_2\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_20\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_21\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_22\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_23\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_24\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_25\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_26\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_27\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_28\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_29\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_3\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_30\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_31\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_32\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_33\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_34\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_35\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_36\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_37\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_47\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_48\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_55\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_56\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_58\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_59\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_complete_wrap_i_6 : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_first_word_i_4 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_fix_i_8 : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal cmd_modified_i : STD_LOGIC;
signal cmd_modified_i_7 : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal cmd_packed_wrap_i_5 : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal current_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal first_word_q : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_102_out : STD_LOGIC;
signal p_131_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_160_out : STD_LOGIC;
signal p_189_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 22 downto 16 );
signal p_1_out_3 : STD_LOGIC_VECTOR ( 22 downto 16 );
signal p_222_out : STD_LOGIC;
signal p_251_in : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal p_71_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal pop_mi_data : STD_LOGIC;
signal pop_si_data : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 2 to 2 );
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal rd_cmd_valid : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_109 : STD_LOGIC;
signal si_register_slice_inst_n_110 : STD_LOGIC;
signal si_register_slice_inst_n_111 : STD_LOGIC;
signal si_register_slice_inst_n_112 : STD_LOGIC;
signal si_register_slice_inst_n_113 : STD_LOGIC;
signal si_register_slice_inst_n_114 : STD_LOGIC;
signal si_register_slice_inst_n_146 : STD_LOGIC;
signal si_register_slice_inst_n_147 : STD_LOGIC;
signal si_register_slice_inst_n_148 : STD_LOGIC;
signal si_register_slice_inst_n_149 : STD_LOGIC;
signal si_register_slice_inst_n_150 : STD_LOGIC;
signal si_register_slice_inst_n_151 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal sr_awvalid : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_cmd_fix : STD_LOGIC;
signal wr_cmd_modified : STD_LOGIC;
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal wr_cmd_packed_wrap : STD_LOGIC;
signal wr_cmd_valid : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wrap_buffer_available_0 : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
s_axi_rlast <= \^s_axi_rlast\;
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \r_pipe/p_1_in\,
Q(66) => \^m_axi_rlast\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_1,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_15_in,
Q(66) => \^m_axi_rlast\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ => \USE_READ.read_addr_inst_n_3\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_READ.read_addr_inst_n_18\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12) => rd_cmd_fix,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11) => rd_cmd_first_word(2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10 downto 9) => rd_cmd_next_word(2 downto 1),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8) => \USE_READ.read_addr_inst_n_8\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7) => \USE_READ.read_addr_inst_n_9\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6) => \USE_READ.read_addr_inst_n_10\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5) => \USE_READ.read_addr_inst_n_11\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4) => \USE_READ.read_addr_inst_n_12\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3) => \USE_READ.read_addr_inst_n_13\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2) => \USE_READ.read_addr_inst_n_14\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1) => \USE_READ.read_addr_inst_n_15\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0) => \USE_READ.read_addr_inst_n_16\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\,
\current_word_1_reg[0]_0\ => \USE_READ.read_addr_inst_n_19\,
\current_word_1_reg[2]_0\(2 downto 0) => pre_next_word_1(2 downto 0),
\current_word_1_reg[2]_1\ => \USE_READ.read_addr_inst_n_2\,
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg_0(2 downto 0) => current_word_1(2 downto 0),
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in\,
m_valid_i_reg(0) => p_7_in,
mr_rvalid => mr_rvalid,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[2]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\pre_next_word_1_reg[2]_1\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => \^s_axi_rlast\,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_ready_i_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
wrap_buffer_available => wrap_buffer_available
);
\USE_READ.read_addr_inst\: entity work.\system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_15_in,
\M_AXI_RDATA_I_reg[63]\(0) => p_7_in,
Q(12) => rd_cmd_fix,
Q(11) => rd_cmd_first_word(2),
Q(10 downto 9) => rd_cmd_next_word(2 downto 1),
Q(8) => \USE_READ.read_addr_inst_n_8\,
Q(7) => \USE_READ.read_addr_inst_n_9\,
Q(6) => \USE_READ.read_addr_inst_n_10\,
Q(5) => \USE_READ.read_addr_inst_n_11\,
Q(4) => \USE_READ.read_addr_inst_n_12\,
Q(3) => \USE_READ.read_addr_inst_n_13\,
Q(2) => \USE_READ.read_addr_inst_n_14\,
Q(1) => \USE_READ.read_addr_inst_n_15\,
Q(0) => \USE_READ.read_addr_inst_n_16\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_2\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_READ.read_addr_inst_n_18\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
\current_word_1_reg[2]\(2 downto 0) => next_word(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => current_word_1(2 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => \USE_READ.read_addr_inst_n_19\,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_146,
\in\(12) => si_register_slice_inst_n_147,
\in\(11) => si_register_slice_inst_n_148,
\in\(10) => si_register_slice_inst_n_149,
\in\(9) => si_register_slice_inst_n_150,
\in\(8) => si_register_slice_inst_n_151,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
\pre_next_word_1_reg[2]\(2 downto 0) => pre_next_word_1(2 downto 0),
\pre_next_word_1_reg[2]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_3\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => \USE_READ.read_addr_inst_n_28\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => \^s_axi_rlast\,
wrap_buffer_available_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\
);
\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer
port map (
D(2 downto 0) => pre_next_word_2(2 downto 0),
E(0) => pop_si_data,
Q(14) => wr_cmd_fix,
Q(13) => wr_cmd_modified,
Q(12) => wr_cmd_packed_wrap,
Q(11) => wr_cmd_first_word(0),
Q(10 downto 9) => wr_cmd_next_word(2 downto 1),
Q(8) => cmd_last_word(0),
Q(7) => \USE_WRITE.write_addr_inst_n_11\,
Q(6) => \USE_WRITE.write_addr_inst_n_12\,
Q(5) => \USE_WRITE.write_addr_inst_n_13\,
Q(4) => \USE_WRITE.write_addr_inst_n_14\,
Q(3) => \USE_WRITE.write_addr_inst_n_15\,
Q(2) => \USE_WRITE.write_addr_inst_n_16\,
Q(1) => \USE_WRITE.write_addr_inst_n_17\,
Q(0) => \USE_WRITE.write_addr_inst_n_18\,
SR(0) => \USE_WRITE.write_addr_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word_1(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\ => \USE_WRITE.write_addr_inst_n_48\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ => \USE_WRITE.write_addr_inst_n_47\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\ => \USE_WRITE.write_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ => \USE_WRITE.write_addr_inst_n_21\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ => \USE_WRITE.write_addr_inst_n_24\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ => \USE_WRITE.write_addr_inst_n_26\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ => \USE_WRITE.write_addr_inst_n_28\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ => \USE_WRITE.write_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ => \USE_WRITE.write_addr_inst_n_32\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ => \USE_WRITE.write_addr_inst_n_34\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ => \USE_WRITE.write_addr_inst_n_36\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ => \USE_WRITE.write_addr_inst_n_2\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_WRITE.write_addr_inst_n_20\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ => \USE_WRITE.write_addr_inst_n_23\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\ => \USE_WRITE.write_addr_inst_n_25\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\ => \USE_WRITE.write_addr_inst_n_27\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\ => \USE_WRITE.write_addr_inst_n_29\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\ => \USE_WRITE.write_addr_inst_n_31\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\ => \USE_WRITE.write_addr_inst_n_33\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\ => \USE_WRITE.write_addr_inst_n_35\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\ => \USE_WRITE.write_addr_inst_n_55\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_WRITE.write_addr_inst_n_58\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0) => \USE_WRITE.write_addr_inst_n_37\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0) => p_41_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0) => p_71_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0) => p_102_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0) => p_131_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0) => p_160_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0) => p_189_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0) => p_222_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\ => \USE_WRITE.write_addr_inst_n_3\,
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\,
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\,
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\,
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0) => current_word_q(2 downto 0),
first_word_q => first_word_q,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => \^m_axi_wvalid\,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_0
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
D(2 downto 0) => pre_next_word_2(2 downto 0),
E(0) => pop_si_data,
Q(14) => wr_cmd_fix,
Q(13) => wr_cmd_modified,
Q(12) => wr_cmd_packed_wrap,
Q(11) => wr_cmd_first_word(0),
Q(10 downto 9) => wr_cmd_next_word(2 downto 1),
Q(8) => cmd_last_word(0),
Q(7) => \USE_WRITE.write_addr_inst_n_11\,
Q(6) => \USE_WRITE.write_addr_inst_n_12\,
Q(5) => \USE_WRITE.write_addr_inst_n_13\,
Q(4) => \USE_WRITE.write_addr_inst_n_14\,
Q(3) => \USE_WRITE.write_addr_inst_n_15\,
Q(2) => \USE_WRITE.write_addr_inst_n_16\,
Q(1) => \USE_WRITE.write_addr_inst_n_17\,
Q(0) => \USE_WRITE.write_addr_inst_n_18\,
SR(0) => \USE_WRITE.write_addr_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_WRITE.write_addr_inst_n_2\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_WRITE.write_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \^m_axi_wvalid\,
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => next_word_1(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => current_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_WRITE.write_addr_inst_n_47\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.write_addr_inst_n_48\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\,
\USE_RTL_LENGTH.length_counter_q_reg[3]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\,
\USE_RTL_LENGTH.length_counter_q_reg[5]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_3\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \USE_WRITE.write_addr_inst_n_35\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ => \USE_WRITE.write_addr_inst_n_55\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_36\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => p_222_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ => \USE_WRITE.write_addr_inst_n_33\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \USE_WRITE.write_addr_inst_n_34\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => p_189_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ => \USE_WRITE.write_addr_inst_n_31\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \USE_WRITE.write_addr_inst_n_32\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => p_160_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ => \USE_WRITE.write_addr_inst_n_29\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \USE_WRITE.write_addr_inst_n_30\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => p_131_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ => \USE_WRITE.write_addr_inst_n_27\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \USE_WRITE.write_addr_inst_n_28\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => p_102_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ => \USE_WRITE.write_addr_inst_n_25\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \USE_WRITE.write_addr_inst_n_26\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => p_71_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ => \USE_WRITE.write_addr_inst_n_23\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \USE_WRITE.write_addr_inst_n_24\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => p_41_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ => \USE_WRITE.write_addr_inst_n_20\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \USE_WRITE.write_addr_inst_n_21\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \USE_WRITE.write_addr_inst_n_37\,
first_word_q => first_word_q,
\in\(27) => cmd_fix_i_8,
\in\(26) => cmd_modified_i_7,
\in\(25) => cmd_complete_wrap_i_6,
\in\(24) => cmd_packed_wrap_i_5,
\in\(23 downto 21) => cmd_first_word_i_4(2 downto 0),
\in\(20 downto 14) => p_1_out_3(22 downto 16),
\in\(13) => si_register_slice_inst_n_109,
\in\(12) => si_register_slice_inst_n_110,
\in\(11) => si_register_slice_inst_n_111,
\in\(10) => si_register_slice_inst_n_112,
\in\(9) => si_register_slice_inst_n_113,
\in\(8) => si_register_slice_inst_n_114,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => \USE_WRITE.write_addr_inst_n_56\,
sr_awvalid => sr_awvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_0,
wrap_buffer_available_reg => \USE_WRITE.write_addr_inst_n_58\
);
si_register_slice_inst: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27) => cmd_fix_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(26) => cmd_modified_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(25) => cmd_complete_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(24) => cmd_packed_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(23 downto 21) => cmd_first_word_i(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(20 downto 14) => p_1_out(22 downto 16),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(13) => si_register_slice_inst_n_146,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12) => si_register_slice_inst_n_147,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11) => si_register_slice_inst_n_148,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10) => si_register_slice_inst_n_149,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(9) => si_register_slice_inst_n_150,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8) => si_register_slice_inst_n_151,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_28\,
cmd_push_block_reg_0 => \USE_WRITE.write_addr_inst_n_56\,
\in\(27) => cmd_fix_i_8,
\in\(26) => cmd_modified_i_7,
\in\(25) => cmd_complete_wrap_i_6,
\in\(24) => cmd_packed_wrap_i_5,
\in\(23 downto 21) => cmd_first_word_i_4(2 downto 0),
\in\(20 downto 14) => p_1_out_3(22 downto 16),
\in\(13) => si_register_slice_inst_n_109,
\in\(12) => si_register_slice_inst_n_110,
\in\(11) => si_register_slice_inst_n_111,
\in\(10) => si_register_slice_inst_n_112,
\in\(9) => si_register_slice_inst_n_113,
\in\(8) => si_register_slice_inst_n_114,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
\m_axi_awregion[3]\(41 downto 0) => \m_axi_awregion[3]\(41 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg => si_register_slice_inst_n_0,
sr_arvalid => sr_arvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_0_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
begin
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^s_axi_bready\ <= s_axi_bready;
m_axi_bready <= \^s_axi_bready\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rid(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_awregion(3 downto 0),
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52) => s_axi_awlock(0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 40) => s_axi_awcache(3 downto 0),
D(39 downto 38) => s_axi_awburst(1 downto 0),
D(37 downto 35) => s_axi_awsize(2 downto 0),
D(34 downto 32) => s_axi_awprot(2 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
Q(44 downto 41) => m_axi_arregion(3 downto 0),
Q(40 downto 37) => m_axi_arqos(3 downto 0),
Q(36) => m_axi_arlock(0),
Q(35 downto 32) => m_axi_arcache(3 downto 0),
Q(31 downto 29) => m_axi_arprot(2 downto 0),
Q(28 downto 0) => m_axi_araddr(31 downto 3),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awready => m_axi_awready,
\m_axi_awregion[3]\(41 downto 38) => m_axi_awregion(3 downto 0),
\m_axi_awregion[3]\(37 downto 34) => m_axi_awqos(3 downto 0),
\m_axi_awregion[3]\(33) => m_axi_awlock(0),
\m_axi_awregion[3]\(32 downto 29) => m_axi_awcache(3 downto 0),
\m_axi_awregion[3]\(28 downto 26) => m_axi_awprot(2 downto 0),
\m_axi_awregion[3]\(25 downto 0) => m_axi_awaddr(31 downto 6),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
\out\ => s_axi_aresetn,
s_axi_aclk => s_axi_aclk,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 57) => s_axi_arregion(3 downto 0),
\s_axi_arregion[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arregion[3]\(52) => s_axi_arlock(0),
\s_axi_arregion[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arregion[3]\(43 downto 40) => s_axi_arcache(3 downto 0),
\s_axi_arregion[3]\(39 downto 38) => s_axi_arburst(1 downto 0),
\s_axi_arregion[3]\(37 downto 35) => s_axi_arsize(2 downto 0),
\s_axi_arregion[3]\(34 downto 32) => s_axi_arprot(2 downto 0),
\s_axi_arregion[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_0 : entity is "system_auto_us_0,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_0 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_0;
architecture STRUCTURE of system_auto_us_0 is
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 8fda5603a88e6dc03ef87f5254030b27 | 0.583026 | 2.504023 | false | false | false | false |
cakesmith/Firefly | VHDL/Test_Link.vhd | 1 | 4,831 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:54:23 12/31/2013
-- Design Name:
-- Module Name: /home/nick/Jarvis/Test_Link.vhd
-- Project Name: Jarvis
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Link
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY Test_Link IS
END Test_Link;
ARCHITECTURE behavior OF Test_Link IS
constant nodes : integer := 5;
constant c_addr_width : positive := 32;
constant c_data_width : positive := 32;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Link
generic ( addr_width : positive := c_addr_width;
data_width : positive := c_data_width;
num_cells : positive
);
PORT(
in_address : IN std_logic_vector(31 downto 0);
in_data : IN std_logic_vector(31 downto 0);
in_wr : IN std_logic;
out_address : OUT std_logic_vector(31 downto 0);
out_data : OUT std_logic_vector(31 downto 0);
out_wr : OUT std_logic;
my_address : OUT std_logic_vector(31 downto 0);
my_in_data : IN std_logic_vector(31 downto 0);
my_out_data : OUT std_logic_vector(31 downto 0);
my_wr : OUT std_logic
);
END COMPONENT;
type vec_32_array is array(0 to nodes - 1) of std_logic_vector(31 downto 0);
--Inputs
signal in_address : vec_32_array := (others => (others => '0'));
signal in_data : vec_32_array := (others => (others => '0'));
signal in_wr : std_logic_vector(0 to nodes - 1) := (others => '0');
signal my_in_data : vec_32_array := (others => (others => '0'));
--Outputs
signal out_address : vec_32_array;
signal out_data : vec_32_array;
signal out_wr : std_logic_vector(0 to nodes - 1);
signal my_address : vec_32_array;
signal my_out_data : vec_32_array;
signal my_wr : std_logic_vector(0 to nodes - 1);
signal clk: std_logic;
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
chain_gen: for I in 0 to nodes - 1 generate
first_node: if I=0 generate
link0: Link generic map (num_cells => 13)
PORT MAP (
in_address => in_address(0),
in_data => in_data(0),
in_wr => in_wr(0),
out_address => out_address(0),
out_data => out_data(0),
out_wr => out_wr(0),
my_address => my_address(0),
my_in_data => my_in_data(0),
my_out_data => my_out_data(0),
my_wr => my_wr(0)
);
end generate first_node;
other_nodes: if I>0 generate
linkX: Link
generic map (num_cells => 7)
PORT MAP (
in_address => out_address(I-1),
in_data => out_data(I-1),
in_wr => out_wr(I-1),
out_address => out_address(I),
out_data => out_data(I),
out_wr => out_wr(I),
my_address => my_address(I),
my_in_data => my_in_data(I),
my_out_data => my_out_data(I),
my_wr => my_wr(I)
);
end generate other_nodes;
end generate chain_gen;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- Initialization mode
wait for clk_period*10;
--
for i in 1 to 64 loop
in_address(0) <= std_logic_vector(to_unsigned(i,32));
wait for clk_period * 10;
end loop;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | df67c2b190138aed8fbbd5e5bc121d51 | 0.530946 | 3.78605 | false | true | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl | 3 | 5,896 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 : entity is "rgb565_to_rgb888";
end system_rgb565_to_rgb888_0_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
| mit | 7829e6c552fe63ba9a4e1b6f3ae39739 | 0.539518 | 3.043882 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zybo_hdmi/zybo_hdmi.srcs/sources_1/new/tmds_encoder.vhd | 6 | 4,438 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
port(
clk : in std_logic;
d_in : in std_logic_vector(7 downto 0); -- 8 bit d_in to be encoded
C : in std_logic_vector(1 downto 0); -- control bits (2)
video_on : in std_logic; -- BLANKING, is video on?
encoded : out std_logic_vector(9 downto 0)); -- output encoded
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : std_logic_vector(8 downto 0);
signal xnored : std_logic_vector(8 downto 0);
signal ones : std_logic_vector(3 downto 0);
signal q_m : std_logic_vector(8 downto 0);
signal q_m_inv : std_logic_vector(8 downto 0);
signal data_word_disparity : std_logic_vector(3 downto 0);
signal dc_bias : std_logic_vector(3 downto 0) := (others => '0');
begin
-- Perform FALSE<1> computations
xored(0) <= d_in(0);
xored(1) <= d_in(1) xor xored(0);
xored(2) <= d_in(2) xor xored(1);
xored(3) <= d_in(3) xor xored(2);
xored(4) <= d_in(4) xor xored(3);
xored(5) <= d_in(5) xor xored(4);
xored(6) <= d_in(6) xor xored(5);
xored(7) <= d_in(7) xor xored(6);
xored(8) <= '1';
-- Perform TRUE<1> computations
xnored(0) <= d_in(0);
xnored(1) <= d_in(1) xnor xnored(0);
xnored(2) <= d_in(2) xnor xnored(1);
xnored(3) <= d_in(3) xnor xnored(2);
xnored(4) <= d_in(4) xnor xnored(3);
xnored(5) <= d_in(5) xnor xnored(4);
xnored(6) <= d_in(6) xnor xnored(5);
xnored(7) <= d_in(7) xnor xnored(6);
xnored(8) <= '0';
-- count all 1's by adding them (0 won't contribute)
ones <= "0000" + d_in(0) + d_in(1) + d_in(2) + d_in(3)
+ d_in(4) + d_in(5) + d_in(6) + d_in(7);
-- decide on encoding
decision0: process(ones, d_in(0), xnored, xored)
begin
-- FIRST CHOICE DIAMOND (https://www.eewiki.net/pages/viewpage.action?pageId=36569119) <1>
if ones > 4 or (ones = 4 and d_in(0) = '0') then
q_m <= xnored;
q_m_inv <= NOT(xnored);
else
q_m <= xored;
q_m_inv <= NOT(xored);
end if;
end process decision0;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + q_m(0) + q_m(1) + q_m(2) + q_m(3)
+ q_m(4) + q_m(5) + q_m(6) + q_m(7);
-- Now work out what the output should be
process(clk)
begin
-- "DISPLAY ENABLE = 1"
if rising_edge(clk) then
if video_on = '0' then
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
-- Ones#(d) = 4 OR disparity = 0
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if q_m(8) = '0' then
encoded <= "10" & q_m_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
else
encoded <= "01" & q_m(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & q_m(8) & q_m_inv(7 downto 0);
dc_bias <= dc_bias + q_m(8) - data_word_disparity;
else
encoded <= '0' & q_m;
dc_bias <= dc_bias - q_m_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral; | mit | 22ba55fdac22c1968dbb340ee1b04550 | 0.463948 | 3.405986 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_g8_to_rgb888_0_0/synth/system_g8_to_rgb888_0_0.vhd | 1 | 3,693 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:g8_to_rgb888:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_g8_to_rgb888_0_0 IS
PORT (
g8 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_g8_to_rgb888_0_0;
ARCHITECTURE system_g8_to_rgb888_0_0_arch OF system_g8_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT g8_to_rgb888 IS
PORT (
g8 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT g8_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "g8_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_g8_to_rgb888_0_0_arch : ARCHITECTURE IS "system_g8_to_rgb888_0_0,g8_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "system_g8_to_rgb888_0_0,g8_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=g8_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : g8_to_rgb888
PORT MAP (
g8 => g8,
rgb888 => rgb888
);
END system_g8_to_rgb888_0_0_arch;
| mit | 343c0ee8b499bb0af455637e1352bf83 | 0.743298 | 3.638424 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl | 1 | 5,906 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 : entity is "rgb565_to_rgb888";
end system_rgb565_to_rgb888_0_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
| mit | 05c505d91d61b11f191837aca22b2430 | 0.539959 | 3.042761 | false | false | false | false |
Kolchuzhin/piezoresistance_of_SWCNT_in_VHDL-AMS_part_I | pr_swcnt.vhd | 1 | 6,147 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Model: piezoresistance of single walled carbon nanotube in hAMSter
--
-- Authors: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
--
-- Date: 07.06.2011 16:03
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: pr_swcnt.vhd
-------------------------------------------------------------------------------
-- Modification History:
--
-- Revision 1.0 25.04.2012 official release for ForGr1713: www.zfm.tu-chemnitz.de/for1713
-- Revision 1.1 02.03.2015 verification for (13.0), (14,0), (15,0)
-- 05.03.2015 GitHub
--
-- Dependencies:
-- mod_ad == modulus after division
-- sign == signum function (Returns 0.0 if X < 0.0) :( e.g. (14,0)
-- floor
--
-- Status: Compile OK, model was compiled with hAMSter simulator
-------------------------------------------------------------------------------
-- Reference:
-- Theory taken from M. A. Cullinan and M.L. Culpepper
-- Carbon nanotubes as piezoresistive microelectromechanical sensors: Theory and experiment
-- Phys Rev. B, American Physical Society, 82, 115428, 2010
-- *********************************************************
-- three types of SWNTs classified by:
-- p =0 => (semi)metallic
-- abs(p)=1 => semiconducting
-- n=m => metallic
-- *********************************************************
-- theta=0; % zigzag m=0 (n,0)
-- theta=30; % armchair n=m (n,n)
-- *********************************************************
-- data for verification (SWCNT_bandgap.m):
-- (13,0) semiconducting p=+1 kind=1 Eg0=0.7423 R_002 = 1.5689e+19
-- (14,0) semiconducting p=-1 kind=1 Eg0=0.6892 R_002 = 7.4154e+11
-- (15,0) semimetallic p= 0 kind=0 Eg0=0.0292 R_002 = 3.3838e+05
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use work.electromagnetic_system.all;
use work.all;
-------------------------------------------------------------------------------
entity pr_swcnt is
-- input parameters:
-- n -- chiral parameter for CNT
-- m -- chiral parameter for CNT
-- c1 -- stiffness, N/m
-- L0 -- initial length of tube, m
-- Rc -- contact resistance, Ohm
-- environment parameters
-- T -- temperature, K
-- s0 -- pretension strain
-- s -- strain = (L-L0)/L0 = f/c1/L0; (L-L0=u; f=c1*u)
-- g -- torsional strain
generic(Rc,T,n,m,s0,g,c1,L0:real); -- given as a generic parameter
port (terminal m1,m2:translational; -- structural ports
terminal e1,e2:electrical); -- electrical ports
end entity pr_swcnt;
--===========================================================================--
--===========================================================================--
architecture analytic of pr_swcnt is
quantity u across f through m1 to m2;
quantity v across i through e1 to e2;
--
quantity strain:real;
quantity p1:real;
quantity p:real;
quantity Eg0:real;
quantity Egs:real;
quantity kind:real;
quantity Rcnt:real;
-- physical constants
constant h:real:=6.6260695729e-34; -- Plancks constant, Js
constant e_charge:real:=1.60217646e-19; -- charge on an electron, As = C
constant kB:real:=1.380648813e-23; -- Boltzmanns constant, J/K
-- parameters of CNT
constant tp:real:=1.0; -- transmission probability t^2 of an electron
constant a:real:=1.421*sqrt(3.0); -- length of lattice vector, Å
constant t0:real:=2.66; -- the tight-binding overlap integral, eV
constant b:real:=3.5; -- change in transfer integral by changed bond lengths, eV/Å
constant nu:real:=0.2; -- Poisson's ratio = E/(2*G)-1
-- calculated parameters of CNT from m,n
constant r0:real:=(a*sqrt(n*n+m*m+m*n)/(2.0*MATH_PI)); -- radius
constant theta:real:=arctan(sqrt(3.0)*m/(2.0*n+m)); -- chiral angle
--===========================================================================--
FUNCTION mod_ad(x:real;y:real) RETURN real is
variable result:real:= 0.0;
-- Modulus after division
-- the inputs must be real scalars
-- MOD(x,0) is x.
-- MOD(x,x) is 0.
-- MOD(x,y) for x~=y and y~=0, has the same sign as y.
-- MOD(x,y) is x - n.*y where n = floor(x./y) if y ~= 0.
begin
if x = y then
result:=0.0; -- x = y
elsif y = 0.0 then -- y = 0
result:=x;
else -- x ~= y
result:=x - y*floor(x/y);
end if;
RETURN result;
END FUNCTION mod_ad;
--===========================================================================--
begin
f == c1*u; -- linear spring
strain == u/L0;
---------------
p1 == abs(mod_ad(n-m,3.0));
if p1 <= 1.0 use
p == p1;
else
p == p1 - 3.0; -- p = p - 3*(p>1)
end use;
if n = m use
kind == 2.0; -- metallic
else
kind == abs(p); -- semimetallic / semiconducting classified by p
end use;
---------------
if kind = 0.0 use -- kind = 0 (semimetallic)
Eg0==t0*a**2/(16.0*r0**2.0)*cos(3.0*theta); -- zero strain band gap
Egs==abs(Eg0-(sqrt(3.0)/2.0)*a*b*cos(3.0*theta)*strain);
elsif kind = 1.0 use -- kind = 1 (semiconducting)
Eg0==t0*a/(sqrt(3.0)*r0); -- zero strain band gap
--Egs==abs(Eg0+sign(2.0*p+1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
if p < 1.0 use
Egs==abs(Eg0+(-1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
else
Egs==abs(Eg0+(+1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
end use;
else -- kind = 2 (metallic)
Eg0==0.0;
Egs==0.0;
end use;
---------------
Rcnt == h/(8.0*(tp*e_charge)**2)*(1.0+exp(Egs/(kB*T/e_charge))); -- resistance of a strained SWCNT, Ohm
---------------
v == i*(Rc + Rcnt);
end architecture analytic;
--===========================================================================--
--===========================================================================--
| mit | be830afe2275412a7613313adf82527f | 0.479089 | 3.215594 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/symmetric_pwm_deadtime.vhd | 2 | 4,046 | -------------------------------------------------------------------------------
-- Title : Symmetric PWM with Deadtime generation
-- Project : Loa
-------------------------------------------------------------------------------
-- File : symmetric_pwm_deadtime.vhd
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Created : 2011-12-16
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Deadtime for on and off can be specified separately.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
package symmetric_pwm_deadtime_pkg is
component symmetric_pwm_deadtime
generic (
WIDTH : natural;
T_DEAD : natural);
port (
pwm_p : out half_bridge_type;
center_p : out std_logic;
clk_en_p : in std_logic;
value_p : in std_logic_vector (WIDTH - 1 downto 0);
break_p : in std_logic := '0';
reset : in std_logic;
clk : in std_logic);
end component;
end package symmetric_pwm_deadtime_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_pkg.all;
entity symmetric_pwm_deadtime is
generic (
-- Number of bits used for the PWM (12bit => 0..4095)
WIDTH : natural := 12;
-- Defines the duration of the dead-time
-- inserted between the complementary outputs (in clock cycles of 'clk').
T_DEAD : natural := 0
);
port (
pwm_p : out half_bridge_type;
center_p : out std_logic; -- PWM is in the middle of the 'on'-periode
clk_en_p : in std_logic; -- clock enable
value_p : in std_logic_vector (WIDTH - 1 downto 0);
-- Disable PWM generation (sets pwm.low = '1' and pwm.high = '0')
break_p : in std_logic := '0';
reset : in std_logic; -- High active, Restarts the PWM period
clk : in std_logic
);
end symmetric_pwm_deadtime;
architecture structural of symmetric_pwm_deadtime is
signal pwm_raw : std_logic := '0'; -- PWM signal from the Symmetric PWM generator
signal pwm : std_logic;
signal pwm_n : std_logic;
signal lowside_center : std_logic;
signal highside_center : std_logic;
begin
pwm_generator : symmetric_pwm
generic map (
WIDTH => WIDTH)
port map (
pwm_p => pwm_raw,
underflow_p => lowside_center,
overflow_p => highside_center,
clk_en_p => clk_en_p,
value_p => value_p,
reset => reset,
clk => clk);
pwm <= '0' when break_p = '1' else pwm_raw;
pwm_n <= not pwm;
deadtime_on : deadtime
generic map (
T_DEAD => T_DEAD)
port map (
in_p => pwm_n,
out_p => pwm_p.low,
clk => clk);
deadtime_off : deadtime
generic map (
T_DEAD => T_DEAD)
port map (
in_p => pwm,
out_p => pwm_p.high,
clk => clk);
-- The deadtime generation delays the PWM output. To keep the center_p signal
-- synchron is has also to be delayed.
process
variable go : std_logic := '0'; -- Delay has started
variable delay : integer range 0 to (T_DEAD / 2) - 1 := 0;
begin
wait until rising_edge(clk);
if go = '0' then
center_p <= '0';
if lowside_center = '1' then
go := '1';
delay := 0;
end if;
else
if delay < (T_DEAD / 2) - 1 then
delay := delay + 1;
else
center_p <= '1';
go := '0';
end if;
end if;
end process;
end architecture structural;
| bsd-3-clause | 3067c5d9de216f498cee365a0a1a8beb | 0.495551 | 3.879195 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_sdram_0_s1_translator.vhd | 1 | 14,760 | -- niosii_system_sdram_0_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 22;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(21 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(1 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_sdram_0_s1_translator;
architecture rtl of niosii_system_sdram_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
sdram_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_sdram_0_s1_translator
| apache-2.0 | 0cf75b473ab9339e2abcbaecfbc661a1 | 0.427304 | 4.375926 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent.vhd | 1 | 17,920 | -- niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 80;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 35;
PKT_BYTEEN_L : integer := 32;
PKT_ADDR_H : integer := 60;
PKT_ADDR_L : integer := 36;
PKT_TRANS_COMPRESSED_READ : integer := 61;
PKT_TRANS_POSTED : integer := 62;
PKT_TRANS_WRITE : integer := 63;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 65;
PKT_SRC_ID_H : integer := 85;
PKT_SRC_ID_L : integer := 82;
PKT_DEST_ID_H : integer := 89;
PKT_DEST_ID_L : integer := 86;
PKT_BURSTWRAP_H : integer := 72;
PKT_BURSTWRAP_L : integer := 70;
PKT_BYTE_CNT_H : integer := 69;
PKT_BYTE_CNT_L : integer := 67;
PKT_PROTECTION_H : integer := 93;
PKT_PROTECTION_L : integer := 91;
PKT_RESPONSE_STATUS_H : integer := 99;
PKT_RESPONSE_STATUS_L : integer := 98;
PKT_BURST_SIZE_H : integer := 75;
PKT_BURST_SIZE_L : integer := 73;
ST_CHANNEL_W : integer := 13;
ST_DATA_W : integer := 100;
AVS_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_CMD : integer := 0;
PREVENT_FIFO_OVERFLOW : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
m0_address : out std_logic_vector(24 downto 0); -- m0.address
m0_burstcount : out std_logic_vector(2 downto 0); -- .burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
m0_debugaccess : out std_logic; -- .debugaccess
m0_lock : out std_logic; -- .lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
m0_readdatavalid : in std_logic := '0'; -- .readdatavalid
m0_read : out std_logic; -- .read
m0_waitrequest : in std_logic := '0'; -- .waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- .writedata
m0_write : out std_logic; -- .write
rp_endofpacket : out std_logic; -- rp.endofpacket
rp_ready : in std_logic := '0'; -- .ready
rp_valid : out std_logic; -- .valid
rp_data : out std_logic_vector(99 downto 0); -- .data
rp_startofpacket : out std_logic; -- .startofpacket
cp_ready : out std_logic; -- cp.ready
cp_valid : in std_logic := '0'; -- .valid
cp_data : in std_logic_vector(99 downto 0) := (others => '0'); -- .data
cp_startofpacket : in std_logic := '0'; -- .startofpacket
cp_endofpacket : in std_logic := '0'; -- .endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
rf_sink_ready : out std_logic; -- rf_sink.ready
rf_sink_valid : in std_logic := '0'; -- .valid
rf_sink_startofpacket : in std_logic := '0'; -- .startofpacket
rf_sink_endofpacket : in std_logic := '0'; -- .endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => '0'); -- .data
rf_source_ready : in std_logic := '0'; -- rf_source.ready
rf_source_valid : out std_logic; -- .valid
rf_source_startofpacket : out std_logic; -- .startofpacket
rf_source_endofpacket : out std_logic; -- .endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- .data
rdata_fifo_sink_ready : out std_logic; -- rdata_fifo_sink.ready
rdata_fifo_sink_valid : in std_logic := '0'; -- .valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => '0'); -- .data
rdata_fifo_src_ready : in std_logic := '0'; -- rdata_fifo_src.ready
rdata_fifo_src_valid : out std_logic; -- .valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- .data
m0_response : in std_logic_vector(1 downto 0) := (others => '0');
m0_writeresponserequest : out std_logic;
m0_writeresponsevalid : in std_logic := '0'
);
end entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent;
architecture rtl of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
component altera_merlin_slave_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_agent;
begin
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => PKT_DATA_H,
PKT_DATA_L => PKT_DATA_L,
PKT_BEGIN_BURST => PKT_BEGIN_BURST,
PKT_SYMBOL_W => PKT_SYMBOL_W,
PKT_BYTEEN_H => PKT_BYTEEN_H,
PKT_BYTEEN_L => PKT_BYTEEN_L,
PKT_ADDR_H => PKT_ADDR_H,
PKT_ADDR_L => PKT_ADDR_L,
PKT_TRANS_COMPRESSED_READ => PKT_TRANS_COMPRESSED_READ,
PKT_TRANS_POSTED => PKT_TRANS_POSTED,
PKT_TRANS_WRITE => PKT_TRANS_WRITE,
PKT_TRANS_READ => PKT_TRANS_READ,
PKT_TRANS_LOCK => PKT_TRANS_LOCK,
PKT_SRC_ID_H => PKT_SRC_ID_H,
PKT_SRC_ID_L => PKT_SRC_ID_L,
PKT_DEST_ID_H => PKT_DEST_ID_H,
PKT_DEST_ID_L => PKT_DEST_ID_L,
PKT_BURSTWRAP_H => PKT_BURSTWRAP_H,
PKT_BURSTWRAP_L => PKT_BURSTWRAP_L,
PKT_BYTE_CNT_H => PKT_BYTE_CNT_H,
PKT_BYTE_CNT_L => PKT_BYTE_CNT_L,
PKT_PROTECTION_H => PKT_PROTECTION_H,
PKT_PROTECTION_L => PKT_PROTECTION_L,
PKT_RESPONSE_STATUS_H => PKT_RESPONSE_STATUS_H,
PKT_RESPONSE_STATUS_L => PKT_RESPONSE_STATUS_L,
PKT_BURST_SIZE_H => PKT_BURST_SIZE_H,
PKT_BURST_SIZE_L => PKT_BURST_SIZE_L,
ST_CHANNEL_W => ST_CHANNEL_W,
ST_DATA_W => ST_DATA_W,
AVS_BURSTCOUNT_W => AVS_BURSTCOUNT_W,
SUPPRESS_0_BYTEEN_CMD => SUPPRESS_0_BYTEEN_CMD,
PREVENT_FIFO_OVERFLOW => PREVENT_FIFO_OVERFLOW,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
m0_address => m0_address, -- m0.address
m0_burstcount => m0_burstcount, -- .burstcount
m0_byteenable => m0_byteenable, -- .byteenable
m0_debugaccess => m0_debugaccess, -- .debugaccess
m0_lock => m0_lock, -- .lock
m0_readdata => m0_readdata, -- .readdata
m0_readdatavalid => m0_readdatavalid, -- .readdatavalid
m0_read => m0_read, -- .read
m0_waitrequest => m0_waitrequest, -- .waitrequest
m0_writedata => m0_writedata, -- .writedata
m0_write => m0_write, -- .write
rp_endofpacket => rp_endofpacket, -- rp.endofpacket
rp_ready => rp_ready, -- .ready
rp_valid => rp_valid, -- .valid
rp_data => rp_data, -- .data
rp_startofpacket => rp_startofpacket, -- .startofpacket
cp_ready => cp_ready, -- cp.ready
cp_valid => cp_valid, -- .valid
cp_data => cp_data, -- .data
cp_startofpacket => cp_startofpacket, -- .startofpacket
cp_endofpacket => cp_endofpacket, -- .endofpacket
cp_channel => cp_channel, -- .channel
rf_sink_ready => rf_sink_ready, -- rf_sink.ready
rf_sink_valid => rf_sink_valid, -- .valid
rf_sink_startofpacket => rf_sink_startofpacket, -- .startofpacket
rf_sink_endofpacket => rf_sink_endofpacket, -- .endofpacket
rf_sink_data => rf_sink_data, -- .data
rf_source_ready => rf_source_ready, -- rf_source.ready
rf_source_valid => rf_source_valid, -- .valid
rf_source_startofpacket => rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => rf_source_endofpacket, -- .endofpacket
rf_source_data => rf_source_data, -- .data
rdata_fifo_sink_ready => rdata_fifo_sink_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => rdata_fifo_sink_valid, -- .valid
rdata_fifo_sink_data => rdata_fifo_sink_data, -- .data
rdata_fifo_src_ready => rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
| apache-2.0 | a636367f4894f9a2980e8c04441f89fb | 0.420871 | 3.961972 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/tb/adc_ltc2351_tb.vhd | 2 | 3,900 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc" (not module)
-------------------------------------------------------------------------------
-- Author : strongly-typed
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-------------------------------------------------------------------------------
entity adc_ltc2351_tb is
end adc_ltc2351_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_tb is
use work.adc_ltc2351_pkg.all;
-- Component generics
constant BASE_ADDRESS : positive := 16#0100#;
-- component ports
signal sck_p : std_logic;
signal sdo_p : std_logic;
signal start_p : std_logic;
signal conv_p : std_logic;
signal done_p : std_logic;
signal clk : std_logic := '0';
signal adc_i : adc_ltc2351_spi_in_type;
signal adc_o : adc_ltc2351_spi_out_type;
begin
-- component instantiation
DUT : adc_ltc2351
port map (
-- connection between component's signals (left) and
-- testbench's signals (right)
adc_out => adc_o,
adc_in => adc_i,
start_p => start_p,
done_p => done_p,
clk => clk
);
-- connection between signals of DUT
-- and testbench signals
adc_i.sdo <= sdo_p;
sck_p <= adc_o.sck;
conv_p <= adc_o.conv;
-----------------------------------------------------------------------------
-- clock generation
clk <= not clk after 10 ns;
-----------------------------------------------------------------------------
-- stimuli generation
waveform : process
begin
start_p <= '0';
wait for 200 ns;
start_p <= '1';
wait for 100 ns;
start_p <= '0';
wait for 10 ms;
for i in 1 to 3 loop
wait until rising_edge(clk);
-- encoder.a <= '1';
wait until rising_edge(clk);
-- encoder.b <= '1';
wait until rising_edge(clk);
-- encoder.a <= '0';
wait until rising_edge(clk);
-- encoder.b <= '0';
wait until rising_edge(clk);
end loop; -- i
-- repeat process
wait for 50 ns;
end process waveform;
-----------------------------------------------------------------------------
-- ADC side stimulus
-- simulate the behaviour of the ADC here and generate test data.
process
begin
sdo_p <= 'Z';
-- wait for rising edge of conv
wait until sck_p = '0';
wait until conv_p = '1';
wait until sck_p = '1';
-- 6 words of 14 bit, separated by two Hi-Z's
for i in 1 to 6 loop -- two bits high-Z
wait until sck_p = '1';
wait until sck_p = '1';
-- start output of data, 14 bits
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '1';
wait until sck_p = '1';
sdo_p <= '0';
wait until sck_p = '1';
sdo_p <= 'Z';
end loop; -- i
-- repeat everything
end process;
-----------------------------------------------------------------------------
end tb;
configuration adc_ltc2351_tb_tb_cfg of adc_ltc2351_tb is
for tb
end for;
end adc_ltc2351_tb_tb_cfg;
| bsd-3-clause | 58b6936cb321446c8aa3f195d17a694b | 0.428718 | 3.880597 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 18,012 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue May 09 02:12:18 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
gclk : in STD_LOGIC;
hsync : out STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_board_cnt=1,da_ps7_cnt=2,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_rgb888_to_rgb565_0_0;
component system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_zed_vga_0_0 is
port (
clk : in STD_LOGIC;
active : in STD_LOGIC;
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component system_zed_vga_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_0;
component system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal rgb888_to_rgb565_0_rgb_565 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zed_vga_0_vga_b : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_g : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_FCLK_RESET0_N_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
clk_wiz_0_clk_out1 <= gclk;
hsync <= vga_sync_0_hsync;
vga_b(3 downto 0) <= zed_vga_0_vga_b(3 downto 0);
vga_g(3 downto 0) <= zed_vga_0_vga_g(3 downto 0);
vga_r(3 downto 0) <= zed_vga_0_vga_r(3 downto 0);
vsync <= vga_sync_0_vsync;
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => NLW_processing_system7_0_FCLK_RESET0_N_UNCONNECTED,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb888_to_rgb565_0: component system_rgb888_to_rgb565_0_0
port map (
rgb_565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
rgb_888(23 downto 0) => vga_color_test_0_rgb(23 downto 0)
);
vdd: component system_xlconstant_0_0
port map (
dout(0) => vdd_dout(0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk => clk_wiz_0_clk_out1,
hsync => vga_sync_0_hsync,
rst => vdd_dout(0),
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zed_vga_0: component system_zed_vga_0_0
port map (
active => vga_sync_0_active,
clk => clk_wiz_0_clk_out1,
rgb565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
vga_b(3 downto 0) => zed_vga_0_vga_b(3 downto 0),
vga_g(3 downto 0) => zed_vga_0_vga_g(3 downto 0),
vga_r(3 downto 0) => zed_vga_0_vga_r(3 downto 0)
);
end STRUCTURE;
| mit | 294c83cab47f4342a8e707ccf968deb5 | 0.66489 | 2.902353 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/tb/encoder_module_tb.vhd | 2 | 3,620 | -------------------------------------------------------------------------------
-- Title : Testbench for design "encoder_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.encoder_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module_tb is
end encoder_module_tb;
-------------------------------------------------------------------------------
architecture tb of encoder_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
-- component ports
signal encoder : encoder_type := ('0', '0');
signal index : std_logic := '0';
signal load : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : encoder_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
encoder_p => encoder,
index_p => index,
load_p => load,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 20 NS;
for i in 1 to 3 loop
wait until rising_edge(clk);
encoder.a <= '1';
wait until rising_edge(clk);
encoder.b <= '1';
wait until rising_edge(clk);
encoder.a <= '0';
wait until rising_edge(clk);
encoder.b <= '0';
wait until rising_edge(clk);
end loop; -- i
wait for 50 NS;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait for 30 NS;
wait until rising_edge(clk);
load <= '1';
wait until rising_edge(clk);
load <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
wait until rising_edge(clk);
-- generate two read cycles directly following each other
bus_i.re <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.re <= '0';
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
end process waveform;
end tb;
| bsd-3-clause | f1d4da7d03294991cbcf91915e088c5c | 0.459392 | 3.947655 | false | false | false | false |
loa-org/loa-hdl | modules/onewire/tb/onewire_write_tb.vhd | 1 | 2,955 | -------------------------------------------------------------------------------
-- Title : Onewire Master Testbench - Write Operation
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.onewire_pkg.all;
use work.onewire_cfg_pkg.all;
-------------------------------------------------------------------------------
entity onewire_write_tb is
end onewire_write_tb;
-------------------------------------------------------------------------------
architecture tb of onewire_write_tb is
component onewire
port (
onewire_in : in onewire_in_type;
onewire_out : out onewire_out_type;
onewire_bus_in : in onewire_bus_in_type;
onewire_bus_out : out onewire_bus_out_type;
clk : in std_logic);
end component;
-- component ports
signal onewire_in : onewire_in_type;
signal onewire_out : onewire_out_type;
signal onewire_bus_in : onewire_bus_in_type;
signal onewire_bus_out : onewire_bus_out_type;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : onewire
port map (
onewire_in => onewire_in,
onewire_out => onewire_out,
onewire_bus_in => onewire_bus_in,
onewire_bus_out => onewire_bus_out,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns; -- 50MHz Clock
-- waveform generation
WaveGen_Proc : process
begin
onewire_in.d <= (others => '0');
onewire_in.re <= '0';
onewire_in.we <= '0';
onewire_in.reset_bus <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
onewire_in.we <= '1';
onewire_in.d <= "0011" & "0101";
wait until Clk = '1';
onewire_in.we <= '0';
wait for 2.5 ms;
end process WaveGen_Proc;
WaveGen_onewire_device : process
variable device_response : std_logic := '0';
begin
onewire_bus_in.d <= 'H';
wait until onewire_bus_out.en_driver = '1';
end process WaveGen_onewire_device;
end tb;
-------------------------------------------------------------------------------
configuration onewire_write_tb_tb_cfg of onewire_write_tb is
for tb
end for;
end onewire_write_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | 1463225ebe590a4082aa31702188ce17 | 0.460914 | 4.326501 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4,331 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:45:50 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit | 135a132a4973f3308c41dc71fcfb30df | 0.554145 | 2.924375 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_transceiver_tb.vhd | 2 | 3,028 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_transceiver"
-- Project :
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_transceiver_tb is
end entity imotor_transceiver_tb;
-------------------------------------------------------------------------------
architecture tb of imotor_transceiver_tb is
-- component generics
constant DATA_WORDS_SEND : positive := 2;
constant DATA_WORDS_READ : positive := 3;
constant DATA_WIDTH : positive := 16;
constant CLOCK : positive := 50000000;
constant BAUD : positive := 1000000;
constant SEND_FREQUENCY : positive := 5000;
-- component ports
signal data_in_p : imotor_input_type(DATA_WORDS_SEND - 1 downto 0);
signal data_out_p : imotor_output_type(DATA_WORDS_READ - 1 downto 0);
signal tx_out_p : std_logic;
signal rx_in_p : std_logic;
signal rx_in_can : std_logic;
signal rx_in : std_logic := '1';
signal imotor_clock_s : imotor_timer_type;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.imotor_transceiver
generic map (
DATA_WORDS_SEND => DATA_WORDS_SEND,
DATA_WORDS_READ => DATA_WORDS_READ,
DATA_WIDTH => DATA_WIDTH)
port map (
data_in_p => data_in_p,
data_out_p => data_out_p,
tx_out_p => tx_out_p,
rx_in_p => rx_in_can,
timer_in_p => imotor_clock_s,
clk => clk);
imotor_timer : entity work.imotor_timer
generic map (
CLOCK => CLOCK,
BAUD => BAUD,
SEND_FREQUENCY => SEND_FREQUENCY)
port map (
clock_out_p => imotor_clock_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
rx_in_can <= '0' when rx_in = '0' or tx_out_p = '0' else '1';
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration imotor_transceiver_tb_tb_cfg of imotor_transceiver_tb is
for tb
end for;
end imotor_transceiver_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | 81a9f7939fcd0882fa1aee324dc5eff6 | 0.457398 | 4.472674 | false | false | false | false |
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